79#include "llvm/IR/IntrinsicsAArch64.h"
80#include "llvm/IR/IntrinsicsAMDGPU.h"
81#include "llvm/IR/IntrinsicsWebAssembly.h"
114using namespace PatternMatch;
115using namespace SwitchCG;
117#define DEBUG_TYPE "isel"
125 cl::desc(
"Insert the experimental `assertalign` node."),
130 cl::desc(
"Generate low-precision inline sequences "
131 "for some float libcalls"),
137 cl::desc(
"Set the case probability threshold for peeling the case from a "
138 "switch statement. A value greater than 100 will void this "
158 const SDValue *Parts,
unsigned NumParts,
161 std::optional<CallingConv::ID>
CC);
170 unsigned NumParts,
MVT PartVT,
EVT ValueVT,
const Value *V,
172 std::optional<CallingConv::ID>
CC = std::nullopt,
173 std::optional<ISD::NodeType> AssertOp = std::nullopt) {
177 PartVT, ValueVT,
CC))
184 assert(NumParts > 0 &&
"No parts to assemble!");
195 unsigned RoundBits = PartBits * RoundParts;
196 EVT RoundVT = RoundBits == ValueBits ?
202 if (RoundParts > 2) {
206 PartVT, HalfVT, V, InChain);
217 if (RoundParts < NumParts) {
219 unsigned OddParts = NumParts - RoundParts;
222 OddVT, V, InChain,
CC);
239 assert(ValueVT ==
EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
250 !PartVT.
isVector() &&
"Unexpected split");
262 if (PartEVT == ValueVT)
266 ValueVT.
bitsLT(PartEVT)) {
279 if (ValueVT.
bitsLT(PartEVT)) {
284 Val = DAG.
getNode(*AssertOp,
DL, PartEVT, Val,
299 llvm::Attribute::StrictFP)) {
301 DAG.
getVTList(ValueVT, MVT::Other), InChain, Val,
313 if (PartEVT == MVT::x86mmx && ValueVT.
isInteger() &&
314 ValueVT.
bitsLT(PartEVT)) {
323 const Twine &ErrMsg) {
324 const Instruction *
I = dyn_cast_or_null<Instruction>(V);
328 const char *AsmError =
", possible invalid constraint for vector type";
329 if (
const CallInst *CI = dyn_cast<CallInst>(
I))
330 if (CI->isInlineAsm())
342 const SDValue *Parts,
unsigned NumParts,
345 std::optional<CallingConv::ID> CallConv) {
347 assert(NumParts > 0 &&
"No parts to assemble!");
348 const bool IsABIRegCopy = CallConv.has_value();
357 unsigned NumIntermediates;
362 *DAG.
getContext(), *CallConv, ValueVT, IntermediateVT,
363 NumIntermediates, RegisterVT);
367 NumIntermediates, RegisterVT);
370 assert(NumRegs == NumParts &&
"Part count doesn't match vector breakdown!");
372 assert(RegisterVT == PartVT &&
"Part type doesn't match vector breakdown!");
375 "Part type sizes don't match!");
379 if (NumIntermediates == NumParts) {
382 for (
unsigned i = 0; i != NumParts; ++i)
384 V, InChain, CallConv);
385 }
else if (NumParts > 0) {
388 assert(NumParts % NumIntermediates == 0 &&
389 "Must expand into a divisible number of parts!");
390 unsigned Factor = NumParts / NumIntermediates;
391 for (
unsigned i = 0; i != NumIntermediates; ++i)
393 IntermediateVT, V, InChain, CallConv);
408 DL, BuiltVectorTy, Ops);
414 if (PartEVT == ValueVT)
430 "Cannot narrow, it would be a lossy transformation");
436 if (PartEVT == ValueVT)
461 }
else if (ValueVT.
bitsLT(PartEVT)) {
470 *DAG.
getContext(), V,
"non-trivial scalar-to-vector conversion");
501 std::optional<CallingConv::ID> CallConv);
508 unsigned NumParts,
MVT PartVT,
const Value *V,
509 std::optional<CallingConv::ID> CallConv = std::nullopt,
523 unsigned OrigNumParts = NumParts;
525 "Copying to an illegal type!");
531 EVT PartEVT = PartVT;
532 if (PartEVT == ValueVT) {
533 assert(NumParts == 1 &&
"No-op copy with multiple parts!");
542 assert(NumParts == 1 &&
"Do not know what to promote to!");
553 "Unknown mismatch!");
555 Val = DAG.
getNode(ExtendKind,
DL, ValueVT, Val);
556 if (PartVT == MVT::x86mmx)
561 assert(NumParts == 1 && PartEVT != ValueVT);
567 "Unknown mismatch!");
570 if (PartVT == MVT::x86mmx)
577 "Failed to tile the value with PartVT!");
580 if (PartEVT != ValueVT) {
582 "scalar-to-vector conversion failed");
591 if (NumParts & (NumParts - 1)) {
594 "Do not know what to expand to!");
596 unsigned RoundBits = RoundParts * PartBits;
597 unsigned OddParts = NumParts - RoundParts;
606 std::reverse(Parts + RoundParts, Parts + NumParts);
608 NumParts = RoundParts;
620 for (
unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
621 for (
unsigned i = 0; i < NumParts; i += StepSize) {
622 unsigned ThisBits = StepSize * PartBits / 2;
625 SDValue &Part1 = Parts[i+StepSize/2];
632 if (ThisBits == PartBits && ThisVT != PartVT) {
640 std::reverse(Parts, Parts + OrigNumParts);
657 if (ElementCount::isKnownLE(PartNumElts, ValueNumElts) ||
662 if (ValueEVT == MVT::bf16 && PartEVT == MVT::f16) {
664 "Cannot widen to illegal type");
667 }
else if (PartEVT != ValueEVT) {
682 Ops.
append((PartNumElts - ValueNumElts).getFixedValue(), EltUndef);
693 std::optional<CallingConv::ID> CallConv) {
697 const bool IsABIRegCopy = CallConv.has_value();
700 EVT PartEVT = PartVT;
701 if (PartEVT == ValueVT) {
720 TargetLowering::TypeWidenVector) {
747 "lossy conversion of vector to scalar type");
762 unsigned NumIntermediates;
766 *DAG.
getContext(), *CallConv, ValueVT, IntermediateVT, NumIntermediates,
771 NumIntermediates, RegisterVT);
774 assert(NumRegs == NumParts &&
"Part count doesn't match vector breakdown!");
776 assert(RegisterVT == PartVT &&
"Part type doesn't match vector breakdown!");
779 "Mixing scalable and fixed vectors when copying in parts");
781 std::optional<ElementCount> DestEltCnt;
791 if (ValueVT == BuiltVectorTy) {
815 for (
unsigned i = 0; i != NumIntermediates; ++i) {
830 if (NumParts == NumIntermediates) {
833 for (
unsigned i = 0; i != NumParts; ++i)
835 }
else if (NumParts > 0) {
838 assert(NumIntermediates != 0 &&
"division by zero");
839 assert(NumParts % NumIntermediates == 0 &&
840 "Must expand into a divisible number of parts!");
841 unsigned Factor = NumParts / NumIntermediates;
842 for (
unsigned i = 0; i != NumIntermediates; ++i)
849 EVT valuevt, std::optional<CallingConv::ID>
CC)
850 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs),
851 RegCount(1, regs.
size()), CallConv(
CC) {}
855 std::optional<CallingConv::ID>
CC) {
869 for (
unsigned i = 0; i != NumRegs; ++i)
871 RegVTs.push_back(RegisterVT);
900 for (
unsigned i = 0; i != NumRegs; ++i) {
906 *Glue =
P.getValue(2);
909 Chain =
P.getValue(1);
938 EVT FromVT(MVT::Other);
942 }
else if (NumSignBits > 1) {
950 assert(FromVT != MVT::Other);
956 RegisterVT, ValueVT, V, Chain,
CallConv);
986 NumParts, RegisterVT, V,
CallConv, ExtendKind);
992 for (
unsigned i = 0; i != NumRegs; ++i) {
1004 if (NumRegs == 1 || Glue)
1015 Chain = Chains[NumRegs-1];
1021 unsigned MatchingIdx,
const SDLoc &dl,
1023 std::vector<SDValue> &Ops)
const {
1028 Flag.setMatchingOp(MatchingIdx);
1037 Flag.setRegClass(RC->
getID());
1048 "No 1:1 mapping from clobbers to regs?");
1051 for (
unsigned I = 0, E =
ValueVTs.size();
I != E; ++
I) {
1056 "If we clobbered the stack pointer, MFI should know about it.");
1065 for (
unsigned i = 0; i != NumRegs; ++i) {
1067 unsigned TheReg =
Regs[Reg++];
1078 unsigned RegCount = std::get<0>(CountAndVT);
1079 MVT RegisterVT = std::get<1>(CountAndVT);
1103 UnusedArgNodeMap.clear();
1105 PendingExports.clear();
1106 PendingConstrainedFP.clear();
1107 PendingConstrainedFPStrict.clear();
1115 DanglingDebugInfoMap.clear();
1122 if (Pending.
empty())
1128 unsigned i = 0, e = Pending.
size();
1129 for (; i != e; ++i) {
1131 if (Pending[i].
getNode()->getOperand(0) == Root)
1139 if (Pending.
size() == 1)
1158 PendingConstrainedFP.size() +
1159 PendingConstrainedFPStrict.size());
1161 PendingConstrainedFP.end());
1162 PendingLoads.append(PendingConstrainedFPStrict.begin(),
1163 PendingConstrainedFPStrict.end());
1164 PendingConstrainedFP.clear();
1165 PendingConstrainedFPStrict.clear();
1172 PendingExports.append(PendingConstrainedFPStrict.begin(),
1173 PendingConstrainedFPStrict.end());
1174 PendingConstrainedFPStrict.clear();
1175 return updateRoot(PendingExports);
1182 assert(Variable &&
"Missing variable");
1189 <<
"dbg_declare: Dropping debug info (bad/undef/unused-arg address)\n");
1196 if (!
N.getNode() && isa<Argument>(
Address))
1204 auto *FINode = dyn_cast<FrameIndexSDNode>(
N.getNode());
1205 if (IsParameter && FINode) {
1208 true,
DL, SDNodeOrder);
1209 }
else if (isa<Argument>(
Address)) {
1213 FuncArgumentDbgValueKind::Declare,
N);
1217 true,
DL, SDNodeOrder);
1224 FuncArgumentDbgValueKind::Declare,
N)) {
1226 <<
" (could not emit func-arg dbg_value)\n");
1238 for (
auto It = FnVarLocs->locs_begin(&
I),
End = FnVarLocs->locs_end(&
I);
1240 auto *Var = FnVarLocs->getDILocalVariable(It->VariableID);
1242 if (It->Values.isKillLocation(It->Expr)) {
1248 It->Values.hasArgList())) {
1250 for (
Value *V : It->Values.location_ops())
1253 FnVarLocs->getDILocalVariable(It->VariableID),
1254 It->Expr, Vals.
size() > 1, It->DL, SDNodeOrder);
1270 for (
DbgRecord &DR :
I.getDbgRecordRange()) {
1272 assert(DLR->getLabel() &&
"Missing label");
1274 DAG.
getDbgLabel(DLR->getLabel(), DLR->getDebugLoc(), SDNodeOrder);
1279 if (SkipDbgVariableRecords)
1289 LLVM_DEBUG(
dbgs() <<
"SelectionDAG visiting dbg_declare: " << DVR
1298 if (Values.
empty()) {
1307 [](
Value *V) {
return !V || isa<UndefValue>(V); })) {
1315 SDNodeOrder, IsVariadic)) {
1326 if (
I.isTerminator()) {
1327 HandlePHINodesInSuccessorBlocks(
I.getParent());
1331 if (!isa<DbgInfoIntrinsic>(
I))
1337 bool NodeInserted =
false;
1338 std::unique_ptr<SelectionDAG::DAGNodeInsertedListener> InsertedListener;
1339 MDNode *PCSectionsMD =
I.getMetadata(LLVMContext::MD_pcsections);
1340 MDNode *MMRA =
I.getMetadata(LLVMContext::MD_mmra);
1341 if (PCSectionsMD || MMRA) {
1342 InsertedListener = std::make_unique<SelectionDAG::DAGNodeInsertedListener>(
1343 DAG, [&](
SDNode *) { NodeInserted =
true; });
1349 !isa<GCStatepointInst>(
I))
1353 if (PCSectionsMD || MMRA) {
1354 auto It = NodeMap.find(&
I);
1355 if (It != NodeMap.end()) {
1360 }
else if (NodeInserted) {
1363 errs() <<
"warning: loosing !pcsections and/or !mmra metadata ["
1364 <<
I.getModule()->getName() <<
"]\n";
1373void SelectionDAGBuilder::visitPHI(
const PHINode &) {
1383#define HANDLE_INST(NUM, OPCODE, CLASS) \
1384 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
1385#include "llvm/IR/Instruction.def"
1397 for (
const Value *V : Values) {
1422 DanglingDebugInfoMap[Values[0]].emplace_back(Var, Expr,
DL, Order);
1427 auto isMatchingDbgValue = [&](DanglingDebugInfo &DDI) {
1428 DIVariable *DanglingVariable = DDI.getVariable();
1430 if (DanglingVariable == Variable && Expr->
fragmentsOverlap(DanglingExpr)) {
1432 << printDDI(
nullptr, DDI) <<
"\n");
1438 for (
auto &DDIMI : DanglingDebugInfoMap) {
1439 DanglingDebugInfoVector &DDIV = DDIMI.second;
1443 for (
auto &DDI : DDIV)
1444 if (isMatchingDbgValue(DDI))
1447 erase_if(DDIV, isMatchingDbgValue);
1455 auto DanglingDbgInfoIt = DanglingDebugInfoMap.find(V);
1456 if (DanglingDbgInfoIt == DanglingDebugInfoMap.end())
1459 DanglingDebugInfoVector &DDIV = DanglingDbgInfoIt->second;
1460 for (
auto &DDI : DDIV) {
1463 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
1467 "Expected inlined-at fields to agree");
1476 if (!EmitFuncArgumentDbgValue(V, Variable, Expr,
DL,
1477 FuncArgumentDbgValueKind::Value, Val)) {
1479 << printDDI(V, DDI) <<
"\n");
1486 <<
"changing SDNodeOrder from " << DbgSDNodeOrder <<
" to "
1487 << ValSDNodeOrder <<
"\n");
1488 SDV = getDbgValue(Val, Variable, Expr,
DL,
1489 std::max(DbgSDNodeOrder, ValSDNodeOrder));
1494 <<
" in EmitFuncArgumentDbgValue\n");
1496 LLVM_DEBUG(
dbgs() <<
"Dropping debug info for " << printDDI(V, DDI)
1508 DanglingDebugInfo &DDI) {
1513 const Value *OrigV = V;
1517 unsigned SDOrder = DDI.getSDNodeOrder();
1521 bool StackValue =
true;
1530 while (isa<Instruction>(V)) {
1531 const Instruction &VAsInst = *cast<const Instruction>(V);
1546 if (!AdditionalValues.
empty())
1556 dbgs() <<
"Salvaged debug location info for:\n " << *Var <<
"\n"
1557 << *OrigV <<
"\nBy stripping back to:\n " << *V <<
"\n");
1565 assert(OrigV &&
"V shouldn't be null");
1570 << printDDI(OrigV, DDI) <<
"\n");
1587 unsigned Order,
bool IsVariadic) {
1592 if (visitEntryValueDbgValue(Values, Var, Expr, DbgLoc))
1597 for (
const Value *V : Values) {
1599 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V) ||
1600 isa<ConstantPointerNull>(V)) {
1606 if (
auto *CE = dyn_cast<ConstantExpr>(V))
1607 if (CE->getOpcode() == Instruction::IntToPtr) {
1614 if (
const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1625 if (!
N.getNode() && isa<Argument>(V))
1626 N = UnusedArgNodeMap[V];
1630 EmitFuncArgumentDbgValue(V, Var, Expr, DbgLoc,
1631 FuncArgumentDbgValueKind::Value,
N))
1633 if (
auto *FISDN = dyn_cast<FrameIndexSDNode>(
N.getNode())) {
1658 bool IsParamOfFunc =
1668 unsigned Reg = VMI->second;
1672 V->getType(), std::nullopt);
1678 unsigned BitsToDescribe = 0;
1680 BitsToDescribe = *VarSize;
1682 BitsToDescribe = Fragment->SizeInBits;
1685 if (
Offset >= BitsToDescribe)
1688 unsigned RegisterSize = RegAndSize.second;
1689 unsigned FragmentSize = (
Offset + RegisterSize > BitsToDescribe)
1690 ? BitsToDescribe -
Offset
1693 Expr,
Offset, FragmentSize);
1697 Var, *FragmentExpr, RegAndSize.first,
false, DbgLoc, Order);
1715 false, DbgLoc, Order, IsVariadic);
1722 for (
auto &Pair : DanglingDebugInfoMap)
1723 for (
auto &DDI : Pair.second)
1755 if (
N.getNode())
return N;
1797 if (
const Constant *
C = dyn_cast<Constant>(V)) {
1809 getValue(CPA->getAddrDiscriminator()),
1810 getValue(CPA->getDiscriminator()));
1813 if (isa<ConstantPointerNull>(
C)) {
1814 unsigned AS = V->getType()->getPointerAddressSpace();
1822 if (
const ConstantFP *CFP = dyn_cast<ConstantFP>(
C))
1825 if (isa<UndefValue>(
C) && !V->getType()->isAggregateType())
1829 visit(CE->getOpcode(), *CE);
1831 assert(N1.
getNode() &&
"visit didn't populate the NodeMap!");
1835 if (isa<ConstantStruct>(
C) || isa<ConstantArray>(
C)) {
1837 for (
const Use &U :
C->operands()) {
1843 for (
unsigned i = 0, e = Val->
getNumValues(); i != e; ++i)
1851 dyn_cast<ConstantDataSequential>(
C)) {
1853 for (
unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1857 for (
unsigned i = 0, e = Val->
getNumValues(); i != e; ++i)
1861 if (isa<ArrayType>(CDS->getType()))
1866 if (
C->getType()->isStructTy() ||
C->getType()->isArrayTy()) {
1867 assert((isa<ConstantAggregateZero>(
C) || isa<UndefValue>(
C)) &&
1868 "Unknown struct or array constant!");
1872 unsigned NumElts = ValueVTs.
size();
1876 for (
unsigned i = 0; i != NumElts; ++i) {
1877 EVT EltVT = ValueVTs[i];
1878 if (isa<UndefValue>(
C))
1892 if (
const auto *Equiv = dyn_cast<DSOLocalEquivalent>(
C))
1893 return getValue(Equiv->getGlobalValue());
1895 if (
const auto *
NC = dyn_cast<NoCFIValue>(
C))
1898 if (VT == MVT::aarch64svcount) {
1899 assert(
C->isNullValue() &&
"Can only zero this target type!");
1904 VectorType *VecTy = cast<VectorType>(V->getType());
1910 unsigned NumElements = cast<FixedVectorType>(VecTy)->getNumElements();
1911 for (
unsigned i = 0; i != NumElements; ++i)
1917 if (isa<ConstantAggregateZero>(
C)) {
1935 if (
const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1944 if (
const Instruction *Inst = dyn_cast<Instruction>(V)) {
1948 Inst->getType(), std::nullopt);
1956 if (
const auto *BB = dyn_cast<BasicBlock>(V))
1962void SelectionDAGBuilder::visitCatchPad(
const CatchPadInst &
I) {
1971 if (IsMSVCCXX || IsCoreCLR)
1998 Value *ParentPad =
I.getCatchSwitchParentPad();
2000 if (isa<ConstantTokenNone>(ParentPad))
2003 SuccessorColor = cast<Instruction>(ParentPad)->
getParent();
2004 assert(SuccessorColor &&
"No parent funclet for catchret!");
2006 assert(SuccessorColorMBB &&
"No MBB for SuccessorColor!");
2015void SelectionDAGBuilder::visitCleanupPad(
const CleanupPadInst &CPI) {
2059 if (isa<CleanupPadInst>(Pad)) {
2061 UnwindDests.emplace_back(FuncInfo.
MBBMap[EHPadBB], Prob);
2062 UnwindDests.back().first->setIsEHScopeEntry();
2064 }
else if (
const auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) {
2067 for (
const BasicBlock *CatchPadBB : CatchSwitch->handlers()) {
2068 UnwindDests.emplace_back(FuncInfo.
MBBMap[CatchPadBB], Prob);
2069 UnwindDests.back().first->setIsEHScopeEntry();
2100 assert(UnwindDests.size() <= 1 &&
2101 "There should be at most one unwind destination for wasm");
2108 if (isa<LandingPadInst>(Pad)) {
2110 UnwindDests.emplace_back(FuncInfo.
MBBMap[EHPadBB], Prob);
2112 }
else if (isa<CleanupPadInst>(Pad)) {
2115 UnwindDests.emplace_back(FuncInfo.
MBBMap[EHPadBB], Prob);
2116 UnwindDests.
back().first->setIsEHScopeEntry();
2117 UnwindDests.back().first->setIsEHFuncletEntry();
2119 }
else if (
const auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) {
2121 for (
const BasicBlock *CatchPadBB : CatchSwitch->handlers()) {
2122 UnwindDests.emplace_back(FuncInfo.
MBBMap[CatchPadBB], Prob);
2124 if (IsMSVCCXX || IsCoreCLR)
2125 UnwindDests.back().first->setIsEHFuncletEntry();
2127 UnwindDests.back().first->setIsEHScopeEntry();
2129 NewEHPadBB = CatchSwitch->getUnwindDest();
2135 if (BPI && NewEHPadBB)
2137 EHPadBB = NewEHPadBB;
2144 auto UnwindDest =
I.getUnwindDest();
2151 for (
auto &UnwindDest : UnwindDests) {
2152 UnwindDest.first->setIsEHPad();
2153 addSuccessorWithProb(
FuncInfo.
MBB, UnwindDest.first, UnwindDest.second);
2163void SelectionDAGBuilder::visitCatchSwitch(
const CatchSwitchInst &CSI) {
2167void SelectionDAGBuilder::visitRet(
const ReturnInst &
I) {
2181 if (
I.getParent()->getTerminatingDeoptimizeCall()) {
2188 const Function *
F =
I.getParent()->getParent();
2207 unsigned NumValues = ValueVTs.
size();
2210 Align BaseAlign =
DL.getPrefTypeAlign(
I.getOperand(0)->getType());
2211 for (
unsigned i = 0; i != NumValues; ++i) {
2218 if (MemVTs[i] != ValueVTs[i])
2228 MVT::Other, Chains);
2229 }
else if (
I.getNumOperands() != 0) {
2232 unsigned NumValues = ValueVTs.
size();
2236 const Function *
F =
I.getParent()->getParent();
2239 I.getOperand(0)->getType(),
F->getCallingConv(),
2243 if (
F->getAttributes().hasRetAttr(Attribute::SExt))
2245 else if (
F->getAttributes().hasRetAttr(Attribute::ZExt))
2249 bool RetInReg =
F->getAttributes().hasRetAttr(Attribute::InReg);
2251 for (
unsigned j = 0;
j != NumValues; ++
j) {
2252 EVT VT = ValueVTs[
j];
2264 &Parts[0], NumParts, PartVT, &
I,
CC, ExtendKind);
2271 if (
I.getOperand(0)->getType()->isPointerTy()) {
2273 Flags.setPointerAddrSpace(
2274 cast<PointerType>(
I.getOperand(0)->getType())->getAddressSpace());
2277 if (NeedsRegBlock) {
2278 Flags.setInConsecutiveRegs();
2279 if (j == NumValues - 1)
2280 Flags.setInConsecutiveRegsLast();
2289 for (
unsigned i = 0; i < NumParts; ++i) {
2291 Parts[i].getValueType().getSimpleVT(),
2302 const Function *
F =
I.getParent()->getParent();
2304 F->getAttributes().hasAttrSomewhere(Attribute::SwiftError)) {
2307 Flags.setSwiftError();
2326 "LowerReturn didn't return a valid chain!");
2337 if (V->getType()->isEmptyTy())
2342 assert((!V->use_empty() || isa<CallBrInst>(V)) &&
2343 "Unused value assigned virtual registers!");
2353 if (!isa<Instruction>(V) && !isa<Argument>(V))
return;
2366 if (
const Instruction *VI = dyn_cast<Instruction>(V)) {
2368 if (VI->getParent() == FromBB)
2377 if (isa<Argument>(V)) {
2394 const BasicBlock *SrcBB = Src->getBasicBlock();
2395 const BasicBlock *DstBB = Dst->getBasicBlock();
2399 auto SuccSize = std::max<uint32_t>(
succ_size(SrcBB), 1);
2409 Src->addSuccessorWithoutProb(Dst);
2412 Prob = getEdgeProbability(Src, Dst);
2413 Src->addSuccessor(Dst, Prob);
2419 return I->getParent() == BB;
2439 if (
const CmpInst *BOp = dyn_cast<CmpInst>(
Cond)) {
2443 if (CurBB == SwitchBB ||
2449 InvertCond ? IC->getInversePredicate() : IC->getPredicate();
2454 InvertCond ? FC->getInversePredicate() : FC->getPredicate();
2460 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1),
nullptr,
2462 SL->SwitchCases.push_back(CB);
2471 SL->SwitchCases.push_back(CB);
2479 unsigned Depth = 0) {
2484 auto *
I = dyn_cast<Instruction>(V);
2488 if (Necessary !=
nullptr) {
2491 if (Necessary->contains(
I))
2499 for (
unsigned OpIdx = 0, E =
I->getNumOperands(); OpIdx < E; ++OpIdx)
2510 if (
I.getNumSuccessors() != 2)
2513 if (!
I.isConditional())
2525 if (BPI !=
nullptr) {
2531 std::optional<bool> Likely;
2534 else if (BPI->
isEdgeHot(
I.getParent(), IfFalse))
2538 if (Opc == (*Likely ? Instruction::And : Instruction::Or))
2550 if (CostThresh <= 0)
2564 if (
const auto *RhsI = dyn_cast<Instruction>(Rhs))
2575 Value *BrCond =
I.getCondition();
2576 auto ShouldCountInsn = [&RhsDeps, &BrCond](
const Instruction *Ins) {
2577 for (
const auto *U : Ins->users()) {
2579 if (
auto *UIns = dyn_cast<Instruction>(U))
2580 if (UIns != BrCond && !RhsDeps.
contains(UIns))
2593 for (
unsigned PruneIters = 0; PruneIters < MaxPruneIters; ++PruneIters) {
2595 for (
const auto &InsPair : RhsDeps) {
2596 if (!ShouldCountInsn(InsPair.first)) {
2597 ToDrop = InsPair.first;
2601 if (ToDrop ==
nullptr)
2603 RhsDeps.erase(ToDrop);
2606 for (
const auto &InsPair : RhsDeps) {
2614 if (CostOfIncluding > CostThresh)
2640 const Value *BOpOp0, *BOpOp1;
2654 if (BOpc == Instruction::And)
2655 BOpc = Instruction::Or;
2656 else if (BOpc == Instruction::Or)
2657 BOpc = Instruction::And;
2663 bool BOpIsInOrAndTree = BOpc && BOpc == Opc && BOp->
hasOneUse();
2668 TProb, FProb, InvertCond);
2678 if (Opc == Instruction::Or) {
2699 auto NewTrueProb = TProb / 2;
2700 auto NewFalseProb = TProb / 2 + FProb;
2703 NewFalseProb, InvertCond);
2710 Probs[1], InvertCond);
2712 assert(Opc == Instruction::And &&
"Unknown merge op!");
2732 auto NewTrueProb = TProb + FProb / 2;
2733 auto NewFalseProb = FProb / 2;
2736 NewFalseProb, InvertCond);
2743 Probs[1], InvertCond);
2752 if (Cases.size() != 2)
return true;
2756 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
2757 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
2758 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
2759 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
2765 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
2766 Cases[0].
CC == Cases[1].
CC &&
2767 isa<Constant>(Cases[0].CmpRHS) &&
2768 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
2769 if (Cases[0].
CC ==
ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
2771 if (Cases[0].
CC ==
ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
2778void SelectionDAGBuilder::visitBr(
const BranchInst &
I) {
2784 if (
I.isUnconditional()) {
2790 if (Succ0MBB != NextBlock(BrMBB) ||
2803 const Value *CondVal =
I.getCondition();
2823 const Instruction *BOp = dyn_cast<Instruction>(CondVal);
2825 BOp->
hasOneUse() && !
I.hasMetadata(LLVMContext::MD_unpredictable)) {
2827 const Value *BOp0, *BOp1;
2830 Opcode = Instruction::And;
2832 Opcode = Instruction::Or;
2840 Opcode, BOp0, BOp1))) {
2842 getEdgeProbability(BrMBB, Succ0MBB),
2843 getEdgeProbability(BrMBB, Succ1MBB),
2848 assert(
SL->SwitchCases[0].ThisBB == BrMBB &&
"Unexpected lowering!");
2852 for (
unsigned i = 1, e =
SL->SwitchCases.size(); i != e; ++i) {
2859 SL->SwitchCases.erase(
SL->SwitchCases.begin());
2865 for (
unsigned i = 1, e =
SL->SwitchCases.size(); i != e; ++i)
2868 SL->SwitchCases.clear();
2874 nullptr, Succ0MBB, Succ1MBB, BrMBB,
getCurSDLoc());
2893 if (CB.
TrueBB != NextBlock(SwitchBB)) {
2935 if (cast<ConstantInt>(CB.
CmpLHS)->isMinValue(
true)) {
2956 if (CB.
TrueBB == NextBlock(SwitchBB)) {
2980 assert(JT.SL &&
"Should set SDLoc for SelectionDAG!");
2981 assert(JT.Reg != -1U &&
"Should lower JT Header first!");
2995 assert(JT.SL &&
"Should set SDLoc for SelectionDAG!");
2996 const SDLoc &dl = *JT.SL;
3012 unsigned JumpTableReg =
3015 JumpTableReg, SwitchOp);
3016 JT.Reg = JumpTableReg;
3028 MVT::Other, CopyTo, CMP,
3032 if (JT.MBB != NextBlock(SwitchBB))
3039 if (JT.MBB != NextBlock(SwitchBB))
3067 if (PtrTy != PtrMemTy)
3115 Entry.Node = GuardVal;
3117 if (GuardCheckFn->hasParamAttribute(0, Attribute::AttrKind::InReg))
3118 Entry.IsInReg =
true;
3119 Args.push_back(Entry);
3125 getValue(GuardCheckFn), std::move(Args));
3127 std::pair<SDValue, SDValue> Result = TLI.
LowerCallTo(CLI);
3141 Guard =
DAG.
getLoad(PtrMemTy, dl, Chain, GuardPtr,
3178 TLI.
makeLibCall(
DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
3209 bool UsePtrType =
false;
3213 for (
unsigned i = 0, e =
B.Cases.size(); i != e; ++i)
3233 if (!
B.FallthroughUnreachable)
3234 addSuccessorWithProb(SwitchBB,
B.Default,
B.DefaultProb);
3235 addSuccessorWithProb(SwitchBB,
MBB,
B.Prob);
3239 if (!
B.FallthroughUnreachable) {
3252 if (
MBB != NextBlock(SwitchBB))
3271 if (PopCount == 1) {
3278 }
else if (PopCount == BB.
Range) {
3297 addSuccessorWithProb(SwitchBB,
B.TargetBB,
B.ExtraProb);
3299 addSuccessorWithProb(SwitchBB, NextMBB, BranchProbToNext);
3310 if (NextMBB != NextBlock(SwitchBB))
3317void SelectionDAGBuilder::visitInvoke(
const InvokeInst &
I) {
3328 assert(!
I.hasOperandBundlesOtherThan(
3329 {LLVMContext::OB_deopt, LLVMContext::OB_gc_transition,
3330 LLVMContext::OB_gc_live, LLVMContext::OB_funclet,
3331 LLVMContext::OB_cfguardtarget, LLVMContext::OB_ptrauth,
3332 LLVMContext::OB_clang_arc_attachedcall}) &&
3333 "Cannot lower invokes with arbitrary operand bundles yet!");
3335 const Value *Callee(
I.getCalledOperand());
3336 const Function *Fn = dyn_cast<Function>(Callee);
3337 if (isa<InlineAsm>(Callee))
3338 visitInlineAsm(
I, EHPadBB);
3343 case Intrinsic::donothing:
3345 case Intrinsic::seh_try_begin:
3346 case Intrinsic::seh_scope_begin:
3347 case Intrinsic::seh_try_end:
3348 case Intrinsic::seh_scope_end:
3354 case Intrinsic::experimental_patchpoint_void:
3355 case Intrinsic::experimental_patchpoint:
3356 visitPatchpoint(
I, EHPadBB);
3358 case Intrinsic::experimental_gc_statepoint:
3361 case Intrinsic::wasm_rethrow: {
3376 }
else if (
I.hasDeoptState()) {
3392 if (!isa<GCStatepointInst>(
I)) {
3404 addSuccessorWithProb(InvokeMBB, Return);
3405 for (
auto &UnwindDest : UnwindDests) {
3406 UnwindDest.first->setIsEHPad();
3407 addSuccessorWithProb(InvokeMBB, UnwindDest.first, UnwindDest.second);
3416void SelectionDAGBuilder::visitCallBr(
const CallBrInst &
I) {
3421 assert(!
I.hasOperandBundlesOtherThan(
3422 {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) &&
3423 "Cannot lower callbrs with arbitrary operand bundles yet!");
3425 assert(
I.isInlineAsm() &&
"Only know how to handle inlineasm callbr");
3431 Dests.
insert(
I.getDefaultDest());
3436 for (
unsigned i = 0, e =
I.getNumIndirectDests(); i < e; ++i) {
3439 Target->setIsInlineAsmBrIndirectTarget();
3440 Target->setMachineBlockAddressTaken();
3441 Target->setLabelMustBeEmitted();
3443 if (Dests.
insert(Dest).second)
3454void SelectionDAGBuilder::visitResume(
const ResumeInst &RI) {
3455 llvm_unreachable(
"SelectionDAGBuilder shouldn't visit resume instructions!");
3458void SelectionDAGBuilder::visitLandingPad(
const LandingPadInst &LP) {
3460 "Call to landingpad not in landing pad!");
3480 assert(ValueVTs.
size() == 2 &&
"Only two-valued landingpads are supported");
3510 if (JTB.first.HeaderBB ==
First)
3511 JTB.first.HeaderBB =
Last;
3524 for (
unsigned i = 0, e =
I.getNumSuccessors(); i != e; ++i) {
3526 bool Inserted =
Done.insert(BB).second;
3531 addSuccessorWithProb(IndirectBrMBB, Succ);
3545 if (
const CallInst *Call = dyn_cast_or_null<CallInst>(
I.getPrevNode());
3546 Call &&
Call->doesNotReturn()) {
3550 if (
Call->isNonContinuableTrap())
3557void SelectionDAGBuilder::visitUnary(
const User &
I,
unsigned Opcode) {
3559 if (
auto *FPOp = dyn_cast<FPMathOperator>(&
I))
3560 Flags.copyFMF(*FPOp);
3568void SelectionDAGBuilder::visitBinary(
const User &
I,
unsigned Opcode) {
3570 if (
auto *OFBinOp = dyn_cast<OverflowingBinaryOperator>(&
I)) {
3571 Flags.setNoSignedWrap(OFBinOp->hasNoSignedWrap());
3572 Flags.setNoUnsignedWrap(OFBinOp->hasNoUnsignedWrap());
3574 if (
auto *ExactOp = dyn_cast<PossiblyExactOperator>(&
I))
3575 Flags.setExact(ExactOp->isExact());
3576 if (
auto *DisjointOp = dyn_cast<PossiblyDisjointInst>(&
I))
3577 Flags.setDisjoint(DisjointOp->isDisjoint());
3578 if (
auto *FPOp = dyn_cast<FPMathOperator>(&
I))
3579 Flags.copyFMF(*FPOp);
3588void SelectionDAGBuilder::visitShift(
const User &
I,
unsigned Opcode) {
3597 if (!
I.getType()->isVectorTy() && Op2.
getValueType() != ShiftTy) {
3599 "Unexpected shift type");
3610 dyn_cast<const OverflowingBinaryOperator>(&
I)) {
3611 nuw = OFBinOp->hasNoUnsignedWrap();
3612 nsw = OFBinOp->hasNoSignedWrap();
3615 dyn_cast<const PossiblyExactOperator>(&
I))
3616 exact = ExactOp->isExact();
3619 Flags.setExact(exact);
3620 Flags.setNoSignedWrap(nsw);
3621 Flags.setNoUnsignedWrap(nuw);
3627void SelectionDAGBuilder::visitSDiv(
const User &
I) {
3632 Flags.setExact(isa<PossiblyExactOperator>(&
I) &&
3633 cast<PossiblyExactOperator>(&
I)->isExact());
3638void SelectionDAGBuilder::visitICmp(
const ICmpInst &
I) {
3661void SelectionDAGBuilder::visitFCmp(
const FCmpInst &
I) {
3667 auto *FPMO = cast<FPMathOperator>(&
I);
3672 Flags.copyFMF(*FPMO);
3684 return isa<SelectInst>(V);
3688void SelectionDAGBuilder::visitSelect(
const User &
I) {
3692 unsigned NumValues = ValueVTs.
size();
3693 if (NumValues == 0)
return;
3703 bool IsUnaryAbs =
false;
3704 bool Negate =
false;
3707 if (
auto *FPOp = dyn_cast<FPMathOperator>(&
I))
3708 Flags.copyFMF(*FPOp);
3710 Flags.setUnpredictable(
3711 cast<SelectInst>(
I).getMetadata(LLVMContext::MD_unpredictable));
3715 EVT VT = ValueVTs[0];
3727 bool UseScalarMinMax = VT.
isVector() &&
3736 switch (SPR.Flavor) {
3742 switch (SPR.NaNBehavior) {
3755 switch (SPR.NaNBehavior) {
3799 for (
unsigned i = 0; i != NumValues; ++i) {
3808 for (
unsigned i = 0; i != NumValues; ++i) {
3822void SelectionDAGBuilder::visitTrunc(
const User &
I) {
3830void SelectionDAGBuilder::visitZExt(
const User &
I) {
3838 if (
auto *PNI = dyn_cast<PossiblyNonNegInst>(&
I))
3839 Flags.setNonNeg(PNI->hasNonNeg());
3844 if (
Flags.hasNonNeg() &&
3853void SelectionDAGBuilder::visitSExt(
const User &
I) {
3862void SelectionDAGBuilder::visitFPTrunc(
const User &
I) {
3873void SelectionDAGBuilder::visitFPExt(
const User &
I) {
3881void SelectionDAGBuilder::visitFPToUI(
const User &
I) {
3889void SelectionDAGBuilder::visitFPToSI(
const User &
I) {
3897void SelectionDAGBuilder::visitUIToFP(
const User &
I) {
3903 if (
auto *PNI = dyn_cast<PossiblyNonNegInst>(&
I))
3904 Flags.setNonNeg(PNI->hasNonNeg());
3909void SelectionDAGBuilder::visitSIToFP(
const User &
I) {
3917void SelectionDAGBuilder::visitPtrToInt(
const User &
I) {
3931void SelectionDAGBuilder::visitIntToPtr(
const User &
I) {
3943void SelectionDAGBuilder::visitBitCast(
const User &
I) {
3951 if (DestVT !=
N.getValueType())
3958 else if(
ConstantInt *
C = dyn_cast<ConstantInt>(
I.getOperand(0)))
3965void SelectionDAGBuilder::visitAddrSpaceCast(
const User &
I) {
3967 const Value *SV =
I.getOperand(0);
3972 unsigned DestAS =
I.getType()->getPointerAddressSpace();
3980void SelectionDAGBuilder::visitInsertElement(
const User &
I) {
3988 InVec, InVal, InIdx));
3991void SelectionDAGBuilder::visitExtractElement(
const User &
I) {
4001void SelectionDAGBuilder::visitShuffleVector(
const User &
I) {
4005 if (
auto *SVI = dyn_cast<ShuffleVectorInst>(&
I))
4006 Mask = SVI->getShuffleMask();
4008 Mask = cast<ConstantExpr>(
I).getShuffleMask();
4014 if (
all_of(Mask, [](
int Elem) {
return Elem == 0; }) &&
4030 unsigned MaskNumElts =
Mask.size();
4032 if (SrcNumElts == MaskNumElts) {
4038 if (SrcNumElts < MaskNumElts) {
4042 if (MaskNumElts % SrcNumElts == 0) {
4046 unsigned NumConcat = MaskNumElts / SrcNumElts;
4047 bool IsConcat =
true;
4049 for (
unsigned i = 0; i != MaskNumElts; ++i) {
4055 if ((
Idx % SrcNumElts != (i % SrcNumElts)) ||
4056 (ConcatSrcs[i / SrcNumElts] >= 0 &&
4057 ConcatSrcs[i / SrcNumElts] != (
int)(
Idx / SrcNumElts))) {
4062 ConcatSrcs[i / SrcNumElts] =
Idx / SrcNumElts;
4069 for (
auto Src : ConcatSrcs) {
4082 unsigned PaddedMaskNumElts =
alignTo(MaskNumElts, SrcNumElts);
4083 unsigned NumConcat = PaddedMaskNumElts / SrcNumElts;
4100 for (
unsigned i = 0; i != MaskNumElts; ++i) {
4102 if (
Idx >= (
int)SrcNumElts)
4103 Idx -= SrcNumElts - PaddedMaskNumElts;
4111 if (MaskNumElts != PaddedMaskNumElts)
4119 if (SrcNumElts > MaskNumElts) {
4122 int StartIdx[2] = { -1, -1 };
4123 bool CanExtract =
true;
4124 for (
int Idx : Mask) {
4129 if (
Idx >= (
int)SrcNumElts) {
4138 if (NewStartIdx + MaskNumElts > SrcNumElts ||
4139 (StartIdx[Input] >= 0 && StartIdx[Input] != NewStartIdx))
4143 StartIdx[Input] = NewStartIdx;
4146 if (StartIdx[0] < 0 && StartIdx[1] < 0) {
4152 for (
unsigned Input = 0; Input < 2; ++Input) {
4153 SDValue &Src = Input == 0 ? Src1 : Src2;
4154 if (StartIdx[Input] < 0)
4164 for (
int &
Idx : MappedOps) {
4165 if (
Idx >= (
int)SrcNumElts)
4166 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
4181 for (
int Idx : Mask) {
4187 SDValue &Src =
Idx < (int)SrcNumElts ? Src1 : Src2;
4188 if (
Idx >= (
int)SrcNumElts)
Idx -= SrcNumElts;
4202 const Value *Op0 =
I.getOperand(0);
4203 const Value *Op1 =
I.getOperand(1);
4204 Type *AggTy =
I.getType();
4206 bool IntoUndef = isa<UndefValue>(Op0);
4207 bool FromUndef = isa<UndefValue>(Op1);
4217 unsigned NumAggValues = AggValueVTs.
size();
4218 unsigned NumValValues = ValValueVTs.
size();
4222 if (!NumAggValues) {
4230 for (; i != LinearIndex; ++i)
4231 Values[i] = IntoUndef ?
DAG.
getUNDEF(AggValueVTs[i]) :
4236 for (; i != LinearIndex + NumValValues; ++i)
4237 Values[i] = FromUndef ?
DAG.
getUNDEF(AggValueVTs[i]) :
4241 for (; i != NumAggValues; ++i)
4242 Values[i] = IntoUndef ?
DAG.
getUNDEF(AggValueVTs[i]) :
4251 const Value *Op0 =
I.getOperand(0);
4253 Type *ValTy =
I.getType();
4254 bool OutOfUndef = isa<UndefValue>(Op0);
4262 unsigned NumValValues = ValValueVTs.
size();
4265 if (!NumValValues) {
4274 for (
unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
4275 Values[i - LinearIndex] =
4284void SelectionDAGBuilder::visitGetElementPtr(
const User &
I) {
4285 Value *Op0 =
I.getOperand(0);
4295 bool IsVectorGEP =
I.getType()->isVectorTy();
4297 IsVectorGEP ? cast<VectorType>(
I.getType())->getElementCount()
4300 if (IsVectorGEP && !
N.getValueType().isVector()) {
4308 const Value *
Idx = GTI.getOperand();
4309 if (
StructType *StTy = GTI.getStructTypeOrNull()) {
4310 unsigned Field = cast<Constant>(
Idx)->getUniqueInteger().getZExtValue();
4319 if (int64_t(
Offset) >= 0 && cast<GEPOperator>(
I).isInBounds())
4320 Flags.setNoUnsignedWrap(
true);
4336 bool ElementScalable = ElementSize.
isScalable();
4340 const auto *
C = dyn_cast<Constant>(
Idx);
4341 if (
C && isa<VectorType>(
C->getType()))
4342 C =
C->getSplatValue();
4344 const auto *CI = dyn_cast_or_null<ConstantInt>(
C);
4345 if (CI && CI->isZero())
4347 if (CI && !ElementScalable) {
4361 Flags.setNoUnsignedWrap(
true);
4374 VectorElementCount);
4382 if (ElementScalable) {
4383 EVT VScaleTy =
N.getValueType().getScalarType();
4393 if (ElementMul != 1) {
4394 if (ElementMul.isPowerOf2()) {
4395 unsigned Amt = ElementMul.logBase2();
4397 N.getValueType(), IdxN,
4403 N.getValueType(), IdxN, Scale);
4409 N.getValueType(),
N, IdxN);
4420 if (PtrMemTy != PtrTy && !cast<GEPOperator>(
I).isInBounds())
4426void SelectionDAGBuilder::visitAlloca(
const AllocaInst &
I) {
4433 Type *Ty =
I.getAllocatedType();
4437 MaybeAlign Alignment = std::max(
DL.getPrefTypeAlign(Ty),
I.getAlign());
4461 if (*Alignment <= StackAlign)
4462 Alignment = std::nullopt;
4469 Flags.setNoUnsignedWrap(
true);
4479 DAG.
getConstant(Alignment ? Alignment->value() : 0, dl, IntPtr)};
4495 if (!
I.hasMetadata(LLVMContext::MD_noundef))
4497 return I.getMetadata(LLVMContext::MD_range);
4501 if (
const auto *CB = dyn_cast<CallBase>(&
I)) {
4503 if (CB->hasRetAttr(Attribute::NoUndef))
4504 return CB->getRange();
4508 return std::nullopt;
4511void SelectionDAGBuilder::visitLoad(
const LoadInst &
I) {
4513 return visitAtomicLoad(
I);
4516 const Value *SV =
I.getOperand(0);
4520 if (
const Argument *Arg = dyn_cast<Argument>(SV)) {
4521 if (Arg->hasSwiftErrorAttr())
4522 return visitLoadFromSwiftError(
I);
4525 if (
const AllocaInst *Alloca = dyn_cast<AllocaInst>(SV)) {
4526 if (Alloca->isSwiftError())
4527 return visitLoadFromSwiftError(
I);
4533 Type *Ty =
I.getType();
4537 unsigned NumValues = ValueVTs.
size();
4541 Align Alignment =
I.getAlign();
4544 bool isVolatile =
I.isVolatile();
4549 bool ConstantMemory =
false;
4562 ConstantMemory =
true;
4577 unsigned ChainI = 0;
4578 for (
unsigned i = 0; i != NumValues; ++i, ++ChainI) {
4601 MMOFlags, AAInfo, Ranges);
4602 Chains[ChainI] =
L.getValue(1);
4604 if (MemVTs[i] != ValueVTs[i])
4610 if (!ConstantMemory) {
4623void SelectionDAGBuilder::visitStoreToSwiftError(
const StoreInst &
I) {
4625 "call visitStoreToSwiftError when backend supports swifterror");
4629 const Value *SrcV =
I.getOperand(0);
4631 SrcV->
getType(), ValueVTs, &Offsets, 0);
4632 assert(ValueVTs.
size() == 1 && Offsets[0] == 0 &&
4633 "expect a single EVT for swifterror");
4642 SDValue(Src.getNode(), Src.getResNo()));
4646void SelectionDAGBuilder::visitLoadFromSwiftError(
const LoadInst &
I) {
4648 "call visitLoadFromSwiftError when backend supports swifterror");
4651 !
I.hasMetadata(LLVMContext::MD_nontemporal) &&
4652 !
I.hasMetadata(LLVMContext::MD_invariant_load) &&
4653 "Support volatile, non temporal, invariant for load_from_swift_error");
4655 const Value *SV =
I.getOperand(0);
4656 Type *Ty =
I.getType();
4661 I.getAAMetadata()))) &&
4662 "load_from_swift_error should not be constant memory");
4667 ValueVTs, &Offsets, 0);
4668 assert(ValueVTs.
size() == 1 && Offsets[0] == 0 &&
4669 "expect a single EVT for swifterror");
4679void SelectionDAGBuilder::visitStore(
const StoreInst &
I) {
4681 return visitAtomicStore(
I);
4683 const Value *SrcV =
I.getOperand(0);
4684 const Value *PtrV =
I.getOperand(1);
4690 if (
const Argument *Arg = dyn_cast<Argument>(PtrV)) {
4691 if (Arg->hasSwiftErrorAttr())
4692 return visitStoreToSwiftError(
I);
4695 if (
const AllocaInst *Alloca = dyn_cast<AllocaInst>(PtrV)) {
4696 if (Alloca->isSwiftError())
4697 return visitStoreToSwiftError(
I);
4704 SrcV->
getType(), ValueVTs, &MemVTs, &Offsets);
4705 unsigned NumValues = ValueVTs.
size();
4718 Align Alignment =
I.getAlign();
4723 unsigned ChainI = 0;
4724 for (
unsigned i = 0; i != NumValues; ++i, ++ChainI) {
4741 if (MemVTs[i] != ValueVTs[i])
4744 DAG.
getStore(Root, dl, Val,
Add, PtrInfo, Alignment, MMOFlags, AAInfo);
4745 Chains[ChainI] = St;
4754void SelectionDAGBuilder::visitMaskedStore(
const CallInst &
I,
4755 bool IsCompressing) {
4761 Src0 =
I.getArgOperand(0);
4762 Ptr =
I.getArgOperand(1);
4763 Alignment = cast<ConstantInt>(
I.getArgOperand(2))->getAlignValue();
4764 Mask =
I.getArgOperand(3);
4769 Src0 =
I.getArgOperand(0);
4770 Ptr =
I.getArgOperand(1);
4771 Mask =
I.getArgOperand(2);
4772 Alignment =
I.getParamAlign(1).valueOrOne();
4775 Value *PtrOperand, *MaskOperand, *Src0Operand;
4778 getCompressingStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4780 getMaskedStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4790 if (
I.hasMetadata(LLVMContext::MD_nontemporal))
4835 assert(
Ptr->getType()->isVectorTy() &&
"Unexpected pointer type");
4838 if (
auto *
C = dyn_cast<Constant>(
Ptr)) {
4839 C =
C->getSplatValue();
4845 ElementCount NumElts = cast<VectorType>(
Ptr->getType())->getElementCount();
4854 if (!
GEP ||
GEP->getParent() != CurBB)
4857 if (
GEP->getNumOperands() != 2)
4860 const Value *BasePtr =
GEP->getPointerOperand();
4861 const Value *IndexVal =
GEP->getOperand(
GEP->getNumOperands() - 1);
4867 TypeSize ScaleVal =
DL.getTypeAllocSize(
GEP->getResultElementType());
4872 if (ScaleVal != 1 &&
4885void SelectionDAGBuilder::visitMaskedScatter(
const CallInst &
I) {
4893 Align Alignment = cast<ConstantInt>(
I.getArgOperand(2))
4894 ->getMaybeAlignValue()
4905 unsigned AS =
Ptr->getType()->getScalarType()->getPointerAddressSpace();
4925 Ops, MMO, IndexType,
false);
4930void SelectionDAGBuilder::visitMaskedLoad(
const CallInst &
I,
bool IsExpanding) {
4936 Ptr =
I.getArgOperand(0);
4937 Alignment = cast<ConstantInt>(
I.getArgOperand(1))->getAlignValue();
4938 Mask =
I.getArgOperand(2);
4939 Src0 =
I.getArgOperand(3);
4944 Ptr =
I.getArgOperand(0);
4945 Alignment =
I.getParamAlign(0).valueOrOne();
4946 Mask =
I.getArgOperand(1);
4947 Src0 =
I.getArgOperand(2);
4950 Value *PtrOperand, *MaskOperand, *Src0Operand;
4953 getExpandingLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4955 getMaskedLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4973 if (
I.hasMetadata(LLVMContext::MD_nontemporal))
4999void SelectionDAGBuilder::visitMaskedGather(
const CallInst &
I) {
5009 Align Alignment = cast<ConstantInt>(
I.getArgOperand(1))
5010 ->getMaybeAlignValue()
5022 unsigned AS =
Ptr->getType()->getScalarType()->getPointerAddressSpace();
5068 AAMDNodes(),
nullptr, SSID, SuccessOrdering, FailureOrdering);
5071 dl, MemVT, VTs, InChain,
5082void SelectionDAGBuilder::visitAtomicRMW(
const AtomicRMWInst &
I) {
5085 switch (
I.getOperation()) {
5135void SelectionDAGBuilder::visitFence(
const FenceInst &
I) {
5149void SelectionDAGBuilder::visitAtomicLoad(
const LoadInst &
I) {
5169 nullptr, SSID, Order);
5185void SelectionDAGBuilder::visitAtomicStore(
const StoreInst &
I) {
5207 nullptr, SSID, Ordering);
5223void SelectionDAGBuilder::visitTargetIntrinsic(
const CallInst &
I,
5224 unsigned Intrinsic) {
5229 bool HasChain = !
F->doesNotAccessMemory();
5230 bool OnlyLoad = HasChain &&
F->onlyReadsMemory();
5257 for (
unsigned i = 0, e =
I.arg_size(); i != e; ++i) {
5258 const Value *Arg =
I.getArgOperand(i);
5259 if (!
I.paramHasAttr(i, Attribute::ImmArg)) {
5266 if (
const ConstantInt *CI = dyn_cast<ConstantInt>(Arg)) {
5267 assert(CI->getBitWidth() <= 64 &&
5268 "large intrinsic immediates not handled");
5286 if (
auto *FPMO = dyn_cast<FPMathOperator>(&
I))
5287 Flags.copyFMF(*FPMO);
5294 auto *Token = Bundle->Inputs[0].get();
5296 assert(Ops.
back().getValueType() != MVT::Glue &&
5297 "Did not expected another glue node here.");
5305 if (IsTgtIntrinsic) {
5313 else if (
Info.fallbackAddressSpace)
5317 Info.size,
I.getAAMetadata());
5318 }
else if (!HasChain) {
5320 }
else if (!
I.getType()->isVoidTy()) {
5334 if (!
I.getType()->isVoidTy()) {
5335 if (!isa<VectorType>(
I.getType()))
5407 SDValue TwoToFractionalPartOfX;
5484 if (
Op.getValueType() == MVT::f32 &&
5508 if (
Op.getValueType() == MVT::f32 &&
5607 if (
Op.getValueType() == MVT::f32 &&
5691 return DAG.
getNode(
ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
5704 if (
Op.getValueType() == MVT::f32 &&
5781 return DAG.
getNode(
ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
5792 if (
Op.getValueType() == MVT::f32 &&
5805 bool IsExp10 =
false;
5806 if (
LHS.getValueType() == MVT::f32 &&
RHS.getValueType() == MVT::f32 &&
5810 IsExp10 = LHSC->isExactlyValue(Ten);
5837 unsigned Val = RHSC->getSExtValue();
5866 CurSquare, CurSquare);
5871 if (RHSC->getSExtValue() < 0)
5885 EVT VT =
LHS.getValueType();
5908 if ((ScaleInt > 0 || (Saturating &&
Signed)) &&
5912 Opcode, VT, ScaleInt);
5947 switch (
N.getOpcode()) {
5950 Regs.emplace_back(cast<RegisterSDNode>(
Op)->
getReg(),
5951 Op.getValueType().getSizeInBits());
5976bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
5979 const Argument *Arg = dyn_cast<Argument>(V);
5993 auto &Inst =
TII->get(TargetOpcode::DBG_INSTR_REF);
6000 auto *NewDIExpr = FragExpr;
6007 return BuildMI(MF,
DL, Inst,
false, MOs, Variable, NewDIExpr);
6010 auto &Inst =
TII->get(TargetOpcode::DBG_VALUE);
6011 return BuildMI(MF,
DL, Inst, Indirect, Reg, Variable, FragExpr);
6015 if (Kind == FuncArgumentDbgValueKind::Value) {
6020 if (!IsInEntryBlock)
6036 bool VariableIsFunctionInputArg = Variable->
isParameter() &&
6037 !
DL->getInlinedAt();
6039 if (!IsInPrologue && !VariableIsFunctionInputArg)
6073 if (VariableIsFunctionInputArg) {
6078 return !NodeMap[
V].getNode();
6083 bool IsIndirect =
false;
6084 std::optional<MachineOperand>
Op;
6087 if (FI != std::numeric_limits<int>::max())
6091 if (!
Op &&
N.getNode()) {
6094 if (ArgRegsAndSizes.
size() == 1)
6095 Reg = ArgRegsAndSizes.
front().first;
6097 if (Reg &&
Reg.isVirtual()) {
6105 IsIndirect =
Kind != FuncArgumentDbgValueKind::Value;
6109 if (!
Op &&
N.getNode()) {
6114 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
6123 for (
const auto &RegAndSize : SplitRegs) {
6127 int RegFragmentSizeInBits = RegAndSize.second;
6129 uint64_t ExprFragmentSizeInBits = ExprFragmentInfo->SizeInBits;
6132 if (
Offset >= ExprFragmentSizeInBits)
6136 if (
Offset + RegFragmentSizeInBits > ExprFragmentSizeInBits) {
6137 RegFragmentSizeInBits = ExprFragmentSizeInBits -
Offset;
6142 Expr,
Offset, RegFragmentSizeInBits);
6143 Offset += RegAndSize.second;
6146 if (!FragmentExpr) {
6153 MakeVRegDbgValue(RegAndSize.first, *FragmentExpr,
6154 Kind != FuncArgumentDbgValueKind::Value);
6165 V->getType(), std::nullopt);
6166 if (RFV.occupiesMultipleRegs()) {
6167 splitMultiRegDbgValue(RFV.getRegsAndSizes());
6172 IsIndirect =
Kind != FuncArgumentDbgValueKind::Value;
6173 }
else if (ArgRegsAndSizes.
size() > 1) {
6176 splitMultiRegDbgValue(ArgRegsAndSizes);
6185 "Expected inlined-at fields to agree");
6189 NewMI = MakeVRegDbgValue(
Op->getReg(), Expr, IsIndirect);
6191 NewMI =
BuildMI(MF,
DL,
TII->get(TargetOpcode::DBG_VALUE),
true, *
Op,
6204 unsigned DbgSDNodeOrder) {
6205 if (
auto *FISDN = dyn_cast<FrameIndexSDNode>(
N.getNode())) {
6217 false, dl, DbgSDNodeOrder);
6220 false, dl, DbgSDNodeOrder);
6224 switch (Intrinsic) {
6225 case Intrinsic::smul_fix:
6227 case Intrinsic::umul_fix:
6229 case Intrinsic::smul_fix_sat:
6231 case Intrinsic::umul_fix_sat:
6233 case Intrinsic::sdiv_fix:
6235 case Intrinsic::udiv_fix:
6237 case Intrinsic::sdiv_fix_sat:
6239 case Intrinsic::udiv_fix_sat:
6246void SelectionDAGBuilder::lowerCallToExternalSymbol(
const CallInst &
I,
6247 const char *FunctionName) {
6248 assert(FunctionName &&
"FunctionName must not be nullptr");
6258 assert(cast<CallBase>(PreallocatedSetup)
6261 "expected call_preallocated_setup Value");
6262 for (
const auto *U : PreallocatedSetup->
users()) {
6263 auto *UseCall = cast<CallBase>(U);
6264 const Function *Fn = UseCall->getCalledFunction();
6265 if (!Fn || Fn->
getIntrinsicID() != Intrinsic::call_preallocated_arg) {
6275bool SelectionDAGBuilder::visitEntryValueDbgValue(
6282 const Argument *Arg = cast<Argument>(Values[0]);
6288 dbgs() <<
"Dropping dbg.value: expression is entry_value but "
6289 "couldn't find an associated register for the Argument\n");
6292 Register ArgVReg = ArgIt->getSecond();
6295 if (ArgVReg == VirtReg || ArgVReg == PhysReg) {
6297 Variable, Expr, PhysReg,
false , DbgLoc, SDNodeOrder);
6301 LLVM_DEBUG(
dbgs() <<
"Dropping dbg.value: expression is entry_value but "
6302 "couldn't find a physical register\n");
6307void SelectionDAGBuilder::visitConvergenceControl(
const CallInst &
I,
6308 unsigned Intrinsic) {
6310 switch (Intrinsic) {
6311 case Intrinsic::experimental_convergence_anchor:
6314 case Intrinsic::experimental_convergence_entry:
6317 case Intrinsic::experimental_convergence_loop: {
6319 auto *Token = Bundle->Inputs[0].get();
6327void SelectionDAGBuilder::visitVectorHistogram(
const CallInst &
I,
6328 unsigned IntrinsicID) {
6331 assert(IntrinsicID == Intrinsic::experimental_vector_histogram_add &&
6332 "Tried to lower unsupported histogram type");
6353 unsigned AS =
Ptr->getType()->getScalarType()->getPointerAddressSpace();
6379 Ops, MMO, IndexType);
6386void SelectionDAGBuilder::visitIntrinsicCall(
const CallInst &
I,
6387 unsigned Intrinsic) {
6394 if (
auto *FPOp = dyn_cast<FPMathOperator>(&
I))
6395 Flags.copyFMF(*FPOp);
6397 switch (Intrinsic) {
6400 visitTargetIntrinsic(
I, Intrinsic);
6402 case Intrinsic::vscale: {
6407 case Intrinsic::vastart: visitVAStart(
I);
return;
6408 case Intrinsic::vaend: visitVAEnd(
I);
return;
6409 case Intrinsic::vacopy: visitVACopy(
I);
return;
6410 case Intrinsic::returnaddress:
6415 case Intrinsic::addressofreturnaddress:
6420 case Intrinsic::sponentry:
6425 case Intrinsic::frameaddress:
6430 case Intrinsic::read_volatile_register:
6431 case Intrinsic::read_register: {
6435 DAG.
getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
6443 case Intrinsic::write_register: {
6445 Value *RegValue =
I.getArgOperand(1);
6448 DAG.
getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
6453 case Intrinsic::memcpy: {
6454 const auto &MCI = cast<MemCpyInst>(
I);
6459 Align DstAlign = MCI.getDestAlign().valueOrOne();
6460 Align SrcAlign = MCI.getSourceAlign().valueOrOne();
6461 Align Alignment = std::min(DstAlign, SrcAlign);
6462 bool isVol = MCI.isVolatile();
6467 false, &
I, std::nullopt,
6470 I.getAAMetadata(),
AA);
6471 updateDAGForMaybeTailCall(MC);
6474 case Intrinsic::memcpy_inline: {
6475 const auto &MCI = cast<MemCpyInlineInst>(
I);
6479 assert(isa<ConstantSDNode>(
Size) &&
"memcpy_inline needs constant size");
6481 Align DstAlign = MCI.getDestAlign().valueOrOne();
6482 Align SrcAlign = MCI.getSourceAlign().valueOrOne();
6483 Align Alignment = std::min(DstAlign, SrcAlign);
6484 bool isVol = MCI.isVolatile();
6488 true, &
I, std::nullopt,
6491 I.getAAMetadata(),
AA);
6492 updateDAGForMaybeTailCall(MC);
6495 case Intrinsic::memset: {
6496 const auto &MSI = cast<MemSetInst>(
I);
6501 Align Alignment = MSI.getDestAlign().valueOrOne();
6502 bool isVol = MSI.isVolatile();
6505 Root, sdl, Op1, Op2, Op3, Alignment, isVol,
false,
6507 updateDAGForMaybeTailCall(MS);
6510 case Intrinsic::memset_inline: {
6511 const auto &MSII = cast<MemSetInlineInst>(
I);
6515 assert(isa<ConstantSDNode>(
Size) &&
"memset_inline needs constant size");
6517 Align DstAlign = MSII.getDestAlign().valueOrOne();
6518 bool isVol = MSII.isVolatile();
6524 updateDAGForMaybeTailCall(MC);
6527 case Intrinsic::memmove: {
6528 const auto &MMI = cast<MemMoveInst>(
I);
6533 Align DstAlign = MMI.getDestAlign().valueOrOne();
6534 Align SrcAlign = MMI.getSourceAlign().valueOrOne();
6535 Align Alignment = std::min(DstAlign, SrcAlign);
6536 bool isVol = MMI.isVolatile();
6544 I.getAAMetadata(),
AA);
6545 updateDAGForMaybeTailCall(MM);
6548 case Intrinsic::memcpy_element_unordered_atomic: {
6554 Type *LengthTy =
MI.getLength()->getType();
6555 unsigned ElemSz =
MI.getElementSizeInBytes();
6561 updateDAGForMaybeTailCall(MC);
6564 case Intrinsic::memmove_element_unordered_atomic: {
6565 auto &
MI = cast<AtomicMemMoveInst>(
I);
6570 Type *LengthTy =
MI.getLength()->getType();
6571 unsigned ElemSz =
MI.getElementSizeInBytes();
6577 updateDAGForMaybeTailCall(MC);
6580 case Intrinsic::memset_element_unordered_atomic: {
6581 auto &
MI = cast<AtomicMemSetInst>(
I);
6586 Type *LengthTy =
MI.getLength()->getType();
6587 unsigned ElemSz =
MI.getElementSizeInBytes();
6592 updateDAGForMaybeTailCall(MC);
6595 case Intrinsic::call_preallocated_setup: {
6604 case Intrinsic::call_preallocated_arg: {
6619 case Intrinsic::dbg_declare: {
6620 const auto &DI = cast<DbgDeclareInst>(
I);
6623 if (AssignmentTrackingEnabled ||
6626 LLVM_DEBUG(
dbgs() <<
"SelectionDAG visiting dbg_declare: " << DI <<
"\n");
6632 assert(!DI.hasArgList() &&
"Only dbg.value should currently use DIArgList");
6637 case Intrinsic::dbg_label: {
6640 assert(Label &&
"Missing label");
6647 case Intrinsic::dbg_assign: {
6649 if (AssignmentTrackingEnabled)
6655 case Intrinsic::dbg_value: {
6657 if (AssignmentTrackingEnabled)
6677 SDNodeOrder, IsVariadic))
6683 case Intrinsic::eh_typeid_for: {
6692 case Intrinsic::eh_return_i32:
6693 case Intrinsic::eh_return_i64:
6701 case Intrinsic::eh_unwind_init:
6704 case Intrinsic::eh_dwarf_cfa:
6709 case Intrinsic::eh_sjlj_callsite: {
6710 ConstantInt *CI = cast<ConstantInt>(
I.getArgOperand(0));
6712 "Overlapping call sites!");
6717 case Intrinsic::eh_sjlj_functioncontext: {
6721 cast<AllocaInst>(
I.getArgOperand(0)->stripPointerCasts());
6726 case Intrinsic::eh_sjlj_setjmp: {
6736 case Intrinsic::eh_sjlj_longjmp:
6740 case Intrinsic::eh_sjlj_setup_dispatch:
6744 case Intrinsic::masked_gather:
6745 visitMaskedGather(
I);
6747 case Intrinsic::masked_load:
6750 case Intrinsic::masked_scatter:
6751 visitMaskedScatter(
I);
6753 case Intrinsic::masked_store:
6754 visitMaskedStore(
I);
6756 case Intrinsic::masked_expandload:
6757 visitMaskedLoad(
I,
true );
6759 case Intrinsic::masked_compressstore:
6760 visitMaskedStore(
I,
true );
6762 case Intrinsic::powi:
6766 case Intrinsic::log:
6769 case Intrinsic::log2:
6773 case Intrinsic::log10:
6777 case Intrinsic::exp:
6780 case Intrinsic::exp2:
6784 case Intrinsic::pow:
6788 case Intrinsic::sqrt:
6789 case Intrinsic::fabs:
6790 case Intrinsic::sin:
6791 case Intrinsic::cos:
6792 case Intrinsic::tan:
6793 case Intrinsic::asin:
6794 case Intrinsic::acos:
6795 case Intrinsic::atan:
6796 case Intrinsic::sinh:
6797 case Intrinsic::cosh:
6798 case Intrinsic::tanh:
6799 case Intrinsic::exp10:
6800 case Intrinsic::floor:
6801 case Intrinsic::ceil:
6802 case Intrinsic::trunc:
6803 case Intrinsic::rint:
6804 case Intrinsic::nearbyint:
6805 case Intrinsic::round:
6806 case Intrinsic::roundeven:
6807 case Intrinsic::canonicalize: {
6810 switch (Intrinsic) {
6812 case Intrinsic::sqrt: Opcode =
ISD::FSQRT;
break;
6813 case Intrinsic::fabs: Opcode =
ISD::FABS;
break;
6814 case Intrinsic::sin: Opcode =
ISD::FSIN;
break;
6815 case Intrinsic::cos: Opcode =
ISD::FCOS;
break;
6816 case Intrinsic::tan: Opcode =
ISD::FTAN;
break;
6817 case Intrinsic::asin: Opcode =
ISD::FASIN;
break;
6818 case Intrinsic::acos: Opcode =
ISD::FACOS;
break;
6819 case Intrinsic::atan: Opcode =
ISD::FATAN;
break;
6820 case Intrinsic::sinh: Opcode =
ISD::FSINH;
break;
6821 case Intrinsic::cosh: Opcode =
ISD::FCOSH;
break;
6822 case Intrinsic::tanh: Opcode =
ISD::FTANH;
break;
6823 case Intrinsic::exp10: Opcode =
ISD::FEXP10;
break;
6824 case Intrinsic::floor: Opcode =
ISD::FFLOOR;
break;
6825 case Intrinsic::ceil: Opcode =
ISD::FCEIL;
break;
6826 case Intrinsic::trunc: Opcode =
ISD::FTRUNC;
break;
6827 case Intrinsic::rint: Opcode =
ISD::FRINT;
break;
6829 case Intrinsic::round: Opcode =
ISD::FROUND;
break;
6840 case Intrinsic::lround:
6841 case Intrinsic::llround:
6842 case Intrinsic::lrint:
6843 case Intrinsic::llrint: {
6846 switch (Intrinsic) {
6848 case Intrinsic::lround: Opcode =
ISD::LROUND;
break;
6850 case Intrinsic::lrint: Opcode =
ISD::LRINT;
break;
6851 case Intrinsic::llrint: Opcode =
ISD::LLRINT;
break;
6860 case Intrinsic::minnum:
6866 case Intrinsic::maxnum:
6872 case Intrinsic::minimum:
6878 case Intrinsic::maximum:
6884 case Intrinsic::copysign:
6890 case Intrinsic::ldexp:
6896 case Intrinsic::frexp: {
6904 case Intrinsic::arithmetic_fence: {
6910 case Intrinsic::fma:
6916#define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \
6917 case Intrinsic::INTRINSIC:
6918#include "llvm/IR/ConstrainedOps.def"
6919 visitConstrainedFPIntrinsic(cast<ConstrainedFPIntrinsic>(
I));
6921#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID:
6922#include "llvm/IR/VPIntrinsics.def"
6923 visitVectorPredicationIntrinsic(cast<VPIntrinsic>(
I));
6925 case Intrinsic::fptrunc_round: {
6928 Metadata *MD = cast<MetadataAsValue>(
I.getArgOperand(1))->getMetadata();
6929 std::optional<RoundingMode> RoundMode =
6936 Flags.copyFMF(*cast<FPMathOperator>(&
I));
6948 case Intrinsic::fmuladd: {
6969 case Intrinsic::convert_to_fp16:
6976 case Intrinsic::convert_from_fp16:
6982 case Intrinsic::fptosi_sat: {
6989 case Intrinsic::fptoui_sat: {
6996 case Intrinsic::set_rounding:
7002 case Intrinsic::is_fpclass: {
7007 cast<ConstantInt>(
I.getArgOperand(1))->getZExtValue());
7012 Flags.setNoFPExcept(
7013 !
F.getAttributes().hasFnAttr(llvm::Attribute::StrictFP));
7028 case Intrinsic::get_fpenv: {
7043 int SPFI = cast<FrameIndexSDNode>(Temp.
getNode())->getIndex();
7050 Res =
DAG.
getLoad(EnvVT, sdl, Chain, Temp, MPI);
7056 case Intrinsic::set_fpenv: {
7070 int SPFI = cast<FrameIndexSDNode>(Temp.
getNode())->getIndex();
7073 Chain =
DAG.
getStore(Chain, sdl, Env, Temp, MPI, TempAlign,
7083 case Intrinsic::reset_fpenv:
7086 case Intrinsic::get_fpmode:
7095 case Intrinsic::set_fpmode:
7100 case Intrinsic::reset_fpmode: {
7105 case Intrinsic::pcmarker: {
7110 case Intrinsic::readcyclecounter: {
7118 case Intrinsic::readsteadycounter: {
7126 case Intrinsic::bitreverse:
7131 case Intrinsic::bswap:
7136 case Intrinsic::cttz: {
7138 ConstantInt *CI = cast<ConstantInt>(
I.getArgOperand(1));
7144 case Intrinsic::ctlz: {
7146 ConstantInt *CI = cast<ConstantInt>(
I.getArgOperand(1));
7152 case Intrinsic::ctpop: {
7158 case Intrinsic::fshl:
7159 case Intrinsic::fshr: {
7160 bool IsFSHL =
Intrinsic == Intrinsic::fshl;
7164 EVT VT =
X.getValueType();
7175 case Intrinsic::sadd_sat: {
7181 case Intrinsic::uadd_sat: {
7187 case Intrinsic::ssub_sat: {
7193 case Intrinsic::usub_sat: {
7199 case Intrinsic::sshl_sat: {
7205 case Intrinsic::ushl_sat: {
7211 case Intrinsic::smul_fix:
7212 case Intrinsic::umul_fix:
7213 case Intrinsic::smul_fix_sat:
7214 case Intrinsic::umul_fix_sat: {
7222 case Intrinsic::sdiv_fix:
7223 case Intrinsic::udiv_fix:
7224 case Intrinsic::sdiv_fix_sat:
7225 case Intrinsic::udiv_fix_sat: {
7230 Op1, Op2, Op3,
DAG, TLI));
7233 case Intrinsic::smax: {
7239 case Intrinsic::smin: {
7245 case Intrinsic::umax: {
7251 case Intrinsic::umin: {
7257 case Intrinsic::abs: {
7263 case Intrinsic::scmp: {
7270 case Intrinsic::ucmp: {
7277 case Intrinsic::stacksave: {
7285 case Intrinsic::stackrestore:
7289 case Intrinsic::get_dynamic_area_offset: {
7304 case Intrinsic::stackguard: {
7325 case Intrinsic::stackprotector: {
7346 Chain, sdl, Src, FIN,
7353 case Intrinsic::objectsize:
7356 case Intrinsic::is_constant:
7359 case Intrinsic::annotation:
7360 case Intrinsic::ptr_annotation:
7361 case Intrinsic::launder_invariant_group:
7362 case Intrinsic::strip_invariant_group:
7367 case Intrinsic::assume:
7368 case Intrinsic::experimental_noalias_scope_decl:
7369 case Intrinsic::var_annotation:
7370 case Intrinsic::sideeffect:
7375 case Intrinsic::codeview_annotation: {
7379 Metadata *MD = cast<MetadataAsValue>(
I.getArgOperand(0))->getMetadata();
7386 case Intrinsic::init_trampoline: {
7387 const Function *
F = cast<Function>(
I.getArgOperand(1)->stripPointerCasts());
7402 case Intrinsic::adjust_trampoline:
7407 case Intrinsic::gcroot: {
7409 "only valid in functions with gc specified, enforced by Verifier");
7411 const Value *Alloca =
I.getArgOperand(0)->stripPointerCasts();
7412 const Constant *TypeMap = cast<Constant>(
I.getArgOperand(1));
7418 case Intrinsic::gcread:
7419 case Intrinsic::gcwrite:
7421 case Intrinsic::get_rounding:
7427 case Intrinsic::expect:
7432 case Intrinsic::ubsantrap:
7433 case Intrinsic::debugtrap:
7434 case Intrinsic::trap: {
7436 I.getAttributes().getFnAttr(
"trap-func-name").getValueAsString();
7437 if (TrapFuncName.
empty()) {
7438 switch (Intrinsic) {
7439 case Intrinsic::trap:
7442 case Intrinsic::debugtrap:
7445 case Intrinsic::ubsantrap:
7449 cast<ConstantInt>(
I.getArgOperand(0))->getZExtValue(), sdl,
7457 if (Intrinsic == Intrinsic::ubsantrap) {
7459 Args[0].Val =
I.getArgOperand(0);
7461 Args[0].Ty =
Args[0].Val->getType();
7465 CLI.setDebugLoc(sdl).setChain(
getRoot()).setLibCallee(
7476 case Intrinsic::allow_runtime_check:
7477 case Intrinsic::allow_ubsan_check:
7481 case Intrinsic::uadd_with_overflow:
7482 case Intrinsic::sadd_with_overflow:
7483 case Intrinsic::usub_with_overflow:
7484 case Intrinsic::ssub_with_overflow:
7485 case Intrinsic::umul_with_overflow:
7486 case Intrinsic::smul_with_overflow: {
7488 switch (Intrinsic) {
7490 case Intrinsic::uadd_with_overflow:
Op =
ISD::UADDO;
break;
7491 case Intrinsic::sadd_with_overflow:
Op =
ISD::SADDO;
break;
7492 case Intrinsic::usub_with_overflow:
Op =
ISD::USUBO;
break;
7493 case Intrinsic::ssub_with_overflow:
Op =
ISD::SSUBO;
break;
7494 case Intrinsic::umul_with_overflow:
Op =
ISD::UMULO;
break;
7495 case Intrinsic::smul_with_overflow:
Op =
ISD::SMULO;
break;
7501 EVT OverflowVT = MVT::i1;
7510 case Intrinsic::prefetch: {
7512 unsigned rw = cast<ConstantInt>(
I.getArgOperand(1))->getZExtValue();
7525 std::nullopt, Flags);
7534 case Intrinsic::lifetime_start:
7535 case Intrinsic::lifetime_end: {
7536 bool IsStart = (
Intrinsic == Intrinsic::lifetime_start);
7541 const int64_t ObjectSize =
7542 cast<ConstantInt>(
I.getArgOperand(0))->getSExtValue();
7547 for (
const Value *Alloca : Allocas) {
7548 const AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(Alloca);
7551 if (!LifetimeObject)
7571 case Intrinsic::pseudoprobe: {
7572 auto Guid = cast<ConstantInt>(
I.getArgOperand(0))->getZExtValue();
7573 auto Index = cast<ConstantInt>(
I.getArgOperand(1))->getZExtValue();
7574 auto Attr = cast<ConstantInt>(
I.getArgOperand(2))->getZExtValue();
7579 case Intrinsic::invariant_start:
7584 case Intrinsic::invariant_end:
7587 case Intrinsic::clear_cache: {
7592 {InputChain, StartVal, EndVal});
7597 case Intrinsic::donothing:
7598 case Intrinsic::seh_try_begin:
7599 case Intrinsic::seh_scope_begin:
7600 case Intrinsic::seh_try_end:
7601 case Intrinsic::seh_scope_end:
7604 case Intrinsic::experimental_stackmap:
7607 case Intrinsic::experimental_patchpoint_void:
7608 case Intrinsic::experimental_patchpoint:
7611 case Intrinsic::experimental_gc_statepoint:
7614 case Intrinsic::experimental_gc_result:
7615 visitGCResult(cast<GCResultInst>(
I));
7617 case Intrinsic::experimental_gc_relocate:
7618 visitGCRelocate(cast<GCRelocateInst>(
I));
7620 case Intrinsic::instrprof_cover:
7622 case Intrinsic::instrprof_increment:
7624 case Intrinsic::instrprof_timestamp:
7626 case Intrinsic::instrprof_value_profile:
7628 case Intrinsic::instrprof_mcdc_parameters:
7630 case Intrinsic::instrprof_mcdc_tvbitmap_update:
7632 case Intrinsic::localescape: {
7638 for (
unsigned Idx = 0, E =
I.arg_size();
Idx < E; ++
Idx) {
7639 Value *Arg =
I.getArgOperand(
Idx)->stripPointerCasts();
7640 if (isa<ConstantPointerNull>(Arg))
7644 "can only escape static allocas");
7649 TII->get(TargetOpcode::LOCAL_ESCAPE))
7657 case Intrinsic::localrecover: {
7662 auto *Fn = cast<Function>(
I.getArgOperand(0)->stripPointerCasts());
7663 auto *
Idx = cast<ConstantInt>(
I.getArgOperand(2));
7665 unsigned(
Idx->getLimitedValue(std::numeric_limits<int>::max()));
7686 case Intrinsic::eh_exceptionpointer:
7687 case Intrinsic::eh_exceptioncode: {
7689 const auto *CPI = cast<CatchPadInst>(
I.getArgOperand(0));
7694 if (Intrinsic == Intrinsic::eh_exceptioncode)
7699 case Intrinsic::xray_customevent: {
7728 case Intrinsic::xray_typedevent: {
7755 TargetOpcode::PATCHABLE_TYPED_EVENT_CALL, sdl, NodeTys, Ops);
7761 case Intrinsic::experimental_deoptimize:
7764 case Intrinsic::experimental_stepvector:
7767 case Intrinsic::vector_reduce_fadd:
7768 case Intrinsic::vector_reduce_fmul:
7769 case Intrinsic::vector_reduce_add:
7770 case Intrinsic::vector_reduce_mul:
7771 case Intrinsic::vector_reduce_and:
7772 case Intrinsic::vector_reduce_or:
7773 case Intrinsic::vector_reduce_xor:
7774 case Intrinsic::vector_reduce_smax:
7775 case Intrinsic::vector_reduce_smin:
7776 case Intrinsic::vector_reduce_umax:
7777 case Intrinsic::vector_reduce_umin:
7778 case Intrinsic::vector_reduce_fmax:
7779 case Intrinsic::vector_reduce_fmin:
7780 case Intrinsic::vector_reduce_fmaximum:
7781 case Intrinsic::vector_reduce_fminimum:
7782 visitVectorReduce(
I, Intrinsic);
7785 case Intrinsic::icall_branch_funnel: {
7794 "llvm.icall.branch.funnel operand must be a GlobalValue");
7797 struct BranchFunnelTarget {
7803 for (
unsigned Op = 1,
N =
I.arg_size();
Op !=
N;
Op += 2) {
7806 if (ElemBase !=
Base)
7808 "to the same GlobalValue");
7811 auto *GA = dyn_cast<GlobalAddressSDNode>(Val);
7814 "llvm.icall.branch.funnel operand must be a GlobalValue");
7820 [](
const BranchFunnelTarget &T1,
const BranchFunnelTarget &T2) {
7821 return T1.Offset < T2.Offset;
7824 for (
auto &
T : Targets) {
7839 case Intrinsic::wasm_landingpad_index:
7845 case Intrinsic::aarch64_settag:
7846 case Intrinsic::aarch64_settag_zero: {
7848 bool ZeroMemory =
Intrinsic == Intrinsic::aarch64_settag_zero;
7857 case Intrinsic::amdgcn_cs_chain: {
7858 assert(
I.arg_size() == 5 &&
"Additional args not supported yet");
7859 assert(cast<ConstantInt>(
I.getOperand(4))->isZero() &&
7860 "Non-zero flags not supported yet");
7876 for (
unsigned Idx : {2, 3, 1}) {
7879 Arg.
Ty =
I.getOperand(
Idx)->getType();
7881 Args.push_back(Arg);
7884 assert(Args[0].IsInReg &&
"SGPR args should be marked inreg");
7885 assert(!Args[1].IsInReg &&
"VGPR args should not be marked inreg");
7886 Args[2].IsInReg =
true;
7891 .setCallee(
CC,
RetTy, Callee, std::move(Args))
7894 .setConvergent(
I.isConvergent());
7896 std::pair<SDValue, SDValue>
Result =
7900 "Should've lowered as tail call");
7905 case Intrinsic::ptrmask: {
7925 case Intrinsic::threadlocal_address: {
7929 case Intrinsic::get_active_lane_mask: {
7932 EVT ElementVT =
Index.getValueType();
7935 visitTargetIntrinsic(
I, Intrinsic);
7953 case Intrinsic::experimental_get_vector_length: {
7954 assert(cast<ConstantInt>(
I.getOperand(1))->getSExtValue() > 0 &&
7955 "Expected positive VF");
7956 unsigned VF = cast<ConstantInt>(
I.getOperand(1))->getZExtValue();
7957 bool IsScalable = cast<ConstantInt>(
I.getOperand(2))->isOne();
7963 visitTargetIntrinsic(
I, Intrinsic);
7972 if (CountVT.
bitsLT(VT)) {
7987 case Intrinsic::experimental_vector_partial_reduce_add: {
7996 std::deque<SDValue> Subvectors;
7997 Subvectors.push_back(
getValue(
I.getOperand(0)));
7998 for (
unsigned i = 0; i < ScaleFactor; i++) {
8001 {OpNode, SourceIndex}));
8005 while (Subvectors.size() > 1) {
8007 {Subvectors[0], Subvectors[1]}));
8008 Subvectors.pop_front();
8009 Subvectors.pop_front();
8012 assert(Subvectors.size() == 1 &&
8013 "There should only be one subvector after tree flattening");
8018 case Intrinsic::experimental_cttz_elts: {
8021 EVT OpVT =
Op.getValueType();
8024 visitTargetIntrinsic(
I, Intrinsic);
8039 !cast<ConstantSDNode>(
getValue(
I.getOperand(1)))->isZero();
8041 if (isa<ScalableVectorType>(
I.getOperand(0)->getType()))
8069 case Intrinsic::vector_insert: {
8077 if (
Index.getValueType() != VectorIdxTy)
8085 case Intrinsic::vector_extract: {
8093 if (
Index.getValueType() != VectorIdxTy)
8100 case Intrinsic::vector_reverse:
8101 visitVectorReverse(
I);
8103 case Intrinsic::vector_splice:
8104 visitVectorSplice(
I);
8106 case Intrinsic::callbr_landingpad:
8107 visitCallBrLandingPad(
I);
8109 case Intrinsic::vector_interleave2:
8110 visitVectorInterleave(
I);
8112 case Intrinsic::vector_deinterleave2:
8113 visitVectorDeinterleave(
I);
8115 case Intrinsic::experimental_vector_compress:
8122 case Intrinsic::experimental_convergence_anchor:
8123 case Intrinsic::experimental_convergence_entry:
8124 case Intrinsic::experimental_convergence_loop:
8125 visitConvergenceControl(
I, Intrinsic);
8127 case Intrinsic::experimental_vector_histogram_add: {
8128 visitVectorHistogram(
I, Intrinsic);
8134void SelectionDAGBuilder::visitConstrainedFPIntrinsic(
8162 PendingConstrainedFP.push_back(OutChain);
8168 PendingConstrainedFPStrict.push_back(OutChain);
8180 Flags.setNoFPExcept(
true);
8182 if (
auto *FPOp = dyn_cast<FPMathOperator>(&FPI))
8183 Flags.copyFMF(*FPOp);
8188#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
8189 case Intrinsic::INTRINSIC: \
8190 Opcode = ISD::STRICT_##DAGN; \
8192#include "llvm/IR/ConstrainedOps.def"
8193 case Intrinsic::experimental_constrained_fmuladd: {
8200 pushOutChain(
Mul, EB);
8221 auto *
FPCmp = dyn_cast<ConstrainedFPCmpIntrinsic>(&FPI);
8231 pushOutChain(Result, EB);
8238 std::optional<unsigned> ResOPC;
8240 case Intrinsic::vp_ctlz: {
8241 bool IsZeroUndef = cast<ConstantInt>(VPIntrin.
getArgOperand(1))->isOne();
8242 ResOPC = IsZeroUndef ? ISD::VP_CTLZ_ZERO_UNDEF : ISD::VP_CTLZ;
8245 case Intrinsic::vp_cttz: {
8246 bool IsZeroUndef = cast<ConstantInt>(VPIntrin.
getArgOperand(1))->isOne();
8247 ResOPC = IsZeroUndef ? ISD::VP_CTTZ_ZERO_UNDEF : ISD::VP_CTTZ;
8250 case Intrinsic::vp_cttz_elts: {
8251 bool IsZeroPoison = cast<ConstantInt>(VPIntrin.
getArgOperand(1))->isOne();
8252 ResOPC = IsZeroPoison ? ISD::VP_CTTZ_ELTS_ZERO_UNDEF : ISD::VP_CTTZ_ELTS;
8255#define HELPER_MAP_VPID_TO_VPSD(VPID, VPSD) \
8256 case Intrinsic::VPID: \
8257 ResOPC = ISD::VPSD; \
8259#include "llvm/IR/VPIntrinsics.def"
8264 "Inconsistency: no SDNode available for this VPIntrinsic!");
8266 if (*ResOPC == ISD::VP_REDUCE_SEQ_FADD ||
8267 *ResOPC == ISD::VP_REDUCE_SEQ_FMUL) {
8269 return *ResOPC == ISD::VP_REDUCE_SEQ_FADD ? ISD::VP_REDUCE_FADD
8270 : ISD::VP_REDUCE_FMUL;
8276void SelectionDAGBuilder::visitVPLoad(
8302void SelectionDAGBuilder::visitVPGather(
8338 {DAG.getRoot(), Base, Index, Scale, OpValues[1], OpValues[2]}, MMO,
8344void SelectionDAGBuilder::visitVPStore(
8348 EVT VT = OpValues[0].getValueType();
8366void SelectionDAGBuilder::visitVPScatter(
8371 EVT VT = OpValues[0].getValueType();
8401 {getMemoryRoot(), OpValues[0], Base, Index, Scale,
8402 OpValues[2], OpValues[3]},
8408void SelectionDAGBuilder::visitVPStridedLoad(
8427 OpValues[2], OpValues[3], MMO,
8435void SelectionDAGBuilder::visitVPStridedStore(
8439 EVT VT = OpValues[0].getValueType();
8451 DAG.
getUNDEF(OpValues[1].getValueType()), OpValues[2], OpValues[3],
8459void SelectionDAGBuilder::visitVPCmp(
const VPCmpIntrinsic &VPIntrin) {
8484 "Unexpected target EVL type");
8493void SelectionDAGBuilder::visitVectorPredicationIntrinsic(
8500 if (
const auto *CmpI = dyn_cast<VPCmpIntrinsic>(&VPIntrin))
8501 return visitVPCmp(*CmpI);
8512 "Unexpected target EVL type");
8516 for (
unsigned I = 0;
I < VPIntrin.
arg_size(); ++
I) {
8518 if (
I == EVLParamPos)
8526 if (
auto *FPMO = dyn_cast<FPMathOperator>(&VPIntrin))
8533 visitVPLoad(VPIntrin, ValueVTs[0], OpValues);
8535 case ISD::VP_GATHER:
8536 visitVPGather(VPIntrin, ValueVTs[0], OpValues);
8538 case ISD::EXPERIMENTAL_VP_STRIDED_LOAD:
8539 visitVPStridedLoad(VPIntrin, ValueVTs[0], OpValues);
8542 visitVPStore(VPIntrin, OpValues);
8544 case ISD::VP_SCATTER:
8545 visitVPScatter(VPIntrin, OpValues);
8547 case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
8548 visitVPStridedStore(VPIntrin, OpValues);
8550 case ISD::VP_FMULADD: {
8551 assert(OpValues.
size() == 5 &&
"Unexpected number of operands");
8553 if (
auto *FPMO = dyn_cast<FPMathOperator>(&VPIntrin))
8560 ISD::VP_FMUL,
DL, VTs,
8561 {OpValues[0], OpValues[1], OpValues[3], OpValues[4]}, SDFlags);
8564 {
Mul, OpValues[2], OpValues[3], OpValues[4]}, SDFlags);
8569 case ISD::VP_IS_FPCLASS: {
8572 auto Constant = OpValues[1]->getAsZExtVal();
8575 {OpValues[0],
Check, OpValues[2], OpValues[3]});
8579 case ISD::VP_INTTOPTR: {
8590 case ISD::VP_PTRTOINT: {
8605 case ISD::VP_CTLZ_ZERO_UNDEF:
8607 case ISD::VP_CTTZ_ZERO_UNDEF:
8608 case ISD::VP_CTTZ_ELTS_ZERO_UNDEF:
8609 case ISD::VP_CTTZ_ELTS: {
8611 DAG.
getNode(Opcode,
DL, VTs, {OpValues[0], OpValues[2], OpValues[3]});
8631 if (CallSiteIndex) {
8645 assert(BeginLabel &&
"BeginLabel should've been set");
8659 assert(
II &&
"II should've been set");
8670std::pair<SDValue, SDValue>
8684 std::pair<SDValue, SDValue> Result = TLI.
LowerCallTo(CLI);
8687 "Non-null chain expected with non-tail call!");
8688 assert((Result.second.getNode() || !Result.first.getNode()) &&
8689 "Null value expected with tail call!");
8691 if (!Result.second.getNode()) {
8698 PendingExports.clear();
8713 bool isTailCall,
bool isMustTailCall,
8723 const Value *SwiftErrorVal =
nullptr;
8729 auto *Caller = CB.
getParent()->getParent();
8730 if (Caller->getFnAttribute(
"disable-tail-calls").getValueAsString() ==
8731 "true" && !isMustTailCall)
8738 Caller->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
8747 if (V->getType()->isEmptyTy())
8751 Entry.Node = ArgNode; Entry.Ty = V->getType();
8753 Entry.setAttributes(&CB,
I - CB.
arg_begin());
8765 Args.push_back(Entry);
8769 if (Entry.IsSRet && isa<Instruction>(V))
8777 Value *V = Bundle->Inputs[0];
8779 Entry.Node = ArgNode;
8780 Entry.Ty = V->getType();
8781 Entry.IsCFGuardTarget =
true;
8782 Args.push_back(Entry);
8800 "Target doesn't support calls with kcfi operand bundles.");
8801 CFIType = cast<ConstantInt>(Bundle->Inputs[0]);
8808 auto *Token = Bundle->Inputs[0].get();
8809 ConvControlToken =
getValue(Token);
8827 "This target doesn't support calls with ptrauth operand bundles.");
8831 std::pair<SDValue, SDValue> Result =
lowerInvokable(CLI, EHPadBB);
8833 if (Result.first.getNode()) {
8855 if (
const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
8874 bool ConstantMemory =
false;
8879 ConstantMemory =
true;
8890 if (!ConstantMemory)
8897void SelectionDAGBuilder::processIntegerCallValue(
const Instruction &
I,
8911bool SelectionDAGBuilder::visitMemCmpBCmpCall(
const CallInst &
I) {
8912 const Value *
LHS =
I.getArgOperand(0), *
RHS =
I.getArgOperand(1);
8926 if (Res.first.getNode()) {
8927 processIntegerCallValue(
I, Res.first,
true);
8941 auto hasFastLoadsAndCompare = [&](
unsigned NumBits) {
8964 switch (NumBitsToCompare) {
8976 LoadVT = hasFastLoadsAndCompare(NumBitsToCompare);
8994 processIntegerCallValue(
I, Cmp,
false);
9003bool SelectionDAGBuilder::visitMemChrCall(
const CallInst &
I) {
9004 const Value *Src =
I.getArgOperand(0);
9009 std::pair<SDValue, SDValue> Res =
9013 if (Res.first.getNode()) {
9027bool SelectionDAGBuilder::visitMemPCpyCall(
const CallInst &
I) {
9035 Align Alignment = std::min(DstAlign, SrcAlign);
9044 Root, sdl, Dst, Src,
Size, Alignment,
false,
false,
nullptr,
9048 "** memcpy should not be lowered as TailCall in mempcpy context **");
9066bool SelectionDAGBuilder::visitStrCpyCall(
const CallInst &
I,
bool isStpcpy) {
9067 const Value *Arg0 =
I.getArgOperand(0), *Arg1 =
I.getArgOperand(1);
9070 std::pair<SDValue, SDValue> Res =
9075 if (Res.first.getNode()) {
9089bool SelectionDAGBuilder::visitStrCmpCall(
const CallInst &
I) {
9090 const Value *Arg0 =
I.getArgOperand(0), *Arg1 =
I.getArgOperand(1);
9093 std::pair<SDValue, SDValue> Res =
9098 if (Res.first.getNode()) {
9099 processIntegerCallValue(
I, Res.first,
true);
9112bool SelectionDAGBuilder::visitStrLenCall(
const CallInst &
I) {
9113 const Value *Arg0 =
I.getArgOperand(0);
9116 std::pair<SDValue, SDValue> Res =
9119 if (Res.first.getNode()) {
9120 processIntegerCallValue(
I, Res.first,
false);
9133bool SelectionDAGBuilder::visitStrNLenCall(
const CallInst &
I) {
9134 const Value *Arg0 =
I.getArgOperand(0), *Arg1 =
I.getArgOperand(1);
9137 std::pair<SDValue, SDValue> Res =
9141 if (Res.first.getNode()) {
9142 processIntegerCallValue(
I, Res.first,
false);
9155bool SelectionDAGBuilder::visitUnaryFloatCall(
const CallInst &
I,
9158 if (!
I.onlyReadsMemory())
9162 Flags.copyFMF(cast<FPMathOperator>(
I));
9175bool SelectionDAGBuilder::visitBinaryFloatCall(
const CallInst &
I,
9178 if (!
I.onlyReadsMemory())
9182 Flags.copyFMF(cast<FPMathOperator>(
I));
9191void SelectionDAGBuilder::visitCall(
const CallInst &
I) {
9193 if (
I.isInlineAsm()) {
9201 if (
F->isDeclaration()) {
9203 unsigned IID =
F->getIntrinsicID();
9206 IID =
II->getIntrinsicID(
F);
9209 visitIntrinsicCall(
I, IID);
9218 if (!
I.isNoBuiltin() && !
I.isStrictFP() && !
F->hasLocalLinkage() &&
9224 if (visitMemCmpBCmpCall(
I))
9227 case LibFunc_copysign:
9228 case LibFunc_copysignf:
9229 case LibFunc_copysignl:
9232 if (
I.onlyReadsMemory()) {
9236 LHS.getValueType(), LHS, RHS));
9315 case LibFunc_sqrt_finite:
9316 case LibFunc_sqrtf_finite:
9317 case LibFunc_sqrtl_finite:
9322 case LibFunc_floorf:
9323 case LibFunc_floorl:
9327 case LibFunc_nearbyint:
9328 case LibFunc_nearbyintf:
9329 case LibFunc_nearbyintl:
9346 case LibFunc_roundf:
9347 case LibFunc_roundl:
9352 case LibFunc_truncf:
9353 case LibFunc_truncl:
9370 case LibFunc_exp10f:
9371 case LibFunc_exp10l:
9376 case LibFunc_ldexpf:
9377 case LibFunc_ldexpl:
9381 case LibFunc_memcmp:
9382 if (visitMemCmpBCmpCall(
I))
9385 case LibFunc_mempcpy:
9386 if (visitMemPCpyCall(
I))
9389 case LibFunc_memchr:
9390 if (visitMemChrCall(
I))
9393 case LibFunc_strcpy:
9394 if (visitStrCpyCall(
I,
false))
9397 case LibFunc_stpcpy:
9398 if (visitStrCpyCall(
I,
true))
9401 case LibFunc_strcmp:
9402 if (visitStrCmpCall(
I))
9405 case LibFunc_strlen:
9406 if (visitStrLenCall(
I))
9409 case LibFunc_strnlen:
9410 if (visitStrNLenCall(
I))
9425 assert(!
I.hasOperandBundlesOtherThan(
9426 {LLVMContext::OB_deopt, LLVMContext::OB_funclet,
9427 LLVMContext::OB_cfguardtarget, LLVMContext::OB_preallocated,
9428 LLVMContext::OB_clang_arc_attachedcall, LLVMContext::OB_kcfi,
9429 LLVMContext::OB_convergencectrl}) &&
9430 "Cannot lower calls with arbitrary operand bundles!");
9434 if (
I.hasDeoptState())
9450 const auto *Key = cast<ConstantInt>(PAB->Inputs[0]);
9451 const Value *Discriminator = PAB->Inputs[1];
9453 assert(Key->getType()->isIntegerTy(32) &&
"Invalid ptrauth key");
9454 assert(Discriminator->getType()->isIntegerTy(64) &&
9455 "Invalid ptrauth discriminator");
9459 if (
const auto *CalleeCPA = dyn_cast<ConstantPtrAuth>(CalleeV))
9460 if (CalleeCPA->isKnownCompatibleWith(Key, Discriminator,
9466 assert(!isa<Function>(CalleeV) &&
"invalid direct ptrauth call");
9501 for (
const auto &Code : Codes)
9516 SDISelAsmOperandInfo &MatchingOpInfo,
9518 if (OpInfo.ConstraintVT == MatchingOpInfo.ConstraintVT)
9524 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
9526 OpInfo.ConstraintVT);
9527 std::pair<unsigned, const TargetRegisterClass *> InputRC =
9529 MatchingOpInfo.ConstraintVT);
9530 if ((OpInfo.ConstraintVT.isInteger() !=
9531 MatchingOpInfo.ConstraintVT.isInteger()) ||
9532 (MatchRC.second != InputRC.second)) {
9535 " with a matching output constraint of"
9536 " incompatible type!");
9538 MatchingOpInfo.ConstraintVT = OpInfo.ConstraintVT;
9545 SDISelAsmOperandInfo &OpInfo,
9558 const Value *OpVal = OpInfo.CallOperandVal;
9559 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
9560 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
9576 DL.getPrefTypeAlign(Ty),
false,
9579 Chain = DAG.
getTruncStore(Chain, Location, OpInfo.CallOperand, StackSlot,
9582 OpInfo.CallOperand = StackSlot;
9595static std::optional<unsigned>
9597 SDISelAsmOperandInfo &OpInfo,
9598 SDISelAsmOperandInfo &RefOpInfo) {
9609 return std::nullopt;
9613 unsigned AssignedReg;
9616 &
TRI, RefOpInfo.ConstraintCode, RefOpInfo.ConstraintVT);
9619 return std::nullopt;
9624 const MVT RegVT = *
TRI.legalclasstypes_begin(*RC);
9626 if (OpInfo.ConstraintVT != MVT::Other && RegVT != MVT::Untyped) {
9635 !
TRI.isTypeLegalForClass(*RC, OpInfo.ConstraintVT)) {
9640 if (RegVT.
getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
9645 OpInfo.CallOperand =
9647 OpInfo.ConstraintVT = RegVT;
9651 }
else if (RegVT.
isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
9654 OpInfo.CallOperand =
9656 OpInfo.ConstraintVT = VT;
9663 if (OpInfo.isMatchingInputConstraint())
9664 return std::nullopt;
9666 EVT ValueVT = OpInfo.ConstraintVT;
9667 if (OpInfo.ConstraintVT == MVT::Other)
9671 unsigned NumRegs = 1;
9672 if (OpInfo.ConstraintVT != MVT::Other)
9687 I = std::find(
I, RC->
end(), AssignedReg);
9688 if (
I == RC->
end()) {
9691 return {AssignedReg};
9695 for (; NumRegs; --NumRegs, ++
I) {
9696 assert(
I != RC->
end() &&
"Ran out of registers to allocate!");
9701 OpInfo.AssignedRegs =
RegsForValue(Regs, RegVT, ValueVT);
9702 return std::nullopt;
9707 const std::vector<SDValue> &AsmNodeOperands) {
9710 for (; OperandNo; --OperandNo) {
9712 unsigned OpFlag = AsmNodeOperands[CurOp]->getAsZExtVal();
9715 (
F.isRegDefKind() ||
F.isRegDefEarlyClobberKind() ||
F.isMemKind()) &&
9716 "Skipped past definitions?");
9717 CurOp +=
F.getNumOperandRegisters() + 1;
9728 explicit ExtraFlags(
const CallBase &Call) {
9730 if (
IA->hasSideEffects())
9732 if (
IA->isAlignStack())
9734 if (
Call.isConvergent())
9755 unsigned get()
const {
return Flags; }
9762 if (
auto *GA = dyn_cast<GlobalAddressSDNode>(
Op)) {
9763 auto Fn = dyn_cast_or_null<Function>(GA->getGlobal());
9778void SelectionDAGBuilder::visitInlineAsm(
const CallBase &Call,
9791 bool HasSideEffect =
IA->hasSideEffects();
9792 ExtraFlags ExtraInfo(Call);
9794 for (
auto &
T : TargetConstraints) {
9795 ConstraintOperands.
push_back(SDISelAsmOperandInfo(
T));
9796 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.
back();
9798 if (OpInfo.CallOperandVal)
9799 OpInfo.CallOperand =
getValue(OpInfo.CallOperandVal);
9802 HasSideEffect = OpInfo.hasMemory(TLI);
9811 OpInfo.CallOperand && !isa<ConstantSDNode>(OpInfo.CallOperand))
9814 return emitInlineAsmError(Call,
"constraint '" +
Twine(
T.ConstraintCode) +
9815 "' expects an integer constant "
9818 ExtraInfo.update(
T);
9825 bool EmitEHLabels = isa<InvokeInst>(Call);
9827 assert(EHPadBB &&
"InvokeInst must have an EHPadBB");
9829 bool IsCallBr = isa<CallBrInst>(Call);
9831 if (IsCallBr || EmitEHLabels) {
9840 Chain = lowerStartEH(Chain, EHPadBB, BeginLabel);
9845 IA->collectAsmStrs(AsmStrs);
9848 for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) {
9856 if (OpInfo.hasMatchingInput()) {
9857 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
9888 if (OpInfo.isIndirect &&
isFunction(OpInfo.CallOperand) &&
9891 OpInfo.isIndirect =
false;
9898 !OpInfo.isIndirect) {
9899 assert((OpInfo.isMultipleAlternative ||
9901 "Can only indirectify direct input operands!");
9907 OpInfo.CallOperandVal =
nullptr;
9910 OpInfo.isIndirect =
true;
9916 std::vector<SDValue> AsmNodeOperands;
9917 AsmNodeOperands.push_back(
SDValue());
9924 const MDNode *SrcLoc =
Call.getMetadata(
"srcloc");
9934 for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) {
9936 SDISelAsmOperandInfo &RefOpInfo =
9937 OpInfo.isMatchingInputConstraint()
9938 ? ConstraintOperands[OpInfo.getMatchedOperand()]
9940 const auto RegError =
9945 const char *
RegName =
TRI.getName(*RegError);
9946 emitInlineAsmError(Call,
"register '" +
Twine(
RegName) +
9947 "' allocated for constraint '" +
9948 Twine(OpInfo.ConstraintCode) +
9949 "' does not match required type");
9953 auto DetectWriteToReservedRegister = [&]() {
9956 for (
unsigned Reg : OpInfo.AssignedRegs.Regs) {
9958 TRI.isInlineAsmReadOnlyReg(MF, Reg)) {
9960 emitInlineAsmError(Call,
"write to reserved register '" +
9969 !OpInfo.isMatchingInputConstraint())) &&
9970 "Only address as input operand is allowed.");
9972 switch (OpInfo.Type) {
9978 "Failed to convert memory constraint code to constraint id.");
9982 OpFlags.setMemConstraint(ConstraintID);
9985 AsmNodeOperands.push_back(OpInfo.CallOperand);
9990 if (OpInfo.AssignedRegs.Regs.empty()) {
9992 Call,
"couldn't allocate output register for constraint '" +
9993 Twine(OpInfo.ConstraintCode) +
"'");
9997 if (DetectWriteToReservedRegister())
10002 OpInfo.AssignedRegs.AddInlineAsmOperands(
10011 SDValue InOperandVal = OpInfo.CallOperand;
10013 if (OpInfo.isMatchingInputConstraint()) {
10019 if (
Flag.isRegDefKind() ||
Flag.isRegDefEarlyClobberKind()) {
10020 if (OpInfo.isIndirect) {
10022 emitInlineAsmError(Call,
"inline asm not supported yet: "
10023 "don't know how to handle tied "
10024 "indirect register inputs");
10032 auto *
R = cast<RegisterSDNode>(AsmNodeOperands[CurOp+1]);
10034 MVT RegVT =
R->getSimpleValueType(0);
10038 :
TRI.getMinimalPhysRegClass(TiedReg);
10039 for (
unsigned i = 0, e =
Flag.getNumOperandRegisters(); i != e; ++i)
10046 MatchedRegs.getCopyToRegs(InOperandVal,
DAG, dl, Chain, &Glue, &Call);
10048 OpInfo.getMatchedOperand(), dl,
DAG,
10053 assert(
Flag.isMemKind() &&
"Unknown matching constraint!");
10054 assert(
Flag.getNumOperandRegisters() == 1 &&
10055 "Unexpected number of operands");
10058 Flag.clearMemConstraint();
10059 Flag.setMatchingOp(OpInfo.getMatchedOperand());
10062 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
10073 std::vector<SDValue> Ops;
10078 if (isa<ConstantSDNode>(InOperandVal)) {
10079 emitInlineAsmError(Call,
"value out of range for constraint '" +
10080 Twine(OpInfo.ConstraintCode) +
"'");
10084 emitInlineAsmError(Call,
10085 "invalid operand for inline asm constraint '" +
10086 Twine(OpInfo.ConstraintCode) +
"'");
10099 assert((OpInfo.isIndirect ||
10101 "Operand must be indirect to be a mem!");
10104 "Memory operands expect pointer values");
10109 "Failed to convert memory constraint code to constraint id.");
10113 ResOpType.setMemConstraint(ConstraintID);
10117 AsmNodeOperands.push_back(InOperandVal);
10125 "Failed to convert memory constraint code to constraint id.");
10129 SDValue AsmOp = InOperandVal;
10131 auto *GA = cast<GlobalAddressSDNode>(InOperandVal);
10139 ResOpType.setMemConstraint(ConstraintID);
10141 AsmNodeOperands.push_back(
10144 AsmNodeOperands.push_back(AsmOp);
10150 emitInlineAsmError(Call,
"unknown asm constraint '" +
10151 Twine(OpInfo.ConstraintCode) +
"'");
10156 if (OpInfo.isIndirect) {
10157 emitInlineAsmError(
10158 Call,
"Don't know how to handle indirect register inputs yet "
10159 "for constraint '" +
10160 Twine(OpInfo.ConstraintCode) +
"'");
10165 if (OpInfo.AssignedRegs.Regs.empty()) {
10166 emitInlineAsmError(Call,
10167 "couldn't allocate input reg for constraint '" +
10168 Twine(OpInfo.ConstraintCode) +
"'");
10172 if (DetectWriteToReservedRegister())
10177 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal,
DAG, dl, Chain, &Glue,
10181 0, dl,
DAG, AsmNodeOperands);
10187 if (!OpInfo.AssignedRegs.Regs.empty())
10197 if (Glue.
getNode()) AsmNodeOperands.push_back(Glue);
10201 DAG.
getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
10212 if (
StructType *StructResult = dyn_cast<StructType>(CallResultType))
10213 ResultTypes = StructResult->elements();
10214 else if (!CallResultType->
isVoidTy())
10215 ResultTypes =
ArrayRef(CallResultType);
10217 auto CurResultType = ResultTypes.
begin();
10218 auto handleRegAssign = [&](
SDValue V) {
10219 assert(CurResultType != ResultTypes.
end() &&
"Unexpected value");
10220 assert((*CurResultType)->isSized() &&
"Unexpected unsized type");
10233 if (ResultVT !=
V.getValueType() &&
10236 else if (ResultVT !=
V.getValueType() && ResultVT.
isInteger() &&
10237 V.getValueType().isInteger()) {
10243 assert(ResultVT ==
V.getValueType() &&
"Asm result value mismatch!");
10249 for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) {
10253 if (OpInfo.AssignedRegs.Regs.empty())
10256 switch (OpInfo.ConstraintType) {
10260 Chain, &Glue, &Call);
10272 assert(
false &&
"Unexpected unknown constraint");
10276 if (OpInfo.isIndirect) {
10277 const Value *
Ptr = OpInfo.CallOperandVal;
10278 assert(
Ptr &&
"Expected value CallOperandVal for indirect asm operand");
10284 assert(!
Call.getType()->isVoidTy() &&
"Bad inline asm!");
10287 handleRegAssign(V);
10289 handleRegAssign(Val);
10295 if (!ResultValues.
empty()) {
10296 assert(CurResultType == ResultTypes.
end() &&
10297 "Mismatch in number of ResultTypes");
10299 "Mismatch in number of output operands in asm result");
10307 if (!OutChains.
empty())
10310 if (EmitEHLabels) {
10311 Chain = lowerEndEH(Chain, cast<InvokeInst>(&Call), EHPadBB, BeginLabel);
10315 if (ResultValues.
empty() || HasSideEffect || !OutChains.
empty() || IsCallBr ||
10320void SelectionDAGBuilder::emitInlineAsmError(
const CallBase &Call,
10321 const Twine &Message) {
10330 if (ValueVTs.
empty())
10334 for (
const EVT &VT : ValueVTs)
10340void SelectionDAGBuilder::visitVAStart(
const CallInst &
I) {
10347void SelectionDAGBuilder::visitVAArg(
const VAArgInst &
I) {
10353 DL.getABITypeAlign(
I.getType()).value());
10356 if (
I.getType()->isPointerTy())
10362void SelectionDAGBuilder::visitVAEnd(
const CallInst &
I) {
10369void SelectionDAGBuilder::visitVACopy(
const CallInst &
I) {
10381 std::optional<ConstantRange> CR =
getRange(
I);
10383 if (!CR || CR->isFullSet() || CR->isEmptySet() || CR->isUpperWrapped())
10386 APInt Lo = CR->getUnsignedMin();
10387 if (!
Lo.isMinValue())
10390 APInt Hi = CR->getUnsignedMax();
10391 unsigned Bits = std::max(
Hi.getActiveBits(),
10400 unsigned NumVals =
Op.getNode()->getNumValues();
10407 for (
unsigned I = 1;
I != NumVals; ++
I)
10421 unsigned ArgIdx,
unsigned NumArgs,
SDValue Callee,
Type *ReturnTy,
10424 Args.reserve(NumArgs);
10428 for (
unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs;
10429 ArgI != ArgE; ++ArgI) {
10430 const Value *V = Call->getOperand(ArgI);
10432 assert(!V->getType()->isEmptyTy() &&
"Empty type passed to intrinsic.");
10436 Entry.Ty = V->getType();
10437 Entry.setAttributes(Call, ArgI);
10438 Args.push_back(Entry);
10443 .
setCallee(Call->getCallingConv(), ReturnTy, Callee, std::move(Args),
10472 for (
unsigned I = StartIdx;
I < Call.arg_size();
I++) {
10487void SelectionDAGBuilder::visitStackmap(
const CallInst &CI) {
10521 assert(
ID.getValueType() == MVT::i64);
10552void SelectionDAGBuilder::visitPatchpoint(
const CallBase &CB,
10568 if (
auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
10571 else if (
auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
10573 SDLoc(SymbolicCallee),
10574 SymbolicCallee->getValueType(0));
10584 "Not enough arguments provided to the patchpoint intrinsic");
10587 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
10605 "Expected a callseq node.");
10607 bool HasGlue =
Call->getGluedNode();
10637 unsigned NumCallRegArgs =
Call->getNumOperands() - (HasGlue ? 4 : 3);
10638 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
10647 for (
unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i !=
e; ++i)
10658 if (IsAnyRegCC && HasDef) {
10663 assert(ValueVTs.
size() == 1 &&
"Expected only one return value type.");
10687 if (IsAnyRegCC && HasDef) {
10699void SelectionDAGBuilder::visitVectorReduce(
const CallInst &
I,
10700 unsigned Intrinsic) {
10704 if (
I.arg_size() > 1)
10710 if (
auto *FPMO = dyn_cast<FPMathOperator>(&
I))
10713 switch (Intrinsic) {
10714 case Intrinsic::vector_reduce_fadd:
10722 case Intrinsic::vector_reduce_fmul:
10730 case Intrinsic::vector_reduce_add:
10733 case Intrinsic::vector_reduce_mul:
10736 case Intrinsic::vector_reduce_and:
10739 case Intrinsic::vector_reduce_or:
10742 case Intrinsic::vector_reduce_xor:
10745 case Intrinsic::vector_reduce_smax:
10748 case Intrinsic::vector_reduce_smin:
10751 case Intrinsic::vector_reduce_umax:
10754 case Intrinsic::vector_reduce_umin:
10757 case Intrinsic::vector_reduce_fmax:
10760 case Intrinsic::vector_reduce_fmin:
10763 case Intrinsic::vector_reduce_fmaximum:
10766 case Intrinsic::vector_reduce_fminimum:
10780 Attrs.push_back(Attribute::SExt);
10782 Attrs.push_back(Attribute::ZExt);
10784 Attrs.push_back(Attribute::InReg);
10794std::pair<SDValue, SDValue>
10808 RetTys.
swap(OldRetTys);
10809 Offsets.swap(OldOffsets);
10811 for (
size_t i = 0, e = OldRetTys.
size(); i != e; ++i) {
10812 EVT RetVT = OldRetTys[i];
10816 unsigned RegisterVTByteSZ = RegisterVT.
getSizeInBits() / 8;
10817 RetTys.
append(NumRegs, RegisterVT);
10818 for (
unsigned j = 0; j != NumRegs; ++j)
10831 int DemoteStackIdx = -100;
10842 DL.getAllocaAddrSpace());
10846 Entry.Node = DemoteStackSlot;
10847 Entry.Ty = StackSlotPtrType;
10848 Entry.IsSExt =
false;
10849 Entry.IsZExt =
false;
10850 Entry.IsInReg =
false;
10851 Entry.IsSRet =
true;
10852 Entry.IsNest =
false;
10853 Entry.IsByVal =
false;
10854 Entry.IsByRef =
false;
10855 Entry.IsReturned =
false;
10856 Entry.IsSwiftSelf =
false;
10857 Entry.IsSwiftAsync =
false;
10858 Entry.IsSwiftError =
false;
10859 Entry.IsCFGuardTarget =
false;
10860 Entry.Alignment = Alignment;
10872 for (
unsigned I = 0, E = RetTys.
size();
I != E; ++
I) {
10874 if (NeedsRegBlock) {
10875 Flags.setInConsecutiveRegs();
10876 if (
I == RetTys.
size() - 1)
10877 Flags.setInConsecutiveRegsLast();
10879 EVT VT = RetTys[
I];
10884 for (
unsigned i = 0; i != NumRegs; ++i) {
10886 MyFlags.
Flags = Flags;
10887 MyFlags.
VT = RegisterVT;
10888 MyFlags.
ArgVT = VT;
10893 cast<PointerType>(CLI.
RetTy)->getAddressSpace());
10901 CLI.
Ins.push_back(MyFlags);
10915 CLI.
Ins.push_back(MyFlags);
10923 for (
unsigned i = 0, e = Args.size(); i != e; ++i) {
10927 Type *FinalType = Args[i].Ty;
10928 if (Args[i].IsByVal)
10929 FinalType = Args[i].IndirectType;
10932 for (
unsigned Value = 0, NumValues = ValueVTs.
size();
Value != NumValues;
10937 Args[i].Node.getResNo() +
Value);
10944 Flags.setOrigAlign(OriginalAlignment);
10946 if (Args[i].Ty->isPointerTy()) {
10947 Flags.setPointer();
10948 Flags.setPointerAddrSpace(
10949 cast<PointerType>(Args[i].Ty)->getAddressSpace());
10951 if (Args[i].IsZExt)
10953 if (Args[i].IsSExt)
10955 if (Args[i].IsInReg) {
10959 isa<StructType>(FinalType)) {
10962 Flags.setHvaStart();
10968 if (Args[i].IsSRet)
10970 if (Args[i].IsSwiftSelf)
10971 Flags.setSwiftSelf();
10972 if (Args[i].IsSwiftAsync)
10973 Flags.setSwiftAsync();
10974 if (Args[i].IsSwiftError)
10975 Flags.setSwiftError();
10976 if (Args[i].IsCFGuardTarget)
10977 Flags.setCFGuardTarget();
10978 if (Args[i].IsByVal)
10980 if (Args[i].IsByRef)
10982 if (Args[i].IsPreallocated) {
10983 Flags.setPreallocated();
10991 if (Args[i].IsInAlloca) {
10992 Flags.setInAlloca();
11001 if (Args[i].IsByVal || Args[i].IsInAlloca || Args[i].IsPreallocated) {
11002 unsigned FrameSize =
DL.getTypeAllocSize(Args[i].IndirectType);
11003 Flags.setByValSize(FrameSize);
11006 if (
auto MA = Args[i].Alignment)
11010 }
else if (
auto MA = Args[i].Alignment) {
11013 MemAlign = OriginalAlignment;
11015 Flags.setMemAlign(MemAlign);
11016 if (Args[i].IsNest)
11019 Flags.setInConsecutiveRegs();
11028 if (Args[i].IsSExt)
11030 else if (Args[i].IsZExt)
11035 if (Args[i].IsReturned && !
Op.getValueType().isVector() &&
11040 Args[i].Ty->getPointerAddressSpace())) &&
11041 RetTys.
size() == NumValues &&
"unexpected use of 'returned'");
11054 CLI.
RetZExt == Args[i].IsZExt))
11055 Flags.setReturned();
11061 for (
unsigned j = 0; j != NumParts; ++j) {
11068 j * Parts[j].getValueType().getStoreSize().getKnownMinValue());
11069 if (NumParts > 1 && j == 0)
11073 if (j == NumParts - 1)
11077 CLI.
Outs.push_back(MyFlags);
11078 CLI.
OutVals.push_back(Parts[j]);
11081 if (NeedsRegBlock &&
Value == NumValues - 1)
11082 CLI.
Outs[CLI.
Outs.size() - 1].Flags.setInConsecutiveRegsLast();
11094 "LowerCall didn't return a valid chain!");
11096 "LowerCall emitted a return value for a tail call!");
11098 "LowerCall didn't emit the correct number of values!");
11110 for (
unsigned i = 0, e = CLI.
Ins.size(); i != e; ++i) {
11111 assert(InVals[i].
getNode() &&
"LowerCall emitted a null value!");
11112 assert(
EVT(CLI.
Ins[i].VT) == InVals[i].getValueType() &&
11113 "LowerCall emitted a value with the wrong type!");
11126 assert(PVTs.
size() == 1 &&
"Pointers should fit in one register");
11127 EVT PtrVT = PVTs[0];
11129 unsigned NumValues = RetTys.
size();
11130 ReturnValues.
resize(NumValues);
11136 Flags.setNoUnsignedWrap(
true);
11140 for (
unsigned i = 0; i < NumValues; ++i) {
11147 DemoteStackIdx, Offsets[i]),
11149 ReturnValues[i] = L;
11150 Chains[i] = L.getValue(1);
11157 std::optional<ISD::NodeType> AssertOp;
11162 unsigned CurReg = 0;
11163 for (
EVT VT : RetTys) {
11170 CLI.
DAG, CLI.
DL, &InVals[CurReg], NumRegs, RegisterVT, VT,
nullptr,
11178 if (ReturnValues.
empty())
11184 return std::make_pair(Res, CLI.
Chain);
11201 if (
N->getNumValues() == 1) {
11209 "Lowering returned the wrong number of results!");
11212 for (
unsigned I = 0, E =
N->getNumValues();
I != E; ++
I)
11225 cast<RegisterSDNode>(
Op.getOperand(1))->getReg() != Reg) &&
11226 "Copy from a reg to the same reg!");
11240 ExtendType = PreferredExtendIt->second;
11243 PendingExports.push_back(Chain);
11255 return A->use_empty();
11257 const BasicBlock &Entry =
A->getParent()->front();
11258 for (
const User *U :
A->users())
11259 if (cast<Instruction>(U)->
getParent() != &Entry || isa<SwitchInst>(U))
11267 std::pair<const AllocaInst *, const StoreInst *>>;
11279 enum StaticAllocaInfo {
Unknown, Clobbered, Elidable };
11281 unsigned NumArgs = FuncInfo->
Fn->
arg_size();
11282 StaticAllocas.
reserve(NumArgs * 2);
11284 auto GetInfoIfStaticAlloca = [&](
const Value *V) -> StaticAllocaInfo * {
11287 V = V->stripPointerCasts();
11288 const auto *AI = dyn_cast<AllocaInst>(V);
11289 if (!AI || !AI->isStaticAlloca() || !FuncInfo->
StaticAllocaMap.count(AI))
11292 return &Iter.first->second;
11302 const auto *SI = dyn_cast<StoreInst>(&
I);
11309 if (
I.isDebugOrPseudoInst())
11313 for (
const Use &U :
I.operands()) {
11314 if (StaticAllocaInfo *
Info = GetInfoIfStaticAlloca(U))
11315 *
Info = StaticAllocaInfo::Clobbered;
11321 if (StaticAllocaInfo *
Info = GetInfoIfStaticAlloca(SI->getValueOperand()))
11322 *
Info = StaticAllocaInfo::Clobbered;
11325 const Value *Dst = SI->getPointerOperand()->stripPointerCasts();
11326 StaticAllocaInfo *
Info = GetInfoIfStaticAlloca(Dst);
11329 const AllocaInst *AI = cast<AllocaInst>(Dst);
11332 if (*
Info != StaticAllocaInfo::Unknown)
11340 const Value *Val = SI->getValueOperand()->stripPointerCasts();
11341 const auto *Arg = dyn_cast<Argument>(Val);
11342 if (!Arg || Arg->hasPassPointeeByValueCopyAttr() ||
11343 Arg->getType()->isEmptyTy() ||
11344 DL.getTypeStoreSize(Arg->getType()) !=
11346 !
DL.typeSizeEqualsStoreSize(Arg->getType()) ||
11347 ArgCopyElisionCandidates.
count(Arg)) {
11348 *
Info = StaticAllocaInfo::Clobbered;
11352 LLVM_DEBUG(
dbgs() <<
"Found argument copy elision candidate: " << *AI
11356 *
Info = StaticAllocaInfo::Elidable;
11357 ArgCopyElisionCandidates.
insert({Arg, {AI, SI}});
11362 if (ArgCopyElisionCandidates.
size() == NumArgs)
11376 auto *LNode = dyn_cast<LoadSDNode>(ArgVals[0]);
11379 auto *FINode = dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode());
11386 auto ArgCopyIter = ArgCopyElisionCandidates.
find(&Arg);
11387 assert(ArgCopyIter != ArgCopyElisionCandidates.
end());
11388 const AllocaInst *AI = ArgCopyIter->second.first;
11389 int FixedIndex = FINode->getIndex();
11391 int OldIndex = AllocaIndex;
11395 dbgs() <<
" argument copy elision failed due to bad fixed stack "
11401 LLVM_DEBUG(
dbgs() <<
" argument copy elision failed: alignment of alloca "
11402 "greater than stack argument alignment ("
11403 <<
DebugStr(RequiredAlignment) <<
" vs "
11411 dbgs() <<
"Eliding argument copy from " << Arg <<
" to " << *AI <<
'\n'
11412 <<
" Replacing frame index " << OldIndex <<
" with " << FixedIndex
11418 AllocaIndex = FixedIndex;
11419 ArgCopyElisionFrameIndexMap.
insert({OldIndex, FixedIndex});
11420 for (
SDValue ArgVal : ArgVals)
11424 const StoreInst *SI = ArgCopyIter->second.second;
11425 ElidedArgCopyInstrs.
insert(SI);
11437void SelectionDAGISel::LowerArguments(
const Function &
F) {
11444 if (
F.hasFnAttribute(Attribute::Naked))
11462 Ins.push_back(RetArg);
11470 ArgCopyElisionCandidates);
11474 unsigned ArgNo = Arg.getArgNo();
11477 bool isArgValueUsed = !Arg.use_empty();
11478 unsigned PartBase = 0;
11479 Type *FinalType = Arg.getType();
11480 if (Arg.hasAttribute(Attribute::ByVal))
11481 FinalType = Arg.getParamByValType();
11483 FinalType,
F.getCallingConv(),
F.isVarArg(),
DL);
11484 for (
unsigned Value = 0, NumValues = ValueVTs.
size();
11491 if (Arg.getType()->isPointerTy()) {
11492 Flags.setPointer();
11493 Flags.setPointerAddrSpace(
11494 cast<PointerType>(Arg.getType())->getAddressSpace());
11496 if (Arg.hasAttribute(Attribute::ZExt))
11498 if (Arg.hasAttribute(Attribute::SExt))
11500 if (Arg.hasAttribute(Attribute::InReg)) {
11504 isa<StructType>(Arg.getType())) {
11507 Flags.setHvaStart();
11513 if (Arg.hasAttribute(Attribute::StructRet))
11515 if (Arg.hasAttribute(Attribute::SwiftSelf))
11516 Flags.setSwiftSelf();
11517 if (Arg.hasAttribute(Attribute::SwiftAsync))
11518 Flags.setSwiftAsync();
11519 if (Arg.hasAttribute(Attribute::SwiftError))
11520 Flags.setSwiftError();
11521 if (Arg.hasAttribute(Attribute::ByVal))
11523 if (Arg.hasAttribute(Attribute::ByRef))
11525 if (Arg.hasAttribute(Attribute::InAlloca)) {
11526 Flags.setInAlloca();
11534 if (Arg.hasAttribute(Attribute::Preallocated)) {
11535 Flags.setPreallocated();
11547 const Align OriginalAlignment(
11549 Flags.setOrigAlign(OriginalAlignment);
11552 Type *ArgMemTy =
nullptr;
11553 if (
Flags.isByVal() ||
Flags.isInAlloca() ||
Flags.isPreallocated() ||
11556 ArgMemTy = Arg.getPointeeInMemoryValueType();
11558 uint64_t MemSize =
DL.getTypeAllocSize(ArgMemTy);
11563 if (
auto ParamAlign = Arg.getParamStackAlign())
11564 MemAlign = *ParamAlign;
11565 else if ((ParamAlign = Arg.getParamAlign()))
11566 MemAlign = *ParamAlign;
11569 if (
Flags.isByRef())
11570 Flags.setByRefSize(MemSize);
11572 Flags.setByValSize(MemSize);
11573 }
else if (
auto ParamAlign = Arg.getParamStackAlign()) {
11574 MemAlign = *ParamAlign;
11576 MemAlign = OriginalAlignment;
11578 Flags.setMemAlign(MemAlign);
11580 if (Arg.hasAttribute(Attribute::Nest))
11583 Flags.setInConsecutiveRegs();
11584 if (ArgCopyElisionCandidates.
count(&Arg))
11585 Flags.setCopyElisionCandidate();
11586 if (Arg.hasAttribute(Attribute::Returned))
11587 Flags.setReturned();
11593 for (
unsigned i = 0; i != NumRegs; ++i) {
11598 Flags, RegisterVT, VT, isArgValueUsed, ArgNo,
11600 if (NumRegs > 1 && i == 0)
11601 MyFlags.Flags.setSplit();
11604 MyFlags.Flags.setOrigAlign(
Align(1));
11605 if (i == NumRegs - 1)
11606 MyFlags.Flags.setSplitEnd();
11608 Ins.push_back(MyFlags);
11610 if (NeedsRegBlock &&
Value == NumValues - 1)
11611 Ins[
Ins.size() - 1].Flags.setInConsecutiveRegsLast();
11619 DAG.
getRoot(),
F.getCallingConv(),
F.isVarArg(), Ins, dl, DAG, InVals);
11623 "LowerFormalArguments didn't return a valid chain!");
11625 "LowerFormalArguments didn't emit the correct number of values!");
11627 for (
unsigned i = 0, e =
Ins.size(); i != e; ++i) {
11628 assert(InVals[i].getNode() &&
11629 "LowerFormalArguments emitted a null value!");
11630 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
11631 "LowerFormalArguments emitted a value with the wrong type!");
11648 MVT VT = ValueVTs[0].getSimpleVT();
11650 std::optional<ISD::NodeType> AssertOp;
11653 F.getCallingConv(), AssertOp);
11659 FuncInfo->DemoteRegister = SRetReg;
11661 SDB->DAG.getCopyToReg(NewRoot,
SDB->getCurSDLoc(), SRetReg, ArgValue);
11674 unsigned NumValues = ValueVTs.
size();
11675 if (NumValues == 0)
11678 bool ArgHasUses = !Arg.use_empty();
11682 if (Ins[i].
Flags.isCopyElisionCandidate()) {
11683 unsigned NumParts = 0;
11684 for (
EVT VT : ValueVTs)
11686 F.getCallingConv(), VT);
11690 ArrayRef(&InVals[i], NumParts), ArgHasUses);
11695 bool isSwiftErrorArg =
11697 Arg.hasAttribute(Attribute::SwiftError);
11698 if (!ArgHasUses && !isSwiftErrorArg) {
11699 SDB->setUnusedArgValue(&Arg, InVals[i]);
11703 dyn_cast<FrameIndexSDNode>(InVals[i].
getNode()))
11704 FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex());
11707 for (
unsigned Val = 0; Val != NumValues; ++Val) {
11708 EVT VT = ValueVTs[Val];
11710 F.getCallingConv(), VT);
11717 if (ArgHasUses || isSwiftErrorArg) {
11718 std::optional<ISD::NodeType> AssertOp;
11719 if (Arg.hasAttribute(Attribute::SExt))
11721 else if (Arg.hasAttribute(Attribute::ZExt))
11725 PartVT, VT,
nullptr, NewRoot,
11726 F.getCallingConv(), AssertOp));
11733 if (ArgValues.
empty())
11738 dyn_cast<FrameIndexSDNode>(ArgValues[0].
getNode()))
11739 FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex());
11742 SDB->getCurSDLoc());
11744 SDB->setValue(&Arg, Res);
11757 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
11758 FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex());
11767 unsigned Reg = cast<RegisterSDNode>(Res.
getOperand(1))->getReg();
11779 unsigned Reg = cast<RegisterSDNode>(Res.
getOperand(1))->getReg();
11786 FuncInfo->InitializeRegForValue(&Arg);
11787 SDB->CopyToExportRegsIfNeeded(&Arg);
11791 if (!Chains.
empty()) {
11798 assert(i == InVals.
size() &&
"Argument register count mismatch!");
11802 if (!ArgCopyElisionFrameIndexMap.
empty()) {
11805 auto I = ArgCopyElisionFrameIndexMap.
find(
VI.getStackSlot());
11806 if (
I != ArgCopyElisionFrameIndexMap.
end())
11807 VI.updateStackSlot(
I->second);
11822SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(
const BasicBlock *LLVMBB) {
11830 if (!isa<PHINode>(SuccBB->begin()))
continue;
11835 if (!SuccsHandled.
insert(SuccMBB).second)
11843 for (
const PHINode &PN : SuccBB->phis()) {
11845 if (PN.use_empty())
11849 if (PN.getType()->isEmptyTy())
11853 const Value *PHIOp = PN.getIncomingValueForBlock(LLVMBB);
11855 if (
const auto *
C = dyn_cast<Constant>(PHIOp)) {
11862 if (
auto *CI = dyn_cast<ConstantInt>(
C))
11874 assert(isa<AllocaInst>(PHIOp) &&
11876 "Didn't codegen value into a register!??");
11886 for (
EVT VT : ValueVTs) {
11888 for (
unsigned i = 0; i != NumRegisters; ++i)
11890 std::make_pair(&*
MBBI++, Reg + i));
11891 Reg += NumRegisters;
11911void SelectionDAGBuilder::updateDAGForMaybeTailCall(
SDValue MaybeTC) {
11913 if (MaybeTC.
getNode() !=
nullptr)
11928 unsigned Size =
W.LastCluster -
W.FirstCluster + 1;
11932 if (
Size == 2 &&
W.MBB == SwitchMBB) {
11945 const APInt &SmallValue =
Small.Low->getValue();
11946 const APInt &BigValue =
Big.Low->getValue();
11949 APInt CommonBit = BigValue ^ SmallValue;
11964 addSuccessorWithProb(SwitchMBB,
Small.MBB,
Small.Prob +
Big.Prob);
11966 addSuccessorWithProb(
11967 SwitchMBB, DefaultMBB,
11971 addSuccessorWithProb(SwitchMBB, DefaultMBB);
11994 return a.Prob != b.Prob ?
11996 a.Low->getValue().slt(b.Low->getValue());
12003 if (
I->Prob >
W.LastCluster->Prob)
12005 if (
I->Kind ==
CC_Range &&
I->MBB == NextMBB) {
12016 UnhandledProbs +=
I->Prob;
12020 bool FallthroughUnreachable =
false;
12022 if (
I ==
W.LastCluster) {
12024 Fallthrough = DefaultMBB;
12025 FallthroughUnreachable = isa<UnreachableInst>(
12029 CurMF->
insert(BBI, Fallthrough);
12033 UnhandledProbs -=
I->Prob;
12043 CurMF->
insert(BBI, JumpMBB);
12045 auto JumpProb =
I->Prob;
12046 auto FallthroughProb = UnhandledProbs;
12054 if (*SI == DefaultMBB) {
12055 JumpProb += DefaultProb / 2;
12056 FallthroughProb -= DefaultProb / 2;
12074 if (FallthroughUnreachable) {
12081 addSuccessorWithProb(CurMBB, Fallthrough, FallthroughProb);
12082 addSuccessorWithProb(CurMBB, JumpMBB, JumpProb);
12088 JT->Default = Fallthrough;
12091 if (CurMBB == SwitchMBB) {
12114 BTB->
Prob += DefaultProb / 2;
12118 if (FallthroughUnreachable)
12122 if (CurMBB == SwitchMBB) {
12131 if (
I->Low ==
I->High) {
12146 if (FallthroughUnreachable)
12150 CaseBlock CB(
CC, LHS, RHS, MHS,
I->MBB, Fallthrough, CurMBB,
12153 if (CurMBB == SwitchMBB)
12156 SL->SwitchCases.push_back(CB);
12161 CurMBB = Fallthrough;
12165void SelectionDAGBuilder::splitWorkItem(
SwitchWorkList &WorkList,
12169 assert(
W.FirstCluster->Low->getValue().slt(
W.LastCluster->Low->getValue()) &&
12170 "Clusters not sorted?");
12171 assert(
W.LastCluster -
W.FirstCluster + 1 >= 2 &&
"Too small to split!");
12173 auto [LastLeft, FirstRight, LeftProb, RightProb] =
12174 SL->computeSplitWorkItemInfo(W);
12179 assert(PivotCluster >
W.FirstCluster);
12180 assert(PivotCluster <=
W.LastCluster);
12195 if (FirstLeft == LastLeft && FirstLeft->Kind ==
CC_Range &&
12196 FirstLeft->Low ==
W.GE &&
12197 (FirstLeft->High->getValue() + 1LL) == Pivot->
getValue()) {
12198 LeftMBB = FirstLeft->MBB;
12203 {LeftMBB, FirstLeft, LastLeft,
W.GE, Pivot,
W.DefaultProb / 2});
12212 if (FirstRight == LastRight && FirstRight->Kind ==
CC_Range &&
12213 W.LT && (FirstRight->High->getValue() + 1ULL) ==
W.LT->getValue()) {
12214 RightMBB = FirstRight->MBB;
12219 {RightMBB, FirstRight, LastRight, Pivot,
W.LT,
W.DefaultProb / 2});
12228 if (
W.MBB == SwitchMBB)
12231 SL->SwitchCases.push_back(CB);
12264 unsigned PeeledCaseIndex = 0;
12265 bool SwitchPeeled =
false;
12268 if (
CC.Prob < TopCaseProb)
12270 TopCaseProb =
CC.Prob;
12271 PeeledCaseIndex =
Index;
12272 SwitchPeeled =
true;
12277 LLVM_DEBUG(
dbgs() <<
"Peeled one top case in switch stmt, prob: "
12278 << TopCaseProb <<
"\n");
12288 auto PeeledCaseIt = Clusters.begin() + PeeledCaseIndex;
12290 nullptr,
nullptr, TopCaseProb.
getCompl()};
12291 lowerWorkItem(W,
SI.getCondition(), SwitchMBB, PeeledSwitchMBB);
12293 Clusters.erase(PeeledCaseIt);
12296 dbgs() <<
"Scale the probablity for one cluster, before scaling: "
12297 <<
CC.Prob <<
"\n");
12301 PeeledCaseProb = TopCaseProb;
12302 return PeeledSwitchMBB;
12305void SelectionDAGBuilder::visitSwitch(
const SwitchInst &SI) {
12309 Clusters.reserve(
SI.getNumCases());
12310 for (
auto I :
SI.cases()) {
12329 peelDominantCaseCluster(SI, Clusters, PeeledCaseProb);
12333 if (Clusters.empty()) {
12334 assert(PeeledSwitchMBB == SwitchMBB);
12336 if (DefaultMBB != NextBlock(SwitchMBB)) {
12345 SL->findBitTestClusters(Clusters, &SI);
12348 dbgs() <<
"Case clusters: ";
12355 C.Low->getValue().print(
dbgs(),
true);
12356 if (
C.Low !=
C.High) {
12358 C.High->getValue().print(
dbgs(),
true);
12365 assert(!Clusters.empty());
12369 auto DefaultProb = getEdgeProbability(PeeledSwitchMBB, DefaultMBB);
12376 {PeeledSwitchMBB,
First,
Last,
nullptr,
nullptr, DefaultProb});
12378 while (!WorkList.
empty()) {
12380 unsigned NumClusters =
W.LastCluster -
W.FirstCluster + 1;
12385 splitWorkItem(WorkList, W,
SI.getCondition(), SwitchMBB);
12389 lowerWorkItem(W,
SI.getCondition(), SwitchMBB, DefaultMBB);
12393void SelectionDAGBuilder::visitStepVector(
const CallInst &
I) {
12400void SelectionDAGBuilder::visitVectorReverse(
const CallInst &
I) {
12406 assert(VT ==
V.getValueType() &&
"Malformed vector.reverse!");
12417 for (
unsigned i = 0; i != NumElts; ++i)
12418 Mask.push_back(NumElts - 1 - i);
12423void SelectionDAGBuilder::visitVectorDeinterleave(
const CallInst &
I) {
12454void SelectionDAGBuilder::visitVectorInterleave(
const CallInst &
I) {
12479void SelectionDAGBuilder::visitFreeze(
const FreezeInst &
I) {
12483 unsigned NumValues = ValueVTs.
size();
12484 if (NumValues == 0)
return;
12489 for (
unsigned i = 0; i != NumValues; ++i)
12497void SelectionDAGBuilder::visitVectorSplice(
const CallInst &
I) {
12504 int64_t
Imm = cast<ConstantInt>(
I.getOperand(2))->getSExtValue();
12519 for (
unsigned i = 0; i < NumElts; ++i)
12548 assert(
MI->getOpcode() == TargetOpcode::COPY &&
12549 "start of copy chain MUST be COPY");
12550 Reg =
MI->getOperand(1).getReg();
12551 MI =
MRI.def_begin(Reg)->getParent();
12553 if (
MI->getOpcode() == TargetOpcode::COPY) {
12554 assert(Reg.isVirtual() &&
"expected COPY of virtual register");
12555 Reg =
MI->getOperand(1).getReg();
12556 assert(Reg.isPhysical() &&
"expected COPY of physical register");
12557 MI =
MRI.def_begin(Reg)->getParent();
12560 assert(
MI->getOpcode() == TargetOpcode::INLINEASM_BR &&
12561 "end of copy chain MUST be INLINEASM_BR");
12569void SelectionDAGBuilder::visitCallBrLandingPad(
const CallInst &
I) {
12573 cast<CallBrInst>(
I.getParent()->getUniquePredecessor()->getTerminator());
12585 for (
auto &
T : TargetConstraints) {
12586 SDISelAsmOperandInfo OpInfo(
T);
12594 switch (OpInfo.ConstraintType) {
12602 for (
unsigned &Reg : OpInfo.AssignedRegs.Regs) {
12610 SDValue V = OpInfo.AssignedRegs.getCopyFromRegs(
12613 ResultVTs.
push_back(OpInfo.ConstraintVT);
12622 ResultVTs.
push_back(OpInfo.ConstraintVT);
unsigned const MachineRegisterInfo * MRI
static unsigned getIntrinsicID(const SDNode *N)
static msgpack::DocNode getNode(msgpack::DocNode DN, msgpack::Type Type, MCValue Val)
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Function Alias Analysis Results
Atomic ordering constants.
This file contains the simple types necessary to represent the attributes associated with functions a...
static const Function * getParent(const Value *V)
This file implements the BitVector class.
BlockVerifier::State From
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Analysis containing CSE Info
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static AttributeList getReturnAttrs(FastISel::CallLoweringInfo &CLI)
Returns an AttributeList representing the attributes applied to the return value of the given call.
const HexagonInstrInfo * TII
This file provides various utilities for inspecting and working with the control flow graph in LLVM I...
static void getRegistersForValue(MachineFunction &MF, MachineIRBuilder &MIRBuilder, GISelAsmOperandInfo &OpInfo, GISelAsmOperandInfo &RefOpInfo)
Assign virtual/physical registers for the specified register operand.
This file defines an InstructionCost class that is used when calculating the cost of an instruction,...
static std::optional< ConstantRange > getRange(Value *V, const InstrInfoQuery &IIQ)
Helper method to get range from metadata or attribute.
unsigned const TargetRegisterInfo * TRI
static const Function * getCalledFunction(const Value *V, bool &IsNoBuiltin)
This file provides utility analysis objects describing memory locations.
This file provides utility for Memory Model Relaxation Annotations (MMRAs).
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
Module.h This file contains the declarations for the Module class.
ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))
uint64_t IntrinsicInst * II
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool hasOnlySelectUsers(const Value *Cond)
static SDValue getLoadStackGuard(SelectionDAG &DAG, const SDLoc &DL, SDValue &Chain)
Create a LOAD_STACK_GUARD node, and let it carry the target specific global variable if there exists ...
static void addStackMapLiveVars(const CallBase &Call, unsigned StartIdx, const SDLoc &DL, SmallVectorImpl< SDValue > &Ops, SelectionDAGBuilder &Builder)
Add a stack map intrinsic call's live variable operands to a stackmap or patchpoint target node's ope...
static const unsigned MaxParallelChains
static void getUnderlyingArgRegs(SmallVectorImpl< std::pair< unsigned, TypeSize > > &Regs, const SDValue &N)
static SDValue expandPow(const SDLoc &dl, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const TargetLowering &TLI, SDNodeFlags Flags)
visitPow - Lower a pow intrinsic.
static bool getUniformBase(const Value *Ptr, SDValue &Base, SDValue &Index, ISD::MemIndexType &IndexType, SDValue &Scale, SelectionDAGBuilder *SDB, const BasicBlock *CurBB, uint64_t ElemSize)
static const CallBase * FindPreallocatedCall(const Value *PreallocatedSetup)
Given a @llvm.call.preallocated.setup, return the corresponding preallocated call.
static cl::opt< unsigned > SwitchPeelThreshold("switch-peel-threshold", cl::Hidden, cl::init(66), cl::desc("Set the case probability threshold for peeling the case from a " "switch statement. A value greater than 100 will void this " "optimization"))
static cl::opt< bool > InsertAssertAlign("insert-assert-align", cl::init(true), cl::desc("Insert the experimental `assertalign` node."), cl::ReallyHidden)
static unsigned getISDForVPIntrinsic(const VPIntrinsic &VPIntrin)
static bool handleDanglingVariadicDebugInfo(SelectionDAG &DAG, DILocalVariable *Variable, DebugLoc DL, unsigned Order, SmallVectorImpl< Value * > &Values, DIExpression *Expression)
static unsigned findMatchingInlineAsmOperand(unsigned OperandNo, const std::vector< SDValue > &AsmNodeOperands)
static void patchMatchingInput(const SDISelAsmOperandInfo &OpInfo, SDISelAsmOperandInfo &MatchingOpInfo, SelectionDAG &DAG)
Make sure that the output operand OpInfo and its corresponding input operand MatchingOpInfo have comp...
static void findUnwindDestinations(FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB, BranchProbability Prob, SmallVectorImpl< std::pair< MachineBasicBlock *, BranchProbability > > &UnwindDests)
When an invoke or a cleanupret unwinds to the next EH pad, there are many places it could ultimately ...
static unsigned FixedPointIntrinsicToOpcode(unsigned Intrinsic)
static BranchProbability scaleCaseProbality(BranchProbability CaseProb, BranchProbability PeeledCaseProb)
static SDValue expandExp2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI, SDNodeFlags Flags)
expandExp2 - Lower an exp2 intrinsic.
static SDValue expandDivFix(unsigned Opcode, const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue Scale, SelectionDAG &DAG, const TargetLowering &TLI)
static SDValue getF32Constant(SelectionDAG &DAG, unsigned Flt, const SDLoc &dl)
getF32Constant - Get 32-bit floating point constant.
static SDValue widenVectorToPartType(SelectionDAG &DAG, SDValue Val, const SDLoc &DL, EVT PartVT)
static SDValue expandLog10(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI, SDNodeFlags Flags)
expandLog10 - Lower a log10 intrinsic.
static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &dl, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, const Value *V, std::optional< CallingConv::ID > CallConv)
getCopyToPartsVector - Create a series of nodes that contain the specified value split into legal par...
static void getCopyToParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, const Value *V, std::optional< CallingConv::ID > CallConv=std::nullopt, ISD::NodeType ExtendKind=ISD::ANY_EXTEND)
getCopyToParts - Create a series of nodes that contain the specified value split into legal parts.
static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, SelectionDAGBuilder &Builder)
static SDValue expandLog2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI, SDNodeFlags Flags)
expandLog2 - Lower a log2 intrinsic.
static SDValue getAddressForMemoryInput(SDValue Chain, const SDLoc &Location, SDISelAsmOperandInfo &OpInfo, SelectionDAG &DAG)
Get a direct memory input to behave well as an indirect operand.
static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel)
isOnlyUsedInEntryBlock - If the specified argument is only used in the entry block,...
static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V, const Twine &ErrMsg)
static bool collectInstructionDeps(SmallMapVector< const Instruction *, bool, 8 > *Deps, const Value *V, SmallMapVector< const Instruction *, bool, 8 > *Necessary=nullptr, unsigned Depth=0)
static void findArgumentCopyElisionCandidates(const DataLayout &DL, FunctionLoweringInfo *FuncInfo, ArgCopyElisionMapTy &ArgCopyElisionCandidates)
Scan the entry block of the function in FuncInfo for arguments that look like copies into a local all...
static bool isFunction(SDValue Op)
static SDValue GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, const SDLoc &dl)
GetExponent - Get the exponent:
static Register FollowCopyChain(MachineRegisterInfo &MRI, Register Reg)
static SDValue ExpandPowI(const SDLoc &DL, SDValue LHS, SDValue RHS, SelectionDAG &DAG)
ExpandPowI - Expand a llvm.powi intrinsic.
static void findWasmUnwindDestinations(FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB, BranchProbability Prob, SmallVectorImpl< std::pair< MachineBasicBlock *, BranchProbability > > &UnwindDests)
static SDValue expandLog(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI, SDNodeFlags Flags)
expandLog - Lower a log intrinsic.
static SDValue getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V, SDValue InChain, std::optional< CallingConv::ID > CC=std::nullopt, std::optional< ISD::NodeType > AssertOp=std::nullopt)
getCopyFromParts - Create a value that contains the specified legal parts combined into the value the...
static SDValue getLimitedPrecisionExp2(SDValue t0, const SDLoc &dl, SelectionDAG &DAG)
static SDValue GetSignificand(SelectionDAG &DAG, SDValue Op, const SDLoc &dl)
GetSignificand - Get the significand and build it into a floating-point number with exponent of 1:
static SDValue expandExp(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI, SDNodeFlags Flags)
expandExp - Lower an exp intrinsic.
static const MDNode * getRangeMetadata(const Instruction &I)
static cl::opt< unsigned, true > LimitFPPrecision("limit-float-precision", cl::desc("Generate low-precision inline sequences " "for some float libcalls"), cl::location(LimitFloatPrecision), cl::Hidden, cl::init(0))
static void tryToElideArgumentCopy(FunctionLoweringInfo &FuncInfo, SmallVectorImpl< SDValue > &Chains, DenseMap< int, int > &ArgCopyElisionFrameIndexMap, SmallPtrSetImpl< const Instruction * > &ElidedArgCopyInstrs, ArgCopyElisionMapTy &ArgCopyElisionCandidates, const Argument &Arg, ArrayRef< SDValue > ArgVals, bool &ArgHasUses)
Try to elide argument copies from memory into a local alloca.
static unsigned LimitFloatPrecision
LimitFloatPrecision - Generate low-precision inline sequences for some float libcalls (6,...
static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V, SDValue InChain, std::optional< CallingConv::ID > CC)
getCopyFromPartsVector - Create a value that contains the specified legal parts combined into the val...
static bool InBlock(const Value *V, const BasicBlock *BB)
This file defines the SmallPtrSet class.
This file defines the SmallSet class.
static SymbolRef::Type getType(const Symbol *Sym)
support::ulittle16_t & Lo
support::ulittle16_t & Hi
bool pointsToConstantMemory(const MemoryLocation &Loc, bool OrLocal=false)
Checks whether the given location points to constant memory, or if OrLocal is true whether it points ...
Class for arbitrary precision integers.
APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
bool isNonNegative() const
Determine if this APInt Value is non-negative (>= 0)
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
an instruction to allocate memory on the stack
Align getAlign() const
Return the alignment of the memory that is being allocated by the instruction.
Type * getAllocatedType() const
Return the type that is being allocated by the instruction.
This class represents an incoming formal argument to a Function.
bool hasAttribute(Attribute::AttrKind Kind) const
Check if an argument has a given attribute.
unsigned getArgNo() const
Return the index of this formal argument in its containing function.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
A cache of @llvm.assume calls within a function.
An instruction that atomically checks whether a specified value is in a memory location,...
This class represents the atomic memcpy intrinsic i.e.
an instruction that atomically reads a memory location, combines it with another value,...
@ Min
*p = old <signed v ? old : v
@ UIncWrap
Increment one up to a maximum value.
@ Max
*p = old >signed v ? old : v
@ UMin
*p = old <unsigned v ? old : v
@ FMin
*p = minnum(old, v) minnum matches the behavior of llvm.minnum.
@ UMax
*p = old >unsigned v ? old : v
@ FMax
*p = maxnum(old, v) maxnum matches the behavior of llvm.maxnum.
@ UDecWrap
Decrement one until a minimum value or zero.
static AttributeList get(LLVMContext &C, ArrayRef< std::pair< unsigned, Attribute > > Attrs)
Create an AttributeList with the specified parameters in it.
AttributeSet getRetAttrs() const
The attributes for the ret value are returned.
bool hasFnAttr(Attribute::AttrKind Kind) const
Return true if the attribute exists for the function.
LLVM Basic Block Representation.
const Instruction * getFirstNonPHI() const
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
bool isEntryBlock() const
Return true if this is the entry block of the containing function.
const Function * getParent() const
Return the enclosing method, or null if none.
const Instruction * getFirstNonPHIOrDbg(bool SkipPseudoOp=true) const
Returns a pointer to the first instruction in this block that is not a PHINode or a debug intrinsic,...
const Instruction * getTerminator() const LLVM_READONLY
Returns the terminator instruction if the block is well formed or null if the block is not well forme...
const Instruction & back() const
This class represents a no-op cast from one type to another.
bool test(unsigned Idx) const
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
size_type size() const
size - Returns the number of bits in this bitvector.
The address of a basic block.
Conditional or Unconditional Branch instruction.
Analysis providing branch probability information.
BranchProbability getEdgeProbability(const BasicBlock *Src, unsigned IndexInSuccessors) const
Get an edge's probability, relative to other out-edges of the Src.
bool isEdgeHot(const BasicBlock *Src, const BasicBlock *Dst) const
Test if an edge is hot relative to other out-edges of the Src.
static uint32_t getDenominator()
static BranchProbability getOne()
uint32_t getNumerator() const
uint64_t scale(uint64_t Num) const
Scale a large integer.
BranchProbability getCompl() const
static BranchProbability getZero()
static void normalizeProbabilities(ProbabilityIter Begin, ProbabilityIter End)
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
std::optional< OperandBundleUse > getOperandBundle(StringRef Name) const
Return an operand bundle by name, if present.
CallingConv::ID getCallingConv() const
User::op_iterator arg_begin()
Return the iterator pointing to the beginning of the argument list.
bool isMustTailCall() const
Tests if this call site must be tail call optimized.
bool isIndirectCall() const
Return true if the callsite is an indirect call.
unsigned countOperandBundlesOfType(StringRef Name) const
Return the number of operand bundles with the tag Name attached to this instruction.
Value * getCalledOperand() const
Value * getArgOperand(unsigned i) const
User::op_iterator arg_end()
Return the iterator pointing to the end of the argument list.
bool isConvergent() const
Determine if the invoke is convergent.
FunctionType * getFunctionType() const
unsigned arg_size() const
AttributeList getAttributes() const
Return the parameter attributes for this call.
bool isTailCall() const
Tests if this call site is marked as a tail call.
CallBr instruction, tracking function calls that may not return control but instead transfer it to a ...
This class represents a function call, abstracting a target machine's calling convention.
This class is the base class for the comparison instructions.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
ConstantDataSequential - A vector or array constant whose element type is a simple 1/2/4/8-byte integ...
A constant value that is initialized with an expression using other constant values.
static Constant * getBitCast(Constant *C, Type *Ty, bool OnlyIfReduced=false)
ConstantFP - Floating Point Values [float, double].
This is the shared class of boolean and integer constants.
static ConstantInt * getTrue(LLVMContext &Context)
bool isZero() const
This is just a convenience method to make client code smaller for a common code.
static ConstantInt * getFalse(LLVMContext &Context)
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
const APInt & getValue() const
Return the constant as an APInt value reference.
A signed pointer, in the ptrauth sense.
This class represents a range of values.
uint64_t getZExtValue() const
Constant Vector Declarations.
This is an important base class in LLVM.
This is the common base class for constrained floating point intrinsics.
std::optional< fp::ExceptionBehavior > getExceptionBehavior() const
unsigned getNonMetadataArgCount() const
bool isEntryValue() const
Check if the expression consists of exactly one entry value operand.
static bool fragmentsOverlap(const FragmentInfo &A, const FragmentInfo &B)
Check if fragments overlap between a pair of FragmentInfos.
static DIExpression * appendOpsToArg(const DIExpression *Expr, ArrayRef< uint64_t > Ops, unsigned ArgNo, bool StackValue=false)
Create a copy of Expr by appending the given list of Ops to each instance of the operand DW_OP_LLVM_a...
static std::optional< FragmentInfo > getFragmentInfo(expr_op_iterator Start, expr_op_iterator End)
Retrieve the details of this fragment expression.
uint64_t getNumLocationOperands() const
Return the number of unique location operands referred to (via DW_OP_LLVM_arg) in this expression; th...
static std::optional< DIExpression * > createFragmentExpression(const DIExpression *Expr, unsigned OffsetInBits, unsigned SizeInBits)
Create a DIExpression to describe one part of an aggregate variable that is fragmented across multipl...
static const DIExpression * convertToUndefExpression(const DIExpression *Expr)
Removes all elements from Expr that do not apply to an undef debug value, which includes every operat...
static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...
static DIExpression * prependOpcodes(const DIExpression *Expr, SmallVectorImpl< uint64_t > &Ops, bool StackValue=false, bool EntryValue=false)
Prepend DIExpr with the given opcodes and optionally turn it into a stack value.
bool isValidLocationForIntrinsic(const DILocation *DL) const
Check that a location is valid for this variable.
Base class for variables.
std::optional< uint64_t > getSizeInBits() const
Determines the size of the variable's type.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
const StructLayout * getStructLayout(StructType *Ty) const
Returns a StructLayout object, indicating the alignment of the struct, its size, and the offsets of i...
unsigned getAllocaAddrSpace() const
unsigned getIndexSizeInBits(unsigned AS) const
Size in bits of index used for address calculation in getelementptr.
TypeSize getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type.
Align getPrefTypeAlign(Type *Ty) const
Returns the preferred stack/global alignment for the specified type.
This represents the llvm.dbg.label instruction.
DILabel * getLabel() const
Records a position in IR for a source label (DILabel).
Base class for non-instruction debug metadata records that have positions within IR.
DebugLoc getDebugLoc() const
This represents the llvm.dbg.value instruction.
iterator_range< location_op_iterator > getValues() const
DILocalVariable * getVariable() const
DIExpression * getExpression() const
bool isKillLocation() const
Record of a variable value-assignment, aka a non instruction representation of the dbg....
LocationType getType() const
DIExpression * getExpression() const
Value * getVariableLocationOp(unsigned OpIdx) const
DILocalVariable * getVariable() const
iterator_range< location_op_iterator > location_ops() const
Get the locations corresponding to the variable referenced by the debug info intrinsic.
DILocation * getInlinedAt() const
iterator find(const_arg_type_t< KeyT > Val)
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
void reserve(size_type NumEntries)
Grow the densemap so that it can contain at least NumEntries items before resizing again.
static constexpr ElementCount getFixed(ScalarTy MinVal)
static constexpr ElementCount get(ScalarTy MinVal, bool Scalable)
constexpr bool isScalar() const
Exactly one element.
Class representing an expression and its matching format.
This instruction compares its operands according to the predicate given to the constructor.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
bool allowReassoc() const
Flag queries.
An instruction for ordering other memory operations.
static FixedVectorType * get(Type *ElementType, unsigned NumElts)
This class represents a freeze function that returns random concrete value if an operand is either a ...
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
BranchProbabilityInfo * BPI
Register CreateRegs(const Value *V)
SmallPtrSet< const DbgVariableRecord *, 8 > PreprocessedDVRDeclares
Register DemoteRegister
DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg allocated to hold a pointer to ...
BitVector DescribedArgs
Bitvector with a bit set if corresponding argument is described in ArgDbgValues.
DenseMap< const AllocaInst *, int > StaticAllocaMap
StaticAllocaMap - Keep track of frame indices for fixed sized allocas in the entry block.
int getArgumentFrameIndex(const Argument *A)
getArgumentFrameIndex - Get frame index for the byval argument.
DenseMap< const BasicBlock *, MachineBasicBlock * > MBBMap
MBBMap - A mapping from LLVM basic blocks to their machine code entry.
bool isExportedInst(const Value *V) const
isExportedInst - Return true if the specified value is an instruction exported from its block.
const LiveOutInfo * GetLiveOutRegInfo(Register Reg)
GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the register is a PHI destinat...
Register InitializeRegForValue(const Value *V)
unsigned ExceptionPointerVirtReg
If the current MBB is a landing pad, the exception pointer and exception selector registers are copie...
SmallPtrSet< const DbgDeclareInst *, 8 > PreprocessedDbgDeclares
Collection of dbg.declare instructions handled after argument lowering and before ISel proper.
DenseMap< const Value *, Register > ValueMap
ValueMap - Since we emit code for the function a basic block at a time, we must remember which virtua...
MachineBasicBlock::iterator InsertPt
MBB - The current insert position inside the current block.
MachineBasicBlock * MBB
MBB - The current block.
std::vector< std::pair< MachineInstr *, unsigned > > PHINodesToUpdate
PHINodesToUpdate - A list of phi instructions whose operand list will be updated after processing the...
unsigned ExceptionSelectorVirtReg
SmallVector< MachineInstr *, 8 > ArgDbgValues
ArgDbgValues - A list of DBG_VALUE instructions created during isel for function arguments that are i...
MachineRegisterInfo * RegInfo
Register CreateReg(MVT VT, bool isDivergent=false)
CreateReg - Allocate a single virtual register for the given type.
bool CanLowerReturn
CanLowerReturn - true iff the function's return value can be lowered to registers.
DenseMap< const Value *, ISD::NodeType > PreferredExtendType
Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND) for a value.
Register getCatchPadExceptionPointerVReg(const Value *CPI, const TargetRegisterClass *RC)
Class to represent function types.
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Type * getParamType(unsigned i) const
Parameter type accessors.
Type * getReturnType() const
Data structure describing the variable locations in a function.
const BasicBlock & getEntryBlock() const
Intrinsic::ID getIntrinsicID() const LLVM_READONLY
getIntrinsicID - This method returns the ID number of the specified function, or Intrinsic::not_intri...
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
bool hasGC() const
hasGC/getGC/setGC/clearGC - The name of the garbage collection algorithm to use during code generatio...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Constant * getPersonalityFn() const
Get the personality function associated with this function.
AttributeList getAttributes() const
Return the attribute list for this Function.
bool isIntrinsic() const
isIntrinsic - Returns true if the function's name starts with "llvm.".
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Garbage collection metadata for a single function.
void addStackRoot(int Num, const Constant *Metadata)
addStackRoot - Registers a root that lives on the stack.
an instruction for type-safe pointer arithmetic to access elements of arrays and structs
static StringRef dropLLVMManglingEscape(StringRef Name)
If the given string begins with the GlobalValue name mangling escape character '\1',...
bool hasDLLImportStorageClass() const
Module * getParent()
Get the module that this global value is contained inside of...
This instruction compares its operands according to the predicate given to the constructor.
Indirect Branch Instruction.
This instruction inserts a struct field of array element value into an aggregate value.
const DebugLoc & getDebugLoc() const
Return the debug location for this node as a DebugLoc.
FastMathFlags getFastMathFlags() const LLVM_READONLY
Convenience function for getting all the fast-math flags, which must be an operator which supports th...
AAMDNodes getAAMetadata() const
Returns the AA metadata for this instruction.
@ MIN_INT_BITS
Minimum number of bits that can be specified.
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
This is an important class for using LLVM in a threaded context.
void emitError(uint64_t LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
The landingpad instruction holds all of the information necessary to generate correct exception handl...
An instruction for reading from memory.
This class is used to represent ISD::LOAD nodes.
static LocationSize precise(uint64_t Value)
static constexpr LocationSize beforeOrAfterPointer()
Any location before or after the base pointer (but still within the underlying object).
MCSymbol * createTempSymbol()
Create a temporary symbol with a unique name.
MCSymbol * getOrCreateFrameAllocSymbol(const Twine &FuncName, unsigned Idx)
Gets a symbol that will be defined to the final stack offset of a local variable after codegen.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
uint64_t getScalarSizeInBits() const
@ INVALID_SIMPLE_VALUE_TYPE
unsigned getVectorNumElements() const
bool isVector() const
Return true if this is a vector value type.
bool isInteger() const
Return true if this is an integer or a vector integer type.
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
ElementCount getVectorElementCount() const
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
bool bitsGE(MVT VT) const
Return true if this has no less bits than VT.
bool isScalarInteger() const
Return true if this is an integer, not including vectors.
static MVT getVectorVT(MVT VT, unsigned NumElements)
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
static MVT getIntegerVT(unsigned BitWidth)
void normalizeSuccProbs()
Normalize probabilities of all successors so that the sum of them becomes one.
bool isEHPad() const
Returns true if the block is a landing pad.
void setIsEHCatchretTarget(bool V=true)
Indicates if this is a target block of a catchret.
void setIsCleanupFuncletEntry(bool V=true)
Indicates if this is the entry block of a cleanup funclet.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void setSuccProbability(succ_iterator I, BranchProbability Prob)
Set successor probability of a given iterator.
succ_iterator succ_begin()
std::vector< MachineBasicBlock * >::iterator succ_iterator
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void setIsEHFuncletEntry(bool V=true)
Indicates if this is the entry block of an EH funclet.
void setIsEHScopeEntry(bool V=true)
Indicates if this is the entry block of an EH scope, i.e., the block that that used to have a catchpa...
void setMachineBlockAddressTaken()
Set this block to indicate that its address is used as something other than the target of a terminato...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
void setIsImmutableObjectIndex(int ObjectIdx, bool IsImmutable)
Marks the immutability of an object.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
void setHasPatchPoint(bool s=true)
void setHasStackMap(bool s=true)
bool hasOpaqueSPAdjustment() const
Returns true if the function contains opaque dynamic stack adjustments.
int getStackProtectorIndex() const
Return the index for the stack protector object.
void setStackProtectorIndex(int I)
void setIsAliasedObjectIndex(int ObjectIdx, bool IsAliased)
Set "maybe pointed to by an LLVM IR value" for an object.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
void RemoveStackObject(int ObjectIdx)
Remove or mark dead a statically sized stack object.
void setFunctionContextIndex(int I)
Description of the location of a variable whose Address is valid and unchanging during function execu...
const WinEHFuncInfo * getWinEHFuncInfo() const
getWinEHFuncInfo - Return information about how the current function uses Windows exception handling.
void setCallsUnwindInit(bool b)
bool useDebugInstrRef() const
Returns true if the function's variable locations are tracked with instruction referencing.
void setCallSiteBeginLabel(MCSymbol *BeginLabel, unsigned Site)
Map the begin label for a call site.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
void setHasEHCatchret(bool V)
void setCallsEHReturn(bool b)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
unsigned getTypeIDFor(const GlobalValue *TI)
Return the type id for the specified typeinfo. This is function wide.
MCContext & getContext() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
auto getInStackSlotVariableDbgInfo()
Returns the collection of variables for which we have debug info and that have been assigned a stack ...
void addCodeViewAnnotation(MCSymbol *Label, MDNode *MD)
Record annotations associated with a particular label.
Function & getFunction()
Return the LLVM function that this machine code represents.
MachineModuleInfo & getMMI() const
const MachineBasicBlock & front() const
bool hasEHFunclets() const
void addInvoke(MachineBasicBlock *LandingPad, MCSymbol *BeginLabel, MCSymbol *EndLabel)
Provide the begin and end labels of an invoke style call and associate it with a try landing pad bloc...
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
void erase(iterator MBBI)
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
Representation of each machine instruction.
A description of a memory reference used in the backend.
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MONonTemporal
The memory access is non-temporal.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
This class contains meta information specific to a module.
void setCurrentCallSite(unsigned Site)
Set the call site currently being processed.
unsigned getCurrentCallSite()
Get the call site currently being processed, if any.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
static MachineOperand CreateFI(int Idx)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
ArrayRef< std::pair< MCRegister, Register > > liveins() const
An SDNode that represents everything that will be needed to construct a MachineInstr.
bool contains(const KeyT &Key) const
std::pair< iterator, bool > try_emplace(const KeyT &Key, Ts &&...Args)
Representation for a specific memory location.
static MemoryLocation getAfter(const Value *Ptr, const AAMDNodes &AATags=AAMDNodes())
Return a location that may access any location after Ptr, while remaining within the underlying objec...
A Module instance is used to store all the information related to an LLVM module.
Utility class for integer operators which may exhibit overflow - Add, Sub, Mul, and Shl.
static PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space.
static PointerType * getUnqual(Type *ElementType)
This constructs a pointer to an object of the specified type in the default address space (address sp...
static PoisonValue * get(Type *T)
Static factory methods - Return an 'poison' object of the specified type.
A udiv or sdiv instruction, which can be marked as "exact", indicating that no bits are destroyed.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
static constexpr bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
static constexpr bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Resume the propagation of an exception.
Return a value (possibly void), from a function.
Holds the information from a dbg_label node through SDISel.
static SDDbgOperand fromNode(SDNode *Node, unsigned ResNo)
static SDDbgOperand fromFrameIdx(unsigned FrameIdx)
static SDDbgOperand fromVReg(unsigned VReg)
static SDDbgOperand fromConst(const Value *Const)
Holds the information from a dbg_value node through SDISel.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
iterator_range< value_op_iterator > op_values() const
unsigned getIROrder() const
Return the node ordering.
uint64_t getAsZExtVal() const
Helper method returns the zero-extended integer value of a ConstantSDNode.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
const SDValue & getOperand(unsigned Num) const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
Represents a use of a SDNode.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
TypeSize getValueSizeInBits() const
Returns the size of the value in bits.
const SDValue & getOperand(unsigned i) const
unsigned getResNo() const
get the index which selects a specific result in the SDNode
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
unsigned getOpcode() const
SelectionDAGBuilder - This is the common target-independent lowering implementation that is parameter...
SDValue getValue(const Value *V)
getValue - Return an SDValue for the given Value.
void addDanglingDebugInfo(SmallVectorImpl< Value * > &Values, DILocalVariable *Var, DIExpression *Expr, bool IsVariadic, DebugLoc DL, unsigned Order)
Register a dbg_value which relies on a Value which we have not yet seen.
void visitDbgInfo(const Instruction &I)
void clearDanglingDebugInfo()
Clear the dangling debug information map.
void LowerCallTo(const CallBase &CB, SDValue Callee, bool IsTailCall, bool IsMustTailCall, const BasicBlock *EHPadBB=nullptr, const TargetLowering::PtrAuthInfo *PAI=nullptr)
void clear()
Clear out the current SelectionDAG and the associated state and prepare this SelectionDAGBuilder obje...
void visitBitTestHeader(SwitchCG::BitTestBlock &B, MachineBasicBlock *SwitchBB)
visitBitTestHeader - This function emits necessary code to produce value suitable for "bit tests"
void LowerStatepoint(const GCStatepointInst &I, const BasicBlock *EHPadBB=nullptr)
std::unique_ptr< SDAGSwitchLowering > SL
SDValue lowerRangeToAssertZExt(SelectionDAG &DAG, const Instruction &I, SDValue Op)
bool HasTailCall
This is set to true if a call in the current block has been translated as a tail call.
bool ShouldEmitAsBranches(const std::vector< SwitchCG::CaseBlock > &Cases)
If the set of cases should be emitted as a series of branches, return true.
void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB, BranchProbability TProb, BranchProbability FProb, bool InvertCond)
EmitBranchForMergedCondition - Helper method for FindMergedConditions.
void LowerDeoptimizeCall(const CallInst *CI)
void LowerCallSiteWithDeoptBundle(const CallBase *Call, SDValue Callee, const BasicBlock *EHPadBB)
SwiftErrorValueTracking & SwiftError
Information about the swifterror values used throughout the function.
SDValue getNonRegisterValue(const Value *V)
getNonRegisterValue - Return an SDValue for the given Value, but don't look in FuncInfo....
void CopyValueToVirtualRegister(const Value *V, unsigned Reg, ISD::NodeType ExtendType=ISD::ANY_EXTEND)
DenseMap< MachineBasicBlock *, SmallVector< unsigned, 4 > > LPadToCallSiteMap
Map a landing pad to the call site indexes.
void handleDebugDeclare(Value *Address, DILocalVariable *Variable, DIExpression *Expression, DebugLoc DL)
void visitBitTestCase(SwitchCG::BitTestBlock &BB, MachineBasicBlock *NextMBB, BranchProbability BranchProbToNext, unsigned Reg, SwitchCG::BitTestCase &B, MachineBasicBlock *SwitchBB)
visitBitTestCase - this function produces one "bit test"
bool shouldKeepJumpConditionsTogether(const FunctionLoweringInfo &FuncInfo, const BranchInst &I, Instruction::BinaryOps Opc, const Value *Lhs, const Value *Rhs, TargetLoweringBase::CondMergingParams Params) const
StatepointLoweringState StatepointLowering
State used while lowering a statepoint sequence (gc_statepoint, gc_relocate, and gc_result).
void init(GCFunctionInfo *gfi, AAResults *AA, AssumptionCache *AC, const TargetLibraryInfo *li)
DenseMap< const Constant *, unsigned > ConstantsOut
void populateCallLoweringInfo(TargetLowering::CallLoweringInfo &CLI, const CallBase *Call, unsigned ArgIdx, unsigned NumArgs, SDValue Callee, Type *ReturnTy, AttributeSet RetAttrs, bool IsPatchPoint)
Populate a CallLowerinInfo (into CLI) based on the properties of the call being lowered.
void salvageUnresolvedDbgValue(const Value *V, DanglingDebugInfo &DDI)
For the given dangling debuginfo record, perform last-ditch efforts to resolve the debuginfo to somet...
SmallVector< SDValue, 8 > PendingLoads
Loads are not emitted to the program immediately.
GCFunctionInfo * GFI
Garbage collection metadata for the function.
SDValue getRoot()
Similar to getMemoryRoot, but also flushes PendingConstrainedFP(Strict) items.
void ExportFromCurrentBlock(const Value *V)
ExportFromCurrentBlock - If this condition isn't known to be exported from the current basic block,...
DebugLoc getCurDebugLoc() const
void resolveOrClearDbgInfo()
Evict any dangling debug information, attempting to salvage it first.
std::pair< SDValue, SDValue > lowerInvokable(TargetLowering::CallLoweringInfo &CLI, const BasicBlock *EHPadBB=nullptr)
SDValue getMemoryRoot()
Return the current virtual root of the Selection DAG, flushing any PendingLoad items.
void resolveDanglingDebugInfo(const Value *V, SDValue Val)
If we saw an earlier dbg_value referring to V, generate the debug data structures now that we've seen...
SDLoc getCurSDLoc() const
void visit(const Instruction &I)
void dropDanglingDebugInfo(const DILocalVariable *Variable, const DIExpression *Expr)
If we have dangling debug info that describes Variable, or an overlapping part of variable considerin...
SDValue getCopyFromRegs(const Value *V, Type *Ty)
If there was virtual register allocated for the value V emit CopyFromReg of the specified type Ty.
void CopyToExportRegsIfNeeded(const Value *V)
CopyToExportRegsIfNeeded - If the given value has virtual registers created for it,...
void handleKillDebugValue(DILocalVariable *Var, DIExpression *Expr, DebugLoc DbgLoc, unsigned Order)
Create a record for a kill location debug intrinsic.
void visitJumpTable(SwitchCG::JumpTable &JT)
visitJumpTable - Emit JumpTable node in the current MBB
void visitJumpTableHeader(SwitchCG::JumpTable &JT, SwitchCG::JumpTableHeader &JTH, MachineBasicBlock *SwitchBB)
visitJumpTableHeader - This function emits necessary code to produce index in the JumpTable from swit...
void LowerCallSiteWithPtrAuthBundle(const CallBase &CB, const BasicBlock *EHPadBB)
static const unsigned LowestSDNodeOrder
Lowest valid SDNodeOrder.
void LowerDeoptimizingReturn()
FunctionLoweringInfo & FuncInfo
Information about the function as a whole.
void setValue(const Value *V, SDValue NewN)
void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB, Instruction::BinaryOps Opc, BranchProbability TProb, BranchProbability FProb, bool InvertCond)
const TargetLibraryInfo * LibInfo
bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB)
void visitSPDescriptorParent(StackProtectorDescriptor &SPD, MachineBasicBlock *ParentBB)
Codegen a new tail for a stack protector check ParentMBB which has had its tail spliced into a stack ...
bool handleDebugValue(ArrayRef< const Value * > Values, DILocalVariable *Var, DIExpression *Expr, DebugLoc DbgLoc, unsigned Order, bool IsVariadic)
For a given list of Values, attempt to create and record a SDDbgValue in the SelectionDAG.
SDValue getControlRoot()
Similar to getRoot, but instead of flushing all the PendingLoad items, flush all the PendingExports (...
void UpdateSplitBlock(MachineBasicBlock *First, MachineBasicBlock *Last)
When an MBB was split during scheduling, update the references that need to refer to the last resulti...
SDValue getValueImpl(const Value *V)
getValueImpl - Helper function for getValue and getNonRegisterValue.
void visitSwitchCase(SwitchCG::CaseBlock &CB, MachineBasicBlock *SwitchBB)
visitSwitchCase - Emits the necessary code to represent a single node in the binary search tree resul...
void visitSPDescriptorFailure(StackProtectorDescriptor &SPD)
Codegen the failure basic block for a stack protector check.
std::unique_ptr< FunctionLoweringInfo > FuncInfo
SmallPtrSet< const Instruction *, 4 > ElidedArgCopyInstrs
const TargetLowering * TLI
virtual void emitFunctionEntryCode()
SwiftErrorValueTracking * SwiftError
std::unique_ptr< SelectionDAGBuilder > SDB
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
virtual std::pair< SDValue, SDValue > EmitTargetCodeForStrnlen(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src, SDValue MaxLength, MachinePointerInfo SrcPtrInfo) const
virtual std::pair< SDValue, SDValue > EmitTargetCodeForMemcmp(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const
Emit target-specific code that performs a memcmp/bcmp, in cases where that is faster than a libcall.
virtual std::pair< SDValue, SDValue > EmitTargetCodeForStrcpy(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dest, SDValue Src, MachinePointerInfo DestPtrInfo, MachinePointerInfo SrcPtrInfo, bool isStpcpy) const
Emit target-specific code that performs a strcpy or stpcpy, in cases where that is faster than a libc...
virtual std::pair< SDValue, SDValue > EmitTargetCodeForMemchr(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Src, SDValue Char, SDValue Length, MachinePointerInfo SrcPtrInfo) const
Emit target-specific code that performs a memchr, in cases where that is faster than a libcall.
virtual std::pair< SDValue, SDValue > EmitTargetCodeForStrcmp(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const
Emit target-specific code that performs a strcmp, in cases where that is faster than a libcall.
virtual std::pair< SDValue, SDValue > EmitTargetCodeForStrlen(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src, MachinePointerInfo SrcPtrInfo) const
virtual SDValue EmitTargetCodeForSetTag(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Addr, SDValue Size, MachinePointerInfo DstPtrInfo, bool ZeroData) const
Help to insert SDNodeFlags automatically in transforming.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
SDValue getExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT, unsigned Opcode)
Convert Op, which must be of integer type, to the integer type VT, by either any/sign/zero-extending ...
SDValue getLabelNode(unsigned Opcode, const SDLoc &dl, SDValue Root, MCSymbol *Label)
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
SDValue getMaskedGather(SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType, ISD::LoadExtType ExtTy)
SDValue getAddrSpaceCast(const SDLoc &dl, EVT VT, SDValue Ptr, unsigned SrcAS, unsigned DestAS)
Return an AddrSpaceCastSDNode.
const TargetSubtargetInfo & getSubtarget() const
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
BlockFrequencyInfo * getBFI() const
SDValue getShiftAmountConstant(uint64_t Val, EVT VT, const SDLoc &DL)
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
void ExtractVectorElements(SDValue Op, SmallVectorImpl< SDValue > &Args, unsigned Start=0, unsigned Count=0, EVT EltVT=EVT())
Append the extracted elements from Start to Count out of the vector Op in Args.
SDValue getAtomicMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Value, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo)
SDValue getVScale(const SDLoc &DL, EVT VT, APInt MulImm, bool ConstantFold=true)
Return a node that represents the runtime scaling 'MulImm * RuntimeVL'.
SDValue getPseudoProbeNode(const SDLoc &Dl, SDValue Chain, uint64_t Guid, uint64_t Index, uint32_t Attr)
Creates a PseudoProbeSDNode with function GUID Guid and the index of the block Index it is probing,...
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, const CallInst *CI, std::optional< bool > OverrideTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
SDValue getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, const CallInst *CI, MachinePointerInfo DstPtrInfo, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offs=0, bool isT=false, unsigned TargetFlags=0)
SDValue getStridedLoadVP(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &DL, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false)
SDValue getAtomicCmpSwap(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDVTList VTs, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachineMemOperand *MMO)
Gets a node for an atomic cmpxchg op.
MachineModuleInfo * getMMI() const
SDDbgValue * getVRegDbgValue(DIVariable *Var, DIExpression *Expr, unsigned VReg, bool IsIndirect, const DebugLoc &DL, unsigned O)
Creates a VReg SDDbgValue node.
void ReplaceAllUsesOfValuesWith(const SDValue *From, const SDValue *To, unsigned Num)
Like ReplaceAllUsesOfValueWith, but for multiple values at once.
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
void addMMRAMetadata(const SDNode *Node, MDNode *MMRA)
Set MMRAMetadata to be associated with Node.
SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
SDValue getElementCount(const SDLoc &DL, EVT VT, ElementCount EC, bool ConstantFold=true)
SDValue getGetFPEnv(SDValue Chain, const SDLoc &dl, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO)
SDValue getAssertAlign(const SDLoc &DL, SDValue V, Align A)
Return an AssertAlignSDNode.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getStepVector(const SDLoc &DL, EVT ResVT, const APInt &StepVal)
Returns a vector of type ResVT whose elements contain the linear sequence <0, Step,...
SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO)
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands.
Align getEVTAlign(EVT MemoryVT) const
Compute the default alignment value for the given type.
bool shouldOptForSize() const
SDValue getVPZExtOrTrunc(const SDLoc &DL, EVT VT, SDValue Op, SDValue Mask, SDValue EVL)
Convert a vector-predicated Op, which must be an integer vector, to the vector-type VT,...
const TargetLowering & getTargetLoweringInfo() const
static constexpr unsigned MaxRecursionDepth
SDValue getStridedStoreVP(SDValue Chain, const SDLoc &DL, SDValue Val, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
void AddDbgValue(SDDbgValue *DB, bool isParameter)
Add a dbg_value SDNode.
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
SDValue getGatherVP(SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType)
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
void DeleteNode(SDNode *N)
Remove the specified node from the system.
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
SDDbgValue * getDbgValueList(DIVariable *Var, DIExpression *Expr, ArrayRef< SDDbgOperand > Locs, ArrayRef< SDNode * > Dependencies, bool IsIndirect, const DebugLoc &DL, unsigned O, bool IsVariadic)
Creates a SDDbgValue node from a list of locations.
SDValue getNegative(SDValue Val, const SDLoc &DL, EVT VT)
Create negative operation as (SUB 0, Val).
void setNodeMemRefs(MachineSDNode *N, ArrayRef< MachineMemOperand * > NewMemRefs)
Mutate the specified machine node's memory references to the provided list.
const DataLayout & getDataLayout() const
ProfileSummaryInfo * getPSI() const
SDValue getTargetFrameIndex(int FI, EVT VT)
SDValue getTokenFactor(const SDLoc &DL, SmallVectorImpl< SDValue > &Vals)
Creates a new TokenFactor containing Vals.
const SelectionDAGTargetInfo & getSelectionDAGInfo() const
SDValue getMaskedHistogram(SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType)
SDValue getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, const CallInst *CI, std::optional< bool > OverrideTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
SDDbgLabel * getDbgLabel(DILabel *Label, const DebugLoc &DL, unsigned O)
Creates a SDDbgLabel node.
SDValue getStoreVP(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getMemBasePlusOffset(SDValue Base, TypeSize Offset, const SDLoc &DL, const SDNodeFlags Flags=SDNodeFlags())
Returns sum of the base pointer and offset.
SDValue getGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, bool isTargetGA=false, unsigned TargetFlags=0)
SDValue getVAArg(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue SV, unsigned Align)
VAArg produces a result and token chain, and takes a pointer and a source value as input.
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getMDNode(const MDNode *MD)
Return an MDNodeSDNode which holds an MDNode.
void ReplaceAllUsesWith(SDValue From, SDValue To)
Modify anything using 'From' to use 'To' instead.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getSrcValue(const Value *v)
Construct a node to track a Value* through the backend.
SDValue getSplatVector(EVT VT, const SDLoc &DL, SDValue Op)
SDValue getAtomicMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
MaybeAlign InferPtrAlign(SDValue Ptr) const
Infer alignment of a load / store address.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
SDValue getRegister(unsigned Reg, EVT VT)
void AddDbgLabel(SDDbgLabel *DB)
Add a dbg_label SDNode.
SDValue getBasicBlock(MachineBasicBlock *MBB)
SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or trunca...
SDValue getEHLabel(const SDLoc &dl, SDValue Root, MCSymbol *Label)
SDValue getSetFPEnv(SDValue Chain, const SDLoc &dl, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO)
SDValue getMaskedStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Base, SDValue Offset, SDValue Mask, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
SDValue getExternalSymbol(const char *Sym, EVT VT)
const TargetMachine & getTarget() const
SDValue getPtrExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either truncating it or perform...
SDValue getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncat...
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
SDValue getBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, bool isTarget=false, unsigned TargetFlags=0)
SDValue getLoadVP(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, Align Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, const MDNode *Ranges=nullptr, bool IsExpanding=false)
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDDbgValue * getConstantDbgValue(DIVariable *Var, DIExpression *Expr, const Value *C, const DebugLoc &DL, unsigned O)
Creates a constant SDDbgValue node.
SDValue getScatterVP(SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType)
SDValue getValueType(EVT)
SDValue getTargetConstantFP(double Val, const SDLoc &DL, EVT VT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getFPExtendOrRound(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of float type, to the float type VT, by either extending or rounding (by tr...
SDValue getAtomicMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
SDDbgValue * getFrameIndexDbgValue(DIVariable *Var, DIExpression *Expr, unsigned FI, bool IsIndirect, const DebugLoc &DL, unsigned O)
Creates a FrameIndex SDDbgValue node.
SDValue getJumpTable(int JTI, EVT VT, bool isTarget=false, unsigned TargetFlags=0)
SDValue getVPPtrExtOrTrunc(const SDLoc &DL, EVT VT, SDValue Op, SDValue Mask, SDValue EVL)
Convert a vector-predicated Op, which must be of integer type, to the vector-type integer type VT,...
SDValue getVectorIdxConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
MachineFunction & getMachineFunction() const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
SDValue getPtrExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to extend the Op as a pointer value assuming it was the smaller SrcTy ...
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
const FunctionVarLocs * getFunctionVarLocs() const
Returns the result of the AssignmentTrackingAnalysis pass if it's available, otherwise return nullptr...
SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
SDValue getCondCode(ISD::CondCode Cond)
SDValue getLifetimeNode(bool IsStart, const SDLoc &dl, SDValue Chain, int FrameIndex, int64_t Size, int64_t Offset=-1)
Creates a LifetimeSDNode that starts (IsStart==true) or ends (IsStart==false) the lifetime of the por...
SDValue getObjectPtrOffset(const SDLoc &SL, SDValue Ptr, TypeSize Offset)
Create an add instruction with appropriate flags when used for addressing some offset of an object.
LLVMContext * getContext() const
const SDValue & setRoot(SDValue N)
Set the current root tag of the SelectionDAG.
void addPCSections(const SDNode *Node, MDNode *MD)
Set PCSections to be associated with Node.
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, LocationSize Size=0, const AAMDNodes &AAInfo=AAMDNodes())
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getMCSymbol(MCSymbol *Sym, EVT VT)
SDValue getSetCCVP(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Mask, SDValue EVL)
Helper function to make it easier to build VP_SETCCs if you just have an ISD::CondCode instead of an ...
SDValue CreateStackTemporary(TypeSize Bytes, Align Alignment)
Create a stack temporary based on the size in bytes and the alignment.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
SDDbgValue * getDbgValue(DIVariable *Var, DIExpression *Expr, SDNode *N, unsigned R, bool IsIndirect, const DebugLoc &DL, unsigned O)
Creates a SDDbgValue node.
SDValue getMaskedLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Base, SDValue Offset, SDValue Mask, SDValue Src0, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, ISD::LoadExtType, bool IsExpanding=false)
SDValue getSplat(EVT VT, const SDLoc &DL, SDValue Op)
Returns a node representing a splat of one value into all lanes of the provided vector type.
SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, ArrayRef< int > Mask)
Return an ISD::VECTOR_SHUFFLE node.
SDValue getMaskedScatter(SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType, bool IsTruncating=false)
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
reference emplace_back(ArgTypes &&... Args)
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
void swap(SmallVectorImpl &RHS)
void push_back(const T &Elt)
pointer data()
Return a pointer to the vector's buffer, even if empty().
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Encapsulates all of the information needed to generate a stack protector check, and signals to isel w...
MachineBasicBlock * getSuccessMBB()
MachineBasicBlock * getFailureMBB()
void clear()
Clear the memory usage of this object.
An instruction for storing to memory.
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
constexpr const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
TypeSize getElementOffset(unsigned Idx) const
Class to represent struct types.
void setCurrentVReg(const MachineBasicBlock *MBB, const Value *, Register)
Set the swifterror virtual register in the VRegDefMap for this basic block.
Register getOrCreateVRegUseAt(const Instruction *, const MachineBasicBlock *, const Value *)
Get or create the swifterror value virtual register for a use of a swifterror by an instruction.
Register getOrCreateVRegDefAt(const Instruction *, const MachineBasicBlock *, const Value *)
Get or create the swifterror value virtual register for a def of a swifterror by an instruction.
const Value * getFunctionArg() const
Get the (unique) function argument that was marked swifterror, or nullptr if this function has no swi...
Information about stack frame layout on the target.
virtual TargetStackID::Value getStackIDForScalableVectors() const
Returns the StackID that scalable vectors should be associated with.
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
TargetInstrInfo - Interface to description of machine instruction set.
TargetIntrinsicInfo - Interface to description of machine instruction set.
Provides information about what library functions are available for the current target.
bool hasOptimizedCodeGen(LibFunc F) const
Tests if the function is both available and a candidate for optimized code generation.
bool getLibFunc(StringRef funcName, LibFunc &F) const
Searches for a particular function name.
void setAttributes(const CallBase *Call, unsigned ArgIdx)
Set CallLoweringInfo attribute flags based on a call instruction and called function attributes.
virtual bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT) const
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
EVT getMemValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
virtual bool useStackGuardXorFP() const
If this function returns true, stack protection checks should XOR the frame pointer (or whichever poi...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
virtual bool isLegalScaleForGatherScatter(uint64_t Scale, uint64_t ElemSize) const
virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
virtual CondMergingParams getJumpConditionMergingParams(Instruction::BinaryOps, const Value *, const Value *) const
const TargetMachine & getTargetMachine() const
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
virtual Value * getSDagStackGuard(const Module &M) const
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
virtual unsigned getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const
Return the number of registers that this ValueType will eventually require.
bool isJumpExpensive() const
Return true if Flow Control is an expensive operation that should be avoided.
unsigned getBitWidthForCttzElements(Type *RetTy, ElementCount EC, bool ZeroIsPoison, const ConstantRange *VScaleRange) const
Return the minimum number of bits required to hold the maximum possible number of trailing zero vecto...
virtual bool shouldExtendGSIndex(EVT VT, EVT &EltTy) const
Returns true if the index type for a masked gather/scatter requires extending.
virtual unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
virtual Function * getSSPStackGuardCheck(const Module &M) const
If the target has a standard stack protection check function that performs validation and error handl...
Register getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
LegalizeAction getFixedPointOperationAction(unsigned Op, EVT VT, unsigned Scale) const
Some fixed point operations may be natively supported by the target but only for specific scales.
MachineMemOperand::Flags getAtomicMemOperandFlags(const Instruction &AI, const DataLayout &DL) const
virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *=nullptr) const
Determine if the target supports unaligned memory accesses.
bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const
When splitting a value of the specified type into parts, does the Lo or Hi part come first?...
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const
Returns the type for the shift amount of a shift opcode.
virtual Align getABIAlignmentForCallingConv(Type *ArgTy, const DataLayout &DL) const
Certain targets have context sensitive alignment requirements, where one type has the alignment requi...
virtual bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const
Return true if the @llvm.get.active.lane.mask intrinsic should be expanded using generic code in Sele...
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
MachineMemOperand::Flags getLoadMemOperandFlags(const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC=nullptr, const TargetLibraryInfo *LibInfo=nullptr) const
virtual EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
MVT getProgramPointerTy(const DataLayout &DL) const
Return the type for code pointers, which is determined by the program address space specified through...
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
virtual MVT getFenceOperandTy(const DataLayout &DL) const
Return the type for operands of fence.
virtual bool shouldExpandGetVectorLength(EVT CountVT, unsigned VF, bool IsScalable) const
bool isOperationLegalOrCustom(unsigned Op, EVT VT, bool LegalOnly=false) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
virtual uint64_t getByValTypeAlignment(Type *Ty, const DataLayout &DL) const
Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller paramet...
virtual MVT hasFastEqualityCompare(unsigned NumBits) const
Return the preferred operand type if the target has a quick way to compare integer values of the give...
MachineMemOperand::Flags getStoreMemOperandFlags(const StoreInst &SI, const DataLayout &DL) const
virtual bool shouldExpandCttzElements(EVT VT) const
Return true if the @llvm.experimental.cttz.elts intrinsic should be expanded using generic code in Se...
virtual bool signExtendConstant(const ConstantInt *C) const
Return true if this constant should be sign extended when promoting to a larger type.
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...
virtual Register getExceptionPointerRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception address on entry to an ...
bool supportsUnalignedAtomics() const
Whether the target supports unaligned atomic operations.
std::vector< ArgListEntry > ArgListTy
bool isBeneficialToExpandPowI(int64_t Exponent, bool OptForSize) const
Return true if it is beneficial to expand an @llvm.powi.
MVT getFrameIndexTy(const DataLayout &DL) const
Return the type for frame index, which is determined by the alloca address space specified through th...
virtual Register getExceptionSelectorRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception typeid on entry to a la...
virtual MVT getPointerMemTy(const DataLayout &DL, uint32_t AS=0) const
Return the in-memory pointer type for the given address space, defaults to the pointer type from the ...
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT, bool LegalOnly=false) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
virtual MVT getVPExplicitVectorLengthTy() const
Returns the type to be used for the EVL/AVL operand of VP nodes: ISD::VP_ADD, ISD::VP_SUB,...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual bool supportKCFIBundles() const
Return true if the target supports kcfi operand bundles.
virtual bool supportPtrAuthBundles() const
Return true if the target supports ptrauth operand bundles.
virtual bool supportSwiftError() const
Return true if the target supports swifterror attribute.
virtual SDValue visitMaskedLoad(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, MachineMemOperand *MMO, SDValue &NewLoad, SDValue Ptr, SDValue PassThru, SDValue Mask) const
virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const
virtual bool useLoadStackGuardNode() const
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const
Return the type that should be used to zero or sign extend a zeroext/signext integer return value.
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, MakeLibCallOptions CallOptions, const SDLoc &dl, SDValue Chain=SDValue()) const
Returns a pair of (return value, chain).
virtual InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const
std::vector< AsmOperandInfo > AsmOperandInfoVector
SDValue expandIS_FPCLASS(EVT ResultVT, SDValue Op, FPClassTest Test, SDNodeFlags Flags, const SDLoc &DL, SelectionDAG &DAG) const
Expand check for floating point class.
virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const
This callback is used to prepare for a volatile or atomic load.
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
virtual bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, std::optional< CallingConv::ID > CC) const
Target-specific splitting of values into parts that fit a register storing a legal type.
virtual SDValue joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, std::optional< CallingConv::ID > CC) const
Target-specific combining of register parts into its original value.
virtual SDValue LowerCall(CallLoweringInfo &, SmallVectorImpl< SDValue > &) const
This hook must be implemented to lower calls into the specified DAG.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
virtual SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Glue, const SDLoc &DL, const AsmOperandInfo &OpInfo, SelectionDAG &DAG) const
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
virtual SDValue LowerFormalArguments(SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::InputArg > &, const SDLoc &, SelectionDAG &, SmallVectorImpl< SDValue > &) const
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL, const TargetRegisterInfo *TRI, const CallBase &Call) const
Split up the constraint string from the inline assembly value into the specific constraints and their...
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const
This callback is invoked for operations that are unsupported by the target, which are registered to u...
virtual SDValue LowerReturn(SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::OutputArg > &, const SmallVectorImpl< SDValue > &, const SDLoc &, SelectionDAG &) const
This hook must be implemented to lower outgoing return values, described by the Outs array,...
virtual bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const
For some targets, an LLVM struct type must be broken down into multiple simple types,...
virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const
Determines the constraint code and constraint type to use for the specific AsmOperandInfo,...
virtual void CollectTargetIntrinsicOperands(const CallInst &I, SmallVectorImpl< SDValue > &Ops, SelectionDAG &DAG) const
virtual SDValue visitMaskedStore(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, MachineMemOperand *MMO, SDValue Ptr, SDValue Val, SDValue Mask) const
virtual void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
virtual bool CanLowerReturn(CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const
This hook should be implemented to check whether the return values described by the Outs array can fi...
virtual void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
virtual bool isInlineAsmTargetBranch(const SmallVectorImpl< StringRef > &AsmStrs, unsigned OpNo) const
On x86, return true if the operand with index OpNo is a CALL or JUMP instruction, which can use eithe...
virtual const TargetIntrinsicInfo * getIntrinsicInfo() const
If intrinsic information is available, return it. If not, return null.
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast between SrcAS and DestAS is a noop.
const Triple & getTargetTriple() const
virtual TargetTransformInfo getTargetTransformInfo(const Function &F) const
Return a TargetTransformInfo for a given function.
CodeModel::Model getCodeModel() const
Returns the code model.
CodeGenOptLevel getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
unsigned NoNaNsFPMath
NoNaNsFPMath - This flag is enabled when the -enable-no-nans-fp-math flag is specified on the command...
unsigned EnableFastISel
EnableFastISel - This flag enables fast-path instruction selection which trades away generated code q...
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
FPOpFusion::FPOpFusionMode AllowFPOpFusion
AllowFPOpFusion - This flag is set by the -fp-contract=xxx option.
unsigned getID() const
Return the register class ID number.
iterator begin() const
begin/end - Return all of the registers in this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetFrameLowering * getFrameLowering() const
virtual const TargetInstrInfo * getInstrInfo() const
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
ArchType getArch() const
Get the parsed architecture type of this triple.
bool isPS() const
Tests whether the target is the PS4 or PS5 platform.
bool isWasm() const
Tests whether the target is wasm (32- and 64-bit).
bool isAArch64() const
Tests whether the target is AArch64 (little and big endian).
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
static constexpr TypeSize getFixed(ScalarTy ExactSize)
The instances of the Type class are immutable: once they are created, they are never changed.
bool isVectorTy() const
True if this is an instance of VectorType.
bool isPointerTy() const
True if this is an instance of PointerType.
static IntegerType * getInt1Ty(LLVMContext &C)
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
TypeID
Definitions of all of the base types for the Type system.
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
static Type * getVoidTy(LLVMContext &C)
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
bool isIntegerTy() const
True if this is an instance of IntegerType.
bool isTokenTy() const
Return true if this is 'token'.
bool isFPOrFPVectorTy() const
Return true if this is a FP type or a vector of FP.
bool isVoidTy() const
Return true if this is 'void'.
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
static UndefValue * get(Type *T)
Static factory methods - Return an 'undef' object of the specified type.
This function has undefined behavior.
A Use represents the edge between a Value definition and its users.
Value * getOperand(unsigned i) const
This class represents the va_arg llvm instruction, which returns an argument of the specified type gi...
CmpInst::Predicate getPredicate() const
This is the common base class for vector predication intrinsics.
static std::optional< unsigned > getVectorLengthParamPos(Intrinsic::ID IntrinsicID)
MaybeAlign getPointerAlignment() const
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
bool hasOneUse() const
Return true if there is exactly one use of this value.
iterator_range< user_iterator > users()
LLVMContext & getContext() const
All values hold a context through their type.
StringRef getName() const
Return a constant reference to the value's name.
Base class of all SIMD vector types.
Type * getElementType() const
constexpr ScalarTy getFixedValue() const
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
const ParentTy * getParent() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
@ AnyReg
OBSOLETED - Used for stack based JavaScript calls.
@ AMDGPU_CS_Chain
Used on AMDGPUs to give the middle-end more control over argument placement.
@ X86_VectorCall
MSVC calling convention that passes vectors and vector aggregates in SSE registers.
@ C
The default llvm calling convention, compatible with C.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
@ STRICT_FSETCC
STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used for floating-point operands only.
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
@ SET_FPENV
Sets the current floating-point environment.
@ VECREDUCE_SEQ_FADD
Generic reduction nodes.
@ EH_SJLJ_LONGJMP
OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.longjmp intrinsic.
@ INSERT_SUBVECTOR
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1.
@ BSWAP
Byte Swap and Counting operators.
@ SMULFIX
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
@ ATOMIC_STORE
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
@ RESET_FPENV
Set floating-point environment to default state.
@ ADD
Simple integer binary arithmetic operators.
@ SMULFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
@ SET_FPMODE
Sets the current dynamic floating-point control modes.
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
@ EH_SJLJ_SETUP_DISPATCH
OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) The target initializes the dispatch table here.
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
@ VECREDUCE_FMAX
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
@ FADD
Simple binary floating point operators.
@ VECREDUCE_FMAXIMUM
FMINIMUM/FMAXIMUM nodes propatate NaNs and signed zeroes using the llvm.minimum and llvm....
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
@ RESET_FPMODE
Sets default dynamic floating-point control modes.
@ FPTRUNC_ROUND
FPTRUNC_ROUND - This corresponds to the fptrunc_round intrinsic.
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
@ INIT_TRAMPOLINE
INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic.
@ FLDEXP
FLDEXP - ldexp, inspired by libm (op0 * 2**op1).
@ SDIVFIX
RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on 2 integers with the same width...
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
@ EH_RETURN
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin,...
@ ANNOTATION_LABEL
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
@ SET_ROUNDING
Set rounding mode.
@ SIGN_EXTEND
Conversion operators.
@ PREALLOCATED_SETUP
PREALLOCATED_SETUP - This has 2 operands: an input chain and a SRCVALUE with the preallocated call Va...
@ READSTEADYCOUNTER
READSTEADYCOUNTER - This corresponds to the readfixedcounter intrinsic.
@ ADDROFRETURNADDR
ADDROFRETURNADDR - Represents the llvm.addressofreturnaddress intrinsic.
@ BR
Control flow instructions. These all have token chains.
@ VECREDUCE_FADD
These reductions have relaxed evaluation order semantics, and have a single vector operand.
@ CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
@ SSUBO
Same for subtraction.
@ PREALLOCATED_ARG
PREALLOCATED_ARG - This has 3 operands: an input chain, a SRCVALUE with the preallocated call Value,...
@ BRIND
BRIND - Indirect branch.
@ BR_JT
BR_JT - Jumptable branch.
@ VECTOR_INTERLEAVE
VECTOR_INTERLEAVE(VEC1, VEC2) - Returns two vectors with all input and output vectors having the same...
@ FCANONICALIZE
Returns platform specific canonical encoding of a floating point number.
@ IS_FPCLASS
Performs a check of floating point class property, defined by IEEE-754.
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ ATOMIC_LOAD
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
@ EXTRACT_ELEMENT
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
@ ARITH_FENCE
ARITH_FENCE - This corresponds to a arithmetic fence intrinsic.
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
@ GET_ROUNDING
Returns current rounding mode: -1 Undefined 0 Round to 0 1 Round to nearest, ties to even 2 Round to ...
@ CLEANUPRET
CLEANUPRET - Represents a return from a cleanup block funclet.
@ GET_FPMODE
Reads the current dynamic floating-point control modes.
@ GET_FPENV
Gets the current floating-point environment.
@ SHL
Shift and rotation operations.
@ PtrAuthGlobalAddress
A ptrauth constant.
@ EXTRACT_SUBVECTOR
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
@ EntryToken
EntryToken - This is the marker used to indicate the start of a region.
@ READ_REGISTER
READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on the DAG, which implements the n...
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
@ VSCALE
VSCALE(IMM) - Returns the runtime scaling factor used to calculate the number of elements within a sc...
@ LOCAL_RECOVER
LOCAL_RECOVER - Represents the llvm.localrecover intrinsic.
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
@ UBSANTRAP
UBSANTRAP - Trap with an immediate describing the kind of sanitizer failure.
@ SSHLSAT
RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.
@ SMULO
Same for multiplication.
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
@ VECTOR_REVERSE
VECTOR_REVERSE(VECTOR) - Returns a vector, of the same type as VECTOR, whose elements are shuffled us...
@ SDIVFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ VSELECT
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
@ PCMARKER
PCMARKER - This corresponds to the pcmarker intrinsic.
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
@ EH_DWARF_CFA
EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical Frame Address (CFA),...
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
@ STRICT_FP_ROUND
X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision ...
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ READCYCLECOUNTER
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ TRAP
TRAP - Trapping instruction.
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
@ SCMP
[US]CMP - 3-way comparison of signed or unsigned integers.
@ STRICT_FADD
Constrained versions of the binary floating point operators.
@ FREEZE
FREEZE - FREEZE(VAL) returns an arbitrary value if VAL is UNDEF (or is evaluated to UNDEF),...
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ VECTOR_SPLICE
VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
@ FFREXP
FFREXP - frexp, extract fractional and exponent component of a floating-point value.
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
@ VECTOR_COMPRESS
VECTOR_COMPRESS(Vec, Mask, Passthru) consecutively place vector elements based on mask e....
@ SPONENTRY
SPONENTRY - Represents the llvm.sponentry intrinsic.
@ INLINEASM
INLINEASM - Represents an inline asm block.
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...
@ EH_SJLJ_SETJMP
RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) This corresponds to the eh.sjlj....
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ BRCOND
BRCOND - Conditional branch.
@ CATCHRET
CATCHRET - Represents a return from a catch block funclet.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
@ VECTOR_DEINTERLEAVE
VECTOR_DEINTERLEAVE(VEC1, VEC2) - Returns two vectors with all input and output vectors having the sa...
@ GET_DYNAMIC_AREA_OFFSET
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca.
@ ADJUST_TRAMPOLINE
ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
@ INTRINSIC_W_CHAIN
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
MemIndexType
MemIndexType enum - This enum defines how to interpret MGATHER/SCATTER's index parameter when calcula...
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
bool match(Val *V, const Pattern &P)
specificval_ty m_Specific(const Value *V)
Match if we have a specific specified value.
TwoOps_match< Val_t, Idx_t, Instruction::ExtractElement > m_ExtractElt(const Val_t &Val, const Idx_t &Idx)
Matches ExtractElementInst.
OneUse_match< T > m_OneUse(const T &SubPattern)
auto m_LogicalOr()
Matches L || R where L and R are arbitrary values.
VScaleVal_match m_VScale()
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
auto m_LogicalAnd()
Matches L && R where L and R are arbitrary values.
BinaryOp_match< cst_pred_ty< is_all_ones >, ValTy, Instruction::Xor, true > m_Not(const ValTy &V)
Matches a 'Not' as 'xor V, -1' or 'xor -1, V'.
std::vector< CaseCluster > CaseClusterVector
void sortAndRangeify(CaseClusterVector &Clusters)
Sort Clusters and merge adjacent cases.
CaseClusterVector::iterator CaseClusterIt
std::pair< JumpTableHeader, JumpTable > JumpTableBlock
@ CC_Range
A cluster of adjacent case labels with the same destination, or just one case.
@ CC_JumpTable
A cluster of cases suitable for jump table lowering.
@ CC_BitTests
A cluster of cases suitable for bit test lowering.
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
LocationClass< Ty > location(Ty &L)
@ DW_OP_LLVM_arg
Only used in LLVM metadata.
ExceptionBehavior
Exception behavior used for floating point operations.
@ ebStrict
This corresponds to "fpexcept.strict".
@ ebMayTrap
This corresponds to "fpexcept.maytrap".
@ ebIgnore
This corresponds to "fpexcept.ignore".
NodeAddr< FuncNode * > Func
This is an optimization pass for GlobalISel generic memory operations.
@ Low
Lower the current thread's priority such that it does not affect foreground tasks significantly.
unsigned Log2_32_Ceil(uint32_t Value)
Return the ceil log base 2 of the specified value, 32 if the value is zero.
ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred)
getICmpCondCode - Return the ISD condition code corresponding to the given LLVM IR integer condition ...
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
int popcount(T Value) noexcept
Count the number of set bits in a value.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool isUIntN(unsigned N, uint64_t x)
Checks if an unsigned integer fits into the given (dynamic) bit width.
bool isOnlyUsedInZeroEqualityComparison(const Instruction *CxtI)
SDValue peekThroughBitcasts(SDValue V)
Return the non-bitcasted source operand of V if it exists.
int countr_one(T Value)
Count the number of ones from the least significant bit to the first zero bit.
void diagnoseDontCall(const CallInst &CI)
auto successors(const MachineBasicBlock *BB)
bool isIntOrFPConstant(SDValue V)
Return true if V is either a integer or FP constant.
void append_range(Container &C, Range &&R)
Wrapper function to append range R to container C.
Value * GetPointerBaseWithConstantOffset(Value *Ptr, int64_t &Offset, const DataLayout &DL, bool AllowNonInbounds=true)
Analyze the specified pointer to see if it can be expressed as a base pointer plus a constant offset.
constexpr T alignDown(U Value, V Align, W Skew=0)
Returns the largest unsigned integer less than or equal to Value and is Skew mod Align.
gep_type_iterator gep_type_end(const User *GEP)
ConstantRange getConstantRangeFromMetadata(const MDNode &RangeMD)
Parse out a conservative ConstantRange from !range metadata.
bool isScopedEHPersonality(EHPersonality Pers)
Returns true if this personality uses scope-style EH IR instructions: catchswitch,...
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
llvm::SmallVector< int, 16 > createStrideMask(unsigned Start, unsigned Stride, unsigned VF)
Create a stride shuffle mask.
@ SPF_ABS
Floating point maxnum.
@ SPF_NABS
Absolute value.
@ SPF_FMAXNUM
Floating point minnum.
@ SPF_UMIN
Signed minimum.
@ SPF_UMAX
Signed maximum.
@ SPF_SMAX
Unsigned minimum.
@ SPF_FMINNUM
Unsigned maximum.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
detail::zippy< detail::zip_first, T, U, Args... > zip_first(T &&t, U &&u, Args &&...args)
zip iterator that, for the sake of efficiency, assumes the first iteratee to be the shortest.
void sort(IteratorTy Start, IteratorTy End)
FPClassTest
Floating-point class tests, supported by 'is_fpclass' intrinsic.
SelectPatternResult matchSelectPattern(Value *V, Value *&LHS, Value *&RHS, Instruction::CastOps *CastOp=nullptr, unsigned Depth=0)
Pattern match integer [SU]MIN, [SU]MAX and ABS idioms, returning the kind and providing the out param...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool hasSingleElement(ContainerTy &&C)
Returns true if the given container only contains a single element.
ConstantRange getVScaleRange(const Function *F, unsigned BitWidth)
Determine the possible constant range of vscale with the given bit width, based on the vscale_range f...
ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred)
getFCmpCondCode - Return the ISD condition code corresponding to the given LLVM IR floating-point con...
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
Value * salvageDebugInfoImpl(Instruction &I, uint64_t CurrentLocOps, SmallVectorImpl< uint64_t > &Ops, SmallVectorImpl< Value * > &AdditionalValues)
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
@ Global
Append to llvm.global_dtors.
AtomicOrdering
Atomic ordering for LLVM's memory model.
@ First
Helpers to iterate all locations in the MemoryEffectsBase class.
bool isFuncletEHPersonality(EHPersonality Pers)
Returns true if this is a personality function that invokes handler funclets (which must return to it...
bool isAssignmentTrackingEnabled(const Module &M)
Return true if assignment tracking is enabled for module M.
llvm::SmallVector< int, 16 > createInterleaveMask(unsigned VF, unsigned NumVecs)
Create an interleave shuffle mask.
@ UMin
Unsigned integer min implemented in terms of select(cmp()).
@ Or
Bitwise or logical OR of integers.
@ Mul
Product of integers.
@ And
Bitwise or logical AND of integers.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
@ SPNB_RETURNS_NAN
NaN behavior not applicable.
@ SPNB_RETURNS_OTHER
Given one NaN input, returns the NaN.
@ SPNB_RETURNS_ANY
Given one NaN input, returns the non-NaN.
bool isInTailCallPosition(const CallBase &Call, const TargetMachine &TM, bool ReturnsFirstArg=false)
Test if the given instruction is in a position to be optimized with a tail-call.
DWARFExpression::Operation Op
ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC)
getFCmpCodeWithoutNaN - Given an ISD condition code comparing floats, return the equivalent code if w...
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< EVT > *MemVTs, SmallVectorImpl< TypeSize > *Offsets=nullptr, TypeSize StartingOffset=TypeSize::getZero())
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
bool isAsynchronousEHPersonality(EHPersonality Pers)
Returns true if this personality function catches asynchronous exceptions.
std::optional< RoundingMode > convertStrToRoundingMode(StringRef)
Returns a valid RoundingMode enumerator when given a string that is valid as input in constrained int...
gep_type_iterator gep_type_begin(const User *GEP)
void erase_if(Container &C, UnaryPredicate P)
Provide a container algorithm similar to C++ Library Fundamentals v2's erase_if which is equivalent t...
GlobalValue * ExtractTypeInfo(Value *V)
ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
void getUnderlyingObjects(const Value *V, SmallVectorImpl< const Value * > &Objects, const LoopInfo *LI=nullptr, unsigned MaxLookup=6)
This method is similar to getUnderlyingObject except that it can look through phi and select instruct...
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
bool all_equal(std::initializer_list< T > Values)
Returns true if all Values in the initializer lists are equal or the list.
Constant * ConstantFoldLoadFromConstPtr(Constant *C, Type *Ty, APInt Offset, const DataLayout &DL)
Return the value that a load from C with offset Offset would produce if it is constant and determinab...
unsigned succ_size(const MachineBasicBlock *BB)
unsigned ComputeLinearIndex(Type *Ty, const unsigned *Indices, const unsigned *IndicesEnd, unsigned CurIndex=0)
Compute the linearized index of a member in a nested aggregate/struct/array.
T bit_floor(T Value)
Returns the largest integral power of two no greater than Value if Value is nonzero.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
static const fltSemantics & IEEEsingle() LLVM_READNONE
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
uint64_t getScalarStoreSize() const
bool bitsGT(EVT VT) const
Return true if this has more bits than VT.
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
ElementCount getVectorElementCount() const
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
unsigned getVectorMinNumElements() const
Given a vector type, return the minimum number of elements it contains.
uint64_t getScalarSizeInBits() const
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
bool isFixedLengthVector() const
bool isVector() const
Return true if this is a vector value type.
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
bool bitsGE(EVT VT) const
Return true if this has no less bits than VT.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
bool isScalableVector() const
Return true if this is a vector type where the runtime length is machine dependent.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
EVT changeVectorElementType(EVT EltVT) const
Return a VT for a vector type whose attributes match ourselves with the exception of the element type...
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
EVT getHalfNumVectorElementsVT(LLVMContext &Context) const
bool isInteger() const
Return true if this is an integer or a vector integer type.
void setPointerAddrSpace(unsigned AS)
void setOrigAlign(Align A)
OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...
ConstraintPrefix Type
Type - The basic type of the constraint: input/output/clobber/label.
unsigned countMinLeadingZeros() const
Returns the minimum number of leading zero bits.
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getUnknownStack(MachineFunction &MF)
Stack memory without other information.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Align valueOrOne() const
For convenience, returns a valid alignment or 1 if undefined.
This struct represents the registers (physical or virtual) that a particular set of values is assigne...
SmallVector< unsigned, 4 > Regs
This list holds the registers assigned to the values.
SmallVector< unsigned, 4 > RegCount
This list holds the number of registers for each value.
bool isABIMangled() const
SmallVector< EVT, 4 > ValueVTs
The value types of the values, which may not be legal, and may need be promoted or synthesized from o...
SmallVector< std::pair< unsigned, TypeSize >, 4 > getRegsAndSizes() const
Return a list of registers and their sizes.
void AddInlineAsmOperands(InlineAsm::Kind Code, bool HasMatching, unsigned MatchingIdx, const SDLoc &dl, SelectionDAG &DAG, std::vector< SDValue > &Ops) const
Add this value to the specified inlineasm node operand list.
SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, const SDLoc &dl, SDValue &Chain, SDValue *Glue, const Value *V=nullptr) const
Emit a series of CopyFromReg nodes that copies from this value and returns the result as a ValueVTs v...
SmallVector< MVT, 4 > RegVTs
The value types of the registers.
void getCopyToRegs(SDValue Val, SelectionDAG &DAG, const SDLoc &dl, SDValue &Chain, SDValue *Glue, const Value *V=nullptr, ISD::NodeType PreferredExtendType=ISD::ANY_EXTEND) const
Emit a series of CopyToReg nodes that copies the specified value into the registers specified by this...
std::optional< CallingConv::ID > CallConv
Records if this value needs to be treated in an ABI dependant manner, different to normal type legali...
bool occupiesMultipleRegs() const
Check if the total RegCount is greater than one.
These are IR-level optimization flags that may be propagated to SDNodes.
void copyFMF(const FPMathOperator &FPMO)
Propagate the fast-math-flags from an IR FPMathOperator.
bool hasAllowReassociation() const
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
A MapVector that performs no allocations if smaller than a certain size.
MachineBasicBlock * Default
BranchProbability DefaultProb
MachineBasicBlock * Parent
bool FallthroughUnreachable
MachineBasicBlock * ThisBB
This structure is used to communicate between SelectionDAGBuilder and SDISel for the code generation ...
BranchProbability TrueProb
BranchProbability FalseProb
MachineBasicBlock * TrueBB
MachineBasicBlock * FalseBB
SDLoc DL
The debug location of the instruction this CaseBlock was produced from.
A cluster of case labels.
static CaseCluster range(const ConstantInt *Low, const ConstantInt *High, MachineBasicBlock *MBB, BranchProbability Prob)
This contains information for each constraint that we are lowering.
TargetLowering::ConstraintType ConstraintType
Information about the constraint code, e.g.
This structure contains all information that is necessary for lowering calls.
CallLoweringInfo & setConvergent(bool Value=true)
CallLoweringInfo & setCFIType(const ConstantInt *Type)
SmallVector< ISD::InputArg, 32 > Ins
bool IsPostTypeLegalization
SmallVector< SDValue, 4 > InVals
CallLoweringInfo & setDiscardResult(bool Value=true)
CallLoweringInfo & setIsPatchPoint(bool Value=true)
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
CallLoweringInfo & setTailCall(bool Value=true)
CallLoweringInfo & setIsPreallocated(bool Value=true)
CallLoweringInfo & setConvergenceControlToken(SDValue Token)
SmallVector< ISD::OutputArg, 32 > Outs
SmallVector< SDValue, 32 > OutVals
CallLoweringInfo & setChain(SDValue InChain)
CallLoweringInfo & setPtrAuth(PtrAuthInfo Value)
CallLoweringInfo & setCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList, AttributeSet ResultAttrs={})
This structure is used to pass arguments to makeLibCall function.
MakeLibCallOptions & setDiscardResult(bool Value=true)
This structure contains the information necessary for lowering pointer-authenticating indirect calls.
void addIPToStateRange(const InvokeInst *II, MCSymbol *InvokeBegin, MCSymbol *InvokeEnd)