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TargetLowering.h
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1 //===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file describes how to lower LLVM code to machine code. This has two
11 /// main components:
12 ///
13 /// 1. Which ValueTypes are natively supported by the target.
14 /// 2. Which operations are supported for supported ValueTypes.
15 /// 3. Cost thresholds for alternative implementations of certain operations.
16 ///
17 /// In addition it has a few other components, like information about FP
18 /// immediates.
19 ///
20 //===----------------------------------------------------------------------===//
21 
22 #ifndef LLVM_CODEGEN_TARGETLOWERING_H
23 #define LLVM_CODEGEN_TARGETLOWERING_H
24 
25 #include "llvm/ADT/APInt.h"
26 #include "llvm/ADT/ArrayRef.h"
27 #include "llvm/ADT/DenseMap.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/StringRef.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/CallSite.h"
41 #include "llvm/IR/CallingConv.h"
42 #include "llvm/IR/DataLayout.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/IRBuilder.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instruction.h"
48 #include "llvm/IR/Instructions.h"
49 #include "llvm/IR/Type.h"
50 #include "llvm/MC/MCRegisterInfo.h"
51 #include "llvm/Support/Alignment.h"
53 #include "llvm/Support/Casting.h"
57 #include <algorithm>
58 #include <cassert>
59 #include <climits>
60 #include <cstdint>
61 #include <iterator>
62 #include <map>
63 #include <string>
64 #include <utility>
65 #include <vector>
66 
67 namespace llvm {
68 
69 class BranchProbability;
70 class CCState;
71 class CCValAssign;
72 class Constant;
73 class FastISel;
74 class FunctionLoweringInfo;
75 class GlobalValue;
76 class IntrinsicInst;
77 struct KnownBits;
78 class LLVMContext;
79 class MachineBasicBlock;
80 class MachineFunction;
81 class MachineInstr;
82 class MachineJumpTableInfo;
83 class MachineLoop;
84 class MachineRegisterInfo;
85 class MCContext;
86 class MCExpr;
87 class Module;
88 class TargetRegisterClass;
89 class TargetLibraryInfo;
90 class TargetRegisterInfo;
91 class Value;
92 
93 namespace Sched {
94 
95  enum Preference {
96  None, // No preference
97  Source, // Follow source order.
98  RegPressure, // Scheduling for lowest register pressure.
99  Hybrid, // Scheduling for both latency and register pressure.
100  ILP, // Scheduling for ILP in low register pressure mode.
101  VLIW // Scheduling for VLIW targets.
102  };
103 
104 } // end namespace Sched
105 
106 /// This base class for TargetLowering contains the SelectionDAG-independent
107 /// parts that can be used from the rest of CodeGen.
109 public:
110  /// This enum indicates whether operations are valid for a target, and if not,
111  /// what action should be used to make them valid.
112  enum LegalizeAction : uint8_t {
113  Legal, // The target natively supports this operation.
114  Promote, // This operation should be executed in a larger type.
115  Expand, // Try to expand this to other ops, otherwise use a libcall.
116  LibCall, // Don't try to expand this to other ops, always use a libcall.
117  Custom // Use the LowerOperation hook to implement custom lowering.
118  };
119 
120  /// This enum indicates whether a types are legal for a target, and if not,
121  /// what action should be used to make them valid.
122  enum LegalizeTypeAction : uint8_t {
123  TypeLegal, // The target natively supports this type.
124  TypePromoteInteger, // Replace this integer with a larger one.
125  TypeExpandInteger, // Split this integer into two of half the size.
126  TypeSoftenFloat, // Convert this float to a same size integer type,
127  // if an operation is not supported in target HW.
128  TypeExpandFloat, // Split this float into two of half the size.
129  TypeScalarizeVector, // Replace this one-element vector with its element.
130  TypeSplitVector, // Split this vector into two of half the size.
131  TypeWidenVector, // This vector should be widened into a larger vector.
132  TypePromoteFloat // Replace this float with a larger one.
133  };
134 
135  /// LegalizeKind holds the legalization kind that needs to happen to EVT
136  /// in order to type-legalize it.
137  using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;
138 
139  /// Enum that describes how the target represents true/false values.
141  UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
142  ZeroOrOneBooleanContent, // All bits zero except for bit 0.
143  ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
144  };
145 
146  /// Enum that describes what type of support for selects the target has.
148  ScalarValSelect, // The target supports scalar selects (ex: cmov).
149  ScalarCondVectorVal, // The target supports selects with a scalar condition
150  // and vector values (ex: cmov).
151  VectorMaskSelect // The target supports vector selects with a vector
152  // mask (ex: x86 blends).
153  };
154 
155  /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
156  /// to, if at all. Exists because different targets have different levels of
157  /// support for these atomic instructions, and also have different options
158  /// w.r.t. what they should expand to.
159  enum class AtomicExpansionKind {
160  None, // Don't expand the instruction.
161  LLSC, // Expand the instruction into loadlinked/storeconditional; used
162  // by ARM/AArch64.
163  LLOnly, // Expand the (load) instruction into just a load-linked, which has
164  // greater atomic guarantees than a normal load.
165  CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
166  MaskedIntrinsic, // Use a target-specific intrinsic for the LL/SC loop.
167  };
168 
169  /// Enum that specifies when a multiplication should be expanded.
170  enum class MulExpansionKind {
171  Always, // Always expand the instruction.
172  OnlyLegalOrCustom, // Only expand when the resulting instructions are legal
173  // or custom.
174  };
175 
176  class ArgListEntry {
177  public:
178  Value *Val = nullptr;
180  Type *Ty = nullptr;
181  bool IsSExt : 1;
182  bool IsZExt : 1;
183  bool IsInReg : 1;
184  bool IsSRet : 1;
185  bool IsNest : 1;
186  bool IsByVal : 1;
187  bool IsInAlloca : 1;
188  bool IsReturned : 1;
189  bool IsSwiftSelf : 1;
190  bool IsSwiftError : 1;
191  uint16_t Alignment = 0;
192  Type *ByValType = nullptr;
193 
195  : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
196  IsNest(false), IsByVal(false), IsInAlloca(false), IsReturned(false),
197  IsSwiftSelf(false), IsSwiftError(false) {}
198 
199  void setAttributes(const CallBase *Call, unsigned ArgIdx);
200 
201  void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx) {
202  return setAttributes(cast<CallBase>(CS->getInstruction()), ArgIdx);
203  }
204  };
205  using ArgListTy = std::vector<ArgListEntry>;
206 
207  virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
208  ArgListTy &Args) const {};
209 
211  switch (Content) {
212  case UndefinedBooleanContent:
213  // Extend by adding rubbish bits.
214  return ISD::ANY_EXTEND;
215  case ZeroOrOneBooleanContent:
216  // Extend by adding zero bits.
217  return ISD::ZERO_EXTEND;
218  case ZeroOrNegativeOneBooleanContent:
219  // Extend by copying the sign bit.
220  return ISD::SIGN_EXTEND;
221  }
222  llvm_unreachable("Invalid content kind");
223  }
224 
225  /// NOTE: The TargetMachine owns TLOF.
226  explicit TargetLoweringBase(const TargetMachine &TM);
227  TargetLoweringBase(const TargetLoweringBase &) = delete;
228  TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
229  virtual ~TargetLoweringBase() = default;
230 
231 protected:
232  /// Initialize all of the actions to default values.
233  void initActions();
234 
235 public:
236  const TargetMachine &getTargetMachine() const { return TM; }
237 
238  virtual bool useSoftFloat() const { return false; }
239 
240  /// Return the pointer type for the given address space, defaults to
241  /// the pointer type from the data layout.
242  /// FIXME: The default needs to be removed once all the code is updated.
243  virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
245  }
246 
247  /// Return the in-memory pointer type for the given address space, defaults to
248  /// the pointer type from the data layout. FIXME: The default needs to be
249  /// removed once all the code is updated.
250  MVT getPointerMemTy(const DataLayout &DL, uint32_t AS = 0) const {
252  }
253 
254  /// Return the type for frame index, which is determined by
255  /// the alloca address space specified through the data layout.
256  MVT getFrameIndexTy(const DataLayout &DL) const {
257  return getPointerTy(DL, DL.getAllocaAddrSpace());
258  }
259 
260  /// Return the type for operands of fence.
261  /// TODO: Let fence operands be of i32 type and remove this.
262  virtual MVT getFenceOperandTy(const DataLayout &DL) const {
263  return getPointerTy(DL);
264  }
265 
266  /// EVT is not used in-tree, but is used by out-of-tree target.
267  /// A documentation for this function would be nice...
268  virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
269 
270  EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL,
271  bool LegalTypes = true) const;
272 
273  /// Returns the type to be used for the index operand of:
274  /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
275  /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
276  virtual MVT getVectorIdxTy(const DataLayout &DL) const {
277  return getPointerTy(DL);
278  }
279 
280  virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
281  return true;
282  }
283 
284  /// Return true if it is profitable to convert a select of FP constants into
285  /// a constant pool load whose address depends on the select condition. The
286  /// parameter may be used to differentiate a select with FP compare from
287  /// integer compare.
288  virtual bool reduceSelectOfFPConstantLoads(bool IsFPSetCC) const {
289  return true;
290  }
291 
292  /// Return true if multiple condition registers are available.
294  return HasMultipleConditionRegisters;
295  }
296 
297  /// Return true if the target has BitExtract instructions.
298  bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
299 
300  /// Return the preferred vector type legalization action.
303  // The default action for one element vectors is to scalarize
304  if (VT.getVectorNumElements() == 1)
305  return TypeScalarizeVector;
306  // The default action for an odd-width vector is to widen.
307  if (!VT.isPow2VectorType())
308  return TypeWidenVector;
309  // The default action for other vectors is to promote
310  return TypePromoteInteger;
311  }
312 
313  // There are two general methods for expanding a BUILD_VECTOR node:
314  // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
315  // them together.
316  // 2. Build the vector on the stack and then load it.
317  // If this function returns true, then method (1) will be used, subject to
318  // the constraint that all of the necessary shuffles are legal (as determined
319  // by isShuffleMaskLegal). If this function returns false, then method (2) is
320  // always used. The vector type, and the number of defined values, are
321  // provided.
322  virtual bool
324  unsigned DefinedValues) const {
325  return DefinedValues < 3;
326  }
327 
328  /// Return true if integer divide is usually cheaper than a sequence of
329  /// several shifts, adds, and multiplies for this target.
330  /// The definition of "cheaper" may depend on whether we're optimizing
331  /// for speed or for size.
332  virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
333 
334  /// Return true if the target can handle a standalone remainder operation.
335  virtual bool hasStandaloneRem(EVT VT) const {
336  return true;
337  }
338 
339  /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
340  virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const {
341  // Default behavior is to replace SQRT(X) with X*RSQRT(X).
342  return false;
343  }
344 
345  /// Reciprocal estimate status values used by the functions below.
346  enum ReciprocalEstimate : int {
347  Unspecified = -1,
348  Disabled = 0,
350  };
351 
352  /// Return a ReciprocalEstimate enum value for a square root of the given type
353  /// based on the function's attributes. If the operation is not overridden by
354  /// the function's attributes, "Unspecified" is returned and target defaults
355  /// are expected to be used for instruction selection.
356  int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
357 
358  /// Return a ReciprocalEstimate enum value for a division of the given type
359  /// based on the function's attributes. If the operation is not overridden by
360  /// the function's attributes, "Unspecified" is returned and target defaults
361  /// are expected to be used for instruction selection.
362  int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
363 
364  /// Return the refinement step count for a square root of the given type based
365  /// on the function's attributes. If the operation is not overridden by
366  /// the function's attributes, "Unspecified" is returned and target defaults
367  /// are expected to be used for instruction selection.
368  int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
369 
370  /// Return the refinement step count for a division of the given type based
371  /// on the function's attributes. If the operation is not overridden by
372  /// the function's attributes, "Unspecified" is returned and target defaults
373  /// are expected to be used for instruction selection.
374  int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;
375 
376  /// Returns true if target has indicated at least one type should be bypassed.
377  bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
378 
379  /// Returns map of slow types for division or remainder with corresponding
380  /// fast types
382  return BypassSlowDivWidths;
383  }
384 
385  /// Return true if Flow Control is an expensive operation that should be
386  /// avoided.
387  bool isJumpExpensive() const { return JumpIsExpensive; }
388 
389  /// Return true if selects are only cheaper than branches if the branch is
390  /// unlikely to be predicted right.
392  return PredictableSelectIsExpensive;
393  }
394 
395  /// If a branch or a select condition is skewed in one direction by more than
396  /// this factor, it is very likely to be predicted correctly.
397  virtual BranchProbability getPredictableBranchThreshold() const;
398 
399  /// Return true if the following transform is beneficial:
400  /// fold (conv (load x)) -> (load (conv*)x)
401  /// On architectures that don't natively support some vector loads
402  /// efficiently, casting the load to a smaller vector of larger types and
403  /// loading is more efficient, however, this can be undone by optimizations in
404  /// dag combiner.
405  virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,
406  const SelectionDAG &DAG,
407  const MachineMemOperand &MMO) const {
408  // Don't do if we could do an indexed load on the original type, but not on
409  // the new one.
410  if (!LoadVT.isSimple() || !BitcastVT.isSimple())
411  return true;
412 
413  MVT LoadMVT = LoadVT.getSimpleVT();
414 
415  // Don't bother doing this if it's just going to be promoted again later, as
416  // doing so might interfere with other combines.
417  if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
418  getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
419  return false;
420 
421  bool Fast = false;
422  return allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), BitcastVT,
423  MMO, &Fast) && Fast;
424  }
425 
426  /// Return true if the following transform is beneficial:
427  /// (store (y (conv x)), y*)) -> (store x, (x*))
428  virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT,
429  const SelectionDAG &DAG,
430  const MachineMemOperand &MMO) const {
431  // Default to the same logic as loads.
432  return isLoadBitCastBeneficial(StoreVT, BitcastVT, DAG, MMO);
433  }
434 
435  /// Return true if it is expected to be cheaper to do a store of a non-zero
436  /// vector constant with the given size and type for the address space than to
437  /// store the individual scalar element constants.
438  virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
439  unsigned NumElem,
440  unsigned AddrSpace) const {
441  return false;
442  }
443 
444  /// Allow store merging for the specified type after legalization in addition
445  /// to before legalization. This may transform stores that do not exist
446  /// earlier (for example, stores created from intrinsics).
447  virtual bool mergeStoresAfterLegalization(EVT MemVT) const {
448  return true;
449  }
450 
451  /// Returns if it's reasonable to merge stores to MemVT size.
452  virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
453  const SelectionDAG &DAG) const {
454  return true;
455  }
456 
457  /// Return true if it is cheap to speculate a call to intrinsic cttz.
458  virtual bool isCheapToSpeculateCttz() const {
459  return false;
460  }
461 
462  /// Return true if it is cheap to speculate a call to intrinsic ctlz.
463  virtual bool isCheapToSpeculateCtlz() const {
464  return false;
465  }
466 
467  /// Return true if ctlz instruction is fast.
468  virtual bool isCtlzFast() const {
469  return false;
470  }
471 
472  /// Return true if it is safe to transform an integer-domain bitwise operation
473  /// into the equivalent floating-point operation. This should be set to true
474  /// if the target has IEEE-754-compliant fabs/fneg operations for the input
475  /// type.
476  virtual bool hasBitPreservingFPLogic(EVT VT) const {
477  return false;
478  }
479 
480  /// Return true if it is cheaper to split the store of a merged int val
481  /// from a pair of smaller values into multiple stores.
482  virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {
483  return false;
484  }
485 
486  /// Return if the target supports combining a
487  /// chain like:
488  /// \code
489  /// %andResult = and %val1, #mask
490  /// %icmpResult = icmp %andResult, 0
491  /// \endcode
492  /// into a single machine instruction of a form like:
493  /// \code
494  /// cc = test %register, #mask
495  /// \endcode
496  virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
497  return false;
498  }
499 
500  /// Use bitwise logic to make pairs of compares more efficient. For example:
501  /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
502  /// This should be true when it takes more than one instruction to lower
503  /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on
504  /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
505  virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const {
506  return false;
507  }
508 
509  /// Return the preferred operand type if the target has a quick way to compare
510  /// integer values of the given size. Assume that any legal integer type can
511  /// be compared efficiently. Targets may override this to allow illegal wide
512  /// types to return a vector type if there is support to compare that type.
513  virtual MVT hasFastEqualityCompare(unsigned NumBits) const {
514  MVT VT = MVT::getIntegerVT(NumBits);
515  return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE;
516  }
517 
518  /// Return true if the target should transform:
519  /// (X & Y) == Y ---> (~X & Y) == 0
520  /// (X & Y) != Y ---> (~X & Y) != 0
521  ///
522  /// This may be profitable if the target has a bitwise and-not operation that
523  /// sets comparison flags. A target may want to limit the transformation based
524  /// on the type of Y or if Y is a constant.
525  ///
526  /// Note that the transform will not occur if Y is known to be a power-of-2
527  /// because a mask and compare of a single bit can be handled by inverting the
528  /// predicate, for example:
529  /// (X & 8) == 8 ---> (X & 8) != 0
530  virtual bool hasAndNotCompare(SDValue Y) const {
531  return false;
532  }
533 
534  /// Return true if the target has a bitwise and-not operation:
535  /// X = ~A & B
536  /// This can be used to simplify select or other instructions.
537  virtual bool hasAndNot(SDValue X) const {
538  // If the target has the more complex version of this operation, assume that
539  // it has this operation too.
540  return hasAndNotCompare(X);
541  }
542 
543  /// Return true if the target has a bit-test instruction:
544  /// (X & (1 << Y)) ==/!= 0
545  /// This knowledge can be used to prevent breaking the pattern,
546  /// or creating it if it could be recognized.
547  virtual bool hasBitTest(SDValue X, SDValue Y) const { return false; }
548 
549  /// There are two ways to clear extreme bits (either low or high):
550  /// Mask: x & (-1 << y) (the instcombine canonical form)
551  /// Shifts: x >> y << y
552  /// Return true if the variant with 2 variable shifts is preferred.
553  /// Return false if there is no preference.
555  // By default, let's assume that no one prefers shifts.
556  return false;
557  }
558 
559  /// Return true if it is profitable to fold a pair of shifts into a mask.
560  /// This is usually true on most targets. But some targets, like Thumb1,
561  /// have immediate shift instructions, but no immediate "and" instruction;
562  /// this makes the fold unprofitable.
564  CombineLevel Level) const {
565  return true;
566  }
567 
568  /// Should we tranform the IR-optimal check for whether given truncation
569  /// down into KeptBits would be truncating or not:
570  /// (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits)
571  /// Into it's more traditional form:
572  /// ((%x << C) a>> C) dstcond %x
573  /// Return true if we should transform.
574  /// Return false if there is no preference.
576  unsigned KeptBits) const {
577  // By default, let's assume that no one prefers shifts.
578  return false;
579  }
580 
581  /// Given the pattern
582  /// (X & (C l>>/<< Y)) ==/!= 0
583  /// return true if it should be transformed into:
584  /// ((X <</l>> Y) & C) ==/!= 0
585  /// WARNING: if 'X' is a constant, the fold may deadlock!
586  /// FIXME: we could avoid passing XC, but we can't use isConstOrConstSplat()
587  /// here because it can end up being not linked in.
590  unsigned OldShiftOpcode, unsigned NewShiftOpcode,
591  SelectionDAG &DAG) const {
592  if (hasBitTest(X, Y)) {
593  // One interesting pattern that we'd want to form is 'bit test':
594  // ((1 << Y) & C) ==/!= 0
595  // But we also need to be careful not to try to reverse that fold.
596 
597  // Is this '1 << Y' ?
598  if (OldShiftOpcode == ISD::SHL && CC->isOne())
599  return false; // Keep the 'bit test' pattern.
600 
601  // Will it be '1 << Y' after the transform ?
602  if (XC && NewShiftOpcode == ISD::SHL && XC->isOne())
603  return true; // Do form the 'bit test' pattern.
604  }
605 
606  // If 'X' is a constant, and we transform, then we will immediately
607  // try to undo the fold, thus causing endless combine loop.
608  // So by default, let's assume everyone prefers the fold
609  // iff 'X' is not a constant.
610  return !XC;
611  }
612 
613  /// These two forms are equivalent:
614  /// sub %y, (xor %x, -1)
615  /// add (add %x, 1), %y
616  /// The variant with two add's is IR-canonical.
617  /// Some targets may prefer one to the other.
618  virtual bool preferIncOfAddToSubOfNot(EVT VT) const {
619  // By default, let's assume that everyone prefers the form with two add's.
620  return true;
621  }
622 
623  /// Return true if the target wants to use the optimization that
624  /// turns ext(promotableInst1(...(promotableInstN(load)))) into
625  /// promotedInst1(...(promotedInstN(ext(load)))).
626  bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
627 
628  /// Return true if the target can combine store(extractelement VectorTy,
629  /// Idx).
630  /// \p Cost[out] gives the cost of that transformation when this is true.
631  virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
632  unsigned &Cost) const {
633  return false;
634  }
635 
636  /// Return true if inserting a scalar into a variable element of an undef
637  /// vector is more efficiently handled by splatting the scalar instead.
638  virtual bool shouldSplatInsEltVarIndex(EVT) const {
639  return false;
640  }
641 
642  /// Return true if target always beneficiates from combining into FMA for a
643  /// given value type. This must typically return false on targets where FMA
644  /// takes more cycles to execute than FADD.
645  virtual bool enableAggressiveFMAFusion(EVT VT) const {
646  return false;
647  }
648 
649  /// Return the ValueType of the result of SETCC operations.
650  virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
651  EVT VT) const;
652 
653  /// Return the ValueType for comparison libcalls. Comparions libcalls include
654  /// floating point comparion calls, and Ordered/Unordered check calls on
655  /// floating point numbers.
656  virtual
657  MVT::SimpleValueType getCmpLibcallReturnType() const;
658 
659  /// For targets without i1 registers, this gives the nature of the high-bits
660  /// of boolean values held in types wider than i1.
661  ///
662  /// "Boolean values" are special true/false values produced by nodes like
663  /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
664  /// Not to be confused with general values promoted from i1. Some cpus
665  /// distinguish between vectors of boolean and scalars; the isVec parameter
666  /// selects between the two kinds. For example on X86 a scalar boolean should
667  /// be zero extended from i1, while the elements of a vector of booleans
668  /// should be sign extended from i1.
669  ///
670  /// Some cpus also treat floating point types the same way as they treat
671  /// vectors instead of the way they treat scalars.
672  BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
673  if (isVec)
674  return BooleanVectorContents;
675  return isFloat ? BooleanFloatContents : BooleanContents;
676  }
677 
679  return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
680  }
681 
682  /// Return target scheduling preference.
684  return SchedPreferenceInfo;
685  }
686 
687  /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
688  /// for different nodes. This function returns the preference (or none) for
689  /// the given node.
691  return Sched::None;
692  }
693 
694  /// Return the register class that should be used for the specified value
695  /// type.
696  virtual const TargetRegisterClass *getRegClassFor(MVT VT, bool isDivergent = false) const {
697  (void)isDivergent;
698  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
699  assert(RC && "This value type is not natively supported!");
700  return RC;
701  }
702 
703  /// Allows target to decide about the register class of the
704  /// specific value that is live outside the defining block.
705  /// Returns true if the value needs uniform register class.
707  const Value *) const {
708  return false;
709  }
710 
711  /// Return the 'representative' register class for the specified value
712  /// type.
713  ///
714  /// The 'representative' register class is the largest legal super-reg
715  /// register class for the register class of the value type. For example, on
716  /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
717  /// register class is GR64 on x86_64.
718  virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
719  const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
720  return RC;
721  }
722 
723  /// Return the cost of the 'representative' register class for the specified
724  /// value type.
725  virtual uint8_t getRepRegClassCostFor(MVT VT) const {
726  return RepRegClassCostForVT[VT.SimpleTy];
727  }
728 
729  /// Return true if SHIFT instructions should be expanded to SHIFT_PARTS
730  /// instructions, and false if a library call is preferred (e.g for code-size
731  /// reasons).
732  virtual bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const {
733  return true;
734  }
735 
736  /// Return true if the target has native support for the specified value type.
737  /// This means that it has a register that directly holds it without
738  /// promotions or expansions.
739  bool isTypeLegal(EVT VT) const {
740  assert(!VT.isSimple() ||
741  (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
742  return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
743  }
744 
746  /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
747  /// that indicates how instruction selection should deal with the type.
748  LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE];
749 
750  public:
752  std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
753  TypeLegal);
754  }
755 
757  return ValueTypeActions[VT.SimpleTy];
758  }
759 
761  ValueTypeActions[VT.SimpleTy] = Action;
762  }
763  };
764 
766  return ValueTypeActions;
767  }
768 
769  /// Return how we should legalize values of this type, either it is already
770  /// legal (return 'Legal') or we need to promote it to a larger type (return
771  /// 'Promote'), or we need to expand it into multiple registers of smaller
772  /// integer type (return 'Expand'). 'Custom' is not an option.
774  return getTypeConversion(Context, VT).first;
775  }
777  return ValueTypeActions.getTypeAction(VT);
778  }
779 
780  /// For types supported by the target, this is an identity function. For
781  /// types that must be promoted to larger types, this returns the larger type
782  /// to promote to. For integer types that are larger than the largest integer
783  /// register, this contains one step in the expansion to get to the smaller
784  /// register. For illegal floating point types, this returns the integer type
785  /// to transform to.
786  EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
787  return getTypeConversion(Context, VT).second;
788  }
789 
790  /// For types supported by the target, this is an identity function. For
791  /// types that must be expanded (i.e. integer types that are larger than the
792  /// largest integer register or illegal floating point types), this returns
793  /// the largest legal type it will be expanded to.
794  EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
795  assert(!VT.isVector());
796  while (true) {
797  switch (getTypeAction(Context, VT)) {
798  case TypeLegal:
799  return VT;
800  case TypeExpandInteger:
801  VT = getTypeToTransformTo(Context, VT);
802  break;
803  default:
804  llvm_unreachable("Type is not legal nor is it to be expanded!");
805  }
806  }
807  }
808 
809  /// Vector types are broken down into some number of legal first class types.
810  /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
811  /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
812  /// turns into 4 EVT::i32 values with both PPC and X86.
813  ///
814  /// This method returns the number of registers needed, and the VT for each
815  /// register. It also returns the VT and quantity of the intermediate values
816  /// before they are promoted/expanded.
817  unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
818  EVT &IntermediateVT,
819  unsigned &NumIntermediates,
820  MVT &RegisterVT) const;
821 
822  /// Certain targets such as MIPS require that some types such as vectors are
823  /// always broken down into scalars in some contexts. This occurs even if the
824  /// vector type is legal.
826  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
827  unsigned &NumIntermediates, MVT &RegisterVT) const {
828  return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
829  RegisterVT);
830  }
831 
832  struct IntrinsicInfo {
833  unsigned opc = 0; // target opcode
834  EVT memVT; // memory VT
835 
836  // value representing memory location
838 
839  int offset = 0; // offset off of ptrVal
840  unsigned size = 0; // the size of the memory location
841  // (taken from memVT if zero)
842  MaybeAlign align = Align(1); // alignment
843 
845  IntrinsicInfo() = default;
846  };
847 
848  /// Given an intrinsic, checks if on the target the intrinsic will need to map
849  /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
850  /// true and store the intrinsic information into the IntrinsicInfo that was
851  /// passed to the function.
852  virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
853  MachineFunction &,
854  unsigned /*Intrinsic*/) const {
855  return false;
856  }
857 
858  /// Returns true if the target can instruction select the specified FP
859  /// immediate natively. If false, the legalizer will materialize the FP
860  /// immediate as a load from a constant pool.
861  virtual bool isFPImmLegal(const APFloat & /*Imm*/, EVT /*VT*/,
862  bool ForCodeSize = false) const {
863  return false;
864  }
865 
866  /// Targets can use this to indicate that they only support *some*
867  /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
868  /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
869  /// legal.
870  virtual bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const {
871  return true;
872  }
873 
874  /// Returns true if the operation can trap for the value type.
875  ///
876  /// VT must be a legal type. By default, we optimistically assume most
877  /// operations don't trap except for integer divide and remainder.
878  virtual bool canOpTrap(unsigned Op, EVT VT) const;
879 
880  /// Similar to isShuffleMaskLegal. Targets can use this to indicate if there
881  /// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a
882  /// constant pool entry.
883  virtual bool isVectorClearMaskLegal(ArrayRef<int> /*Mask*/,
884  EVT /*VT*/) const {
885  return false;
886  }
887 
888  /// Return how this operation should be treated: either it is legal, needs to
889  /// be promoted to a larger size, needs to be expanded to some other code
890  /// sequence, or the target has a custom expander for it.
891  LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
892  if (VT.isExtended()) return Expand;
893  // If a target-specific SDNode requires legalization, require the target
894  // to provide custom legalization for it.
895  if (Op >= array_lengthof(OpActions[0])) return Custom;
896  return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
897  }
898 
899  /// Custom method defined by each target to indicate if an operation which
900  /// may require a scale is supported natively by the target.
901  /// If not, the operation is illegal.
902  virtual bool isSupportedFixedPointOperation(unsigned Op, EVT VT,
903  unsigned Scale) const {
904  return false;
905  }
906 
907  /// Some fixed point operations may be natively supported by the target but
908  /// only for specific scales. This method allows for checking
909  /// if the width is supported by the target for a given operation that may
910  /// depend on scale.
912  unsigned Scale) const {
913  auto Action = getOperationAction(Op, VT);
914  if (Action != Legal)
915  return Action;
916 
917  // This operation is supported in this type but may only work on specific
918  // scales.
919  bool Supported;
920  switch (Op) {
921  default:
922  llvm_unreachable("Unexpected fixed point operation.");
923  case ISD::SMULFIX:
924  case ISD::SMULFIXSAT:
925  case ISD::UMULFIX:
926  Supported = isSupportedFixedPointOperation(Op, VT, Scale);
927  break;
928  }
929 
930  return Supported ? Action : Expand;
931  }
932 
933  // If Op is a strict floating-point operation, return the result
934  // of getOperationAction for the equivalent non-strict operation.
936  unsigned EqOpc;
937  switch (Op) {
938  default: llvm_unreachable("Unexpected FP pseudo-opcode");
939  case ISD::STRICT_FADD: EqOpc = ISD::FADD; break;
940  case ISD::STRICT_FSUB: EqOpc = ISD::FSUB; break;
941  case ISD::STRICT_FMUL: EqOpc = ISD::FMUL; break;
942  case ISD::STRICT_FDIV: EqOpc = ISD::FDIV; break;
943  case ISD::STRICT_FREM: EqOpc = ISD::FREM; break;
944  case ISD::STRICT_FSQRT: EqOpc = ISD::FSQRT; break;
945  case ISD::STRICT_FPOW: EqOpc = ISD::FPOW; break;
946  case ISD::STRICT_FPOWI: EqOpc = ISD::FPOWI; break;
947  case ISD::STRICT_FMA: EqOpc = ISD::FMA; break;
948  case ISD::STRICT_FSIN: EqOpc = ISD::FSIN; break;
949  case ISD::STRICT_FCOS: EqOpc = ISD::FCOS; break;
950  case ISD::STRICT_FEXP: EqOpc = ISD::FEXP; break;
951  case ISD::STRICT_FEXP2: EqOpc = ISD::FEXP2; break;
952  case ISD::STRICT_FLOG: EqOpc = ISD::FLOG; break;
953  case ISD::STRICT_FLOG10: EqOpc = ISD::FLOG10; break;
954  case ISD::STRICT_FLOG2: EqOpc = ISD::FLOG2; break;
955  case ISD::STRICT_FRINT: EqOpc = ISD::FRINT; break;
956  case ISD::STRICT_FNEARBYINT: EqOpc = ISD::FNEARBYINT; break;
957  case ISD::STRICT_FMAXNUM: EqOpc = ISD::FMAXNUM; break;
958  case ISD::STRICT_FMINNUM: EqOpc = ISD::FMINNUM; break;
959  case ISD::STRICT_FCEIL: EqOpc = ISD::FCEIL; break;
960  case ISD::STRICT_FFLOOR: EqOpc = ISD::FFLOOR; break;
961  case ISD::STRICT_FROUND: EqOpc = ISD::FROUND; break;
962  case ISD::STRICT_FTRUNC: EqOpc = ISD::FTRUNC; break;
963  case ISD::STRICT_FP_ROUND: EqOpc = ISD::FP_ROUND; break;
964  case ISD::STRICT_FP_EXTEND: EqOpc = ISD::FP_EXTEND; break;
965  }
966 
967  return getOperationAction(EqOpc, VT);
968  }
969 
970  /// Return true if the specified operation is legal on this target or can be
971  /// made legal with custom lowering. This is used to help guide high-level
972  /// lowering decisions.
973  bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
974  return (VT == MVT::Other || isTypeLegal(VT)) &&
975  (getOperationAction(Op, VT) == Legal ||
976  getOperationAction(Op, VT) == Custom);
977  }
978 
979  /// Return true if the specified operation is legal on this target or can be
980  /// made legal using promotion. This is used to help guide high-level lowering
981  /// decisions.
982  bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
983  return (VT == MVT::Other || isTypeLegal(VT)) &&
984  (getOperationAction(Op, VT) == Legal ||
985  getOperationAction(Op, VT) == Promote);
986  }
987 
988  /// Return true if the specified operation is legal on this target or can be
989  /// made legal with custom lowering or using promotion. This is used to help
990  /// guide high-level lowering decisions.
991  bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const {
992  return (VT == MVT::Other || isTypeLegal(VT)) &&
993  (getOperationAction(Op, VT) == Legal ||
994  getOperationAction(Op, VT) == Custom ||
995  getOperationAction(Op, VT) == Promote);
996  }
997 
998  /// Return true if the operation uses custom lowering, regardless of whether
999  /// the type is legal or not.
1000  bool isOperationCustom(unsigned Op, EVT VT) const {
1001  return getOperationAction(Op, VT) == Custom;
1002  }
1003 
1004  /// Return true if lowering to a jump table is allowed.
1005  virtual bool areJTsAllowed(const Function *Fn) const {
1006  if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
1007  return false;
1008 
1009  return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1010  isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
1011  }
1012 
1013  /// Check whether the range [Low,High] fits in a machine word.
1014  bool rangeFitsInWord(const APInt &Low, const APInt &High,
1015  const DataLayout &DL) const {
1016  // FIXME: Using the pointer type doesn't seem ideal.
1017  uint64_t BW = DL.getIndexSizeInBits(0u);
1018  uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
1019  return Range <= BW;
1020  }
1021 
1022  /// Return true if lowering to a jump table is suitable for a set of case
1023  /// clusters which may contain \p NumCases cases, \p Range range of values.
1024  virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
1025  uint64_t Range) const {
1026  // FIXME: This function check the maximum table size and density, but the
1027  // minimum size is not checked. It would be nice if the minimum size is
1028  // also combined within this function. Currently, the minimum size check is
1029  // performed in findJumpTable() in SelectionDAGBuiler and
1030  // getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
1031  const bool OptForSize = SI->getParent()->getParent()->hasOptSize();
1032  const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
1033  const unsigned MaxJumpTableSize = getMaximumJumpTableSize();
1034 
1035  // Check whether the number of cases is small enough and
1036  // the range is dense enough for a jump table.
1037  if ((OptForSize || Range <= MaxJumpTableSize) &&
1038  (NumCases * 100 >= Range * MinDensity)) {
1039  return true;
1040  }
1041  return false;
1042  }
1043 
1044  /// Return true if lowering to a bit test is suitable for a set of case
1045  /// clusters which contains \p NumDests unique destinations, \p Low and
1046  /// \p High as its lowest and highest case values, and expects \p NumCmps
1047  /// case value comparisons. Check if the number of destinations, comparison
1048  /// metric, and range are all suitable.
1049  bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
1050  const APInt &Low, const APInt &High,
1051  const DataLayout &DL) const {
1052  // FIXME: I don't think NumCmps is the correct metric: a single case and a
1053  // range of cases both require only one branch to lower. Just looking at the
1054  // number of clusters and destinations should be enough to decide whether to
1055  // build bit tests.
1056 
1057  // To lower a range with bit tests, the range must fit the bitwidth of a
1058  // machine word.
1059  if (!rangeFitsInWord(Low, High, DL))
1060  return false;
1061 
1062  // Decide whether it's profitable to lower this range with bit tests. Each
1063  // destination requires a bit test and branch, and there is an overall range
1064  // check branch. For a small number of clusters, separate comparisons might
1065  // be cheaper, and for many destinations, splitting the range might be
1066  // better.
1067  return (NumDests == 1 && NumCmps >= 3) || (NumDests == 2 && NumCmps >= 5) ||
1068  (NumDests == 3 && NumCmps >= 6);
1069  }
1070 
1071  /// Return true if the specified operation is illegal on this target or
1072  /// unlikely to be made legal with custom lowering. This is used to help guide
1073  /// high-level lowering decisions.
1074  bool isOperationExpand(unsigned Op, EVT VT) const {
1075  return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
1076  }
1077 
1078  /// Return true if the specified operation is legal on this target.
1079  bool isOperationLegal(unsigned Op, EVT VT) const {
1080  return (VT == MVT::Other || isTypeLegal(VT)) &&
1081  getOperationAction(Op, VT) == Legal;
1082  }
1083 
1084  /// Return how this load with extension should be treated: either it is legal,
1085  /// needs to be promoted to a larger size, needs to be expanded to some other
1086  /// code sequence, or the target has a custom expander for it.
1088  EVT MemVT) const {
1089  if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
1090  unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
1091  unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
1092  assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
1093  MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
1094  unsigned Shift = 4 * ExtType;
1095  return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
1096  }
1097 
1098  /// Return true if the specified load with extension is legal on this target.
1099  bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
1100  return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
1101  }
1102 
1103  /// Return true if the specified load with extension is legal or custom
1104  /// on this target.
1105  bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
1106  return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
1107  getLoadExtAction(ExtType, ValVT, MemVT) == Custom;
1108  }
1109 
1110  /// Return how this store with truncation should be treated: either it is
1111  /// legal, needs to be promoted to a larger size, needs to be expanded to some
1112  /// other code sequence, or the target has a custom expander for it.
1114  if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
1115  unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
1116  unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
1117  assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
1118  "Table isn't big enough!");
1119  return TruncStoreActions[ValI][MemI];
1120  }
1121 
1122  /// Return true if the specified store with truncation is legal on this
1123  /// target.
1124  bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
1125  return isTypeLegal(ValVT) && getTruncStoreAction(ValVT, MemVT) == Legal;
1126  }
1127 
1128  /// Return true if the specified store with truncation has solution on this
1129  /// target.
1130  bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const {
1131  return isTypeLegal(ValVT) &&
1132  (getTruncStoreAction(ValVT, MemVT) == Legal ||
1133  getTruncStoreAction(ValVT, MemVT) == Custom);
1134  }
1135 
1136  /// Return how the indexed load should be treated: either it is legal, needs
1137  /// to be promoted to a larger size, needs to be expanded to some other code
1138  /// sequence, or the target has a custom expander for it.
1140  getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
1141  assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
1142  "Table isn't big enough!");
1143  unsigned Ty = (unsigned)VT.SimpleTy;
1144  return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
1145  }
1146 
1147  /// Return true if the specified indexed load is legal on this target.
1148  bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
1149  return VT.isSimple() &&
1150  (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
1151  getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
1152  }
1153 
1154  /// Return how the indexed store should be treated: either it is legal, needs
1155  /// to be promoted to a larger size, needs to be expanded to some other code
1156  /// sequence, or the target has a custom expander for it.
1158  getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
1159  assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
1160  "Table isn't big enough!");
1161  unsigned Ty = (unsigned)VT.SimpleTy;
1162  return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
1163  }
1164 
1165  /// Return true if the specified indexed load is legal on this target.
1166  bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
1167  return VT.isSimple() &&
1168  (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
1169  getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
1170  }
1171 
1172  /// Return how the condition code should be treated: either it is legal, needs
1173  /// to be expanded to some other code sequence, or the target has a custom
1174  /// expander for it.
1177  assert((unsigned)CC < array_lengthof(CondCodeActions) &&
1178  ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&
1179  "Table isn't big enough!");
1180  // See setCondCodeAction for how this is encoded.
1181  uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1182  uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
1183  LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
1184  assert(Action != Promote && "Can't promote condition code!");
1185  return Action;
1186  }
1187 
1188  /// Return true if the specified condition code is legal on this target.
1189  bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
1190  return getCondCodeAction(CC, VT) == Legal;
1191  }
1192 
1193  /// Return true if the specified condition code is legal or custom on this
1194  /// target.
1196  return getCondCodeAction(CC, VT) == Legal ||
1197  getCondCodeAction(CC, VT) == Custom;
1198  }
1199 
1200  /// If the action for this operation is to promote, this method returns the
1201  /// ValueType to promote to.
1202  MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
1203  assert(getOperationAction(Op, VT) == Promote &&
1204  "This operation isn't promoted!");
1205 
1206  // See if this has an explicit type specified.
1207  std::map<std::pair<unsigned, MVT::SimpleValueType>,
1209  PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
1210  if (PTTI != PromoteToType.end()) return PTTI->second;
1211 
1212  assert((VT.isInteger() || VT.isFloatingPoint()) &&
1213  "Cannot autopromote this type, add it with AddPromotedToType.");
1214 
1215  MVT NVT = VT;
1216  do {
1217  NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
1218  assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
1219  "Didn't find type to promote to!");
1220  } while (!isTypeLegal(NVT) ||
1221  getOperationAction(Op, NVT) == Promote);
1222  return NVT;
1223  }
1224 
1225  /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
1226  /// operations except for the pointer size. If AllowUnknown is true, this
1227  /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
1228  /// otherwise it will assert.
1230  bool AllowUnknown = false) const {
1231  // Lower scalar pointers to native pointer types.
1232  if (auto *PTy = dyn_cast<PointerType>(Ty))
1233  return getPointerTy(DL, PTy->getAddressSpace());
1234 
1235  if (auto *VTy = dyn_cast<VectorType>(Ty)) {
1236  Type *EltTy = VTy->getElementType();
1237  // Lower vectors of pointers to native pointer types.
1238  if (auto *PTy = dyn_cast<PointerType>(EltTy)) {
1239  EVT PointerTy(getPointerTy(DL, PTy->getAddressSpace()));
1240  EltTy = PointerTy.getTypeForEVT(Ty->getContext());
1241  }
1242  return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(EltTy, false),
1243  VTy->getElementCount());
1244  }
1245 
1246  return EVT::getEVT(Ty, AllowUnknown);
1247  }
1248 
1250  bool AllowUnknown = false) const {
1251  // Lower scalar pointers to native pointer types.
1252  if (PointerType *PTy = dyn_cast<PointerType>(Ty))
1253  return getPointerMemTy(DL, PTy->getAddressSpace());
1254  else if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1255  Type *Elm = VTy->getElementType();
1256  if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
1257  EVT PointerTy(getPointerMemTy(DL, PT->getAddressSpace()));
1258  Elm = PointerTy.getTypeForEVT(Ty->getContext());
1259  }
1260  return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
1261  VTy->getNumElements());
1262  }
1263 
1264  return getValueType(DL, Ty, AllowUnknown);
1265  }
1266 
1267 
1268  /// Return the MVT corresponding to this LLVM type. See getValueType.
1270  bool AllowUnknown = false) const {
1271  return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
1272  }
1273 
1274  /// Return the desired alignment for ByVal or InAlloca aggregate function
1275  /// arguments in the caller parameter area. This is the actual alignment, not
1276  /// its logarithm.
1277  virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
1278 
1279  /// Return the type of registers that this ValueType will eventually require.
1281  assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
1282  return RegisterTypeForVT[VT.SimpleTy];
1283  }
1284 
1285  /// Return the type of registers that this ValueType will eventually require.
1286  MVT getRegisterType(LLVMContext &Context, EVT VT) const {
1287  if (VT.isSimple()) {
1288  assert((unsigned)VT.getSimpleVT().SimpleTy <
1289  array_lengthof(RegisterTypeForVT));
1290  return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
1291  }
1292  if (VT.isVector()) {
1293  EVT VT1;
1294  MVT RegisterVT;
1295  unsigned NumIntermediates;
1296  (void)getVectorTypeBreakdown(Context, VT, VT1,
1297  NumIntermediates, RegisterVT);
1298  return RegisterVT;
1299  }
1300  if (VT.isInteger()) {
1301  return getRegisterType(Context, getTypeToTransformTo(Context, VT));
1302  }
1303  llvm_unreachable("Unsupported extended type!");
1304  }
1305 
1306  /// Return the number of registers that this ValueType will eventually
1307  /// require.
1308  ///
1309  /// This is one for any types promoted to live in larger registers, but may be
1310  /// more than one for types (like i64) that are split into pieces. For types
1311  /// like i140, which are first promoted then expanded, it is the number of
1312  /// registers needed to hold all the bits of the original type. For an i140
1313  /// on a 32 bit machine this means 5 registers.
1314  unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
1315  if (VT.isSimple()) {
1316  assert((unsigned)VT.getSimpleVT().SimpleTy <
1317  array_lengthof(NumRegistersForVT));
1318  return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
1319  }
1320  if (VT.isVector()) {
1321  EVT VT1;
1322  MVT VT2;
1323  unsigned NumIntermediates;
1324  return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
1325  }
1326  if (VT.isInteger()) {
1327  unsigned BitWidth = VT.getSizeInBits();
1328  unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
1329  return (BitWidth + RegWidth - 1) / RegWidth;
1330  }
1331  llvm_unreachable("Unsupported extended type!");
1332  }
1333 
1334  /// Certain combinations of ABIs, Targets and features require that types
1335  /// are legal for some operations and not for other operations.
1336  /// For MIPS all vector types must be passed through the integer register set.
1338  CallingConv::ID CC, EVT VT) const {
1339  return getRegisterType(Context, VT);
1340  }
1341 
1342  /// Certain targets require unusual breakdowns of certain types. For MIPS,
1343  /// this occurs when a vector type is used, as vector are passed through the
1344  /// integer register set.
1345  virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
1346  CallingConv::ID CC,
1347  EVT VT) const {
1348  return getNumRegisters(Context, VT);
1349  }
1350 
1351  /// Certain targets have context senstive alignment requirements, where one
1352  /// type has the alignment requirement of another type.
1353  virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy,
1354  DataLayout DL) const {
1355  return DL.getABITypeAlignment(ArgTy);
1356  }
1357 
1358  /// If true, then instruction selection should seek to shrink the FP constant
1359  /// of the specified type to a smaller type in order to save space and / or
1360  /// reduce runtime.
1361  virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
1362 
1363  /// Return true if it is profitable to reduce a load to a smaller type.
1364  /// Example: (i16 (trunc (i32 (load x))) -> i16 load x
1366  EVT NewVT) const {
1367  // By default, assume that it is cheaper to extract a subvector from a wide
1368  // vector load rather than creating multiple narrow vector loads.
1369  if (NewVT.isVector() && !Load->hasOneUse())
1370  return false;
1371 
1372  return true;
1373  }
1374 
1375  /// When splitting a value of the specified type into parts, does the Lo
1376  /// or Hi part come first? This usually follows the endianness, except
1377  /// for ppcf128, where the Hi part always comes first.
1378  bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
1379  return DL.isBigEndian() || VT == MVT::ppcf128;
1380  }
1381 
1382  /// If true, the target has custom DAG combine transformations that it can
1383  /// perform for the specified node.
1385  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1386  return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
1387  }
1388 
1389  unsigned getGatherAllAliasesMaxDepth() const {
1390  return GatherAllAliasesMaxDepth;
1391  }
1392 
1393  /// Returns the size of the platform's va_list object.
1394  virtual unsigned getVaListSizeInBits(const DataLayout &DL) const {
1395  return getPointerTy(DL).getSizeInBits();
1396  }
1397 
1398  /// Get maximum # of store operations permitted for llvm.memset
1399  ///
1400  /// This function returns the maximum number of store operations permitted
1401  /// to replace a call to llvm.memset. The value is set by the target at the
1402  /// performance threshold for such a replacement. If OptSize is true,
1403  /// return the limit for functions that have OptSize attribute.
1404  unsigned getMaxStoresPerMemset(bool OptSize) const {
1405  return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
1406  }
1407 
1408  /// Get maximum # of store operations permitted for llvm.memcpy
1409  ///
1410  /// This function returns the maximum number of store operations permitted
1411  /// to replace a call to llvm.memcpy. The value is set by the target at the
1412  /// performance threshold for such a replacement. If OptSize is true,
1413  /// return the limit for functions that have OptSize attribute.
1414  unsigned getMaxStoresPerMemcpy(bool OptSize) const {
1415  return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
1416  }
1417 
1418  /// \brief Get maximum # of store operations to be glued together
1419  ///
1420  /// This function returns the maximum number of store operations permitted
1421  /// to glue together during lowering of llvm.memcpy. The value is set by
1422  // the target at the performance threshold for such a replacement.
1423  virtual unsigned getMaxGluedStoresPerMemcpy() const {
1424  return MaxGluedStoresPerMemcpy;
1425  }
1426 
1427  /// Get maximum # of load operations permitted for memcmp
1428  ///
1429  /// This function returns the maximum number of load operations permitted
1430  /// to replace a call to memcmp. The value is set by the target at the
1431  /// performance threshold for such a replacement. If OptSize is true,
1432  /// return the limit for functions that have OptSize attribute.
1433  unsigned getMaxExpandSizeMemcmp(bool OptSize) const {
1434  return OptSize ? MaxLoadsPerMemcmpOptSize : MaxLoadsPerMemcmp;
1435  }
1436 
1437  /// Get maximum # of store operations permitted for llvm.memmove
1438  ///
1439  /// This function returns the maximum number of store operations permitted
1440  /// to replace a call to llvm.memmove. The value is set by the target at the
1441  /// performance threshold for such a replacement. If OptSize is true,
1442  /// return the limit for functions that have OptSize attribute.
1443  unsigned getMaxStoresPerMemmove(bool OptSize) const {
1444  return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
1445  }
1446 
1447  /// Determine if the target supports unaligned memory accesses.
1448  ///
1449  /// This function returns true if the target allows unaligned memory accesses
1450  /// of the specified type in the given address space. If true, it also returns
1451  /// whether the unaligned memory access is "fast" in the last argument by
1452  /// reference. This is used, for example, in situations where an array
1453  /// copy/move/set is converted to a sequence of store operations. Its use
1454  /// helps to ensure that such replacements don't generate code that causes an
1455  /// alignment error (trap) on the target machine.
1457  EVT, unsigned AddrSpace = 0, unsigned Align = 1,
1459  bool * /*Fast*/ = nullptr) const {
1460  return false;
1461  }
1462 
1463  /// LLT handling variant.
1465  LLT, unsigned AddrSpace = 0, unsigned Align = 1,
1467  bool * /*Fast*/ = nullptr) const {
1468  return false;
1469  }
1470 
1471  /// Return true if the target supports a memory access of this type for the
1472  /// given address space and alignment. If the access is allowed, the optional
1473  /// final parameter returns if the access is also fast (as defined by the
1474  /// target).
1475  bool
1476  allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
1477  unsigned AddrSpace = 0, unsigned Alignment = 1,
1479  bool *Fast = nullptr) const;
1480 
1481  /// Return true if the target supports a memory access of this type for the
1482  /// given MachineMemOperand. If the access is allowed, the optional
1483  /// final parameter returns if the access is also fast (as defined by the
1484  /// target).
1485  bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
1486  const MachineMemOperand &MMO,
1487  bool *Fast = nullptr) const;
1488 
1489  /// Returns the target specific optimal type for load and store operations as
1490  /// a result of memset, memcpy, and memmove lowering.
1491  ///
1492  /// If DstAlign is zero that means it's safe to destination alignment can
1493  /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
1494  /// a need to check it against alignment requirement, probably because the
1495  /// source does not need to be loaded. If 'IsMemset' is true, that means it's
1496  /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
1497  /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
1498  /// does not need to be loaded. It returns EVT::Other if the type should be
1499  /// determined using generic target-independent logic.
1500  virtual EVT
1501  getOptimalMemOpType(uint64_t /*Size*/, unsigned /*DstAlign*/,
1502  unsigned /*SrcAlign*/, bool /*IsMemset*/,
1503  bool /*ZeroMemset*/, bool /*MemcpyStrSrc*/,
1504  const AttributeList & /*FuncAttributes*/) const {
1505  return MVT::Other;
1506  }
1507 
1508 
1509  /// LLT returning variant.
1510  virtual LLT
1511  getOptimalMemOpLLT(uint64_t /*Size*/, unsigned /*DstAlign*/,
1512  unsigned /*SrcAlign*/, bool /*IsMemset*/,
1513  bool /*ZeroMemset*/, bool /*MemcpyStrSrc*/,
1514  const AttributeList & /*FuncAttributes*/) const {
1515  return LLT();
1516  }
1517 
1518  /// Returns true if it's safe to use load / store of the specified type to
1519  /// expand memcpy / memset inline.
1520  ///
1521  /// This is mostly true for all types except for some special cases. For
1522  /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
1523  /// fstpl which also does type conversion. Note the specified type doesn't
1524  /// have to be legal as the hook is used before type legalization.
1525  virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
1526 
1527  /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
1528  bool usesUnderscoreSetJmp() const {
1529  return UseUnderscoreSetJmp;
1530  }
1531 
1532  /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
1533  bool usesUnderscoreLongJmp() const {
1534  return UseUnderscoreLongJmp;
1535  }
1536 
1537  /// Return lower limit for number of blocks in a jump table.
1538  virtual unsigned getMinimumJumpTableEntries() const;
1539 
1540  /// Return lower limit of the density in a jump table.
1541  unsigned getMinimumJumpTableDensity(bool OptForSize) const;
1542 
1543  /// Return upper limit for number of entries in a jump table.
1544  /// Zero if no limit.
1545  unsigned getMaximumJumpTableSize() const;
1546 
1547  virtual bool isJumpTableRelative() const {
1548  return TM.isPositionIndependent();
1549  }
1550 
1551  /// If a physical register, this specifies the register that
1552  /// llvm.savestack/llvm.restorestack should save and restore.
1554  return StackPointerRegisterToSaveRestore;
1555  }
1556 
1557  /// If a physical register, this returns the register that receives the
1558  /// exception address on entry to an EH pad.
1559  virtual unsigned
1560  getExceptionPointerRegister(const Constant *PersonalityFn) const {
1561  // 0 is guaranteed to be the NoRegister value on all targets
1562  return 0;
1563  }
1564 
1565  /// If a physical register, this returns the register that receives the
1566  /// exception typeid on entry to a landing pad.
1567  virtual unsigned
1568  getExceptionSelectorRegister(const Constant *PersonalityFn) const {
1569  // 0 is guaranteed to be the NoRegister value on all targets
1570  return 0;
1571  }
1572 
1573  virtual bool needsFixedCatchObjects() const {
1574  report_fatal_error("Funclet EH is not implemented for this target");
1575  }
1576 
1577  /// Returns the target's jmp_buf size in bytes (if never set, the default is
1578  /// 200)
1579  unsigned getJumpBufSize() const {
1580  return JumpBufSize;
1581  }
1582 
1583  /// Returns the target's jmp_buf alignment in bytes (if never set, the default
1584  /// is 0)
1585  unsigned getJumpBufAlignment() const {
1586  return JumpBufAlignment;
1587  }
1588 
1589  /// Return the minimum stack alignment of an argument.
1590  unsigned getMinStackArgumentAlignment() const {
1591  return MinStackArgumentAlignment;
1592  }
1593 
1594  /// Return the minimum function alignment.
1595  unsigned getMinFunctionAlignment() const {
1596  return MinFunctionAlignment;
1597  }
1598 
1599  /// Return the preferred function alignment.
1600  unsigned getPrefFunctionAlignment() const {
1601  return PrefFunctionAlignment;
1602  }
1603 
1604  /// Return the preferred loop alignment.
1605  virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
1606  return PrefLoopAlignment;
1607  }
1608 
1609  /// Should loops be aligned even when the function is marked OptSize (but not
1610  /// MinSize).
1611  virtual bool alignLoopsWithOptSize() const {
1612  return false;
1613  }
1614 
1615  /// If the target has a standard location for the stack protector guard,
1616  /// returns the address of that location. Otherwise, returns nullptr.
1617  /// DEPRECATED: please override useLoadStackGuardNode and customize
1618  /// LOAD_STACK_GUARD, or customize \@llvm.stackguard().
1619  virtual Value *getIRStackGuard(IRBuilder<> &IRB) const;
1620 
1621  /// Inserts necessary declarations for SSP (stack protection) purpose.
1622  /// Should be used only when getIRStackGuard returns nullptr.
1623  virtual void insertSSPDeclarations(Module &M) const;
1624 
1625  /// Return the variable that's previously inserted by insertSSPDeclarations,
1626  /// if any, otherwise return nullptr. Should be used only when
1627  /// getIRStackGuard returns nullptr.
1628  virtual Value *getSDagStackGuard(const Module &M) const;
1629 
1630  /// If this function returns true, stack protection checks should XOR the
1631  /// frame pointer (or whichever pointer is used to address locals) into the
1632  /// stack guard value before checking it. getIRStackGuard must return nullptr
1633  /// if this returns true.
1634  virtual bool useStackGuardXorFP() const { return false; }
1635 
1636  /// If the target has a standard stack protection check function that
1637  /// performs validation and error handling, returns the function. Otherwise,
1638  /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
1639  /// Should be used only when getIRStackGuard returns nullptr.
1640  virtual Function *getSSPStackGuardCheck(const Module &M) const;
1641 
1642 protected:
1643  Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1644  bool UseTLS) const;
1645 
1646 public:
1647  /// Returns the target-specific address of the unsafe stack pointer.
1648  virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;
1649 
1650  /// Returns the name of the symbol used to emit stack probes or the empty
1651  /// string if not applicable.
1653  return "";
1654  }
1655 
1656  /// Returns true if a cast between SrcAS and DestAS is a noop.
1657  virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1658  return false;
1659  }
1660 
1661  /// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
1662  /// are happy to sink it into basic blocks. A cast may be free, but not
1663  /// necessarily a no-op. e.g. a free truncate from a 64-bit to 32-bit pointer.
1664  virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1665  return isNoopAddrSpaceCast(SrcAS, DestAS);
1666  }
1667 
1668  /// Return true if the pointer arguments to CI should be aligned by aligning
1669  /// the object whose address is being passed. If so then MinSize is set to the
1670  /// minimum size the object must be to be aligned and PrefAlign is set to the
1671  /// preferred alignment.
1672  virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
1673  unsigned & /*PrefAlign*/) const {
1674  return false;
1675  }
1676 
1677  //===--------------------------------------------------------------------===//
1678  /// \name Helpers for TargetTransformInfo implementations
1679  /// @{
1680 
1681  /// Get the ISD node that corresponds to the Instruction class opcode.
1682  int InstructionOpcodeToISD(unsigned Opcode) const;
1683 
1684  /// Estimate the cost of type-legalization and the legalized type.
1685  std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
1686  Type *Ty) const;
1687 
1688  /// @}
1689 
1690  //===--------------------------------------------------------------------===//
1691  /// \name Helpers for atomic expansion.
1692  /// @{
1693 
1694  /// Returns the maximum atomic operation size (in bits) supported by
1695  /// the backend. Atomic operations greater than this size (as well
1696  /// as ones that are not naturally aligned), will be expanded by
1697  /// AtomicExpandPass into an __atomic_* library call.
1699  return MaxAtomicSizeInBitsSupported;
1700  }
1701 
1702  /// Returns the size of the smallest cmpxchg or ll/sc instruction
1703  /// the backend supports. Any smaller operations are widened in
1704  /// AtomicExpandPass.
1705  ///
1706  /// Note that *unlike* operations above the maximum size, atomic ops
1707  /// are still natively supported below the minimum; they just
1708  /// require a more complex expansion.
1709  unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; }
1710 
1711  /// Whether the target supports unaligned atomic operations.
1712  bool supportsUnalignedAtomics() const { return SupportsUnalignedAtomics; }
1713 
1714  /// Whether AtomicExpandPass should automatically insert fences and reduce
1715  /// ordering for this atomic. This should be true for most architectures with
1716  /// weak memory ordering. Defaults to false.
1717  virtual bool shouldInsertFencesForAtomic(const Instruction *I) const {
1718  return false;
1719  }
1720 
1721  /// Perform a load-linked operation on Addr, returning a "Value *" with the
1722  /// corresponding pointee type. This may entail some non-trivial operations to
1723  /// truncate or reconstruct types that will be illegal in the backend. See
1724  /// ARMISelLowering for an example implementation.
1725  virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1726  AtomicOrdering Ord) const {
1727  llvm_unreachable("Load linked unimplemented on this target");
1728  }
1729 
1730  /// Perform a store-conditional operation to Addr. Return the status of the
1731  /// store. This should be 0 if the store succeeded, non-zero otherwise.
1732  virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1733  Value *Addr, AtomicOrdering Ord) const {
1734  llvm_unreachable("Store conditional unimplemented on this target");
1735  }
1736 
1737  /// Perform a masked atomicrmw using a target-specific intrinsic. This
1738  /// represents the core LL/SC loop which will be lowered at a late stage by
1739  /// the backend.
1741  AtomicRMWInst *AI,
1742  Value *AlignedAddr, Value *Incr,
1743  Value *Mask, Value *ShiftAmt,
1744  AtomicOrdering Ord) const {
1745  llvm_unreachable("Masked atomicrmw expansion unimplemented on this target");
1746  }
1747 
1748  /// Perform a masked cmpxchg using a target-specific intrinsic. This
1749  /// represents the core LL/SC loop which will be lowered at a late stage by
1750  /// the backend.
1752  IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
1753  Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
1754  llvm_unreachable("Masked cmpxchg expansion unimplemented on this target");
1755  }
1756 
1757  /// Inserts in the IR a target-specific intrinsic specifying a fence.
1758  /// It is called by AtomicExpandPass before expanding an
1759  /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
1760  /// if shouldInsertFencesForAtomic returns true.
1761  ///
1762  /// Inst is the original atomic instruction, prior to other expansions that
1763  /// may be performed.
1764  ///
1765  /// This function should either return a nullptr, or a pointer to an IR-level
1766  /// Instruction*. Even complex fence sequences can be represented by a
1767  /// single Instruction* through an intrinsic to be lowered later.
1768  /// Backends should override this method to produce target-specific intrinsic
1769  /// for their fences.
1770  /// FIXME: Please note that the default implementation here in terms of
1771  /// IR-level fences exists for historical/compatibility reasons and is
1772  /// *unsound* ! Fences cannot, in general, be used to restore sequential
1773  /// consistency. For example, consider the following example:
1774  /// atomic<int> x = y = 0;
1775  /// int r1, r2, r3, r4;
1776  /// Thread 0:
1777  /// x.store(1);
1778  /// Thread 1:
1779  /// y.store(1);
1780  /// Thread 2:
1781  /// r1 = x.load();
1782  /// r2 = y.load();
1783  /// Thread 3:
1784  /// r3 = y.load();
1785  /// r4 = x.load();
1786  /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1787  /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1788  /// IR-level fences can prevent it.
1789  /// @{
1791  AtomicOrdering Ord) const {
1792  if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
1793  return Builder.CreateFence(Ord);
1794  else
1795  return nullptr;
1796  }
1797 
1799  Instruction *Inst,
1800  AtomicOrdering Ord) const {
1801  if (isAcquireOrStronger(Ord))
1802  return Builder.CreateFence(Ord);
1803  else
1804  return nullptr;
1805  }
1806  /// @}
1807 
1808  // Emits code that executes when the comparison result in the ll/sc
1809  // expansion of a cmpxchg instruction is such that the store-conditional will
1810  // not execute. This makes it possible to balance out the load-linked with
1811  // a dedicated instruction, if desired.
1812  // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
1813  // be unnecessarily held, except if clrex, inserted by this hook, is executed.
1814  virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
1815 
1816  /// Returns true if the given (atomic) store should be expanded by the
1817  /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1819  return false;
1820  }
1821 
1822  /// Returns true if arguments should be sign-extended in lib calls.
1823  virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1824  return IsSigned;
1825  }
1826 
1827  /// Returns how the given (atomic) load should be expanded by the
1828  /// IR-level AtomicExpand pass.
1831  }
1832 
1833  /// Returns how the given atomic cmpxchg should be expanded by the IR-level
1834  /// AtomicExpand pass.
1835  virtual AtomicExpansionKind
1838  }
1839 
1840  /// Returns how the IR-level AtomicExpand pass should expand the given
1841  /// AtomicRMW, if at all. Default is to never expand.
1843  return RMW->isFloatingPointOperation() ?
1844  AtomicExpansionKind::CmpXChg : AtomicExpansionKind::None;
1845  }
1846 
1847  /// On some platforms, an AtomicRMW that never actually modifies the value
1848  /// (such as fetch_add of 0) can be turned into a fence followed by an
1849  /// atomic load. This may sound useless, but it makes it possible for the
1850  /// processor to keep the cacheline shared, dramatically improving
1851  /// performance. And such idempotent RMWs are useful for implementing some
1852  /// kinds of locks, see for example (justification + benchmarks):
1853  /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1854  /// This method tries doing that transformation, returning the atomic load if
1855  /// it succeeds, and nullptr otherwise.
1856  /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1857  /// another round of expansion.
1858  virtual LoadInst *
1860  return nullptr;
1861  }
1862 
1863  /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
1864  /// SIGN_EXTEND, or ANY_EXTEND).
1866  return ISD::ZERO_EXTEND;
1867  }
1868 
1869  /// @}
1870 
1871  /// Returns true if we should normalize
1872  /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1873  /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1874  /// that it saves us from materializing N0 and N1 in an integer register.
1875  /// Targets that are able to perform and/or on flags should return false here.
1877  EVT VT) const {
1878  // If a target has multiple condition registers, then it likely has logical
1879  // operations on those registers.
1880  if (hasMultipleConditionRegisters())
1881  return false;
1882  // Only do the transform if the value won't be split into multiple
1883  // registers.
1884  LegalizeTypeAction Action = getTypeAction(Context, VT);
1885  return Action != TypeExpandInteger && Action != TypeExpandFloat &&
1886  Action != TypeSplitVector;
1887  }
1888 
1889  virtual bool isProfitableToCombineMinNumMaxNum(EVT VT) const { return true; }
1890 
1891  /// Return true if a select of constants (select Cond, C1, C2) should be
1892  /// transformed into simple math ops with the condition value. For example:
1893  /// select Cond, C1, C1-1 --> add (zext Cond), C1-1
1894  virtual bool convertSelectOfConstantsToMath(EVT VT) const {
1895  return false;
1896  }
1897 
1898  /// Return true if it is profitable to transform an integer
1899  /// multiplication-by-constant into simpler operations like shifts and adds.
1900  /// This may be true if the target does not directly support the
1901  /// multiplication operation for the specified type or the sequence of simpler
1902  /// ops is faster than the multiply.
1903  virtual bool decomposeMulByConstant(LLVMContext &Context,
1904  EVT VT, SDValue C) const {
1905  return false;
1906  }
1907 
1908  /// Return true if it is more correct/profitable to use strict FP_TO_INT
1909  /// conversion operations - canonicalizing the FP source value instead of
1910  /// converting all cases and then selecting based on value.
1911  /// This may be true if the target throws exceptions for out of bounds
1912  /// conversions or has fast FP CMOV.
1913  virtual bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT,
1914  bool IsSigned) const {
1915  return false;
1916  }
1917 
1918  //===--------------------------------------------------------------------===//
1919  // TargetLowering Configuration Methods - These methods should be invoked by
1920  // the derived class constructor to configure this object for the target.
1921  //
1922 protected:
1923  /// Specify how the target extends the result of integer and floating point
1924  /// boolean values from i1 to a wider type. See getBooleanContents.
1926  BooleanContents = Ty;
1927  BooleanFloatContents = Ty;
1928  }
1929 
1930  /// Specify how the target extends the result of integer and floating point
1931  /// boolean values from i1 to a wider type. See getBooleanContents.
1933  BooleanContents = IntTy;
1934  BooleanFloatContents = FloatTy;
1935  }
1936 
1937  /// Specify how the target extends the result of a vector boolean value from a
1938  /// vector of i1 to a wider type. See getBooleanContents.
1940  BooleanVectorContents = Ty;
1941  }
1942 
1943  /// Specify the target scheduling preference.
1945  SchedPreferenceInfo = Pref;
1946  }
1947 
1948  /// Indicate whether this target prefers to use _setjmp to implement
1949  /// llvm.setjmp or the version without _. Defaults to false.
1950  void setUseUnderscoreSetJmp(bool Val) {
1951  UseUnderscoreSetJmp = Val;
1952  }
1953 
1954  /// Indicate whether this target prefers to use _longjmp to implement
1955  /// llvm.longjmp or the version without _. Defaults to false.
1956  void setUseUnderscoreLongJmp(bool Val) {
1957  UseUnderscoreLongJmp = Val;
1958  }
1959 
1960  /// Indicate the minimum number of blocks to generate jump tables.
1961  void setMinimumJumpTableEntries(unsigned Val);
1962 
1963  /// Indicate the maximum number of entries in jump tables.
1964  /// Set to zero to generate unlimited jump tables.
1965  void setMaximumJumpTableSize(unsigned);
1966 
1967  /// If set to a physical register, this specifies the register that
1968  /// llvm.savestack/llvm.restorestack should save and restore.
1970  StackPointerRegisterToSaveRestore = R;
1971  }
1972 
1973  /// Tells the code generator that the target has multiple (allocatable)
1974  /// condition registers that can be used to store the results of comparisons
1975  /// for use by selects and conditional branches. With multiple condition
1976  /// registers, the code generator will not aggressively sink comparisons into
1977  /// the blocks of their users.
1978  void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1979  HasMultipleConditionRegisters = hasManyRegs;
1980  }
1981 
1982  /// Tells the code generator that the target has BitExtract instructions.
1983  /// The code generator will aggressively sink "shift"s into the blocks of
1984  /// their users if the users will generate "and" instructions which can be
1985  /// combined with "shift" to BitExtract instructions.
1986  void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1987  HasExtractBitsInsn = hasExtractInsn;
1988  }
1989 
1990  /// Tells the code generator not to expand logic operations on comparison
1991  /// predicates into separate sequences that increase the amount of flow
1992  /// control.
1993  void setJumpIsExpensive(bool isExpensive = true);
1994 
1995  /// Tells the code generator which bitwidths to bypass.
1996  void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1997  BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1998  }
1999 
2000  /// Add the specified register class as an available regclass for the
2001  /// specified value type. This indicates the selector can handle values of
2002  /// that class natively.
2004  assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
2005  RegClassForVT[VT.SimpleTy] = RC;
2006  }
2007 
2008  /// Return the largest legal super-reg register class of the register class
2009  /// for the specified type and its associated "cost".
2010  virtual std::pair<const TargetRegisterClass *, uint8_t>
2011  findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
2012 
2013  /// Once all of the register classes are added, this allows us to compute
2014  /// derived properties we expose.
2015  void computeRegisterProperties(const TargetRegisterInfo *TRI);
2016 
2017  /// Indicate that the specified operation does not work with the specified
2018  /// type and indicate what to do about it. Note that VT may refer to either
2019  /// the type of a result or that of an operand of Op.
2020  void setOperationAction(unsigned Op, MVT VT,
2021  LegalizeAction Action) {
2022  assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
2023  OpActions[(unsigned)VT.SimpleTy][Op] = Action;
2024  }
2025 
2026  /// Indicate that the specified load with extension does not work with the
2027  /// specified type and indicate what to do about it.
2028  void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
2029  LegalizeAction Action) {
2030  assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
2031  MemVT.isValid() && "Table isn't big enough!");
2032  assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
2033  unsigned Shift = 4 * ExtType;
2034  LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
2035  LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
2036  }
2037 
2038  /// Indicate that the specified truncating store does not work with the
2039  /// specified type and indicate what to do about it.
2040  void setTruncStoreAction(MVT ValVT, MVT MemVT,
2041  LegalizeAction Action) {
2042  assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
2043  TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action;
2044  }
2045 
2046  /// Indicate that the specified indexed load does or does not work with the
2047  /// specified type and indicate what to do abort it.
2048  ///
2049  /// NOTE: All indexed mode loads are initialized to Expand in
2050  /// TargetLowering.cpp
2051  void setIndexedLoadAction(unsigned IdxMode, MVT VT,
2052  LegalizeAction Action) {
2053  assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
2054  (unsigned)Action < 0xf && "Table isn't big enough!");
2055  // Load action are kept in the upper half.
2056  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
2057  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
2058  }
2059 
2060  /// Indicate that the specified indexed store does or does not work with the
2061  /// specified type and indicate what to do about it.
2062  ///
2063  /// NOTE: All indexed mode stores are initialized to Expand in
2064  /// TargetLowering.cpp
2065  void setIndexedStoreAction(unsigned IdxMode, MVT VT,
2066  LegalizeAction Action) {
2067  assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
2068  (unsigned)Action < 0xf && "Table isn't big enough!");
2069  // Store action are kept in the lower half.
2070  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
2071  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
2072  }
2073 
2074  /// Indicate that the specified condition code is or isn't supported on the
2075  /// target and indicate what to do about it.
2077  LegalizeAction Action) {
2078  assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
2079  "Table isn't big enough!");
2080  assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
2081  /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
2082  /// value and the upper 29 bits index into the second dimension of the array
2083  /// to select what 32-bit value to use.
2084  uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
2085  CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
2086  CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
2087  }
2088 
2089  /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
2090  /// to trying a larger integer/fp until it can find one that works. If that
2091  /// default is insufficient, this method can be used by the target to override
2092  /// the default.
2093  void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
2094  PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
2095  }
2096 
2097  /// Convenience method to set an operation to Promote and specify the type
2098  /// in a single call.
2099  void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
2100  setOperationAction(Opc, OrigVT, Promote);
2101  AddPromotedToType(Opc, OrigVT, DestVT);
2102  }
2103 
2104  /// Targets should invoke this method for each target independent node that
2105  /// they want to provide a custom DAG combiner for by implementing the
2106  /// PerformDAGCombine virtual method.
2108  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
2109  TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
2110  }
2111 
2112  /// Set the target's required jmp_buf buffer size (in bytes); default is 200
2113  void setJumpBufSize(unsigned Size) {
2114  JumpBufSize = Size;
2115  }
2116 
2117  /// Set the target's required jmp_buf buffer alignment (in bytes); default is
2118  /// 0
2119  void setJumpBufAlignment(unsigned Align) {
2120  JumpBufAlignment = Align;
2121  }
2122 
2123  /// Set the target's minimum function alignment (in log2(bytes))
2125  MinFunctionAlignment = Align;
2126  }
2127 
2128  /// Set the target's preferred function alignment. This should be set if
2129  /// there is a performance benefit to higher-than-minimum alignment (in
2130  /// log2(bytes))
2132  PrefFunctionAlignment = Align;
2133  }
2134 
2135  /// Set the target's preferred loop alignment. Default alignment is zero, it
2136  /// means the target does not care about loop alignment. The alignment is
2137  /// specified in log2(bytes). The target may also override
2138  /// getPrefLoopAlignment to provide per-loop values.
2139  void setPrefLoopAlignment(unsigned Align) {
2140  PrefLoopAlignment = Align;
2141  }
2142 
2143  /// Set the minimum stack alignment of an argument (in log2(bytes)).
2145  MinStackArgumentAlignment = Align;
2146  }
2147 
2148  /// Set the maximum atomic operation size supported by the
2149  /// backend. Atomic operations greater than this size (as well as
2150  /// ones that are not naturally aligned), will be expanded by
2151  /// AtomicExpandPass into an __atomic_* library call.
2152  void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
2153  MaxAtomicSizeInBitsSupported = SizeInBits;
2154  }
2155 
2156  /// Sets the minimum cmpxchg or ll/sc size supported by the backend.
2157  void setMinCmpXchgSizeInBits(unsigned SizeInBits) {
2158  MinCmpXchgSizeInBits = SizeInBits;
2159  }
2160 
2161  /// Sets whether unaligned atomic operations are supported.
2162  void setSupportsUnalignedAtomics(bool UnalignedSupported) {
2163  SupportsUnalignedAtomics = UnalignedSupported;
2164  }
2165 
2166 public:
2167  //===--------------------------------------------------------------------===//
2168  // Addressing mode description hooks (used by LSR etc).
2169  //
2170 
2171  /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
2172  /// instructions reading the address. This allows as much computation as
2173  /// possible to be done in the address mode for that operand. This hook lets
2174  /// targets also pass back when this should be done on intrinsics which
2175  /// load/store.
2176  virtual bool getAddrModeArguments(IntrinsicInst * /*I*/,
2177  SmallVectorImpl<Value*> &/*Ops*/,
2178  Type *&/*AccessTy*/) const {
2179  return false;
2180  }
2181 
2182  /// This represents an addressing mode of:
2183  /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
2184  /// If BaseGV is null, there is no BaseGV.
2185  /// If BaseOffs is zero, there is no base offset.
2186  /// If HasBaseReg is false, there is no base register.
2187  /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
2188  /// no scale.
2189  struct AddrMode {
2190  GlobalValue *BaseGV = nullptr;
2191  int64_t BaseOffs = 0;
2192  bool HasBaseReg = false;
2193  int64_t Scale = 0;
2194  AddrMode() = default;
2195  };
2196 
2197  /// Return true if the addressing mode represented by AM is legal for this
2198  /// target, for a load/store of the specified type.
2199  ///
2200  /// The type may be VoidTy, in which case only return true if the addressing
2201  /// mode is legal for a load/store of any legal type. TODO: Handle
2202  /// pre/postinc as well.
2203  ///
2204  /// If the address space cannot be determined, it will be -1.
2205  ///
2206  /// TODO: Remove default argument
2207  virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
2208  Type *Ty, unsigned AddrSpace,
2209  Instruction *I = nullptr) const;
2210 
2211  /// Return the cost of the scaling factor used in the addressing mode
2212  /// represented by AM for this target, for a load/store of the specified type.
2213  ///
2214  /// If the AM is supported, the return value must be >= 0.
2215  /// If the AM is not supported, it returns a negative value.
2216  /// TODO: Handle pre/postinc as well.
2217  /// TODO: Remove default argument
2218  virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
2219  Type *Ty, unsigned AS = 0) const {
2220  // Default: assume that any scaling factor used in a legal AM is free.
2221  if (isLegalAddressingMode(DL, AM, Ty, AS))
2222  return 0;
2223  return -1;
2224  }
2225 
2226  /// Return true if the specified immediate is legal icmp immediate, that is
2227  /// the target has icmp instructions which can compare a register against the
2228  /// immediate without having to materialize the immediate into a register.
2229  virtual bool isLegalICmpImmediate(int64_t) const {
2230  return true;
2231  }
2232 
2233  /// Return true if the specified immediate is legal add immediate, that is the
2234  /// target has add instructions which can add a register with the immediate
2235  /// without having to materialize the immediate into a register.
2236  virtual bool isLegalAddImmediate(int64_t) const {
2237  return true;
2238  }
2239 
2240  /// Return true if the specified immediate is legal for the value input of a
2241  /// store instruction.
2242  virtual bool isLegalStoreImmediate(int64_t Value) const {
2243  // Default implementation assumes that at least 0 works since it is likely
2244  // that a zero register exists or a zero immediate is allowed.
2245  return Value == 0;
2246  }
2247 
2248  /// Return true if it's significantly cheaper to shift a vector by a uniform
2249  /// scalar than by an amount which will vary across each lane. On x86, for
2250  /// example, there is a "psllw" instruction for the former case, but no simple
2251  /// instruction for a general "a << b" operation on vectors.
2252  virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
2253  return false;
2254  }
2255 
2256  /// Returns true if the opcode is a commutative binary operation.
2257  virtual bool isCommutativeBinOp(unsigned Opcode) const {
2258  // FIXME: This should get its info from the td file.
2259  switch (Opcode) {
2260  case ISD::ADD:
2261  case ISD::SMIN:
2262  case ISD::SMAX:
2263  case ISD::UMIN:
2264  case ISD::UMAX:
2265  case ISD::MUL:
2266  case ISD::MULHU:
2267  case ISD::MULHS:
2268  case ISD::SMUL_LOHI:
2269  case ISD::UMUL_LOHI:
2270  case ISD::FADD:
2271  case ISD::FMUL:
2272  case ISD::AND:
2273  case ISD::OR:
2274  case ISD::XOR:
2275  case ISD::SADDO:
2276  case ISD::UADDO:
2277  case ISD::ADDC:
2278  case ISD::ADDE:
2279  case ISD::SADDSAT:
2280  case ISD::UADDSAT:
2281  case ISD::FMINNUM:
2282  case ISD::FMAXNUM:
2283  case ISD::FMINNUM_IEEE:
2284  case ISD::FMAXNUM_IEEE:
2285  case ISD::FMINIMUM:
2286  case ISD::FMAXIMUM:
2287  return true;
2288  default: return false;
2289  }
2290  }
2291 
2292  /// Return true if the node is a math/logic binary operator.
2293  virtual bool isBinOp(unsigned Opcode) const {
2294  // A commutative binop must be a binop.
2295  if (isCommutativeBinOp(Opcode))
2296  return true;
2297  // These are non-commutative binops.
2298  switch (Opcode) {
2299  case ISD::SUB:
2300  case ISD::SHL:
2301  case ISD::SRL:
2302  case ISD::SRA:
2303  case ISD::SDIV:
2304  case ISD::UDIV:
2305  case ISD::SREM:
2306  case ISD::UREM:
2307  case ISD::FSUB:
2308  case ISD::FDIV:
2309  case ISD::FREM:
2310  return true;
2311  default:
2312  return false;
2313  }
2314  }
2315 
2316  /// Return true if it's free to truncate a value of type FromTy to type
2317  /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
2318  /// by referencing its sub-register AX.
2319  /// Targets must return false when FromTy <= ToTy.
2320  virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
2321  return false;
2322  }
2323 
2324  /// Return true if a truncation from FromTy to ToTy is permitted when deciding
2325  /// whether a call is in tail position. Typically this means that both results
2326  /// would be assigned to the same register or stack slot, but it could mean
2327  /// the target performs adequate checks of its own before proceeding with the
2328  /// tail call. Targets must return false when FromTy <= ToTy.
2329  virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
2330  return false;
2331  }
2332 
2333  virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
2334  return false;
2335  }
2336 
2337  virtual bool isProfitableToHoist(Instruction *I) const { return true; }
2338 
2339  /// Return true if the extension represented by \p I is free.
2340  /// Unlikely the is[Z|FP]ExtFree family which is based on types,
2341  /// this method can use the context provided by \p I to decide
2342  /// whether or not \p I is free.
2343  /// This method extends the behavior of the is[Z|FP]ExtFree family.
2344  /// In other words, if is[Z|FP]Free returns true, then this method
2345  /// returns true as well. The converse is not true.
2346  /// The target can perform the adequate checks by overriding isExtFreeImpl.
2347  /// \pre \p I must be a sign, zero, or fp extension.
2348  bool isExtFree(const Instruction *I) const {
2349  switch (I->getOpcode()) {
2350  case Instruction::FPExt:
2351  if (isFPExtFree(EVT::getEVT(I->getType()),
2352  EVT::getEVT(I->getOperand(0)->getType())))
2353  return true;
2354  break;
2355  case Instruction::ZExt:
2356  if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
2357  return true;
2358  break;
2359  case Instruction::SExt:
2360  break;
2361  default:
2362  llvm_unreachable("Instruction is not an extension");
2363  }
2364  return isExtFreeImpl(I);
2365  }
2366 
2367  /// Return true if \p Load and \p Ext can form an ExtLoad.
2368  /// For example, in AArch64
2369  /// %L = load i8, i8* %ptr
2370  /// %E = zext i8 %L to i32
2371  /// can be lowered into one load instruction
2372  /// ldrb w0, [x0]
2373  bool isExtLoad(const LoadInst *Load, const Instruction *Ext,
2374  const DataLayout &DL) const {
2375  EVT VT = getValueType(DL, Ext->getType());
2376  EVT LoadVT = getValueType(DL, Load->getType());
2377 
2378  // If the load has other users and the truncate is not free, the ext
2379  // probably isn't free.
2380  if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) &&
2381  !isTruncateFree(Ext->getType(), Load->getType()))
2382  return false;
2383 
2384  // Check whether the target supports casts folded into loads.
2385  unsigned LType;
2386  if (isa<ZExtInst>(Ext))
2387  LType = ISD::ZEXTLOAD;
2388  else {
2389  assert(isa<SExtInst>(Ext) && "Unexpected ext type!");
2390  LType = ISD::SEXTLOAD;
2391  }
2392 
2393  return isLoadExtLegal(LType, VT, LoadVT);
2394  }
2395 
2396  /// Return true if any actual instruction that defines a value of type FromTy
2397  /// implicitly zero-extends the value to ToTy in the result register.
2398  ///
2399  /// The function should return true when it is likely that the truncate can
2400  /// be freely folded with an instruction defining a value of FromTy. If
2401  /// the defining instruction is unknown (because you're looking at a
2402  /// function argument, PHI, etc.) then the target may require an
2403  /// explicit truncate, which is not necessarily free, but this function
2404  /// does not deal with those cases.
2405  /// Targets must return false when FromTy >= ToTy.
2406  virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
2407  return false;
2408  }
2409 
2410  virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
2411  return false;
2412  }
2413 
2414  /// Return true if sign-extension from FromTy to ToTy is cheaper than
2415  /// zero-extension.
2416  virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const {
2417  return false;
2418  }
2419 
2420  /// Return true if sinking I's operands to the same basic block as I is
2421  /// profitable, e.g. because the operands can be folded into a target
2422  /// instruction during instruction selection. After calling the function
2423  /// \p Ops contains the Uses to sink ordered by dominance (dominating users
2424  /// come first).
2426  SmallVectorImpl<Use *> &Ops) const {
2427  return false;
2428  }
2429 
2430  /// Return true if the target supplies and combines to a paired load
2431  /// two loaded values of type LoadedType next to each other in memory.
2432  /// RequiredAlignment gives the minimal alignment constraints that must be met
2433  /// to be able to select this paired load.
2434  ///
2435  /// This information is *not* used to generate actual paired loads, but it is
2436  /// used to generate a sequence of loads that is easier to combine into a
2437  /// paired load.
2438  /// For instance, something like this:
2439  /// a = load i64* addr
2440  /// b = trunc i64 a to i32
2441  /// c = lshr i64 a, 32
2442  /// d = trunc i64 c to i32
2443  /// will be optimized into:
2444  /// b = load i32* addr1
2445  /// d = load i32* addr2
2446  /// Where addr1 = addr2 +/- sizeof(i32).
2447  ///
2448  /// In other words, unless the target performs a post-isel load combining,
2449  /// this information should not be provided because it will generate more
2450  /// loads.
2451  virtual bool hasPairedLoad(EVT /*LoadedType*/,
2452  unsigned & /*RequiredAlignment*/) const {
2453  return false;
2454  }
2455 
2456  /// Return true if the target has a vector blend instruction.
2457  virtual bool hasVectorBlend() const { return false; }
2458 
2459  /// Get the maximum supported factor for interleaved memory accesses.
2460  /// Default to be the minimum interleave factor: 2.
2461  virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
2462 
2463  /// Lower an interleaved load to target specific intrinsics. Return
2464  /// true on success.
2465  ///
2466  /// \p LI is the vector load instruction.
2467  /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
2468  /// \p Indices is the corresponding indices for each shufflevector.
2469  /// \p Factor is the interleave factor.
2470  virtual bool lowerInterleavedLoad(LoadInst *LI,
2472  ArrayRef<unsigned> Indices,
2473  unsigned Factor) const {
2474  return false;
2475  }
2476 
2477  /// Lower an interleaved store to target specific intrinsics. Return
2478  /// true on success.
2479  ///
2480  /// \p SI is the vector store instruction.
2481  /// \p SVI is the shufflevector to RE-interleave the stored vector.
2482  /// \p Factor is the interleave factor.
2484  unsigned Factor) const {
2485  return false;
2486  }
2487 
2488  /// Return true if zero-extending the specific node Val to type VT2 is free
2489  /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
2490  /// because it's folded such as X86 zero-extending loads).
2491  virtual bool isZExtFree(SDValue Val, EVT VT2) const {
2492  return isZExtFree(Val.getValueType(), VT2);
2493  }
2494 
2495  /// Return true if an fpext operation is free (for instance, because
2496  /// single-precision floating-point numbers are implicitly extended to
2497  /// double-precision).
2498  virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const {
2499  assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&
2500  "invalid fpext types");
2501  return false;
2502  }
2503 
2504  /// Return true if an fpext operation input to an \p Opcode operation is free
2505  /// (for instance, because half-precision floating-point numbers are
2506  /// implicitly extended to float-precision) for an FMA instruction.
2507  virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const {
2508  assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
2509  "invalid fpext types");
2510  return isFPExtFree(DestVT, SrcVT);
2511  }
2512 
2513  /// Return true if folding a vector load into ExtVal (a sign, zero, or any
2514  /// extend node) is profitable.
2515  virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
2516 
2517  /// Return true if an fneg operation is free to the point where it is never
2518  /// worthwhile to replace it with a bitwise operation.
2519  virtual bool isFNegFree(EVT VT) const {
2520  assert(VT.isFloatingPoint());
2521  return false;
2522  }
2523 
2524  /// Return true if an fabs operation is free to the point where it is never
2525  /// worthwhile to replace it with a bitwise operation.
2526  virtual bool isFAbsFree(EVT VT) const {
2527  assert(VT.isFloatingPoint());
2528  return false;
2529  }
2530 
2531  /// Return true if an FMA operation is faster than a pair of fmul and fadd
2532  /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
2533  /// returns true, otherwise fmuladd is expanded to fmul + fadd.
2534  ///
2535  /// NOTE: This may be called before legalization on types for which FMAs are
2536  /// not legal, but should return true if those types will eventually legalize
2537  /// to types that support FMAs. After legalization, it will only be called on
2538  /// types that support FMAs (via Legal or Custom actions)
2539  virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
2540  return false;
2541  }
2542 
2543  /// Return true if it's profitable to narrow operations of type VT1 to
2544  /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
2545  /// i32 to i16.
2546  virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
2547  return false;
2548  }
2549 
2550  /// Return true if it is beneficial to convert a load of a constant to
2551  /// just the constant itself.
2552  /// On some targets it might be more efficient to use a combination of
2553  /// arithmetic instructions to materialize the constant instead of loading it
2554  /// from a constant pool.
2555  virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
2556  Type *Ty) const {
2557  return false;
2558  }
2559 
2560  /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
2561  /// from this source type with this index. This is needed because
2562  /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
2563  /// the first element, and only the target knows which lowering is cheap.
2564  virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
2565  unsigned Index) const {
2566  return false;
2567  }
2568 
2569  /// Try to convert an extract element of a vector binary operation into an
2570  /// extract element followed by a scalar operation.
2571  virtual bool shouldScalarizeBinop(SDValue VecOp) const {
2572  return false;
2573  }
2574 
2575  /// Return true if extraction of a scalar element from the given vector type
2576  /// at the given index is cheap. For example, if scalar operations occur on
2577  /// the same register file as vector operations, then an extract element may
2578  /// be a sub-register rename rather than an actual instruction.
2579  virtual bool isExtractVecEltCheap(EVT VT, unsigned Index) const {
2580  return false;
2581  }
2582 
2583  /// Try to convert math with an overflow comparison into the corresponding DAG
2584  /// node operation. Targets may want to override this independently of whether
2585  /// the operation is legal/custom for the given type because it may obscure
2586  /// matching of other patterns.
2587  virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT) const {
2588  // TODO: The default logic is inherited from code in CodeGenPrepare.
2589  // The opcode should not make a difference by default?
2590  if (Opcode != ISD::UADDO)
2591  return false;
2592 
2593  // Allow the transform as long as we have an integer type that is not
2594  // obviously illegal and unsupported.
2595  if (VT.isVector())
2596  return false;
2597  return VT.isSimple() || !isOperationExpand(Opcode, VT);
2598  }
2599 
2600  // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
2601  // even if the vector itself has multiple uses.
2602  virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
2603  return false;
2604  }
2605 
2606  // Return true if CodeGenPrepare should consider splitting large offset of a
2607  // GEP to make the GEP fit into the addressing mode and can be sunk into the
2608  // same blocks of its users.
2609  virtual bool shouldConsiderGEPOffsetSplit() const { return false; }
2610 
2611  //===--------------------------------------------------------------------===//
2612  // Runtime Library hooks
2613  //
2614 
2615  /// Rename the default libcall routine name for the specified libcall.
2616  void setLibcallName(RTLIB::Libcall Call, const char *Name) {
2617  LibcallRoutineNames[Call] = Name;
2618  }
2619 
2620  /// Get the libcall routine name for the specified libcall.
2621  const char *getLibcallName(RTLIB::Libcall Call) const {
2622  return LibcallRoutineNames[Call];
2623  }
2624 
2625  /// Override the default CondCode to be used to test the result of the
2626  /// comparison libcall against zero.
2628  CmpLibcallCCs[Call] = CC;
2629  }
2630 
2631  /// Get the CondCode that's to be used to test the result of the comparison
2632  /// libcall against zero.
2634  return CmpLibcallCCs[Call];
2635  }
2636 
2637  /// Set the CallingConv that should be used for the specified libcall.
2639  LibcallCallingConvs[Call] = CC;
2640  }
2641 
2642  /// Get the CallingConv that should be used for the specified libcall.
2644  return LibcallCallingConvs[Call];
2645  }
2646 
2647  /// Execute target specific actions to finalize target lowering.
2648  /// This is used to set extra flags in MachineFrameInformation and freezing
2649  /// the set of reserved registers.
2650  /// The default implementation just freezes the set of reserved registers.
2651  virtual void finalizeLowering(MachineFunction &MF) const;
2652 
2653 private:
2654  const TargetMachine &TM;
2655 
2656  /// Tells the code generator that the target has multiple (allocatable)
2657  /// condition registers that can be used to store the results of comparisons
2658  /// for use by selects and conditional branches. With multiple condition
2659  /// registers, the code generator will not aggressively sink comparisons into
2660  /// the blocks of their users.
2661  bool HasMultipleConditionRegisters;
2662 
2663  /// Tells the code generator that the target has BitExtract instructions.
2664  /// The code generator will aggressively sink "shift"s into the blocks of
2665  /// their users if the users will generate "and" instructions which can be
2666  /// combined with "shift" to BitExtract instructions.
2667  bool HasExtractBitsInsn;
2668 
2669  /// Tells the code generator to bypass slow divide or remainder
2670  /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
2671  /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
2672  /// div/rem when the operands are positive and less than 256.
2673  DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
2674 
2675  /// Tells the code generator that it shouldn't generate extra flow control
2676  /// instructions and should attempt to combine flow control instructions via
2677  /// predication.
2678  bool JumpIsExpensive;
2679 
2680  /// This target prefers to use _setjmp to implement llvm.setjmp.
2681  ///
2682  /// Defaults to false.
2683  bool UseUnderscoreSetJmp;
2684 
2685  /// This target prefers to use _longjmp to implement llvm.longjmp.
2686  ///
2687  /// Defaults to false.
2688  bool UseUnderscoreLongJmp;
2689 
2690  /// Information about the contents of the high-bits in boolean values held in
2691  /// a type wider than i1. See getBooleanContents.
2692  BooleanContent BooleanContents;
2693 
2694  /// Information about the contents of the high-bits in boolean values held in
2695  /// a type wider than i1. See getBooleanContents.
2696  BooleanContent BooleanFloatContents;
2697 
2698  /// Information about the contents of the high-bits in boolean vector values
2699  /// when the element type is wider than i1. See getBooleanContents.
2700  BooleanContent BooleanVectorContents;
2701 
2702  /// The target scheduling preference: shortest possible total cycles or lowest
2703  /// register usage.
2704  Sched::Preference SchedPreferenceInfo;
2705 
2706  /// The size, in bytes, of the target's jmp_buf buffers
2707  unsigned JumpBufSize;
2708 
2709  /// The alignment, in bytes, of the target's jmp_buf buffers
2710  unsigned JumpBufAlignment;
2711 
2712  /// The minimum alignment that any argument on the stack needs to have.
2713  unsigned MinStackArgumentAlignment;
2714 
2715  /// The minimum function alignment (used when optimizing for size, and to
2716  /// prevent explicitly provided alignment from leading to incorrect code).
2717  unsigned MinFunctionAlignment;
2718 
2719  /// The preferred function alignment (used when alignment unspecified and
2720  /// optimizing for speed).
2721  unsigned PrefFunctionAlignment;
2722 
2723  /// The preferred loop alignment.
2724  unsigned PrefLoopAlignment;
2725 
2726  /// Size in bits of the maximum atomics size the backend supports.
2727  /// Accesses larger than this will be expanded by AtomicExpandPass.
2728  unsigned MaxAtomicSizeInBitsSupported;
2729 
2730  /// Size in bits of the minimum cmpxchg or ll/sc operation the
2731  /// backend supports.
2732  unsigned MinCmpXchgSizeInBits;
2733 
2734  /// This indicates if the target supports unaligned atomic operations.
2735  bool SupportsUnalignedAtomics;
2736 
2737  /// If set to a physical register, this specifies the register that
2738  /// llvm.savestack/llvm.restorestack should save and restore.
2739  unsigned StackPointerRegisterToSaveRestore;
2740 
2741  /// This indicates the default register class to use for each ValueType the
2742  /// target supports natively.
2743  const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
2744  unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
2745  MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
2746 
2747  /// This indicates the "representative" register class to use for each
2748  /// ValueType the target supports natively. This information is used by the
2749  /// scheduler to track register pressure. By default, the representative
2750  /// register class is the largest legal super-reg register class of the
2751  /// register class of the specified type. e.g. On x86, i8, i16, and i32's
2752  /// representative class would be GR32.
2753  const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
2754 
2755  /// This indicates the "cost" of the "representative" register class for each
2756  /// ValueType. The cost is used by the scheduler to approximate register
2757  /// pressure.
2758  uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
2759 
2760  /// For any value types we are promoting or expanding, this contains the value
2761  /// type that we are changing to. For Expanded types, this contains one step
2762  /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
2763  /// (e.g. i64 -> i16). For types natively supported by the system, this holds
2764  /// the same type (e.g. i32 -> i32).
2765  MVT TransformToType[MVT::LAST_VALUETYPE];
2766 
2767  /// For each operation and each value type, keep a LegalizeAction that
2768  /// indicates how instruction selection should deal with the operation. Most
2769  /// operations are Legal (aka, supported natively by the target), but
2770  /// operations that are not should be described. Note that operations on
2771  /// non-legal value types are not described here.
2773 
2774  /// For each load extension type and each value type, keep a LegalizeAction
2775  /// that indicates how instruction selection should deal with a load of a
2776  /// specific value type and extension type. Uses 4-bits to store the action
2777  /// for each of the 4 load ext types.
2778  uint16_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2779 
2780  /// For each value type pair keep a LegalizeAction that indicates whether a
2781  /// truncating store of a specific value type and truncating type is legal.
2783 
2784  /// For each indexed mode and each value type, keep a pair of LegalizeAction
2785  /// that indicates how instruction selection should deal with the load /
2786  /// store.
2787  ///
2788  /// The first dimension is the value_type for the reference. The second
2789  /// dimension represents the various modes for load store.
2790  uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
2791 
2792  /// For each condition code (ISD::CondCode) keep a LegalizeAction that
2793  /// indicates how instruction selection should deal with the condition code.
2794  ///
2795  /// Because each CC action takes up 4 bits, we need to have the array size be
2796  /// large enough to fit all of the value types. This can be done by rounding
2797  /// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
2798  uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 7) / 8];
2799 
2800 protected:
2802 
2803 private:
2804  LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
2805 
2806  /// Targets can specify ISD nodes that they would like PerformDAGCombine
2807  /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
2808  /// array.
2809  unsigned char
2810  TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
2811 
2812  /// For operations that must be promoted to a specific type, this holds the
2813  /// destination type. This map should be sparse, so don't hold it as an
2814  /// array.
2815  ///
2816  /// Targets add entries to this map with AddPromotedToType(..), clients access
2817  /// this with getTypeToPromoteTo(..).
2818  std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
2819  PromoteToType;
2820 
2821  /// Stores the name each libcall.
2822  const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL + 1];
2823 
2824  /// The ISD::CondCode that should be used to test the result of each of the
2825  /// comparison libcall against zero.
2826  ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2827 
2828  /// Stores the CallingConv that should be used for each libcall.
2829  CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
2830 
2831  /// Set default libcall names and calling conventions.
2832  void InitLibcalls(const Triple &TT);
2833 
2834 protected:
2835  /// Return true if the extension represented by \p I is free.
2836  /// \pre \p I is a sign, zero, or fp extension and
2837  /// is[Z|FP]ExtFree of the related types is not true.
2838  virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
2839 
2840  /// Depth that GatherAllAliases should should continue looking for chain
2841  /// dependencies when trying to find a more preferable chain. As an
2842  /// approximation, this should be more than the number of consecutive stores
2843  /// expected to be merged.
2845 
2846  /// \brief Specify maximum number of store instructions per memset call.
2847  ///
2848  /// When lowering \@llvm.memset this field specifies the maximum number of
2849  /// store operations that may be substituted for the call to memset. Targets
2850  /// must set this value based on the cost threshold for that target. Targets
2851  /// should assume that the memset will be done using as many of the largest
2852  /// store operations first, followed by smaller ones, if necessary, per
2853  /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
2854  /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
2855  /// store. This only applies to setting a constant array of a constant size.
2857  /// Likewise for functions with the OptSize attribute.
2859 
2860  /// \brief Specify maximum number of store instructions per memcpy call.
2861  ///
2862  /// When lowering \@llvm.memcpy this field specifies the maximum number of
2863  /// store operations that may be substituted for a call to memcpy. Targets
2864  /// must set this value based on the cost threshold for that target. Targets
2865  /// should assume that the memcpy will be done using as many of the largest
2866  /// store operations first, followed by smaller ones, if necessary, per
2867  /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
2868  /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
2869  /// and one 1-byte store. This only applies to copying a constant array of
2870  /// constant size.
2872  /// Likewise for functions with the OptSize attribute.
2874  /// \brief Specify max number of store instructions to glue in inlined memcpy.
2875  ///
2876  /// When memcpy is inlined based on MaxStoresPerMemcpy, specify maximum number
2877  /// of store instructions to keep together. This helps in pairing and
2878  // vectorization later on.
2879  unsigned MaxGluedStoresPerMemcpy = 0;
2880 
2881  /// \brief Specify maximum number of load instructions per memcmp call.
2882  ///
2883  /// When lowering \@llvm.memcmp this field specifies the maximum number of
2884  /// pairs of load operations that may be substituted for a call to memcmp.
2885  /// Targets must set this value based on the cost threshold for that target.
2886  /// Targets should assume that the memcmp will be done using as many of the
2887  /// largest load operations first, followed by smaller ones, if necessary, per
2888  /// alignment restrictions. For example, loading 7 bytes on a 32-bit machine
2889  /// with 32-bit alignment would result in one 4-byte load, a one 2-byte load
2890  /// and one 1-byte load. This only applies to copying a constant array of
2891  /// constant size.
2893  /// Likewise for functions with the OptSize attribute.
2895 
2896  /// \brief Specify maximum number of store instructions per memmove call.
2897  ///
2898  /// When lowering \@llvm.memmove this field specifies the maximum number of
2899  /// store instructions that may be substituted for a call to memmove. Targets
2900  /// must set this value based on the cost threshold for that target. Targets
2901  /// should assume that the memmove will be done using as many of the largest
2902  /// store operations first, followed by smaller ones, if necessary, per
2903  /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2904  /// with 8-bit alignment would result in nine 1-byte stores. This only
2905  /// applies to copying a constant array of constant size.
2907  /// Likewise for functions with the OptSize attribute.
2909 
2910  /// Tells the code generator that select is more expensive than a branch if
2911  /// the branch is usually predicted right.
2913 
2914  /// \see enableExtLdPromotion.
2916 
2917  /// Return true if the value types that can be represented by the specified
2918  /// register class are all legal.
2919  bool isLegalRC(const TargetRegisterInfo &TRI,
2920  const TargetRegisterClass &RC) const;
2921 
2922  /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2923  /// sequence of memory operands that is recognized by PrologEpilogInserter.
2924  MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
2925  MachineBasicBlock *MBB) const;
2926 
2927  /// Replace/modify the XRay custom event operands with target-dependent
2928  /// details.
2929  MachineBasicBlock *emitXRayCustomEvent(MachineInstr &MI,
2930  MachineBasicBlock *MBB) const;
2931 
2932  /// Replace/modify the XRay typed event operands with target-dependent
2933  /// details.
2934  MachineBasicBlock *emitXRayTypedEvent(MachineInstr &MI,
2935  MachineBasicBlock *MBB) const;
2936 };
2937 
2938 /// This class defines information used to lower LLVM code to legal SelectionDAG
2939 /// operators that the target instruction selector can accept natively.
2940 ///
2941 /// This class also defines callbacks that targets must implement to lower
2942 /// target-specific constructs to SelectionDAG operators.
2944 public:
2945  struct DAGCombinerInfo;
2946 
2947  TargetLowering(const TargetLowering &) = delete;
2948  TargetLowering &operator=(const TargetLowering &) = delete;
2949 
2950  /// NOTE: The TargetMachine owns TLOF.
2951  explicit TargetLowering(const TargetMachine &TM);
2952 
2953  bool isPositionIndependent() const;
2954 
2955  virtual bool isSDNodeSourceOfDivergence(const SDNode *N,
2956  FunctionLoweringInfo *FLI,
2957  LegacyDivergenceAnalysis *DA) const {
2958  return false;
2959  }
2960 
2961  virtual bool isSDNodeAlwaysUniform(const SDNode * N) const {
2962  return false;
2963  }
2964 
2965  /// Returns true by value, base pointer and offset pointer and addressing mode
2966  /// by reference if the node's address can be legally represented as
2967  /// pre-indexed load / store address.
2968  virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2969  SDValue &/*Offset*/,
2970  ISD::MemIndexedMode &/*AM*/,
2971  SelectionDAG &/*DAG*/) const {
2972  return false;
2973  }
2974 
2975  /// Returns true by value, base pointer and offset pointer and addressing mode
2976  /// by reference if this node can be combined with a load / store to form a
2977  /// post-indexed load / store.
2978  virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2979  SDValue &/*Base*/,
2980  SDValue &/*Offset*/,
2981  ISD::MemIndexedMode &/*AM*/,
2982  SelectionDAG &/*DAG*/) const {
2983  return false;
2984  }
2985 
2986  /// Return the entry encoding for a jump table in the current function. The
2987  /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2988  virtual unsigned getJumpTableEncoding() const;
2989 
2990  virtual const MCExpr *
2992  const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2993  MCContext &/*Ctx*/) const {
2994  llvm_unreachable("Need to implement this hook if target has custom JTIs");
2995  }
2996 
2997  /// Returns relocation base for the given PIC jumptable.
2998  virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2999  SelectionDAG &DAG) const;
3000 
3001  /// This returns the relocation base for the given PIC jumptable, the same as
3002  /// getPICJumpTableRelocBase, but as an MCExpr.
3003  virtual const MCExpr *
3004  getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
3005  unsigned JTI, MCContext &Ctx) const;
3006 
3007  /// Return true if folding a constant offset with the given GlobalAddress is
3008  /// legal. It is frequently not legal in PIC relocation models.
3009  virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
3010 
3012  SDValue &Chain) const;
3013 
3014  void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
3015  SDValue &NewRHS, ISD::CondCode &CCCode,
3016  const SDLoc &DL) const;
3017 
3018  /// Returns a pair of (return value, chain).
3019  /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
3020  std::pair<SDValue, SDValue> makeLibCall(
3021  SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef<SDValue> Ops,
3022  bool isSigned, const SDLoc &dl, bool doesNotReturn = false,
3023  bool isReturnValueUsed = true, bool isPostTypeLegalization = false) const;
3024 
3025  /// Check whether parameters to a call that are passed in callee saved
3026  /// registers are the same as from the calling function. This needs to be
3027  /// checked for tail call eligibility.
3028  bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
3029  const uint32_t *CallerPreservedMask,
3030  const SmallVectorImpl<CCValAssign> &ArgLocs,
3031  const SmallVectorImpl<SDValue> &OutVals) const;
3032 
3033  //===--------------------------------------------------------------------===//
3034  // TargetLowering Optimization Methods
3035  //
3036 
3037  /// A convenience struct that encapsulates a DAG, and two SDValues for
3038  /// returning information from TargetLowering to its clients that want to
3039  /// combine.
3042  bool LegalTys;
3043  bool LegalOps;
3046 
3048  bool LT, bool LO) :
3049  DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
3050 
3051  bool LegalTypes() const { return LegalTys; }
3052  bool LegalOperations() const { return LegalOps; }
3053 
3055  Old = O;
3056  New = N;
3057  return true;
3058  }
3059  };
3060 
3061  /// Determines the optimal series of memory ops to replace the memset / memcpy.
3062  /// Return true if the number of memory ops is below the threshold (Limit).
3063  /// It returns the types of the sequence of memory ops to perform
3064  /// memset / memcpy by reference.
3065  bool findOptimalMemOpLowering(std::vector<EVT> &MemOps,
3066  unsigned Limit, uint64_t Size,
3067  unsigned DstAlign, unsigned SrcAlign,
3068  bool IsMemset,
3069  bool ZeroMemset,
3070  bool MemcpyStrSrc,
3071  bool AllowOverlap,
3072  unsigned DstAS, unsigned SrcAS,
3073  const AttributeList &FuncAttributes) const;
3074 
3075  /// Check to see if the specified operand of the specified instruction is a
3076  /// constant integer. If so, check to see if there are any bits set in the
3077  /// constant that are not demanded. If so, shrink the constant and return
3078  /// true.
3079  bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
3080  TargetLoweringOpt &TLO) const;
3081 
3082  // Target hook to do target-specific const optimization, which is called by
3083  // ShrinkDemandedConstant. This function should return true if the target
3084  // doesn't want ShrinkDemandedConstant to further optimize the constant.
3085  virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
3086  TargetLoweringOpt &TLO) const {
3087  return false;
3088  }
3089 
3090  /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
3091  /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
3092  /// generalized for targets with other types of implicit widening casts.
3093  bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
3094  TargetLoweringOpt &TLO) const;
3095 
3096  /// Look at Op. At this point, we know that only the DemandedBits bits of the
3097  /// result of Op are ever used downstream. If we can use this information to
3098  /// simplify Op, create a new simplified DAG node and return true, returning
3099  /// the original and new nodes in Old and New. Otherwise, analyze the
3100  /// expression and return a mask of KnownOne and KnownZero bits for the
3101  /// expression (used to simplify the caller). The KnownZero/One bits may only
3102  /// be accurate for those bits in the Demanded masks.
3103  /// \p AssumeSingleUse When this parameter is true, this function will
3104  /// attempt to simplify \p Op even if there are multiple uses.
3105  /// Callers are responsible for correctly updating the DAG based on the
3106  /// results of this function, because simply replacing replacing TLO.Old
3107  /// with TLO.New will be incorrect when this parameter is true and TLO.Old
3108  /// has multiple uses.
3109  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
3110  const APInt &DemandedElts, KnownBits &Known,
3111  TargetLoweringOpt &TLO, unsigned Depth = 0,
3112  bool AssumeSingleUse = false) const;
3113 
3114  /// Helper wrapper around SimplifyDemandedBits, demanding all elements.
3115  /// Adds Op back to the worklist upon success.
3116  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
3117  KnownBits &Known, TargetLoweringOpt &TLO,
3118  unsigned Depth = 0,
3119  bool AssumeSingleUse = false) const;
3120 
3121  /// Helper wrapper around SimplifyDemandedBits.
3122  /// Adds Op back to the worklist upon success.
3123  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
3124  DAGCombinerInfo &DCI) const;
3125 
3126  /// More limited version of SimplifyDemandedBits that can be used to "look
3127  /// through" ops that don't contribute to the DemandedBits/DemandedElts -
3128  /// bitwise ops etc.
3129  SDValue SimplifyMultipleUseDemandedBits(SDValue Op, const APInt &DemandedBits,
3130  const APInt &DemandedElts,
3131  SelectionDAG &DAG,
3132  unsigned Depth) const;
3133 
3134  /// Look at Vector Op. At this point, we know that only the DemandedElts
3135  /// elements of the result of Op are ever used downstream. If we can use
3136  /// this information to simplify Op, create a new simplified DAG node and
3137  /// return true, storing the original and new nodes in TLO.
3138  /// Otherwise, analyze the expression and return a mask of KnownUndef and
3139  /// KnownZero elements for the expression (used to simplify the caller).
3140  /// The KnownUndef/Zero elements may only be accurate for those bits
3141  /// in the DemandedMask.
3142  /// \p AssumeSingleUse When this parameter is true, this function will
3143  /// attempt to simplify \p Op even if there are multiple uses.
3144  /// Callers are responsible for correctly updating the DAG based on the
3145  /// results of this function, because simply replacing replacing TLO.Old
3146  /// with TLO.New will be incorrect when this parameter is true and TLO.Old
3147  /// has multiple uses.
3148  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask,
3149  APInt &KnownUndef, APInt &KnownZero,
3150  TargetLoweringOpt &TLO, unsigned Depth = 0,
3151  bool AssumeSingleUse = false) const;
3152 
3153  /// Helper wrapper around SimplifyDemandedVectorElts.
3154  /// Adds Op back to the worklist upon success.
3155  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
3156  APInt &KnownUndef, APInt &KnownZero,
3157  DAGCombinerInfo &DCI) const;
3158 
3159  /// Determine which of the bits specified in Mask are known to be either zero
3160  /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
3161  /// argument allows us to only collect the known bits that are shared by the
3162  /// requested vector elements.
3163  virtual void computeKnownBitsForTargetNode(const SDValue Op,
3164  KnownBits &Known,
3165  const APInt &DemandedElts,
3166  const SelectionDAG &DAG,
3167  unsigned Depth = 0) const;
3168  /// Determine which of the bits specified in Mask are known to be either zero
3169  /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
3170  /// argument allows us to only collect the known bits that are shared by the
3171  /// requested vector elements. This is for GISel.
3172  virtual void computeKnownBitsForTargetInstr(Register R, KnownBits &Known,
3173  const APInt &DemandedElts,
3174  const MachineRegisterInfo &MRI,
3175  unsigned Depth = 0) const;
3176 
3177  /// Determine which of the bits of FrameIndex \p FIOp are known to be 0.
3178  /// Default implementation computes low bits based on alignment
3179  /// information. This should preserve known bits passed into it.
3180  virtual void computeKnownBitsForFrameIndex(const SDValue FIOp,
3181  KnownBits &Known,
3182  const APInt &DemandedElts,
3183  const SelectionDAG &DAG,
3184  unsigned Depth = 0) const;
3185 
3186  /// This method can be implemented by targets that want to expose additional
3187  /// information about sign bits to the DAG Combiner. The DemandedElts
3188  /// argument allows us to only collect the minimum sign bits that are shared
3189  /// by the requested vector elements.
3190  virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
3191  const APInt &DemandedElts,
3192  const SelectionDAG &DAG,
3193  unsigned Depth = 0) const;
3194 
3195  /// Attempt to simplify any target nodes based on the demanded vector
3196  /// elements, returning true on success. Otherwise, analyze the expression and
3197  /// return a mask of KnownUndef and KnownZero elements for the expression
3198  /// (used to simplify the caller). The KnownUndef/Zero elements may only be
3199  /// accurate for those bits in the DemandedMask.
3200  virtual bool SimplifyDemandedVectorEltsForTargetNode(
3201  SDValue Op, const APInt &DemandedElts, APInt &KnownUndef,
3202  APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth = 0) const;
3203 
3204  /// Attempt to simplify any target nodes based on the demanded bits/elts,
3205  /// returning true on success. Otherwise, analyze the
3206  /// expression and return a mask of KnownOne and KnownZero bits for the
3207  /// expression (used to simplify the caller). The KnownZero/One bits may only
3208  /// be accurate for those bits in the Demanded masks.
3209  virtual bool SimplifyDemandedBitsForTargetNode(SDValue Op,
3210  const APInt &DemandedBits,
3211  const APInt &DemandedElts,
3212  KnownBits &Known,
3213  TargetLoweringOpt &TLO,
3214  unsigned Depth = 0) const;
3215 
3216  /// More limited version of SimplifyDemandedBits that can be used to "look
3217  /// through" ops that don't contribute to the DemandedBits/DemandedElts -
3218  /// bitwise ops etc.
3219  virtual SDValue SimplifyMultipleUseDemandedBitsForTargetNode(
3220  SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
3221  SelectionDAG &DAG, unsigned Depth) const;
3222 
3223  /// This method returns the constant pool value that will be loaded by LD.
3224  /// NOTE: You must check for implicit extensions of the constant by LD.
3225  virtual const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const;
3226 
3227  /// If \p SNaN is false, \returns true if \p Op is known to never be any
3228  /// NaN. If \p sNaN is true, returns if \p Op is known to never be a signaling
3229  /// NaN.
3230  virtual bool isKnownNeverNaNForTargetNode(SDValue Op,
3231  const SelectionDAG &DAG,
3232  bool SNaN = false,
3233  unsigned Depth = 0) const;
3235  void *DC; // The DAG Combiner object.
3238 
3239  public:
3241 
3242  DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
3243  : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
3244 
3245  bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
3246  bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
3247  bool isAfterLegalizeDAG() const {
3248  return Level == AfterLegalizeDAG;
3249  }
3251  bool isCalledByLegalizer() const { return CalledByLegalizer; }
3252 
3253  void AddToWorklist(SDNode *N);
3254  SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
3255  SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
3256  SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
3257 
3258  void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
3259  };
3260 
3261  /// Return if the N is a constant or constant vector equal to the true value
3262  /// from getBooleanContents().
3263  bool isConstTrueVal(const SDNode *N) const;
3264 
3265  /// Return if the N is a constant or constant vector equal to the false value
3266  /// from getBooleanContents().
3267  bool isConstFalseVal(const SDNode *N) const;
3268 
3269  /// Return if \p N is a True value when extended to \p VT.
3270  bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) const;
3271 
3272  /// Try to simplify a setcc built with the specified operands and cc. If it is
3273  /// unable to simplify it, return a null SDValue.
3274  SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
3275  bool foldBooleans, DAGCombinerInfo &DCI,
3276  const SDLoc &dl) const;
3277 
3278  // For targets which wrap address, unwrap for analysis.
3279  virtual SDValue unwrapAddress(SDValue N) const { return N; }
3280 
3281  /// Returns true (and the GlobalValue and the offset) if the node is a
3282  /// GlobalAddress + offset.
3283  virtual bool
3284  isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
3285 
3286  /// This method will be invoked for all target nodes and for any
3287  /// target-independent nodes that the target has registered with invoke it
3288  /// for.
3289  ///
3290  /// The semantics are as follows:
3291  /// Return Value:
3292  /// SDValue.Val == 0 - No change was made
3293  /// SDValue.Val == N - N was replaced, is dead, and is already handled.
3294  /// otherwise - N should be replaced by the returned Operand.
3295  ///
3296  /// In addition, methods provided by DAGCombinerInfo may be used to perform
3297  /// more complex transformations.
3298  ///
3299  virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
3300 
3301  /// Return true if it is profitable to move this shift by a constant amount
3302  /// though its operand, adjusting any immediate operands as necessary to
3303  /// preserve semantics. This transformation may not be desirable if it
3304  /// disrupts a particularly auspicious target-specific tree (e.g. bitfield
3305  /// extraction in AArch64). By default, it returns true.
3306  ///
3307  /// @param N the shift node
3308  /// @param Level the current DAGCombine legalization level.
3309  virtual bool isDesirableToCommuteWithShift(const SDNode *N,
3310  CombineLevel Level) const {
3311  return true;
3312  }
3313 
3314  // Return true if it is profitable to combine a BUILD_VECTOR with a stride-pattern
3315  // to a shuffle and a truncate.
3316  // Example of such a combine:
3317  // v4i32 build_vector((extract_elt V, 1),
3318  // (extract_elt V, 3),
3319  // (extract_elt V, 5),
3320  // (extract_elt V, 7))
3321  // -->
3322  // v4i32 truncate (bitcast (shuffle<1,u,3,u,5,u,7,u> V, u) to v4i64)
3324  ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const {
3325  return false;
3326  }
3327 
3328  /// Return true if the target has native support for the specified value type
3329  /// and it is 'desirable' to use the type for the given node type. e.g. On x86
3330  /// i16 is legal, but undesirable since i16 instruction encodings are longer
3331  /// and some i16 instructions are slow.
3332  virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
3333  // By default, assume all legal types are desirable.
3334  return isTypeLegal(VT);
3335  }
3336 
3337  /// Return true if it is profitable for dag combiner to transform a floating
3338  /// point op of specified opcode to a equivalent op of an integer
3339  /// type. e.g. f32 load -> i32 load can be profitable on ARM.
3340  virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
3341  EVT /*VT*/) const {
3342  return false;
3343  }
3344 
3345  /// This method query the target whether it is beneficial for dag combiner to
3346  /// promote the specified node. If true, it should return the desired
3347  /// promotion type by reference.
3348  virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
3349  return false;
3350  }
3351 
3352  /// Return true if the target supports swifterror attribute. It optimizes
3353  /// loads and stores to reading and writing a specific register.
3354  virtual bool supportSwiftError() const {
3355  return false;
3356  }
3357 
3358  /// Return true if the target supports that a subset of CSRs for the given
3359  /// machine function is handled explicitly via copies.
3360  virtual bool supportSplitCSR(MachineFunction *MF) const {
3361  return false;
3362  }
3363 
3364  /// Perform necessary initialization to handle a subset of CSRs explicitly
3365  /// via copies. This function is called at the beginning of instruction
3366  /// selection.
3368  llvm_unreachable("Not Implemented");
3369  }
3370 
3371  /// Insert explicit copies in entry and exit blocks. We copy a subset of
3372  /// CSRs to virtual registers in the entry block, and copy them back to
3373  /// physical registers in the exit blocks. This function is called at the end
3374  /// of instruction selection.
3375  virtual void insertCopiesSplitCSR(
3377  const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
3378  llvm_unreachable("Not Implemented");
3379  }
3380 
3381  //===--------------------------------------------------------------------===//
3382  // Lowering methods - These methods must be implemented by targets so that
3383  // the SelectionDAGBuilder code knows how to lower these.
3384  //
3385 
3386  /// This hook must be implemented to lower the incoming (formal) arguments,
3387  /// described by the Ins array, into the specified DAG. The implementation
3388  /// should fill in the InVals array with legal-type argument values, and
3389  /// return the resulting token chain value.
3391  SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
3392  const SmallVectorImpl<ISD::InputArg> & /*Ins*/, const SDLoc & /*dl*/,
3393  SelectionDAG & /*DAG*/, SmallVectorImpl<SDValue> & /*InVals*/) const {
3394  llvm_unreachable("Not Implemented");
3395  }
3396 
3397  /// This structure contains all information that is necessary for lowering
3398  /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
3399  /// needs to lower a call, and targets will see this struct in their LowerCall
3400  /// implementation.
3403  Type *RetTy = nullptr;
3404  bool RetSExt : 1;
3405  bool RetZExt : 1;
3406  bool IsVarArg : 1;
3407  bool IsInReg : 1;
3408  bool DoesNotReturn : 1;
3410  bool IsConvergent : 1;
3411  bool IsPatchPoint : 1;
3412 
3413  // IsTailCall should be modified by implementations of
3414  // TargetLowering::LowerCall that perform tail call conversions.
3415  bool IsTailCall = false;
3416 
3417  // Is Call lowering done post SelectionDAG type legalization.
3418  bool IsPostTypeLegalization = false;
3419 
3420  unsigned NumFixedArgs = -1;
3423  ArgListTy Args;
3431 
3433  : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
3434  DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
3435  IsPatchPoint(false), DAG(DAG) {}
3436 
3438  DL = dl;
3439  return *this;
3440  }
3441 
3443  Chain = InChain;
3444  return *this;
3445  }
3446 
3447  // setCallee with target/module-specific attributes
3449  SDValue Target, ArgListTy &&ArgsList) {
3450  RetTy = ResultType;
3451  Callee = Target;
3452  CallConv = CC;
3453  NumFixedArgs = ArgsList.size();
3454  Args = std::move(ArgsList);
3455 
3457  &(DAG.getMachineFunction()), CC, Args);
3458  return *this;
3459  }
3460 
3462  SDValue Target, ArgListTy &&ArgsList) {
3463  RetTy = ResultType;
3464  Callee = Target;
3465  CallConv = CC;
3466  NumFixedArgs = ArgsList.size();
3467  Args = std::move(ArgsList);
3468  return *this;
3469  }
3470 
3472  SDValue Target, ArgListTy &&ArgsList,
3473  ImmutableCallSite Call) {
3474  RetTy = ResultType;
3475 
3476  IsInReg = Call.hasRetAttr(Attribute::InReg);
3477  DoesNotReturn =
3478  Call.doesNotReturn() ||
3479  (!Call.isInvoke() &&
3480  isa<UnreachableInst>(Call.getInstruction()->getNextNode()));
3481  IsVarArg = FTy->isVarArg();
3482  IsReturnValueUsed = !Call.getInstruction()->use_empty();
3483  RetSExt = Call.hasRetAttr(Attribute::SExt);
3484  RetZExt = Call.hasRetAttr(Attribute::ZExt);
3485 
3486  Callee = Target;
3487 
3488  CallConv = Call.getCallingConv();
3489  NumFixedArgs = FTy->getNumParams();
3490  Args = std::move(ArgsList);
3491 
3492  CS = Call;
3493 
3494  return *this;
3495  }
3496 
3498  IsInReg = Value;
3499  return *this;
3500  }
3501 
3503  DoesNotReturn = Value;
3504  return *this;
3505  }
3506 
3508  IsVarArg = Value;
3509  return *this;
3510  }
3511 
3513  IsTailCall = Value;
3514  return *this;
3515  }
3516 
3518  IsReturnValueUsed = !Value;
3519  return *this;
3520  }
3521 
3523  IsConvergent = Value;
3524  return *this;
3525  }
3526 
3528  RetSExt = Value;
3529  return *this;
3530  }
3531 
3533  RetZExt = Value;
3534  return *this;
3535  }
3536 
3538  IsPatchPoint = Value;
3539  return *this;
3540  }
3541 
3543  IsPostTypeLegalization = Value;
3544  return *this;
3545  }
3546 
3547  ArgListTy &getArgs() {
3548  return Args;
3549  }
3550  };
3551 
3552  /// This function lowers an abstract call to a function into an actual call.
3553  /// This returns a pair of operands. The first element is the return value
3554  /// for the function (if RetTy is not VoidTy). The second element is the
3555  /// outgoing token chain. It calls LowerCall to do the actual lowering.
3556  std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
3557 
3558  /// This hook must be implemented to lower calls into the specified
3559  /// DAG. The outgoing arguments to the call are described by the Outs array,
3560  /// and the values to be returned by the call are described by the Ins
3561  /// array. The implementation should fill in the InVals array with legal-type
3562  /// return values from the call, and return the resulting token chain value.
3563  virtual SDValue
3565  SmallVectorImpl<SDValue> &/*InVals*/) const {
3566  llvm_unreachable("Not Implemented");
3567  }
3568 
3569  /// Target-specific cleanup for formal ByVal parameters.
3570  virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
3571 
3572  /// This hook should be implemented to check whether the return values
3573  /// described by the Outs array can fit into the return registers. If false
3574  /// is returned, an sret-demotion is performed.
3575  virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
3576  MachineFunction &/*MF*/, bool /*isVarArg*/,
3577  const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
3578  LLVMContext &/*Context*/) const
3579  {
3580  // Return true by default to get preexisting behavior.
3581  return true;
3582  }
3583 
3584  /// This hook must be implemented to lower outgoing return values, described
3585  /// by the Outs array, into the specified DAG. The implementation should
3586  /// return the resulting token chain value.
3587  virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
3588  bool /*isVarArg*/,
3589  const SmallVectorImpl<ISD::OutputArg> & /*Outs*/,
3590  const SmallVectorImpl<SDValue> & /*OutVals*/,
3591  const SDLoc & /*dl*/,
3592  SelectionDAG & /*DAG*/) const {
3593  llvm_unreachable("Not Implemented");
3594  }
3595 
3596  /// Return true if result of the specified node is used by a return node
3597  /// only. It also compute and return the input chain for the tail call.
3598  ///
3599  /// This is used to determine whether it is possible to codegen a libcall as
3600  /// tail call at legalization time.
3601  virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
3602  return false;
3603  }
3604 
3605  /// Return true if the target may be able emit the call instruction as a tail
3606  /// call. This is used by optimization passes to determine if it's profitable
3607  /// to duplicate return instructions to enable tailcall optimization.
3608  virtual bool mayBeEmittedAsTailCall(const CallInst *) const {
3609  return false;
3610  }
3611 
3612  /// Return the builtin name for the __builtin___clear_cache intrinsic
3613  /// Default is to invoke the clear cache library call
3614  virtual const char * getClearCacheBuiltinName() const {
3615  return "__clear_cache";
3616  }
3617 
3618  /// Return the register ID of the name passed in. Used by named register
3619  /// global variables extension. There is no target-independent behaviour
3620  /// so the default action is to bail.
3621  virtual unsigned getRegisterByName(const char* RegName, EVT VT,
3622  SelectionDAG &DAG) const {
3623  report_fatal_error("Named registers not implemented for this target");
3624  }
3625 
3626  /// Return the type that should be used to zero or sign extend a
3627  /// zeroext/signext integer return value. FIXME: Some C calling conventions
3628  /// require the return type to be promoted, but this is not true all the time,
3629  /// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling
3630  /// conventions. The frontend should handle this and include all of the
3631  /// necessary information.
3633  ISD::NodeType /*ExtendKind*/) const {
3634  EVT MinVT = getRegisterType(Context, MVT::i32);
3635  return VT.bitsLT(MinVT) ? MinVT : VT;
3636  }
3637 
3638  /// For some targets, an LLVM struct type must be broken down into multiple
3639  /// simple types, but the calling convention specifies that the entire struct
3640  /// must be passed in a block of consecutive registers.
3641  virtual bool
3643  bool isVarArg) const {
3644  return false;
3645  }
3646 
3647  /// For most targets, an LLVM type must be broken down into multiple
3648  /// smaller types. Usually the halves are ordered according to the endianness
3649  /// but for some platform that would break. So this method will default to
3650  /// matching the endianness but can be overridden.
3651  virtual bool
3653  return DL.isLittleEndian();
3654  }
3655 
3656  /// Returns a 0 terminated array of registers that can be safely used as
3657  /// scratch registers.
3658  virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
3659  return nullptr;
3660  }
3661 
3662  /// This callback is used to prepare for a volatile or atomic load.
3663  /// It takes a chain node as input and returns the chain for the load itself.
3664  ///
3665  /// Having a callback like this is necessary for targets like SystemZ,
3666  /// which allows a CPU to reuse the result of a previous load indefinitely,
3667  /// even if a cache-coherent store is performed by another CPU. The default
3668  /// implementation does nothing.
3670  SelectionDAG &DAG) const {
3671  return Chain;
3672  }
3673 
3674  /// This callback is used to inspect load/store instructions and add
3675  /// target-specific MachineMemOperand flags to them. The default
3676  /// implementation does nothing.
3679  }
3680 
3681  /// This callback is invoked by the type legalizer to legalize nodes with an
3682  /// illegal operand type but legal result types. It replaces the
3683  /// LowerOperation callback in the type Legalizer. The reason we can not do
3684  /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
3685  /// use this callback.
3686  ///
3687  /// TODO: Consider merging with ReplaceNodeResults.
3688  ///
3689  /// The target places new result values for the node in Results (their number
3690  /// and types must exactly match those of the original return values of
3691  /// the node), or leaves Results empty, which indicates that the node is not
3692  /// to be custom lowered after all.
3693  /// The default implementation calls LowerOperation.
3694  virtual void LowerOperationWrapper(SDNode *N,
3696  SelectionDAG &DAG) const;
3697 
3698  /// This callback is invoked for operations that are unsupported by the
3699  /// target, which are registered to use 'custom' lowering, and whose defined
3700  /// values are all legal. If the target has no operations that require custom
3701  /// lowering, it need not implement this. The default implementation of this
3702  /// aborts.
3703  virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
3704 
3705  /// This callback is invoked when a node result type is illegal for the
3706  /// target, and the operation was registered to use 'custom' lowering for that
3707  /// result type. The target places new result values for the node in Results
3708  /// (their number and types must exactly match those of the original return
3709  /// values of the node), or leaves Results empty, which indicates that the
3710  /// node is not to be custom lowered after all.
3711  ///
3712  /// If the target has no operations that require custom lowering, it need not
3713  /// implement this. The default implementation aborts.
3714  virtual void ReplaceNodeResults(SDNode * /*N*/,
3715  SmallVectorImpl<SDValue> &/*Results*/,
3716  SelectionDAG &/*DAG*/) const {
3717  llvm_unreachable("ReplaceNodeResults not implemented for this target!");
3718  }
3719 
3720  /// This method returns the name of a target specific DAG node.
3721  virtual const char *getTargetNodeName(unsigned Opcode) const;
3722 
3723  /// This method returns a target specific FastISel object, or null if the
3724  /// target does not support "fast" ISel.
3726  const TargetLibraryInfo *) const {
3727  return nullptr;
3728  }
3729 
3730  bool verifyReturnAddressArgumentIsConstant(SDValue Op,
3731  SelectionDAG &DAG) const;
3732 
3733  //===--------------------------------------------------------------------===//
3734  // Inline Asm Support hooks
3735  //
3736 
3737  /// This hook allows the target to expand an inline asm call to be explicit
3738  /// llvm code if it wants to. This is useful for turning simple inline asms
3739  /// into LLVM intrinsics, which gives the compiler more information about the
3740  /// behavior of the code.
3741  virtual bool ExpandInlineAsm(CallInst *) const {
3742  return false;
3743  }
3744 
3746  C_Register, // Constraint represents specific register(s).
3747  C_RegisterClass, // Constraint represents any of register(s) in class.
3748  C_Memory, // Memory constraint.
3749  C_Immediate, // Requires an immediate.
3750  C_Other, // Something else.
3751  C_Unknown // Unsupported constraint.
3752  };
3753 
3755  // Generic weights.
3756  CW_Invalid = -1, // No match.
3757  CW_Okay = 0, // Acceptable.
3758  CW_Good = 1, // Good weight.
3759  CW_Better = 2, // Better weight.
3760  CW_Best = 3, // Best weight.
3761 
3762  // Well-known weights.
3763  CW_SpecificReg = CW_Okay, // Specific register operands.
3764  CW_Register = CW_Good, // Register operands.
3765  CW_Memory = CW_Better, // Memory operands.
3766  CW_Constant = CW_Best, // Constant operand.
3767  CW_Default = CW_Okay // Default or don't know type.
3768  };
3769 
3770  /// This contains information for each constraint that we are lowering.
3772  /// This contains the actual string for the code, like "m". TargetLowering
3773  /// picks the 'best' code from ConstraintInfo::Codes that most closely
3774  /// matches the operand.
3775  std::string ConstraintCode;
3776 
3777  /// Information about the constraint code, e.g. Register, RegisterClass,
3778  /// Memory, Other, Unknown.
3780 
3781  /// If this is the result output operand or a clobber, this is null,
3782  /// otherwise it is the incoming operand to the CallInst. This gets
3783  /// modified as the asm is processed.
3784  Value *CallOperandVal = nullptr;
3785 
3786  /// The ValueType for the operand value.
3787  MVT ConstraintVT = MVT::Other;
3788 
3789  /// Copy constructor for copying from a ConstraintInfo.
3791  : InlineAsm::ConstraintInfo(std::move(Info)) {}
3792 
3793  /// Return true of this is an input operand that is a matching constraint
3794  /// like "4".
3795  bool isMatchingInputConstraint() const;
3796 
3797  /// If this is an input matching constraint, this method returns the output
3798  /// operand it matches.
3799  unsigned getMatchedOperand() const;
3800  };
3801 
3802  using AsmOperandInfoVector = std::vector<AsmOperandInfo>;
3803 
3804  /// Split up the constraint string from the inline assembly value into the
3805  /// specific constraints and their prefixes, and also tie in the associated
3806  /// operand values. If this returns an empty vector, and if the constraint
3807  /// string itself isn't empty, there was an error parsing.
3808  virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
3809  const TargetRegisterInfo *TRI,
3810  ImmutableCallSite CS) const;
3811 
3812  /// Examine constraint type and operand type and determine a weight value.
3813  /// The operand object must already have been set up with the operand type.
3814  virtual ConstraintWeight getMultipleConstraintMatchWeight(
3815  AsmOperandInfo &info, int maIndex) const;
3816 
3817  /// Examine constraint string and operand type and determine a weight value.
3818  /// The operand object must already have been set up with the operand type.
3819  virtual ConstraintWeight getSingleConstraintMatchWeight(
3820  AsmOperandInfo &info, const char *constraint) const;
3821 
3822  /// Determines the constraint code and constraint type to use for the specific
3823  /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
3824  /// If the actual operand being passed in is available, it can be passed in as
3825  /// Op, otherwise an empty SDValue can be passed.
3826  virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3827  SDValue Op,
3828  SelectionDAG *DAG = nullptr) const;
3829 
3830  /// Given a constraint, return the type of constraint it is for this target.
3831  virtual ConstraintType getConstraintType(StringRef Constraint) const;
3832 
3833  /// Given a physical register constraint (e.g. {edx}), return the register
3834  /// number and the register class for the register.
3835  ///
3836  /// Given a register class constraint, like 'r', if this corresponds directly
3837  /// to an LLVM register class, return a register of 0 and the register class
3838  /// pointer.
3839  ///
3840  /// This should only be used for C_Register constraints. On error, this
3841  /// returns a register number of 0 and a null register class pointer.
3842  virtual std::pair<unsigned, const TargetRegisterClass *>
3843  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3844  StringRef Constraint, MVT VT) const;
3845 
3846  virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
3847  if (ConstraintCode == "i")
3848  return InlineAsm::Constraint_i;
3849  else if (ConstraintCode == "m")
3850  return InlineAsm::Constraint_m;
3852  }
3853 
3854  /// Try to replace an X constraint, which matches anything, with another that
3855  /// has more specific requirements based on the type of the corresponding
3856  /// operand. This returns null if there is no replacement to make.
3857  virtual const char *LowerXConstraint(EVT ConstraintVT) const;
3858 
3859  /// Lower the specified operand into the Ops vector. If it is invalid, don't
3860  /// add anything to Ops.
3861  virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
3862  std::vector<SDValue> &Ops,
3863  SelectionDAG &DAG) const;
3864 
3865  // Lower custom output constraints. If invalid, return SDValue().
3866  virtual SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag,
3867  SDLoc DL,
3868  const AsmOperandInfo &OpInfo,
3869  SelectionDAG &DAG) const;
3870 
3871  //===--------------------------------------------------------------------===//
3872  // Div utility functions
3873  //
3874  SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3875  SmallVectorImpl<SDNode *> &Created) const;
3876  SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3877  SmallVectorImpl<SDNode *> &Created) const;
3878 
3879  /// Targets may override this function to provide custom SDIV lowering for
3880  /// power-of-2 denominators. If the target returns an empty SDValue, LLVM
3881  /// assumes SDIV is expensive and replaces it with a series of other integer
3882  /// operations.
3883  virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
3884  SelectionDAG &DAG,
3885  SmallVectorImpl<SDNode *> &Created) const;
3886 
3887  /// Indicate whether this target prefers to combine FDIVs with the same
3888  /// divisor. If the transform should never be done, return zero. If the
3889  /// transform should be done, return the minimum number of divisor uses
3890  /// that must exist.
3891  virtual unsigned combineRepeatedFPDivisors() const {
3892  return 0;
3893  }
3894 
3895  /// Hooks for building estimates in place of slower divisions and square
3896  /// roots.
3897 
3898  /// Return either a square root or its reciprocal estimate value for the input
3899  /// operand.
3900  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3901  /// 'Enabled' as set by a potential default override attribute.
3902  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3903  /// refinement iterations required to generate a sufficient (though not
3904  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3905  /// The boolean UseOneConstNR output is used to select a Newton-Raphson
3906  /// algorithm implementation that uses either one or two constants.
3907  /// The boolean Reciprocal is used to select whether the estimate is for the
3908  /// square root of the input operand or the reciprocal of its square root.
3909  /// A target may choose to implement its own refinement within this function.
3910  /// If that's true, then return '0' as the number of RefinementSteps to avoid
3911  /// any further refinement of the estimate.
3912  /// An empty SDValue return means no estimate sequence can be created.
3914  int Enabled, int &RefinementSteps,
3915  bool &UseOneConstNR, bool Reciprocal) const {
3916  return SDValue();
3917  }
3918 
3919  /// Return a reciprocal estimate value for the input operand.
3920  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3921  /// 'Enabled' as set by a potential default override attribute.
3922  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3923  /// refinement iterations required to generate a sufficient (though not
3924  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3925  /// A target may choose to implement its own refinement within this function.
3926  /// If that's true, then return '0' as the number of RefinementSteps to avoid
3927  /// any further refinement of the estimate.
3928  /// An empty SDValue return means no estimate sequence can be created.
3930  int Enabled, int &RefinementSteps) const {
3931  return SDValue();
3932  }
3933 
3934  //===--------------------------------------------------------------------===//
3935  // Legalization utility functions
3936  //
3937 
3938  /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes,
3939  /// respectively, each computing an n/2-bit part of the result.
3940  /// \param Result A vector that will be filled with the parts of the result
3941  /// in little-endian order.
3942  /// \param LL Low bits of the LHS of the MUL. You can use this parameter
3943  /// if you want to control how low bits are extracted from the LHS.
3944  /// \param LH High bits of the LHS of the MUL. See LL for meaning.
3945  /// \param RL Low bits of the RHS of the MUL. See LL for meaning
3946  /// \param RH High bits of the RHS of the MUL. See LL for meaning.
3947  /// \returns true if the node has been expanded, false if it has not
3948  bool expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS,
3949  SDValue RHS, SmallVectorImpl<SDValue> &Result, EVT HiLoVT,
3951  SDValue LL = SDValue(), SDValue LH = SDValue(),
3952  SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3953 
3954  /// Expand a MUL into two nodes. One that computes the high bits of
3955  /// the result and one that computes the low bits.
3956  /// \param HiLoVT The value type to use for the Lo and Hi nodes.
3957  /// \param LL Low bits of the LHS of the MUL. You can use this parameter
3958  /// if you want to control how low bits are extracted from the LHS.
3959  /// \param LH High bits of the LHS of the MUL. See LL for meaning.
3960  /// \param RL Low bits of the RHS of the MUL. See LL for meaning
3961  /// \param RH High bits of the RHS of the MUL. See LL for meaning.
3962  /// \returns true if the node has been expanded. false if it has not
3963  bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
3964  SelectionDAG &DAG, MulExpansionKind Kind,
3965  SDValue LL = SDValue(), SDValue LH = SDValue(),
3966  SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3967 
3968  /// Expand funnel shift.
3969  /// \param N Node to expand
3970  /// \param Result output after conversion
3971  /// \returns True, if the expansion was successful, false otherwise
3972  bool expandFunnelShift(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3973 
3974  /// Expand rotations.
3975  /// \param N Node to expand
3976  /// \param Result output after conversion
3977  /// \returns True, if the expansion was successful, false otherwise
3978  bool expandROT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3979 
3980  /// Expand float(f32) to SINT(i64) conversion
3981  /// \param N Node to expand
3982  /// \param Result output after conversion
3983  /// \returns True, if the expansion was successful, false otherwise
3984  bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3985 
3986  /// Expand float to UINT conversion
3987  /// \param N Node to expand
3988  /// \param Result output after conversion
3989  /// \returns True, if the expansion was successful, false otherwise
3990  bool expandFP_TO_UINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3991 
3992  /// Expand UINT(i64) to double(f64) conversion
3993  /// \param N Node to expand
3994  /// \param Result output after conversion
3995  /// \returns True, if the expansion was successful, false otherwise
3996  bool expandUINT_TO_FP(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3997 
3998  /// Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs.
3999  SDValue expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) const;
4000 
4001  /// Expand CTPOP nodes. Expands vector/scalar CTPOP nodes,
4002  /// vector nodes can only succeed if all operations are legal/custom.
4003  /// \param N Node to expand
4004  /// \param Result output after conversion
4005  /// \returns True, if the expansion was successful, false otherwise
4006  bool expandCTPOP(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
4007 
4008  /// Expand CTLZ/CTLZ_ZERO_UNDEF nodes. Expands vector/scalar CTLZ nodes,
4009  /// vector nodes can only succeed if all operations are legal/custom.
4010  /// \param N Node to expand
4011  /// \param Result output after conversion
4012  /// \returns True, if the expansion was successful, false otherwise
4013  bool expandCTLZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
4014 
4015  /// Expand CTTZ/CTTZ_ZERO_UNDEF nodes. Expands vector/scalar CTTZ nodes,
4016  /// vector nodes can only succeed if all operations are legal/custom.
4017  /// \param N Node to expand
4018  /// \param Result output after conversion
4019  /// \returns True, if the expansion was successful, false otherwise
4020  bool expandCTTZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
4021 
4022  /// Expand ABS nodes. Expands vector/scalar ABS nodes,
4023  /// vector nodes can only succeed if all operations are legal/custom.
4024  /// (ABS x) -> (XOR (ADD x, (SRA x, type_size)), (SRA x, type_size))
4025  /// \param N Node to expand
4026  /// \param Result output after conversion
4027  /// \returns True, if the expansion was successful, false otherwise
4028  bool expandABS(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
4029 
4030  /// Turn load of vector type into a load of the individual elements.
4031  /// \param LD load to expand
4032  /// \returns MERGE_VALUEs of the scalar loads with their chains.
4033  SDValue scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const;
4034 
4035  // Turn a store of a vector type into stores of the individual elements.
4036  /// \param ST Store with a vector value type
4037  /// \returns MERGE_VALUs of the individual store chains.
4039 
4040  /// Expands an unaligned load to 2 half-size loads for an integer, and
4041  /// possibly more for vectors.
4042  std::pair<SDValue, SDValue> expandUnalignedLoad(LoadSDNode *LD,
4043  SelectionDAG &DAG) const;
4044 
4045  /// Expands an unaligned store to 2 half-size stores for integer values, and
4046  /// possibly more for vectors.
4047  SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const;
4048 
4049  /// Increments memory address \p Addr according to the type of the value
4050  /// \p DataVT that should be stored. If the data is stored in compressed
4051  /// form, the memory address should be incremented according to the number of
4052  /// the stored elements. This number is equal to the number of '1's bits
4053  /// in the \p Mask.
4054  /// \p DataVT is a vector type. \p Mask is a vector value.
4055  /// \p DataVT and \p Mask have the same number of vector elements.
4056  SDValue IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL,
4057  EVT DataVT, SelectionDAG &DAG,
4058  bool IsCompressedMemory) const;
4059 
4060  /// Get a pointer to vector element \p Idx located in memory for a vector of
4061  /// type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of
4062  /// bounds the returned pointer is unspecified, but will be within the vector
4063  /// bounds.
4064  SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
4065  SDValue Index) const;
4066 
4067  /// Method for building the DAG expansion of ISD::[US][ADD|SUB]SAT. This
4068  /// method accepts integers as its arguments.
4069  SDValue expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const;
4070 
4071  /// Method for building the DAG expansion of ISD::SMULFIX. This method accepts
4072  /// integers as its arguments.
4073  SDValue expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) const;
4074 
4075  /// Method for building the DAG expansion of ISD::U(ADD|SUB)O. Expansion
4076  /// always suceeds and populates the Result and Overflow arguments.
4077  void expandUADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow,
4078  SelectionDAG &DAG) const;
4079 
4080  /// Method for building the DAG expansion of ISD::S(ADD|SUB)O. Expansion
4081  /// always suceeds and populates the Result and Overflow arguments.
4082  void expandSADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow,
4083  SelectionDAG &DAG) const;
4084 
4085  /// Method for building the DAG expansion of ISD::[US]MULO. Returns whether
4086  /// expansion was successful and populates the Result and Overflow arguments.
4087  bool expandMULO(SDNode *Node, SDValue &Result, SDValue &Overflow,
4088  SelectionDAG &DAG) const;
4089 
4090  /// Expand a VECREDUCE_* into an explicit calculation. If Count is specified,
4091  /// only the first Count elements of the vector are used.
4092  SDValue expandVecReduce(SDNode *Node, SelectionDAG &DAG) const;
4093 
4094  //===--------------------------------------------------------------------===//
4095  // Instruction Emitting Hooks
4096  //
4097 
4098  /// This method should be implemented by targets that mark instructions with
4099  /// the 'usesCustomInserter' flag. These instructions are special in various
4100  /// ways, which require special support to insert. The specified MachineInstr
4101  /// is created but not inserted into any basic blocks, and this method is
4102  /// called to expand it into a sequence of instructions, potentially also
4103  /// creating new basic blocks and control flow.
4104  /// As long as the returned basic block is different (i.e., we created a new
4105  /// one), the custom inserter is free to modify the rest of \p MBB.
4106  virtual MachineBasicBlock *
4107  EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
4108 
4109  /// This method should be implemented by targets that mark instructions with
4110  /// the 'hasPostISelHook' flag. These instructions must be adjusted after
4111  /// instruction selection by target hooks. e.g. To fill in optional defs for
4112  /// ARM 's' setting instructions.
4113  virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,
4114  SDNode *Node) const;
4115 
4116  /// If this function returns true, SelectionDAGBuilder emits a
4117  /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
4118  virtual bool useLoadStackGuardNode() const {
4119  return false;
4120  }
4121 
4123  const SDLoc &DL) const {
4124  llvm_unreachable("not implemented for this target");
4125  }
4126 
4127  /// Lower TLS global address SDNode for target independent emulated TLS model.
4128  virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
4129  SelectionDAG &DAG) const;
4130 
4131  /// Expands target specific indirect branch for the case of JumpTable
4132  /// expanasion.
4134  SelectionDAG &DAG) const {
4135  return DAG.getNode(ISD::BRIND, dl, MVT::Other, Value, Addr);
4136  }
4137 
4138  // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
4139  // If we're comparing for equality to zero and isCtlzFast is true, expose the
4140  // fact that this can be implemented as a ctlz/srl pair, so that the dag
4141  // combiner can fold the new nodes.
4142  SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;
4143 
4144 private:
4145  SDValue foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
4146  const SDLoc &DL, DAGCombinerInfo &DCI) const;
4147  SDValue foldSetCCWithBinOp(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
4148  const SDLoc &DL, DAGCombinerInfo &DCI) const;
4149 
4150  SDValue optimizeSetCCOfSignedTruncationCheck(EVT SCCVT, SDValue N0,
4151  SDValue N1, ISD::CondCode Cond,
4152  DAGCombinerInfo &DCI,
4153  const SDLoc &DL) const;
4154 
4155  // (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0
4156  SDValue optimizeSetCCByHoistingAndByConstFromLogicalShift(
4157  EVT SCCVT, SDValue N0, SDValue N1C, ISD::CondCode Cond,
4158  DAGCombinerInfo &DCI, const SDLoc &DL) const;
4159 
4160  SDValue prepareUREMEqFold(EVT SETCCVT, SDValue REMNode,
4161  SDValue CompTargetNode, ISD::CondCode Cond,
4162  DAGCombinerInfo &DCI, const SDLoc &DL,
4163  SmallVectorImpl<SDNode *> &Created) const;
4164  SDValue buildUREMEqFold(EVT SETCCVT, SDValue REMNode, SDValue CompTargetNode,
4165  ISD::CondCode Cond, DAGCombinerInfo &DCI,
4166  const SDLoc &DL) const;
4167 
4168  SDValue prepareSREMEqFold(EVT SETCCVT, SDValue REMNode,
4169  SDValue CompTargetNode, ISD::CondCode Cond,
4170  DAGCombinerInfo &DCI, const SDLoc &DL,
4171  SmallVectorImpl<SDNode *> &Created) const;
4172  SDValue buildSREMEqFold(EVT SETCCVT, SDValue REMNode, SDValue CompTargetNode,
4173  ISD::CondCode Cond, DAGCombinerInfo &DCI,
4174  const SDLoc &DL) const;
4175 };
4176 
4177 /// Given an LLVM IR type and return type attributes, compute the return value
4178 /// EVTs and flags, and optionally also the offsets, if the return value is
4179 /// being lowered to memory.
4182  const TargetLowering &TLI, const DataLayout &DL);
4183 
4184 } // end namespace llvm
4185 
4186 #endif // LLVM_CODEGEN_TARGETLOWERING_H
virtual AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass...
LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return how this load with extension should be treated: either it is legal, needs to be promoted to a ...
virtual bool isJumpTableRelative() const
uint64_t CallInst * C
X = FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:562
static MVT getIntegerVT(unsigned BitWidth)
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:913
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:622
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
EVT getValueType() const
Return the ValueType of the referenced return value.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
bool isInteger() const
Return true if this is an integer or a vector integer type.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
virtual bool canMergeStoresTo(unsigned AS, EVT MemVT, const SelectionDAG &DAG) const
Returns if it&#39;s reasonable to merge stores to MemVT size.
unsigned getIndexSizeInBits(unsigned AS) const
Size in bits of index used for address calculation in getelementptr.
Definition: DataLayout.h:399
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:300
bool usesUnderscoreLongJmp() const
Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
unsigned MaxLoadsPerMemcmpOptSize
Likewise for functions with the OptSize attribute.
LLVMContext & Context
virtual bool shouldInsertFencesForAtomic(const Instruction *I) const
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic...
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
Atomic ordering constants.
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:288
virtual SDValue expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr, SelectionDAG &DAG) const
Expands target specific indirect branch for the case of JumpTable expanasion.
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isOperationCustom(unsigned Op, EVT VT) const
Return true if the operation uses custom lowering, regardless of whether the type is legal or not...
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0...
Definition: ISDOpcodes.h:633
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
virtual const TargetRegisterClass * getRepRegClassFor(MVT VT) const
Return the &#39;representative&#39; register class for the specified value type.
virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const
Return if the target supports combining a chain like:
bool hasOptSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:622
virtual bool reduceSelectOfFPConstantLoads(bool IsFPSetCC) const
Return true if it is profitable to convert a select of FP constants into a constant pool load whose a...
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
An instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:530
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:284
CallLoweringInfo & setIsPostTypeLegalization(bool Value=true)
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
void setJumpBufAlignment(unsigned Align)
Set the target&#39;s required jmp_buf buffer alignment (in bytes); default is 0.
bool usesUnderscoreSetJmp() const
Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
virtual unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const
Return the register ID of the name passed in.
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:222
virtual unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
virtual bool enableAggressiveFMAFusion(EVT VT) const
Return true if target always beneficiates from combining into FMA for a given value type...
virtual bool getPreIndexedAddressParts(SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node&#39;s...
virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const
Hooks for building estimates in place of slower divisions and square roots.
This class represents a function call, abstracting a target machine&#39;s calling convention.
virtual bool isFNegFree(EVT VT) const
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
virtual unsigned combineRepeatedFPDivisors() const
Indicate whether this target prefers to combine FDIVs with the same divisor.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
virtual bool isExtractVecEltCheap(EVT VT, unsigned Index) const
Return true if extraction of a scalar element from the given vector type at the given index is cheap...
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:250
static ISD::NodeType getExtendForContent(BooleanContent Content)
unsigned getVectorNumElements() const
virtual bool isSelectSupported(SelectSupportKind) const
Function Alias Analysis Results
bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const
Return true if lowering to a bit test is suitable for a set of case clusters which contains NumDests ...
This instruction constructs a fixed permutation of two input vectors.
virtual bool isCommutativeBinOp(unsigned Opcode) const
Returns true if the opcode is a commutative binary operation.
virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) const
bool hasRetAttr(Attribute::AttrKind Kind) const
Return true if this return value has the given attribute.
Definition: CallSite.h:380
unsigned getMaxStoresPerMemset(bool OptSize) const
Get maximum # of store operations permitted for llvm.memset.
virtual void HandleByVal(CCState *, unsigned &, unsigned) const
Target-specific cleanup for formal ByVal parameters.
CallLoweringInfo & setNoReturn(bool Value=true)
virtual bool isSafeMemOpType(MVT) const
Returns true if it&#39;s safe to use load / store of the specified type to expand memcpy / memset inline...
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:389
Constrained versions of the binary floating point operators.
Definition: ISDOpcodes.h:293
LegalizeAction getIndexedStoreAction(unsigned IdxMode, MVT VT) const
Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger ...
bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const
Return true if the specified store with truncation is legal on this target.
unsigned const TargetRegisterInfo * TRI
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:140
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1100
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
bool hasMultipleConditionRegisters() const
Return true if multiple condition registers are available.
block Block Frequency true
An instruction for reading from memory.
Definition: Instructions.h:167
virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass...
virtual bool mayBeEmittedAsTailCall(const CallInst *) const
Return true if the target may be able emit the call instruction as a tail call.
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
Return true if the target has native support for the specified value type and it is &#39;desirable&#39; to us...
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:408
bool hasExtractBitsInsn() const
Return true if the target has BitExtract instructions.
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:693
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
virtual bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AddrSpace) const
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
LegalizeAction getFixedPointOperationAction(unsigned Op, EVT VT, unsigned Scale) const
Some fixed point operations may be natively supported by the target but only for specific scales...
unsigned getJumpBufAlignment() const
Returns the target&#39;s jmp_buf alignment in bytes (if never set, the default is 0)
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it...
CallLoweringInfo & setDiscardResult(bool Value=true)
virtual StringRef getStackProbeSymbolName(MachineFunction &MF) const
Returns the name of the symbol used to emit stack probes or the empty string if not applicable...
uint64_t High
virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:38
bool isValid() const
Return true if this is a valid simple valuetype.
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal on this target.
virtual Value * emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const
Perform a masked atomicrmw using a target-specific intrinsic.
CallLoweringInfo & setCallee(Type *ResultType, FunctionType *FTy, SDValue Target, ArgListTy &&ArgsList, ImmutableCallSite Call)
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:129
virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const
Return true if an fpext operation is free (for instance, because single-precision floating-point numb...
virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
CallingConv::ID getCallingConv() const
Get the calling convention of the call.
Definition: CallSite.h:320
virtual bool isCtlzFast() const
Return true if ctlz instruction is fast.
virtual bool isProfitableToCombineMinNumMaxNum(EVT VT) const
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
virtual bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:135
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
unsigned getAllocaAddrSpace() const
Definition: DataLayout.h:270
void * PointerTy
Definition: GenericValue.h:21
virtual LLT getOptimalMemOpLLT(uint64_t, unsigned, unsigned, bool, bool, bool, const AttributeList &) const
LLT returning variant.
bool hasOneUse() const
Return true if there is exactly one use of this node.
A description of a memory reference used in the backend.
Definition: BitVector.h:937
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
Shift and rotation operations.
Definition: ISDOpcodes.h:434
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:261
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
virtual bool isSupportedFixedPointOperation(unsigned Op, EVT VT, unsigned Scale) const
Custom method defined by each target to indicate if an operation which may require a scale is support...
CallLoweringInfo & setVarArg(bool Value=true)
CallLoweringInfo & setChain(SDValue InChain)
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:279
virtual uint8_t getRepRegClassCostFor(MVT VT) const
Return the cost of the &#39;representative&#39; register class for the specified value type.
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:779
virtual bool useLoadStackGuardNode() const
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn&#39;t supported on the target and indicate what to d...
This file contains the simple types necessary to represent the attributes associated with functions a...
virtual bool mergeStoresAfterLegalization(EVT MemVT) const
Allow store merging for the specified type after legalization in addition to before legalization...
SimpleValueType SimpleTy
void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth)
Tells the code generator which bitwidths to bypass.
virtual bool isVectorShiftByScalarCheap(Type *Ty) const
Return true if it&#39;s significantly cheaper to shift a vector by a uniform scalar than by an amount whi...
bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return true if the specified load with extension is legal or custom on this target.
bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const
When splitting a value of the specified type into parts, does the Lo or Hi part come first...
virtual bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT, bool IsSigned) const
Return true if it is more correct/profitable to use strict FP_TO_INT conversion operations - canonica...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const
Use bitwise logic to make pairs of compares more efficient.
virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:413
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const
This file implements a class to represent arbitrary precision integral constant values and operations...
virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const
Return true if it&#39;s free to truncate a value of type FromTy to type ToTy.
SmallVector< ISD::InputArg, 32 > Ins
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
virtual bool ShouldShrinkFPConstant(EVT) const
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const
This callback is used to prepare for a volatile or atomic load.
Context object for machine code objects.
Definition: MCContext.h:65
virtual void ReplaceNodeResults(SDNode *, SmallVectorImpl< SDValue > &, SelectionDAG &) const
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
InstrTy * getInstruction() const
Definition: CallSite.h:96
virtual EVT getOptimalMemOpType(uint64_t, unsigned, unsigned, bool, bool, bool, const AttributeList &) const
Returns the target specific optimal type for load and store operations as a result of memset...
virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const
Certain targets have context senstive alignment requirements, where one type has the alignment requir...
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:66
Class to represent function types.
Definition: DerivedTypes.h:103
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
#define UINT64_MAX
Definition: DataTypes.h:83
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:410
static cl::opt< unsigned > MaxLoadsPerMemcmpOptSize("max-loads-per-memcmp-opt-size", cl::Hidden, cl::desc("Set maximum number of loads used in expanded memcmp for -Os/Oz"))
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
unsigned MaxLoadsPerMemcmp
Specify maximum number of load instructions per memcmp call.
virtual bool supportSwiftError() const
Return true if the target supports swifterror attribute.
virtual bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use *> &Ops) const
Return true if sinking I&#39;s operands to the same basic block as I is profitable, e.g.
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
bool isVarArg() const
Definition: DerivedTypes.h:123
SmallVector< ISD::OutputArg, 32 > Outs
virtual bool isCheapToSpeculateCtlz() const
Return true if it is cheap to speculate a call to intrinsic ctlz.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
virtual bool hasBitTest(SDValue X, SDValue Y) const
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
bool isLittleEndian() const
Layout endianness...
Definition: DataLayout.h:233
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:125
CallLoweringInfo & setZExtResult(bool Value=true)
BooleanContent getBooleanContents(EVT Type) const
virtual bool shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout &DL) const
For most targets, an LLVM type must be broken down into multiple smaller types.
An instruction for storing to memory.
Definition: Instructions.h:320
unsigned getPrefFunctionAlignment() const
Return the preferred function alignment.
MVT getRegisterType(LLVMContext &Context, EVT VT) const
Return the type of registers that this ValueType will eventually require.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:1012
virtual const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const
virtual bool isCheapToSpeculateCttz() const
Return true if it is cheap to speculate a call to intrinsic cttz.
X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:323
virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const
Lower an interleaved store to target specific intrinsics.
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
Value * getOperand(unsigned i) const
Definition: User.h:169
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Class to represent pointers.
Definition: DerivedTypes.h:544
This class is used to represent ISD::STORE nodes.
void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx)
static cl::opt< unsigned > MaxLoadsPerMemcmp("max-loads-per-memcmp", cl::Hidden, cl::desc("Set maximum number of loads used in expanded memcmp"))
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
bool isJumpExpensive() const
Return true if Flow Control is an expensive operation that should be avoided.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:131
virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const
Return true if the target can combine store(extractelement VectorTy, Idx).
virtual bool alignLoopsWithOptSize() const
Should loops be aligned even when the function is marked OptSize (but not MinSize).
static SDValue scalarizeVectorStore(StoreSDNode *Store, MVT StoreVT, SelectionDAG &DAG)
Scalarize a vector store, bitcasting to TargetVT to determine the scalar type.
virtual Value * emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const
Perform a store-conditional operation to Addr.
EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
std::vector< AsmOperandInfo > AsmOperandInfoVector
virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT) const
Try to convert math with an overflow comparison into the corresponding DAG node operation.
MVT getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the MVT corresponding to this LLVM type. See getValueType.
virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range) const
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumC...
virtual bool getAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value *> &, Type *&) const
CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the add...
unsigned const MachineRegisterInfo * MRI
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
virtual unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception address on entry to an ...
Machine Value Type.
DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
CallLoweringInfo & setIsPatchPoint(bool Value=true)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
void setJumpBufSize(unsigned Size)
Set the target&#39;s required jmp_buf buffer size (in bytes); default is 200.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
Simple binary floating point operators.
Definition: ISDOpcodes.h:287
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
virtual Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const
Perform a masked cmpxchg using a target-specific intrinsic.
virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const
virtual ISD::NodeType getExtendForAtomicOps() const
Returns how the platform&#39;s atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
This is an important base class in LLVM.
Definition: Constant.h:41
virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const
Return true if it is beneficial to convert a load of a constant to just the constant itself...
bool isFloatingPointOperation() const
Definition: Instructions.h:825
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:987
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, unsigned Align=1, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *=nullptr) const
Determine if the target supports unaligned memory accesses.