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TargetLowering.h
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1 //===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file describes how to lower LLVM code to machine code. This has two
11 /// main components:
12 ///
13 /// 1. Which ValueTypes are natively supported by the target.
14 /// 2. Which operations are supported for supported ValueTypes.
15 /// 3. Cost thresholds for alternative implementations of certain operations.
16 ///
17 /// In addition it has a few other components, like information about FP
18 /// immediates.
19 ///
20 //===----------------------------------------------------------------------===//
21 
22 #ifndef LLVM_CODEGEN_TARGETLOWERING_H
23 #define LLVM_CODEGEN_TARGETLOWERING_H
24 
25 #include "llvm/ADT/APInt.h"
26 #include "llvm/ADT/ArrayRef.h"
27 #include "llvm/ADT/DenseMap.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/StringRef.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/CallSite.h"
41 #include "llvm/IR/CallingConv.h"
42 #include "llvm/IR/DataLayout.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/IRBuilder.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instruction.h"
48 #include "llvm/IR/Instructions.h"
49 #include "llvm/IR/Type.h"
50 #include "llvm/MC/MCRegisterInfo.h"
52 #include "llvm/Support/Casting.h"
56 #include <algorithm>
57 #include <cassert>
58 #include <climits>
59 #include <cstdint>
60 #include <iterator>
61 #include <map>
62 #include <string>
63 #include <utility>
64 #include <vector>
65 
66 namespace llvm {
67 
68 class BranchProbability;
69 class CCState;
70 class CCValAssign;
71 class Constant;
72 class FastISel;
73 class FunctionLoweringInfo;
74 class GlobalValue;
75 class IntrinsicInst;
76 struct KnownBits;
77 class LLVMContext;
78 class MachineBasicBlock;
79 class MachineFunction;
80 class MachineInstr;
81 class MachineJumpTableInfo;
82 class MachineLoop;
83 class MachineRegisterInfo;
84 class MCContext;
85 class MCExpr;
86 class Module;
87 class TargetRegisterClass;
88 class TargetLibraryInfo;
89 class TargetRegisterInfo;
90 class Value;
91 
92 namespace Sched {
93 
94  enum Preference {
95  None, // No preference
96  Source, // Follow source order.
97  RegPressure, // Scheduling for lowest register pressure.
98  Hybrid, // Scheduling for both latency and register pressure.
99  ILP, // Scheduling for ILP in low register pressure mode.
100  VLIW // Scheduling for VLIW targets.
101  };
102 
103 } // end namespace Sched
104 
105 /// This base class for TargetLowering contains the SelectionDAG-independent
106 /// parts that can be used from the rest of CodeGen.
108 public:
109  /// This enum indicates whether operations are valid for a target, and if not,
110  /// what action should be used to make them valid.
111  enum LegalizeAction : uint8_t {
112  Legal, // The target natively supports this operation.
113  Promote, // This operation should be executed in a larger type.
114  Expand, // Try to expand this to other ops, otherwise use a libcall.
115  LibCall, // Don't try to expand this to other ops, always use a libcall.
116  Custom // Use the LowerOperation hook to implement custom lowering.
117  };
118 
119  /// This enum indicates whether a types are legal for a target, and if not,
120  /// what action should be used to make them valid.
121  enum LegalizeTypeAction : uint8_t {
122  TypeLegal, // The target natively supports this type.
123  TypePromoteInteger, // Replace this integer with a larger one.
124  TypeExpandInteger, // Split this integer into two of half the size.
125  TypeSoftenFloat, // Convert this float to a same size integer type,
126  // if an operation is not supported in target HW.
127  TypeExpandFloat, // Split this float into two of half the size.
128  TypeScalarizeVector, // Replace this one-element vector with its element.
129  TypeSplitVector, // Split this vector into two of half the size.
130  TypeWidenVector, // This vector should be widened into a larger vector.
131  TypePromoteFloat // Replace this float with a larger one.
132  };
133 
134  /// LegalizeKind holds the legalization kind that needs to happen to EVT
135  /// in order to type-legalize it.
136  using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;
137 
138  /// Enum that describes how the target represents true/false values.
140  UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
141  ZeroOrOneBooleanContent, // All bits zero except for bit 0.
142  ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
143  };
144 
145  /// Enum that describes what type of support for selects the target has.
147  ScalarValSelect, // The target supports scalar selects (ex: cmov).
148  ScalarCondVectorVal, // The target supports selects with a scalar condition
149  // and vector values (ex: cmov).
150  VectorMaskSelect // The target supports vector selects with a vector
151  // mask (ex: x86 blends).
152  };
153 
154  /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
155  /// to, if at all. Exists because different targets have different levels of
156  /// support for these atomic instructions, and also have different options
157  /// w.r.t. what they should expand to.
158  enum class AtomicExpansionKind {
159  None, // Don't expand the instruction.
160  LLSC, // Expand the instruction into loadlinked/storeconditional; used
161  // by ARM/AArch64.
162  LLOnly, // Expand the (load) instruction into just a load-linked, which has
163  // greater atomic guarantees than a normal load.
164  CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
165  MaskedIntrinsic, // Use a target-specific intrinsic for the LL/SC loop.
166  };
167 
168  /// Enum that specifies when a multiplication should be expanded.
169  enum class MulExpansionKind {
170  Always, // Always expand the instruction.
171  OnlyLegalOrCustom, // Only expand when the resulting instructions are legal
172  // or custom.
173  };
174 
175  class ArgListEntry {
176  public:
177  Value *Val = nullptr;
179  Type *Ty = nullptr;
180  bool IsSExt : 1;
181  bool IsZExt : 1;
182  bool IsInReg : 1;
183  bool IsSRet : 1;
184  bool IsNest : 1;
185  bool IsByVal : 1;
186  bool IsInAlloca : 1;
187  bool IsReturned : 1;
188  bool IsSwiftSelf : 1;
189  bool IsSwiftError : 1;
190  uint16_t Alignment = 0;
191 
193  : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
194  IsNest(false), IsByVal(false), IsInAlloca(false), IsReturned(false),
195  IsSwiftSelf(false), IsSwiftError(false) {}
196 
197  void setAttributes(const CallBase *Call, unsigned ArgIdx);
198 
199  void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx) {
200  return setAttributes(cast<CallBase>(CS->getInstruction()), ArgIdx);
201  }
202  };
203  using ArgListTy = std::vector<ArgListEntry>;
204 
205  virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
206  ArgListTy &Args) const {};
207 
209  switch (Content) {
210  case UndefinedBooleanContent:
211  // Extend by adding rubbish bits.
212  return ISD::ANY_EXTEND;
213  case ZeroOrOneBooleanContent:
214  // Extend by adding zero bits.
215  return ISD::ZERO_EXTEND;
216  case ZeroOrNegativeOneBooleanContent:
217  // Extend by copying the sign bit.
218  return ISD::SIGN_EXTEND;
219  }
220  llvm_unreachable("Invalid content kind");
221  }
222 
223  /// NOTE: The TargetMachine owns TLOF.
224  explicit TargetLoweringBase(const TargetMachine &TM);
225  TargetLoweringBase(const TargetLoweringBase &) = delete;
226  TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
227  virtual ~TargetLoweringBase() = default;
228 
229 protected:
230  /// Initialize all of the actions to default values.
231  void initActions();
232 
233 public:
234  const TargetMachine &getTargetMachine() const { return TM; }
235 
236  virtual bool useSoftFloat() const { return false; }
237 
238  /// Return the pointer type for the given address space, defaults to
239  /// the pointer type from the data layout.
240  /// FIXME: The default needs to be removed once all the code is updated.
241  virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
243  }
244 
245  /// Return the in-memory pointer type for the given address space, defaults to
246  /// the pointer type from the data layout. FIXME: The default needs to be
247  /// removed once all the code is updated.
248  MVT getPointerMemTy(const DataLayout &DL, uint32_t AS = 0) const {
250  }
251 
252  /// Return the type for frame index, which is determined by
253  /// the alloca address space specified through the data layout.
254  MVT getFrameIndexTy(const DataLayout &DL) const {
255  return getPointerTy(DL, DL.getAllocaAddrSpace());
256  }
257 
258  /// Return the type for operands of fence.
259  /// TODO: Let fence operands be of i32 type and remove this.
260  virtual MVT getFenceOperandTy(const DataLayout &DL) const {
261  return getPointerTy(DL);
262  }
263 
264  /// EVT is not used in-tree, but is used by out-of-tree target.
265  /// A documentation for this function would be nice...
266  virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
267 
268  EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL,
269  bool LegalTypes = true) const;
270 
271  /// Returns the type to be used for the index operand of:
272  /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
273  /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
274  virtual MVT getVectorIdxTy(const DataLayout &DL) const {
275  return getPointerTy(DL);
276  }
277 
278  virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
279  return true;
280  }
281 
282  /// Return true if it is profitable to convert a select of FP constants into
283  /// a constant pool load whose address depends on the select condition. The
284  /// parameter may be used to differentiate a select with FP compare from
285  /// integer compare.
286  virtual bool reduceSelectOfFPConstantLoads(bool IsFPSetCC) const {
287  return true;
288  }
289 
290  /// Return true if multiple condition registers are available.
292  return HasMultipleConditionRegisters;
293  }
294 
295  /// Return true if the target has BitExtract instructions.
296  bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
297 
298  /// Return the preferred vector type legalization action.
301  // The default action for one element vectors is to scalarize
302  if (VT.getVectorNumElements() == 1)
303  return TypeScalarizeVector;
304  // The default action for an odd-width vector is to widen.
305  if (!VT.isPow2VectorType())
306  return TypeWidenVector;
307  // The default action for other vectors is to promote
308  return TypePromoteInteger;
309  }
310 
311  // There are two general methods for expanding a BUILD_VECTOR node:
312  // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
313  // them together.
314  // 2. Build the vector on the stack and then load it.
315  // If this function returns true, then method (1) will be used, subject to
316  // the constraint that all of the necessary shuffles are legal (as determined
317  // by isShuffleMaskLegal). If this function returns false, then method (2) is
318  // always used. The vector type, and the number of defined values, are
319  // provided.
320  virtual bool
322  unsigned DefinedValues) const {
323  return DefinedValues < 3;
324  }
325 
326  /// Return true if integer divide is usually cheaper than a sequence of
327  /// several shifts, adds, and multiplies for this target.
328  /// The definition of "cheaper" may depend on whether we're optimizing
329  /// for speed or for size.
330  virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
331 
332  /// Return true if the target can handle a standalone remainder operation.
333  virtual bool hasStandaloneRem(EVT VT) const {
334  return true;
335  }
336 
337  /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
338  virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const {
339  // Default behavior is to replace SQRT(X) with X*RSQRT(X).
340  return false;
341  }
342 
343  /// Reciprocal estimate status values used by the functions below.
344  enum ReciprocalEstimate : int {
345  Unspecified = -1,
346  Disabled = 0,
348  };
349 
350  /// Return a ReciprocalEstimate enum value for a square root of the given type
351  /// based on the function's attributes. If the operation is not overridden by
352  /// the function's attributes, "Unspecified" is returned and target defaults
353  /// are expected to be used for instruction selection.
354  int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
355 
356  /// Return a ReciprocalEstimate enum value for a division of the given type
357  /// based on the function's attributes. If the operation is not overridden by
358  /// the function's attributes, "Unspecified" is returned and target defaults
359  /// are expected to be used for instruction selection.
360  int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
361 
362  /// Return the refinement step count for a square root of the given type based
363  /// on the function's attributes. If the operation is not overridden by
364  /// the function's attributes, "Unspecified" is returned and target defaults
365  /// are expected to be used for instruction selection.
366  int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
367 
368  /// Return the refinement step count for a division of the given type based
369  /// on the function's attributes. If the operation is not overridden by
370  /// the function's attributes, "Unspecified" is returned and target defaults
371  /// are expected to be used for instruction selection.
372  int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;
373 
374  /// Returns true if target has indicated at least one type should be bypassed.
375  bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
376 
377  /// Returns map of slow types for division or remainder with corresponding
378  /// fast types
380  return BypassSlowDivWidths;
381  }
382 
383  /// Return true if Flow Control is an expensive operation that should be
384  /// avoided.
385  bool isJumpExpensive() const { return JumpIsExpensive; }
386 
387  /// Return true if selects are only cheaper than branches if the branch is
388  /// unlikely to be predicted right.
390  return PredictableSelectIsExpensive;
391  }
392 
393  /// If a branch or a select condition is skewed in one direction by more than
394  /// this factor, it is very likely to be predicted correctly.
395  virtual BranchProbability getPredictableBranchThreshold() const;
396 
397  /// Return true if the following transform is beneficial:
398  /// fold (conv (load x)) -> (load (conv*)x)
399  /// On architectures that don't natively support some vector loads
400  /// efficiently, casting the load to a smaller vector of larger types and
401  /// loading is more efficient, however, this can be undone by optimizations in
402  /// dag combiner.
403  virtual bool isLoadBitCastBeneficial(EVT LoadVT,
404  EVT BitcastVT) const {
405  // Don't do if we could do an indexed load on the original type, but not on
406  // the new one.
407  if (!LoadVT.isSimple() || !BitcastVT.isSimple())
408  return true;
409 
410  MVT LoadMVT = LoadVT.getSimpleVT();
411 
412  // Don't bother doing this if it's just going to be promoted again later, as
413  // doing so might interfere with other combines.
414  if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
415  getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
416  return false;
417 
418  return true;
419  }
420 
421  /// Return true if the following transform is beneficial:
422  /// (store (y (conv x)), y*)) -> (store x, (x*))
423  virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const {
424  // Default to the same logic as loads.
425  return isLoadBitCastBeneficial(StoreVT, BitcastVT);
426  }
427 
428  /// Return true if it is expected to be cheaper to do a store of a non-zero
429  /// vector constant with the given size and type for the address space than to
430  /// store the individual scalar element constants.
431  virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
432  unsigned NumElem,
433  unsigned AddrSpace) const {
434  return false;
435  }
436 
437  /// Allow store merging after legalization in addition to before legalization.
438  /// This may catch stores that do not exist earlier (eg, stores created from
439  /// intrinsics).
440  virtual bool mergeStoresAfterLegalization() const { return true; }
441 
442  /// Returns if it's reasonable to merge stores to MemVT size.
443  virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
444  const SelectionDAG &DAG) const {
445  return true;
446  }
447 
448  /// Return true if it is cheap to speculate a call to intrinsic cttz.
449  virtual bool isCheapToSpeculateCttz() const {
450  return false;
451  }
452 
453  /// Return true if it is cheap to speculate a call to intrinsic ctlz.
454  virtual bool isCheapToSpeculateCtlz() const {
455  return false;
456  }
457 
458  /// Return true if ctlz instruction is fast.
459  virtual bool isCtlzFast() const {
460  return false;
461  }
462 
463  /// Return true if it is safe to transform an integer-domain bitwise operation
464  /// into the equivalent floating-point operation. This should be set to true
465  /// if the target has IEEE-754-compliant fabs/fneg operations for the input
466  /// type.
467  virtual bool hasBitPreservingFPLogic(EVT VT) const {
468  return false;
469  }
470 
471  /// Return true if it is cheaper to split the store of a merged int val
472  /// from a pair of smaller values into multiple stores.
473  virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {
474  return false;
475  }
476 
477  /// Return if the target supports combining a
478  /// chain like:
479  /// \code
480  /// %andResult = and %val1, #mask
481  /// %icmpResult = icmp %andResult, 0
482  /// \endcode
483  /// into a single machine instruction of a form like:
484  /// \code
485  /// cc = test %register, #mask
486  /// \endcode
487  virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
488  return false;
489  }
490 
491  /// Use bitwise logic to make pairs of compares more efficient. For example:
492  /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
493  /// This should be true when it takes more than one instruction to lower
494  /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on
495  /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
496  virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const {
497  return false;
498  }
499 
500  /// Return the preferred operand type if the target has a quick way to compare
501  /// integer values of the given size. Assume that any legal integer type can
502  /// be compared efficiently. Targets may override this to allow illegal wide
503  /// types to return a vector type if there is support to compare that type.
504  virtual MVT hasFastEqualityCompare(unsigned NumBits) const {
505  MVT VT = MVT::getIntegerVT(NumBits);
506  return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE;
507  }
508 
509  /// Return true if the target should transform:
510  /// (X & Y) == Y ---> (~X & Y) == 0
511  /// (X & Y) != Y ---> (~X & Y) != 0
512  ///
513  /// This may be profitable if the target has a bitwise and-not operation that
514  /// sets comparison flags. A target may want to limit the transformation based
515  /// on the type of Y or if Y is a constant.
516  ///
517  /// Note that the transform will not occur if Y is known to be a power-of-2
518  /// because a mask and compare of a single bit can be handled by inverting the
519  /// predicate, for example:
520  /// (X & 8) == 8 ---> (X & 8) != 0
521  virtual bool hasAndNotCompare(SDValue Y) const {
522  return false;
523  }
524 
525  /// Return true if the target has a bitwise and-not operation:
526  /// X = ~A & B
527  /// This can be used to simplify select or other instructions.
528  virtual bool hasAndNot(SDValue X) const {
529  // If the target has the more complex version of this operation, assume that
530  // it has this operation too.
531  return hasAndNotCompare(X);
532  }
533 
534  /// There are two ways to clear extreme bits (either low or high):
535  /// Mask: x & (-1 << y) (the instcombine canonical form)
536  /// Shifts: x >> y << y
537  /// Return true if the variant with 2 variable shifts is preferred.
538  /// Return false if there is no preference.
540  // By default, let's assume that no one prefers shifts.
541  return false;
542  }
543 
544  /// Return true if it is profitable to fold a pair of shifts into a mask.
545  /// This is usually true on most targets. But some targets, like Thumb1,
546  /// have immediate shift instructions, but no immediate "and" instruction;
547  /// this makes the fold unprofitable.
549  CombineLevel Level) const {
550  return true;
551  }
552 
553  /// Should we tranform the IR-optimal check for whether given truncation
554  /// down into KeptBits would be truncating or not:
555  /// (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits)
556  /// Into it's more traditional form:
557  /// ((%x << C) a>> C) dstcond %x
558  /// Return true if we should transform.
559  /// Return false if there is no preference.
561  unsigned KeptBits) const {
562  // By default, let's assume that no one prefers shifts.
563  return false;
564  }
565 
566  /// Return true if the target wants to use the optimization that
567  /// turns ext(promotableInst1(...(promotableInstN(load)))) into
568  /// promotedInst1(...(promotedInstN(ext(load)))).
569  bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
570 
571  /// Return true if the target can combine store(extractelement VectorTy,
572  /// Idx).
573  /// \p Cost[out] gives the cost of that transformation when this is true.
574  virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
575  unsigned &Cost) const {
576  return false;
577  }
578 
579  /// Return true if inserting a scalar into a variable element of an undef
580  /// vector is more efficiently handled by splatting the scalar instead.
581  virtual bool shouldSplatInsEltVarIndex(EVT) const {
582  return false;
583  }
584 
585  /// Return true if target always beneficiates from combining into FMA for a
586  /// given value type. This must typically return false on targets where FMA
587  /// takes more cycles to execute than FADD.
588  virtual bool enableAggressiveFMAFusion(EVT VT) const {
589  return false;
590  }
591 
592  /// Return the ValueType of the result of SETCC operations.
593  virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
594  EVT VT) const;
595 
596  /// Return the ValueType for comparison libcalls. Comparions libcalls include
597  /// floating point comparion calls, and Ordered/Unordered check calls on
598  /// floating point numbers.
599  virtual
600  MVT::SimpleValueType getCmpLibcallReturnType() const;
601 
602  /// For targets without i1 registers, this gives the nature of the high-bits
603  /// of boolean values held in types wider than i1.
604  ///
605  /// "Boolean values" are special true/false values produced by nodes like
606  /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
607  /// Not to be confused with general values promoted from i1. Some cpus
608  /// distinguish between vectors of boolean and scalars; the isVec parameter
609  /// selects between the two kinds. For example on X86 a scalar boolean should
610  /// be zero extended from i1, while the elements of a vector of booleans
611  /// should be sign extended from i1.
612  ///
613  /// Some cpus also treat floating point types the same way as they treat
614  /// vectors instead of the way they treat scalars.
615  BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
616  if (isVec)
617  return BooleanVectorContents;
618  return isFloat ? BooleanFloatContents : BooleanContents;
619  }
620 
622  return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
623  }
624 
625  /// Return target scheduling preference.
627  return SchedPreferenceInfo;
628  }
629 
630  /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
631  /// for different nodes. This function returns the preference (or none) for
632  /// the given node.
634  return Sched::None;
635  }
636 
637  /// Return the register class that should be used for the specified value
638  /// type.
639  virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
640  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
641  assert(RC && "This value type is not natively supported!");
642  return RC;
643  }
644 
645  /// Return the 'representative' register class for the specified value
646  /// type.
647  ///
648  /// The 'representative' register class is the largest legal super-reg
649  /// register class for the register class of the value type. For example, on
650  /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
651  /// register class is GR64 on x86_64.
652  virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
653  const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
654  return RC;
655  }
656 
657  /// Return the cost of the 'representative' register class for the specified
658  /// value type.
659  virtual uint8_t getRepRegClassCostFor(MVT VT) const {
660  return RepRegClassCostForVT[VT.SimpleTy];
661  }
662 
663  /// Return true if SHIFT instructions should be expanded to SHIFT_PARTS
664  /// instructions, and false if a library call is preferred (e.g for code-size
665  /// reasons).
666  virtual bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const {
667  return true;
668  }
669 
670  /// Return true if the target has native support for the specified value type.
671  /// This means that it has a register that directly holds it without
672  /// promotions or expansions.
673  bool isTypeLegal(EVT VT) const {
674  assert(!VT.isSimple() ||
675  (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
676  return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
677  }
678 
680  /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
681  /// that indicates how instruction selection should deal with the type.
682  LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE];
683 
684  public:
686  std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
687  TypeLegal);
688  }
689 
691  return ValueTypeActions[VT.SimpleTy];
692  }
693 
695  ValueTypeActions[VT.SimpleTy] = Action;
696  }
697  };
698 
700  return ValueTypeActions;
701  }
702 
703  /// Return how we should legalize values of this type, either it is already
704  /// legal (return 'Legal') or we need to promote it to a larger type (return
705  /// 'Promote'), or we need to expand it into multiple registers of smaller
706  /// integer type (return 'Expand'). 'Custom' is not an option.
708  return getTypeConversion(Context, VT).first;
709  }
711  return ValueTypeActions.getTypeAction(VT);
712  }
713 
714  /// For types supported by the target, this is an identity function. For
715  /// types that must be promoted to larger types, this returns the larger type
716  /// to promote to. For integer types that are larger than the largest integer
717  /// register, this contains one step in the expansion to get to the smaller
718  /// register. For illegal floating point types, this returns the integer type
719  /// to transform to.
720  EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
721  return getTypeConversion(Context, VT).second;
722  }
723 
724  /// For types supported by the target, this is an identity function. For
725  /// types that must be expanded (i.e. integer types that are larger than the
726  /// largest integer register or illegal floating point types), this returns
727  /// the largest legal type it will be expanded to.
728  EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
729  assert(!VT.isVector());
730  while (true) {
731  switch (getTypeAction(Context, VT)) {
732  case TypeLegal:
733  return VT;
734  case TypeExpandInteger:
735  VT = getTypeToTransformTo(Context, VT);
736  break;
737  default:
738  llvm_unreachable("Type is not legal nor is it to be expanded!");
739  }
740  }
741  }
742 
743  /// Vector types are broken down into some number of legal first class types.
744  /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
745  /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
746  /// turns into 4 EVT::i32 values with both PPC and X86.
747  ///
748  /// This method returns the number of registers needed, and the VT for each
749  /// register. It also returns the VT and quantity of the intermediate values
750  /// before they are promoted/expanded.
751  unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
752  EVT &IntermediateVT,
753  unsigned &NumIntermediates,
754  MVT &RegisterVT) const;
755 
756  /// Certain targets such as MIPS require that some types such as vectors are
757  /// always broken down into scalars in some contexts. This occurs even if the
758  /// vector type is legal.
760  LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
761  unsigned &NumIntermediates, MVT &RegisterVT) const {
762  return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
763  RegisterVT);
764  }
765 
766  struct IntrinsicInfo {
767  unsigned opc = 0; // target opcode
768  EVT memVT; // memory VT
769 
770  // value representing memory location
772 
773  int offset = 0; // offset off of ptrVal
774  unsigned size = 0; // the size of the memory location
775  // (taken from memVT if zero)
776  unsigned align = 1; // alignment
777 
779  IntrinsicInfo() = default;
780  };
781 
782  /// Given an intrinsic, checks if on the target the intrinsic will need to map
783  /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
784  /// true and store the intrinsic information into the IntrinsicInfo that was
785  /// passed to the function.
786  virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
787  MachineFunction &,
788  unsigned /*Intrinsic*/) const {
789  return false;
790  }
791 
792  /// Returns true if the target can instruction select the specified FP
793  /// immediate natively. If false, the legalizer will materialize the FP
794  /// immediate as a load from a constant pool.
795  virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/,
796  bool ForCodeSize = false) const {
797  return false;
798  }
799 
800  /// Targets can use this to indicate that they only support *some*
801  /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
802  /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
803  /// legal.
804  virtual bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const {
805  return true;
806  }
807 
808  /// Returns true if the operation can trap for the value type.
809  ///
810  /// VT must be a legal type. By default, we optimistically assume most
811  /// operations don't trap except for integer divide and remainder.
812  virtual bool canOpTrap(unsigned Op, EVT VT) const;
813 
814  /// Similar to isShuffleMaskLegal. Targets can use this to indicate if there
815  /// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a
816  /// constant pool entry.
817  virtual bool isVectorClearMaskLegal(ArrayRef<int> /*Mask*/,
818  EVT /*VT*/) const {
819  return false;
820  }
821 
822  /// Return how this operation should be treated: either it is legal, needs to
823  /// be promoted to a larger size, needs to be expanded to some other code
824  /// sequence, or the target has a custom expander for it.
825  LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
826  if (VT.isExtended()) return Expand;
827  // If a target-specific SDNode requires legalization, require the target
828  // to provide custom legalization for it.
829  if (Op >= array_lengthof(OpActions[0])) return Custom;
830  return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
831  }
832 
833  /// Custom method defined by each target to indicate if an operation which
834  /// may require a scale is supported natively by the target.
835  /// If not, the operation is illegal.
836  virtual bool isSupportedFixedPointOperation(unsigned Op, EVT VT,
837  unsigned Scale) const {
838  return false;
839  }
840 
841  /// Some fixed point operations may be natively supported by the target but
842  /// only for specific scales. This method allows for checking
843  /// if the width is supported by the target for a given operation that may
844  /// depend on scale.
846  unsigned Scale) const {
847  auto Action = getOperationAction(Op, VT);
848  if (Action != Legal)
849  return Action;
850 
851  // This operation is supported in this type but may only work on specific
852  // scales.
853  bool Supported;
854  switch (Op) {
855  default:
856  llvm_unreachable("Unexpected fixed point operation.");
857  case ISD::SMULFIX:
858  case ISD::SMULFIXSAT:
859  case ISD::UMULFIX:
860  Supported = isSupportedFixedPointOperation(Op, VT, Scale);
861  break;
862  }
863 
864  return Supported ? Action : Expand;
865  }
866 
868  unsigned EqOpc;
869  switch (Op) {
870  default: llvm_unreachable("Unexpected FP pseudo-opcode");
871  case ISD::STRICT_FADD: EqOpc = ISD::FADD; break;
872  case ISD::STRICT_FSUB: EqOpc = ISD::FSUB; break;
873  case ISD::STRICT_FMUL: EqOpc = ISD::FMUL; break;
874  case ISD::STRICT_FDIV: EqOpc = ISD::FDIV; break;
875  case ISD::STRICT_FREM: EqOpc = ISD::FREM; break;
876  case ISD::STRICT_FSQRT: EqOpc = ISD::FSQRT; break;
877  case ISD::STRICT_FPOW: EqOpc = ISD::FPOW; break;
878  case ISD::STRICT_FPOWI: EqOpc = ISD::FPOWI; break;
879  case ISD::STRICT_FMA: EqOpc = ISD::FMA; break;
880  case ISD::STRICT_FSIN: EqOpc = ISD::FSIN; break;
881  case ISD::STRICT_FCOS: EqOpc = ISD::FCOS; break;
882  case ISD::STRICT_FEXP: EqOpc = ISD::FEXP; break;
883  case ISD::STRICT_FEXP2: EqOpc = ISD::FEXP2; break;
884  case ISD::STRICT_FLOG: EqOpc = ISD::FLOG; break;
885  case ISD::STRICT_FLOG10: EqOpc = ISD::FLOG10; break;
886  case ISD::STRICT_FLOG2: EqOpc = ISD::FLOG2; break;
887  case ISD::STRICT_FRINT: EqOpc = ISD::FRINT; break;
888  case ISD::STRICT_FNEARBYINT: EqOpc = ISD::FNEARBYINT; break;
889  case ISD::STRICT_FMAXNUM: EqOpc = ISD::FMAXNUM; break;
890  case ISD::STRICT_FMINNUM: EqOpc = ISD::FMINNUM; break;
891  case ISD::STRICT_FCEIL: EqOpc = ISD::FCEIL; break;
892  case ISD::STRICT_FFLOOR: EqOpc = ISD::FFLOOR; break;
893  case ISD::STRICT_FROUND: EqOpc = ISD::FROUND; break;
894  case ISD::STRICT_FTRUNC: EqOpc = ISD::FTRUNC; break;
895  case ISD::STRICT_FP_ROUND: EqOpc = ISD::FP_ROUND; break;
896  case ISD::STRICT_FP_EXTEND: EqOpc = ISD::FP_EXTEND; break;
897  }
898 
899  auto Action = getOperationAction(EqOpc, VT);
900 
901  // We don't currently handle Custom or Promote for strict FP pseudo-ops.
902  // For now, we just expand for those cases.
903  if (Action != Legal)
904  Action = Expand;
905 
906  return Action;
907  }
908 
909  /// Return true if the specified operation is legal on this target or can be
910  /// made legal with custom lowering. This is used to help guide high-level
911  /// lowering decisions.
912  bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
913  return (VT == MVT::Other || isTypeLegal(VT)) &&
914  (getOperationAction(Op, VT) == Legal ||
915  getOperationAction(Op, VT) == Custom);
916  }
917 
918  /// Return true if the specified operation is legal on this target or can be
919  /// made legal using promotion. This is used to help guide high-level lowering
920  /// decisions.
921  bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
922  return (VT == MVT::Other || isTypeLegal(VT)) &&
923  (getOperationAction(Op, VT) == Legal ||
924  getOperationAction(Op, VT) == Promote);
925  }
926 
927  /// Return true if the specified operation is legal on this target or can be
928  /// made legal with custom lowering or using promotion. This is used to help
929  /// guide high-level lowering decisions.
930  bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const {
931  return (VT == MVT::Other || isTypeLegal(VT)) &&
932  (getOperationAction(Op, VT) == Legal ||
933  getOperationAction(Op, VT) == Custom ||
934  getOperationAction(Op, VT) == Promote);
935  }
936 
937  /// Return true if the operation uses custom lowering, regardless of whether
938  /// the type is legal or not.
939  bool isOperationCustom(unsigned Op, EVT VT) const {
940  return getOperationAction(Op, VT) == Custom;
941  }
942 
943  /// Return true if lowering to a jump table is allowed.
944  virtual bool areJTsAllowed(const Function *Fn) const {
945  if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
946  return false;
947 
948  return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
949  isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
950  }
951 
952  /// Check whether the range [Low,High] fits in a machine word.
953  bool rangeFitsInWord(const APInt &Low, const APInt &High,
954  const DataLayout &DL) const {
955  // FIXME: Using the pointer type doesn't seem ideal.
956  uint64_t BW = DL.getIndexSizeInBits(0u);
957  uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
958  return Range <= BW;
959  }
960 
961  /// Return true if lowering to a jump table is suitable for a set of case
962  /// clusters which may contain \p NumCases cases, \p Range range of values.
963  /// FIXME: This function check the maximum table size and density, but the
964  /// minimum size is not checked. It would be nice if the minimum size is
965  /// also combined within this function. Currently, the minimum size check is
966  /// performed in findJumpTable() in SelectionDAGBuiler and
967  /// getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
968  virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
969  uint64_t Range) const {
970  const bool OptForSize = SI->getParent()->getParent()->hasOptSize();
971  const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
972  const unsigned MaxJumpTableSize =
973  OptForSize ? UINT_MAX : getMaximumJumpTableSize();
974  // Check whether a range of clusters is dense enough for a jump table.
975  if (Range <= MaxJumpTableSize &&
976  (NumCases * 100 >= Range * MinDensity)) {
977  return true;
978  }
979  return false;
980  }
981 
982  /// Return true if lowering to a bit test is suitable for a set of case
983  /// clusters which contains \p NumDests unique destinations, \p Low and
984  /// \p High as its lowest and highest case values, and expects \p NumCmps
985  /// case value comparisons. Check if the number of destinations, comparison
986  /// metric, and range are all suitable.
987  bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
988  const APInt &Low, const APInt &High,
989  const DataLayout &DL) const {
990  // FIXME: I don't think NumCmps is the correct metric: a single case and a
991  // range of cases both require only one branch to lower. Just looking at the
992  // number of clusters and destinations should be enough to decide whether to
993  // build bit tests.
994 
995  // To lower a range with bit tests, the range must fit the bitwidth of a
996  // machine word.
997  if (!rangeFitsInWord(Low, High, DL))
998  return false;
999 
1000  // Decide whether it's profitable to lower this range with bit tests. Each
1001  // destination requires a bit test and branch, and there is an overall range
1002  // check branch. For a small number of clusters, separate comparisons might
1003  // be cheaper, and for many destinations, splitting the range might be
1004  // better.
1005  return (NumDests == 1 && NumCmps >= 3) || (NumDests == 2 && NumCmps >= 5) ||
1006  (NumDests == 3 && NumCmps >= 6);
1007  }
1008 
1009  /// Return true if the specified operation is illegal on this target or
1010  /// unlikely to be made legal with custom lowering. This is used to help guide
1011  /// high-level lowering decisions.
1012  bool isOperationExpand(unsigned Op, EVT VT) const {
1013  return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
1014  }
1015 
1016  /// Return true if the specified operation is legal on this target.
1017  bool isOperationLegal(unsigned Op, EVT VT) const {
1018  return (VT == MVT::Other || isTypeLegal(VT)) &&
1019  getOperationAction(Op, VT) == Legal;
1020  }
1021 
1022  /// Return how this load with extension should be treated: either it is legal,
1023  /// needs to be promoted to a larger size, needs to be expanded to some other
1024  /// code sequence, or the target has a custom expander for it.
1026  EVT MemVT) const {
1027  if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
1028  unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
1029  unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
1030  assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
1031  MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
1032  unsigned Shift = 4 * ExtType;
1033  return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
1034  }
1035 
1036  /// Return true if the specified load with extension is legal on this target.
1037  bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
1038  return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
1039  }
1040 
1041  /// Return true if the specified load with extension is legal or custom
1042  /// on this target.
1043  bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
1044  return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
1045  getLoadExtAction(ExtType, ValVT, MemVT) == Custom;
1046  }
1047 
1048  /// Return how this store with truncation should be treated: either it is
1049  /// legal, needs to be promoted to a larger size, needs to be expanded to some
1050  /// other code sequence, or the target has a custom expander for it.
1052  if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
1053  unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
1054  unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
1055  assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
1056  "Table isn't big enough!");
1057  return TruncStoreActions[ValI][MemI];
1058  }
1059 
1060  /// Return true if the specified store with truncation is legal on this
1061  /// target.
1062  bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
1063  return isTypeLegal(ValVT) && getTruncStoreAction(ValVT, MemVT) == Legal;
1064  }
1065 
1066  /// Return true if the specified store with truncation has solution on this
1067  /// target.
1068  bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const {
1069  return isTypeLegal(ValVT) &&
1070  (getTruncStoreAction(ValVT, MemVT) == Legal ||
1071  getTruncStoreAction(ValVT, MemVT) == Custom);
1072  }
1073 
1074  /// Return how the indexed load should be treated: either it is legal, needs
1075  /// to be promoted to a larger size, needs to be expanded to some other code
1076  /// sequence, or the target has a custom expander for it.
1078  getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
1079  assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
1080  "Table isn't big enough!");
1081  unsigned Ty = (unsigned)VT.SimpleTy;
1082  return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
1083  }
1084 
1085  /// Return true if the specified indexed load is legal on this target.
1086  bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
1087  return VT.isSimple() &&
1088  (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
1089  getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
1090  }
1091 
1092  /// Return how the indexed store should be treated: either it is legal, needs
1093  /// to be promoted to a larger size, needs to be expanded to some other code
1094  /// sequence, or the target has a custom expander for it.
1096  getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
1097  assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
1098  "Table isn't big enough!");
1099  unsigned Ty = (unsigned)VT.SimpleTy;
1100  return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
1101  }
1102 
1103  /// Return true if the specified indexed load is legal on this target.
1104  bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
1105  return VT.isSimple() &&
1106  (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
1107  getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
1108  }
1109 
1110  /// Return how the condition code should be treated: either it is legal, needs
1111  /// to be expanded to some other code sequence, or the target has a custom
1112  /// expander for it.
1115  assert((unsigned)CC < array_lengthof(CondCodeActions) &&
1116  ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&
1117  "Table isn't big enough!");
1118  // See setCondCodeAction for how this is encoded.
1119  uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1120  uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
1121  LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
1122  assert(Action != Promote && "Can't promote condition code!");
1123  return Action;
1124  }
1125 
1126  /// Return true if the specified condition code is legal on this target.
1127  bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
1128  return getCondCodeAction(CC, VT) == Legal;
1129  }
1130 
1131  /// Return true if the specified condition code is legal or custom on this
1132  /// target.
1134  return getCondCodeAction(CC, VT) == Legal ||
1135  getCondCodeAction(CC, VT) == Custom;
1136  }
1137 
1138  /// If the action for this operation is to promote, this method returns the
1139  /// ValueType to promote to.
1140  MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
1141  assert(getOperationAction(Op, VT) == Promote &&
1142  "This operation isn't promoted!");
1143 
1144  // See if this has an explicit type specified.
1145  std::map<std::pair<unsigned, MVT::SimpleValueType>,
1147  PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
1148  if (PTTI != PromoteToType.end()) return PTTI->second;
1149 
1150  assert((VT.isInteger() || VT.isFloatingPoint()) &&
1151  "Cannot autopromote this type, add it with AddPromotedToType.");
1152 
1153  MVT NVT = VT;
1154  do {
1155  NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
1156  assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
1157  "Didn't find type to promote to!");
1158  } while (!isTypeLegal(NVT) ||
1159  getOperationAction(Op, NVT) == Promote);
1160  return NVT;
1161  }
1162 
1163  /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
1164  /// operations except for the pointer size. If AllowUnknown is true, this
1165  /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
1166  /// otherwise it will assert.
1168  bool AllowUnknown = false) const {
1169  // Lower scalar pointers to native pointer types.
1170  if (auto *PTy = dyn_cast<PointerType>(Ty))
1171  return getPointerTy(DL, PTy->getAddressSpace());
1172 
1173  if (auto *VTy = dyn_cast<VectorType>(Ty)) {
1174  Type *EltTy = VTy->getElementType();
1175  // Lower vectors of pointers to native pointer types.
1176  if (auto *PTy = dyn_cast<PointerType>(EltTy)) {
1177  EVT PointerTy(getPointerTy(DL, PTy->getAddressSpace()));
1178  EltTy = PointerTy.getTypeForEVT(Ty->getContext());
1179  }
1180  return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(EltTy, false),
1181  VTy->getNumElements());
1182  }
1183 
1184  return EVT::getEVT(Ty, AllowUnknown);
1185  }
1186 
1188  bool AllowUnknown = false) const {
1189  // Lower scalar pointers to native pointer types.
1190  if (PointerType *PTy = dyn_cast<PointerType>(Ty))
1191  return getPointerMemTy(DL, PTy->getAddressSpace());
1192  else if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1193  Type *Elm = VTy->getElementType();
1194  if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
1195  EVT PointerTy(getPointerMemTy(DL, PT->getAddressSpace()));
1196  Elm = PointerTy.getTypeForEVT(Ty->getContext());
1197  }
1198  return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
1199  VTy->getNumElements());
1200  }
1201 
1202  return getValueType(DL, Ty, AllowUnknown);
1203  }
1204 
1205 
1206  /// Return the MVT corresponding to this LLVM type. See getValueType.
1208  bool AllowUnknown = false) const {
1209  return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
1210  }
1211 
1212  /// Return the desired alignment for ByVal or InAlloca aggregate function
1213  /// arguments in the caller parameter area. This is the actual alignment, not
1214  /// its logarithm.
1215  virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
1216 
1217  /// Return the type of registers that this ValueType will eventually require.
1219  assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
1220  return RegisterTypeForVT[VT.SimpleTy];
1221  }
1222 
1223  /// Return the type of registers that this ValueType will eventually require.
1224  MVT getRegisterType(LLVMContext &Context, EVT VT) const {
1225  if (VT.isSimple()) {
1226  assert((unsigned)VT.getSimpleVT().SimpleTy <
1227  array_lengthof(RegisterTypeForVT));
1228  return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
1229  }
1230  if (VT.isVector()) {
1231  EVT VT1;
1232  MVT RegisterVT;
1233  unsigned NumIntermediates;
1234  (void)getVectorTypeBreakdown(Context, VT, VT1,
1235  NumIntermediates, RegisterVT);
1236  return RegisterVT;
1237  }
1238  if (VT.isInteger()) {
1239  return getRegisterType(Context, getTypeToTransformTo(Context, VT));
1240  }
1241  llvm_unreachable("Unsupported extended type!");
1242  }
1243 
1244  /// Return the number of registers that this ValueType will eventually
1245  /// require.
1246  ///
1247  /// This is one for any types promoted to live in larger registers, but may be
1248  /// more than one for types (like i64) that are split into pieces. For types
1249  /// like i140, which are first promoted then expanded, it is the number of
1250  /// registers needed to hold all the bits of the original type. For an i140
1251  /// on a 32 bit machine this means 5 registers.
1252  unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
1253  if (VT.isSimple()) {
1254  assert((unsigned)VT.getSimpleVT().SimpleTy <
1255  array_lengthof(NumRegistersForVT));
1256  return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
1257  }
1258  if (VT.isVector()) {
1259  EVT VT1;
1260  MVT VT2;
1261  unsigned NumIntermediates;
1262  return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
1263  }
1264  if (VT.isInteger()) {
1265  unsigned BitWidth = VT.getSizeInBits();
1266  unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
1267  return (BitWidth + RegWidth - 1) / RegWidth;
1268  }
1269  llvm_unreachable("Unsupported extended type!");
1270  }
1271 
1272  /// Certain combinations of ABIs, Targets and features require that types
1273  /// are legal for some operations and not for other operations.
1274  /// For MIPS all vector types must be passed through the integer register set.
1276  CallingConv::ID CC, EVT VT) const {
1277  return getRegisterType(Context, VT);
1278  }
1279 
1280  /// Certain targets require unusual breakdowns of certain types. For MIPS,
1281  /// this occurs when a vector type is used, as vector are passed through the
1282  /// integer register set.
1283  virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
1284  CallingConv::ID CC,
1285  EVT VT) const {
1286  return getNumRegisters(Context, VT);
1287  }
1288 
1289  /// Certain targets have context senstive alignment requirements, where one
1290  /// type has the alignment requirement of another type.
1291  virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy,
1292  DataLayout DL) const {
1293  return DL.getABITypeAlignment(ArgTy);
1294  }
1295 
1296  /// If true, then instruction selection should seek to shrink the FP constant
1297  /// of the specified type to a smaller type in order to save space and / or
1298  /// reduce runtime.
1299  virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
1300 
1301  /// Return true if it is profitable to reduce a load to a smaller type.
1302  /// Example: (i16 (trunc (i32 (load x))) -> i16 load x
1304  EVT NewVT) const {
1305  // By default, assume that it is cheaper to extract a subvector from a wide
1306  // vector load rather than creating multiple narrow vector loads.
1307  if (NewVT.isVector() && !Load->hasOneUse())
1308  return false;
1309 
1310  return true;
1311  }
1312 
1313  /// When splitting a value of the specified type into parts, does the Lo
1314  /// or Hi part come first? This usually follows the endianness, except
1315  /// for ppcf128, where the Hi part always comes first.
1316  bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
1317  return DL.isBigEndian() || VT == MVT::ppcf128;
1318  }
1319 
1320  /// If true, the target has custom DAG combine transformations that it can
1321  /// perform for the specified node.
1323  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1324  return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
1325  }
1326 
1327  unsigned getGatherAllAliasesMaxDepth() const {
1328  return GatherAllAliasesMaxDepth;
1329  }
1330 
1331  /// Returns the size of the platform's va_list object.
1332  virtual unsigned getVaListSizeInBits(const DataLayout &DL) const {
1333  return getPointerTy(DL).getSizeInBits();
1334  }
1335 
1336  /// Get maximum # of store operations permitted for llvm.memset
1337  ///
1338  /// This function returns the maximum number of store operations permitted
1339  /// to replace a call to llvm.memset. The value is set by the target at the
1340  /// performance threshold for such a replacement. If OptSize is true,
1341  /// return the limit for functions that have OptSize attribute.
1342  unsigned getMaxStoresPerMemset(bool OptSize) const {
1343  return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
1344  }
1345 
1346  /// Get maximum # of store operations permitted for llvm.memcpy
1347  ///
1348  /// This function returns the maximum number of store operations permitted
1349  /// to replace a call to llvm.memcpy. The value is set by the target at the
1350  /// performance threshold for such a replacement. If OptSize is true,
1351  /// return the limit for functions that have OptSize attribute.
1352  unsigned getMaxStoresPerMemcpy(bool OptSize) const {
1353  return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
1354  }
1355 
1356  /// \brief Get maximum # of store operations to be glued together
1357  ///
1358  /// This function returns the maximum number of store operations permitted
1359  /// to glue together during lowering of llvm.memcpy. The value is set by
1360  // the target at the performance threshold for such a replacement.
1361  virtual unsigned getMaxGluedStoresPerMemcpy() const {
1362  return MaxGluedStoresPerMemcpy;
1363  }
1364 
1365  /// Get maximum # of load operations permitted for memcmp
1366  ///
1367  /// This function returns the maximum number of load operations permitted
1368  /// to replace a call to memcmp. The value is set by the target at the
1369  /// performance threshold for such a replacement. If OptSize is true,
1370  /// return the limit for functions that have OptSize attribute.
1371  unsigned getMaxExpandSizeMemcmp(bool OptSize) const {
1372  return OptSize ? MaxLoadsPerMemcmpOptSize : MaxLoadsPerMemcmp;
1373  }
1374 
1375  /// For memcmp expansion when the memcmp result is only compared equal or
1376  /// not-equal to 0, allow up to this number of load pairs per block. As an
1377  /// example, this may allow 'memcmp(a, b, 3) == 0' in a single block:
1378  /// a0 = load2bytes &a[0]
1379  /// b0 = load2bytes &b[0]
1380  /// a2 = load1byte &a[2]
1381  /// b2 = load1byte &b[2]
1382  /// r = cmp eq (a0 ^ b0 | a2 ^ b2), 0
1383  virtual unsigned getMemcmpEqZeroLoadsPerBlock() const {
1384  return 1;
1385  }
1386 
1387  /// Get maximum # of store operations permitted for llvm.memmove
1388  ///
1389  /// This function returns the maximum number of store operations permitted
1390  /// to replace a call to llvm.memmove. The value is set by the target at the
1391  /// performance threshold for such a replacement. If OptSize is true,
1392  /// return the limit for functions that have OptSize attribute.
1393  unsigned getMaxStoresPerMemmove(bool OptSize) const {
1394  return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
1395  }
1396 
1397  /// Determine if the target supports unaligned memory accesses.
1398  ///
1399  /// This function returns true if the target allows unaligned memory accesses
1400  /// of the specified type in the given address space. If true, it also returns
1401  /// whether the unaligned memory access is "fast" in the last argument by
1402  /// reference. This is used, for example, in situations where an array
1403  /// copy/move/set is converted to a sequence of store operations. Its use
1404  /// helps to ensure that such replacements don't generate code that causes an
1405  /// alignment error (trap) on the target machine.
1407  unsigned AddrSpace = 0,
1408  unsigned Align = 1,
1409  bool * /*Fast*/ = nullptr) const {
1410  return false;
1411  }
1412 
1413  /// Return true if the target supports a memory access of this type for the
1414  /// given address space and alignment. If the access is allowed, the optional
1415  /// final parameter returns if the access is also fast (as defined by the
1416  /// target).
1417  bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
1418  unsigned AddrSpace = 0, unsigned Alignment = 1,
1419  bool *Fast = nullptr) const;
1420 
1421  /// Returns the target specific optimal type for load and store operations as
1422  /// a result of memset, memcpy, and memmove lowering.
1423  ///
1424  /// If DstAlign is zero that means it's safe to destination alignment can
1425  /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
1426  /// a need to check it against alignment requirement, probably because the
1427  /// source does not need to be loaded. If 'IsMemset' is true, that means it's
1428  /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
1429  /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
1430  /// does not need to be loaded. It returns EVT::Other if the type should be
1431  /// determined using generic target-independent logic.
1432  virtual EVT
1433  getOptimalMemOpType(uint64_t /*Size*/, unsigned /*DstAlign*/,
1434  unsigned /*SrcAlign*/, bool /*IsMemset*/,
1435  bool /*ZeroMemset*/, bool /*MemcpyStrSrc*/,
1436  const AttributeList & /*FuncAttributes*/) const {
1437  return MVT::Other;
1438  }
1439 
1440  /// Returns true if it's safe to use load / store of the specified type to
1441  /// expand memcpy / memset inline.
1442  ///
1443  /// This is mostly true for all types except for some special cases. For
1444  /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
1445  /// fstpl which also does type conversion. Note the specified type doesn't
1446  /// have to be legal as the hook is used before type legalization.
1447  virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
1448 
1449  /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
1450  bool usesUnderscoreSetJmp() const {
1451  return UseUnderscoreSetJmp;
1452  }
1453 
1454  /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
1455  bool usesUnderscoreLongJmp() const {
1456  return UseUnderscoreLongJmp;
1457  }
1458 
1459  /// Return lower limit for number of blocks in a jump table.
1460  virtual unsigned getMinimumJumpTableEntries() const;
1461 
1462  /// Return lower limit of the density in a jump table.
1463  unsigned getMinimumJumpTableDensity(bool OptForSize) const;
1464 
1465  /// Return upper limit for number of entries in a jump table.
1466  /// Zero if no limit.
1467  unsigned getMaximumJumpTableSize() const;
1468 
1469  virtual bool isJumpTableRelative() const {
1470  return TM.isPositionIndependent();
1471  }
1472 
1473  /// If a physical register, this specifies the register that
1474  /// llvm.savestack/llvm.restorestack should save and restore.
1476  return StackPointerRegisterToSaveRestore;
1477  }
1478 
1479  /// If a physical register, this returns the register that receives the
1480  /// exception address on entry to an EH pad.
1481  virtual unsigned
1482  getExceptionPointerRegister(const Constant *PersonalityFn) const {
1483  // 0 is guaranteed to be the NoRegister value on all targets
1484  return 0;
1485  }
1486 
1487  /// If a physical register, this returns the register that receives the
1488  /// exception typeid on entry to a landing pad.
1489  virtual unsigned
1490  getExceptionSelectorRegister(const Constant *PersonalityFn) const {
1491  // 0 is guaranteed to be the NoRegister value on all targets
1492  return 0;
1493  }
1494 
1495  virtual bool needsFixedCatchObjects() const {
1496  report_fatal_error("Funclet EH is not implemented for this target");
1497  }
1498 
1499  /// Returns the target's jmp_buf size in bytes (if never set, the default is
1500  /// 200)
1501  unsigned getJumpBufSize() const {
1502  return JumpBufSize;
1503  }
1504 
1505  /// Returns the target's jmp_buf alignment in bytes (if never set, the default
1506  /// is 0)
1507  unsigned getJumpBufAlignment() const {
1508  return JumpBufAlignment;
1509  }
1510 
1511  /// Return the minimum stack alignment of an argument.
1512  unsigned getMinStackArgumentAlignment() const {
1513  return MinStackArgumentAlignment;
1514  }
1515 
1516  /// Return the minimum function alignment.
1517  unsigned getMinFunctionAlignment() const {
1518  return MinFunctionAlignment;
1519  }
1520 
1521  /// Return the preferred function alignment.
1522  unsigned getPrefFunctionAlignment() const {
1523  return PrefFunctionAlignment;
1524  }
1525 
1526  /// Return the preferred loop alignment.
1527  virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
1528  return PrefLoopAlignment;
1529  }
1530 
1531  /// Should loops be aligned even when the function is marked OptSize (but not
1532  /// MinSize).
1533  virtual bool alignLoopsWithOptSize() const {
1534  return false;
1535  }
1536 
1537  /// If the target has a standard location for the stack protector guard,
1538  /// returns the address of that location. Otherwise, returns nullptr.
1539  /// DEPRECATED: please override useLoadStackGuardNode and customize
1540  /// LOAD_STACK_GUARD, or customize \@llvm.stackguard().
1541  virtual Value *getIRStackGuard(IRBuilder<> &IRB) const;
1542 
1543  /// Inserts necessary declarations for SSP (stack protection) purpose.
1544  /// Should be used only when getIRStackGuard returns nullptr.
1545  virtual void insertSSPDeclarations(Module &M) const;
1546 
1547  /// Return the variable that's previously inserted by insertSSPDeclarations,
1548  /// if any, otherwise return nullptr. Should be used only when
1549  /// getIRStackGuard returns nullptr.
1550  virtual Value *getSDagStackGuard(const Module &M) const;
1551 
1552  /// If this function returns true, stack protection checks should XOR the
1553  /// frame pointer (or whichever pointer is used to address locals) into the
1554  /// stack guard value before checking it. getIRStackGuard must return nullptr
1555  /// if this returns true.
1556  virtual bool useStackGuardXorFP() const { return false; }
1557 
1558  /// If the target has a standard stack protection check function that
1559  /// performs validation and error handling, returns the function. Otherwise,
1560  /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
1561  /// Should be used only when getIRStackGuard returns nullptr.
1562  virtual Function *getSSPStackGuardCheck(const Module &M) const;
1563 
1564 protected:
1565  Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1566  bool UseTLS) const;
1567 
1568 public:
1569  /// Returns the target-specific address of the unsafe stack pointer.
1570  virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;
1571 
1572  /// Returns the name of the symbol used to emit stack probes or the empty
1573  /// string if not applicable.
1575  return "";
1576  }
1577 
1578  /// Returns true if a cast between SrcAS and DestAS is a noop.
1579  virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1580  return false;
1581  }
1582 
1583  /// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
1584  /// are happy to sink it into basic blocks.
1585  virtual bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1586  return isNoopAddrSpaceCast(SrcAS, DestAS);
1587  }
1588 
1589  /// Return true if the pointer arguments to CI should be aligned by aligning
1590  /// the object whose address is being passed. If so then MinSize is set to the
1591  /// minimum size the object must be to be aligned and PrefAlign is set to the
1592  /// preferred alignment.
1593  virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
1594  unsigned & /*PrefAlign*/) const {
1595  return false;
1596  }
1597 
1598  //===--------------------------------------------------------------------===//
1599  /// \name Helpers for TargetTransformInfo implementations
1600  /// @{
1601 
1602  /// Get the ISD node that corresponds to the Instruction class opcode.
1603  int InstructionOpcodeToISD(unsigned Opcode) const;
1604 
1605  /// Estimate the cost of type-legalization and the legalized type.
1606  std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
1607  Type *Ty) const;
1608 
1609  /// @}
1610 
1611  //===--------------------------------------------------------------------===//
1612  /// \name Helpers for atomic expansion.
1613  /// @{
1614 
1615  /// Returns the maximum atomic operation size (in bits) supported by
1616  /// the backend. Atomic operations greater than this size (as well
1617  /// as ones that are not naturally aligned), will be expanded by
1618  /// AtomicExpandPass into an __atomic_* library call.
1620  return MaxAtomicSizeInBitsSupported;
1621  }
1622 
1623  /// Returns the size of the smallest cmpxchg or ll/sc instruction
1624  /// the backend supports. Any smaller operations are widened in
1625  /// AtomicExpandPass.
1626  ///
1627  /// Note that *unlike* operations above the maximum size, atomic ops
1628  /// are still natively supported below the minimum; they just
1629  /// require a more complex expansion.
1630  unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; }
1631 
1632  /// Whether the target supports unaligned atomic operations.
1633  bool supportsUnalignedAtomics() const { return SupportsUnalignedAtomics; }
1634 
1635  /// Whether AtomicExpandPass should automatically insert fences and reduce
1636  /// ordering for this atomic. This should be true for most architectures with
1637  /// weak memory ordering. Defaults to false.
1638  virtual bool shouldInsertFencesForAtomic(const Instruction *I) const {
1639  return false;
1640  }
1641 
1642  /// Perform a load-linked operation on Addr, returning a "Value *" with the
1643  /// corresponding pointee type. This may entail some non-trivial operations to
1644  /// truncate or reconstruct types that will be illegal in the backend. See
1645  /// ARMISelLowering for an example implementation.
1646  virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1647  AtomicOrdering Ord) const {
1648  llvm_unreachable("Load linked unimplemented on this target");
1649  }
1650 
1651  /// Perform a store-conditional operation to Addr. Return the status of the
1652  /// store. This should be 0 if the store succeeded, non-zero otherwise.
1653  virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1654  Value *Addr, AtomicOrdering Ord) const {
1655  llvm_unreachable("Store conditional unimplemented on this target");
1656  }
1657 
1658  /// Perform a masked atomicrmw using a target-specific intrinsic. This
1659  /// represents the core LL/SC loop which will be lowered at a late stage by
1660  /// the backend.
1662  AtomicRMWInst *AI,
1663  Value *AlignedAddr, Value *Incr,
1664  Value *Mask, Value *ShiftAmt,
1665  AtomicOrdering Ord) const {
1666  llvm_unreachable("Masked atomicrmw expansion unimplemented on this target");
1667  }
1668 
1669  /// Perform a masked cmpxchg using a target-specific intrinsic. This
1670  /// represents the core LL/SC loop which will be lowered at a late stage by
1671  /// the backend.
1673  IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
1674  Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
1675  llvm_unreachable("Masked cmpxchg expansion unimplemented on this target");
1676  }
1677 
1678  /// Inserts in the IR a target-specific intrinsic specifying a fence.
1679  /// It is called by AtomicExpandPass before expanding an
1680  /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
1681  /// if shouldInsertFencesForAtomic returns true.
1682  ///
1683  /// Inst is the original atomic instruction, prior to other expansions that
1684  /// may be performed.
1685  ///
1686  /// This function should either return a nullptr, or a pointer to an IR-level
1687  /// Instruction*. Even complex fence sequences can be represented by a
1688  /// single Instruction* through an intrinsic to be lowered later.
1689  /// Backends should override this method to produce target-specific intrinsic
1690  /// for their fences.
1691  /// FIXME: Please note that the default implementation here in terms of
1692  /// IR-level fences exists for historical/compatibility reasons and is
1693  /// *unsound* ! Fences cannot, in general, be used to restore sequential
1694  /// consistency. For example, consider the following example:
1695  /// atomic<int> x = y = 0;
1696  /// int r1, r2, r3, r4;
1697  /// Thread 0:
1698  /// x.store(1);
1699  /// Thread 1:
1700  /// y.store(1);
1701  /// Thread 2:
1702  /// r1 = x.load();
1703  /// r2 = y.load();
1704  /// Thread 3:
1705  /// r3 = y.load();
1706  /// r4 = x.load();
1707  /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1708  /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1709  /// IR-level fences can prevent it.
1710  /// @{
1712  AtomicOrdering Ord) const {
1713  if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
1714  return Builder.CreateFence(Ord);
1715  else
1716  return nullptr;
1717  }
1718 
1720  Instruction *Inst,
1721  AtomicOrdering Ord) const {
1722  if (isAcquireOrStronger(Ord))
1723  return Builder.CreateFence(Ord);
1724  else
1725  return nullptr;
1726  }
1727  /// @}
1728 
1729  // Emits code that executes when the comparison result in the ll/sc
1730  // expansion of a cmpxchg instruction is such that the store-conditional will
1731  // not execute. This makes it possible to balance out the load-linked with
1732  // a dedicated instruction, if desired.
1733  // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
1734  // be unnecessarily held, except if clrex, inserted by this hook, is executed.
1735  virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
1736 
1737  /// Returns true if the given (atomic) store should be expanded by the
1738  /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1740  return false;
1741  }
1742 
1743  /// Returns true if arguments should be sign-extended in lib calls.
1744  virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1745  return IsSigned;
1746  }
1747 
1748  /// Returns how the given (atomic) load should be expanded by the
1749  /// IR-level AtomicExpand pass.
1752  }
1753 
1754  /// Returns how the given atomic cmpxchg should be expanded by the IR-level
1755  /// AtomicExpand pass.
1756  virtual AtomicExpansionKind
1759  }
1760 
1761  /// Returns how the IR-level AtomicExpand pass should expand the given
1762  /// AtomicRMW, if at all. Default is to never expand.
1764  return RMW->isFloatingPointOperation() ?
1765  AtomicExpansionKind::CmpXChg : AtomicExpansionKind::None;
1766  }
1767 
1768  /// On some platforms, an AtomicRMW that never actually modifies the value
1769  /// (such as fetch_add of 0) can be turned into a fence followed by an
1770  /// atomic load. This may sound useless, but it makes it possible for the
1771  /// processor to keep the cacheline shared, dramatically improving
1772  /// performance. And such idempotent RMWs are useful for implementing some
1773  /// kinds of locks, see for example (justification + benchmarks):
1774  /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1775  /// This method tries doing that transformation, returning the atomic load if
1776  /// it succeeds, and nullptr otherwise.
1777  /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1778  /// another round of expansion.
1779  virtual LoadInst *
1781  return nullptr;
1782  }
1783 
1784  /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
1785  /// SIGN_EXTEND, or ANY_EXTEND).
1787  return ISD::ZERO_EXTEND;
1788  }
1789 
1790  /// @}
1791 
1792  /// Returns true if we should normalize
1793  /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1794  /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1795  /// that it saves us from materializing N0 and N1 in an integer register.
1796  /// Targets that are able to perform and/or on flags should return false here.
1798  EVT VT) const {
1799  // If a target has multiple condition registers, then it likely has logical
1800  // operations on those registers.
1801  if (hasMultipleConditionRegisters())
1802  return false;
1803  // Only do the transform if the value won't be split into multiple
1804  // registers.
1805  LegalizeTypeAction Action = getTypeAction(Context, VT);
1806  return Action != TypeExpandInteger && Action != TypeExpandFloat &&
1807  Action != TypeSplitVector;
1808  }
1809 
1810  virtual bool isProfitableToCombineMinNumMaxNum(EVT VT) const { return true; }
1811 
1812  /// Return true if a select of constants (select Cond, C1, C2) should be
1813  /// transformed into simple math ops with the condition value. For example:
1814  /// select Cond, C1, C1-1 --> add (zext Cond), C1-1
1815  virtual bool convertSelectOfConstantsToMath(EVT VT) const {
1816  return false;
1817  }
1818 
1819  /// Return true if it is profitable to transform an integer
1820  /// multiplication-by-constant into simpler operations like shifts and adds.
1821  /// This may be true if the target does not directly support the
1822  /// multiplication operation for the specified type or the sequence of simpler
1823  /// ops is faster than the multiply.
1824  virtual bool decomposeMulByConstant(EVT VT, SDValue C) const {
1825  return false;
1826  }
1827 
1828  /// Return true if it is more correct/profitable to use strict FP_TO_INT
1829  /// conversion operations - canonicalizing the FP source value instead of
1830  /// converting all cases and then selecting based on value.
1831  /// This may be true if the target throws exceptions for out of bounds
1832  /// conversions or has fast FP CMOV.
1833  virtual bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT,
1834  bool IsSigned) const {
1835  return false;
1836  }
1837 
1838  //===--------------------------------------------------------------------===//
1839  // TargetLowering Configuration Methods - These methods should be invoked by
1840  // the derived class constructor to configure this object for the target.
1841  //
1842 protected:
1843  /// Specify how the target extends the result of integer and floating point
1844  /// boolean values from i1 to a wider type. See getBooleanContents.
1846  BooleanContents = Ty;
1847  BooleanFloatContents = Ty;
1848  }
1849 
1850  /// Specify how the target extends the result of integer and floating point
1851  /// boolean values from i1 to a wider type. See getBooleanContents.
1853  BooleanContents = IntTy;
1854  BooleanFloatContents = FloatTy;
1855  }
1856 
1857  /// Specify how the target extends the result of a vector boolean value from a
1858  /// vector of i1 to a wider type. See getBooleanContents.
1860  BooleanVectorContents = Ty;
1861  }
1862 
1863  /// Specify the target scheduling preference.
1865  SchedPreferenceInfo = Pref;
1866  }
1867 
1868  /// Indicate whether this target prefers to use _setjmp to implement
1869  /// llvm.setjmp or the version without _. Defaults to false.
1870  void setUseUnderscoreSetJmp(bool Val) {
1871  UseUnderscoreSetJmp = Val;
1872  }
1873 
1874  /// Indicate whether this target prefers to use _longjmp to implement
1875  /// llvm.longjmp or the version without _. Defaults to false.
1876  void setUseUnderscoreLongJmp(bool Val) {
1877  UseUnderscoreLongJmp = Val;
1878  }
1879 
1880  /// Indicate the minimum number of blocks to generate jump tables.
1881  void setMinimumJumpTableEntries(unsigned Val);
1882 
1883  /// Indicate the maximum number of entries in jump tables.
1884  /// Set to zero to generate unlimited jump tables.
1885  void setMaximumJumpTableSize(unsigned);
1886 
1887  /// If set to a physical register, this specifies the register that
1888  /// llvm.savestack/llvm.restorestack should save and restore.
1890  StackPointerRegisterToSaveRestore = R;
1891  }
1892 
1893  /// Tells the code generator that the target has multiple (allocatable)
1894  /// condition registers that can be used to store the results of comparisons
1895  /// for use by selects and conditional branches. With multiple condition
1896  /// registers, the code generator will not aggressively sink comparisons into
1897  /// the blocks of their users.
1898  void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1899  HasMultipleConditionRegisters = hasManyRegs;
1900  }
1901 
1902  /// Tells the code generator that the target has BitExtract instructions.
1903  /// The code generator will aggressively sink "shift"s into the blocks of
1904  /// their users if the users will generate "and" instructions which can be
1905  /// combined with "shift" to BitExtract instructions.
1906  void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1907  HasExtractBitsInsn = hasExtractInsn;
1908  }
1909 
1910  /// Tells the code generator not to expand logic operations on comparison
1911  /// predicates into separate sequences that increase the amount of flow
1912  /// control.
1913  void setJumpIsExpensive(bool isExpensive = true);
1914 
1915  /// Tells the code generator which bitwidths to bypass.
1916  void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1917  BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1918  }
1919 
1920  /// Add the specified register class as an available regclass for the
1921  /// specified value type. This indicates the selector can handle values of
1922  /// that class natively.
1924  assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1925  RegClassForVT[VT.SimpleTy] = RC;
1926  }
1927 
1928  /// Return the largest legal super-reg register class of the register class
1929  /// for the specified type and its associated "cost".
1930  virtual std::pair<const TargetRegisterClass *, uint8_t>
1931  findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1932 
1933  /// Once all of the register classes are added, this allows us to compute
1934  /// derived properties we expose.
1935  void computeRegisterProperties(const TargetRegisterInfo *TRI);
1936 
1937  /// Indicate that the specified operation does not work with the specified
1938  /// type and indicate what to do about it. Note that VT may refer to either
1939  /// the type of a result or that of an operand of Op.
1940  void setOperationAction(unsigned Op, MVT VT,
1941  LegalizeAction Action) {
1942  assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1943  OpActions[(unsigned)VT.SimpleTy][Op] = Action;
1944  }
1945 
1946  /// Indicate that the specified load with extension does not work with the
1947  /// specified type and indicate what to do about it.
1948  void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1949  LegalizeAction Action) {
1950  assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1951  MemVT.isValid() && "Table isn't big enough!");
1952  assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1953  unsigned Shift = 4 * ExtType;
1954  LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
1955  LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
1956  }
1957 
1958  /// Indicate that the specified truncating store does not work with the
1959  /// specified type and indicate what to do about it.
1960  void setTruncStoreAction(MVT ValVT, MVT MemVT,
1961  LegalizeAction Action) {
1962  assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1963  TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action;
1964  }
1965 
1966  /// Indicate that the specified indexed load does or does not work with the
1967  /// specified type and indicate what to do abort it.
1968  ///
1969  /// NOTE: All indexed mode loads are initialized to Expand in
1970  /// TargetLowering.cpp
1971  void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1972  LegalizeAction Action) {
1973  assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1974  (unsigned)Action < 0xf && "Table isn't big enough!");
1975  // Load action are kept in the upper half.
1976  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1977  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1978  }
1979 
1980  /// Indicate that the specified indexed store does or does not work with the
1981  /// specified type and indicate what to do about it.
1982  ///
1983  /// NOTE: All indexed mode stores are initialized to Expand in
1984  /// TargetLowering.cpp
1985  void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1986  LegalizeAction Action) {
1987  assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1988  (unsigned)Action < 0xf && "Table isn't big enough!");
1989  // Store action are kept in the lower half.
1990  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1991  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1992  }
1993 
1994  /// Indicate that the specified condition code is or isn't supported on the
1995  /// target and indicate what to do about it.
1997  LegalizeAction Action) {
1998  assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1999  "Table isn't big enough!");
2000  assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
2001  /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
2002  /// value and the upper 29 bits index into the second dimension of the array
2003  /// to select what 32-bit value to use.
2004  uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
2005  CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
2006  CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
2007  }
2008 
2009  /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
2010  /// to trying a larger integer/fp until it can find one that works. If that
2011  /// default is insufficient, this method can be used by the target to override
2012  /// the default.
2013  void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
2014  PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
2015  }
2016 
2017  /// Convenience method to set an operation to Promote and specify the type
2018  /// in a single call.
2019  void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
2020  setOperationAction(Opc, OrigVT, Promote);
2021  AddPromotedToType(Opc, OrigVT, DestVT);
2022  }
2023 
2024  /// Targets should invoke this method for each target independent node that
2025  /// they want to provide a custom DAG combiner for by implementing the
2026  /// PerformDAGCombine virtual method.
2028  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
2029  TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
2030  }
2031 
2032  /// Set the target's required jmp_buf buffer size (in bytes); default is 200
2033  void setJumpBufSize(unsigned Size) {
2034  JumpBufSize = Size;
2035  }
2036 
2037  /// Set the target's required jmp_buf buffer alignment (in bytes); default is
2038  /// 0
2039  void setJumpBufAlignment(unsigned Align) {
2040  JumpBufAlignment = Align;
2041  }
2042 
2043  /// Set the target's minimum function alignment (in log2(bytes))
2045  MinFunctionAlignment = Align;
2046  }
2047 
2048  /// Set the target's preferred function alignment. This should be set if
2049  /// there is a performance benefit to higher-than-minimum alignment (in
2050  /// log2(bytes))
2052  PrefFunctionAlignment = Align;
2053  }
2054 
2055  /// Set the target's preferred loop alignment. Default alignment is zero, it
2056  /// means the target does not care about loop alignment. The alignment is
2057  /// specified in log2(bytes). The target may also override
2058  /// getPrefLoopAlignment to provide per-loop values.
2059  void setPrefLoopAlignment(unsigned Align) {
2060  PrefLoopAlignment = Align;
2061  }
2062 
2063  /// Set the minimum stack alignment of an argument (in log2(bytes)).
2065  MinStackArgumentAlignment = Align;
2066  }
2067 
2068  /// Set the maximum atomic operation size supported by the
2069  /// backend. Atomic operations greater than this size (as well as
2070  /// ones that are not naturally aligned), will be expanded by
2071  /// AtomicExpandPass into an __atomic_* library call.
2072  void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
2073  MaxAtomicSizeInBitsSupported = SizeInBits;
2074  }
2075 
2076  /// Sets the minimum cmpxchg or ll/sc size supported by the backend.
2077  void setMinCmpXchgSizeInBits(unsigned SizeInBits) {
2078  MinCmpXchgSizeInBits = SizeInBits;
2079  }
2080 
2081  /// Sets whether unaligned atomic operations are supported.
2082  void setSupportsUnalignedAtomics(bool UnalignedSupported) {
2083  SupportsUnalignedAtomics = UnalignedSupported;
2084  }
2085 
2086 public:
2087  //===--------------------------------------------------------------------===//
2088  // Addressing mode description hooks (used by LSR etc).
2089  //
2090 
2091  /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
2092  /// instructions reading the address. This allows as much computation as
2093  /// possible to be done in the address mode for that operand. This hook lets
2094  /// targets also pass back when this should be done on intrinsics which
2095  /// load/store.
2096  virtual bool getAddrModeArguments(IntrinsicInst * /*I*/,
2097  SmallVectorImpl<Value*> &/*Ops*/,
2098  Type *&/*AccessTy*/) const {
2099  return false;
2100  }
2101 
2102  /// This represents an addressing mode of:
2103  /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
2104  /// If BaseGV is null, there is no BaseGV.
2105  /// If BaseOffs is zero, there is no base offset.
2106  /// If HasBaseReg is false, there is no base register.
2107  /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
2108  /// no scale.
2109  struct AddrMode {
2110  GlobalValue *BaseGV = nullptr;
2111  int64_t BaseOffs = 0;
2112  bool HasBaseReg = false;
2113  int64_t Scale = 0;
2114  AddrMode() = default;
2115  };
2116 
2117  /// Return true if the addressing mode represented by AM is legal for this
2118  /// target, for a load/store of the specified type.
2119  ///
2120  /// The type may be VoidTy, in which case only return true if the addressing
2121  /// mode is legal for a load/store of any legal type. TODO: Handle
2122  /// pre/postinc as well.
2123  ///
2124  /// If the address space cannot be determined, it will be -1.
2125  ///
2126  /// TODO: Remove default argument
2127  virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
2128  Type *Ty, unsigned AddrSpace,
2129  Instruction *I = nullptr) const;
2130 
2131  /// Return the cost of the scaling factor used in the addressing mode
2132  /// represented by AM for this target, for a load/store of the specified type.
2133  ///
2134  /// If the AM is supported, the return value must be >= 0.
2135  /// If the AM is not supported, it returns a negative value.
2136  /// TODO: Handle pre/postinc as well.
2137  /// TODO: Remove default argument
2138  virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
2139  Type *Ty, unsigned AS = 0) const {
2140  // Default: assume that any scaling factor used in a legal AM is free.
2141  if (isLegalAddressingMode(DL, AM, Ty, AS))
2142  return 0;
2143  return -1;
2144  }
2145 
2146  /// Return true if the specified immediate is legal icmp immediate, that is
2147  /// the target has icmp instructions which can compare a register against the
2148  /// immediate without having to materialize the immediate into a register.
2149  virtual bool isLegalICmpImmediate(int64_t) const {
2150  return true;
2151  }
2152 
2153  /// Return true if the specified immediate is legal add immediate, that is the
2154  /// target has add instructions which can add a register with the immediate
2155  /// without having to materialize the immediate into a register.
2156  virtual bool isLegalAddImmediate(int64_t) const {
2157  return true;
2158  }
2159 
2160  /// Return true if the specified immediate is legal for the value input of a
2161  /// store instruction.
2162  virtual bool isLegalStoreImmediate(int64_t Value) const {
2163  // Default implementation assumes that at least 0 works since it is likely
2164  // that a zero register exists or a zero immediate is allowed.
2165  return Value == 0;
2166  }
2167 
2168  /// Return true if it's significantly cheaper to shift a vector by a uniform
2169  /// scalar than by an amount which will vary across each lane. On x86, for
2170  /// example, there is a "psllw" instruction for the former case, but no simple
2171  /// instruction for a general "a << b" operation on vectors.
2172  virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
2173  return false;
2174  }
2175 
2176  /// Return true if the node is a math/logic binary operator.
2177  virtual bool isBinOp(unsigned Opcode) const {
2178  switch (Opcode) {
2179  case ISD::ADD:
2180  case ISD::SUB:
2181  case ISD::MUL:
2182  case ISD::AND:
2183  case ISD::OR:
2184  case ISD::XOR:
2185  case ISD::SHL:
2186  case ISD::SRL:
2187  case ISD::SRA:
2188  case ISD::SDIV:
2189  case ISD::UDIV:
2190  case ISD::SREM:
2191  case ISD::UREM:
2192  case ISD::FADD:
2193  case ISD::FSUB:
2194  case ISD::FMUL:
2195  case ISD::FDIV:
2196  case ISD::FREM:
2197  case ISD::FMINNUM:
2198  case ISD::FMAXNUM:
2199  case ISD::FMINNUM_IEEE:
2200  case ISD::FMAXNUM_IEEE:
2201  case ISD::FMAXIMUM:
2202  case ISD::FMINIMUM:
2203  return true;
2204  default:
2205  return false;
2206  }
2207  }
2208 
2209  /// Returns true if the opcode is a commutative binary operation.
2210  virtual bool isCommutativeBinOp(unsigned Opcode) const {
2211  // FIXME: This should get its info from the td file.
2212  switch (Opcode) {
2213  case ISD::ADD:
2214  case ISD::SMIN:
2215  case ISD::SMAX:
2216  case ISD::UMIN:
2217  case ISD::UMAX:
2218  case ISD::MUL:
2219  case ISD::MULHU:
2220  case ISD::MULHS:
2221  case ISD::SMUL_LOHI:
2222  case ISD::UMUL_LOHI:
2223  case ISD::FADD:
2224  case ISD::FMUL:
2225  case ISD::AND:
2226  case ISD::OR:
2227  case ISD::XOR:
2228  case ISD::SADDO:
2229  case ISD::UADDO:
2230  case ISD::ADDC:
2231  case ISD::ADDE:
2232  case ISD::SADDSAT:
2233  case ISD::UADDSAT:
2234  case ISD::FMINNUM:
2235  case ISD::FMAXNUM:
2236  case ISD::FMINIMUM:
2237  case ISD::FMAXIMUM:
2238  return true;
2239  default: return false;
2240  }
2241  }
2242 
2243  /// Return true if it's free to truncate a value of type FromTy to type
2244  /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
2245  /// by referencing its sub-register AX.
2246  /// Targets must return false when FromTy <= ToTy.
2247  virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
2248  return false;
2249  }
2250 
2251  /// Return true if a truncation from FromTy to ToTy is permitted when deciding
2252  /// whether a call is in tail position. Typically this means that both results
2253  /// would be assigned to the same register or stack slot, but it could mean
2254  /// the target performs adequate checks of its own before proceeding with the
2255  /// tail call. Targets must return false when FromTy <= ToTy.
2256  virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
2257  return false;
2258  }
2259 
2260  virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
2261  return false;
2262  }
2263 
2264  virtual bool isProfitableToHoist(Instruction *I) const { return true; }
2265 
2266  /// Return true if the extension represented by \p I is free.
2267  /// Unlikely the is[Z|FP]ExtFree family which is based on types,
2268  /// this method can use the context provided by \p I to decide
2269  /// whether or not \p I is free.
2270  /// This method extends the behavior of the is[Z|FP]ExtFree family.
2271  /// In other words, if is[Z|FP]Free returns true, then this method
2272  /// returns true as well. The converse is not true.
2273  /// The target can perform the adequate checks by overriding isExtFreeImpl.
2274  /// \pre \p I must be a sign, zero, or fp extension.
2275  bool isExtFree(const Instruction *I) const {
2276  switch (I->getOpcode()) {
2277  case Instruction::FPExt:
2278  if (isFPExtFree(EVT::getEVT(I->getType()),
2279  EVT::getEVT(I->getOperand(0)->getType())))
2280  return true;
2281  break;
2282  case Instruction::ZExt:
2283  if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
2284  return true;
2285  break;
2286  case Instruction::SExt:
2287  break;
2288  default:
2289  llvm_unreachable("Instruction is not an extension");
2290  }
2291  return isExtFreeImpl(I);
2292  }
2293 
2294  /// Return true if \p Load and \p Ext can form an ExtLoad.
2295  /// For example, in AArch64
2296  /// %L = load i8, i8* %ptr
2297  /// %E = zext i8 %L to i32
2298  /// can be lowered into one load instruction
2299  /// ldrb w0, [x0]
2300  bool isExtLoad(const LoadInst *Load, const Instruction *Ext,
2301  const DataLayout &DL) const {
2302  EVT VT = getValueType(DL, Ext->getType());
2303  EVT LoadVT = getValueType(DL, Load->getType());
2304 
2305  // If the load has other users and the truncate is not free, the ext
2306  // probably isn't free.
2307  if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) &&
2308  !isTruncateFree(Ext->getType(), Load->getType()))
2309  return false;
2310 
2311  // Check whether the target supports casts folded into loads.
2312  unsigned LType;
2313  if (isa<ZExtInst>(Ext))
2314  LType = ISD::ZEXTLOAD;
2315  else {
2316  assert(isa<SExtInst>(Ext) && "Unexpected ext type!");
2317  LType = ISD::SEXTLOAD;
2318  }
2319 
2320  return isLoadExtLegal(LType, VT, LoadVT);
2321  }
2322 
2323  /// Return true if any actual instruction that defines a value of type FromTy
2324  /// implicitly zero-extends the value to ToTy in the result register.
2325  ///
2326  /// The function should return true when it is likely that the truncate can
2327  /// be freely folded with an instruction defining a value of FromTy. If
2328  /// the defining instruction is unknown (because you're looking at a
2329  /// function argument, PHI, etc.) then the target may require an
2330  /// explicit truncate, which is not necessarily free, but this function
2331  /// does not deal with those cases.
2332  /// Targets must return false when FromTy >= ToTy.
2333  virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
2334  return false;
2335  }
2336 
2337  virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
2338  return false;
2339  }
2340 
2341  /// Return true if sign-extension from FromTy to ToTy is cheaper than
2342  /// zero-extension.
2343  virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const {
2344  return false;
2345  }
2346 
2347  /// Return true if sinking I's operands to the same basic block as I is
2348  /// profitable, e.g. because the operands can be folded into a target
2349  /// instruction during instruction selection. After calling the function
2350  /// \p Ops contains the Uses to sink ordered by dominance (dominating users
2351  /// come first).
2353  SmallVectorImpl<Use *> &Ops) const {
2354  return false;
2355  }
2356 
2357  /// Return true if the target supplies and combines to a paired load
2358  /// two loaded values of type LoadedType next to each other in memory.
2359  /// RequiredAlignment gives the minimal alignment constraints that must be met
2360  /// to be able to select this paired load.
2361  ///
2362  /// This information is *not* used to generate actual paired loads, but it is
2363  /// used to generate a sequence of loads that is easier to combine into a
2364  /// paired load.
2365  /// For instance, something like this:
2366  /// a = load i64* addr
2367  /// b = trunc i64 a to i32
2368  /// c = lshr i64 a, 32
2369  /// d = trunc i64 c to i32
2370  /// will be optimized into:
2371  /// b = load i32* addr1
2372  /// d = load i32* addr2
2373  /// Where addr1 = addr2 +/- sizeof(i32).
2374  ///
2375  /// In other words, unless the target performs a post-isel load combining,
2376  /// this information should not be provided because it will generate more
2377  /// loads.
2378  virtual bool hasPairedLoad(EVT /*LoadedType*/,
2379  unsigned & /*RequiredAlignment*/) const {
2380  return false;
2381  }
2382 
2383  /// Return true if the target has a vector blend instruction.
2384  virtual bool hasVectorBlend() const { return false; }
2385 
2386  /// Get the maximum supported factor for interleaved memory accesses.
2387  /// Default to be the minimum interleave factor: 2.
2388  virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
2389 
2390  /// Lower an interleaved load to target specific intrinsics. Return
2391  /// true on success.
2392  ///
2393  /// \p LI is the vector load instruction.
2394  /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
2395  /// \p Indices is the corresponding indices for each shufflevector.
2396  /// \p Factor is the interleave factor.
2397  virtual bool lowerInterleavedLoad(LoadInst *LI,
2399  ArrayRef<unsigned> Indices,
2400  unsigned Factor) const {
2401  return false;
2402  }
2403 
2404  /// Lower an interleaved store to target specific intrinsics. Return
2405  /// true on success.
2406  ///
2407  /// \p SI is the vector store instruction.
2408  /// \p SVI is the shufflevector to RE-interleave the stored vector.
2409  /// \p Factor is the interleave factor.
2411  unsigned Factor) const {
2412  return false;
2413  }
2414 
2415  /// Return true if zero-extending the specific node Val to type VT2 is free
2416  /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
2417  /// because it's folded such as X86 zero-extending loads).
2418  virtual bool isZExtFree(SDValue Val, EVT VT2) const {
2419  return isZExtFree(Val.getValueType(), VT2);
2420  }
2421 
2422  /// Return true if an fpext operation is free (for instance, because
2423  /// single-precision floating-point numbers are implicitly extended to
2424  /// double-precision).
2425  virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const {
2426  assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&
2427  "invalid fpext types");
2428  return false;
2429  }
2430 
2431  /// Return true if an fpext operation input to an \p Opcode operation is free
2432  /// (for instance, because half-precision floating-point numbers are
2433  /// implicitly extended to float-precision) for an FMA instruction.
2434  virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const {
2435  assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
2436  "invalid fpext types");
2437  return isFPExtFree(DestVT, SrcVT);
2438  }
2439 
2440  /// Return true if folding a vector load into ExtVal (a sign, zero, or any
2441  /// extend node) is profitable.
2442  virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
2443 
2444  /// Return true if an fneg operation is free to the point where it is never
2445  /// worthwhile to replace it with a bitwise operation.
2446  virtual bool isFNegFree(EVT VT) const {
2447  assert(VT.isFloatingPoint());
2448  return false;
2449  }
2450 
2451  /// Return true if an fabs operation is free to the point where it is never
2452  /// worthwhile to replace it with a bitwise operation.
2453  virtual bool isFAbsFree(EVT VT) const {
2454  assert(VT.isFloatingPoint());
2455  return false;
2456  }
2457 
2458  /// Return true if an FMA operation is faster than a pair of fmul and fadd
2459  /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
2460  /// returns true, otherwise fmuladd is expanded to fmul + fadd.
2461  ///
2462  /// NOTE: This may be called before legalization on types for which FMAs are
2463  /// not legal, but should return true if those types will eventually legalize
2464  /// to types that support FMAs. After legalization, it will only be called on
2465  /// types that support FMAs (via Legal or Custom actions)
2466  virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
2467  return false;
2468  }
2469 
2470  /// Return true if it's profitable to narrow operations of type VT1 to
2471  /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
2472  /// i32 to i16.
2473  virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
2474  return false;
2475  }
2476 
2477  /// Return true if it is beneficial to convert a load of a constant to
2478  /// just the constant itself.
2479  /// On some targets it might be more efficient to use a combination of
2480  /// arithmetic instructions to materialize the constant instead of loading it
2481  /// from a constant pool.
2482  virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
2483  Type *Ty) const {
2484  return false;
2485  }
2486 
2487  /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
2488  /// from this source type with this index. This is needed because
2489  /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
2490  /// the first element, and only the target knows which lowering is cheap.
2491  virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
2492  unsigned Index) const {
2493  return false;
2494  }
2495 
2496  /// Try to convert an extract element of a vector binary operation into an
2497  /// extract element followed by a scalar operation.
2498  virtual bool shouldScalarizeBinop(SDValue VecOp) const {
2499  return false;
2500  }
2501 
2502  /// Return true if extraction of a scalar element from the given vector type
2503  /// at the given index is cheap. For example, if scalar operations occur on
2504  /// the same register file as vector operations, then an extract element may
2505  /// be a sub-register rename rather than an actual instruction.
2506  virtual bool isExtractVecEltCheap(EVT VT, unsigned Index) const {
2507  return false;
2508  }
2509 
2510  /// Try to convert math with an overflow comparison into the corresponding DAG
2511  /// node operation. Targets may want to override this independently of whether
2512  /// the operation is legal/custom for the given type because it may obscure
2513  /// matching of other patterns.
2514  virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT) const {
2515  // TODO: The default logic is inherited from code in CodeGenPrepare.
2516  // The opcode should not make a difference by default?
2517  if (Opcode != ISD::UADDO)
2518  return false;
2519 
2520  // Allow the transform as long as we have an integer type that is not
2521  // obviously illegal and unsupported.
2522  if (VT.isVector())
2523  return false;
2524  return VT.isSimple() || !isOperationExpand(Opcode, VT);
2525  }
2526 
2527  // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
2528  // even if the vector itself has multiple uses.
2529  virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
2530  return false;
2531  }
2532 
2533  // Return true if CodeGenPrepare should consider splitting large offset of a
2534  // GEP to make the GEP fit into the addressing mode and can be sunk into the
2535  // same blocks of its users.
2536  virtual bool shouldConsiderGEPOffsetSplit() const { return false; }
2537 
2538  //===--------------------------------------------------------------------===//
2539  // Runtime Library hooks
2540  //
2541 
2542  /// Rename the default libcall routine name for the specified libcall.
2543  void setLibcallName(RTLIB::Libcall Call, const char *Name) {
2544  LibcallRoutineNames[Call] = Name;
2545  }
2546 
2547  /// Get the libcall routine name for the specified libcall.
2548  const char *getLibcallName(RTLIB::Libcall Call) const {
2549  return LibcallRoutineNames[Call];
2550  }
2551 
2552  /// Override the default CondCode to be used to test the result of the
2553  /// comparison libcall against zero.
2555  CmpLibcallCCs[Call] = CC;
2556  }
2557 
2558  /// Get the CondCode that's to be used to test the result of the comparison
2559  /// libcall against zero.
2561  return CmpLibcallCCs[Call];
2562  }
2563 
2564  /// Set the CallingConv that should be used for the specified libcall.
2566  LibcallCallingConvs[Call] = CC;
2567  }
2568 
2569  /// Get the CallingConv that should be used for the specified libcall.
2571  return LibcallCallingConvs[Call];
2572  }
2573 
2574  /// Execute target specific actions to finalize target lowering.
2575  /// This is used to set extra flags in MachineFrameInformation and freezing
2576  /// the set of reserved registers.
2577  /// The default implementation just freezes the set of reserved registers.
2578  virtual void finalizeLowering(MachineFunction &MF) const;
2579 
2580 private:
2581  const TargetMachine &TM;
2582 
2583  /// Tells the code generator that the target has multiple (allocatable)
2584  /// condition registers that can be used to store the results of comparisons
2585  /// for use by selects and conditional branches. With multiple condition
2586  /// registers, the code generator will not aggressively sink comparisons into
2587  /// the blocks of their users.
2588  bool HasMultipleConditionRegisters;
2589 
2590  /// Tells the code generator that the target has BitExtract instructions.
2591  /// The code generator will aggressively sink "shift"s into the blocks of
2592  /// their users if the users will generate "and" instructions which can be
2593  /// combined with "shift" to BitExtract instructions.
2594  bool HasExtractBitsInsn;
2595 
2596  /// Tells the code generator to bypass slow divide or remainder
2597  /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
2598  /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
2599  /// div/rem when the operands are positive and less than 256.
2600  DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
2601 
2602  /// Tells the code generator that it shouldn't generate extra flow control
2603  /// instructions and should attempt to combine flow control instructions via
2604  /// predication.
2605  bool JumpIsExpensive;
2606 
2607  /// This target prefers to use _setjmp to implement llvm.setjmp.
2608  ///
2609  /// Defaults to false.
2610  bool UseUnderscoreSetJmp;
2611 
2612  /// This target prefers to use _longjmp to implement llvm.longjmp.
2613  ///
2614  /// Defaults to false.
2615  bool UseUnderscoreLongJmp;
2616 
2617  /// Information about the contents of the high-bits in boolean values held in
2618  /// a type wider than i1. See getBooleanContents.
2619  BooleanContent BooleanContents;
2620 
2621  /// Information about the contents of the high-bits in boolean values held in
2622  /// a type wider than i1. See getBooleanContents.
2623  BooleanContent BooleanFloatContents;
2624 
2625  /// Information about the contents of the high-bits in boolean vector values
2626  /// when the element type is wider than i1. See getBooleanContents.
2627  BooleanContent BooleanVectorContents;
2628 
2629  /// The target scheduling preference: shortest possible total cycles or lowest
2630  /// register usage.
2631  Sched::Preference SchedPreferenceInfo;
2632 
2633  /// The size, in bytes, of the target's jmp_buf buffers
2634  unsigned JumpBufSize;
2635 
2636  /// The alignment, in bytes, of the target's jmp_buf buffers
2637  unsigned JumpBufAlignment;
2638 
2639  /// The minimum alignment that any argument on the stack needs to have.
2640  unsigned MinStackArgumentAlignment;
2641 
2642  /// The minimum function alignment (used when optimizing for size, and to
2643  /// prevent explicitly provided alignment from leading to incorrect code).
2644  unsigned MinFunctionAlignment;
2645 
2646  /// The preferred function alignment (used when alignment unspecified and
2647  /// optimizing for speed).
2648  unsigned PrefFunctionAlignment;
2649 
2650  /// The preferred loop alignment.
2651  unsigned PrefLoopAlignment;
2652 
2653  /// Size in bits of the maximum atomics size the backend supports.
2654  /// Accesses larger than this will be expanded by AtomicExpandPass.
2655  unsigned MaxAtomicSizeInBitsSupported;
2656 
2657  /// Size in bits of the minimum cmpxchg or ll/sc operation the
2658  /// backend supports.
2659  unsigned MinCmpXchgSizeInBits;
2660 
2661  /// This indicates if the target supports unaligned atomic operations.
2662  bool SupportsUnalignedAtomics;
2663 
2664  /// If set to a physical register, this specifies the register that
2665  /// llvm.savestack/llvm.restorestack should save and restore.
2666  unsigned StackPointerRegisterToSaveRestore;
2667 
2668  /// This indicates the default register class to use for each ValueType the
2669  /// target supports natively.
2670  const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
2671  unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
2672  MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
2673 
2674  /// This indicates the "representative" register class to use for each
2675  /// ValueType the target supports natively. This information is used by the
2676  /// scheduler to track register pressure. By default, the representative
2677  /// register class is the largest legal super-reg register class of the
2678  /// register class of the specified type. e.g. On x86, i8, i16, and i32's
2679  /// representative class would be GR32.
2680  const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
2681 
2682  /// This indicates the "cost" of the "representative" register class for each
2683  /// ValueType. The cost is used by the scheduler to approximate register
2684  /// pressure.
2685  uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
2686 
2687  /// For any value types we are promoting or expanding, this contains the value
2688  /// type that we are changing to. For Expanded types, this contains one step
2689  /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
2690  /// (e.g. i64 -> i16). For types natively supported by the system, this holds
2691  /// the same type (e.g. i32 -> i32).
2692  MVT TransformToType[MVT::LAST_VALUETYPE];
2693 
2694  /// For each operation and each value type, keep a LegalizeAction that
2695  /// indicates how instruction selection should deal with the operation. Most
2696  /// operations are Legal (aka, supported natively by the target), but
2697  /// operations that are not should be described. Note that operations on
2698  /// non-legal value types are not described here.
2700 
2701  /// For each load extension type and each value type, keep a LegalizeAction
2702  /// that indicates how instruction selection should deal with a load of a
2703  /// specific value type and extension type. Uses 4-bits to store the action
2704  /// for each of the 4 load ext types.
2705  uint16_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2706 
2707  /// For each value type pair keep a LegalizeAction that indicates whether a
2708  /// truncating store of a specific value type and truncating type is legal.
2710 
2711  /// For each indexed mode and each value type, keep a pair of LegalizeAction
2712  /// that indicates how instruction selection should deal with the load /
2713  /// store.
2714  ///
2715  /// The first dimension is the value_type for the reference. The second
2716  /// dimension represents the various modes for load store.
2717  uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
2718 
2719  /// For each condition code (ISD::CondCode) keep a LegalizeAction that
2720  /// indicates how instruction selection should deal with the condition code.
2721  ///
2722  /// Because each CC action takes up 4 bits, we need to have the array size be
2723  /// large enough to fit all of the value types. This can be done by rounding
2724  /// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
2725  uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 7) / 8];
2726 
2727 protected:
2729 
2730 private:
2731  LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
2732 
2733  /// Targets can specify ISD nodes that they would like PerformDAGCombine
2734  /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
2735  /// array.
2736  unsigned char
2737  TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
2738 
2739  /// For operations that must be promoted to a specific type, this holds the
2740  /// destination type. This map should be sparse, so don't hold it as an
2741  /// array.
2742  ///
2743  /// Targets add entries to this map with AddPromotedToType(..), clients access
2744  /// this with getTypeToPromoteTo(..).
2745  std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
2746  PromoteToType;
2747 
2748  /// Stores the name each libcall.
2749  const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL + 1];
2750 
2751  /// The ISD::CondCode that should be used to test the result of each of the
2752  /// comparison libcall against zero.
2753  ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2754 
2755  /// Stores the CallingConv that should be used for each libcall.
2756  CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
2757 
2758  /// Set default libcall names and calling conventions.
2759  void InitLibcalls(const Triple &TT);
2760 
2761 protected:
2762  /// Return true if the extension represented by \p I is free.
2763  /// \pre \p I is a sign, zero, or fp extension and
2764  /// is[Z|FP]ExtFree of the related types is not true.
2765  virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
2766 
2767  /// Depth that GatherAllAliases should should continue looking for chain
2768  /// dependencies when trying to find a more preferable chain. As an
2769  /// approximation, this should be more than the number of consecutive stores
2770  /// expected to be merged.
2772 
2773  /// Specify maximum number of store instructions per memset call.
2774  ///
2775  /// When lowering \@llvm.memset this field specifies the maximum number of
2776  /// store operations that may be substituted for the call to memset. Targets
2777  /// must set this value based on the cost threshold for that target. Targets
2778  /// should assume that the memset will be done using as many of the largest
2779  /// store operations first, followed by smaller ones, if necessary, per
2780  /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
2781  /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
2782  /// store. This only applies to setting a constant array of a constant size.
2784 
2785  /// Maximum number of stores operations that may be substituted for the call
2786  /// to memset, used for functions with OptSize attribute.
2788 
2789  /// Specify maximum bytes of store instructions per memcpy call.
2790  ///
2791  /// When lowering \@llvm.memcpy this field specifies the maximum number of
2792  /// store operations that may be substituted for a call to memcpy. Targets
2793  /// must set this value based on the cost threshold for that target. Targets
2794  /// should assume that the memcpy will be done using as many of the largest
2795  /// store operations first, followed by smaller ones, if necessary, per
2796  /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
2797  /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
2798  /// and one 1-byte store. This only applies to copying a constant array of
2799  /// constant size.
2801 
2802 
2803  /// \brief Specify max number of store instructions to glue in inlined memcpy.
2804  ///
2805  /// When memcpy is inlined based on MaxStoresPerMemcpy, specify maximum number
2806  /// of store instructions to keep together. This helps in pairing and
2807  // vectorization later on.
2808  unsigned MaxGluedStoresPerMemcpy = 0;
2809 
2810  /// Maximum number of store operations that may be substituted for a call to
2811  /// memcpy, used for functions with OptSize attribute.
2815 
2816  /// Specify maximum bytes of store instructions per memmove call.
2817  ///
2818  /// When lowering \@llvm.memmove this field specifies the maximum number of
2819  /// store instructions that may be substituted for a call to memmove. Targets
2820  /// must set this value based on the cost threshold for that target. Targets
2821  /// should assume that the memmove will be done using as many of the largest
2822  /// store operations first, followed by smaller ones, if necessary, per
2823  /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2824  /// with 8-bit alignment would result in nine 1-byte stores. This only
2825  /// applies to copying a constant array of constant size.
2827 
2828  /// Maximum number of store instructions that may be substituted for a call to
2829  /// memmove, used for functions with OptSize attribute.
2831 
2832  /// Tells the code generator that select is more expensive than a branch if
2833  /// the branch is usually predicted right.
2835 
2836  /// \see enableExtLdPromotion.
2838 
2839  /// Return true if the value types that can be represented by the specified
2840  /// register class are all legal.
2841  bool isLegalRC(const TargetRegisterInfo &TRI,
2842  const TargetRegisterClass &RC) const;
2843 
2844  /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2845  /// sequence of memory operands that is recognized by PrologEpilogInserter.
2846  MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
2847  MachineBasicBlock *MBB) const;
2848 
2849  /// Replace/modify the XRay custom event operands with target-dependent
2850  /// details.
2851  MachineBasicBlock *emitXRayCustomEvent(MachineInstr &MI,
2852  MachineBasicBlock *MBB) const;
2853 
2854  /// Replace/modify the XRay typed event operands with target-dependent
2855  /// details.
2856  MachineBasicBlock *emitXRayTypedEvent(MachineInstr &MI,
2857  MachineBasicBlock *MBB) const;
2858 };
2859 
2860 /// This class defines information used to lower LLVM code to legal SelectionDAG
2861 /// operators that the target instruction selector can accept natively.
2862 ///
2863 /// This class also defines callbacks that targets must implement to lower
2864 /// target-specific constructs to SelectionDAG operators.
2866 public:
2867  struct DAGCombinerInfo;
2868 
2869  TargetLowering(const TargetLowering &) = delete;
2870  TargetLowering &operator=(const TargetLowering &) = delete;
2871 
2872  /// NOTE: The TargetMachine owns TLOF.
2873  explicit TargetLowering(const TargetMachine &TM);
2874 
2875  bool isPositionIndependent() const;
2876 
2877  virtual bool isSDNodeSourceOfDivergence(const SDNode *N,
2878  FunctionLoweringInfo *FLI,
2879  LegacyDivergenceAnalysis *DA) const {
2880  return false;
2881  }
2882 
2883  virtual bool isSDNodeAlwaysUniform(const SDNode * N) const {
2884  return false;
2885  }
2886 
2887  /// Returns true by value, base pointer and offset pointer and addressing mode
2888  /// by reference if the node's address can be legally represented as
2889  /// pre-indexed load / store address.
2890  virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2891  SDValue &/*Offset*/,
2892  ISD::MemIndexedMode &/*AM*/,
2893  SelectionDAG &/*DAG*/) const {
2894  return false;
2895  }
2896 
2897  /// Returns true by value, base pointer and offset pointer and addressing mode
2898  /// by reference if this node can be combined with a load / store to form a
2899  /// post-indexed load / store.
2900  virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2901  SDValue &/*Base*/,
2902  SDValue &/*Offset*/,
2903  ISD::MemIndexedMode &/*AM*/,
2904  SelectionDAG &/*DAG*/) const {
2905  return false;
2906  }
2907 
2908  /// Return the entry encoding for a jump table in the current function. The
2909  /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2910  virtual unsigned getJumpTableEncoding() const;
2911 
2912  virtual const MCExpr *
2914  const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2915  MCContext &/*Ctx*/) const {
2916  llvm_unreachable("Need to implement this hook if target has custom JTIs");
2917  }
2918 
2919  /// Returns relocation base for the given PIC jumptable.
2920  virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2921  SelectionDAG &DAG) const;
2922 
2923  /// This returns the relocation base for the given PIC jumptable, the same as
2924  /// getPICJumpTableRelocBase, but as an MCExpr.
2925  virtual const MCExpr *
2926  getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2927  unsigned JTI, MCContext &Ctx) const;
2928 
2929  /// Return true if folding a constant offset with the given GlobalAddress is
2930  /// legal. It is frequently not legal in PIC relocation models.
2931  virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2932 
2934  SDValue &Chain) const;
2935 
2936  void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
2937  SDValue &NewRHS, ISD::CondCode &CCCode,
2938  const SDLoc &DL) const;
2939 
2940  /// Returns a pair of (return value, chain).
2941  /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2942  std::pair<SDValue, SDValue> makeLibCall(
2943  SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef<SDValue> Ops,
2944  bool isSigned, const SDLoc &dl, bool doesNotReturn = false,
2945  bool isReturnValueUsed = true, bool isPostTypeLegalization = false) const;
2946 
2947  /// Check whether parameters to a call that are passed in callee saved
2948  /// registers are the same as from the calling function. This needs to be
2949  /// checked for tail call eligibility.
2950  bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
2951  const uint32_t *CallerPreservedMask,
2952  const SmallVectorImpl<CCValAssign> &ArgLocs,
2953  const SmallVectorImpl<SDValue> &OutVals) const;
2954 
2955  //===--------------------------------------------------------------------===//
2956  // TargetLowering Optimization Methods
2957  //
2958 
2959  /// A convenience struct that encapsulates a DAG, and two SDValues for
2960  /// returning information from TargetLowering to its clients that want to
2961  /// combine.
2964  bool LegalTys;
2965  bool LegalOps;
2968 
2970  bool LT, bool LO) :
2971  DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2972 
2973  bool LegalTypes() const { return LegalTys; }
2974  bool LegalOperations() const { return LegalOps; }
2975 
2977  Old = O;
2978  New = N;
2979  return true;
2980  }
2981  };
2982 
2983  /// Determines the optimal series of memory ops to replace the memset / memcpy.
2984  /// Return true if the number of memory ops is below the threshold (Limit).
2985  /// It returns the types of the sequence of memory ops to perform
2986  /// memset / memcpy by reference.
2987  bool findOptimalMemOpLowering(std::vector<EVT> &MemOps,
2988  unsigned Limit, uint64_t Size,
2989  unsigned DstAlign, unsigned SrcAlign,
2990  bool IsMemset,
2991  bool ZeroMemset,
2992  bool MemcpyStrSrc,
2993  bool AllowOverlap,
2994  unsigned DstAS, unsigned SrcAS,
2995  const AttributeList &FuncAttributes) const;
2996 
2997  /// Check to see if the specified operand of the specified instruction is a
2998  /// constant integer. If so, check to see if there are any bits set in the
2999  /// constant that are not demanded. If so, shrink the constant and return
3000  /// true.
3001  bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
3002  TargetLoweringOpt &TLO) const;
3003 
3004  // Target hook to do target-specific const optimization, which is called by
3005  // ShrinkDemandedConstant. This function should return true if the target
3006  // doesn't want ShrinkDemandedConstant to further optimize the constant.
3007  virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
3008  TargetLoweringOpt &TLO) const {
3009  return false;
3010  }
3011 
3012  /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
3013  /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
3014  /// generalized for targets with other types of implicit widening casts.
3015  bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
3016  TargetLoweringOpt &TLO) const;
3017 
3018  /// Look at Op. At this point, we know that only the DemandedBits bits of the
3019  /// result of Op are ever used downstream. If we can use this information to
3020  /// simplify Op, create a new simplified DAG node and return true, returning
3021  /// the original and new nodes in Old and New. Otherwise, analyze the
3022  /// expression and return a mask of KnownOne and KnownZero bits for the
3023  /// expression (used to simplify the caller). The KnownZero/One bits may only
3024  /// be accurate for those bits in the Demanded masks.
3025  /// \p AssumeSingleUse When this parameter is true, this function will
3026  /// attempt to simplify \p Op even if there are multiple uses.
3027  /// Callers are responsible for correctly updating the DAG based on the
3028  /// results of this function, because simply replacing replacing TLO.Old
3029  /// with TLO.New will be incorrect when this parameter is true and TLO.Old
3030  /// has multiple uses.
3031  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
3032  const APInt &DemandedElts, KnownBits &Known,
3033  TargetLoweringOpt &TLO, unsigned Depth = 0,
3034  bool AssumeSingleUse = false) const;
3035 
3036  /// Helper wrapper around SimplifyDemandedBits, demanding all elements.
3037  /// Adds Op back to the worklist upon success.
3038  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
3039  KnownBits &Known, TargetLoweringOpt &TLO,
3040  unsigned Depth = 0,
3041  bool AssumeSingleUse = false) const;
3042 
3043  /// Helper wrapper around SimplifyDemandedBits.
3044  /// Adds Op back to the worklist upon success.
3045  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
3046  DAGCombinerInfo &DCI) const;
3047 
3048  /// Look at Vector Op. At this point, we know that only the DemandedElts
3049  /// elements of the result of Op are ever used downstream. If we can use
3050  /// this information to simplify Op, create a new simplified DAG node and
3051  /// return true, storing the original and new nodes in TLO.
3052  /// Otherwise, analyze the expression and return a mask of KnownUndef and
3053  /// KnownZero elements for the expression (used to simplify the caller).
3054  /// The KnownUndef/Zero elements may only be accurate for those bits
3055  /// in the DemandedMask.
3056  /// \p AssumeSingleUse When this parameter is true, this function will
3057  /// attempt to simplify \p Op even if there are multiple uses.
3058  /// Callers are responsible for correctly updating the DAG based on the
3059  /// results of this function, because simply replacing replacing TLO.Old
3060  /// with TLO.New will be incorrect when this parameter is true and TLO.Old
3061  /// has multiple uses.
3062  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask,
3063  APInt &KnownUndef, APInt &KnownZero,
3064  TargetLoweringOpt &TLO, unsigned Depth = 0,
3065  bool AssumeSingleUse = false) const;
3066 
3067  /// Helper wrapper around SimplifyDemandedVectorElts.
3068  /// Adds Op back to the worklist upon success.
3069  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
3070  APInt &KnownUndef, APInt &KnownZero,
3071  DAGCombinerInfo &DCI) const;
3072 
3073  /// Determine which of the bits specified in Mask are known to be either zero
3074  /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
3075  /// argument allows us to only collect the known bits that are shared by the
3076  /// requested vector elements.
3077  virtual void computeKnownBitsForTargetNode(const SDValue Op,
3078  KnownBits &Known,
3079  const APInt &DemandedElts,
3080  const SelectionDAG &DAG,
3081  unsigned Depth = 0) const;
3082 
3083  /// Determine which of the bits of FrameIndex \p FIOp are known to be 0.
3084  /// Default implementation computes low bits based on alignment
3085  /// information. This should preserve known bits passed into it.
3086  virtual void computeKnownBitsForFrameIndex(const SDValue FIOp,
3087  KnownBits &Known,
3088  const APInt &DemandedElts,
3089  const SelectionDAG &DAG,
3090  unsigned Depth = 0) const;
3091 
3092  /// This method can be implemented by targets that want to expose additional
3093  /// information about sign bits to the DAG Combiner. The DemandedElts
3094  /// argument allows us to only collect the minimum sign bits that are shared
3095  /// by the requested vector elements.
3096  virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
3097  const APInt &DemandedElts,
3098  const SelectionDAG &DAG,
3099  unsigned Depth = 0) const;
3100 
3101  /// Attempt to simplify any target nodes based on the demanded vector
3102  /// elements, returning true on success. Otherwise, analyze the expression and
3103  /// return a mask of KnownUndef and KnownZero elements for the expression
3104  /// (used to simplify the caller). The KnownUndef/Zero elements may only be
3105  /// accurate for those bits in the DemandedMask.
3106  virtual bool SimplifyDemandedVectorEltsForTargetNode(
3107  SDValue Op, const APInt &DemandedElts, APInt &KnownUndef,
3108  APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth = 0) const;
3109 
3110  /// Attempt to simplify any target nodes based on the demanded bits/elts,
3111  /// returning true on success. Otherwise, analyze the
3112  /// expression and return a mask of KnownOne and KnownZero bits for the
3113  /// expression (used to simplify the caller). The KnownZero/One bits may only
3114  /// be accurate for those bits in the Demanded masks.
3115  virtual bool SimplifyDemandedBitsForTargetNode(SDValue Op,
3116  const APInt &DemandedBits,
3117  const APInt &DemandedElts,
3118  KnownBits &Known,
3119  TargetLoweringOpt &TLO,
3120  unsigned Depth = 0) const;
3121 
3122  /// If \p SNaN is false, \returns true if \p Op is known to never be any
3123  /// NaN. If \p sNaN is true, returns if \p Op is known to never be a signaling
3124  /// NaN.
3125  virtual bool isKnownNeverNaNForTargetNode(SDValue Op,
3126  const SelectionDAG &DAG,
3127  bool SNaN = false,
3128  unsigned Depth = 0) const;
3130  void *DC; // The DAG Combiner object.
3133 
3134  public:
3136 
3137  DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
3138  : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
3139 
3140  bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
3141  bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
3142  bool isAfterLegalizeDAG() const {
3143  return Level == AfterLegalizeDAG;
3144  }
3146  bool isCalledByLegalizer() const { return CalledByLegalizer; }
3147 
3148  void AddToWorklist(SDNode *N);
3149  SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
3150  SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
3151  SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
3152 
3153  void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
3154  };
3155 
3156  /// Return if the N is a constant or constant vector equal to the true value
3157  /// from getBooleanContents().
3158  bool isConstTrueVal(const SDNode *N) const;
3159 
3160  /// Return if the N is a constant or constant vector equal to the false value
3161  /// from getBooleanContents().
3162  bool isConstFalseVal(const SDNode *N) const;
3163 
3164  /// Return if \p N is a True value when extended to \p VT.
3165  bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) const;
3166 
3167  /// Try to simplify a setcc built with the specified operands and cc. If it is
3168  /// unable to simplify it, return a null SDValue.
3169  SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
3170  bool foldBooleans, DAGCombinerInfo &DCI,
3171  const SDLoc &dl) const;
3172 
3173  // For targets which wrap address, unwrap for analysis.
3174  virtual SDValue unwrapAddress(SDValue N) const { return N; }
3175 
3176  /// Returns true (and the GlobalValue and the offset) if the node is a
3177  /// GlobalAddress + offset.
3178  virtual bool
3179  isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
3180 
3181  /// This method will be invoked for all target nodes and for any
3182  /// target-independent nodes that the target has registered with invoke it
3183  /// for.
3184  ///
3185  /// The semantics are as follows:
3186  /// Return Value:
3187  /// SDValue.Val == 0 - No change was made
3188  /// SDValue.Val == N - N was replaced, is dead, and is already handled.
3189  /// otherwise - N should be replaced by the returned Operand.
3190  ///
3191  /// In addition, methods provided by DAGCombinerInfo may be used to perform
3192  /// more complex transformations.
3193  ///
3194  virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
3195 
3196  /// Return true if it is profitable to move this shift by a constant amount
3197  /// though its operand, adjusting any immediate operands as necessary to
3198  /// preserve semantics. This transformation may not be desirable if it
3199  /// disrupts a particularly auspicious target-specific tree (e.g. bitfield
3200  /// extraction in AArch64). By default, it returns true.
3201  ///
3202  /// @param N the shift node
3203  /// @param Level the current DAGCombine legalization level.
3204  virtual bool isDesirableToCommuteWithShift(const SDNode *N,
3205  CombineLevel Level) const {
3206  return true;
3207  }
3208 
3209  // Return true if it is profitable to combine a BUILD_VECTOR with a stride-pattern
3210  // to a shuffle and a truncate.
3211  // Example of such a combine:
3212  // v4i32 build_vector((extract_elt V, 1),
3213  // (extract_elt V, 3),
3214  // (extract_elt V, 5),
3215  // (extract_elt V, 7))
3216  // -->
3217  // v4i32 truncate (bitcast (shuffle<1,u,3,u,5,u,7,u> V, u) to v4i64)
3219  ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const {
3220  return false;
3221  }
3222 
3223  /// Return true if the target has native support for the specified value type
3224  /// and it is 'desirable' to use the type for the given node type. e.g. On x86
3225  /// i16 is legal, but undesirable since i16 instruction encodings are longer
3226  /// and some i16 instructions are slow.
3227  virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
3228  // By default, assume all legal types are desirable.
3229  return isTypeLegal(VT);
3230  }
3231 
3232  /// Return true if it is profitable for dag combiner to transform a floating
3233  /// point op of specified opcode to a equivalent op of an integer
3234  /// type. e.g. f32 load -> i32 load can be profitable on ARM.
3235  virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
3236  EVT /*VT*/) const {
3237  return false;
3238  }
3239 
3240  /// This method query the target whether it is beneficial for dag combiner to
3241  /// promote the specified node. If true, it should return the desired
3242  /// promotion type by reference.
3243  virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
3244  return false;
3245  }
3246 
3247  /// Return true if the target supports swifterror attribute. It optimizes
3248  /// loads and stores to reading and writing a specific register.
3249  virtual bool supportSwiftError() const {
3250  return false;
3251  }
3252 
3253  /// Return true if the target supports that a subset of CSRs for the given
3254  /// machine function is handled explicitly via copies.
3255  virtual bool supportSplitCSR(MachineFunction *MF) const {
3256  return false;
3257  }
3258 
3259  /// Perform necessary initialization to handle a subset of CSRs explicitly
3260  /// via copies. This function is called at the beginning of instruction
3261  /// selection.
3263  llvm_unreachable("Not Implemented");
3264  }
3265 
3266  /// Insert explicit copies in entry and exit blocks. We copy a subset of
3267  /// CSRs to virtual registers in the entry block, and copy them back to
3268  /// physical registers in the exit blocks. This function is called at the end
3269  /// of instruction selection.
3270  virtual void insertCopiesSplitCSR(
3272  const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
3273  llvm_unreachable("Not Implemented");
3274  }
3275 
3276  //===--------------------------------------------------------------------===//
3277  // Lowering methods - These methods must be implemented by targets so that
3278  // the SelectionDAGBuilder code knows how to lower these.
3279  //
3280 
3281  /// This hook must be implemented to lower the incoming (formal) arguments,
3282  /// described by the Ins array, into the specified DAG. The implementation
3283  /// should fill in the InVals array with legal-type argument values, and
3284  /// return the resulting token chain value.
3286  SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
3287  const SmallVectorImpl<ISD::InputArg> & /*Ins*/, const SDLoc & /*dl*/,
3288  SelectionDAG & /*DAG*/, SmallVectorImpl<SDValue> & /*InVals*/) const {
3289  llvm_unreachable("Not Implemented");
3290  }
3291 
3292  /// This structure contains all information that is necessary for lowering
3293  /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
3294  /// needs to lower a call, and targets will see this struct in their LowerCall
3295  /// implementation.
3298  Type *RetTy = nullptr;
3299  bool RetSExt : 1;
3300  bool RetZExt : 1;
3301  bool IsVarArg : 1;
3302  bool IsInReg : 1;
3303  bool DoesNotReturn : 1;
3305  bool IsConvergent : 1;
3306  bool IsPatchPoint : 1;
3307 
3308  // IsTailCall should be modified by implementations of
3309  // TargetLowering::LowerCall that perform tail call conversions.
3310  bool IsTailCall = false;
3311 
3312  // Is Call lowering done post SelectionDAG type legalization.
3313  bool IsPostTypeLegalization = false;
3314 
3315  unsigned NumFixedArgs = -1;
3318  ArgListTy Args;
3326 
3328  : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
3329  DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
3330  IsPatchPoint(false), DAG(DAG) {}
3331 
3333  DL = dl;
3334  return *this;
3335  }
3336 
3338  Chain = InChain;
3339  return *this;
3340  }
3341 
3342  // setCallee with target/module-specific attributes
3344  SDValue Target, ArgListTy &&ArgsList) {
3345  RetTy = ResultType;
3346  Callee = Target;
3347  CallConv = CC;
3348  NumFixedArgs = ArgsList.size();
3349  Args = std::move(ArgsList);
3350 
3352  &(DAG.getMachineFunction()), CC, Args);
3353  return *this;
3354  }
3355 
3357  SDValue Target, ArgListTy &&ArgsList) {
3358  RetTy = ResultType;
3359  Callee = Target;
3360  CallConv = CC;
3361  NumFixedArgs = ArgsList.size();
3362  Args = std::move(ArgsList);
3363  return *this;
3364  }
3365 
3367  SDValue Target, ArgListTy &&ArgsList,
3368  ImmutableCallSite Call) {
3369  RetTy = ResultType;
3370 
3371  IsInReg = Call.hasRetAttr(Attribute::InReg);
3372  DoesNotReturn =
3373  Call.doesNotReturn() ||
3374  (!Call.isInvoke() &&
3375  isa<UnreachableInst>(Call.getInstruction()->getNextNode()));
3376  IsVarArg = FTy->isVarArg();
3377  IsReturnValueUsed = !Call.getInstruction()->use_empty();
3378  RetSExt = Call.hasRetAttr(Attribute::SExt);
3379  RetZExt = Call.hasRetAttr(Attribute::ZExt);
3380 
3381  Callee = Target;
3382 
3383  CallConv = Call.getCallingConv();
3384  NumFixedArgs = FTy->getNumParams();
3385  Args = std::move(ArgsList);
3386 
3387  CS = Call;
3388 
3389  return *this;
3390  }
3391 
3393  IsInReg = Value;
3394  return *this;
3395  }
3396 
3398  DoesNotReturn = Value;
3399  return *this;
3400  }
3401 
3403  IsVarArg = Value;
3404  return *this;
3405  }
3406 
3408  IsTailCall = Value;
3409  return *this;
3410  }
3411 
3413  IsReturnValueUsed = !Value;
3414  return *this;
3415  }
3416 
3418  IsConvergent = Value;
3419  return *this;
3420  }
3421 
3423  RetSExt = Value;
3424  return *this;
3425  }
3426 
3428  RetZExt = Value;
3429  return *this;
3430  }
3431 
3433  IsPatchPoint = Value;
3434  return *this;
3435  }
3436 
3438  IsPostTypeLegalization = Value;
3439  return *this;
3440  }
3441 
3442  ArgListTy &getArgs() {
3443  return Args;
3444  }
3445  };
3446 
3447  /// This function lowers an abstract call to a function into an actual call.
3448  /// This returns a pair of operands. The first element is the return value
3449  /// for the function (if RetTy is not VoidTy). The second element is the
3450  /// outgoing token chain. It calls LowerCall to do the actual lowering.
3451  std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
3452 
3453  /// This hook must be implemented to lower calls into the specified
3454  /// DAG. The outgoing arguments to the call are described by the Outs array,
3455  /// and the values to be returned by the call are described by the Ins
3456  /// array. The implementation should fill in the InVals array with legal-type
3457  /// return values from the call, and return the resulting token chain value.
3458  virtual SDValue
3460  SmallVectorImpl<SDValue> &/*InVals*/) const {
3461  llvm_unreachable("Not Implemented");
3462  }
3463 
3464  /// Target-specific cleanup for formal ByVal parameters.
3465  virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
3466 
3467  /// This hook should be implemented to check whether the return values
3468  /// described by the Outs array can fit into the return registers. If false
3469  /// is returned, an sret-demotion is performed.
3470  virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
3471  MachineFunction &/*MF*/, bool /*isVarArg*/,
3472  const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
3473  LLVMContext &/*Context*/) const
3474  {
3475  // Return true by default to get preexisting behavior.
3476  return true;
3477  }
3478 
3479  /// This hook must be implemented to lower outgoing return values, described
3480  /// by the Outs array, into the specified DAG. The implementation should
3481  /// return the resulting token chain value.
3482  virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
3483  bool /*isVarArg*/,
3484  const SmallVectorImpl<ISD::OutputArg> & /*Outs*/,
3485  const SmallVectorImpl<SDValue> & /*OutVals*/,
3486  const SDLoc & /*dl*/,
3487  SelectionDAG & /*DAG*/) const {
3488  llvm_unreachable("Not Implemented");
3489  }
3490 
3491  /// Return true if result of the specified node is used by a return node
3492  /// only. It also compute and return the input chain for the tail call.
3493  ///
3494  /// This is used to determine whether it is possible to codegen a libcall as
3495  /// tail call at legalization time.
3496  virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
3497  return false;
3498  }
3499 
3500  /// Return true if the target may be able emit the call instruction as a tail
3501  /// call. This is used by optimization passes to determine if it's profitable
3502  /// to duplicate return instructions to enable tailcall optimization.
3503  virtual bool mayBeEmittedAsTailCall(const CallInst *) const {
3504  return false;
3505  }
3506 
3507  /// Return the builtin name for the __builtin___clear_cache intrinsic
3508  /// Default is to invoke the clear cache library call
3509  virtual const char * getClearCacheBuiltinName() const {
3510  return "__clear_cache";
3511  }
3512 
3513  /// Return the register ID of the name passed in. Used by named register
3514  /// global variables extension. There is no target-independent behaviour
3515  /// so the default action is to bail.
3516  virtual unsigned getRegisterByName(const char* RegName, EVT VT,
3517  SelectionDAG &DAG) const {
3518  report_fatal_error("Named registers not implemented for this target");
3519  }
3520 
3521  /// Return the type that should be used to zero or sign extend a
3522  /// zeroext/signext integer return value. FIXME: Some C calling conventions
3523  /// require the return type to be promoted, but this is not true all the time,
3524  /// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling
3525  /// conventions. The frontend should handle this and include all of the
3526  /// necessary information.
3528  ISD::NodeType /*ExtendKind*/) const {
3529  EVT MinVT = getRegisterType(Context, MVT::i32);
3530  return VT.bitsLT(MinVT) ? MinVT : VT;
3531  }
3532 
3533  /// For some targets, an LLVM struct type must be broken down into multiple
3534  /// simple types, but the calling convention specifies that the entire struct
3535  /// must be passed in a block of consecutive registers.
3536  virtual bool
3538  bool isVarArg) const {
3539  return false;
3540  }
3541 
3542  /// For most targets, an LLVM type must be broken down into multiple
3543  /// smaller types. Usually the halves are ordered according to the endianness
3544  /// but for some platform that would break. So this method will default to
3545  /// matching the endianness but can be overridden.
3546  virtual bool
3548  return DL.isLittleEndian();
3549  }
3550 
3551  /// Returns a 0 terminated array of registers that can be safely used as
3552  /// scratch registers.
3553  virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
3554  return nullptr;
3555  }
3556 
3557  /// This callback is used to prepare for a volatile or atomic load.
3558  /// It takes a chain node as input and returns the chain for the load itself.
3559  ///
3560  /// Having a callback like this is necessary for targets like SystemZ,
3561  /// which allows a CPU to reuse the result of a previous load indefinitely,
3562  /// even if a cache-coherent store is performed by another CPU. The default
3563  /// implementation does nothing.
3565  SelectionDAG &DAG) const {
3566  return Chain;
3567  }
3568 
3569  /// This callback is used to inspect load/store instructions and add
3570  /// target-specific MachineMemOperand flags to them. The default
3571  /// implementation does nothing.
3574  }
3575 
3576  /// This callback is invoked by the type legalizer to legalize nodes with an
3577  /// illegal operand type but legal result types. It replaces the
3578  /// LowerOperation callback in the type Legalizer. The reason we can not do
3579  /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
3580  /// use this callback.
3581  ///
3582  /// TODO: Consider merging with ReplaceNodeResults.
3583  ///
3584  /// The target places new result values for the node in Results (their number
3585  /// and types must exactly match those of the original return values of
3586  /// the node), or leaves Results empty, which indicates that the node is not
3587  /// to be custom lowered after all.
3588  /// The default implementation calls LowerOperation.
3589  virtual void LowerOperationWrapper(SDNode *N,
3591  SelectionDAG &DAG) const;
3592 
3593  /// This callback is invoked for operations that are unsupported by the
3594  /// target, which are registered to use 'custom' lowering, and whose defined
3595  /// values are all legal. If the target has no operations that require custom
3596  /// lowering, it need not implement this. The default implementation of this
3597  /// aborts.
3598  virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
3599 
3600  /// This callback is invoked when a node result type is illegal for the
3601  /// target, and the operation was registered to use 'custom' lowering for that
3602  /// result type. The target places new result values for the node in Results
3603  /// (their number and types must exactly match those of the original return
3604  /// values of the node), or leaves Results empty, which indicates that the
3605  /// node is not to be custom lowered after all.
3606  ///
3607  /// If the target has no operations that require custom lowering, it need not
3608  /// implement this. The default implementation aborts.
3609  virtual void ReplaceNodeResults(SDNode * /*N*/,
3610  SmallVectorImpl<SDValue> &/*Results*/,
3611  SelectionDAG &/*DAG*/) const {
3612  llvm_unreachable("ReplaceNodeResults not implemented for this target!");
3613  }
3614 
3615  /// This method returns the name of a target specific DAG node.
3616  virtual const char *getTargetNodeName(unsigned Opcode) const;
3617 
3618  /// This method returns a target specific FastISel object, or null if the
3619  /// target does not support "fast" ISel.
3621  const TargetLibraryInfo *) const {
3622  return nullptr;
3623  }
3624 
3625  bool verifyReturnAddressArgumentIsConstant(SDValue Op,
3626  SelectionDAG &DAG) const;
3627 
3628  //===--------------------------------------------------------------------===//
3629  // Inline Asm Support hooks
3630  //
3631 
3632  /// This hook allows the target to expand an inline asm call to be explicit
3633  /// llvm code if it wants to. This is useful for turning simple inline asms
3634  /// into LLVM intrinsics, which gives the compiler more information about the
3635  /// behavior of the code.
3636  virtual bool ExpandInlineAsm(CallInst *) const {
3637  return false;
3638  }
3639 
3641  C_Register, // Constraint represents specific register(s).
3642  C_RegisterClass, // Constraint represents any of register(s) in class.
3643  C_Memory, // Memory constraint.
3644  C_Other, // Something else.
3645  C_Unknown // Unsupported constraint.
3646  };
3647 
3649  // Generic weights.
3650  CW_Invalid = -1, // No match.
3651  CW_Okay = 0, // Acceptable.
3652  CW_Good = 1, // Good weight.
3653  CW_Better = 2, // Better weight.
3654  CW_Best = 3, // Best weight.
3655 
3656  // Well-known weights.
3657  CW_SpecificReg = CW_Okay, // Specific register operands.
3658  CW_Register = CW_Good, // Register operands.
3659  CW_Memory = CW_Better, // Memory operands.
3660  CW_Constant = CW_Best, // Constant operand.
3661  CW_Default = CW_Okay // Default or don't know type.
3662  };
3663 
3664  /// This contains information for each constraint that we are lowering.
3666  /// This contains the actual string for the code, like "m". TargetLowering
3667  /// picks the 'best' code from ConstraintInfo::Codes that most closely
3668  /// matches the operand.
3669  std::string ConstraintCode;
3670 
3671  /// Information about the constraint code, e.g. Register, RegisterClass,
3672  /// Memory, Other, Unknown.
3674 
3675  /// If this is the result output operand or a clobber, this is null,
3676  /// otherwise it is the incoming operand to the CallInst. This gets
3677  /// modified as the asm is processed.
3678  Value *CallOperandVal = nullptr;
3679 
3680  /// The ValueType for the operand value.
3681  MVT ConstraintVT = MVT::Other;
3682 
3683  /// Copy constructor for copying from a ConstraintInfo.
3685  : InlineAsm::ConstraintInfo(std::move(Info)) {}
3686 
3687  /// Return true of this is an input operand that is a matching constraint
3688  /// like "4".
3689  bool isMatchingInputConstraint() const;
3690 
3691  /// If this is an input matching constraint, this method returns the output
3692  /// operand it matches.
3693  unsigned getMatchedOperand() const;
3694  };
3695 
3696  using AsmOperandInfoVector = std::vector<AsmOperandInfo>;
3697 
3698  /// Split up the constraint string from the inline assembly value into the
3699  /// specific constraints and their prefixes, and also tie in the associated
3700  /// operand values. If this returns an empty vector, and if the constraint
3701  /// string itself isn't empty, there was an error parsing.
3702  virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
3703  const TargetRegisterInfo *TRI,
3704  ImmutableCallSite CS) const;
3705 
3706  /// Examine constraint type and operand type and determine a weight value.
3707  /// The operand object must already have been set up with the operand type.
3708  virtual ConstraintWeight getMultipleConstraintMatchWeight(
3709  AsmOperandInfo &info, int maIndex) const;
3710 
3711  /// Examine constraint string and operand type and determine a weight value.
3712  /// The operand object must already have been set up with the operand type.
3713  virtual ConstraintWeight getSingleConstraintMatchWeight(
3714  AsmOperandInfo &info, const char *constraint) const;
3715 
3716  /// Determines the constraint code and constraint type to use for the specific
3717  /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
3718  /// If the actual operand being passed in is available, it can be passed in as
3719  /// Op, otherwise an empty SDValue can be passed.
3720  virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3721  SDValue Op,
3722  SelectionDAG *DAG = nullptr) const;
3723 
3724  /// Given a constraint, return the type of constraint it is for this target.
3725  virtual ConstraintType getConstraintType(StringRef Constraint) const;
3726 
3727  /// Given a physical register constraint (e.g. {edx}), return the register
3728  /// number and the register class for the register.
3729  ///
3730  /// Given a register class constraint, like 'r', if this corresponds directly
3731  /// to an LLVM register class, return a register of 0 and the register class
3732  /// pointer.
3733  ///
3734  /// This should only be used for C_Register constraints. On error, this
3735  /// returns a register number of 0 and a null register class pointer.
3736  virtual std::pair<unsigned, const TargetRegisterClass *>
3737  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3738  StringRef Constraint, MVT VT) const;
3739 
3740  virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
3741  if (ConstraintCode == "i")
3742  return InlineAsm::Constraint_i;
3743  else if (ConstraintCode == "m")
3744  return InlineAsm::Constraint_m;
3746  }
3747 
3748  /// Try to replace an X constraint, which matches anything, with another that
3749  /// has more specific requirements based on the type of the corresponding
3750  /// operand. This returns null if there is no replacement to make.
3751  virtual const char *LowerXConstraint(EVT ConstraintVT) const;
3752 
3753  /// Lower the specified operand into the Ops vector. If it is invalid, don't
3754  /// add anything to Ops.
3755  virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
3756  std::vector<SDValue> &Ops,
3757  SelectionDAG &DAG) const;
3758 
3759  // Lower custom output constraints. If invalid, return SDValue().
3760  virtual SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag,
3761  SDLoc DL,
3762  const AsmOperandInfo &OpInfo,
3763  SelectionDAG &DAG) const;
3764 
3765  //===--------------------------------------------------------------------===//
3766  // Div utility functions
3767  //
3768  SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3769  SmallVectorImpl<SDNode *> &Created) const;
3770  SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3771  SmallVectorImpl<SDNode *> &Created) const;
3772 
3773  /// Targets may override this function to provide custom SDIV lowering for
3774  /// power-of-2 denominators. If the target returns an empty SDValue, LLVM
3775  /// assumes SDIV is expensive and replaces it with a series of other integer
3776  /// operations.
3777  virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
3778  SelectionDAG &DAG,
3779  SmallVectorImpl<SDNode *> &Created) const;
3780 
3781  /// Indicate whether this target prefers to combine FDIVs with the same
3782  /// divisor. If the transform should never be done, return zero. If the
3783  /// transform should be done, return the minimum number of divisor uses
3784  /// that must exist.
3785  virtual unsigned combineRepeatedFPDivisors() const {
3786  return 0;
3787  }
3788 
3789  /// Hooks for building estimates in place of slower divisions and square
3790  /// roots.
3791 
3792  /// Return either a square root or its reciprocal estimate value for the input
3793  /// operand.
3794  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3795  /// 'Enabled' as set by a potential default override attribute.
3796  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3797  /// refinement iterations required to generate a sufficient (though not
3798  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3799  /// The boolean UseOneConstNR output is used to select a Newton-Raphson
3800  /// algorithm implementation that uses either one or two constants.
3801  /// The boolean Reciprocal is used to select whether the estimate is for the
3802  /// square root of the input operand or the reciprocal of its square root.
3803  /// A target may choose to implement its own refinement within this function.
3804  /// If that's true, then return '0' as the number of RefinementSteps to avoid
3805  /// any further refinement of the estimate.
3806  /// An empty SDValue return means no estimate sequence can be created.
3808  int Enabled, int &RefinementSteps,
3809  bool &UseOneConstNR, bool Reciprocal) const {
3810  return SDValue();
3811  }
3812 
3813  /// Return a reciprocal estimate value for the input operand.
3814  /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3815  /// 'Enabled' as set by a potential default override attribute.
3816  /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3817  /// refinement iterations required to generate a sufficient (though not
3818  /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3819  /// A target may choose to implement its own refinement within this function.
3820  /// If that's true, then return '0' as the number of RefinementSteps to avoid
3821  /// any further refinement of the estimate.
3822  /// An empty SDValue return means no estimate sequence can be created.
3824  int Enabled, int &RefinementSteps) const {
3825  return SDValue();
3826  }
3827 
3828  //===--------------------------------------------------------------------===//
3829  // Legalization utility functions
3830  //
3831 
3832  /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes,
3833  /// respectively, each computing an n/2-bit part of the result.
3834  /// \param Result A vector that will be filled with the parts of the result
3835  /// in little-endian order.
3836  /// \param LL Low bits of the LHS of the MUL. You can use this parameter
3837  /// if you want to control how low bits are extracted from the LHS.
3838  /// \param LH High bits of the LHS of the MUL. See LL for meaning.
3839  /// \param RL Low bits of the RHS of the MUL. See LL for meaning
3840  /// \param RH High bits of the RHS of the MUL. See LL for meaning.
3841  /// \returns true if the node has been expanded, false if it has not
3842  bool expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS,
3843  SDValue RHS, SmallVectorImpl<SDValue> &Result, EVT HiLoVT,
3845  SDValue LL = SDValue(), SDValue LH = SDValue(),
3846  SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3847 
3848  /// Expand a MUL into two nodes. One that computes the high bits of
3849  /// the result and one that computes the low bits.
3850  /// \param HiLoVT The value type to use for the Lo and Hi nodes.
3851  /// \param LL Low bits of the LHS of the MUL. You can use this parameter
3852  /// if you want to control how low bits are extracted from the LHS.
3853  /// \param LH High bits of the LHS of the MUL. See LL for meaning.
3854  /// \param RL Low bits of the RHS of the MUL. See LL for meaning
3855  /// \param RH High bits of the RHS of the MUL. See LL for meaning.
3856  /// \returns true if the node has been expanded. false if it has not
3857  bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
3858  SelectionDAG &DAG, MulExpansionKind Kind,
3859  SDValue LL = SDValue(), SDValue LH = SDValue(),
3860  SDValue RL = SDValue(), SDValue RH = SDValue()) const;
3861 
3862  /// Expand funnel shift.
3863  /// \param N Node to expand
3864  /// \param Result output after conversion
3865  /// \returns True, if the expansion was successful, false otherwise
3866  bool expandFunnelShift(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3867 
3868  /// Expand rotations.
3869  /// \param N Node to expand
3870  /// \param Result output after conversion
3871  /// \returns True, if the expansion was successful, false otherwise
3872  bool expandROT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3873 
3874  /// Expand float(f32) to SINT(i64) conversion
3875  /// \param N Node to expand
3876  /// \param Result output after conversion
3877  /// \returns True, if the expansion was successful, false otherwise
3878  bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3879 
3880  /// Expand float to UINT conversion
3881  /// \param N Node to expand
3882  /// \param Result output after conversion
3883  /// \returns True, if the expansion was successful, false otherwise
3884  bool expandFP_TO_UINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3885 
3886  /// Expand UINT(i64) to double(f64) conversion
3887  /// \param N Node to expand
3888  /// \param Result output after conversion
3889  /// \returns True, if the expansion was successful, false otherwise
3890  bool expandUINT_TO_FP(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3891 
3892  /// Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs.
3893  SDValue expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) const;
3894 
3895  /// Expand CTPOP nodes. Expands vector/scalar CTPOP nodes,
3896  /// vector nodes can only succeed if all operations are legal/custom.
3897  /// \param N Node to expand
3898  /// \param Result output after conversion
3899  /// \returns True, if the expansion was successful, false otherwise
3900  bool expandCTPOP(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3901 
3902  /// Expand CTLZ/CTLZ_ZERO_UNDEF nodes. Expands vector/scalar CTLZ nodes,
3903  /// vector nodes can only succeed if all operations are legal/custom.
3904  /// \param N Node to expand
3905  /// \param Result output after conversion
3906  /// \returns True, if the expansion was successful, false otherwise
3907  bool expandCTLZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3908 
3909  /// Expand CTTZ/CTTZ_ZERO_UNDEF nodes. Expands vector/scalar CTTZ nodes,
3910  /// vector nodes can only succeed if all operations are legal/custom.
3911  /// \param N Node to expand
3912  /// \param Result output after conversion
3913  /// \returns True, if the expansion was successful, false otherwise
3914  bool expandCTTZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3915 
3916  /// Expand ABS nodes. Expands vector/scalar ABS nodes,
3917  /// vector nodes can only succeed if all operations are legal/custom.
3918  /// (ABS x) -> (XOR (ADD x, (SRA x, type_size)), (SRA x, type_size))
3919  /// \param N Node to expand
3920  /// \param Result output after conversion
3921  /// \returns True, if the expansion was successful, false otherwise
3922  bool expandABS(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
3923 
3924  /// Turn load of vector type into a load of the individual elements.
3925  /// \param LD load to expand
3926  /// \returns MERGE_VALUEs of the scalar loads with their chains.
3927  SDValue scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const;
3928 
3929  // Turn a store of a vector type into stores of the individual elements.
3930  /// \param ST Store with a vector value type
3931  /// \returns MERGE_VALUs of the individual store chains.
3932  SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3933 
3934  /// Expands an unaligned load to 2 half-size loads for an integer, and
3935  /// possibly more for vectors.
3936  std::pair<SDValue, SDValue> expandUnalignedLoad(LoadSDNode *LD,
3937  SelectionDAG &DAG) const;
3938 
3939  /// Expands an unaligned store to 2 half-size stores for integer values, and
3940  /// possibly more for vectors.
3941  SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const;
3942 
3943  /// Increments memory address \p Addr according to the type of the value
3944  /// \p DataVT that should be stored. If the data is stored in compressed
3945  /// form, the memory address should be incremented according to the number of
3946  /// the stored elements. This number is equal to the number of '1's bits
3947  /// in the \p Mask.
3948  /// \p DataVT is a vector type. \p Mask is a vector value.
3949  /// \p DataVT and \p Mask have the same number of vector elements.
3950  SDValue IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL,
3951  EVT DataVT, SelectionDAG &DAG,
3952  bool IsCompressedMemory) const;
3953 
3954  /// Get a pointer to vector element \p Idx located in memory for a vector of
3955  /// type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of
3956  /// bounds the returned pointer is unspecified, but will be within the vector
3957  /// bounds.
3958  SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
3959  SDValue Index) const;
3960 
3961  /// Method for building the DAG expansion of ISD::[US][ADD|SUB]SAT. This
3962  /// method accepts integers as its arguments.
3963  SDValue expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const;
3964 
3965  /// Method for building the DAG expansion of ISD::SMULFIX. This method accepts
3966  /// integers as its arguments.
3967  SDValue expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) const;
3968 
3969  /// Method for building the DAG expansion of ISD::U(ADD|SUB)O. Expansion
3970  /// always suceeds and populates the Result and Overflow arguments.
3971  void expandUADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow,
3972  SelectionDAG &DAG) const;
3973 
3974  /// Method for building the DAG expansion of ISD::S(ADD|SUB)O. Expansion
3975  /// always suceeds and populates the Result and Overflow arguments.
3976  void expandSADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow,
3977  SelectionDAG &DAG) const;
3978 
3979  /// Method for building the DAG expansion of ISD::[US]MULO. Returns whether
3980  /// expansion was successful and populates the Result and Overflow arguments.
3981  bool expandMULO(SDNode *Node, SDValue &Result, SDValue &Overflow,
3982  SelectionDAG &DAG) const;
3983 
3984  /// Expand a VECREDUCE_* into an explicit calculation. If Count is specified,
3985  /// only the first Count elements of the vector are used.
3986  SDValue expandVecReduce(SDNode *Node, SelectionDAG &DAG) const;
3987 
3988  //===--------------------------------------------------------------------===//
3989  // Instruction Emitting Hooks
3990  //
3991 
3992  /// This method should be implemented by targets that mark instructions with
3993  /// the 'usesCustomInserter' flag. These instructions are special in various
3994  /// ways, which require special support to insert. The specified MachineInstr
3995  /// is created but not inserted into any basic blocks, and this method is
3996  /// called to expand it into a sequence of instructions, potentially also
3997  /// creating new basic blocks and control flow.
3998  /// As long as the returned basic block is different (i.e., we created a new
3999  /// one), the custom inserter is free to modify the rest of \p MBB.
4000  virtual MachineBasicBlock *
4001  EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
4002 
4003  /// This method should be implemented by targets that mark instructions with
4004  /// the 'hasPostISelHook' flag. These instructions must be adjusted after
4005  /// instruction selection by target hooks. e.g. To fill in optional defs for
4006  /// ARM 's' setting instructions.
4007  virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,
4008  SDNode *Node) const;
4009 
4010  /// If this function returns true, SelectionDAGBuilder emits a
4011  /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
4012  virtual bool useLoadStackGuardNode() const {
4013  return false;
4014  }
4015 
4017  const SDLoc &DL) const {
4018  llvm_unreachable("not implemented for this target");
4019  }
4020 
4021  /// Lower TLS global address SDNode for target independent emulated TLS model.
4022  virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
4023  SelectionDAG &DAG) const;
4024 
4025  /// Expands target specific indirect branch for the case of JumpTable
4026  /// expanasion.
4028  SelectionDAG &DAG) const {
4029  return DAG.getNode(ISD::BRIND, dl, MVT::Other, Value, Addr);
4030  }
4031 
4032  // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
4033  // If we're comparing for equality to zero and isCtlzFast is true, expose the
4034  // fact that this can be implemented as a ctlz/srl pair, so that the dag
4035  // combiner can fold the new nodes.
4036  SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;
4037 
4038 private:
4039  SDValue foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
4040  const SDLoc &DL, DAGCombinerInfo &DCI) const;
4041  SDValue foldSetCCWithBinOp(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
4042  const SDLoc &DL, DAGCombinerInfo &DCI) const;
4043 
4044  SDValue optimizeSetCCOfSignedTruncationCheck(EVT SCCVT, SDValue N0,
4045  SDValue N1, ISD::CondCode Cond,
4046  DAGCombinerInfo &DCI,
4047  const SDLoc &DL) const;
4048 };
4049 
4050 /// Given an LLVM IR type and return type attributes, compute the return value
4051 /// EVTs and flags, and optionally also the offsets, if the return value is
4052 /// being lowered to memory.
4055  const TargetLowering &TLI, const DataLayout &DL);
4056 
4057 } // end namespace llvm
4058 
4059 #endif // LLVM_CODEGEN_TARGETLOWERING_H
virtual AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass...
LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return how this load with extension should be treated: either it is legal, needs to be promoted to a ...
virtual bool isJumpTableRelative() const
uint64_t CallInst * C
X = FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:562
static MVT getIntegerVT(unsigned BitWidth)
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:913
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:622
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
EVT getValueType() const
Return the ValueType of the referenced return value.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
bool isInteger() const
Return true if this is an integer or a vector integer type.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
virtual bool canMergeStoresTo(unsigned AS, EVT MemVT, const SelectionDAG &DAG) const
Returns if it&#39;s reasonable to merge stores to MemVT size.
unsigned getIndexSizeInBits(unsigned AS) const
Size in bits of index used for address calculation in getelementptr.
Definition: DataLayout.h:398
virtual bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:300
bool usesUnderscoreLongJmp() const
Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
LLVMContext & Context
virtual bool shouldInsertFencesForAtomic(const Instruction *I) const
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic...
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
Atomic ordering constants.
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
Definition: ilist_node.h:288
virtual SDValue expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr, SelectionDAG &DAG) const
Expands target specific indirect branch for the case of JumpTable expanasion.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isOperationCustom(unsigned Op, EVT VT) const
Return true if the operation uses custom lowering, regardless of whether the type is legal or not...
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0...
Definition: ISDOpcodes.h:633
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
virtual const TargetRegisterClass * getRepRegClassFor(MVT VT) const
Return the &#39;representative&#39; register class for the specified value type.
virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const
Return if the target supports combining a chain like:
bool hasOptSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:603
virtual bool reduceSelectOfFPConstantLoads(bool IsFPSetCC) const
Return true if it is profitable to convert a select of FP constants into a constant pool load whose a...
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:528
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:284
CallLoweringInfo & setIsPostTypeLegalization(bool Value=true)
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
void setJumpBufAlignment(unsigned Align)
Set the target&#39;s required jmp_buf buffer alignment (in bytes); default is 0.
bool usesUnderscoreSetJmp() const
Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
virtual unsigned getRegisterByName(const char *RegName, EVT VT, SelectionDAG &DAG) const
Return the register ID of the name passed in.
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:222
virtual unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
virtual bool enableAggressiveFMAFusion(EVT VT) const
Return true if target always beneficiates from combining into FMA for a given value type...
virtual bool getPreIndexedAddressParts(SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node&#39;s...
virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const
Hooks for building estimates in place of slower divisions and square roots.
This class represents a function call, abstracting a target machine&#39;s calling convention.
virtual bool isFNegFree(EVT VT) const
Return true if an fneg operation is free to the point where it is never worthwhile to replace it with...
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
virtual unsigned combineRepeatedFPDivisors() const
Indicate whether this target prefers to combine FDIVs with the same divisor.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
virtual bool isExtractVecEltCheap(EVT VT, unsigned Index) const
Return true if extraction of a scalar element from the given vector type at the given index is cheap...
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:250
static ISD::NodeType getExtendForContent(BooleanContent Content)
unsigned getVectorNumElements() const
virtual bool isSelectSupported(SelectSupportKind) const
Function Alias Analysis Results
bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const
Return true if lowering to a bit test is suitable for a set of case clusters which contains NumDests ...
This instruction constructs a fixed permutation of two input vectors.
virtual bool isCommutativeBinOp(unsigned Opcode) const
Returns true if the opcode is a commutative binary operation.
virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC, ArgListTy &Args) const
bool hasRetAttr(Attribute::AttrKind Kind) const
Return true if this return value has the given attribute.
Definition: CallSite.h:380
unsigned getMaxStoresPerMemset(bool OptSize) const
Get maximum # of store operations permitted for llvm.memset.
virtual void HandleByVal(CCState *, unsigned &, unsigned) const
Target-specific cleanup for formal ByVal parameters.
CallLoweringInfo & setNoReturn(bool Value=true)
virtual bool isSafeMemOpType(MVT) const
Returns true if it&#39;s safe to use load / store of the specified type to expand memcpy / memset inline...
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:388
Constrained versions of the binary floating point operators.
Definition: ISDOpcodes.h:293
LegalizeAction getIndexedStoreAction(unsigned IdxMode, MVT VT) const
Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger ...
bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const
Return true if the specified store with truncation is legal on this target.
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Return the register class that should be used for the specified value type.
unsigned const TargetRegisterInfo * TRI
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:140
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1077
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
bool hasMultipleConditionRegisters() const
Return true if multiple condition registers are available.
block Block Frequency true
An instruction for reading from memory.
Definition: Instructions.h:167
virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass...
virtual bool mayBeEmittedAsTailCall(const CallInst *) const
Return true if the target may be able emit the call instruction as a tail call.
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
Return true if the target has native support for the specified value type and it is &#39;desirable&#39; to us...
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:408
bool hasExtractBitsInsn() const
Return true if the target has BitExtract instructions.
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:691
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all...
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
virtual bool storeOfVectorConstantIsCheap(EVT MemVT, unsigned NumElem, unsigned AddrSpace) const
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the give...
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
LegalizeAction getFixedPointOperationAction(unsigned Op, EVT VT, unsigned Scale) const
Some fixed point operations may be natively supported by the target but only for specific scales...
unsigned getJumpBufAlignment() const
Returns the target&#39;s jmp_buf alignment in bytes (if never set, the default is 0)
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it...
CallLoweringInfo & setDiscardResult(bool Value=true)
virtual StringRef getStackProbeSymbolName(MachineFunction &MF) const
Returns the name of the symbol used to emit stack probes or the empty string if not applicable...
uint64_t High
virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:38
bool isValid() const
Return true if this is a valid simple valuetype.
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal on this target.
virtual Value * emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const
Perform a masked atomicrmw using a target-specific intrinsic.
CallLoweringInfo & setCallee(Type *ResultType, FunctionType *FTy, SDValue Target, ArgListTy &&ArgsList, ImmutableCallSite Call)
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:129
virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const
Return true if an fpext operation is free (for instance, because single-precision floating-point numb...
virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const
Return true if the following transform is beneficial: (store (y (conv x)), y*)) -> (store x...
CallingConv::ID getCallingConv() const
Get the calling convention of the call.
Definition: CallSite.h:320
virtual bool isCtlzFast() const
Return true if ctlz instruction is fast.
virtual bool isProfitableToCombineMinNumMaxNum(EVT VT) const
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
virtual bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:135
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
unsigned getAllocaAddrSpace() const
Definition: DataLayout.h:269
void * PointerTy
Definition: GenericValue.h:21
bool hasOneUse() const
Return true if there is exactly one use of this node.
Definition: BitVector.h:937
virtual bool decomposeMulByConstant(EVT VT, SDValue C) const
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
Shift and rotation operations.
Definition: ISDOpcodes.h:434
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:205
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
virtual bool isSupportedFixedPointOperation(unsigned Op, EVT VT, unsigned Scale) const
Custom method defined by each target to indicate if an operation which may require a scale is support...
CallLoweringInfo & setVarArg(bool Value=true)
CallLoweringInfo & setChain(SDValue InChain)
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:279
virtual uint8_t getRepRegClassCostFor(MVT VT) const
Return the cost of the &#39;representative&#39; register class for the specified value type.
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:742
virtual bool useLoadStackGuardNode() const
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn&#39;t supported on the target and indicate what to d...
This file contains the simple types necessary to represent the attributes associated with functions a...
SimpleValueType SimpleTy
void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth)
Tells the code generator which bitwidths to bypass.
virtual bool isVectorShiftByScalarCheap(Type *Ty) const
Return true if it&#39;s significantly cheaper to shift a vector by a uniform scalar than by an amount whi...
bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const
Return true if the specified load with extension is legal or custom on this target.
bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const
When splitting a value of the specified type into parts, does the Lo or Hi part come first...
virtual bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT, bool IsSigned) const
Return true if it is more correct/profitable to use strict FP_TO_INT conversion operations - canonica...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const
Use bitwise logic to make pairs of compares more efficient.
virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const
This file implements a class to represent arbitrary precision integral constant values and operations...
virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const
Return true if it&#39;s free to truncate a value of type FromTy to type ToTy.
SmallVector< ISD::InputArg, 32 > Ins
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
virtual bool ShouldShrinkFPConstant(EVT) const
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const
This callback is used to prepare for a volatile or atomic load.
Context object for machine code objects.
Definition: MCContext.h:62
virtual void ReplaceNodeResults(SDNode *, SmallVectorImpl< SDValue > &, SelectionDAG &) const
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
InstrTy * getInstruction() const
Definition: CallSite.h:96
virtual EVT getOptimalMemOpType(uint64_t, unsigned, unsigned, bool, bool, bool, const AttributeList &) const
Returns the target specific optimal type for load and store operations as a result of memset...
virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const
Certain targets have context senstive alignment requirements, where one type has the alignment requir...
virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT) const
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:66
Class to represent function types.
Definition: DerivedTypes.h:102
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
#define UINT64_MAX
Definition: DataTypes.h:83
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:400
static cl::opt< unsigned > MaxLoadsPerMemcmpOptSize("max-loads-per-memcmp-opt-size", cl::Hidden, cl::desc("Set maximum number of loads used in expanded memcmp for -Os/Oz"))
virtual bool supportSwiftError() const
Return true if the target supports swifterror attribute.
virtual bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use *> &Ops) const
Return true if sinking I&#39;s operands to the same basic block as I is profitable, e.g.
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
This contains information for each constraint that we are lowering.
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
bool isVarArg() const
Definition: DerivedTypes.h:122
SmallVector< ISD::OutputArg, 32 > Outs
virtual bool isCheapToSpeculateCtlz() const
Return true if it is cheap to speculate a call to intrinsic ctlz.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
bool isLittleEndian() const
Layout endianness...
Definition: DataLayout.h:232
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:125
CallLoweringInfo & setZExtResult(bool Value=true)
BooleanContent getBooleanContents(EVT Type) const
virtual bool shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout &DL) const
For most targets, an LLVM type must be broken down into multiple smaller types.
An instruction for storing to memory.
Definition: Instructions.h:320
unsigned getPrefFunctionAlignment() const
Return the preferred function alignment.
MVT getRegisterType(LLVMContext &Context, EVT VT) const
Return the type of registers that this ValueType will eventually require.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:995
virtual const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *, const MachineBasicBlock *, unsigned, MCContext &) const
virtual bool isCheapToSpeculateCttz() const
Return true if it is cheap to speculate a call to intrinsic cttz.
X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:323
virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const
Lower an interleaved store to target specific intrinsics.
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
Value * getOperand(unsigned i) const
Definition: User.h:169
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Class to represent pointers.
Definition: DerivedTypes.h:498
This class is used to represent ISD::STORE nodes.
void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx)
static cl::opt< unsigned > MaxLoadsPerMemcmp("max-loads-per-memcmp", cl::Hidden, cl::desc("Set maximum number of loads used in expanded memcmp"))
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool isJumpExpensive() const
Return true if Flow Control is an expensive operation that should be avoided.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:117
virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, unsigned &Cost) const
Return true if the target can combine store(extractelement VectorTy, Idx).
virtual bool alignLoopsWithOptSize() const
Should loops be aligned even when the function is marked OptSize (but not MinSize).
virtual Value * emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const
Perform a store-conditional operation to Addr.
EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
std::vector< AsmOperandInfo > AsmOperandInfoVector
virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT) const
Try to convert math with an overflow comparison into the corresponding DAG node operation.
MVT getSimpleValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the MVT corresponding to this LLVM type. See getValueType.
virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range) const
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumC...
virtual bool getAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value *> &, Type *&) const
CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the add...
unsigned const MachineRegisterInfo * MRI
virtual unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception address on entry to an ...
Machine Value Type.
DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
CallLoweringInfo & setIsPatchPoint(bool Value=true)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
void setJumpBufSize(unsigned Size)
Set the target&#39;s required jmp_buf buffer size (in bytes); default is 200.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type...
Simple binary floating point operators.
Definition: ISDOpcodes.h:287
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
virtual Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const
Perform a masked cmpxchg using a target-specific intrinsic.
virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const
virtual ISD::NodeType getExtendForAtomicOps() const
Returns how the platform&#39;s atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
This is an important base class in LLVM.
Definition: Constant.h:41
virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const
Return true if it is beneficial to convert a load of a constant to just the constant itself...
bool isFloatingPointOperation() const
Definition: Instructions.h:823
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:970
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:231
bool isSlowDivBypassed() const
Returns true if target has indicated at least one type should be bypassed.
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:138
virtual Value * emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type...
virtual unsigned getPrefLoopAlignment(MachineLoop *ML=nullptr) const
Return the preferred loop alignment.
virtual SDValue unwrapAddress(SDValue N) const
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
bool isAcquireOrStronger(AtomicOrdering ao)
virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const
virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const
Return true if an fpext operation input to an Opcode operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.
virtual LoadInst * lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const
On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can b...
virtual unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception typeid on entry to a la...
CombineLevel
Definition: DAGCombine.h:15
LegalizeAction getCondCodeAction(ISD::CondCode CC, MVT VT) const
Return how the condition code should be treated: either it is legal, needs to be expanded to some oth...
virtual bool areJTsAllowed(const Function *Fn) const
Return true if lowering to a jump table is allowed.
void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
Convenience method to set an operation to Promote and specify the type in a single call...
bool CombineTo(SDValue O, SDValue N)
MVT getPointerMemTy(const DataLayout &DL, uint32_t AS=0) const
Return the in-memory pointer type for the given address space, defaults to the pointer type from the ...
bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded, TargetLoweringOpt &TLO) const
virtual bool ExpandInlineAsm(CallInst *) const
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to...
void setPrefFunctionAlignment(unsigned Align)
Set the target&#39;s preferred function alignment.
virtual bool hasPairedLoad(EVT, unsigned &) const
Return true if the target supplies and combines to a paired load two loaded values of type LoadedType...
virtual MVT getFenceOperandTy(const DataLayout &DL) const
Return the type for operands of fence.
virtual bool isDesirableToCombineBuildVectorToShuffleTruncate(ArrayRef< int > ShuffleMask, EVT SrcVT, EVT TruncVT) const
bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const
Return true if the specified indexed load is legal on this target.
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
virtual bool isDesirableToTransformToIntegerOp(unsigned, EVT) const
Return true if it is profitable for dag combiner to transform a floating point op of specified opcode...
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
lazy value info
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension. ...
virtual bool isProfitableToHoist(Instruction *I) const
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:580
bool supportsUnalignedAtomics() const
Whether the target supports unaligned atomic operations.
virtual bool hasVectorBlend() const
Return true if the target has a vector blend instruction.
virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const
Return the type that should be used to zero or sign extend a zeroext/signext integer return value...
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
static unsigned NumFixedArgs
std::vector< ArgListEntry > ArgListTy
Extended Value Type.
Definition: ValueTypes.h:33
virtual bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const
For some targets, an LLVM struct type must be broken down into multiple simple types, but the calling convention specifies that the entire struct must be passed in a block of consecutive registers.
virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual Sched::Preference getSchedulingPreference(SDNode *) const
Some scheduler, e.g.
This structure contains all information t