22 #ifndef LLVM_CODEGEN_TARGETLOWERING_H
23 #define LLVM_CODEGEN_TARGETLOWERING_H
65 class BranchProbability;
70 class FunctionLoweringInfo;
75 class LegacyDivergenceAnalysis;
77 class MachineBasicBlock;
78 class MachineFunction;
80 class MachineJumpTableInfo;
82 class MachineRegisterInfo;
86 class ProfileSummaryInfo;
87 class TargetLibraryInfo;
89 class TargetRegisterClass;
90 class TargetRegisterInfo;
91 class TargetTransformInfo;
112 bool DstAlignCanChange;
128 bool MemcpyStrSrc =
false) {
131 Op.DstAlignCanChange = DstAlignCanChange;
132 Op.DstAlign = DstAlign;
135 Op.ZeroMemset =
false;
136 Op.MemcpyStrSrc = MemcpyStrSrc;
137 Op.SrcAlign = SrcAlign;
145 Op.DstAlignCanChange = DstAlignCanChange;
146 Op.DstAlign = DstAlign;
149 Op.ZeroMemset = IsZeroMemset;
150 Op.MemcpyStrSrc =
false;
154 uint64_t
size()
const {
return Size; }
156 assert(!DstAlignCanChange);
164 return isMemcpy() && !DstAlignCanChange;
376 bool LegalTypes =
true)
const;
420 return HasMultipleConditionRegisters;
456 unsigned DefinedValues)
const {
457 return DefinedValues < 3;
514 return BypassSlowDivWidths;
576 unsigned AddrSpace)
const {
722 unsigned KeptBits)
const {
736 unsigned OldShiftOpcode,
unsigned NewShiftOpcode,
778 unsigned &Cost)
const {
820 return BooleanVectorContents;
821 return isFloat ? BooleanFloatContents : BooleanContents;
830 return SchedPreferenceInfo;
845 assert(RC &&
"This value type is not natively supported!");
853 const Value *)
const {
872 return RepRegClassCostForVT[VT.
SimpleTy];
903 return ValueTypeActions[VT.
SimpleTy];
907 ValueTypeActions[VT.
SimpleTy] = Action;
912 return ValueTypeActions;
920 return getTypeConversion(
Context, VT).first;
933 return getTypeConversion(
Context, VT).second;
965 unsigned &NumIntermediates,
966 MVT &RegisterVT)
const;
973 unsigned &NumIntermediates,
MVT &RegisterVT)
const {
1008 bool ForCodeSize =
false)
const {
1049 unsigned Scale)
const {
1058 unsigned Scale)
const {
1060 if (Action !=
Legal)
1081 return Supported ? Action :
Expand;
1090 #define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
1091 case ISD::STRICT_##DAGN: EqOpc = ISD::DAGN; break;
1092 #define CMP_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
1093 case ISD::STRICT_##DAGN: EqOpc = ISD::SETCC; break;
1094 #include "llvm/IR/ConstrainedOps.def"
1105 bool LegalOnly =
false)
const {
1119 bool LegalOnly =
false)
const {
1133 bool LegalOnly =
false)
const {
1162 uint64_t BW =
DL.getIndexSizeInBits(0u);
1163 uint64_t Range = (
High - Low).getLimitedValue(
UINT64_MAX - 1) + 1;
1196 return (NumDests == 1 && NumCmps >= 3) || (NumDests == 2 && NumCmps >= 5) ||
1197 (NumDests == 3 && NumCmps >= 6);
1223 unsigned Shift = 4 * ExtType;
1247 "Table isn't big enough!");
1248 return TruncStoreActions[ValI][MemI];
1269 return getIndexedModeAction(IdxMode, VT, IMAB_Load);
1283 return getIndexedModeAction(IdxMode, VT, IMAB_Store);
1297 return getIndexedModeAction(IdxMode, VT, IMAB_MaskedLoad);
1311 return getIndexedModeAction(IdxMode, VT, IMAB_MaskedStore);
1336 "Table isn't big enough!");
1341 assert(Action !=
Promote &&
"Can't promote condition code!");
1361 "This operation isn't promoted!");
1364 std::map<std::pair<unsigned, MVT::SimpleValueType>,
1366 PromoteToType.find(std::make_pair(
Op, VT.
SimpleTy));
1367 if (PTTI != PromoteToType.end())
return PTTI->second;
1370 "Cannot autopromote this type, add it with AddPromotedToType.");
1376 "Didn't find type to promote to!");
1387 bool AllowUnknown =
false)
const {
1389 if (
auto *PTy = dyn_cast<PointerType>(Ty))
1392 if (
auto *VTy = dyn_cast<VectorType>(Ty)) {
1393 Type *EltTy = VTy->getElementType();
1395 if (
auto *PTy = dyn_cast<PointerType>(EltTy)) {
1400 VTy->getElementCount());
1407 bool AllowUnknown =
false)
const {
1411 else if (
VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1412 Type *Elm = VTy->getElementType();
1413 if (
PointerType *PT = dyn_cast<PointerType>(Elm)) {
1418 VTy->getElementCount());
1427 bool AllowUnknown =
false)
const {
1439 return RegisterTypeForVT[VT.
SimpleTy];
1452 unsigned NumIntermediates;
1454 NumIntermediates, RegisterVT);
1480 unsigned NumIntermediates;
1486 return (
BitWidth + RegWidth - 1) / RegWidth;
1512 return DL.getABITypeAlign(ArgTy);
1543 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
1616 bool * =
nullptr)
const {
1624 bool * =
nullptr)
const {
1634 unsigned AddrSpace = 0,
Align Alignment =
Align(1),
1636 bool *Fast =
nullptr)
const;
1645 bool *Fast =
nullptr)
const;
1653 unsigned AddrSpace = 0,
Align Alignment =
Align(1),
1655 bool *Fast =
nullptr)
const;
1663 bool *Fast =
nullptr)
const;
1668 bool *Fast =
nullptr)
const;
1711 return StackPointerRegisterToSaveRestore;
1734 return MinStackArgumentAlignment;
1745 return PrefLoopAlignment;
1809 unsigned & )
const {
1835 return MaxAtomicSizeInBitsSupported;
1881 llvm_unreachable(
"Masked atomicrmw expansion unimplemented on this target");
1929 return Builder.CreateFence(Ord);
1938 return Builder.CreateFence(Ord);
2067 bool IsSigned)
const {
2079 BooleanContents = Ty;
2080 BooleanFloatContents = Ty;
2086 BooleanContents = IntTy;
2087 BooleanFloatContents = FloatTy;
2093 BooleanVectorContents = Ty;
2098 SchedPreferenceInfo = Pref;
2111 StackPointerRegisterToSaveRestore = R;
2120 HasMultipleConditionRegisters = hasManyRegs;
2128 HasExtractBitsInsn = hasExtractInsn;
2138 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
2151 virtual std::pair<const TargetRegisterClass *, uint8_t>
2164 OpActions[(unsigned)VT.
SimpleTy][
Op] = Action;
2172 MemVT.
isValid() &&
"Table isn't big enough!");
2173 assert((
unsigned)Action < 0x10 &&
"too many bits for bitfield array");
2174 unsigned Shift = 4 * ExtType;
2193 setIndexedModeAction(IdxMode, VT, IMAB_Load, Action);
2202 setIndexedModeAction(IdxMode, VT, IMAB_Store, Action);
2212 setIndexedModeAction(IdxMode, VT, IMAB_MaskedLoad, Action);
2222 setIndexedModeAction(IdxMode, VT, IMAB_MaskedStore, Action);
2230 "Table isn't big enough!");
2231 assert((
unsigned)Action < 0x10 &&
"too many bits for bitfield array");
2260 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
2265 MinFunctionAlignment = Alignment;
2271 PrefFunctionAlignment = Alignment;
2281 MinStackArgumentAlignment = Alignment;
2289 MaxAtomicSizeInBitsSupported = SizeInBits;
2294 MinCmpXchgSizeInBits = SizeInBits;
2299 SupportsUnalignedAtomics = UnalignedSupported;
2344 Type *Ty,
unsigned AddrSpace,
2355 Type *Ty,
unsigned AS = 0)
const {
2406 return (
From->isIntegerTy() ||
From->isFloatingPointTy()) &&
2442 default:
return false;
2503 switch (
I->getOpcode()) {
2504 case Instruction::FPExt:
2509 case Instruction::ZExt:
2510 if (
isZExtFree(
I->getOperand(0)->getType(),
I->getType()))
2513 case Instruction::SExt:
2540 if (isa<ZExtInst>(
Ext))
2543 assert(isa<SExtInst>(
Ext) &&
"Unexpected ext type!");
2627 unsigned Factor)
const {
2638 unsigned Factor)
const {
2654 "invalid fpext types");
2662 EVT DestVT,
EVT SrcVT)
const {
2664 "invalid fpext types");
2710 "unexpected node in FMAD forming combine");
2743 unsigned Index)
const {
2766 bool MathUsed)
const {
2809 LibcallRoutineNames[Call] =
Name;
2814 return LibcallRoutineNames[Call];
2820 CmpLibcallCCs[Call] = CC;
2826 return CmpLibcallCCs[Call];
2831 LibcallCallingConvs[Call] = CC;
2836 return LibcallCallingConvs[Call];
2860 bool HasMultipleConditionRegisters;
2866 bool HasExtractBitsInsn;
2877 bool JumpIsExpensive;
2896 Align MinStackArgumentAlignment;
2900 Align MinFunctionAlignment;
2904 Align PrefFunctionAlignment;
2907 Align PrefLoopAlignment;
2911 unsigned MaxAtomicSizeInBitsSupported;
2915 unsigned MinCmpXchgSizeInBits;
2918 bool SupportsUnalignedAtomics;
2922 Register StackPointerRegisterToSaveRestore;
2983 ValueTypeActionImpl ValueTypeActions;
3004 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL + 1];
3014 void InitLibcalls(
const Triple &TT);
3018 enum IndexedModeActionsBits {
3021 IMAB_MaskedStore = 8,
3022 IMAB_MaskedLoad = 12
3025 void setIndexedModeAction(
unsigned IdxMode, MVT VT,
unsigned Shift,
3028 (
unsigned)Action < 0xf &&
"Table isn't big enough!");
3029 unsigned Ty = (unsigned)VT.SimpleTy;
3030 IndexedModeActions[Ty][IdxMode] &= ~(0xf <<
Shift);
3031 IndexedModeActions[Ty][IdxMode] |= ((
uint16_t)Action) <<
Shift;
3035 unsigned Shift)
const {
3037 "Table isn't big enough!");
3038 unsigned Ty = (unsigned)VT.SimpleTy;
3231 bool IsSignaling =
false)
const;
3237 MakeLibCallOptions CallOptions,
3245 const uint32_t *CallerPreservedMask,
3282 const MemOp &
Op,
unsigned DstAS,
unsigned SrcAS,
3290 const APInt &DemandedElts,
3291 TargetLoweringOpt &TLO)
const;
3295 TargetLoweringOpt &TLO)
const;
3302 const APInt &DemandedElts,
3311 TargetLoweringOpt &TLO)
const;
3328 TargetLoweringOpt &TLO,
unsigned Depth = 0,
3329 bool AssumeSingleUse =
false)
const;
3334 KnownBits &Known, TargetLoweringOpt &TLO,
3336 bool AssumeSingleUse =
false)
const;
3341 DAGCombinerInfo &DCI)
const;
3347 const APInt &DemandedElts,
3349 unsigned Depth)
const;
3355 unsigned Depth = 0)
const;
3360 const APInt &DemandedElts,
3362 unsigned Depth = 0)
const;
3380 TargetLoweringOpt &TLO,
unsigned Depth = 0,
3381 bool AssumeSingleUse =
false)
const;
3387 DAGCombinerInfo &DCI)
const;
3395 const APInt &DemandedElts,
3397 unsigned Depth = 0)
const;
3405 const APInt &DemandedElts,
3407 unsigned Depth = 0)
const;
3416 unsigned Depth = 0)
const;
3430 const APInt &DemandedElts,
3432 unsigned Depth = 0)
const;
3440 const APInt &DemandedElts,
3442 unsigned Depth = 0)
const;
3451 APInt &KnownZero, TargetLoweringOpt &TLO,
unsigned Depth = 0)
const;
3460 const APInt &DemandedElts,
3462 TargetLoweringOpt &TLO,
3463 unsigned Depth = 0)
const;
3490 unsigned Depth = 0)
const;
3532 bool foldBooleans, DAGCombinerInfo &DCI,
3533 const SDLoc &dl)
const;
3628 bool LegalOps,
bool OptForSize,
3630 unsigned Depth = 0)
const;
3635 bool LegalOps,
bool OptForSize,
3636 unsigned Depth = 0)
const {
3651 bool OptForSize,
unsigned Depth = 0)
const {
3665 unsigned NumParts,
MVT PartVT,
3673 const SDValue *Parts,
unsigned NumParts,
3772 IsInReg = Call.hasRetAttr(Attribute::InReg);
3774 Call.doesNotReturn() ||
3775 (!isa<InvokeInst>(Call) && isa<UnreachableInst>(Call.getNextNode()));
3778 RetSExt = Call.hasRetAttr(Attribute::SExt);
3779 RetZExt = Call.hasRetAttr(Attribute::ZExt);
3780 NoMerge = Call.hasFnAttr(Attribute::NoMerge);
3890 bool Value =
true) {
3902 std::pair<SDValue, SDValue>
LowerCallTo(CallLoweringInfo &CLI)
const;
3961 return "__clear_cache";
3981 return VT.
bitsLT(MinVT) ? MinVT : VT;
3989 bool isVarArg)
const {
3999 return DL.isLittleEndian();
4025 assert(
SI.isAtomic() &&
"violated precondition");
4200 virtual std::pair<unsigned, const TargetRegisterClass *>
4205 if (ConstraintCode ==
"m")
4218 std::vector<SDValue> &Ops,
4224 const AsmOperandInfo &OpInfo,
4270 int Enabled,
int &RefinementSteps,
4271 bool &UseOneConstNR,
bool Reciprocal)
const {
4286 int Enabled,
int &RefinementSteps)
const {
4412 bool IsNegative =
false)
const;
4455 bool IsCompressedMemory)
const;