#include "llvm/CodeGen/TargetRegisterInfo.h"

Public Types
using	iterator = const MCPhysReg *

using	const_iterator = const MCPhysReg *

Public Member Functions
unsigned	getID () const
	Return the register class ID number.

iterator	begin () const
	begin/end - Return all of the registers in this class.

iterator	end () const

unsigned	getNumRegs () const
	Return the number of registers in this class.

ArrayRef< MCPhysReg >	getRegisters () const

MCRegister	getRegister (unsigned i) const
	Return the specified register in the class.

bool	contains (Register Reg) const
	Return true if the specified register is included in this register class.

bool	contains (Register Reg1, Register Reg2) const
	Return true if both registers are in this class.

int	getCopyCost () const
	Return the cost of copying a value between two registers in this class.

bool	isAllocatable () const
	Return true if this register class may be used to create virtual registers.

bool	isBaseClass () const
	Return true if this register class has a defined BaseClassOrder.

bool	hasSubClass (const TargetRegisterClass *RC) const
	Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.

bool	hasSubClassEq (const TargetRegisterClass *RC) const
	Returns true if RC is a sub-class of or equal to this class.

bool	hasSuperClass (const TargetRegisterClass *RC) const
	Return true if the specified TargetRegisterClass is a proper super-class of this TargetRegisterClass.

bool	hasSuperClassEq (const TargetRegisterClass *RC) const
	Returns true if RC is a super-class of or equal to this class.

const uint32_t *	getSubClassMask () const
	Returns a bit vector of subclasses, including this one.

const uint16_t *	getSuperRegIndices () const
	Returns a 0-terminated list of sub-register indices that project some super-register class into this register class.

ArrayRef< unsigned >	superclasses () const
	Returns a list of super-classes.

bool	isASubClass () const
	Return true if this TargetRegisterClass is a subset class of at least one other TargetRegisterClass.

ArrayRef< MCPhysReg >	getRawAllocationOrder (const MachineFunction &MF) const
	Returns the preferred order for allocating registers from this register class in MF.

LaneBitmask	getLaneMask () const
	Returns the combination of all lane masks of register in this class.

Public Attributes
const MCRegisterClass *	MC

const uint32_t *	SubClassMask

const uint16_t *	SuperRegIndices

const LaneBitmask	LaneMask

const uint8_t	AllocationPriority
	Classes with a higher priority value are assigned first by register allocators using a greedy heuristic.

const bool	GlobalPriority

const uint8_t	TSFlags
	Configurable target specific flags.

const bool	HasDisjunctSubRegs
	Whether the class supports two (or more) disjunct subregister indices.

const bool	CoveredBySubRegs
	Whether a combination of subregisters can cover every register in the class.

const unsigned *	SuperClasses

const uint16_t	SuperClassesSize

ArrayRef< MCPhysReg >(*	OrderFunc )(const MachineFunction &)

Detailed Description

Definition at line 44 of file TargetRegisterInfo.h.

Member Typedef Documentation

◆ const_iterator

using llvm::TargetRegisterClass::const_iterator = const MCPhysReg *

Definition at line 47 of file TargetRegisterInfo.h.

◆ iterator

using llvm::TargetRegisterClass::iterator = const MCPhysReg *

Definition at line 46 of file TargetRegisterInfo.h.

Member Function Documentation

◆ begin()

iterator llvm::TargetRegisterClass::begin ( ) const

inline

begin/end - Return all of the registers in this class.

Definition at line 77 of file TargetRegisterInfo.h.

References llvm::MCRegisterClass::begin(), and MC.

Referenced by allocateSGPR32InputImpl(), getRegisters(), and getRegistersForValue().

◆ contains() [1/2]

bool llvm::TargetRegisterClass::contains ( Register Reg ) const

inline

Return true if the specified register is included in this register class.

This does not include virtual registers.

FIXME: Historically this function has returned false when given vregs but it should probably only receive physical registers

Definition at line 94 of file TargetRegisterInfo.h.

References llvm::MCRegisterClass::contains(), MC, and Reg.

Referenced by addHints(), llvm::MachineFunction::addLiveIn(), canFoldCopy(), llvm::PPCInstrInfo::ClobbersPredicate(), llvm::VirtRegAuxInfo::copyHint(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), estimateRSStackSizeLimit(), llvm::SIInstrInfo::foldImmediate(), llvm::R600InstrInfo::getIndirectIndexBegin(), llvm::M68kRegisterInfo::getMatchingMegaReg(), llvm::M68kRegisterInfo::getMaximalPhysRegClass(), llvm::AArch64RegisterInfo::getRegAllocationHints(), llvm::PPCRegisterInfo::getRegAllocationHints(), llvm::X86RegisterInfo::getRegAllocationHints(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::SIInstrInfo::isLegalRegOperand(), llvm::rewriteT2FrameIndex(), llvm::SystemZRegisterInfo::shouldCoalesce(), UpdateOperandRegClass(), and llvm::SIInstrInfo::verifyInstruction().

◆ contains() [2/2]

bool llvm::TargetRegisterClass::contains	(	Register	Reg1,
		Register	Reg2
	)		const

inline

Return true if both registers are in this class.

FIXME: Historically this function has returned false when given a vregs but it should probably only receive physical registers

Definition at line 103 of file TargetRegisterInfo.h.

References llvm::Register::asMCReg(), llvm::MCRegisterClass::contains(), llvm::Register::isPhysical(), and MC.

◆ end()

iterator llvm::TargetRegisterClass::end ( ) const

inline

Definition at line 78 of file TargetRegisterInfo.h.

References llvm::MCRegisterClass::end(), and MC.

Referenced by getRegistersForValue().

◆ getCopyCost()

int llvm::TargetRegisterClass::getCopyCost ( ) const

inline

Return the cost of copying a value between two registers in this class.

A negative number means the register class is very expensive to copy e.g. status flag register classes.

Definition at line 114 of file TargetRegisterInfo.h.

References llvm::MCRegisterClass::getCopyCost(), and MC.

Referenced by CheckForPhysRegDependency(), and llvm::SITargetLowering::checkForPhysRegDependency().

◆ getID()

unsigned llvm::TargetRegisterClass::getID ( ) const

inline

Return the register class ID number.

Definition at line 73 of file TargetRegisterInfo.h.

References llvm::MCRegisterClass::getID(), and MC.

Referenced by llvm::RegsForValue::AddInlineAsmOperands(), llvm::HexagonEvaluator::composeWithSubRegIndex(), llvm::RegisterBank::covers(), llvm::HexagonFrameLowering::determineCalleeSaves(), llvm::SITargetLowering::finalizeLowering(), llvm::HexagonRegisterInfo::getCallerSavedRegs(), llvm::WebAssembly::getCopyOpcodeForRegClass(), GetCostForDef(), llvm::HexagonRegisterInfo::getHexagonSubRegIndex(), llvm::ARMBaseRegisterInfo::getLargestLegalSuperClass(), llvm::X86RegisterInfo::getRegAllocationHints(), llvm::AArch64RegisterBankInfo::getRegBankFromRegClass(), llvm::PPCRegisterBankInfo::getRegBankFromRegClass(), llvm::SPIRVRegisterBankInfo::getRegBankFromRegClass(), llvm::AMDGPU::getRegBitWidth(), llvm::TargetRegisterInfo::getRegClassInfo(), llvm::AArch64RegisterInfo::getRegPressureLimit(), llvm::SIRegisterInfo::getRegPressureLimit(), llvm::ARMBaseRegisterInfo::getRegPressureLimit(), llvm::MipsRegisterInfo::getRegPressureLimit(), llvm::PPCRegisterInfo::getRegPressureLimit(), llvm::X86RegisterInfo::getRegPressureLimit(), hasSubClassEq(), INITIALIZE_PASS(), llvm::X86RegisterInfo::isTileRegisterClass(), IsWritingToVCCR(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::InlineAsmLowering::lowerInlineAsm(), llvm::HexagonEvaluator::mask(), llvm::ResourcePriorityQueue::rawRegPressureDelta(), llvm::ResourcePriorityQueue::scheduledNode(), llvm::AMDGPUDAGToDAGISel::Select(), llvm::AArch64RegisterInfo::shouldCoalesce(), and llvm::HexagonRegisterInfo::shouldCoalesce().

◆ getLaneMask()

LaneBitmask llvm::TargetRegisterClass::getLaneMask ( ) const

inline

Returns the combination of all lane masks of register in this class.

The lane masks of the registers are the combination of all lane masks of their subregisters. Returns 1 if there are no subregisters.

Definition at line 208 of file TargetRegisterInfo.h.

References LaneMask.

Referenced by llvm::ScheduleDAGInstrs::getLaneMaskForMO(), and llvm::MachineRegisterInfo::getMaxLaneMaskForVReg().

◆ getNumRegs()

unsigned llvm::TargetRegisterClass::getNumRegs ( ) const

inline

Return the number of registers in this class.

Definition at line 81 of file TargetRegisterInfo.h.

References llvm::MCRegisterClass::getNumRegs(), and MC.

Referenced by llvm::RegisterClassInfo::computePSetLimit(), constrainRegClass(), llvm::R600InstrInfo::getIndirectIndexBegin(), llvm::M68kRegisterInfo::getMaximalPhysRegClass(), llvm::M68kRegisterInfo::getRegisterOrder(), getRegisters(), llvm::ExecutionDomainFix::runOnMachineFunction(), and llvm::SystemZRegisterInfo::shouldCoalesce().

◆ getRawAllocationOrder()

ArrayRef< MCPhysReg > llvm::TargetRegisterClass::getRawAllocationOrder ( const MachineFunction & MF ) const

inline

Returns the preferred order for allocating registers from this register class in MF.

The raw order comes directly from the .td file and may include reserved registers that are not allocatable. Register allocators should also make sure to allocate callee-saved registers only after all the volatiles are used. The RegisterClassInfo class provides filtered allocation orders with callee-saved registers moved to the end.

The MachineFunction argument can be used to tune the allocatable registers based on the characteristics of the function, subtarget, or other criteria.

By default, this method returns all registers in the class.

Definition at line 201 of file TargetRegisterInfo.h.

References getRegisters(), and OrderFunc.

Referenced by getAllocatableSetForRC(), and llvm::RegScavenger::scavengeRegisterBackwards().

◆ getRegister()

MCRegister llvm::TargetRegisterClass::getRegister ( unsigned i ) const

inline

Return the specified register in the class.

Definition at line 88 of file TargetRegisterInfo.h.

References llvm::MCRegisterClass::getRegister(), and MC.

Referenced by llvm::R600InstrInfo::getIndirectIndexBegin(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), llvm::M68kRegisterInfo::getRegisterOrder(), and llvm::tryFoldSPUpdateIntoPushPop().

◆ getRegisters()

ArrayRef< MCPhysReg > llvm::TargetRegisterClass::getRegisters ( ) const

inline

Definition at line 83 of file TargetRegisterInfo.h.

References begin(), and getNumRegs().

Referenced by llvm::SIMachineFunctionInfo::allocateVGPRSpillToAGPR(), llvm::RegAllocBase::getErrorAssignment(), llvm::SIRegisterInfo::getNumUsedPhysRegs(), and getRawAllocationOrder().

◆ getSubClassMask()

const uint32_t * llvm::TargetRegisterClass::getSubClassMask ( ) const

inline

Returns a bit vector of subclasses, including this one.

The vector is indexed by class IDs.

To use it, consider the returned array as a chunk of memory that contains an array of bits of size NumRegClasses. Each 32-bit chunk contains a bitset of the ID of the subclasses in big-endian style. I.e., the representation of the memory from left to right at the bit level looks like: [31 30 ... 1 0] [ 63 62 ... 33 32] ... [ XXX NumRegClasses NumRegClasses - 1 ... ] Where the number represents the class ID and XXX bits that should be ignored.

See the implementation of hasSubClassEq for an example of how it can be used.

Definition at line 162 of file TargetRegisterInfo.h.

References SubClassMask.

Referenced by llvm::TargetRegisterInfo::getAllocatableClass().