29#include "llvm/Config/llvm-config.h"
38#define DEBUG_TYPE "pre-RA-sched"
40STATISTIC(LoadsClustered,
"Number of loads clustered together");
47 cl::desc(
"Roughly estimate the number of cycles that 'long latency' "
48 "instructions take for targets with no itinerary"));
71 const SUnit *Addr =
nullptr;
77 "SUnits std::vector reallocated on the fly!");
82 (
N->isMachineOpcode() &&
83 N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF))
126 }
else if (Def->isMachineOpcode()) {
128 if (ResNo >=
II.getNumDefs() &&
II.hasImplicitDefOfPhysReg(
Reg))
134 TRI->getMinimalPhysRegClass(
Reg, Def->getSimpleValueType(ResNo));
143 if (ExtraOper.getNode())
144 Ops.push_back(ExtraOper);
165 if (GlueDestNode ==
N)
return false;
169 N->getOperand(
N->getNumOperands()-1).getValueType() == MVT::Glue) {
173 if (
N->getValueType(
N->getNumValues() - 1) == MVT::Glue)
return false;
187 assert((
N->getValueType(
N->getNumValues() - 1) == MVT::Glue &&
188 !
N->hasAnyUseOfValue(
N->getNumValues() - 1)) &&
189 "expected an unused glue value");
192 ArrayRef(
N->value_begin(),
N->getNumValues() - 1));
200void ScheduleDAGSDNodes::ClusterNeighboringLoads(
SDNode *Node) {
203 if (
Node->getOperand(
NumOps-1).getValueType() == MVT::Other)
211 auto hasTiedInput = [
this](
const SDNode *
N) {
212 const MCInstrDesc &MCID =
TII->get(
N->getMachineOpcode());
223 SmallPtrSet<SDNode*, 16> Visited;
225 DenseMap<long long, SDNode*> O2SMap;
229 if (hasTiedInput(
Base))
234 unsigned UseCount = 0;
236 I !=
E && UseCount < 100; ++
I, ++UseCount) {
237 if (
I.getUse().getResNo() != Chain.
getResNo())
241 if (User == Node || !Visited.
insert(User).second)
243 int64_t Offset1, Offset2;
244 if (!
TII->areLoadsFromSameBasePtr(
Base, User, Offset1, Offset2) ||
245 Offset1 == Offset2 ||
246 hasTiedInput(User)) {
251 if (O2SMap.
insert(std::make_pair(Offset1,
Base)).second)
253 O2SMap.
insert(std::make_pair(Offset2, User));
255 if (Offset2 < Offset1)
270 unsigned NumLoads = 0;
272 SDNode *BaseLoad = O2SMap[BaseOff];
274 for (
unsigned i = 1, e =
Offsets.size(); i != e; ++i) {
277 if (!
TII->shouldScheduleLoadsNear(BaseLoad, Load, BaseOff,
Offset,NumLoads))
288 SDNode *Lead = Loads[0];
292 for (
unsigned I = 1,
E = Loads.
size();
I !=
E; ++
I) {
293 bool OutGlue =
I <
E - 1;
294 SDNode *
Load = Loads[
I];
304 else if (!OutGlue && InGlue.
getNode())
311void ScheduleDAGSDNodes::ClusterNodes() {
312 for (SDNode &NI :
DAG->allnodes()) {
314 if (!Node || !
Node->isMachineOpcode())
317 unsigned Opc =
Node->getMachineOpcode();
318 const MCInstrDesc &MCID =
TII->get(
Opc);
321 ClusterNeighboringLoads(Node);
325void ScheduleDAGSDNodes::BuildSchedUnits() {
329 unsigned NumNodes = 0;
330 for (SDNode &NI :
DAG->allnodes()) {
340 SUnits.reserve(NumNodes * 2);
344 SmallPtrSet<SDNode*, 32> Visited;
346 Visited.
insert(
DAG->getRoot().getNode());
349 while (!Worklist.
empty()) {
354 if (Visited.
insert(
Op.getNode()).second)
371 while (
N->getNumOperands() &&
372 N->getOperand(
N->getNumOperands()-1).getValueType() == MVT::Glue) {
373 N =
N->getOperand(
N->getNumOperands()-1).getNode();
374 assert(
N->getNodeId() == -1 &&
"Node already inserted!");
376 if (
N->isMachineOpcode() &&
TII->get(
N->getMachineOpcode()).isCall())
382 while (
N->getValueType(
N->getNumValues()-1) == MVT::Glue) {
386 bool HasGlueUse =
false;
387 for (SDNode *U :
N->users())
388 if (GlueVal.isOperandOf(U)) {
390 assert(
N->getNodeId() == -1 &&
"Node already inserted!");
393 if (
N->isMachineOpcode() &&
TII->get(
N->getMachineOpcode()).isCall())
397 if (!HasGlueUse)
break;
413 assert(
N->getNodeId() == -1 &&
"Node already inserted!");
424 while (!CallSUnits.
empty()) {
426 for (
const SDNode *SUNode = SU->
getNode(); SUNode;
430 SDNode *SrcN = SUNode->getOperand(2).getNode();
438void ScheduleDAGSDNodes::AddSchedEdges() {
439 const TargetSubtargetInfo &
ST =
MF.getSubtarget();
445 for (SUnit &SU :
SUnits) {
446 SDNode *MainNode = SU.
getNode();
450 const MCInstrDesc &MCID =
TII->get(
Opc);
463 if (
N->isMachineOpcode() &&
464 !
TII->get(
N->getMachineOpcode()).implicit_defs().empty()) {
467 while (NumUsed != 0 && !
N->hasAnyUseOfValue(NumUsed - 1))
469 if (NumUsed >
TII->get(
N->getMachineOpcode()).getNumDefs())
473 for (
unsigned i = 0, e =
N->getNumOperands(); i != e; ++i) {
474 SDNode *OpN =
N->getOperand(i).getNode();
475 unsigned DefIdx =
N->getOperand(i).getResNo();
478 assert(OpSU &&
"Node has no SUnit!");
482 EVT OpVT =
N->getOperand(i).getValueType();
483 assert(OpVT != MVT::Glue &&
"Glued nodes should be in same sunit!");
484 bool isChain = OpVT == MVT::Other;
490 assert((!PhysReg || !isChain) &&
"Chain dependence via physreg data?");
497 PhysReg = MCRegister();
500 unsigned OpLatency = isChain ? 1 : OpSU->
Latency;
506 : SDep(OpSU, SDep::
Data, PhysReg);
508 if (!isChain && !UnitLatencies) {
510 ST.adjustSchedDependency(OpSU, DefIdx, &SU, i, Dep,
nullptr);
522 --OpSU->NumRegDefsLeft;
543void ScheduleDAGSDNodes::RegDefIter::InitNodeNumDefs() {
548 if (!
Node->isMachineOpcode()) {
555 unsigned POpc =
Node->getMachineOpcode();
556 if (POpc == TargetOpcode::IMPLICIT_DEF) {
561 if (POpc == TargetOpcode::PATCHPOINT &&
562 Node->getValueType(0) == MVT::Other) {
569 unsigned NRegDefs = SchedDAG->TII->get(Node->getMachineOpcode()).getNumDefs();
572 NodeNumDefs = std::min(Node->getNumValues(), NRegDefs);
579 : SchedDAG(SD), Node(SU->
getNode()) {
587 for (;DefIdx < NodeNumDefs; ++DefIdx) {
588 if (!Node->hasAnyUseOfValue(DefIdx))
590 ValueType = Node->getSimpleValueType(DefIdx);
594 Node = Node->getGluedNode();
628 if (
N &&
N->isMachineOpcode() &&
629 TII->isHighLatencyDef(
N->getMachineOpcode()))
640 if (
N->isMachineOpcode())
653 unsigned DefIdx =
Use->getOperand(
OpIdx).getResNo();
654 if (
Use->isMachineOpcode())
656 OpIdx +=
TII->get(
Use->getMachineOpcode()).getNumDefs();
657 std::optional<unsigned>
Latency =
673#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
678 dbgs() <<
"PHYS REG COPY\n";
687 while (!GluedNodes.
empty()) {
697#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
698 if (
EntrySU.getNode() !=
nullptr)
702 if (
ExitSU.getNode() !=
nullptr)
707#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
713 dbgs() <<
"**** NOOP ****\n";
726 "The number of nodes scheduled doesn't match the expected number!");
735 if (!
N->getHasDebugValue())
740 auto HasUnknownVReg = [&VRBaseMap](
SDDbgValue *DV) {
743 VRBaseMap.
count({L.getSDNode(), L.getResNo()}) == 0)
756 unsigned DVOrder = DV->getOrder();
757 if (Order != 0 && DVOrder != Order)
764 if (!DV->isInvalidated() && HasUnknownVReg(DV))
769 Orders.push_back({DVOrder, DbgMI});
782 unsigned Order =
N->getIROrder();
783 if (!Order || Seen.
count(Order)) {
796 Orders.push_back({Order, NewInsn});
804void ScheduleDAGSDNodes::
805EmitPhysRegCopy(SUnit *SU, SmallDenseMap<SUnit *, Register, 16> &VRBaseMap,
807 for (
const SDep &Pred : SU->
Preds) {
814 assert(VRI != VRBaseMap.
end() &&
"Node emitted out of order - late");
817 for (
const SDep &Succ : SU->
Succs) {
831 bool isNew = VRBaseMap.
insert(std::make_pair(SU, VRBase)).second;
833 assert(isNew &&
"Node emitted out of order - early");
852 bool HasDbg =
DAG->hasDebugValues();
857 [&](
SDNode *
Node,
bool IsClone,
bool IsCloned,
861 if (
I ==
BB->begin())
864 return std::prev(
Emitter.getInsertPos());
868 Emitter.EmitNode(
Node, IsClone, IsCloned, VRBaseMap);
876 if (Before ==
BB->end()) {
882 MI = &*std::next(Before);
885 if (
MI->isCandidateForAdditionalCallInfo()) {
886 if (
DAG->getTarget().Options.EmitCallSiteInfo ||
887 DAG->getTarget().Options.EmitCallGraphSection)
888 MF.addCallSiteInfo(
MI,
DAG->getCallSiteInfo(
Node));
890 if (
auto CalledGlobal =
DAG->getCalledGlobal(
Node))
891 if (CalledGlobal->Callee)
892 MF.addCalledGlobal(
MI, *CalledGlobal);
895 if (
DAG->getNoMergeSiteInfo(
Node)) {
900 MI->setPCSections(
MF, MD);
905 End = std::next(After);
907 It->setMMRAMetadata(
MF, MMRA);
917 for (; PDI != PDE; ++PDI) {
920 BB->insert(InsertPos, DbgMI);
923 (*PDI)->clearIsEmitted();
931 TII->insertNoop(*
Emitter.getBlock(), InsertPos);
939 EmitPhysRegCopy(SU, CopyVRBaseMap, InsertPos);
946 while (!GluedNodes.
empty()) {
954 if (NewInsn && NewInsn->isCall())
955 NewInsn->setHeapAllocMarker(
MF, MD);
967 if (NewInsn && NewInsn->isCall())
968 NewInsn->setHeapAllocMarker(
MF, MD);
981 std::stable_sort(
DAG->DbgBegin(),
DAG->DbgEnd(),
983 return LHS->getOrder() < RHS->getOrder();
989 unsigned LastOrder = 0;
990 for (
unsigned i = 0, e = Orders.
size(); i != e && DI != DE; ++i) {
991 unsigned Order = Orders[i].first;
995 for (; DI != DE; ++DI) {
996 if ((*DI)->getOrder() < LastOrder || (*DI)->getOrder() >= Order)
998 if ((*DI)->isEmitted())
1005 BB->insert(BBBegin, DbgMI);
1010 MI->getParent()->insert(Pos, DbgMI);
1019 for (; DI != DE; ++DI) {
1020 if ((*DI)->isEmitted())
1022 assert((*DI)->getOrder() >= LastOrder &&
1023 "emitting DBG_VALUE out of order");
1036 for (
const auto &InstrOrder : Orders) {
1037 unsigned Order = InstrOrder.first;
1043 for (; DLI != DLE &&
1044 (*DLI)->getOrder() >= LastOrder && (*DLI)->getOrder() < Order;
1050 BB->insert(BBBegin, DbgMI);
1055 MI->getParent()->insert(Pos, DbgMI);
1066 InsertPos =
Emitter.getInsertPos();
1072 if (FirstTerm != InsertBB->
end()) {
1073 assert(!FirstTerm->isDebugValue() &&
1074 "first terminator cannot be a debug value");
1078 if (&
MI == InsertPos)
1081 if (!
MI.isDebugValue())
1086 MI.getOperand(0).ChangeToRegister(0,
false);
1087 MI.moveBefore(&*FirstTerm);
1095 return "sunit-dag." +
BB->getFullName();
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
static msgpack::DocNode getNode(msgpack::DocNode DN, msgpack::Type Type, MCValue Val)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
dxil DXContainer Global Emitter
This file defines the DenseMap class.
const HexagonInstrInfo * TII
const size_t AbstractManglingParser< Derived, Alloc >::NumOps
const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]
Register const TargetRegisterInfo * TRI
Promote Memory to Register
This file provides utility for Memory Model Relaxation Annotations (MMRAs).
MachineInstr unsigned OpIdx
uint64_t IntrinsicInst * II
static void ProcessSourceNode(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter, InstrEmitter::VRBaseMapType &VRBaseMap, SmallVectorImpl< std::pair< unsigned, MachineInstr * > > &Orders, SmallSet< Register, 8 > &Seen, MachineInstr *NewInsn)
static bool AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG)
static void RemoveUnusedGlue(SDNode *N, SelectionDAG *DAG)
static cl::opt< int > HighLatencyCycles("sched-high-latency-cycles", cl::Hidden, cl::init(10), cl::desc("Roughly estimate the number of cycles that 'long latency' " "instructions take for targets with no itinerary"))
static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, MCRegister &PhysReg, int &Cost)
CheckForPhysRegDependency - Check if the dependency between def and use of a specified operand is a p...
static void ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter, SmallVectorImpl< std::pair< unsigned, MachineInstr * > > &Orders, InstrEmitter::VRBaseMapType &VRBaseMap, unsigned Order)
ProcessSDDbgValues - Process SDDbgValues associated with this node.
static void CloneNodeWithValues(SDNode *N, SelectionDAG *DAG, ArrayRef< EVT > VTs, SDValue ExtraOper=SDValue())
This file defines the SmallPtrSet class.
This file defines the SmallSet class.
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
This file describes how to lower LLVM code to machine code.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
iterator find(const_arg_type_t< KeyT > Val)
DenseMapIterator< KeyT, ValueT, KeyInfoT, BucketT > iterator
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
SmallDenseMap< SDValue, Register, 16 > VRBaseMapType
static unsigned CountResults(SDNode *Node)
CountResults - The results of target nodes have register or immediate operands first,...
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
bool mayLoad() const
Return true if this instruction could possibly read memory.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
bool isCommutable() const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z,...
Wrapper class representing physical registers. Should be passed by value.
LLVM_ABI instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
LLVM_ABI iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
MachineInstrBundleIterator< MachineInstr > iterator
BasicBlockListType::iterator iterator
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
An SDNode that represents everything that will be needed to construct a MachineInstr.
mmo_iterator memoperands_begin() const
mmo_iterator memoperands_end() const
Wrapper class representing virtual and physical registers.
SmallVectorImpl< SDDbgLabel * >::iterator DbgLabelIterator
SmallVectorImpl< SDDbgValue * >::iterator DbgIterator
Holds the information for a single machine location through SDISel; either an SDNode,...
@ SDNODE
Value is the result of an expression.
Holds the information from a dbg_value node through SDISel.
Represents one node in the SelectionDAG.
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode.
int getNodeId() const
Return the unique node id.
LLVM_ABI void dump() const
Dump this node, for debugging.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
iterator_range< value_op_iterator > op_values() const
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
static user_iterator user_end()
user_iterator user_begin() const
Provide iteration support to walk over all users of an SDNode.
SDNode * getGluedNode() const
If this node has a glue operand, return the node to which the glue operand points.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
unsigned getResNo() const
get the index which selects a specific result in the SDNode
Kind getKind() const
Returns an enum value representing the kind of the dependence.
@ Data
Regular data dependence (aka true-dependence).
void setLatency(unsigned Lat)
Sets the latency for this edge.
@ Barrier
An unknown scheduling barrier.
bool isCtrl() const
Shorthand for getKind() != SDep::Data.
Register getReg() const
Returns the register associated with this edge.
Scheduling unit. This is a node in the scheduling DAG.
bool isCloned
True if this node has been cloned.
bool isCall
Is a function call.
void setNode(SDNode *N)
Assigns the representative SDNode for this SUnit.
unsigned NodeNum
Entry # of node in the node vector.
bool hasPhysRegClobbers
Has any physreg defs, used or not.
bool isCallOp
Is a function call operand.
const TargetRegisterClass * CopyDstRC
Is a special copy node if != nullptr.
unsigned short Latency
Node latency.
unsigned short NumRegDefsLeft
bool isScheduleHigh
True if preferable to schedule high.
bool isScheduleLow
True if preferable to schedule low.
bool hasPhysRegDefs
Has physreg defs that are being used.
SmallVector< SDep, 4 > Succs
All sunit successors.
Sched::Preference SchedulingPref
Scheduling preference.
SDNode * getNode() const
Returns the representative SDNode for this SUnit.
bool isTwoAddress
Is a two-address instruction.
bool isCommutable
Is a commutable instruction.
bool isVRegCycle
May use and def the same vreg.
SmallVector< SDep, 4 > Preds
All sunit predecessors.
SUnit * OrigNode
If not this, the node from which this node was cloned.
LLVM_ABI bool addPred(const SDep &D, bool Required=true)
Adds the specified edge as a pred of the current node if not already.
RegDefIter - In place iteration over the values defined by an SUnit.
RegDefIter(const SUnit *SU, const ScheduleDAGSDNodes *SD)
SUnit * newSUnit(SDNode *N)
NewSUnit - Creates a new SUnit and return a ptr to it.
void VerifyScheduledSequence(bool isBottomUp)
VerifyScheduledSequence - Verify that all SUnits are scheduled and consistent with the Sequence of sc...
virtual void Schedule()=0
Schedule - Order nodes according to selected style, filling in the Sequence member.
virtual void computeLatency(SUnit *SU)
computeLatency - Compute node latency.
std::string getDAGName() const override
Return the basic block label.
virtual MachineBasicBlock * EmitSchedule(MachineBasicBlock::iterator &InsertPos)
EmitSchedule - Insert MachineInstrs into the MachineBasicBlock according to the order specified in Se...
virtual bool forceUnitLatencies() const
ForceUnitLatencies - Return true if all scheduling edges should be given a latency value of one.
static bool isPassiveNode(SDNode *Node)
isPassiveNode - Return true if the node is a non-scheduled leaf.
const InstrItineraryData * InstrItins
void InitNumRegDefsLeft(SUnit *SU)
InitNumRegDefsLeft - Determine the # of regs defined by this node.
std::vector< SUnit * > Sequence
The schedule. Null SUnit*'s represent noop instructions.
void Run(SelectionDAG *dag, MachineBasicBlock *bb)
Run - perform scheduling.
void BuildSchedGraph()
BuildSchedGraph - Build the SUnit graph from the selection dag that we are input.
void dump() const override
void dumpNode(const SUnit &SU) const override
SUnit * Clone(SUnit *Old)
Clone - Creates a clone of the specified SUnit.
ScheduleDAGSDNodes(MachineFunction &mf)
void dumpSchedule() const
virtual void computeOperandLatency(SDNode *Def, SDNode *Use, unsigned OpIdx, SDep &dep) const
MachineRegisterInfo & MRI
Virtual/real register map.
void clearDAG()
Clears the DAG state (between regions).
const TargetInstrInfo * TII
Target instruction information.
std::vector< SUnit > SUnits
The scheduling units.
const TargetRegisterInfo * TRI
Target processor register info.
SUnit EntrySU
Special node for the region entry.
MachineFunction & MF
Machine function.
ScheduleDAG(const ScheduleDAG &)=delete
void dumpNodeAll(const SUnit &SU) const
unsigned VerifyScheduledDAG(bool isBottomUp)
Verifies that all SUnits were scheduled and that their state is consistent.
void dumpNodeName(const SUnit &SU) const
SUnit ExitSU
Special node for the region exit.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
LLVM_ABI SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
LLVM_ABI SDNode * MorphNodeTo(SDNode *N, unsigned Opc, SDVTList VTs, ArrayRef< SDValue > Ops)
This mutates the specified node to have the specified return type, opcode, and operands.
LLVM_ABI void setNodeMemRefs(MachineSDNode *N, ArrayRef< MachineMemOperand * > NewMemRefs)
Mutate the specified machine node's memory references to the provided list.
ArrayRef< SDDbgValue * > GetDbgValues(const SDNode *SD) const
Get the debug values which reference the given SDNode.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void assign(size_type NumElts, ValueParamT Elt)
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetInstrInfo - Interface to description of machine instruction set.
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
uint8_t getCopyCost() const
Return the cost of copying a value between two registers in this class.
bool expensiveOrImpossibleToCopy() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
A Use represents the edge between a Value definition and its users.
Value * getOperand(unsigned i) const
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
initializer< Ty > init(const Ty &Val)
@ User
could "use" a pointer
NodeAddr< NodeBase * > Node
This is an optimization pass for GlobalISel generic memory operations.
void stable_sort(R &&Range)
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
void sort(IteratorTy Start, IteratorTy End)
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
class LLVM_GSL_OWNER SmallVector
Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...
FunctionAddr VTableAddr uintptr_t uintptr_t Data
auto count(R &&Range, const E &Element)
Wrapper function around std::count to count the number of times an element Element occurs in the give...
DWARFExpression::Operation Op
ArrayRef(const T &OneElt) -> ArrayRef< T >
decltype(auto) cast(const From &Val)
cast<X> - Return the argument parameter cast to the specified type.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Function object to check whether the first component of a container supported by std::get (like std::...