Scheduling dependency. More...

#include "llvm/CodeGen/ScheduleDAG.h"

Public Types
enum	Kind { Data , Anti , Output , Order }
	These are the different kinds of scheduling dependencies. More...
enum	OrderKind { Barrier , MayAliasMem , MustAliasMem , Artificial , Weak , Cluster }

Public Member Functions
	SDep ()
	Constructs a null SDep.
	SDep (SUnit *S, Kind kind, Register Reg)
	Constructs an SDep with the specified values.
	SDep (SUnit *S, OrderKind kind)
bool	overlaps (const SDep &Other) const
	Returns true if the specified SDep is equivalent except for latency.
bool	operator== (const SDep &Other) const
bool	operator!= (const SDep &Other) const
unsigned	getLatency () const
	Returns the latency value for this edge, which roughly means the minimum number of cycles that must elapse between the predecessor and the successor, given that they have this edge between them.
void	setLatency (unsigned Lat)
	Sets the latency for this edge.
SUnit *	getSUnit () const
void	setSUnit (SUnit *SU)
Kind	getKind () const
	Returns an enum value representing the kind of the dependence.
bool	isCtrl () const
	Shorthand for getKind() != SDep::Data.
bool	isNormalMemory () const
	Tests if this is an Order dependence between two memory accesses where both sides of the dependence access memory in non-volatile and fully modeled ways.
bool	isBarrier () const
	Tests if this is an Order dependence that is marked as a barrier.
bool	isNormalMemoryOrBarrier () const
	Tests if this is could be any kind of memory dependence.
bool	isMustAlias () const
	Tests if this is an Order dependence that is marked as "must alias", meaning that the SUnits at either end of the edge have a memory dependence on a known memory location.
bool	isWeak () const
	Tests if this a weak dependence.
bool	isArtificial () const
	Tests if this is an Order dependence that is marked as "artificial", meaning it isn't necessary for correctness.
bool	isCluster () const
	Tests if this is an Order dependence that is marked as "cluster", meaning it is artificial and wants to be adjacent.
bool	isAssignedRegDep () const
	Tests if this is a Data dependence that is associated with a register.
Register	getReg () const
	Returns the register associated with this edge.
void	setReg (Register Reg)
	Assigns the associated register for this edge.
LLVM_ABI void	dump (const TargetRegisterInfo *TRI=nullptr) const

Detailed Description

Scheduling dependency.

This represents one direction of an edge in the scheduling DAG.

Definition at line 51 of file ScheduleDAG.h.

Member Enumeration Documentation

◆ Kind

enum llvm::SDep::Kind

These are the different kinds of scheduling dependencies.

Enumerator
Data	Regular data dependence (aka true-dependence).
Anti	A register anti-dependence (aka WAR).
Output	A register output-dependence (aka WAW).
Order	Any other ordering dependency.

Definition at line 54 of file ScheduleDAG.h.

◆ OrderKind

enum llvm::SDep::OrderKind

Enumerator
Barrier	An unknown scheduling barrier.
MayAliasMem	Nonvolatile load/Store instructions that may alias.
MustAliasMem	Nonvolatile load/Store instructions that must alias.
Artificial	Arbitrary strong DAG edge (no real dependence).
Weak	Arbitrary weak DAG edge.
Cluster	Weak DAG edge linking a chain of clustered instrs.

Definition at line 70 of file ScheduleDAG.h.

Constructor & Destructor Documentation

◆ SDep() [1/3]

llvm::SDep::SDep ( )

inline

Constructs a null SDep.

This is only for use by container classes which require default constructors. SUnits may not/ have null SDep edges.

Definition at line 103 of file ScheduleDAG.h.

References Data.

Referenced by operator!=(), operator==(), and overlaps().

◆ SDep() [2/3]

llvm::SDep::SDep	(	SUnit *	S,
		Kind	kind,
		Register	Reg )

inline

Constructs an SDep with the specified values.

Definition at line 106 of file ScheduleDAG.h.

References Anti, assert(), Data, llvm_unreachable, Output, and Reg.

◆ SDep() [3/3]

llvm::SDep::SDep	(	SUnit *	S,
		OrderKind	kind )

inline

Definition at line 123 of file ScheduleDAG.h.

References Order.

Member Function Documentation

◆ dump()

LLVM_DUMP_METHOD void SDep::dump ( const TargetRegisterInfo * TRI = nullptr ) const

Definition at line 74 of file ScheduleDAG.cpp.

References Anti, Artificial, Barrier, Cluster, Data, llvm::dbgs(), getKind(), getLatency(), getReg(), isAssignedRegDep(), LLVM_DUMP_METHOD, MayAliasMem, MustAliasMem, Order, Output, llvm::printReg(), TRI, and Weak.

Referenced by llvm::ScheduleDAG::dumpNodeAll().

◆ getKind()

SDep::Kind llvm::SDep::getKind ( ) const

inline

Returns an enum value representing the kind of the dependence.

Definition at line 513 of file ScheduleDAG.h.

Referenced by llvm::AArch64Subtarget::adjustSchedDependency(), llvm::GCNSubtarget::adjustSchedDependency(), llvm::SchedDFSResult::compute(), llvm::ScheduleDAGSDNodes::computeOperandLatency(), dump(), getReg(), hasDataSucc(), isArtificial(), isAssignedRegDep(), isBarrier(), isCluster(), isCtrl(), isHazard(), isMustAlias(), isNormalMemory(), isWeak(), llvm::SchedDFSImpl::joinPredSubtree(), setReg(), llvm::SchedDFSImpl::visitPostorderNode(), and llvm::ARMOverrideBypasses::zeroOutputDependences().

◆ getLatency()

unsigned llvm::SDep::getLatency ( ) const

inline

Returns the latency value for this edge, which roughly means the minimum number of cycles that must elapse between the predecessor and the successor, given that they have this edge between them.

Definition at line 142 of file ScheduleDAG.h.

Referenced by llvm::GCNSubtarget::adjustSchedDependency(), llvm::HexagonSubtarget::adjustSchedDependency(), dump(), llvm::ScheduleDAGMI::releasePred(), llvm::ScheduleDAGMI::releaseSucc(), llvm::ConvergingVLIWScheduler::releaseTopNode(), and llvm::ConvergingVLIWScheduler::SchedulingCost().

◆ getReg()

Register llvm::SDep::getReg ( ) const

inline

Returns the register associated with this edge.

This is only valid on Data, Anti, and Output edges. On Data edges, this value may be zero, meaning there is no associated register.

Definition at line 216 of file ScheduleDAG.h.

References Anti, assert(), Data, getKind(), and Output.

Referenced by llvm::AArch64Subtarget::adjustSchedDependency(), llvm::GCNSubtarget::adjustSchedDependency(), canClobberReachingPhysRegUse(), dump(), and llvm::ARMOverrideBypasses::makeBundleAssumptions().

◆ getSUnit()

SUnit * llvm::SDep::getSUnit ( ) const

inline

Definition at line 507 of file ScheduleDAG.h.

Referenced by llvm::ScheduleDAGInstrs::addEdge(), llvm::SUnit::addPred(), canClobberReachingPhysRegUse(), closestSucc(), closestSucc(), llvm::SchedDFSResult::compute(), llvm::ScheduleDAG::dumpNodeAll(), hasDataSucc(), hasOnlyLiveOutUses(), llvm::ScheduleDAGTopologicalSort::InitDAGTopologicalSorting(), llvm::ResourcePriorityQueue::isResourceAvailable(), llvm::isSoleUseCopyToV0(), llvm::SchedDFSImpl::joinPredSubtree(), llvm::ARMOverrideBypasses::makeBundleAssumptions(), llvm::ARMOverrideBypasses::memoryRAWHazard(), llvm::LatencyPriorityQueue::push(), llvm::ResourcePriorityQueue::push(), llvm::ScheduleDAGMI::releasePred(), llvm::ScheduleDAGMI::releaseSucc(), llvm::ConvergingVLIWScheduler::releaseTopNode(), llvm::LatencyPriorityQueue::scheduledNode(), llvm::ResourcePriorityQueue::scheduledNode(), llvm::ConvergingVLIWScheduler::SchedulingCost(), llvm::ARMOverrideBypasses::setBidirLatencies(), llvm::SUnit::setDepthDirty(), llvm::SUnit::setHeightDirty(), llvm::SwingSchedulerDDGEdge::SwingSchedulerDDGEdge(), llvm::SchedDFSImpl::visitCrossEdge(), llvm::SchedDFSImpl::visitPostorderEdge(), llvm::SchedDFSImpl::visitPostorderNode(), and llvm::ScheduleDAGTopologicalSort::WillCreateCycle().

◆ isArtificial()

bool llvm::SDep::isArtificial ( ) const

inline

Tests if this is an Order dependence that is marked as "artificial", meaning it isn't necessary for correctness.

Definition at line 200 of file ScheduleDAG.h.

References Artificial, getKind(), and Order.

Referenced by llvm::ScheduleDAGInstrs::addEdge(), llvm::HexagonSubtarget::adjustSchedDependency(), and llvm::SUnitIterator::isArtificialDep().

◆ isAssignedRegDep()

bool llvm::SDep::isAssignedRegDep ( ) const

inline

Tests if this is a Data dependence that is associated with a register.

Definition at line 211 of file ScheduleDAG.h.

References Data, and getKind().

Referenced by canClobberReachingPhysRegUse(), dump(), llvm::ARMOverrideBypasses::makeBundleAssumptions(), llvm::ConvergingVLIWScheduler::SchedulingCost(), and llvm::ScheduleDAGTopologicalSort::WillCreateCycle().

◆ isBarrier()

bool llvm::SDep::isBarrier ( ) const

inline

Tests if this is an Order dependence that is marked as a barrier.

Definition at line 174 of file ScheduleDAG.h.

References Barrier, getKind(), and Order.

Referenced by isNormalMemoryOrBarrier().

◆ isCluster()

bool llvm::SDep::isCluster ( ) const

inline

Tests if this is an Order dependence that is marked as "cluster", meaning it is artificial and wants to be adjacent.

Definition at line 206 of file ScheduleDAG.h.

References Cluster, getKind(), and Order.

◆ isCtrl()

bool llvm::SDep::isCtrl ( ) const

inline

Shorthand for getKind() != SDep::Data.

Definition at line 161 of file ScheduleDAG.h.

References Data, and getKind().

Referenced by closestSucc(), closestSucc(), hasOnlyLiveOutUses(), llvm::SUnitIterator::isCtrlDep(), llvm::ResourcePriorityQueue::isResourceAvailable(), numberCtrlDepsInSU(), and llvm::ResourcePriorityQueue::scheduledNode().

◆ isMustAlias()

bool llvm::SDep::isMustAlias ( ) const

inline

Tests if this is an Order dependence that is marked as "must alias", meaning that the SUnits at either end of the edge have a memory dependence on a known memory location.

Definition at line 186 of file ScheduleDAG.h.

References getKind(), MustAliasMem, and Order.

◆ isNormalMemory()

bool llvm::SDep::isNormalMemory ( ) const

inline

Tests if this is an Order dependence between two memory accesses where both sides of the dependence access memory in non-volatile and fully modeled ways.

Definition at line 168 of file ScheduleDAG.h.

References getKind(), MayAliasMem, MustAliasMem, and Order.

Referenced by isNormalMemoryOrBarrier(), and llvm::ARMOverrideBypasses::memoryRAWHazard().

◆ isNormalMemoryOrBarrier()

bool llvm::SDep::isNormalMemoryOrBarrier ( ) const

inline

Tests if this is could be any kind of memory dependence.

Definition at line 179 of file ScheduleDAG.h.

References isBarrier(), and isNormalMemory().

◆ isWeak()

bool llvm::SDep::isWeak ( ) const

inline

Tests if this a weak dependence.

Weak dependencies are considered DAG edges for height computation and other heuristics, but do not force ordering. Breaking a weak edge may require the scheduler to compensate, for example by inserting a copy.

Definition at line 194 of file ScheduleDAG.h.

References getKind(), Order, and Weak.

Referenced by llvm::isSoleUseCopyToV0(), llvm::ScheduleDAGMI::releasePred(), and llvm::ScheduleDAGMI::releaseSucc().

◆ operator!=()

bool llvm::SDep::operator!= ( const SDep & Other ) const

inline

Definition at line 135 of file ScheduleDAG.h.

References operator==(), llvm::Other, and SDep().

◆ operator==()

bool llvm::SDep::operator== ( const SDep & Other ) const

inline

Definition at line 131 of file ScheduleDAG.h.

References llvm::Other, overlaps(), and SDep().

Referenced by operator!=().

◆ overlaps()

bool llvm::SDep::overlaps ( const SDep & Other ) const

inline

Returns true if the specified SDep is equivalent except for latency.

Definition at line 492 of file ScheduleDAG.h.

References Anti, Data, llvm_unreachable, Order, llvm::Other, Output, and SDep().

Referenced by operator==().

◆ setLatency()

void llvm::SDep::setLatency ( unsigned Lat )

inline

Sets the latency for this edge.

Definition at line 147 of file ScheduleDAG.h.

Referenced by llvm::ScheduleDAGInstrs::addChainDependency(), llvm::ScheduleDAGInstrs::addPhysRegDataDeps(), llvm::ScheduleDAGInstrs::addPhysRegDeps(), llvm::SUnit::addPred(), llvm::SUnit::addPredBarrier(), llvm::ScheduleDAGInstrs::addVRegDefDeps(), llvm::AArch64Subtarget::adjustSchedDependency(), llvm::GCNSubtarget::adjustSchedDependency(), llvm::HexagonSubtarget::adjustSchedDependency(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::ScheduleDAGSDNodes::computeOperandLatency(), llvm::LoopCarriedEdges::modifySUnits(), and llvm::ARMOverrideBypasses::setBidirLatencies().

◆ setReg()

void llvm::SDep::setReg ( Register Reg )

inline

Assigns the associated register for this edge.

This is only valid on Data, Anti, and Output edges. On Anti and Output edges, this value must not be zero. On Data edges, the value may be zero, which would mean that no specific register is associated with this edge.

Definition at line 226 of file ScheduleDAG.h.

References Anti, assert(), Data, getKind(), Output, and Reg.

◆ setSUnit()

void llvm::SDep::setSUnit ( SUnit * SU )

inline

Definition at line 510 of file ScheduleDAG.h.

Referenced by llvm::SUnit::addPred(), and llvm::LoopCarriedEdges::modifySUnits().

Member Data Documentation

◆ OrdKind

unsigned llvm::SDep::OrdKind

Additional information about Order dependencies.

Definition at line 92 of file ScheduleDAG.h.

◆ Reg

unsigned llvm::SDep::Reg

For Data, Anti, and Output dependencies, the associated register.

For Data dependencies that don't currently have a register/ assigned, this is set to zero.

Definition at line 89 of file ScheduleDAG.h.

Referenced by SDep(), and setReg().

The documentation for this class was generated from the following files:

include/llvm/CodeGen/ScheduleDAG.h
lib/CodeGen/ScheduleDAG.cpp

Public Types

Public Member Functions

Detailed Description

Member Enumeration Documentation

◆ Kind

◆ OrderKind

Constructor & Destructor Documentation

◆ SDep() [1/3]

◆ SDep() [2/3]

◆ SDep() [3/3]

Member Function Documentation

◆ dump()

◆ getKind()

◆ getLatency()

◆ getReg()

◆ getSUnit()

◆ isArtificial()

◆ isAssignedRegDep()

◆ isBarrier()

◆ isCluster()

◆ isCtrl()

◆ isMustAlias()

◆ isNormalMemory()

◆ isNormalMemoryOrBarrier()

◆ isWeak()

◆ operator!=()

◆ operator==()

◆ overlaps()

◆ setLatency()

◆ setReg()

◆ setSUnit()

Member Data Documentation

◆ OrdKind

◆ Reg