LLVM  14.0.0git
HexagonSubtarget.cpp
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1 //===- HexagonSubtarget.cpp - Hexagon Subtarget Information ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the Hexagon specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "HexagonSubtarget.h"
14 #include "Hexagon.h"
15 #include "HexagonInstrInfo.h"
16 #include "HexagonRegisterInfo.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/StringRef.h"
30 #include <algorithm>
31 #include <cassert>
32 #include <map>
33 
34 using namespace llvm;
35 
36 #define DEBUG_TYPE "hexagon-subtarget"
37 
38 #define GET_SUBTARGETINFO_CTOR
39 #define GET_SUBTARGETINFO_TARGET_DESC
40 #include "HexagonGenSubtargetInfo.inc"
41 
42 static cl::opt<bool> EnableBSBSched("enable-bsb-sched",
44 
45 static cl::opt<bool> EnableTCLatencySched("enable-tc-latency-sched",
47 
48 static cl::opt<bool> EnableDotCurSched("enable-cur-sched",
50  cl::desc("Enable the scheduler to generate .cur"));
51 
52 static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched",
54  cl::desc("Disable Hexagon MI Scheduling"));
55 
56 static cl::opt<bool> EnableSubregLiveness("hexagon-subreg-liveness",
58  cl::desc("Enable subregister liveness tracking for Hexagon"));
59 
60 static cl::opt<bool> OverrideLongCalls("hexagon-long-calls",
62  cl::desc("If present, forces/disables the use of long calls"));
63 
64 static cl::opt<bool> EnablePredicatedCalls("hexagon-pred-calls",
66  cl::desc("Consider calls to be predicable"));
67 
68 static cl::opt<bool> SchedPredsCloser("sched-preds-closer",
70 
71 static cl::opt<bool> SchedRetvalOptimization("sched-retval-optimization",
73 
74 static cl::opt<bool> EnableCheckBankConflict("hexagon-check-bank-conflict",
76  cl::desc("Enable checking for cache bank conflicts"));
77 
79  StringRef FS, const TargetMachine &TM)
80  : HexagonGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
81  OptLevel(TM.getOptLevel()),
82  CPUString(std::string(Hexagon_MC::selectHexagonCPU(CPU))),
83  TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)),
84  RegInfo(getHwMode()), TLInfo(TM, *this),
85  InstrItins(getInstrItineraryForCPU(CPUString)) {
87  // Beware of the default constructor of InstrItineraryData: it will
88  // reset all members to 0.
89  assert(InstrItins.Itineraries != nullptr && "InstrItins not initialized");
90 }
91 
96  if (ArchVer)
97  HexagonArchVersion = *ArchVer;
98  else
99  llvm_unreachable("Unrecognized Hexagon processor version");
100 
101  UseHVX128BOps = false;
102  UseHVX64BOps = false;
103  UseAudioOps = false;
104  UseLongCalls = false;
105 
107 
108  ParseSubtargetFeatures(CPUString, /*TuneCPU*/ CPUString, FS);
109 
111  UseLongCalls = OverrideLongCalls;
112 
113  if (isTinyCore()) {
114  // Tiny core has a single thread, so back-to-back scheduling is enabled by
115  // default.
117  UseBSBScheduling = false;
118  }
119 
120  FeatureBitset Features = getFeatureBits();
122  setFeatureBits(Features.reset(Hexagon::FeatureDuplex));
123  setFeatureBits(Hexagon_MC::completeHVXFeatures(Features));
124 
125  return *this;
126 }
127 
128 bool HexagonSubtarget::isHVXElementType(MVT Ty, bool IncludeBool) const {
129  if (!useHVXOps())
130  return false;
131  if (Ty.isVector())
132  Ty = Ty.getVectorElementType();
133  if (IncludeBool && Ty == MVT::i1)
134  return true;
135  ArrayRef<MVT> ElemTypes = getHVXElementTypes();
136  return llvm::is_contained(ElemTypes, Ty);
137 }
138 
139 bool HexagonSubtarget::isHVXVectorType(MVT VecTy, bool IncludeBool) const {
140  if (!VecTy.isVector() || !useHVXOps() || VecTy.isScalableVector())
141  return false;
142  MVT ElemTy = VecTy.getVectorElementType();
143  if (!IncludeBool && ElemTy == MVT::i1)
144  return false;
145 
146  unsigned HwLen = getVectorLength();
147  unsigned NumElems = VecTy.getVectorNumElements();
148  ArrayRef<MVT> ElemTypes = getHVXElementTypes();
149 
150  if (IncludeBool && ElemTy == MVT::i1) {
151  // Boolean HVX vector types are formed from regular HVX vector types
152  // by replacing the element type with i1.
153  for (MVT T : ElemTypes)
154  if (NumElems * T.getSizeInBits() == 8 * HwLen)
155  return true;
156  return false;
157  }
158 
159  unsigned VecWidth = VecTy.getSizeInBits();
160  if (VecWidth != 8 * HwLen && VecWidth != 16 * HwLen)
161  return false;
162  return llvm::is_contained(ElemTypes, ElemTy);
163 }
164 
165 bool HexagonSubtarget::isTypeForHVX(Type *VecTy, bool IncludeBool) const {
166  if (!VecTy->isVectorTy() || isa<ScalableVectorType>(VecTy))
167  return false;
168  // Avoid types like <2 x i32*>.
169  if (!cast<VectorType>(VecTy)->getElementType()->isIntegerTy())
170  return false;
171  // The given type may be something like <17 x i32>, which is not MVT,
172  // but can be represented as (non-simple) EVT.
173  EVT Ty = EVT::getEVT(VecTy, /*HandleUnknown*/false);
174  if (Ty.getSizeInBits() <= 64 || !Ty.getVectorElementType().isSimple())
175  return false;
176 
177  auto isHvxTy = [this, IncludeBool](MVT SimpleTy) {
178  if (isHVXVectorType(SimpleTy, IncludeBool))
179  return true;
180  auto Action = getTargetLowering()->getPreferredVectorAction(SimpleTy);
181  return Action == TargetLoweringBase::TypeWidenVector;
182  };
183 
184  // Round up EVT to have power-of-2 elements, and keep checking if it
185  // qualifies for HVX, dividing it in half after each step.
186  MVT ElemTy = Ty.getVectorElementType().getSimpleVT();
187  unsigned VecLen = PowerOf2Ceil(Ty.getVectorNumElements());
188  while (ElemTy.getSizeInBits() * VecLen > 64) {
189  MVT SimpleTy = MVT::getVectorVT(ElemTy, VecLen);
190  if (SimpleTy.isValid() && isHvxTy(SimpleTy))
191  return true;
192  VecLen /= 2;
193  }
194 
195  return false;
196 }
197 
199  for (SUnit &SU : DAG->SUnits) {
200  if (!SU.isInstr())
201  continue;
202  SmallVector<SDep, 4> Erase;
203  for (auto &D : SU.Preds)
204  if (D.getKind() == SDep::Output && D.getReg() == Hexagon::USR_OVF)
205  Erase.push_back(D);
206  for (auto &E : Erase)
207  SU.removePred(E);
208  }
209 }
210 
212  for (SUnit &SU : DAG->SUnits) {
213  // Update the latency of chain edges between v60 vector load or store
214  // instructions to be 1. These instruction cannot be scheduled in the
215  // same packet.
216  MachineInstr &MI1 = *SU.getInstr();
217  auto *QII = static_cast<const HexagonInstrInfo*>(DAG->TII);
218  bool IsStoreMI1 = MI1.mayStore();
219  bool IsLoadMI1 = MI1.mayLoad();
220  if (!QII->isHVXVec(MI1) || !(IsStoreMI1 || IsLoadMI1))
221  continue;
222  for (SDep &SI : SU.Succs) {
223  if (SI.getKind() != SDep::Order || SI.getLatency() != 0)
224  continue;
225  MachineInstr &MI2 = *SI.getSUnit()->getInstr();
226  if (!QII->isHVXVec(MI2))
227  continue;
228  if ((IsStoreMI1 && MI2.mayStore()) || (IsLoadMI1 && MI2.mayLoad())) {
229  SI.setLatency(1);
230  SU.setHeightDirty();
231  // Change the dependence in the opposite direction too.
232  for (SDep &PI : SI.getSUnit()->Preds) {
233  if (PI.getSUnit() != &SU || PI.getKind() != SDep::Order)
234  continue;
235  PI.setLatency(1);
236  SI.getSUnit()->setDepthDirty();
237  }
238  }
239  }
240  }
241 }
242 
243 // Check if a call and subsequent A2_tfrpi instructions should maintain
244 // scheduling affinity. We are looking for the TFRI to be consumed in
245 // the next instruction. This should help reduce the instances of
246 // double register pairs being allocated and scheduled before a call
247 // when not used until after the call. This situation is exacerbated
248 // by the fact that we allocate the pair from the callee saves list,
249 // leading to excess spills and restores.
250 bool HexagonSubtarget::CallMutation::shouldTFRICallBind(
251  const HexagonInstrInfo &HII, const SUnit &Inst1,
252  const SUnit &Inst2) const {
253  if (Inst1.getInstr()->getOpcode() != Hexagon::A2_tfrpi)
254  return false;
255 
256  // TypeXTYPE are 64 bit operations.
257  unsigned Type = HII.getType(*Inst2.getInstr());
260 }
261 
263  ScheduleDAGMI *DAG = static_cast<ScheduleDAGMI*>(DAGInstrs);
264  SUnit* LastSequentialCall = nullptr;
265  // Map from virtual register to physical register from the copy.
266  DenseMap<unsigned, unsigned> VRegHoldingReg;
267  // Map from the physical register to the instruction that uses virtual
268  // register. This is used to create the barrier edge.
269  DenseMap<unsigned, SUnit *> LastVRegUse;
270  auto &TRI = *DAG->MF.getSubtarget().getRegisterInfo();
271  auto &HII = *DAG->MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
272 
273  // Currently we only catch the situation when compare gets scheduled
274  // before preceding call.
275  for (unsigned su = 0, e = DAG->SUnits.size(); su != e; ++su) {
276  // Remember the call.
277  if (DAG->SUnits[su].getInstr()->isCall())
278  LastSequentialCall = &DAG->SUnits[su];
279  // Look for a compare that defines a predicate.
280  else if (DAG->SUnits[su].getInstr()->isCompare() && LastSequentialCall)
281  DAG->addEdge(&DAG->SUnits[su], SDep(LastSequentialCall, SDep::Barrier));
282  // Look for call and tfri* instructions.
283  else if (SchedPredsCloser && LastSequentialCall && su > 1 && su < e-1 &&
284  shouldTFRICallBind(HII, DAG->SUnits[su], DAG->SUnits[su+1]))
285  DAG->addEdge(&DAG->SUnits[su], SDep(&DAG->SUnits[su-1], SDep::Barrier));
286  // Prevent redundant register copies due to reads and writes of physical
287  // registers. The original motivation for this was the code generated
288  // between two calls, which are caused both the return value and the
289  // argument for the next call being in %r0.
290  // Example:
291  // 1: <call1>
292  // 2: %vreg = COPY %r0
293  // 3: <use of %vreg>
294  // 4: %r0 = ...
295  // 5: <call2>
296  // The scheduler would often swap 3 and 4, so an additional register is
297  // needed. This code inserts a Barrier dependence between 3 & 4 to prevent
298  // this.
299  // The code below checks for all the physical registers, not just R0/D0/V0.
300  else if (SchedRetvalOptimization) {
301  const MachineInstr *MI = DAG->SUnits[su].getInstr();
302  if (MI->isCopy() &&
303  Register::isPhysicalRegister(MI->getOperand(1).getReg())) {
304  // %vregX = COPY %r0
305  VRegHoldingReg[MI->getOperand(0).getReg()] = MI->getOperand(1).getReg();
306  LastVRegUse.erase(MI->getOperand(1).getReg());
307  } else {
308  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
309  const MachineOperand &MO = MI->getOperand(i);
310  if (!MO.isReg())
311  continue;
312  if (MO.isUse() && !MI->isCopy() &&
313  VRegHoldingReg.count(MO.getReg())) {
314  // <use of %vregX>
315  LastVRegUse[VRegHoldingReg[MO.getReg()]] = &DAG->SUnits[su];
316  } else if (MO.isDef() && Register::isPhysicalRegister(MO.getReg())) {
317  for (MCRegAliasIterator AI(MO.getReg(), &TRI, true); AI.isValid();
318  ++AI) {
319  if (LastVRegUse.count(*AI) &&
320  LastVRegUse[*AI] != &DAG->SUnits[su])
321  // %r0 = ...
322  DAG->addEdge(&DAG->SUnits[su], SDep(LastVRegUse[*AI], SDep::Barrier));
323  LastVRegUse.erase(*AI);
324  }
325  }
326  }
327  }
328  }
329  }
330 }
331 
334  return;
335 
336  const auto &HII = static_cast<const HexagonInstrInfo&>(*DAG->TII);
337 
338  // Create artificial edges between loads that could likely cause a bank
339  // conflict. Since such loads would normally not have any dependency
340  // between them, we cannot rely on existing edges.
341  for (unsigned i = 0, e = DAG->SUnits.size(); i != e; ++i) {
342  SUnit &S0 = DAG->SUnits[i];
343  MachineInstr &L0 = *S0.getInstr();
344  if (!L0.mayLoad() || L0.mayStore() ||
346  continue;
347  int64_t Offset0;
348  unsigned Size0;
349  MachineOperand *BaseOp0 = HII.getBaseAndOffset(L0, Offset0, Size0);
350  // Is the access size is longer than the L1 cache line, skip the check.
351  if (BaseOp0 == nullptr || !BaseOp0->isReg() || Size0 >= 32)
352  continue;
353  // Scan only up to 32 instructions ahead (to avoid n^2 complexity).
354  for (unsigned j = i+1, m = std::min(i+32, e); j != m; ++j) {
355  SUnit &S1 = DAG->SUnits[j];
356  MachineInstr &L1 = *S1.getInstr();
357  if (!L1.mayLoad() || L1.mayStore() ||
359  continue;
360  int64_t Offset1;
361  unsigned Size1;
362  MachineOperand *BaseOp1 = HII.getBaseAndOffset(L1, Offset1, Size1);
363  if (BaseOp1 == nullptr || !BaseOp1->isReg() || Size1 >= 32 ||
364  BaseOp0->getReg() != BaseOp1->getReg())
365  continue;
366  // Check bits 3 and 4 of the offset: if they differ, a bank conflict
367  // is unlikely.
368  if (((Offset0 ^ Offset1) & 0x18) != 0)
369  continue;
370  // Bits 3 and 4 are the same, add an artificial edge and set extra
371  // latency.
372  SDep A(&S0, SDep::Artificial);
373  A.setLatency(1);
374  S1.addPred(A, true);
375  }
376  }
377 }
378 
379 /// Enable use of alias analysis during code generation (during MI
380 /// scheduling, DAGCombine, etc.).
382  if (OptLevel != CodeGenOpt::None)
383  return true;
384  return false;
385 }
386 
387 /// Perform target specific adjustments to the latency of a schedule
388 /// dependency.
390  SUnit *Dst, int DstOpIdx,
391  SDep &Dep) const {
392  if (!Src->isInstr() || !Dst->isInstr())
393  return;
394 
395  MachineInstr *SrcInst = Src->getInstr();
396  MachineInstr *DstInst = Dst->getInstr();
397  const HexagonInstrInfo *QII = getInstrInfo();
398 
399  // Instructions with .new operands have zero latency.
400  SmallSet<SUnit *, 4> ExclSrc;
401  SmallSet<SUnit *, 4> ExclDst;
402  if (QII->canExecuteInBundle(*SrcInst, *DstInst) &&
403  isBestZeroLatency(Src, Dst, QII, ExclSrc, ExclDst)) {
404  Dep.setLatency(0);
405  return;
406  }
407 
408  if (!hasV60Ops())
409  return;
410 
411  // Set the latency for a copy to zero since we hope that is will get removed.
412  if (DstInst->isCopy())
413  Dep.setLatency(0);
414 
415  // If it's a REG_SEQUENCE/COPY, use its destination instruction to determine
416  // the correct latency.
417  if ((DstInst->isRegSequence() || DstInst->isCopy()) && Dst->NumSuccs == 1) {
418  Register DReg = DstInst->getOperand(0).getReg();
419  MachineInstr *DDst = Dst->Succs[0].getSUnit()->getInstr();
420  unsigned UseIdx = -1;
421  for (unsigned OpNum = 0; OpNum < DDst->getNumOperands(); OpNum++) {
422  const MachineOperand &MO = DDst->getOperand(OpNum);
423  if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == DReg) {
424  UseIdx = OpNum;
425  break;
426  }
427  }
428  int DLatency = (InstrInfo.getOperandLatency(&InstrItins, *SrcInst,
429  0, *DDst, UseIdx));
430  DLatency = std::max(DLatency, 0);
431  Dep.setLatency((unsigned)DLatency);
432  }
433 
434  // Try to schedule uses near definitions to generate .cur.
435  ExclSrc.clear();
436  ExclDst.clear();
437  if (EnableDotCurSched && QII->isToBeScheduledASAP(*SrcInst, *DstInst) &&
438  isBestZeroLatency(Src, Dst, QII, ExclSrc, ExclDst)) {
439  Dep.setLatency(0);
440  return;
441  }
442 
443  updateLatency(*SrcInst, *DstInst, Dep);
444 }
445 
447  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
448  Mutations.push_back(std::make_unique<UsrOverflowMutation>());
449  Mutations.push_back(std::make_unique<HVXMemLatencyMutation>());
450  Mutations.push_back(std::make_unique<BankConflictMutation>());
451 }
452 
454  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
455  Mutations.push_back(std::make_unique<UsrOverflowMutation>());
456  Mutations.push_back(std::make_unique<HVXMemLatencyMutation>());
457 }
458 
459 // Pin the vtable to this file.
460 void HexagonSubtarget::anchor() {}
461 
464  return !DisableHexagonMISched;
465  return true;
466 }
467 
469  return EnablePredicatedCalls;
470 }
471 
472 void HexagonSubtarget::updateLatency(MachineInstr &SrcInst,
473  MachineInstr &DstInst, SDep &Dep) const {
474  if (Dep.isArtificial()) {
475  Dep.setLatency(1);
476  return;
477  }
478 
479  if (!hasV60Ops())
480  return;
481 
482  auto &QII = static_cast<const HexagonInstrInfo&>(*getInstrInfo());
483 
484  // BSB scheduling.
485  if (QII.isHVXVec(SrcInst) || useBSBScheduling())
486  Dep.setLatency((Dep.getLatency() + 1) >> 1);
487 }
488 
489 void HexagonSubtarget::restoreLatency(SUnit *Src, SUnit *Dst) const {
490  MachineInstr *SrcI = Src->getInstr();
491  for (auto &I : Src->Succs) {
492  if (!I.isAssignedRegDep() || I.getSUnit() != Dst)
493  continue;
494  Register DepR = I.getReg();
495  int DefIdx = -1;
496  for (unsigned OpNum = 0; OpNum < SrcI->getNumOperands(); OpNum++) {
497  const MachineOperand &MO = SrcI->getOperand(OpNum);
498  bool IsSameOrSubReg = false;
499  if (MO.isReg()) {
500  Register MOReg = MO.getReg();
501  if (DepR.isVirtual()) {
502  IsSameOrSubReg = (MOReg == DepR);
503  } else {
504  IsSameOrSubReg = getRegisterInfo()->isSubRegisterEq(DepR, MOReg);
505  }
506  if (MO.isDef() && IsSameOrSubReg)
507  DefIdx = OpNum;
508  }
509  }
510  assert(DefIdx >= 0 && "Def Reg not found in Src MI");
511  MachineInstr *DstI = Dst->getInstr();
512  SDep T = I;
513  for (unsigned OpNum = 0; OpNum < DstI->getNumOperands(); OpNum++) {
514  const MachineOperand &MO = DstI->getOperand(OpNum);
515  if (MO.isReg() && MO.isUse() && MO.getReg() == DepR) {
516  int Latency = (InstrInfo.getOperandLatency(&InstrItins, *SrcI,
517  DefIdx, *DstI, OpNum));
518 
519  // For some instructions (ex: COPY), we might end up with < 0 latency
520  // as they don't have any Itinerary class associated with them.
521  Latency = std::max(Latency, 0);
522 
523  I.setLatency(Latency);
524  updateLatency(*SrcI, *DstI, I);
525  }
526  }
527 
528  // Update the latency of opposite edge too.
529  T.setSUnit(Src);
530  auto F = find(Dst->Preds, T);
531  assert(F != Dst->Preds.end());
532  F->setLatency(I.getLatency());
533  }
534 }
535 
536 /// Change the latency between the two SUnits.
537 void HexagonSubtarget::changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat)
538  const {
539  for (auto &I : Src->Succs) {
540  if (!I.isAssignedRegDep() || I.getSUnit() != Dst)
541  continue;
542  SDep T = I;
543  I.setLatency(Lat);
544 
545  // Update the latency of opposite edge too.
546  T.setSUnit(Src);
547  auto F = find(Dst->Preds, T);
548  assert(F != Dst->Preds.end());
549  F->setLatency(Lat);
550  }
551 }
552 
553 /// If the SUnit has a zero latency edge, return the other SUnit.
555  for (auto &I : Deps)
556  if (I.isAssignedRegDep() && I.getLatency() == 0 &&
557  !I.getSUnit()->getInstr()->isPseudo())
558  return I.getSUnit();
559  return nullptr;
560 }
561 
562 // Return true if these are the best two instructions to schedule
563 // together with a zero latency. Only one dependence should have a zero
564 // latency. If there are multiple choices, choose the best, and change
565 // the others, if needed.
566 bool HexagonSubtarget::isBestZeroLatency(SUnit *Src, SUnit *Dst,
567  const HexagonInstrInfo *TII, SmallSet<SUnit*, 4> &ExclSrc,
568  SmallSet<SUnit*, 4> &ExclDst) const {
569  MachineInstr &SrcInst = *Src->getInstr();
570  MachineInstr &DstInst = *Dst->getInstr();
571 
572  // Ignore Boundary SU nodes as these have null instructions.
573  if (Dst->isBoundaryNode())
574  return false;
575 
576  if (SrcInst.isPHI() || DstInst.isPHI())
577  return false;
578 
579  if (!TII->isToBeScheduledASAP(SrcInst, DstInst) &&
580  !TII->canExecuteInBundle(SrcInst, DstInst))
581  return false;
582 
583  // The architecture doesn't allow three dependent instructions in the same
584  // packet. So, if the destination has a zero latency successor, then it's
585  // not a candidate for a zero latency predecessor.
586  if (getZeroLatency(Dst, Dst->Succs) != nullptr)
587  return false;
588 
589  // Check if the Dst instruction is the best candidate first.
590  SUnit *Best = nullptr;
591  SUnit *DstBest = nullptr;
592  SUnit *SrcBest = getZeroLatency(Dst, Dst->Preds);
593  if (SrcBest == nullptr || Src->NodeNum >= SrcBest->NodeNum) {
594  // Check that Src doesn't have a better candidate.
595  DstBest = getZeroLatency(Src, Src->Succs);
596  if (DstBest == nullptr || Dst->NodeNum <= DstBest->NodeNum)
597  Best = Dst;
598  }
599  if (Best != Dst)
600  return false;
601 
602  // The caller frequently adds the same dependence twice. If so, then
603  // return true for this case too.
604  if ((Src == SrcBest && Dst == DstBest ) ||
605  (SrcBest == nullptr && Dst == DstBest) ||
606  (Src == SrcBest && Dst == nullptr))
607  return true;
608 
609  // Reassign the latency for the previous bests, which requires setting
610  // the dependence edge in both directions.
611  if (SrcBest != nullptr) {
612  if (!hasV60Ops())
613  changeLatency(SrcBest, Dst, 1);
614  else
615  restoreLatency(SrcBest, Dst);
616  }
617  if (DstBest != nullptr) {
618  if (!hasV60Ops())
619  changeLatency(Src, DstBest, 1);
620  else
621  restoreLatency(Src, DstBest);
622  }
623 
624  // Attempt to find another opprotunity for zero latency in a different
625  // dependence.
626  if (SrcBest && DstBest)
627  // If there is an edge from SrcBest to DstBst, then try to change that
628  // to 0 now.
629  changeLatency(SrcBest, DstBest, 0);
630  else if (DstBest) {
631  // Check if the previous best destination instruction has a new zero
632  // latency dependence opportunity.
633  ExclSrc.insert(Src);
634  for (auto &I : DstBest->Preds)
635  if (ExclSrc.count(I.getSUnit()) == 0 &&
636  isBestZeroLatency(I.getSUnit(), DstBest, TII, ExclSrc, ExclDst))
637  changeLatency(I.getSUnit(), DstBest, 0);
638  } else if (SrcBest) {
639  // Check if previous best source instruction has a new zero latency
640  // dependence opportunity.
641  ExclDst.insert(Dst);
642  for (auto &I : SrcBest->Succs)
643  if (ExclDst.count(I.getSUnit()) == 0 &&
644  isBestZeroLatency(SrcBest, I.getSUnit(), TII, ExclSrc, ExclDst))
645  changeLatency(SrcBest, I.getSUnit(), 0);
646  }
647 
648  return true;
649 }
650 
652  return 32;
653 }
654 
656  return 32;
657 }
658 
660  return EnableSubregLiveness;
661 }
i
i
Definition: README.txt:29
HexagonMCTargetDesc.h
llvm::HexagonSubtarget::getVectorLength
unsigned getVectorLength() const
Definition: HexagonSubtarget.h:274
llvm::cl::Option::getPosition
unsigned getPosition() const
Definition: CommandLine.h:305
llvm::HexagonSubtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
llvm::MVT::getVectorElementType
MVT getVectorElementType() const
Definition: MachineValueType.h:519
ScheduleDAG.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
MachineInstr.h
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
SchedPredsCloser
static cl::opt< bool > SchedPredsCloser("sched-preds-closer", cl::Hidden, cl::ZeroOrMore, cl::init(true))
llvm::SDep::Artificial
@ Artificial
Arbitrary strong DAG edge (no real dependence).
Definition: ScheduleDAG.h:72
llvm::Latency
@ Latency
Definition: SIMachineScheduler.h:34
StringRef.h
ScheduleDAGInstrs.h
llvm::MachineInstr::mayLoad
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:1005
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::HexagonSubtarget::HexagonSubtarget
HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM)
Definition: HexagonSubtarget.cpp:78
llvm::MVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: MachineValueType.h:366
EnablePredicatedCalls
static cl::opt< bool > EnablePredicatedCalls("hexagon-pred-calls", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Consider calls to be predicable"))
HexagonSubtarget.h
ErrorHandling.h
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::Hexagon_MC::addArchSubtarget
void addArchSubtarget(MCSubtargetInfo const *STI, StringRef FS)
Definition: HexagonMCTargetDesc.cpp:517
llvm::HexagonInstrInfo::getAddrMode
unsigned getAddrMode(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:3182
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::erase
bool erase(const KeyT &Val)
Definition: DenseMap.h:302
llvm::ScheduleDAGInstrs::addEdge
bool addEdge(SUnit *SuccSU, const SDep &PredDep)
Add a DAG edge to the given SU with the given predecessor dependence data.
Definition: ScheduleDAGInstrs.cpp:1205
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
llvm::SUnit::Succs
SmallVector< SDep, 4 > Succs
All sunit successors.
Definition: ScheduleDAG.h:257
llvm::Optional
Definition: APInt.h:33
llvm::HexagonSubtarget::HexagonArchVersion
Hexagon::ArchEnum HexagonArchVersion
Definition: HexagonSubtarget.h:67
llvm::DenseMapBase::count
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:145
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::HexagonSubtarget::enableSubRegLiveness
bool enableSubRegLiveness() const override
Definition: HexagonSubtarget.cpp:659
llvm::MachineInstr::isCopy
bool isCopy() const
Definition: MachineInstr.h:1291
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
SchedRetvalOptimization
static cl::opt< bool > SchedRetvalOptimization("sched-retval-optimization", cl::Hidden, cl::ZeroOrMore, cl::init(true))
STLExtras.h
llvm::Hexagon::GetCpu
llvm::Optional< ArchEnum > GetCpu(ArchCont const &ArchList, Val CPUString)
Definition: HexagonArch.h:28
llvm::PowerOf2Ceil
uint64_t PowerOf2Ceil(uint64_t A)
Returns the power of two which is greater than or equal to the given value.
Definition: MathExtras.h:702
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::HexagonSubtarget::isTypeForHVX
bool isTypeForHVX(Type *VecTy, bool IncludeBool=false) const
Definition: HexagonSubtarget.cpp:165
llvm::HexagonSubtarget::BankConflictMutation::apply
void apply(ScheduleDAGInstrs *DAG) override
Definition: HexagonSubtarget.cpp:332
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::MVT::isScalableVector
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
Definition: MachineValueType.h:373
llvm::HexagonSubtarget::getHVXElementTypes
ArrayRef< MVT > getHVXElementTypes() const
Definition: HexagonSubtarget.h:283
llvm::EVT::isSimple
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:130
llvm::SDep::isArtificial
bool isArtificial() const
Tests if this is an Order dependence that is marked as "artificial", meaning it isn't necessary for c...
Definition: ScheduleDAG.h:200
llvm::MVT::isValid
bool isValid() const
Return true if this is a valid simple valuetype.
Definition: MachineValueType.h:334
llvm::HexagonSubtarget::getL1CacheLineSize
unsigned getL1CacheLineSize() const
Definition: HexagonSubtarget.cpp:651
CommandLine.h
llvm::HexagonSubtarget::getSMSMutations
void getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
Definition: HexagonSubtarget.cpp:453
llvm::HexagonTargetLowering::getPreferredVectorAction
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
Definition: HexagonISelLowering.cpp:2139
llvm::HexagonSubtarget::UseBSBScheduling
bool UseBSBScheduling
True if the target should use Back-Skip-Back scheduling.
Definition: HexagonSubtarget.h:72
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::SUnit::removePred
void removePred(const SDep &D)
Removes the specified edge as a pred of the current node if it exists.
Definition: ScheduleDAG.cpp:175
TargetMachine.h
llvm::HexagonDisableDuplex
cl::opt< bool > HexagonDisableDuplex
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:370
llvm::HexagonSubtarget::OptLevel
CodeGenOpt::Level OptLevel
Definition: HexagonSubtarget.h:69
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
llvm::EVT::getVectorNumElements
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:309
llvm::SUnit::NodeNum
unsigned NodeNum
Entry # of node in the node vector.
Definition: ScheduleDAG.h:264
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::HexagonSubtarget::enableMachineScheduler
bool enableMachineScheduler() const override
Definition: HexagonSubtarget.cpp:462
llvm::Type::isVectorTy
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:237
EnableBSBSched
static cl::opt< bool > EnableBSBSched("enable-bsb-sched", cl::Hidden, cl::ZeroOrMore, cl::init(true))
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::HexagonSubtarget::useHVXOps
bool useHVXOps() const
Definition: HexagonSubtarget.h:204
llvm::HexagonInstrInfo::getType
uint64_t getType(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:4507
llvm::HexagonSubtarget::isTinyCore
bool isTinyCore() const
Definition: HexagonSubtarget.h:201
HexagonGenSubtargetInfo
llvm::cl::Option::getNumOccurrences
int getNumOccurrences() const
Definition: CommandLine.h:404
llvm::SDep::Output
@ Output
A register output-dependence (aka WAW).
Definition: ScheduleDAG.h:55
llvm::InstrItineraryData::Itineraries
const InstrItinerary * Itineraries
Array of itineraries selected.
Definition: MCInstrItineraries.h:116
HexagonInstrInfo.h
llvm::TargetLoweringBase::TypeWidenVector
@ TypeWidenVector
Definition: TargetLowering.h:214
llvm::HexagonInstrInfo::getBaseAndOffset
MachineOperand * getBaseAndOffset(const MachineInstr &MI, int64_t &Offset, unsigned &AccessSize) const
Definition: HexagonInstrInfo.cpp:3191
Hexagon.h
llvm::HexagonSubtarget::isHVXVectorType
bool isHVXVectorType(MVT VecTy, bool IncludeBool=false) const
Definition: HexagonSubtarget.cpp:139
llvm::SDep::Order
@ Order
Any other ordering dependency.
Definition: ScheduleDAG.h:56
llvm::HexagonSubtarget::getL1PrefetchDistance
unsigned getL1PrefetchDistance() const
Definition: HexagonSubtarget.cpp:655
llvm::cl::ZeroOrMore
@ ZeroOrMore
Definition: CommandLine.h:120
llvm::HexagonSubtarget::getInstrInfo
const HexagonInstrInfo * getInstrInfo() const override
Definition: HexagonSubtarget.h:120
DisableHexagonMISched
static cl::opt< bool > DisableHexagonMISched("disable-hexagon-misched", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon MI Scheduling"))
llvm::HexagonII::TypeS_2op
@ TypeS_2op
Definition: HexagonDepITypes.h:61
llvm::M68kBeads::DReg
@ DReg
Definition: M68kBaseInfo.h:61
llvm::Register::isVirtual
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
llvm::cl::opt< bool >
llvm::SmallSet::count
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:164
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:341
getZeroLatency
static SUnit * getZeroLatency(SUnit *N, SmallVector< SDep, 4 > &Deps)
If the SUnit has a zero latency edge, return the other SUnit.
Definition: HexagonSubtarget.cpp:554
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
llvm::HexagonSubtarget::useAA
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...
Definition: HexagonSubtarget.cpp:381
llvm::find
auto find(R &&Range, const T &Val)
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1567
llvm::HexagonII::TypeALU64
@ TypeALU64
Definition: HexagonDepITypes.h:21
EnableDotCurSched
static cl::opt< bool > EnableDotCurSched("enable-cur-sched", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable the scheduler to generate .cur"))
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::DenseMap< unsigned, unsigned >
llvm::HexagonSubtarget::CallMutation::apply
void apply(ScheduleDAGInstrs *DAG) override
Definition: HexagonSubtarget.cpp:262
llvm::EVT::getEVT
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:558
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::SUnit::getInstr
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
Definition: ScheduleDAG.h:373
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1612
llvm::MVT::getVectorNumElements
unsigned getVectorNumElements() const
Definition: MachineValueType.h:850
HexagonRegisterInfo.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:79
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:860
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::MachineInstr::isPHI
bool isPHI() const
Definition: MachineInstr.h:1255
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:266
llvm::HexagonII::BaseImmOffset
@ BaseImmOffset
Definition: HexagonBaseInfo.h:34
llvm::HexagonSubtarget::usePredicatedCalls
bool usePredicatedCalls() const
Definition: HexagonSubtarget.cpp:468
llvm::HexagonInstrInfo
Definition: HexagonInstrInfo.h:38
llvm::MVT::getVectorVT
static MVT getVectorVT(MVT VT, unsigned NumElements)
Definition: MachineValueType.h:1177
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::Hexagon::CpuTable
static const std::map< std::string, ArchEnum > CpuTable
Definition: HexagonDepArch.h:38
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
this
Analysis the ScalarEvolution expression for r is this
Definition: README.txt:8
llvm::HexagonSubtarget::isHVXElementType
bool isHVXElementType(MVT Ty, bool IncludeBool=false) const
Definition: HexagonSubtarget.cpp:128
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:489
llvm::ScheduleDAG::MF
MachineFunction & MF
Machine function.
Definition: ScheduleDAG.h:560
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::HexagonSubtarget::getPostRAMutations
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
Definition: HexagonSubtarget.cpp:446
llvm::SDep::Barrier
@ Barrier
An unknown scheduling barrier.
Definition: ScheduleDAG.h:69
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:375
llvm::SmallSet::insert
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:180
llvm::FeatureBitset::reset
constexpr FeatureBitset & reset(unsigned I)
Definition: SubtargetFeature.h:71
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SDep
Scheduling dependency.
Definition: ScheduleDAG.h:49
llvm::HexagonSubtarget::UsrOverflowMutation::apply
void apply(ScheduleDAGInstrs *DAG) override
Definition: HexagonSubtarget.cpp:198
OverrideLongCalls
static cl::opt< bool > OverrideLongCalls("hexagon-long-calls", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("If present, forces/disables the use of long calls"))
llvm::MachineInstr::isRegSequence
bool isRegSequence() const
Definition: MachineInstr.h:1283
j
return j(j<< 16)
llvm::ScheduleDAG::SUnits
std::vector< SUnit > SUnits
The scheduling units.
Definition: ScheduleDAG.h:562
std
Definition: BitVector.h:838
llvm::HexagonSubtarget::getRegisterInfo
const HexagonRegisterInfo * getRegisterInfo() const override
Definition: HexagonSubtarget.h:121
llvm::HexagonSubtarget::initializeSubtargetDependencies
HexagonSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
Definition: HexagonSubtarget.cpp:93
llvm::HexagonSubtarget::getTargetLowering
const HexagonTargetLowering * getTargetLowering() const override
Definition: HexagonSubtarget.h:124
EnableTCLatencySched
static cl::opt< bool > EnableTCLatencySched("enable-tc-latency-sched", cl::Hidden, cl::ZeroOrMore, cl::init(false))
llvm::SUnit::setHeightDirty
void setHeightDirty()
Sets a flag in this node to indicate that its stored Height value will require recomputation the next...
Definition: ScheduleDAG.cpp:232
llvm::MachineInstr::mayStore
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:1018
llvm::HexagonII::TypeS_3op
@ TypeS_3op
Definition: HexagonDepITypes.h:62
llvm::SDep::setLatency
void setLatency(unsigned Lat)
Sets the latency for this edge.
Definition: ScheduleDAG.h:147
llvm::ScheduleDAG::TII
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:558
llvm::HexagonSubtarget::useBSBScheduling
bool useBSBScheduling() const
Definition: HexagonSubtarget.h:234
llvm::SUnit::addPred
bool addPred(const SDep &D, bool Required=true)
Adds the specified edge as a pred of the current node if not already.
Definition: ScheduleDAG.cpp:107
llvm::EVT::getVectorElementType
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:301
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:805
llvm::Hexagon_MC::selectHexagonCPU
StringRef selectHexagonCPU(StringRef CPU)
Definition: HexagonMCTargetDesc.cpp:129
MachineScheduler.h
SmallVector.h
llvm::SUnit::isInstr
bool isInstr() const
Returns true if this SUnit refers to a machine instruction as opposed to an SDNode.
Definition: ScheduleDAG.h:362
N
#define N
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:492
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::HexagonInstrInfo::isToBeScheduledASAP
bool isToBeScheduledASAP(const MachineInstr &MI1, const MachineInstr &MI2) const
Definition: HexagonInstrInfo.cpp:2643
llvm::HexagonSubtarget
Definition: HexagonSubtarget.h:43
llvm::HexagonInstrInfo::canExecuteInBundle
bool canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const
Can these instructions execute at the same time in a bundle.
Definition: HexagonInstrInfo.cpp:2986
llvm::SmallSet::clear
void clear()
Definition: SmallSet.h:218
llvm::HexagonInstrInfo::getOperandLatency
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
getOperandLatency - Compute and return the use operand latency of a given pair of def and use.
Definition: HexagonInstrInfo.cpp:4220
MachineOperand.h
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::Hexagon_MC::completeHVXFeatures
FeatureBitset completeHVXFeatures(const FeatureBitset &FB)
Definition: HexagonMCTargetDesc.cpp:419
llvm::SUnit::Preds
SmallVector< SDep, 4 > Preds
All sunit predecessors.
Definition: ScheduleDAG.h:256
llvm::SUnit
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
llvm::cl::desc
Definition: CommandLine.h:414
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:119
EnableCheckBankConflict
static cl::opt< bool > EnableCheckBankConflict("hexagon-check-bank-conflict", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable checking for cache bank conflicts"))
llvm::HexagonSubtarget::hasV60Ops
bool hasV60Ops() const
Definition: HexagonSubtarget.h:153
llvm::HexagonSubtarget::adjustSchedDependency
void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep) const override
Perform target specific adjustments to the latency of a schedule dependency.
Definition: HexagonSubtarget.cpp:389
llvm::HexagonSubtarget::HVXMemLatencyMutation::apply
void apply(ScheduleDAGInstrs *DAG) override
Definition: HexagonSubtarget.cpp:211
llvm::SDep::getLatency
unsigned getLatency() const
Returns the latency value for this edge, which roughly means the minimum number of cycles that must e...
Definition: ScheduleDAG.h:142
EnableSubregLiveness
static cl::opt< bool > EnableSubregLiveness("hexagon-subreg-liveness", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable subregister liveness tracking for Hexagon"))
llvm::HexagonII::TypeM
@ TypeM
Definition: HexagonDepITypes.h:55
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:780
SpecialSubKind::string
@ string
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:289
SmallSet.h