LLVM  15.0.0git
HexagonSubtarget.cpp
Go to the documentation of this file.
1 //===- HexagonSubtarget.cpp - Hexagon Subtarget Information ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the Hexagon specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "HexagonSubtarget.h"
14 #include "Hexagon.h"
15 #include "HexagonInstrInfo.h"
16 #include "HexagonRegisterInfo.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/StringRef.h"
30 #include <algorithm>
31 #include <cassert>
32 #include <map>
33 
34 using namespace llvm;
35 
36 #define DEBUG_TYPE "hexagon-subtarget"
37 
38 #define GET_SUBTARGETINFO_CTOR
39 #define GET_SUBTARGETINFO_TARGET_DESC
40 #include "HexagonGenSubtargetInfo.inc"
41 
42 static cl::opt<bool> EnableBSBSched("enable-bsb-sched", cl::Hidden,
43  cl::init(true));
44 
45 static cl::opt<bool> EnableTCLatencySched("enable-tc-latency-sched", cl::Hidden,
46  cl::init(false));
47 
48 static cl::opt<bool>
49  EnableDotCurSched("enable-cur-sched", cl::Hidden, cl::init(true),
50  cl::desc("Enable the scheduler to generate .cur"));
51 
52 static cl::opt<bool>
53  DisableHexagonMISched("disable-hexagon-misched", cl::Hidden,
54  cl::desc("Disable Hexagon MI Scheduling"));
55 
57  "hexagon-subreg-liveness", cl::Hidden, cl::init(true),
58  cl::desc("Enable subregister liveness tracking for Hexagon"));
59 
61  "hexagon-long-calls", cl::Hidden,
62  cl::desc("If present, forces/disables the use of long calls"));
63 
64 static cl::opt<bool>
65  EnablePredicatedCalls("hexagon-pred-calls", cl::Hidden,
66  cl::desc("Consider calls to be predicable"));
67 
68 static cl::opt<bool> SchedPredsCloser("sched-preds-closer", cl::Hidden,
69  cl::init(true));
70 
71 static cl::opt<bool> SchedRetvalOptimization("sched-retval-optimization",
72  cl::Hidden, cl::init(true));
73 
75  "hexagon-check-bank-conflict", cl::Hidden, cl::init(true),
76  cl::desc("Enable checking for cache bank conflicts"));
77 
79  "force-hvx-float", cl::Hidden,
80  cl::desc(
81  "Enable the code-generation for vector float instructions on v68."));
82 
84  StringRef FS, const TargetMachine &TM)
85  : HexagonGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
86  OptLevel(TM.getOptLevel()),
87  CPUString(std::string(Hexagon_MC::selectHexagonCPU(CPU))),
88  TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)),
89  RegInfo(getHwMode()), TLInfo(TM, *this),
90  InstrItins(getInstrItineraryForCPU(CPUString)) {
92  // Beware of the default constructor of InstrItineraryData: it will
93  // reset all members to 0.
94  assert(InstrItins.Itineraries != nullptr && "InstrItins not initialized");
95 }
96 
99  Optional<Hexagon::ArchEnum> ArchVer = Hexagon::getCpu(CPUString);
100  if (ArchVer)
101  HexagonArchVersion = *ArchVer;
102  else
103  llvm_unreachable("Unrecognized Hexagon processor version");
104 
105  UseHVX128BOps = false;
106  UseHVX64BOps = false;
107  UseAudioOps = false;
108  UseLongCalls = false;
109 
110  SubtargetFeatures Features(FS);
111 
112  // Turn on QFloat if the HVX version is v68+.
113  // The function ParseSubtargetFeatures will set feature bits and initialize
114  // subtarget's variables all in one, so there isn't a good way to preprocess
115  // the feature string, other than by tinkering with it directly.
116  auto IsQFloatFS = [](StringRef F) {
117  return F == "+hvx-qfloat" || F == "-hvx-qfloat";
118  };
119  if (!llvm::count_if(Features.getFeatures(), IsQFloatFS)) {
120  auto getHvxVersion = [&Features](StringRef FS) -> StringRef {
121  for (StringRef F : llvm::reverse(Features.getFeatures())) {
122  if (F.startswith("+hvxv"))
123  return F;
124  }
125  for (StringRef F : llvm::reverse(Features.getFeatures())) {
126  if (F == "-hvx")
127  return StringRef();
128  if (F.startswith("+hvx") || F == "-hvx")
129  return F.take_front(4); // Return "+hvx" or "-hvx".
130  }
131  return StringRef();
132  };
133 
134  bool AddQFloat = false;
135  StringRef HvxVer = getHvxVersion(FS);
136  if (HvxVer.startswith("+hvxv")) {
137  int Ver = 0;
138  if (!HvxVer.drop_front(5).consumeInteger(10, Ver) && Ver >= 68)
139  AddQFloat = true;
140  } else if (HvxVer == "+hvx") {
141  if (hasV68Ops())
142  AddQFloat = true;
143  }
144 
145  if (AddQFloat)
146  Features.AddFeature("+hvx-qfloat");
147  }
148 
149  std::string FeatureString = Features.getString();
150  ParseSubtargetFeatures(CPUString, /*TuneCPU*/ CPUString, FeatureString);
151 
152  // Enable float code generation only if the flag(s) are set and
153  // the feature is enabled. v68 is guarded by additional flags.
154  bool GreaterThanV68 = false;
155  if (useHVXV69Ops())
156  GreaterThanV68 = true;
157 
158  // Support for deprecated qfloat/ieee codegen flags
159  if (!GreaterThanV68) {
161  UseHVXFloatingPoint = true;
162  } else {
163  UseHVXFloatingPoint = true;
164  }
165 
166  if (UseHVXQFloatOps && UseHVXIEEEFPOps && UseHVXFloatingPoint)
167  LLVM_DEBUG(
168  dbgs() << "Behavior is undefined for simultaneous qfloat and ieee hvx codegen...");
169 
171  UseLongCalls = OverrideLongCalls;
172 
174 
175  if (isTinyCore()) {
176  // Tiny core has a single thread, so back-to-back scheduling is enabled by
177  // default.
179  UseBSBScheduling = false;
180  }
181 
182  FeatureBitset FeatureBits = getFeatureBits();
184  setFeatureBits(FeatureBits.reset(Hexagon::FeatureDuplex));
185  setFeatureBits(Hexagon_MC::completeHVXFeatures(FeatureBits));
186 
187  return *this;
188 }
189 
190 bool HexagonSubtarget::isHVXElementType(MVT Ty, bool IncludeBool) const {
191  if (!useHVXOps())
192  return false;
193  if (Ty.isVector())
194  Ty = Ty.getVectorElementType();
195  if (IncludeBool && Ty == MVT::i1)
196  return true;
197  ArrayRef<MVT> ElemTypes = getHVXElementTypes();
198  return llvm::is_contained(ElemTypes, Ty);
199 }
200 
201 bool HexagonSubtarget::isHVXVectorType(MVT VecTy, bool IncludeBool) const {
202  if (!VecTy.isVector() || !useHVXOps() || VecTy.isScalableVector())
203  return false;
204  MVT ElemTy = VecTy.getVectorElementType();
205  if (!IncludeBool && ElemTy == MVT::i1)
206  return false;
207 
208  unsigned HwLen = getVectorLength();
209  unsigned NumElems = VecTy.getVectorNumElements();
210  ArrayRef<MVT> ElemTypes = getHVXElementTypes();
211 
212  if (IncludeBool && ElemTy == MVT::i1) {
213  // Boolean HVX vector types are formed from regular HVX vector types
214  // by replacing the element type with i1.
215  for (MVT T : ElemTypes)
216  if (NumElems * T.getSizeInBits() == 8 * HwLen)
217  return true;
218  return false;
219  }
220 
221  unsigned VecWidth = VecTy.getSizeInBits();
222  if (VecWidth != 8 * HwLen && VecWidth != 16 * HwLen)
223  return false;
224  return llvm::is_contained(ElemTypes, ElemTy);
225 }
226 
227 bool HexagonSubtarget::isTypeForHVX(Type *VecTy, bool IncludeBool) const {
228  if (!VecTy->isVectorTy() || isa<ScalableVectorType>(VecTy))
229  return false;
230  // Avoid types like <2 x i32*>.
231  Type *ScalTy = VecTy->getScalarType();
232  if (!ScalTy->isIntegerTy() &&
233  !(ScalTy->isFloatingPointTy() && useHVXFloatingPoint()))
234  return false;
235  // The given type may be something like <17 x i32>, which is not MVT,
236  // but can be represented as (non-simple) EVT.
237  EVT Ty = EVT::getEVT(VecTy, /*HandleUnknown*/false);
238  if (Ty.getSizeInBits() <= 64 || !Ty.getVectorElementType().isSimple())
239  return false;
240 
241  auto isHvxTy = [this, IncludeBool](MVT SimpleTy) {
242  if (isHVXVectorType(SimpleTy, IncludeBool))
243  return true;
244  auto Action = getTargetLowering()->getPreferredVectorAction(SimpleTy);
245  return Action == TargetLoweringBase::TypeWidenVector;
246  };
247 
248  // Round up EVT to have power-of-2 elements, and keep checking if it
249  // qualifies for HVX, dividing it in half after each step.
250  MVT ElemTy = Ty.getVectorElementType().getSimpleVT();
251  unsigned VecLen = PowerOf2Ceil(Ty.getVectorNumElements());
252  while (ElemTy.getSizeInBits() * VecLen > 64) {
253  MVT SimpleTy = MVT::getVectorVT(ElemTy, VecLen);
254  if (SimpleTy.isValid() && isHvxTy(SimpleTy))
255  return true;
256  VecLen /= 2;
257  }
258 
259  return false;
260 }
261 
263  for (SUnit &SU : DAG->SUnits) {
264  if (!SU.isInstr())
265  continue;
266  SmallVector<SDep, 4> Erase;
267  for (auto &D : SU.Preds)
268  if (D.getKind() == SDep::Output && D.getReg() == Hexagon::USR_OVF)
269  Erase.push_back(D);
270  for (auto &E : Erase)
271  SU.removePred(E);
272  }
273 }
274 
276  for (SUnit &SU : DAG->SUnits) {
277  // Update the latency of chain edges between v60 vector load or store
278  // instructions to be 1. These instruction cannot be scheduled in the
279  // same packet.
280  MachineInstr &MI1 = *SU.getInstr();
281  auto *QII = static_cast<const HexagonInstrInfo*>(DAG->TII);
282  bool IsStoreMI1 = MI1.mayStore();
283  bool IsLoadMI1 = MI1.mayLoad();
284  if (!QII->isHVXVec(MI1) || !(IsStoreMI1 || IsLoadMI1))
285  continue;
286  for (SDep &SI : SU.Succs) {
287  if (SI.getKind() != SDep::Order || SI.getLatency() != 0)
288  continue;
289  MachineInstr &MI2 = *SI.getSUnit()->getInstr();
290  if (!QII->isHVXVec(MI2))
291  continue;
292  if ((IsStoreMI1 && MI2.mayStore()) || (IsLoadMI1 && MI2.mayLoad())) {
293  SI.setLatency(1);
294  SU.setHeightDirty();
295  // Change the dependence in the opposite direction too.
296  for (SDep &PI : SI.getSUnit()->Preds) {
297  if (PI.getSUnit() != &SU || PI.getKind() != SDep::Order)
298  continue;
299  PI.setLatency(1);
300  SI.getSUnit()->setDepthDirty();
301  }
302  }
303  }
304  }
305 }
306 
307 // Check if a call and subsequent A2_tfrpi instructions should maintain
308 // scheduling affinity. We are looking for the TFRI to be consumed in
309 // the next instruction. This should help reduce the instances of
310 // double register pairs being allocated and scheduled before a call
311 // when not used until after the call. This situation is exacerbated
312 // by the fact that we allocate the pair from the callee saves list,
313 // leading to excess spills and restores.
314 bool HexagonSubtarget::CallMutation::shouldTFRICallBind(
315  const HexagonInstrInfo &HII, const SUnit &Inst1,
316  const SUnit &Inst2) const {
317  if (Inst1.getInstr()->getOpcode() != Hexagon::A2_tfrpi)
318  return false;
319 
320  // TypeXTYPE are 64 bit operations.
321  unsigned Type = HII.getType(*Inst2.getInstr());
324 }
325 
327  ScheduleDAGMI *DAG = static_cast<ScheduleDAGMI*>(DAGInstrs);
328  SUnit* LastSequentialCall = nullptr;
329  // Map from virtual register to physical register from the copy.
330  DenseMap<unsigned, unsigned> VRegHoldingReg;
331  // Map from the physical register to the instruction that uses virtual
332  // register. This is used to create the barrier edge.
333  DenseMap<unsigned, SUnit *> LastVRegUse;
334  auto &TRI = *DAG->MF.getSubtarget().getRegisterInfo();
335  auto &HII = *DAG->MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
336 
337  // Currently we only catch the situation when compare gets scheduled
338  // before preceding call.
339  for (unsigned su = 0, e = DAG->SUnits.size(); su != e; ++su) {
340  // Remember the call.
341  if (DAG->SUnits[su].getInstr()->isCall())
342  LastSequentialCall = &DAG->SUnits[su];
343  // Look for a compare that defines a predicate.
344  else if (DAG->SUnits[su].getInstr()->isCompare() && LastSequentialCall)
345  DAG->addEdge(&DAG->SUnits[su], SDep(LastSequentialCall, SDep::Barrier));
346  // Look for call and tfri* instructions.
347  else if (SchedPredsCloser && LastSequentialCall && su > 1 && su < e-1 &&
348  shouldTFRICallBind(HII, DAG->SUnits[su], DAG->SUnits[su+1]))
349  DAG->addEdge(&DAG->SUnits[su], SDep(&DAG->SUnits[su-1], SDep::Barrier));
350  // Prevent redundant register copies due to reads and writes of physical
351  // registers. The original motivation for this was the code generated
352  // between two calls, which are caused both the return value and the
353  // argument for the next call being in %r0.
354  // Example:
355  // 1: <call1>
356  // 2: %vreg = COPY %r0
357  // 3: <use of %vreg>
358  // 4: %r0 = ...
359  // 5: <call2>
360  // The scheduler would often swap 3 and 4, so an additional register is
361  // needed. This code inserts a Barrier dependence between 3 & 4 to prevent
362  // this.
363  // The code below checks for all the physical registers, not just R0/D0/V0.
364  else if (SchedRetvalOptimization) {
365  const MachineInstr *MI = DAG->SUnits[su].getInstr();
366  if (MI->isCopy() &&
367  Register::isPhysicalRegister(MI->getOperand(1).getReg())) {
368  // %vregX = COPY %r0
369  VRegHoldingReg[MI->getOperand(0).getReg()] = MI->getOperand(1).getReg();
370  LastVRegUse.erase(MI->getOperand(1).getReg());
371  } else {
372  for (const MachineOperand &MO : MI->operands()) {
373  if (!MO.isReg())
374  continue;
375  if (MO.isUse() && !MI->isCopy() &&
376  VRegHoldingReg.count(MO.getReg())) {
377  // <use of %vregX>
378  LastVRegUse[VRegHoldingReg[MO.getReg()]] = &DAG->SUnits[su];
379  } else if (MO.isDef() && Register::isPhysicalRegister(MO.getReg())) {
380  for (MCRegAliasIterator AI(MO.getReg(), &TRI, true); AI.isValid();
381  ++AI) {
382  if (LastVRegUse.count(*AI) &&
383  LastVRegUse[*AI] != &DAG->SUnits[su])
384  // %r0 = ...
385  DAG->addEdge(&DAG->SUnits[su], SDep(LastVRegUse[*AI], SDep::Barrier));
386  LastVRegUse.erase(*AI);
387  }
388  }
389  }
390  }
391  }
392  }
393 }
394 
397  return;
398 
399  const auto &HII = static_cast<const HexagonInstrInfo&>(*DAG->TII);
400 
401  // Create artificial edges between loads that could likely cause a bank
402  // conflict. Since such loads would normally not have any dependency
403  // between them, we cannot rely on existing edges.
404  for (unsigned i = 0, e = DAG->SUnits.size(); i != e; ++i) {
405  SUnit &S0 = DAG->SUnits[i];
406  MachineInstr &L0 = *S0.getInstr();
407  if (!L0.mayLoad() || L0.mayStore() ||
409  continue;
410  int64_t Offset0;
411  unsigned Size0;
412  MachineOperand *BaseOp0 = HII.getBaseAndOffset(L0, Offset0, Size0);
413  // Is the access size is longer than the L1 cache line, skip the check.
414  if (BaseOp0 == nullptr || !BaseOp0->isReg() || Size0 >= 32)
415  continue;
416  // Scan only up to 32 instructions ahead (to avoid n^2 complexity).
417  for (unsigned j = i+1, m = std::min(i+32, e); j != m; ++j) {
418  SUnit &S1 = DAG->SUnits[j];
419  MachineInstr &L1 = *S1.getInstr();
420  if (!L1.mayLoad() || L1.mayStore() ||
422  continue;
423  int64_t Offset1;
424  unsigned Size1;
425  MachineOperand *BaseOp1 = HII.getBaseAndOffset(L1, Offset1, Size1);
426  if (BaseOp1 == nullptr || !BaseOp1->isReg() || Size1 >= 32 ||
427  BaseOp0->getReg() != BaseOp1->getReg())
428  continue;
429  // Check bits 3 and 4 of the offset: if they differ, a bank conflict
430  // is unlikely.
431  if (((Offset0 ^ Offset1) & 0x18) != 0)
432  continue;
433  // Bits 3 and 4 are the same, add an artificial edge and set extra
434  // latency.
435  SDep A(&S0, SDep::Artificial);
436  A.setLatency(1);
437  S1.addPred(A, true);
438  }
439  }
440 }
441 
442 /// Enable use of alias analysis during code generation (during MI
443 /// scheduling, DAGCombine, etc.).
445  if (OptLevel != CodeGenOpt::None)
446  return true;
447  return false;
448 }
449 
450 /// Perform target specific adjustments to the latency of a schedule
451 /// dependency.
453  SUnit *Dst, int DstOpIdx,
454  SDep &Dep) const {
455  if (!Src->isInstr() || !Dst->isInstr())
456  return;
457 
458  MachineInstr *SrcInst = Src->getInstr();
459  MachineInstr *DstInst = Dst->getInstr();
460  const HexagonInstrInfo *QII = getInstrInfo();
461 
462  // Instructions with .new operands have zero latency.
463  SmallSet<SUnit *, 4> ExclSrc;
464  SmallSet<SUnit *, 4> ExclDst;
465  if (QII->canExecuteInBundle(*SrcInst, *DstInst) &&
466  isBestZeroLatency(Src, Dst, QII, ExclSrc, ExclDst)) {
467  Dep.setLatency(0);
468  return;
469  }
470 
471  // Set the latency for a copy to zero since we hope that is will get
472  // removed.
473  if (DstInst->isCopy())
474  Dep.setLatency(0);
475 
476  // If it's a REG_SEQUENCE/COPY, use its destination instruction to determine
477  // the correct latency.
478  // If there are multiple uses of the def of COPY/REG_SEQUENCE, set the latency
479  // only if the latencies on all the uses are equal, otherwise set it to
480  // default.
481  if ((DstInst->isRegSequence() || DstInst->isCopy())) {
482  Register DReg = DstInst->getOperand(0).getReg();
483  int DLatency = -1;
484  for (const auto &DDep : Dst->Succs) {
485  MachineInstr *DDst = DDep.getSUnit()->getInstr();
486  int UseIdx = -1;
487  for (unsigned OpNum = 0; OpNum < DDst->getNumOperands(); OpNum++) {
488  const MachineOperand &MO = DDst->getOperand(OpNum);
489  if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == DReg) {
490  UseIdx = OpNum;
491  break;
492  }
493  }
494 
495  if (UseIdx == -1)
496  continue;
497 
498  int Latency = (InstrInfo.getOperandLatency(&InstrItins, *SrcInst, 0,
499  *DDst, UseIdx));
500  // Set DLatency for the first time.
501  DLatency = (DLatency == -1) ? Latency : DLatency;
502 
503  // For multiple uses, if the Latency is different across uses, reset
504  // DLatency.
505  if (DLatency != Latency) {
506  DLatency = -1;
507  break;
508  }
509  }
510 
511  DLatency = std::max(DLatency, 0);
512  Dep.setLatency((unsigned)DLatency);
513  }
514 
515  // Try to schedule uses near definitions to generate .cur.
516  ExclSrc.clear();
517  ExclDst.clear();
518  if (EnableDotCurSched && QII->isToBeScheduledASAP(*SrcInst, *DstInst) &&
519  isBestZeroLatency(Src, Dst, QII, ExclSrc, ExclDst)) {
520  Dep.setLatency(0);
521  return;
522  }
523  int Latency = Dep.getLatency();
524  bool IsArtificial = Dep.isArtificial();
525  Latency = updateLatency(*SrcInst, *DstInst, IsArtificial, Latency);
526  Dep.setLatency(Latency);
527 }
528 
530  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
531  Mutations.push_back(std::make_unique<UsrOverflowMutation>());
532  Mutations.push_back(std::make_unique<HVXMemLatencyMutation>());
533  Mutations.push_back(std::make_unique<BankConflictMutation>());
534 }
535 
537  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
538  Mutations.push_back(std::make_unique<UsrOverflowMutation>());
539  Mutations.push_back(std::make_unique<HVXMemLatencyMutation>());
540 }
541 
542 // Pin the vtable to this file.
543 void HexagonSubtarget::anchor() {}
544 
547  return !DisableHexagonMISched;
548  return true;
549 }
550 
552  return EnablePredicatedCalls;
553 }
554 
555 int HexagonSubtarget::updateLatency(MachineInstr &SrcInst,
556  MachineInstr &DstInst, bool IsArtificial,
557  int Latency) const {
558  if (IsArtificial)
559  return 1;
560  if (!hasV60Ops())
561  return Latency;
562 
563  auto &QII = static_cast<const HexagonInstrInfo &>(*getInstrInfo());
564  // BSB scheduling.
565  if (QII.isHVXVec(SrcInst) || useBSBScheduling())
566  Latency = (Latency + 1) >> 1;
567  return Latency;
568 }
569 
570 void HexagonSubtarget::restoreLatency(SUnit *Src, SUnit *Dst) const {
571  MachineInstr *SrcI = Src->getInstr();
572  for (auto &I : Src->Succs) {
573  if (!I.isAssignedRegDep() || I.getSUnit() != Dst)
574  continue;
575  Register DepR = I.getReg();
576  int DefIdx = -1;
577  for (unsigned OpNum = 0; OpNum < SrcI->getNumOperands(); OpNum++) {
578  const MachineOperand &MO = SrcI->getOperand(OpNum);
579  bool IsSameOrSubReg = false;
580  if (MO.isReg()) {
581  Register MOReg = MO.getReg();
582  if (DepR.isVirtual()) {
583  IsSameOrSubReg = (MOReg == DepR);
584  } else {
585  IsSameOrSubReg = getRegisterInfo()->isSubRegisterEq(DepR, MOReg);
586  }
587  if (MO.isDef() && IsSameOrSubReg)
588  DefIdx = OpNum;
589  }
590  }
591  assert(DefIdx >= 0 && "Def Reg not found in Src MI");
592  MachineInstr *DstI = Dst->getInstr();
593  SDep T = I;
594  for (unsigned OpNum = 0; OpNum < DstI->getNumOperands(); OpNum++) {
595  const MachineOperand &MO = DstI->getOperand(OpNum);
596  if (MO.isReg() && MO.isUse() && MO.getReg() == DepR) {
597  int Latency = (InstrInfo.getOperandLatency(&InstrItins, *SrcI,
598  DefIdx, *DstI, OpNum));
599 
600  // For some instructions (ex: COPY), we might end up with < 0 latency
601  // as they don't have any Itinerary class associated with them.
602  Latency = std::max(Latency, 0);
603  bool IsArtificial = I.isArtificial();
604  Latency = updateLatency(*SrcI, *DstI, IsArtificial, Latency);
605  I.setLatency(Latency);
606  }
607  }
608 
609  // Update the latency of opposite edge too.
610  T.setSUnit(Src);
611  auto F = find(Dst->Preds, T);
612  assert(F != Dst->Preds.end());
613  F->setLatency(I.getLatency());
614  }
615 }
616 
617 /// Change the latency between the two SUnits.
618 void HexagonSubtarget::changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat)
619  const {
620  for (auto &I : Src->Succs) {
621  if (!I.isAssignedRegDep() || I.getSUnit() != Dst)
622  continue;
623  SDep T = I;
624  I.setLatency(Lat);
625 
626  // Update the latency of opposite edge too.
627  T.setSUnit(Src);
628  auto F = find(Dst->Preds, T);
629  assert(F != Dst->Preds.end());
630  F->setLatency(Lat);
631  }
632 }
633 
634 /// If the SUnit has a zero latency edge, return the other SUnit.
636  for (auto &I : Deps)
637  if (I.isAssignedRegDep() && I.getLatency() == 0 &&
638  !I.getSUnit()->getInstr()->isPseudo())
639  return I.getSUnit();
640  return nullptr;
641 }
642 
643 // Return true if these are the best two instructions to schedule
644 // together with a zero latency. Only one dependence should have a zero
645 // latency. If there are multiple choices, choose the best, and change
646 // the others, if needed.
647 bool HexagonSubtarget::isBestZeroLatency(SUnit *Src, SUnit *Dst,
648  const HexagonInstrInfo *TII, SmallSet<SUnit*, 4> &ExclSrc,
649  SmallSet<SUnit*, 4> &ExclDst) const {
650  MachineInstr &SrcInst = *Src->getInstr();
651  MachineInstr &DstInst = *Dst->getInstr();
652 
653  // Ignore Boundary SU nodes as these have null instructions.
654  if (Dst->isBoundaryNode())
655  return false;
656 
657  if (SrcInst.isPHI() || DstInst.isPHI())
658  return false;
659 
660  if (!TII->isToBeScheduledASAP(SrcInst, DstInst) &&
661  !TII->canExecuteInBundle(SrcInst, DstInst))
662  return false;
663 
664  // The architecture doesn't allow three dependent instructions in the same
665  // packet. So, if the destination has a zero latency successor, then it's
666  // not a candidate for a zero latency predecessor.
667  if (getZeroLatency(Dst, Dst->Succs) != nullptr)
668  return false;
669 
670  // Check if the Dst instruction is the best candidate first.
671  SUnit *Best = nullptr;
672  SUnit *DstBest = nullptr;
673  SUnit *SrcBest = getZeroLatency(Dst, Dst->Preds);
674  if (SrcBest == nullptr || Src->NodeNum >= SrcBest->NodeNum) {
675  // Check that Src doesn't have a better candidate.
676  DstBest = getZeroLatency(Src, Src->Succs);
677  if (DstBest == nullptr || Dst->NodeNum <= DstBest->NodeNum)
678  Best = Dst;
679  }
680  if (Best != Dst)
681  return false;
682 
683  // The caller frequently adds the same dependence twice. If so, then
684  // return true for this case too.
685  if ((Src == SrcBest && Dst == DstBest ) ||
686  (SrcBest == nullptr && Dst == DstBest) ||
687  (Src == SrcBest && Dst == nullptr))
688  return true;
689 
690  // Reassign the latency for the previous bests, which requires setting
691  // the dependence edge in both directions.
692  if (SrcBest != nullptr) {
693  if (!hasV60Ops())
694  changeLatency(SrcBest, Dst, 1);
695  else
696  restoreLatency(SrcBest, Dst);
697  }
698  if (DstBest != nullptr) {
699  if (!hasV60Ops())
700  changeLatency(Src, DstBest, 1);
701  else
702  restoreLatency(Src, DstBest);
703  }
704 
705  // Attempt to find another opprotunity for zero latency in a different
706  // dependence.
707  if (SrcBest && DstBest)
708  // If there is an edge from SrcBest to DstBst, then try to change that
709  // to 0 now.
710  changeLatency(SrcBest, DstBest, 0);
711  else if (DstBest) {
712  // Check if the previous best destination instruction has a new zero
713  // latency dependence opportunity.
714  ExclSrc.insert(Src);
715  for (auto &I : DstBest->Preds)
716  if (ExclSrc.count(I.getSUnit()) == 0 &&
717  isBestZeroLatency(I.getSUnit(), DstBest, TII, ExclSrc, ExclDst))
718  changeLatency(I.getSUnit(), DstBest, 0);
719  } else if (SrcBest) {
720  // Check if previous best source instruction has a new zero latency
721  // dependence opportunity.
722  ExclDst.insert(Dst);
723  for (auto &I : SrcBest->Succs)
724  if (ExclDst.count(I.getSUnit()) == 0 &&
725  isBestZeroLatency(SrcBest, I.getSUnit(), TII, ExclSrc, ExclDst))
726  changeLatency(SrcBest, I.getSUnit(), 0);
727  }
728 
729  return true;
730 }
731 
733  return 32;
734 }
735 
737  return 32;
738 }
739 
741  return EnableSubregLiveness;
742 }
i
i
Definition: README.txt:29
HexagonMCTargetDesc.h
llvm::HexagonSubtarget::hasV68Ops
bool hasV68Ops() const
Definition: HexagonSubtarget.h:189
llvm::HexagonSubtarget::getVectorLength
unsigned getVectorLength() const
Definition: HexagonSubtarget.h:295
llvm::cl::Option::getPosition
unsigned getPosition() const
Definition: CommandLine.h:298
llvm::HexagonSubtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
llvm::StringRef::startswith
LLVM_NODISCARD bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:290
llvm::MVT::getVectorElementType
MVT getVectorElementType() const
Definition: MachineValueType.h:528
ScheduleDAG.h
SchedRetvalOptimization
static cl::opt< bool > SchedRetvalOptimization("sched-retval-optimization", cl::Hidden, cl::init(true))
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
MachineInstr.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
SchedPredsCloser
static cl::opt< bool > SchedPredsCloser("sched-preds-closer", cl::Hidden, cl::init(true))
llvm::SDep::Artificial
@ Artificial
Arbitrary strong DAG edge (no real dependence).
Definition: ScheduleDAG.h:72
llvm::Latency
@ Latency
Definition: SIMachineScheduler.h:34
T
StringRef.h
ScheduleDAGInstrs.h
llvm::MachineInstr::mayLoad
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:1012
llvm::SubtargetFeatures::AddFeature
void AddFeature(StringRef String, bool Enable=true)
Adds Features.
Definition: SubtargetFeature.cpp:37
llvm::Type::getScalarType
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition: Type.h:309
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::HexagonSubtarget::HexagonSubtarget
HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM)
Definition: HexagonSubtarget.cpp:83
llvm::MVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: MachineValueType.h:374
llvm::HexagonSubtarget::useHVXFloatingPoint
bool useHVXFloatingPoint() const
Definition: HexagonSubtarget.h:221
HexagonSubtarget.h
ErrorHandling.h
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::Hexagon_MC::addArchSubtarget
void addArchSubtarget(MCSubtargetInfo const *STI, StringRef FS)
Definition: HexagonMCTargetDesc.cpp:549
llvm::HexagonInstrInfo::getAddrMode
unsigned getAddrMode(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:3288
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:125
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::erase
bool erase(const KeyT &Val)
Definition: DenseMap.h:304
llvm::ScheduleDAGInstrs::addEdge
bool addEdge(SUnit *SuccSU, const SDep &PredDep)
Add a DAG edge to the given SU with the given predecessor dependence data.
Definition: ScheduleDAGInstrs.cpp:1195
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::reverse
auto reverse(ContainerTy &&C, std::enable_if_t< has_rbegin< ContainerTy >::value > *=nullptr)
Definition: STLExtras.h:380
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:136
llvm::SUnit::Succs
SmallVector< SDep, 4 > Succs
All sunit successors.
Definition: ScheduleDAG.h:257
llvm::Optional
Definition: APInt.h:33
llvm::HexagonSubtarget::HexagonArchVersion
Hexagon::ArchEnum HexagonArchVersion
Definition: HexagonSubtarget.h:71
llvm::DenseMapBase::count
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:147
llvm::HexagonSubtarget::enableSubRegLiveness
bool enableSubRegLiveness() const override
Definition: HexagonSubtarget.cpp:740
llvm::MachineInstr::isCopy
bool isCopy() const
Definition: MachineInstr.h:1292
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
EnableCheckBankConflict
static cl::opt< bool > EnableCheckBankConflict("hexagon-check-bank-conflict", cl::Hidden, cl::init(true), cl::desc("Enable checking for cache bank conflicts"))
STLExtras.h
llvm::PowerOf2Ceil
uint64_t PowerOf2Ceil(uint64_t A)
Returns the power of two which is greater than or equal to the given value.
Definition: MathExtras.h:729
llvm::Type::isFloatingPointTy
bool isFloatingPointTy() const
Return true if this is one of the six floating-point types.
Definition: Type.h:163
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::count_if
auto count_if(R &&Range, UnaryPredicate P)
Wrapper function around std::count_if to count the number of times an element satisfying a given pred...
Definition: STLExtras.h:1716
llvm::HexagonSubtarget::isTypeForHVX
bool isTypeForHVX(Type *VecTy, bool IncludeBool=false) const
Definition: HexagonSubtarget.cpp:227
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::HexagonSubtarget::BankConflictMutation::apply
void apply(ScheduleDAGInstrs *DAG) override
Definition: HexagonSubtarget.cpp:395
F
#define F(x, y, z)
Definition: MD5.cpp:55
EnableV68FloatCodeGen
static cl::opt< bool > EnableV68FloatCodeGen("force-hvx-float", cl::Hidden, cl::desc("Enable the code-generation for vector float instructions on v68."))
llvm::HexagonSubtarget::useHVXV69Ops
bool useHVXV69Ops() const
Definition: HexagonSubtarget.h:243
llvm::MVT::isScalableVector
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
Definition: MachineValueType.h:381
llvm::HexagonSubtarget::getHVXElementTypes
ArrayRef< MVT > getHVXElementTypes() const
Definition: HexagonSubtarget.h:304
llvm::EVT::isSimple
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:129
llvm::SDep::isArtificial
bool isArtificial() const
Tests if this is an Order dependence that is marked as "artificial", meaning it isn't necessary for c...
Definition: ScheduleDAG.h:200
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::MVT::isValid
bool isValid() const
Return true if this is a valid simple valuetype.
Definition: MachineValueType.h:342
llvm::HexagonSubtarget::getL1CacheLineSize
unsigned getL1CacheLineSize() const
Definition: HexagonSubtarget.cpp:732
CommandLine.h
llvm::HexagonSubtarget::getSMSMutations
void getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
Definition: HexagonSubtarget.cpp:536
llvm::HexagonTargetLowering::getPreferredVectorAction
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
Definition: HexagonISelLowering.cpp:2150
llvm::HexagonSubtarget::UseBSBScheduling
bool UseBSBScheduling
True if the target should use Back-Skip-Back scheduling.
Definition: HexagonSubtarget.h:76
llvm::MVT::i1
@ i1
Definition: MachineValueType.h:43
llvm::SUnit::removePred
void removePred(const SDep &D)
Removes the specified edge as a pred of the current node if it exists.
Definition: ScheduleDAG.cpp:175
TargetMachine.h
llvm::HexagonDisableDuplex
cl::opt< bool > HexagonDisableDuplex
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:369
llvm::HexagonSubtarget::OptLevel
CodeGenOpt::Level OptLevel
Definition: HexagonSubtarget.h:73
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:501
llvm::EVT::getVectorNumElements
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:308
llvm::SUnit::NodeNum
unsigned NodeNum
Entry # of node in the node vector.
Definition: ScheduleDAG.h:264
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::HexagonSubtarget::enableMachineScheduler
bool enableMachineScheduler() const override
Definition: HexagonSubtarget.cpp:545
llvm::SubtargetFeatures::getFeatures
const std::vector< std::string > & getFeatures() const
Returns the vector of individual subtarget features.
Definition: SubtargetFeature.h:196
llvm::SubtargetFeatures
Manages the enabling and disabling of subtarget specific features.
Definition: SubtargetFeature.h:183
llvm::Type::isVectorTy
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:227
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::HexagonSubtarget::useHVXOps
bool useHVXOps() const
Definition: HexagonSubtarget.h:222
EnableDotCurSched
static cl::opt< bool > EnableDotCurSched("enable-cur-sched", cl::Hidden, cl::init(true), cl::desc("Enable the scheduler to generate .cur"))
llvm::HexagonInstrInfo::getType
uint64_t getType(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:4624
llvm::HexagonSubtarget::isTinyCore
bool isTinyCore() const
Definition: HexagonSubtarget.h:214
HexagonGenSubtargetInfo
llvm::cl::Option::getNumOccurrences
int getNumOccurrences() const
Definition: CommandLine.h:395
llvm::SDep::Output
@ Output
A register output-dependence (aka WAW).
Definition: ScheduleDAG.h:55
llvm::InstrItineraryData::Itineraries
const InstrItinerary * Itineraries
Array of itineraries selected.
Definition: MCInstrItineraries.h:116
HexagonInstrInfo.h
llvm::TargetLoweringBase::TypeWidenVector
@ TypeWidenVector
Definition: TargetLowering.h:213
llvm::HexagonInstrInfo::getBaseAndOffset
MachineOperand * getBaseAndOffset(const MachineInstr &MI, int64_t &Offset, unsigned &AccessSize) const
Definition: HexagonInstrInfo.cpp:3297
Hexagon.h
llvm::HexagonSubtarget::isHVXVectorType
bool isHVXVectorType(MVT VecTy, bool IncludeBool=false) const
Definition: HexagonSubtarget.cpp:201
llvm::SDep::Order
@ Order
Any other ordering dependency.
Definition: ScheduleDAG.h:56
llvm::HexagonSubtarget::getL1PrefetchDistance
unsigned getL1PrefetchDistance() const
Definition: HexagonSubtarget.cpp:736
EnableBSBSched
static cl::opt< bool > EnableBSBSched("enable-bsb-sched", cl::Hidden, cl::init(true))
llvm::Type::isIntegerTy
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:191
llvm::HexagonSubtarget::getInstrInfo
const HexagonInstrInfo * getInstrInfo() const override
Definition: HexagonSubtarget.h:124
llvm::HexagonII::TypeS_2op
@ TypeS_2op
Definition: HexagonDepITypes.h:61
llvm::Register::isVirtual
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
llvm::SubtargetFeatures::getString
std::string getString() const
Returns features as a string.
Definition: SubtargetFeature.cpp:50
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::cl::opt< bool >
OverrideLongCalls
static cl::opt< bool > OverrideLongCalls("hexagon-long-calls", cl::Hidden, cl::desc("If present, forces/disables the use of long calls"))
llvm::SmallSet::count
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:166
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:340
getZeroLatency
static SUnit * getZeroLatency(SUnit *N, SmallVector< SDep, 4 > &Deps)
If the SUnit has a zero latency edge, return the other SUnit.
Definition: HexagonSubtarget.cpp:635
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
llvm::HexagonSubtarget::useAA
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...
Definition: HexagonSubtarget.cpp:444
llvm::find
auto find(R &&Range, const T &Val)
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1637
llvm::HexagonII::TypeALU64
@ TypeALU64
Definition: HexagonDepITypes.h:21
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::DenseMap< unsigned, unsigned >
llvm::HexagonSubtarget::CallMutation::apply
void apply(ScheduleDAGInstrs *DAG) override
Definition: HexagonSubtarget.cpp:326
llvm::EVT::getEVT
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:573
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::SUnit::getInstr
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
Definition: ScheduleDAG.h:373
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1682
llvm::MVT::getVectorNumElements
unsigned getVectorNumElements() const
Definition: MachineValueType.h:869
HexagonRegisterInfo.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::X86AS::FS
@ FS
Definition: X86.h:192
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:883
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::Hexagon::getCpu
Optional< Hexagon::ArchEnum > getCpu(StringRef CPU)
Definition: HexagonDepArch.h:21
llvm::MachineInstr::isPHI
bool isPHI() const
Definition: MachineInstr.h:1256
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:271
llvm::HexagonII::BaseImmOffset
@ BaseImmOffset
Definition: HexagonBaseInfo.h:34
llvm::HexagonSubtarget::usePredicatedCalls
bool usePredicatedCalls() const
Definition: HexagonSubtarget.cpp:551
llvm::HexagonInstrInfo
Definition: HexagonInstrInfo.h:38
llvm::MVT::getVectorVT
static MVT getVectorVT(MVT VT, unsigned NumElements)
Definition: MachineValueType.h:1216
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
this
Analysis the ScalarEvolution expression for r is this
Definition: README.txt:8
llvm::HexagonSubtarget::isHVXElementType
bool isHVXElementType(MVT Ty, bool IncludeBool=false) const
Definition: HexagonSubtarget.cpp:190
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:491
llvm::ScheduleDAG::MF
MachineFunction & MF
Machine function.
Definition: ScheduleDAG.h:560
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::HexagonSubtarget::getPostRAMutations
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
Definition: HexagonSubtarget.cpp:529
llvm::SDep::Barrier
@ Barrier
An unknown scheduling barrier.
Definition: ScheduleDAG.h:69
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:374
llvm::StringRef::consumeInteger
std::enable_if_t< std::numeric_limits< T >::is_signed, bool > consumeInteger(unsigned Radix, T &Result)
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:548
llvm::SmallSet::insert
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:182
llvm::FeatureBitset::reset
constexpr FeatureBitset & reset(unsigned I)
Definition: SubtargetFeature.h:71
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
DisableHexagonMISched
static cl::opt< bool > DisableHexagonMISched("disable-hexagon-misched", cl::Hidden, cl::desc("Disable Hexagon MI Scheduling"))
llvm::SDep
Scheduling dependency.
Definition: ScheduleDAG.h:49
llvm::HexagonSubtarget::UsrOverflowMutation::apply
void apply(ScheduleDAGInstrs *DAG) override
Definition: HexagonSubtarget.cpp:262
EnableTCLatencySched
static cl::opt< bool > EnableTCLatencySched("enable-tc-latency-sched", cl::Hidden, cl::init(false))
llvm::MachineInstr::isRegSequence
bool isRegSequence() const
Definition: MachineInstr.h:1284
j
return j(j<< 16)
llvm::ScheduleDAG::SUnits
std::vector< SUnit > SUnits
The scheduling units.
Definition: ScheduleDAG.h:562
std
Definition: BitVector.h:851
llvm::StringRef::drop_front
LLVM_NODISCARD StringRef drop_front(size_t N=1) const
Return a StringRef equal to 'this' but with the first N elements dropped.
Definition: StringRef.h:657
llvm::HexagonSubtarget::getRegisterInfo
const HexagonRegisterInfo * getRegisterInfo() const override
Definition: HexagonSubtarget.h:125
llvm::HexagonSubtarget::initializeSubtargetDependencies
HexagonSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
Definition: HexagonSubtarget.cpp:98
llvm::HexagonSubtarget::getTargetLowering
const HexagonTargetLowering * getTargetLowering() const override
Definition: HexagonSubtarget.h:128
llvm::SUnit::setHeightDirty
void setHeightDirty()
Sets a flag in this node to indicate that its stored Height value will require recomputation the next...
Definition: ScheduleDAG.cpp:232
llvm::MachineInstr::mayStore
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:1025
llvm::HexagonII::TypeS_3op
@ TypeS_3op
Definition: HexagonDepITypes.h:62
llvm::SDep::setLatency
void setLatency(unsigned Lat)
Sets the latency for this edge.
Definition: ScheduleDAG.h:147
llvm::ScheduleDAG::TII
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:558
llvm::HexagonSubtarget::useBSBScheduling
bool useBSBScheduling() const
Definition: HexagonSubtarget.h:255
llvm::SUnit::addPred
bool addPred(const SDep &D, bool Required=true)
Adds the specified edge as a pred of the current node if not already.
Definition: ScheduleDAG.cpp:107
EnablePredicatedCalls
static cl::opt< bool > EnablePredicatedCalls("hexagon-pred-calls", cl::Hidden, cl::desc("Consider calls to be predicable"))
EnableSubregLiveness
static cl::opt< bool > EnableSubregLiveness("hexagon-subreg-liveness", cl::Hidden, cl::init(true), cl::desc("Enable subregister liveness tracking for Hexagon"))
llvm::EVT::getVectorElementType
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:300
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:813
llvm::Hexagon_MC::selectHexagonCPU
StringRef selectHexagonCPU(StringRef CPU)
Definition: HexagonMCTargetDesc.cpp:140
MachineScheduler.h
SmallVector.h
llvm::SUnit::isInstr
bool isInstr() const
Returns true if this SUnit refers to a machine instruction as opposed to an SDNode.
Definition: ScheduleDAG.h:362
N
#define N
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:494
llvm::HexagonInstrInfo::isToBeScheduledASAP
bool isToBeScheduledASAP(const MachineInstr &MI1, const MachineInstr &MI2) const
Definition: HexagonInstrInfo.cpp:2722
llvm::HexagonSubtarget
Definition: HexagonSubtarget.h:43
llvm::HexagonInstrInfo::canExecuteInBundle
bool canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const
Can these instructions execute at the same time in a bundle.
Definition: HexagonInstrInfo.cpp:3092
llvm::SmallSet::clear
void clear()
Definition: SmallSet.h:220
llvm::HexagonInstrInfo::getOperandLatency
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
getOperandLatency - Compute and return the use operand latency of a given pair of def and use.
Definition: HexagonInstrInfo.cpp:4334
MachineOperand.h
llvm::M68kBeads::DReg
@ DReg
Definition: M68kBaseInfo.h:61
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::Hexagon_MC::completeHVXFeatures
FeatureBitset completeHVXFeatures(const FeatureBitset &FB)
Definition: HexagonMCTargetDesc.cpp:439
llvm::SUnit::Preds
SmallVector< SDep, 4 > Preds
All sunit predecessors.
Definition: ScheduleDAG.h:256
llvm::SUnit
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
llvm::cl::desc
Definition: CommandLine.h:405
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:119
llvm::HexagonSubtarget::hasV60Ops
bool hasV60Ops() const
Definition: HexagonSubtarget.h:159
llvm::HexagonSubtarget::adjustSchedDependency
void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep) const override
Perform target specific adjustments to the latency of a schedule dependency.
Definition: HexagonSubtarget.cpp:452
llvm::HexagonSubtarget::HVXMemLatencyMutation::apply
void apply(ScheduleDAGInstrs *DAG) override
Definition: HexagonSubtarget.cpp:275
llvm::SDep::getLatency
unsigned getLatency() const
Returns the latency value for this edge, which roughly means the minimum number of cycles that must e...
Definition: ScheduleDAG.h:142
llvm::HexagonII::TypeM
@ TypeM
Definition: HexagonDepITypes.h:55
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:788
SpecialSubKind::string
@ string
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:288
SmallSet.h