LLVM  9.0.0svn
HexagonInstrInfo.cpp
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1 //===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Hexagon implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "HexagonInstrInfo.h"
14 #include "Hexagon.h"
15 #include "HexagonFrameLowering.h"
17 #include "HexagonRegisterInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringRef.h"
41 #include "llvm/IR/DebugLoc.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCInstrDesc.h"
45 #include "llvm/MC/MCRegisterInfo.h"
48 #include "llvm/Support/Debug.h"
54 #include <cassert>
55 #include <cctype>
56 #include <cstdint>
57 #include <cstring>
58 #include <iterator>
59 #include <string>
60 #include <utility>
61 
62 using namespace llvm;
63 
64 #define DEBUG_TYPE "hexagon-instrinfo"
65 
66 #define GET_INSTRINFO_CTOR_DTOR
67 #define GET_INSTRMAP_INFO
69 #include "HexagonGenDFAPacketizer.inc"
70 #include "HexagonGenInstrInfo.inc"
71 
72 cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
73  cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
74  "packetization boundary."));
75 
76 static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
77  cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"));
78 
79 static cl::opt<bool> DisableNVSchedule("disable-hexagon-nv-schedule",
81  cl::desc("Disable schedule adjustment for new value stores."));
82 
84  "enable-timing-class-latency", cl::Hidden, cl::init(false),
85  cl::desc("Enable timing class latency"));
86 
88  "enable-alu-forwarding", cl::Hidden, cl::init(true),
89  cl::desc("Enable vec alu forwarding"));
90 
92  "enable-acc-forwarding", cl::Hidden, cl::init(true),
93  cl::desc("Enable vec acc forwarding"));
94 
95 static cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large",
96  cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"));
97 
98 static cl::opt<bool> UseDFAHazardRec("dfa-hazard-rec",
100  cl::desc("Use the DFA based hazard recognizer."));
101 
102 /// Constants for Hexagon instructions.
103 const int Hexagon_MEMW_OFFSET_MAX = 4095;
104 const int Hexagon_MEMW_OFFSET_MIN = -4096;
105 const int Hexagon_MEMD_OFFSET_MAX = 8191;
106 const int Hexagon_MEMD_OFFSET_MIN = -8192;
107 const int Hexagon_MEMH_OFFSET_MAX = 2047;
108 const int Hexagon_MEMH_OFFSET_MIN = -2048;
109 const int Hexagon_MEMB_OFFSET_MAX = 1023;
110 const int Hexagon_MEMB_OFFSET_MIN = -1024;
111 const int Hexagon_ADDI_OFFSET_MAX = 32767;
112 const int Hexagon_ADDI_OFFSET_MIN = -32768;
113 
114 // Pin the vtable to this file.
115 void HexagonInstrInfo::anchor() {}
116 
118  : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
119  Subtarget(ST) {}
120 
121 static bool isIntRegForSubInst(unsigned Reg) {
122  return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
123  (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
124 }
125 
126 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) {
127  return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) &&
128  isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi));
129 }
130 
131 /// Calculate number of instructions excluding the debug instructions.
134  unsigned Count = 0;
135  for (; MIB != MIE; ++MIB) {
136  if (!MIB->isDebugInstr())
137  ++Count;
138  }
139  return Count;
140 }
141 
142 /// Find the hardware loop instruction used to set-up the specified loop.
143 /// On Hexagon, we have two instructions used to set-up the hardware loop
144 /// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
145 /// to indicate the end of a loop.
147  unsigned EndLoopOp, MachineBasicBlock *TargetBB,
148  SmallPtrSet<MachineBasicBlock *, 8> &Visited) const {
149  unsigned LOOPi;
150  unsigned LOOPr;
151  if (EndLoopOp == Hexagon::ENDLOOP0) {
152  LOOPi = Hexagon::J2_loop0i;
153  LOOPr = Hexagon::J2_loop0r;
154  } else { // EndLoopOp == Hexagon::EndLOOP1
155  LOOPi = Hexagon::J2_loop1i;
156  LOOPr = Hexagon::J2_loop1r;
157  }
158 
159  // The loop set-up instruction will be in a predecessor block
160  for (MachineBasicBlock *PB : BB->predecessors()) {
161  // If this has been visited, already skip it.
162  if (!Visited.insert(PB).second)
163  continue;
164  if (PB == BB)
165  continue;
166  for (auto I = PB->instr_rbegin(), E = PB->instr_rend(); I != E; ++I) {
167  unsigned Opc = I->getOpcode();
168  if (Opc == LOOPi || Opc == LOOPr)
169  return &*I;
170  // We've reached a different loop, which means the loop01 has been
171  // removed.
172  if (Opc == EndLoopOp && I->getOperand(0).getMBB() != TargetBB)
173  return nullptr;
174  }
175  // Check the predecessors for the LOOP instruction.
176  if (MachineInstr *Loop = findLoopInstr(PB, EndLoopOp, TargetBB, Visited))
177  return Loop;
178  }
179  return nullptr;
180 }
181 
182 /// Gather register def/uses from MI.
183 /// This treats possible (predicated) defs as actually happening ones
184 /// (conservatively).
185 static inline void parseOperands(const MachineInstr &MI,
187  Defs.clear();
188  Uses.clear();
189 
190  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
191  const MachineOperand &MO = MI.getOperand(i);
192 
193  if (!MO.isReg())
194  continue;
195 
196  unsigned Reg = MO.getReg();
197  if (!Reg)
198  continue;
199 
200  if (MO.isUse())
201  Uses.push_back(MO.getReg());
202 
203  if (MO.isDef())
204  Defs.push_back(MO.getReg());
205  }
206 }
207 
208 // Position dependent, so check twice for swap.
209 static bool isDuplexPairMatch(unsigned Ga, unsigned Gb) {
210  switch (Ga) {
212  default:
213  return false;
214  case HexagonII::HSIG_L1:
215  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
216  case HexagonII::HSIG_L2:
217  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
218  Gb == HexagonII::HSIG_A);
219  case HexagonII::HSIG_S1:
220  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
221  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_A);
222  case HexagonII::HSIG_S2:
223  return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
224  Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 ||
225  Gb == HexagonII::HSIG_A);
226  case HexagonII::HSIG_A:
227  return (Gb == HexagonII::HSIG_A);
229  return (Gb == HexagonII::HSIG_Compound);
230  }
231  return false;
232 }
233 
234 /// isLoadFromStackSlot - If the specified machine instruction is a direct
235 /// load from a stack slot, return the virtual or physical register number of
236 /// the destination along with the FrameIndex of the loaded stack slot. If
237 /// not, return 0. This predicate must return 0 if the instruction has
238 /// any side effects other than loading from the stack slot.
240  int &FrameIndex) const {
241  switch (MI.getOpcode()) {
242  default:
243  break;
244  case Hexagon::L2_loadri_io:
245  case Hexagon::L2_loadrd_io:
246  case Hexagon::V6_vL32b_ai:
247  case Hexagon::V6_vL32b_nt_ai:
248  case Hexagon::V6_vL32Ub_ai:
249  case Hexagon::LDriw_pred:
250  case Hexagon::LDriw_ctr:
251  case Hexagon::PS_vloadrq_ai:
252  case Hexagon::PS_vloadrw_ai:
253  case Hexagon::PS_vloadrw_nt_ai: {
254  const MachineOperand OpFI = MI.getOperand(1);
255  if (!OpFI.isFI())
256  return 0;
257  const MachineOperand OpOff = MI.getOperand(2);
258  if (!OpOff.isImm() || OpOff.getImm() != 0)
259  return 0;
260  FrameIndex = OpFI.getIndex();
261  return MI.getOperand(0).getReg();
262  }
263 
264  case Hexagon::L2_ploadrit_io:
265  case Hexagon::L2_ploadrif_io:
266  case Hexagon::L2_ploadrdt_io:
267  case Hexagon::L2_ploadrdf_io: {
268  const MachineOperand OpFI = MI.getOperand(2);
269  if (!OpFI.isFI())
270  return 0;
271  const MachineOperand OpOff = MI.getOperand(3);
272  if (!OpOff.isImm() || OpOff.getImm() != 0)
273  return 0;
274  FrameIndex = OpFI.getIndex();
275  return MI.getOperand(0).getReg();
276  }
277  }
278 
279  return 0;
280 }
281 
282 /// isStoreToStackSlot - If the specified machine instruction is a direct
283 /// store to a stack slot, return the virtual or physical register number of
284 /// the source reg along with the FrameIndex of the loaded stack slot. If
285 /// not, return 0. This predicate must return 0 if the instruction has
286 /// any side effects other than storing to the stack slot.
288  int &FrameIndex) const {
289  switch (MI.getOpcode()) {
290  default:
291  break;
292  case Hexagon::S2_storerb_io:
293  case Hexagon::S2_storerh_io:
294  case Hexagon::S2_storeri_io:
295  case Hexagon::S2_storerd_io:
296  case Hexagon::V6_vS32b_ai:
297  case Hexagon::V6_vS32Ub_ai:
298  case Hexagon::STriw_pred:
299  case Hexagon::STriw_ctr:
300  case Hexagon::PS_vstorerq_ai:
301  case Hexagon::PS_vstorerw_ai: {
302  const MachineOperand &OpFI = MI.getOperand(0);
303  if (!OpFI.isFI())
304  return 0;
305  const MachineOperand &OpOff = MI.getOperand(1);
306  if (!OpOff.isImm() || OpOff.getImm() != 0)
307  return 0;
308  FrameIndex = OpFI.getIndex();
309  return MI.getOperand(2).getReg();
310  }
311 
312  case Hexagon::S2_pstorerbt_io:
313  case Hexagon::S2_pstorerbf_io:
314  case Hexagon::S2_pstorerht_io:
315  case Hexagon::S2_pstorerhf_io:
316  case Hexagon::S2_pstorerit_io:
317  case Hexagon::S2_pstorerif_io:
318  case Hexagon::S2_pstorerdt_io:
319  case Hexagon::S2_pstorerdf_io: {
320  const MachineOperand &OpFI = MI.getOperand(1);
321  if (!OpFI.isFI())
322  return 0;
323  const MachineOperand &OpOff = MI.getOperand(2);
324  if (!OpOff.isImm() || OpOff.getImm() != 0)
325  return 0;
326  FrameIndex = OpFI.getIndex();
327  return MI.getOperand(3).getReg();
328  }
329  }
330 
331  return 0;
332 }
333 
334 /// This function checks if the instruction or bundle of instructions
335 /// has load from stack slot and returns frameindex and machine memory
336 /// operand of that instruction if true.
338  const MachineInstr &MI,
340  if (MI.isBundle()) {
341  const MachineBasicBlock *MBB = MI.getParent();
343  for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
344  if (TargetInstrInfo::hasLoadFromStackSlot(*MII, Accesses))
345  return true;
346  return false;
347  }
348 
349  return TargetInstrInfo::hasLoadFromStackSlot(MI, Accesses);
350 }
351 
352 /// This function checks if the instruction or bundle of instructions
353 /// has store to stack slot and returns frameindex and machine memory
354 /// operand of that instruction if true.
356  const MachineInstr &MI,
358  if (MI.isBundle()) {
359  const MachineBasicBlock *MBB = MI.getParent();
361  for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
362  if (TargetInstrInfo::hasStoreToStackSlot(*MII, Accesses))
363  return true;
364  return false;
365  }
366 
367  return TargetInstrInfo::hasStoreToStackSlot(MI, Accesses);
368 }
369 
370 /// This function can analyze one/two way branching only and should (mostly) be
371 /// called by target independent side.
372 /// First entry is always the opcode of the branching instruction, except when
373 /// the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a
374 /// BB with only unconditional jump. Subsequent entries depend upon the opcode,
375 /// e.g. Jump_c p will have
376 /// Cond[0] = Jump_c
377 /// Cond[1] = p
378 /// HW-loop ENDLOOP:
379 /// Cond[0] = ENDLOOP
380 /// Cond[1] = MBB
381 /// New value jump:
382 /// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
383 /// Cond[1] = R
384 /// Cond[2] = Imm
386  MachineBasicBlock *&TBB,
387  MachineBasicBlock *&FBB,
389  bool AllowModify) const {
390  TBB = nullptr;
391  FBB = nullptr;
392  Cond.clear();
393 
394  // If the block has no terminators, it just falls into the block after it.
396  if (I == MBB.instr_begin())
397  return false;
398 
399  // A basic block may looks like this:
400  //
401  // [ insn
402  // EH_LABEL
403  // insn
404  // insn
405  // insn
406  // EH_LABEL
407  // insn ]
408  //
409  // It has two succs but does not have a terminator
410  // Don't know how to handle it.
411  do {
412  --I;
413  if (I->isEHLabel())
414  // Don't analyze EH branches.
415  return true;
416  } while (I != MBB.instr_begin());
417 
418  I = MBB.instr_end();
419  --I;
420 
421  while (I->isDebugInstr()) {
422  if (I == MBB.instr_begin())
423  return false;
424  --I;
425  }
426 
427  bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
428  I->getOperand(0).isMBB();
429  // Delete the J2_jump if it's equivalent to a fall-through.
430  if (AllowModify && JumpToBlock &&
431  MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
432  LLVM_DEBUG(dbgs() << "\nErasing the jump to successor block\n";);
433  I->eraseFromParent();
434  I = MBB.instr_end();
435  if (I == MBB.instr_begin())
436  return false;
437  --I;
438  }
439  if (!isUnpredicatedTerminator(*I))
440  return false;
441 
442  // Get the last instruction in the block.
443  MachineInstr *LastInst = &*I;
444  MachineInstr *SecondLastInst = nullptr;
445  // Find one more terminator if present.
446  while (true) {
447  if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
448  if (!SecondLastInst)
449  SecondLastInst = &*I;
450  else
451  // This is a third branch.
452  return true;
453  }
454  if (I == MBB.instr_begin())
455  break;
456  --I;
457  }
458 
459  int LastOpcode = LastInst->getOpcode();
460  int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
461  // If the branch target is not a basic block, it could be a tail call.
462  // (It is, if the target is a function.)
463  if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
464  return true;
465  if (SecLastOpcode == Hexagon::J2_jump &&
466  !SecondLastInst->getOperand(0).isMBB())
467  return true;
468 
469  bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
470  bool LastOpcodeHasNVJump = isNewValueJump(*LastInst);
471 
472  if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB())
473  return true;
474 
475  // If there is only one terminator instruction, process it.
476  if (LastInst && !SecondLastInst) {
477  if (LastOpcode == Hexagon::J2_jump) {
478  TBB = LastInst->getOperand(0).getMBB();
479  return false;
480  }
481  if (isEndLoopN(LastOpcode)) {
482  TBB = LastInst->getOperand(0).getMBB();
483  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
484  Cond.push_back(LastInst->getOperand(0));
485  return false;
486  }
487  if (LastOpcodeHasJMP_c) {
488  TBB = LastInst->getOperand(1).getMBB();
489  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
490  Cond.push_back(LastInst->getOperand(0));
491  return false;
492  }
493  // Only supporting rr/ri versions of new-value jumps.
494  if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
495  TBB = LastInst->getOperand(2).getMBB();
496  Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
497  Cond.push_back(LastInst->getOperand(0));
498  Cond.push_back(LastInst->getOperand(1));
499  return false;
500  }
501  LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
502  << " with one jump\n";);
503  // Otherwise, don't know what this is.
504  return true;
505  }
506 
507  bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
508  bool SecLastOpcodeHasNVJump = isNewValueJump(*SecondLastInst);
509  if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
510  if (!SecondLastInst->getOperand(1).isMBB())
511  return true;
512  TBB = SecondLastInst->getOperand(1).getMBB();
513  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
514  Cond.push_back(SecondLastInst->getOperand(0));
515  FBB = LastInst->getOperand(0).getMBB();
516  return false;
517  }
518 
519  // Only supporting rr/ri versions of new-value jumps.
520  if (SecLastOpcodeHasNVJump &&
521  (SecondLastInst->getNumExplicitOperands() == 3) &&
522  (LastOpcode == Hexagon::J2_jump)) {
523  TBB = SecondLastInst->getOperand(2).getMBB();
524  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
525  Cond.push_back(SecondLastInst->getOperand(0));
526  Cond.push_back(SecondLastInst->getOperand(1));
527  FBB = LastInst->getOperand(0).getMBB();
528  return false;
529  }
530 
531  // If the block ends with two Hexagon:JMPs, handle it. The second one is not
532  // executed, so remove it.
533  if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
534  TBB = SecondLastInst->getOperand(0).getMBB();
535  I = LastInst->getIterator();
536  if (AllowModify)
537  I->eraseFromParent();
538  return false;
539  }
540 
541  // If the block ends with an ENDLOOP, and J2_jump, handle it.
542  if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
543  TBB = SecondLastInst->getOperand(0).getMBB();
544  Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
545  Cond.push_back(SecondLastInst->getOperand(0));
546  FBB = LastInst->getOperand(0).getMBB();
547  return false;
548  }
549  LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
550  << " with two jumps";);
551  // Otherwise, can't handle this.
552  return true;
553 }
554 
556  int *BytesRemoved) const {
557  assert(!BytesRemoved && "code size not handled");
558 
559  LLVM_DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB));
561  unsigned Count = 0;
562  while (I != MBB.begin()) {
563  --I;
564  if (I->isDebugInstr())
565  continue;
566  // Only removing branches from end of MBB.
567  if (!I->isBranch())
568  return Count;
569  if (Count && (I->getOpcode() == Hexagon::J2_jump))
570  llvm_unreachable("Malformed basic block: unconditional branch not last");
571  MBB.erase(&MBB.back());
572  I = MBB.end();
573  ++Count;
574  }
575  return Count;
576 }
577 
579  MachineBasicBlock *TBB,
580  MachineBasicBlock *FBB,
582  const DebugLoc &DL,
583  int *BytesAdded) const {
584  unsigned BOpc = Hexagon::J2_jump;
585  unsigned BccOpc = Hexagon::J2_jumpt;
586  assert(validateBranchCond(Cond) && "Invalid branching condition");
587  assert(TBB && "insertBranch must not be told to insert a fallthrough");
588  assert(!BytesAdded && "code size not handled");
589 
590  // Check if reverseBranchCondition has asked to reverse this branch
591  // If we want to reverse the branch an odd number of times, we want
592  // J2_jumpf.
593  if (!Cond.empty() && Cond[0].isImm())
594  BccOpc = Cond[0].getImm();
595 
596  if (!FBB) {
597  if (Cond.empty()) {
598  // Due to a bug in TailMerging/CFG Optimization, we need to add a
599  // special case handling of a predicated jump followed by an
600  // unconditional jump. If not, Tail Merging and CFG Optimization go
601  // into an infinite loop.
602  MachineBasicBlock *NewTBB, *NewFBB;
604  auto Term = MBB.getFirstTerminator();
605  if (Term != MBB.end() && isPredicated(*Term) &&
606  !analyzeBranch(MBB, NewTBB, NewFBB, Cond, false) &&
607  MachineFunction::iterator(NewTBB) == ++MBB.getIterator()) {
609  removeBranch(MBB);
610  return insertBranch(MBB, TBB, nullptr, Cond, DL);
611  }
612  BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
613  } else if (isEndLoopN(Cond[0].getImm())) {
614  int EndLoopOp = Cond[0].getImm();
615  assert(Cond[1].isMBB());
616  // Since we're adding an ENDLOOP, there better be a LOOP instruction.
617  // Check for it, and change the BB target if needed.
619  MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
620  VisitedBBs);
621  assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
622  Loop->getOperand(0).setMBB(TBB);
623  // Add the ENDLOOP after the finding the LOOP0.
624  BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
625  } else if (isNewValueJump(Cond[0].getImm())) {
626  assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
627  // New value jump
628  // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
629  // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
630  unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
631  LLVM_DEBUG(dbgs() << "\nInserting NVJump for "
632  << printMBBReference(MBB););
633  if (Cond[2].isReg()) {
634  unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
635  BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
636  addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
637  } else if(Cond[2].isImm()) {
638  BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
639  addImm(Cond[2].getImm()).addMBB(TBB);
640  } else
641  llvm_unreachable("Invalid condition for branching");
642  } else {
643  assert((Cond.size() == 2) && "Malformed cond vector");
644  const MachineOperand &RO = Cond[1];
645  unsigned Flags = getUndefRegState(RO.isUndef());
646  BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
647  }
648  return 1;
649  }
650  assert((!Cond.empty()) &&
651  "Cond. cannot be empty when multiple branchings are required");
652  assert((!isNewValueJump(Cond[0].getImm())) &&
653  "NV-jump cannot be inserted with another branch");
654  // Special case for hardware loops. The condition is a basic block.
655  if (isEndLoopN(Cond[0].getImm())) {
656  int EndLoopOp = Cond[0].getImm();
657  assert(Cond[1].isMBB());
658  // Since we're adding an ENDLOOP, there better be a LOOP instruction.
659  // Check for it, and change the BB target if needed.
661  MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(),
662  VisitedBBs);
663  assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
664  Loop->getOperand(0).setMBB(TBB);
665  // Add the ENDLOOP after the finding the LOOP0.
666  BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
667  } else {
668  const MachineOperand &RO = Cond[1];
669  unsigned Flags = getUndefRegState(RO.isUndef());
670  BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
671  }
672  BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
673 
674  return 2;
675 }
676 
677 /// Analyze the loop code to find the loop induction variable and compare used
678 /// to compute the number of iterations. Currently, we analyze loop that are
679 /// controlled using hardware loops. In this case, the induction variable
680 /// instruction is null. For all other cases, this function returns true, which
681 /// means we're unable to analyze it.
683  MachineInstr *&IndVarInst,
684  MachineInstr *&CmpInst) const {
685 
686  MachineBasicBlock *LoopEnd = L.getBottomBlock();
688  // We really "analyze" only hardware loops right now.
689  if (I != LoopEnd->end() && isEndLoopN(I->getOpcode())) {
690  IndVarInst = nullptr;
691  CmpInst = &*I;
692  return false;
693  }
694  return true;
695 }
696 
697 /// Generate code to reduce the loop iteration by one and check if the loop is
698 /// finished. Return the value/register of the new loop count. this function
699 /// assumes the nth iteration is peeled first.
701  MachineBasicBlock &MBB, MachineBasicBlock &PreHeader, MachineInstr *IndVar,
703  SmallVectorImpl<MachineInstr *> &PrevInsts, unsigned Iter,
704  unsigned MaxIter) const {
705  // We expect a hardware loop currently. This means that IndVar is set
706  // to null, and the compare is the ENDLOOP instruction.
707  assert((!IndVar) && isEndLoopN(Cmp.getOpcode())
708  && "Expecting a hardware loop");
709  MachineFunction *MF = MBB.getParent();
710  DebugLoc DL = Cmp.getDebugLoc();
712  MachineInstr *Loop = findLoopInstr(&MBB, Cmp.getOpcode(),
713  Cmp.getOperand(0).getMBB(), VisitedBBs);
714  if (!Loop)
715  return 0;
716  // If the loop trip count is a compile-time value, then just change the
717  // value.
718  if (Loop->getOpcode() == Hexagon::J2_loop0i ||
719  Loop->getOpcode() == Hexagon::J2_loop1i) {
720  int64_t Offset = Loop->getOperand(1).getImm();
721  if (Offset <= 1)
722  Loop->eraseFromParent();
723  else
724  Loop->getOperand(1).setImm(Offset - 1);
725  return Offset - 1;
726  }
727  // The loop trip count is a run-time value. We generate code to subtract
728  // one from the trip count, and update the loop instruction.
729  assert(Loop->getOpcode() == Hexagon::J2_loop0r && "Unexpected instruction");
730  unsigned LoopCount = Loop->getOperand(1).getReg();
731  // Check if we're done with the loop.
732  unsigned LoopEnd = createVR(MF, MVT::i1);
733  MachineInstr *NewCmp = BuildMI(&MBB, DL, get(Hexagon::C2_cmpgtui), LoopEnd).
734  addReg(LoopCount).addImm(1);
735  unsigned NewLoopCount = createVR(MF, MVT::i32);
736  MachineInstr *NewAdd = BuildMI(&MBB, DL, get(Hexagon::A2_addi), NewLoopCount).
737  addReg(LoopCount).addImm(-1);
738  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
739  // Update the previously generated instructions with the new loop counter.
741  E = PrevInsts.end(); I != E; ++I)
742  (*I)->substituteRegister(LoopCount, NewLoopCount, 0, HRI);
743  PrevInsts.clear();
744  PrevInsts.push_back(NewCmp);
745  PrevInsts.push_back(NewAdd);
746  // Insert the new loop instruction if this is the last time the loop is
747  // decremented.
748  if (Iter == MaxIter)
749  BuildMI(&MBB, DL, get(Hexagon::J2_loop0r)).
750  addMBB(Loop->getOperand(0).getMBB()).addReg(NewLoopCount);
751  // Delete the old loop instruction.
752  if (Iter == 0)
753  Loop->eraseFromParent();
754  Cond.push_back(MachineOperand::CreateImm(Hexagon::J2_jumpf));
755  Cond.push_back(NewCmp->getOperand(0));
756  return NewLoopCount;
757 }
758 
760  unsigned NumCycles, unsigned ExtraPredCycles,
761  BranchProbability Probability) const {
762  return nonDbgBBSize(&MBB) <= 3;
763 }
764 
766  unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB,
767  unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability)
768  const {
769  return nonDbgBBSize(&TMBB) <= 3 && nonDbgBBSize(&FMBB) <= 3;
770 }
771 
773  unsigned NumInstrs, BranchProbability Probability) const {
774  return NumInstrs <= 4;
775 }
776 
779  const DebugLoc &DL, unsigned DestReg,
780  unsigned SrcReg, bool KillSrc) const {
781  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
782  unsigned KillFlag = getKillRegState(KillSrc);
783 
784  if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
785  BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg)
786  .addReg(SrcReg, KillFlag);
787  return;
788  }
789  if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
790  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg)
791  .addReg(SrcReg, KillFlag);
792  return;
793  }
794  if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
795  // Map Pd = Ps to Pd = or(Ps, Ps).
796  BuildMI(MBB, I, DL, get(Hexagon::C2_or), DestReg)
797  .addReg(SrcReg).addReg(SrcReg, KillFlag);
798  return;
799  }
800  if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
801  Hexagon::IntRegsRegClass.contains(SrcReg)) {
802  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
803  .addReg(SrcReg, KillFlag);
804  return;
805  }
806  if (Hexagon::IntRegsRegClass.contains(DestReg) &&
807  Hexagon::CtrRegsRegClass.contains(SrcReg)) {
808  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrcrr), DestReg)
809  .addReg(SrcReg, KillFlag);
810  return;
811  }
812  if (Hexagon::ModRegsRegClass.contains(DestReg) &&
813  Hexagon::IntRegsRegClass.contains(SrcReg)) {
814  BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
815  .addReg(SrcReg, KillFlag);
816  return;
817  }
818  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
819  Hexagon::IntRegsRegClass.contains(DestReg)) {
820  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
821  .addReg(SrcReg, KillFlag);
822  return;
823  }
824  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
825  Hexagon::PredRegsRegClass.contains(DestReg)) {
826  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg)
827  .addReg(SrcReg, KillFlag);
828  return;
829  }
830  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
831  Hexagon::IntRegsRegClass.contains(DestReg)) {
832  BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
833  .addReg(SrcReg, KillFlag);
834  return;
835  }
836  if (Hexagon::HvxVRRegClass.contains(SrcReg, DestReg)) {
837  BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg).
838  addReg(SrcReg, KillFlag);
839  return;
840  }
841  if (Hexagon::HvxWRRegClass.contains(SrcReg, DestReg)) {
842  unsigned LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
843  unsigned HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
844  BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg)
845  .addReg(HiSrc, KillFlag)
846  .addReg(LoSrc, KillFlag);
847  return;
848  }
849  if (Hexagon::HvxQRRegClass.contains(SrcReg, DestReg)) {
850  BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg)
851  .addReg(SrcReg)
852  .addReg(SrcReg, KillFlag);
853  return;
854  }
855  if (Hexagon::HvxQRRegClass.contains(SrcReg) &&
856  Hexagon::HvxVRRegClass.contains(DestReg)) {
857  llvm_unreachable("Unimplemented pred to vec");
858  return;
859  }
860  if (Hexagon::HvxQRRegClass.contains(DestReg) &&
861  Hexagon::HvxVRRegClass.contains(SrcReg)) {
862  llvm_unreachable("Unimplemented vec to pred");
863  return;
864  }
865 
866 #ifndef NDEBUG
867  // Show the invalid registers to ease debugging.
868  dbgs() << "Invalid registers for copy in " << printMBBReference(MBB) << ": "
869  << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n';
870 #endif
871  llvm_unreachable("Unimplemented");
872 }
873 
875  MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI,
876  const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {
877  DebugLoc DL = MBB.findDebugLoc(I);
878  MachineFunction &MF = *MBB.getParent();
879  MachineFrameInfo &MFI = MF.getFrameInfo();
880  unsigned SlotAlign = MFI.getObjectAlignment(FI);
881  unsigned RegAlign = TRI->getSpillAlignment(*RC);
882  unsigned KillFlag = getKillRegState(isKill);
883  bool HasAlloca = MFI.hasVarSizedObjects();
884  const HexagonFrameLowering &HFI = *Subtarget.getFrameLowering();
885 
888  MFI.getObjectSize(FI), SlotAlign);
889 
890  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
891  BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
892  .addFrameIndex(FI).addImm(0)
893  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
894  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
895  BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
896  .addFrameIndex(FI).addImm(0)
897  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
898  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
899  BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
900  .addFrameIndex(FI).addImm(0)
901  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
902  } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
903  BuildMI(MBB, I, DL, get(Hexagon::STriw_ctr))
904  .addFrameIndex(FI).addImm(0)
905  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
906  } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
907  BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai))
908  .addFrameIndex(FI).addImm(0)
909  .addReg(SrcReg, KillFlag).addMemOperand(MMO);
910  } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
911  // If there are variable-sized objects, spills will not be aligned.
912  if (HasAlloca)
913  SlotAlign = HFI.getStackAlignment();
914  unsigned Opc = SlotAlign < RegAlign ? Hexagon::V6_vS32Ub_ai
915  : Hexagon::V6_vS32b_ai;
918  MFI.getObjectSize(FI), SlotAlign);
919  BuildMI(MBB, I, DL, get(Opc))
920  .addFrameIndex(FI).addImm(0)
921  .addReg(SrcReg, KillFlag).addMemOperand(MMOA);
922  } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
923  // If there are variable-sized objects, spills will not be aligned.
924  if (HasAlloca)
925  SlotAlign = HFI.getStackAlignment();
926  unsigned Opc = SlotAlign < RegAlign ? Hexagon::PS_vstorerwu_ai
927  : Hexagon::PS_vstorerw_ai;
930  MFI.getObjectSize(FI), SlotAlign);
931  BuildMI(MBB, I, DL, get(Opc))
932  .addFrameIndex(FI).addImm(0)
933  .addReg(SrcReg, KillFlag).addMemOperand(MMOA);
934  } else {
935  llvm_unreachable("Unimplemented");
936  }
937 }
938 
940  MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg,
941  int FI, const TargetRegisterClass *RC,
942  const TargetRegisterInfo *TRI) const {
943  DebugLoc DL = MBB.findDebugLoc(I);
944  MachineFunction &MF = *MBB.getParent();
945  MachineFrameInfo &MFI = MF.getFrameInfo();
946  unsigned SlotAlign = MFI.getObjectAlignment(FI);
947  unsigned RegAlign = TRI->getSpillAlignment(*RC);
948  bool HasAlloca = MFI.hasVarSizedObjects();
949  const HexagonFrameLowering &HFI = *Subtarget.getFrameLowering();
950 
953  MFI.getObjectSize(FI), SlotAlign);
954 
955  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
956  BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
957  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
958  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
959  BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
960  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
961  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
962  BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
963  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
964  } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
965  BuildMI(MBB, I, DL, get(Hexagon::LDriw_ctr), DestReg)
966  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
967  } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
968  BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai), DestReg)
969  .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
970  } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
971  // If there are variable-sized objects, spills will not be aligned.
972  if (HasAlloca)
973  SlotAlign = HFI.getStackAlignment();
974  unsigned Opc = SlotAlign < RegAlign ? Hexagon::V6_vL32Ub_ai
975  : Hexagon::V6_vL32b_ai;
978  MFI.getObjectSize(FI), SlotAlign);
979  BuildMI(MBB, I, DL, get(Opc), DestReg)
980  .addFrameIndex(FI).addImm(0).addMemOperand(MMOA);
981  } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
982  // If there are variable-sized objects, spills will not be aligned.
983  if (HasAlloca)
984  SlotAlign = HFI.getStackAlignment();
985  unsigned Opc = SlotAlign < RegAlign ? Hexagon::PS_vloadrwu_ai
986  : Hexagon::PS_vloadrw_ai;
989  MFI.getObjectSize(FI), SlotAlign);
990  BuildMI(MBB, I, DL, get(Opc), DestReg)
991  .addFrameIndex(FI).addImm(0).addMemOperand(MMOA);
992  } else {
993  llvm_unreachable("Can't store this register to stack slot");
994  }
995 }
996 
997 static void getLiveRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
998  const MachineBasicBlock &B = *MI.getParent();
999  Regs.addLiveOuts(B);
1000  auto E = ++MachineBasicBlock::const_iterator(MI.getIterator()).getReverse();
1001  for (auto I = B.rbegin(); I != E; ++I)
1002  Regs.stepBackward(*I);
1003 }
1004 
1005 /// expandPostRAPseudo - This function is called for all pseudo instructions
1006 /// that remain after register allocation. Many pseudo instructions are
1007 /// created to help register allocation. This is the place to convert them
1008 /// into real instructions. The target can edit MI in place, or it can insert
1009 /// new instructions and erase MI. The function should return true if
1010 /// anything was changed.
1012  MachineBasicBlock &MBB = *MI.getParent();
1013  MachineFunction &MF = *MBB.getParent();
1015  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1016  DebugLoc DL = MI.getDebugLoc();
1017  unsigned Opc = MI.getOpcode();
1018 
1019  auto RealCirc = [&](unsigned Opc, bool HasImm, unsigned MxOp) {
1020  unsigned Mx = MI.getOperand(MxOp).getReg();
1021  unsigned CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1);
1022  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrrcr), CSx)
1023  .add(MI.getOperand((HasImm ? 5 : 4)));
1024  auto MIB = BuildMI(MBB, MI, DL, get(Opc)).add(MI.getOperand(0))
1025  .add(MI.getOperand(1)).add(MI.getOperand(2)).add(MI.getOperand(3));
1026  if (HasImm)
1027  MIB.add(MI.getOperand(4));
1028  MIB.addReg(CSx, RegState::Implicit);
1029  MBB.erase(MI);
1030  return true;
1031  };
1032 
1033  switch (Opc) {
1034  case TargetOpcode::COPY: {
1035  MachineOperand &MD = MI.getOperand(0);
1036  MachineOperand &MS = MI.getOperand(1);
1038  if (MD.getReg() != MS.getReg() && !MS.isUndef()) {
1039  copyPhysReg(MBB, MI, DL, MD.getReg(), MS.getReg(), MS.isKill());
1040  std::prev(MBBI)->copyImplicitOps(*MBB.getParent(), MI);
1041  }
1042  MBB.erase(MBBI);
1043  return true;
1044  }
1045  case Hexagon::PS_aligna:
1046  BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg())
1047  .addReg(HRI.getFrameRegister())
1048  .addImm(-MI.getOperand(1).getImm());
1049  MBB.erase(MI);
1050  return true;
1051  case Hexagon::V6_vassignp: {
1052  unsigned SrcReg = MI.getOperand(1).getReg();
1053  unsigned DstReg = MI.getOperand(0).getReg();
1054  unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
1055  BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg)
1056  .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi), Kill)
1057  .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo), Kill);
1058  MBB.erase(MI);
1059  return true;
1060  }
1061  case Hexagon::V6_lo: {
1062  unsigned SrcReg = MI.getOperand(1).getReg();
1063  unsigned DstReg = MI.getOperand(0).getReg();
1064  unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1065  copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI.getOperand(1).isKill());
1066  MBB.erase(MI);
1067  MRI.clearKillFlags(SrcSubLo);
1068  return true;
1069  }
1070  case Hexagon::V6_hi: {
1071  unsigned SrcReg = MI.getOperand(1).getReg();
1072  unsigned DstReg = MI.getOperand(0).getReg();
1073  unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1074  copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI.getOperand(1).isKill());
1075  MBB.erase(MI);
1076  MRI.clearKillFlags(SrcSubHi);
1077  return true;
1078  }
1079  case Hexagon::PS_vstorerw_ai:
1080  case Hexagon::PS_vstorerwu_ai: {
1081  bool Aligned = Opc == Hexagon::PS_vstorerw_ai;
1082  unsigned SrcReg = MI.getOperand(2).getReg();
1083  unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1084  unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1085  unsigned NewOpc = Aligned ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32Ub_ai;
1086  unsigned Offset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1087 
1088  MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpc))
1089  .add(MI.getOperand(0))
1090  .addImm(MI.getOperand(1).getImm())
1091  .addReg(SrcSubLo)
1092  .cloneMemRefs(MI);
1093  MI1New->getOperand(0).setIsKill(false);
1094  BuildMI(MBB, MI, DL, get(NewOpc))
1095  .add(MI.getOperand(0))
1096  // The Vectors are indexed in multiples of vector size.
1097  .addImm(MI.getOperand(1).getImm() + Offset)
1098  .addReg(SrcSubHi)
1099  .cloneMemRefs(MI);
1100  MBB.erase(MI);
1101  return true;
1102  }
1103  case Hexagon::PS_vloadrw_ai:
1104  case Hexagon::PS_vloadrwu_ai: {
1105  bool Aligned = Opc == Hexagon::PS_vloadrw_ai;
1106  unsigned DstReg = MI.getOperand(0).getReg();
1107  unsigned NewOpc = Aligned ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32Ub_ai;
1108  unsigned Offset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
1109 
1110  MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpc),
1111  HRI.getSubReg(DstReg, Hexagon::vsub_lo))
1112  .add(MI.getOperand(1))
1113  .addImm(MI.getOperand(2).getImm())
1114  .cloneMemRefs(MI);
1115  MI1New->getOperand(1).setIsKill(false);
1116  BuildMI(MBB, MI, DL, get(NewOpc), HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1117  .add(MI.getOperand(1))
1118  // The Vectors are indexed in multiples of vector size.
1119  .addImm(MI.getOperand(2).getImm() + Offset)
1120  .cloneMemRefs(MI);
1121  MBB.erase(MI);
1122  return true;
1123  }
1124  case Hexagon::PS_true: {
1125  unsigned Reg = MI.getOperand(0).getReg();
1126  BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
1127  .addReg(Reg, RegState::Undef)
1128  .addReg(Reg, RegState::Undef);
1129  MBB.erase(MI);
1130  return true;
1131  }
1132  case Hexagon::PS_false: {
1133  unsigned Reg = MI.getOperand(0).getReg();
1134  BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
1135  .addReg(Reg, RegState::Undef)
1136  .addReg(Reg, RegState::Undef);
1137  MBB.erase(MI);
1138  return true;
1139  }
1140  case Hexagon::PS_qtrue: {
1141  BuildMI(MBB, MI, DL, get(Hexagon::V6_veqw), MI.getOperand(0).getReg())
1142  .addReg(Hexagon::V0, RegState::Undef)
1143  .addReg(Hexagon::V0, RegState::Undef);
1144  MBB.erase(MI);
1145  return true;
1146  }
1147  case Hexagon::PS_qfalse: {
1148  BuildMI(MBB, MI, DL, get(Hexagon::V6_vgtw), MI.getOperand(0).getReg())
1149  .addReg(Hexagon::V0, RegState::Undef)
1150  .addReg(Hexagon::V0, RegState::Undef);
1151  MBB.erase(MI);
1152  return true;
1153  }
1154  case Hexagon::PS_vdd0: {
1155  unsigned Vd = MI.getOperand(0).getReg();
1156  BuildMI(MBB, MI, DL, get(Hexagon::V6_vsubw_dv), Vd)
1157  .addReg(Vd, RegState::Undef)
1158  .addReg(Vd, RegState::Undef);
1159  MBB.erase(MI);
1160  return true;
1161  }
1162  case Hexagon::PS_vmulw: {
1163  // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
1164  unsigned DstReg = MI.getOperand(0).getReg();
1165  unsigned Src1Reg = MI.getOperand(1).getReg();
1166  unsigned Src2Reg = MI.getOperand(2).getReg();
1167  unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1168  unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1169  unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1170  unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1171  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1172  HRI.getSubReg(DstReg, Hexagon::isub_hi))
1173  .addReg(Src1SubHi)
1174  .addReg(Src2SubHi);
1175  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1176  HRI.getSubReg(DstReg, Hexagon::isub_lo))
1177  .addReg(Src1SubLo)
1178  .addReg(Src2SubLo);
1179  MBB.erase(MI);
1180  MRI.clearKillFlags(Src1SubHi);
1181  MRI.clearKillFlags(Src1SubLo);
1182  MRI.clearKillFlags(Src2SubHi);
1183  MRI.clearKillFlags(Src2SubLo);
1184  return true;
1185  }
1186  case Hexagon::PS_vmulw_acc: {
1187  // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
1188  unsigned DstReg = MI.getOperand(0).getReg();
1189  unsigned Src1Reg = MI.getOperand(1).getReg();
1190  unsigned Src2Reg = MI.getOperand(2).getReg();
1191  unsigned Src3Reg = MI.getOperand(3).getReg();
1192  unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1193  unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1194  unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1195  unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1196  unsigned Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
1197  unsigned Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
1198  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1199  HRI.getSubReg(DstReg, Hexagon::isub_hi))
1200  .addReg(Src1SubHi)
1201  .addReg(Src2SubHi)
1202  .addReg(Src3SubHi);
1203  BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1204  HRI.getSubReg(DstReg, Hexagon::isub_lo))
1205  .addReg(Src1SubLo)
1206  .addReg(Src2SubLo)
1207  .addReg(Src3SubLo);
1208  MBB.erase(MI);
1209  MRI.clearKillFlags(Src1SubHi);
1210  MRI.clearKillFlags(Src1SubLo);
1211  MRI.clearKillFlags(Src2SubHi);
1212  MRI.clearKillFlags(Src2SubLo);
1213  MRI.clearKillFlags(Src3SubHi);
1214  MRI.clearKillFlags(Src3SubLo);
1215  return true;
1216  }
1217  case Hexagon::PS_pselect: {
1218  const MachineOperand &Op0 = MI.getOperand(0);
1219  const MachineOperand &Op1 = MI.getOperand(1);
1220  const MachineOperand &Op2 = MI.getOperand(2);
1221  const MachineOperand &Op3 = MI.getOperand(3);
1222  unsigned Rd = Op0.getReg();
1223  unsigned Pu = Op1.getReg();
1224  unsigned Rs = Op2.getReg();
1225  unsigned Rt = Op3.getReg();
1226  DebugLoc DL = MI.getDebugLoc();
1227  unsigned K1 = getKillRegState(Op1.isKill());
1228  unsigned K2 = getKillRegState(Op2.isKill());
1229  unsigned K3 = getKillRegState(Op3.isKill());
1230  if (Rd != Rs)
1231  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
1232  .addReg(Pu, (Rd == Rt) ? K1 : 0)
1233  .addReg(Rs, K2);
1234  if (Rd != Rt)
1235  BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
1236  .addReg(Pu, K1)
1237  .addReg(Rt, K3);
1238  MBB.erase(MI);
1239  return true;
1240  }
1241  case Hexagon::PS_vselect: {
1242  const MachineOperand &Op0 = MI.getOperand(0);
1243  const MachineOperand &Op1 = MI.getOperand(1);
1244  const MachineOperand &Op2 = MI.getOperand(2);
1245  const MachineOperand &Op3 = MI.getOperand(3);
1246  LivePhysRegs LiveAtMI(HRI);
1247  getLiveRegsAt(LiveAtMI, MI);
1248  bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
1249  unsigned PReg = Op1.getReg();
1250  assert(Op1.getSubReg() == 0);
1251  unsigned PState = getRegState(Op1);
1252 
1253  if (Op0.getReg() != Op2.getReg()) {
1254  unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1255  : PState;
1256  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov))
1257  .add(Op0)
1258  .addReg(PReg, S)
1259  .add(Op2);
1260  if (IsDestLive)
1261  T.addReg(Op0.getReg(), RegState::Implicit);
1262  IsDestLive = true;
1263  }
1264  if (Op0.getReg() != Op3.getReg()) {
1265  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov))
1266  .add(Op0)
1267  .addReg(PReg, PState)
1268  .add(Op3);
1269  if (IsDestLive)
1270  T.addReg(Op0.getReg(), RegState::Implicit);
1271  }
1272  MBB.erase(MI);
1273  return true;
1274  }
1275  case Hexagon::PS_wselect: {
1276  MachineOperand &Op0 = MI.getOperand(0);
1277  MachineOperand &Op1 = MI.getOperand(1);
1278  MachineOperand &Op2 = MI.getOperand(2);
1279  MachineOperand &Op3 = MI.getOperand(3);
1280  LivePhysRegs LiveAtMI(HRI);
1281  getLiveRegsAt(LiveAtMI, MI);
1282  bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
1283  unsigned PReg = Op1.getReg();
1284  assert(Op1.getSubReg() == 0);
1285  unsigned PState = getRegState(Op1);
1286 
1287  if (Op0.getReg() != Op2.getReg()) {
1288  unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1289  : PState;
1290  unsigned SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
1291  unsigned SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
1292  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine))
1293  .add(Op0)
1294  .addReg(PReg, S)
1295  .addReg(SrcHi)
1296  .addReg(SrcLo);
1297  if (IsDestLive)
1298  T.addReg(Op0.getReg(), RegState::Implicit);
1299  IsDestLive = true;
1300  }
1301  if (Op0.getReg() != Op3.getReg()) {
1302  unsigned SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);
1303  unsigned SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
1304  auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine))
1305  .add(Op0)
1306  .addReg(PReg, PState)
1307  .addReg(SrcHi)
1308  .addReg(SrcLo);
1309  if (IsDestLive)
1310  T.addReg(Op0.getReg(), RegState::Implicit);
1311  }
1312  MBB.erase(MI);
1313  return true;
1314  }
1315 
1316  case Hexagon::PS_crash: {
1317  // Generate a misaligned load that is guaranteed to cause a crash.
1318  class CrashPseudoSourceValue : public PseudoSourceValue {
1319  public:
1320  CrashPseudoSourceValue(const TargetInstrInfo &TII)
1321  : PseudoSourceValue(TargetCustom, TII) {}
1322 
1323  bool isConstant(const MachineFrameInfo *) const override {
1324  return false;
1325  }
1326  bool isAliased(const MachineFrameInfo *) const override {
1327  return false;
1328  }
1329  bool mayAlias(const MachineFrameInfo *) const override {
1330  return false;
1331  }
1332  void printCustom(raw_ostream &OS) const override {
1333  OS << "MisalignedCrash";
1334  }
1335  };
1336 
1337  static const CrashPseudoSourceValue CrashPSV(*this);
1339  MachinePointerInfo(&CrashPSV),
1341  BuildMI(MBB, MI, DL, get(Hexagon::PS_loadrdabs), Hexagon::D13)
1342  .addImm(0xBADC0FEE) // Misaligned load.
1343  .addMemOperand(MMO);
1344  MBB.erase(MI);
1345  return true;
1346  }
1347 
1348  case Hexagon::PS_tailcall_i:
1349  MI.setDesc(get(Hexagon::J2_jump));
1350  return true;
1351  case Hexagon::PS_tailcall_r:
1352  case Hexagon::PS_jmpret:
1353  MI.setDesc(get(Hexagon::J2_jumpr));
1354  return true;
1355  case Hexagon::PS_jmprett:
1356  MI.setDesc(get(Hexagon::J2_jumprt));
1357  return true;
1358  case Hexagon::PS_jmpretf:
1359  MI.setDesc(get(Hexagon::J2_jumprf));
1360  return true;
1361  case Hexagon::PS_jmprettnewpt:
1362  MI.setDesc(get(Hexagon::J2_jumprtnewpt));
1363  return true;
1364  case Hexagon::PS_jmpretfnewpt:
1365  MI.setDesc(get(Hexagon::J2_jumprfnewpt));
1366  return true;
1367  case Hexagon::PS_jmprettnew:
1368  MI.setDesc(get(Hexagon::J2_jumprtnew));
1369  return true;
1370  case Hexagon::PS_jmpretfnew:
1371  MI.setDesc(get(Hexagon::J2_jumprfnew));
1372  return true;
1373 
1374  case Hexagon::PS_loadrub_pci:
1375  return RealCirc(Hexagon::L2_loadrub_pci, /*HasImm*/true, /*MxOp*/4);
1376  case Hexagon::PS_loadrb_pci:
1377  return RealCirc(Hexagon::L2_loadrb_pci, /*HasImm*/true, /*MxOp*/4);
1378  case Hexagon::PS_loadruh_pci:
1379  return RealCirc(Hexagon::L2_loadruh_pci, /*HasImm*/true, /*MxOp*/4);
1380  case Hexagon::PS_loadrh_pci:
1381  return RealCirc(Hexagon::L2_loadrh_pci, /*HasImm*/true, /*MxOp*/4);
1382  case Hexagon::PS_loadri_pci:
1383  return RealCirc(Hexagon::L2_loadri_pci, /*HasImm*/true, /*MxOp*/4);
1384  case Hexagon::PS_loadrd_pci:
1385  return RealCirc(Hexagon::L2_loadrd_pci, /*HasImm*/true, /*MxOp*/4);
1386  case Hexagon::PS_loadrub_pcr:
1387  return RealCirc(Hexagon::L2_loadrub_pcr, /*HasImm*/false, /*MxOp*/3);
1388  case Hexagon::PS_loadrb_pcr:
1389  return RealCirc(Hexagon::L2_loadrb_pcr, /*HasImm*/false, /*MxOp*/3);
1390  case Hexagon::PS_loadruh_pcr:
1391  return RealCirc(Hexagon::L2_loadruh_pcr, /*HasImm*/false, /*MxOp*/3);
1392  case Hexagon::PS_loadrh_pcr:
1393  return RealCirc(Hexagon::L2_loadrh_pcr, /*HasImm*/false, /*MxOp*/3);
1394  case Hexagon::PS_loadri_pcr:
1395  return RealCirc(Hexagon::L2_loadri_pcr, /*HasImm*/false, /*MxOp*/3);
1396  case Hexagon::PS_loadrd_pcr:
1397  return RealCirc(Hexagon::L2_loadrd_pcr, /*HasImm*/false, /*MxOp*/3);
1398  case Hexagon::PS_storerb_pci:
1399  return RealCirc(Hexagon::S2_storerb_pci, /*HasImm*/true, /*MxOp*/3);
1400  case Hexagon::PS_storerh_pci:
1401  return RealCirc(Hexagon::S2_storerh_pci, /*HasImm*/true, /*MxOp*/3);
1402  case Hexagon::PS_storerf_pci:
1403  return RealCirc(Hexagon::S2_storerf_pci, /*HasImm*/true, /*MxOp*/3);
1404  case Hexagon::PS_storeri_pci:
1405  return RealCirc(Hexagon::S2_storeri_pci, /*HasImm*/true, /*MxOp*/3);
1406  case Hexagon::PS_storerd_pci:
1407  return RealCirc(Hexagon::S2_storerd_pci, /*HasImm*/true, /*MxOp*/3);
1408  case Hexagon::PS_storerb_pcr:
1409  return RealCirc(Hexagon::S2_storerb_pcr, /*HasImm*/false, /*MxOp*/2);
1410  case Hexagon::PS_storerh_pcr:
1411  return RealCirc(Hexagon::S2_storerh_pcr, /*HasImm*/false, /*MxOp*/2);
1412  case Hexagon::PS_storerf_pcr:
1413  return RealCirc(Hexagon::S2_storerf_pcr, /*HasImm*/false, /*MxOp*/2);
1414  case Hexagon::PS_storeri_pcr:
1415  return RealCirc(Hexagon::S2_storeri_pcr, /*HasImm*/false, /*MxOp*/2);
1416  case Hexagon::PS_storerd_pcr:
1417  return RealCirc(Hexagon::S2_storerd_pcr, /*HasImm*/false, /*MxOp*/2);
1418  }
1419 
1420  return false;
1421 }
1422 
1425  MachineBasicBlock &MBB = *MI.getParent();
1426  const DebugLoc &DL = MI.getDebugLoc();
1427  unsigned Opc = MI.getOpcode();
1429 
1430  switch (Opc) {
1431  case Hexagon::V6_vgathermh_pseudo:
1432  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermh))
1433  .add(MI.getOperand(1))
1434  .add(MI.getOperand(2))
1435  .add(MI.getOperand(3));
1436  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1437  .add(MI.getOperand(0))
1438  .addImm(0)
1439  .addReg(Hexagon::VTMP);
1440  MBB.erase(MI);
1441  return First.getInstrIterator();
1442 
1443  case Hexagon::V6_vgathermw_pseudo:
1444  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermw))
1445  .add(MI.getOperand(1))
1446  .add(MI.getOperand(2))
1447  .add(MI.getOperand(3));
1448  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1449  .add(MI.getOperand(0))
1450  .addImm(0)
1451  .addReg(Hexagon::VTMP);
1452  MBB.erase(MI);
1453  return First.getInstrIterator();
1454 
1455  case Hexagon::V6_vgathermhw_pseudo:
1456  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhw))
1457  .add(MI.getOperand(1))
1458  .add(MI.getOperand(2))
1459  .add(MI.getOperand(3));
1460  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1461  .add(MI.getOperand(0))
1462  .addImm(0)
1463  .addReg(Hexagon::VTMP);
1464  MBB.erase(MI);
1465  return First.getInstrIterator();
1466 
1467  case Hexagon::V6_vgathermhq_pseudo:
1468  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhq))
1469  .add(MI.getOperand(1))
1470  .add(MI.getOperand(2))
1471  .add(MI.getOperand(3))
1472  .add(MI.getOperand(4));
1473  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1474  .add(MI.getOperand(0))
1475  .addImm(0)
1476  .addReg(Hexagon::VTMP);
1477  MBB.erase(MI);
1478  return First.getInstrIterator();
1479 
1480  case Hexagon::V6_vgathermwq_pseudo:
1481  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermwq))
1482  .add(MI.getOperand(1))
1483  .add(MI.getOperand(2))
1484  .add(MI.getOperand(3))
1485  .add(MI.getOperand(4));
1486  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1487  .add(MI.getOperand(0))
1488  .addImm(0)
1489  .addReg(Hexagon::VTMP);
1490  MBB.erase(MI);
1491  return First.getInstrIterator();
1492 
1493  case Hexagon::V6_vgathermhwq_pseudo:
1494  First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhwq))
1495  .add(MI.getOperand(1))
1496  .add(MI.getOperand(2))
1497  .add(MI.getOperand(3))
1498  .add(MI.getOperand(4));
1499  BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1500  .add(MI.getOperand(0))
1501  .addImm(0)
1502  .addReg(Hexagon::VTMP);
1503  MBB.erase(MI);
1504  return First.getInstrIterator();
1505  }
1506 
1507  return MI.getIterator();
1508 }
1509 
1510 // We indicate that we want to reverse the branch by
1511 // inserting the reversed branching opcode.
1513  SmallVectorImpl<MachineOperand> &Cond) const {
1514  if (Cond.empty())
1515  return true;
1516  assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1517  unsigned opcode = Cond[0].getImm();
1518  //unsigned temp;
1519  assert(get(opcode).isBranch() && "Should be a branching condition.");
1520  if (isEndLoopN(opcode))
1521  return true;
1522  unsigned NewOpcode = getInvertedPredicatedOpcode(opcode);
1523  Cond[0].setImm(NewOpcode);
1524  return false;
1525 }
1526 
1529  DebugLoc DL;
1530  BuildMI(MBB, MI, DL, get(Hexagon::A2_nop));
1531 }
1532 
1534  return getAddrMode(MI) == HexagonII::PostInc;
1535 }
1536 
1537 // Returns true if an instruction is predicated irrespective of the predicate
1538 // sense. For example, all of the following will return true.
1539 // if (p0) R1 = add(R2, R3)
1540 // if (!p0) R1 = add(R2, R3)
1541 // if (p0.new) R1 = add(R2, R3)
1542 // if (!p0.new) R1 = add(R2, R3)
1543 // Note: New-value stores are not included here as in the current
1544 // implementation, we don't need to check their predicate sense.
1546  const uint64_t F = MI.getDesc().TSFlags;
1548 }
1549 
1551  MachineInstr &MI, ArrayRef<MachineOperand> Cond) const {
1552  if (Cond.empty() || isNewValueJump(Cond[0].getImm()) ||
1553  isEndLoopN(Cond[0].getImm())) {
1554  LLVM_DEBUG(dbgs() << "\nCannot predicate:"; MI.dump(););
1555  return false;
1556  }
1557  int Opc = MI.getOpcode();
1558  assert (isPredicable(MI) && "Expected predicable instruction");
1559  bool invertJump = predOpcodeHasNot(Cond);
1560 
1561  // We have to predicate MI "in place", i.e. after this function returns,
1562  // MI will need to be transformed into a predicated form. To avoid com-
1563  // plicated manipulations with the operands (handling tied operands,
1564  // etc.), build a new temporary instruction, then overwrite MI with it.
1565 
1566  MachineBasicBlock &B = *MI.getParent();
1567  DebugLoc DL = MI.getDebugLoc();
1568  unsigned PredOpc = getCondOpcode(Opc, invertJump);
1569  MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
1570  unsigned NOp = 0, NumOps = MI.getNumOperands();
1571  while (NOp < NumOps) {
1572  MachineOperand &Op = MI.getOperand(NOp);
1573  if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1574  break;
1575  T.add(Op);
1576  NOp++;
1577  }
1578 
1579  unsigned PredReg, PredRegPos, PredRegFlags;
1580  bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1581  (void)GotPredReg;
1582  assert(GotPredReg);
1583  T.addReg(PredReg, PredRegFlags);
1584  while (NOp < NumOps)
1585  T.add(MI.getOperand(NOp++));
1586 
1587  MI.setDesc(get(PredOpc));
1588  while (unsigned n = MI.getNumOperands())
1589  MI.RemoveOperand(n-1);
1590  for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1591  MI.addOperand(T->getOperand(i));
1592 
1594  B.erase(TI);
1595 
1597  MRI.clearKillFlags(PredReg);
1598  return true;
1599 }
1600 
1602  ArrayRef<MachineOperand> Pred2) const {
1603  // TODO: Fix this
1604  return false;
1605 }
1606 
1608  std::vector<MachineOperand> &Pred) const {
1609  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1610 
1611  for (unsigned oper = 0; oper < MI.getNumOperands(); ++oper) {
1612  MachineOperand MO = MI.getOperand(oper);
1613  if (MO.isReg()) {
1614  if (!MO.isDef())
1615  continue;
1616  const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
1617  if (RC == &Hexagon::PredRegsRegClass) {
1618  Pred.push_back(MO);
1619  return true;
1620  }
1621  continue;
1622  } else if (MO.isRegMask()) {
1623  for (unsigned PR : Hexagon::PredRegsRegClass) {
1624  if (!MI.modifiesRegister(PR, &HRI))
1625  continue;
1626  Pred.push_back(MO);
1627  return true;
1628  }
1629  }
1630  }
1631  return false;
1632 }
1633 
1635  if (!MI.getDesc().isPredicable())
1636  return false;
1637 
1638  if (MI.isCall() || isTailCall(MI)) {
1639  if (!Subtarget.usePredicatedCalls())
1640  return false;
1641  }
1642 
1643  // HVX loads are not predicable on v60, but are on v62.
1644  if (!Subtarget.hasV62Ops()) {
1645  switch (MI.getOpcode()) {
1646  case Hexagon::V6_vL32b_ai:
1647  case Hexagon::V6_vL32b_pi:
1648  case Hexagon::V6_vL32b_ppu:
1649  case Hexagon::V6_vL32b_cur_ai:
1650  case Hexagon::V6_vL32b_cur_pi:
1651  case Hexagon::V6_vL32b_cur_ppu:
1652  case Hexagon::V6_vL32b_nt_ai:
1653  case Hexagon::V6_vL32b_nt_pi:
1654  case Hexagon::V6_vL32b_nt_ppu:
1655  case Hexagon::V6_vL32b_tmp_ai:
1656  case Hexagon::V6_vL32b_tmp_pi:
1657  case Hexagon::V6_vL32b_tmp_ppu:
1658  case Hexagon::V6_vL32b_nt_cur_ai:
1659  case Hexagon::V6_vL32b_nt_cur_pi:
1660  case Hexagon::V6_vL32b_nt_cur_ppu:
1661  case Hexagon::V6_vL32b_nt_tmp_ai:
1662  case Hexagon::V6_vL32b_nt_tmp_pi:
1663  case Hexagon::V6_vL32b_nt_tmp_ppu:
1664  return false;
1665  }
1666  }
1667  return true;
1668 }
1669 
1671  const MachineBasicBlock *MBB,
1672  const MachineFunction &MF) const {
1673  // Debug info is never a scheduling boundary. It's necessary to be explicit
1674  // due to the special treatment of IT instructions below, otherwise a
1675  // dbg_value followed by an IT will result in the IT instruction being
1676  // considered a scheduling hazard, which is wrong. It should be the actual
1677  // instruction preceding the dbg_value instruction(s), just like it is
1678  // when debug info is not present.
1679  if (MI.isDebugInstr())
1680  return false;
1681 
1682  // Throwing call is a boundary.
1683  if (MI.isCall()) {
1684  // Don't mess around with no return calls.
1685  if (doesNotReturn(MI))
1686  return true;
1687  // If any of the block's successors is a landing pad, this could be a
1688  // throwing call.
1689  for (auto I : MBB->successors())
1690  if (I->isEHPad())
1691  return true;
1692  }
1693 
1694  // Terminators and labels can't be scheduled around.
1695  if (MI.getDesc().isTerminator() || MI.isPosition())
1696  return true;
1697 
1698  if (MI.isInlineAsm() && !ScheduleInlineAsm)
1699  return true;
1700 
1701  return false;
1702 }
1703 
1704 /// Measure the specified inline asm to determine an approximation of its
1705 /// length.
1706 /// Comments (which run till the next SeparatorString or newline) do not
1707 /// count as an instruction.
1708 /// Any other non-whitespace text is considered an instruction, with
1709 /// multiple instructions separated by SeparatorString or newlines.
1710 /// Variable-length instructions are not handled here; this function
1711 /// may be overloaded in the target code to do that.
1712 /// Hexagon counts the number of ##'s and adjust for that many
1713 /// constant exenders.
1714 unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
1715  const MCAsmInfo &MAI,
1716  const TargetSubtargetInfo *STI) const {
1717  StringRef AStr(Str);
1718  // Count the number of instructions in the asm.
1719  bool atInsnStart = true;
1720  unsigned Length = 0;
1721  const unsigned MaxInstLength = MAI.getMaxInstLength(STI);
1722  for (; *Str; ++Str) {
1723  if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
1724  strlen(MAI.getSeparatorString())) == 0)
1725  atInsnStart = true;
1726  if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
1727  Length += MaxInstLength;
1728  atInsnStart = false;
1729  }
1730  if (atInsnStart && strncmp(Str, MAI.getCommentString().data(),
1731  MAI.getCommentString().size()) == 0)
1732  atInsnStart = false;
1733  }
1734 
1735  // Add to size number of constant extenders seen * 4.
1736  StringRef Occ("##");
1737  Length += AStr.count(Occ)*4;
1738  return Length;
1739 }
1740 
1743  const InstrItineraryData *II, const ScheduleDAG *DAG) const {
1744  if (UseDFAHazardRec)
1745  return new HexagonHazardRecognizer(II, this, Subtarget);
1747 }
1748 
1749 /// For a comparison instruction, return the source registers in
1750 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
1751 /// compares against in CmpValue. Return true if the comparison instruction
1752 /// can be analyzed.
1753 bool HexagonInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1754  unsigned &SrcReg2, int &Mask,
1755  int &Value) const {
1756  unsigned Opc = MI.getOpcode();
1757 
1758  // Set mask and the first source register.
1759  switch (Opc) {
1760  case Hexagon::C2_cmpeq:
1761  case Hexagon::C2_cmpeqp:
1762  case Hexagon::C2_cmpgt:
1763  case Hexagon::C2_cmpgtp:
1764  case Hexagon::C2_cmpgtu:
1765  case Hexagon::C2_cmpgtup:
1766  case Hexagon::C4_cmpneq:
1767  case Hexagon::C4_cmplte:
1768  case Hexagon::C4_cmplteu:
1769  case Hexagon::C2_cmpeqi:
1770  case Hexagon::C2_cmpgti:
1771  case Hexagon::C2_cmpgtui:
1772  case Hexagon::C4_cmpneqi:
1773  case Hexagon::C4_cmplteui:
1774  case Hexagon::C4_cmpltei:
1775  SrcReg = MI.getOperand(1).getReg();
1776  Mask = ~0;
1777  break;
1778  case Hexagon::A4_cmpbeq:
1779  case Hexagon::A4_cmpbgt:
1780  case Hexagon::A4_cmpbgtu:
1781  case Hexagon::A4_cmpbeqi:
1782  case Hexagon::A4_cmpbgti:
1783  case Hexagon::A4_cmpbgtui:
1784  SrcReg = MI.getOperand(1).getReg();
1785  Mask = 0xFF;
1786  break;
1787  case Hexagon::A4_cmpheq:
1788  case Hexagon::A4_cmphgt:
1789  case Hexagon::A4_cmphgtu:
1790  case Hexagon::A4_cmpheqi:
1791  case Hexagon::A4_cmphgti:
1792  case Hexagon::A4_cmphgtui:
1793  SrcReg = MI.getOperand(1).getReg();
1794  Mask = 0xFFFF;
1795  break;
1796  }
1797 
1798  // Set the value/second source register.
1799  switch (Opc) {
1800  case Hexagon::C2_cmpeq:
1801  case Hexagon::C2_cmpeqp:
1802  case Hexagon::C2_cmpgt:
1803  case Hexagon::C2_cmpgtp:
1804  case Hexagon::C2_cmpgtu:
1805  case Hexagon::C2_cmpgtup:
1806  case Hexagon::A4_cmpbeq:
1807  case Hexagon::A4_cmpbgt:
1808  case Hexagon::A4_cmpbgtu:
1809  case Hexagon::A4_cmpheq:
1810  case Hexagon::A4_cmphgt:
1811  case Hexagon::A4_cmphgtu:
1812  case Hexagon::C4_cmpneq:
1813  case Hexagon::C4_cmplte:
1814  case Hexagon::C4_cmplteu:
1815  SrcReg2 = MI.getOperand(2).getReg();
1816  return true;
1817 
1818  case Hexagon::C2_cmpeqi:
1819  case Hexagon::C2_cmpgtui:
1820  case Hexagon::C2_cmpgti:
1821  case Hexagon::C4_cmpneqi:
1822  case Hexagon::C4_cmplteui:
1823  case Hexagon::C4_cmpltei:
1824  case Hexagon::A4_cmpbeqi:
1825  case Hexagon::A4_cmpbgti:
1826  case Hexagon::A4_cmpbgtui:
1827  case Hexagon::A4_cmpheqi:
1828  case Hexagon::A4_cmphgti:
1829  case Hexagon::A4_cmphgtui: {
1830  SrcReg2 = 0;
1831  const MachineOperand &Op2 = MI.getOperand(2);
1832  if (!Op2.isImm())
1833  return false;
1834  Value = MI.getOperand(2).getImm();
1835  return true;
1836  }
1837  }
1838 
1839  return false;
1840 }
1841 
1843  const MachineInstr &MI,
1844  unsigned *PredCost) const {
1845  return getInstrTimingClassLatency(ItinData, MI);
1846 }
1847 
1849  const TargetSubtargetInfo &STI) const {
1850  const InstrItineraryData *II = STI.getInstrItineraryData();
1851  return static_cast<const HexagonSubtarget&>(STI).createDFAPacketizer(II);
1852 }
1853 
1854 // Inspired by this pair:
1855 // %r13 = L2_loadri_io %r29, 136; mem:LD4[FixedStack0]
1856 // S2_storeri_io %r29, 132, killed %r1; flags: mem:ST4[FixedStack1]
1857 // Currently AA considers the addresses in these instructions to be aliasing.
1859  const MachineInstr &MIa, const MachineInstr &MIb,
1860  AliasAnalysis *AA) const {
1861  if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
1863  return false;
1864 
1865  // Instructions that are pure loads, not loads and stores like memops are not
1866  // dependent.
1867  if (MIa.mayLoad() && !isMemOp(MIa) && MIb.mayLoad() && !isMemOp(MIb))
1868  return true;
1869 
1870  // Get the base register in MIa.
1871  unsigned BasePosA, OffsetPosA;
1872  if (!getBaseAndOffsetPosition(MIa, BasePosA, OffsetPosA))
1873  return false;
1874  const MachineOperand &BaseA = MIa.getOperand(BasePosA);
1875  unsigned BaseRegA = BaseA.getReg();
1876  unsigned BaseSubA = BaseA.getSubReg();
1877 
1878  // Get the base register in MIb.
1879  unsigned BasePosB, OffsetPosB;
1880  if (!getBaseAndOffsetPosition(MIb, BasePosB, OffsetPosB))
1881  return false;
1882  const MachineOperand &BaseB = MIb.getOperand(BasePosB);
1883  unsigned BaseRegB = BaseB.getReg();
1884  unsigned BaseSubB = BaseB.getSubReg();
1885 
1886  if (BaseRegA != BaseRegB || BaseSubA != BaseSubB)
1887  return false;
1888 
1889  // Get the access sizes.
1890  unsigned SizeA = getMemAccessSize(MIa);
1891  unsigned SizeB = getMemAccessSize(MIb);
1892 
1893  // Get the offsets. Handle immediates only for now.
1894  const MachineOperand &OffA = MIa.getOperand(OffsetPosA);
1895  const MachineOperand &OffB = MIb.getOperand(OffsetPosB);
1896  if (!MIa.getOperand(OffsetPosA).isImm() ||
1897  !MIb.getOperand(OffsetPosB).isImm())
1898  return false;
1899  int OffsetA = isPostIncrement(MIa) ? 0 : OffA.getImm();
1900  int OffsetB = isPostIncrement(MIb) ? 0 : OffB.getImm();
1901 
1902  // This is a mem access with the same base register and known offsets from it.
1903  // Reason about it.
1904  if (OffsetA > OffsetB) {
1905  uint64_t OffDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
1906  return SizeB <= OffDiff;
1907  }
1908  if (OffsetA < OffsetB) {
1909  uint64_t OffDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
1910  return SizeA <= OffDiff;
1911  }
1912 
1913  return false;
1914 }
1915 
1916 /// If the instruction is an increment of a constant value, return the amount.
1918  int &Value) const {
1919  if (isPostIncrement(MI)) {
1920  unsigned BasePos = 0, OffsetPos = 0;
1921  if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
1922  return false;
1923  const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
1924  if (OffsetOp.isImm()) {
1925  Value = OffsetOp.getImm();
1926  return true;
1927  }
1928  } else if (MI.getOpcode() == Hexagon::A2_addi) {
1929  const MachineOperand &AddOp = MI.getOperand(2);
1930  if (AddOp.isImm()) {
1931  Value = AddOp.getImm();
1932  return true;
1933  }
1934  }
1935 
1936  return false;
1937 }
1938 
1939 std::pair<unsigned, unsigned>
1941  return std::make_pair(TF & ~HexagonII::MO_Bitmasks,
1942  TF & HexagonII::MO_Bitmasks);
1943 }
1944 
1947  using namespace HexagonII;
1948 
1949  static const std::pair<unsigned, const char*> Flags[] = {
1950  {MO_PCREL, "hexagon-pcrel"},
1951  {MO_GOT, "hexagon-got"},
1952  {MO_LO16, "hexagon-lo16"},
1953  {MO_HI16, "hexagon-hi16"},
1954  {MO_GPREL, "hexagon-gprel"},
1955  {MO_GDGOT, "hexagon-gdgot"},
1956  {MO_GDPLT, "hexagon-gdplt"},
1957  {MO_IE, "hexagon-ie"},
1958  {MO_IEGOT, "hexagon-iegot"},
1959  {MO_TPREL, "hexagon-tprel"}
1960  };
1961  return makeArrayRef(Flags);
1962 }
1963 
1966  using namespace HexagonII;
1967 
1968  static const std::pair<unsigned, const char*> Flags[] = {
1969  {HMOTF_ConstExtended, "hexagon-ext"}
1970  };
1971  return makeArrayRef(Flags);
1972 }
1973 
1976  const TargetRegisterClass *TRC;
1977  if (VT == MVT::i1) {
1978  TRC = &Hexagon::PredRegsRegClass;
1979  } else if (VT == MVT::i32 || VT == MVT::f32) {
1980  TRC = &Hexagon::IntRegsRegClass;
1981  } else if (VT == MVT::i64 || VT == MVT::f64) {
1982  TRC = &Hexagon::DoubleRegsRegClass;
1983  } else {
1984  llvm_unreachable("Cannot handle this register class");
1985  }
1986 
1987  unsigned NewReg = MRI.createVirtualRegister(TRC);
1988  return NewReg;
1989 }
1990 
1992  return (getAddrMode(MI) == HexagonII::AbsoluteSet);
1993 }
1994 
1996  const uint64_t F = MI.getDesc().TSFlags;
1998 }
1999 
2001  return getAddrMode(MI) == HexagonII::BaseImmOffset;
2002 }
2003 
2005  return !isTC1(MI) && !isTC2Early(MI) && !MI.getDesc().mayLoad() &&
2006  !MI.getDesc().mayStore() &&
2007  MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&
2008  MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&
2009  !isMemOp(MI) && !MI.isBranch() && !MI.isReturn() && !MI.isCall();
2010 }
2011 
2012 // Return true if the instruction is a compund branch instruction.
2014  return getType(MI) == HexagonII::TypeCJ && MI.isBranch();
2015 }
2016 
2017 // TODO: In order to have isExtendable for fpimm/f32Ext, we need to handle
2018 // isFPImm and later getFPImm as well.
2020  const uint64_t F = MI.getDesc().TSFlags;
2022  if (isExtended) // Instruction must be extended.
2023  return true;
2024 
2025  unsigned isExtendable =
2027  if (!isExtendable)
2028  return false;
2029 
2030  if (MI.isCall())
2031  return false;
2032 
2033  short ExtOpNum = getCExtOpNum(MI);
2034  const MachineOperand &MO = MI.getOperand(ExtOpNum);
2035  // Use MO operand flags to determine if MO
2036  // has the HMOTF_ConstExtended flag set.
2038  return true;
2039  // If this is a Machine BB address we are talking about, and it is
2040  // not marked as extended, say so.
2041  if (MO.isMBB())
2042  return false;
2043 
2044  // We could be using an instruction with an extendable immediate and shoehorn
2045  // a global address into it. If it is a global address it will be constant
2046  // extended. We do this for COMBINE.
2047  if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
2048  MO.isJTI() || MO.isCPI() || MO.isFPImm())
2049  return true;
2050 
2051  // If the extendable operand is not 'Immediate' type, the instruction should
2052  // have 'isExtended' flag set.
2053  assert(MO.isImm() && "Extendable operand must be Immediate type");
2054 
2055  int MinValue = getMinValue(MI);
2056  int MaxValue = getMaxValue(MI);
2057  int ImmValue = MO.getImm();
2058 
2059  return (ImmValue < MinValue || ImmValue > MaxValue);
2060 }
2061 
2063  switch (MI.getOpcode()) {
2064  case Hexagon::L4_return:
2065  case Hexagon::L4_return_t:
2066  case Hexagon::L4_return_f:
2067  case Hexagon::L4_return_tnew_pnt:
2068  case Hexagon::L4_return_fnew_pnt:
2069  case Hexagon::L4_return_tnew_pt:
2070  case Hexagon::L4_return_fnew_pt:
2071  return true;
2072  }
2073  return false;
2074 }
2075 
2076 // Return true when ConsMI uses a register defined by ProdMI.
2078  const MachineInstr &ConsMI) const {
2079  if (!ProdMI.getDesc().getNumDefs())
2080  return false;
2081  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
2082 
2087 
2088  parseOperands(ProdMI, DefsA, UsesA);
2089  parseOperands(ConsMI, DefsB, UsesB);
2090 
2091  for (auto &RegA : DefsA)
2092  for (auto &RegB : UsesB) {
2093  // True data dependency.
2094  if (RegA == RegB)
2095  return true;
2096 
2098  for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs)
2099  if (RegB == *SubRegs)
2100  return true;
2101 
2103  for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs)
2104  if (RegA == *SubRegs)
2105  return true;
2106  }
2107 
2108  return false;
2109 }
2110 
2111 // Returns true if the instruction is alread a .cur.
2113  switch (MI.getOpcode()) {
2114  case Hexagon::V6_vL32b_cur_pi:
2115  case Hexagon::V6_vL32b_cur_ai:
2116  return true;
2117  }
2118  return false;
2119 }
2120 
2121 // Returns true, if any one of the operands is a dot new
2122 // insn, whether it is predicated dot new or register dot new.
2124  if (isNewValueInst(MI) || (isPredicated(MI) && isPredicatedNew(MI)))
2125  return true;
2126 
2127  return false;
2128 }
2129 
2130 /// Symmetrical. See if these two instructions are fit for duplex pair.
2132  const MachineInstr &MIb) const {
2135  return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG));
2136 }
2137 
2139  if (MI.mayLoad() || MI.mayStore() || MI.isCompare())
2140  return true;
2141 
2142  // Multiply
2143  unsigned SchedClass = MI.getDesc().getSchedClass();
2144  return is_TC4x(SchedClass) || is_TC3x(SchedClass);
2145 }
2146 
2147 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
2148  return (Opcode == Hexagon::ENDLOOP0 ||
2149  Opcode == Hexagon::ENDLOOP1);
2150 }
2151 
2152 bool HexagonInstrInfo::isExpr(unsigned OpType) const {
2153  switch(OpType) {
2160  return true;
2161  default:
2162  return false;
2163  }
2164 }
2165 
2167  const MCInstrDesc &MID = MI.getDesc();
2168  const uint64_t F = MID.TSFlags;
2170  return true;
2171 
2172  // TODO: This is largely obsolete now. Will need to be removed
2173  // in consecutive patches.
2174  switch (MI.getOpcode()) {
2175  // PS_fi and PS_fia remain special cases.
2176  case Hexagon::PS_fi:
2177  case Hexagon::PS_fia:
2178  return true;
2179  default:
2180  return false;
2181  }
2182  return false;
2183 }
2184 
2185 // This returns true in two cases:
2186 // - The OP code itself indicates that this is an extended instruction.
2187 // - One of MOs has been marked with HMOTF_ConstExtended flag.
2189  // First check if this is permanently extended op code.
2190  const uint64_t F = MI.getDesc().TSFlags;
2192  return true;
2193  // Use MO operand flags to determine if one of MI's operands
2194  // has HMOTF_ConstExtended flag set.
2195  for (const MachineOperand &MO : MI.operands())
2196  if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
2197  return true;
2198  return false;
2199 }
2200 
2202  unsigned Opcode = MI.getOpcode();
2203  const uint64_t F = get(Opcode).TSFlags;
2204  return (F >> HexagonII::FPPos) & HexagonII::FPMask;
2205 }
2206 
2207 // No V60 HVX VMEM with A_INDIRECT.
2209  const MachineInstr &J) const {
2210  if (!isHVXVec(I))
2211  return false;
2212  if (!I.mayLoad() && !I.mayStore())
2213  return false;
2214  return J.isIndirectBranch() || isIndirectCall(J) || isIndirectL4Return(J);
2215 }
2216 
2218  switch (MI.getOpcode()) {
2219  case Hexagon::J2_callr:
2220  case Hexagon::J2_callrf:
2221  case Hexagon::J2_callrt:
2222  case Hexagon::PS_call_nr:
2223  return true;
2224  }
2225  return false;
2226 }
2227 
2229  switch (MI.getOpcode()) {
2230  case Hexagon::L4_return:
2231  case Hexagon::L4_return_t:
2232  case Hexagon::L4_return_f:
2233  case Hexagon::L4_return_fnew_pnt:
2234  case Hexagon::L4_return_fnew_pt:
2235  case Hexagon::L4_return_tnew_pnt:
2236  case Hexagon::L4_return_tnew_pt:
2237  return true;
2238  }
2239  return false;
2240 }
2241 
2243  switch (MI.getOpcode()) {
2244  case Hexagon::J2_jumpr:
2245  case Hexagon::J2_jumprt:
2246  case Hexagon::J2_jumprf:
2247  case Hexagon::J2_jumprtnewpt:
2248  case Hexagon::J2_jumprfnewpt:
2249  case Hexagon::J2_jumprtnew:
2250  case Hexagon::J2_jumprfnew:
2251  return true;
2252  }
2253  return false;
2254 }
2255 
2256 // Return true if a given MI can accommodate given offset.
2257 // Use abs estimate as oppose to the exact number.
2258 // TODO: This will need to be changed to use MC level
2259 // definition of instruction extendable field size.
2261  unsigned offset) const {
2262  // This selection of jump instructions matches to that what
2263  // analyzeBranch can parse, plus NVJ.
2264  if (isNewValueJump(MI)) // r9:2
2265  return isInt<11>(offset);
2266 
2267  switch (MI.getOpcode()) {
2268  // Still missing Jump to address condition on register value.
2269  default:
2270  return false;
2271  case Hexagon::J2_jump: // bits<24> dst; // r22:2
2272  case Hexagon::J2_call:
2273  case Hexagon::PS_call_nr:
2274  return isInt<24>(offset);
2275  case Hexagon::J2_jumpt: //bits<17> dst; // r15:2
2276  case Hexagon::J2_jumpf:
2277  case Hexagon::J2_jumptnew:
2278  case Hexagon::J2_jumptnewpt:
2279  case Hexagon::J2_jumpfnew:
2280  case Hexagon::J2_jumpfnewpt:
2281  case Hexagon::J2_callt:
2282  case Hexagon::J2_callf:
2283  return isInt<17>(offset);
2284  case Hexagon::J2_loop0i:
2285  case Hexagon::J2_loop0iext:
2286  case Hexagon::J2_loop0r:
2287  case Hexagon::J2_loop0rext:
2288  case Hexagon::J2_loop1i:
2289  case Hexagon::J2_loop1iext:
2290  case Hexagon::J2_loop1r:
2291  case Hexagon::J2_loop1rext:
2292  return isInt<9>(offset);
2293  // TODO: Add all the compound branches here. Can we do this in Relation model?
2294  case Hexagon::J4_cmpeqi_tp0_jump_nt:
2295  case Hexagon::J4_cmpeqi_tp1_jump_nt:
2296  case Hexagon::J4_cmpeqn1_tp0_jump_nt:
2297  case Hexagon::J4_cmpeqn1_tp1_jump_nt:
2298  return isInt<11>(offset);
2299  }
2300 }
2301 
2303  const MachineInstr &ESMI) const {
2304  bool isLate = isLateResultInstr(LRMI);
2305  bool isEarly = isEarlySourceInstr(ESMI);
2306 
2307  LLVM_DEBUG(dbgs() << "V60" << (isLate ? "-LR " : " -- "));
2308  LLVM_DEBUG(LRMI.dump());
2309  LLVM_DEBUG(dbgs() << "V60" << (isEarly ? "-ES " : " -- "));
2310  LLVM_DEBUG(ESMI.dump());
2311 
2312  if (isLate && isEarly) {
2313  LLVM_DEBUG(dbgs() << "++Is Late Result feeding Early Source\n");
2314  return true;
2315  }
2316 
2317  return false;
2318 }
2319 
2321  switch (MI.getOpcode()) {
2322  case TargetOpcode::EXTRACT_SUBREG:
2323  case TargetOpcode::INSERT_SUBREG:
2324  case TargetOpcode::SUBREG_TO_REG:
2325  case TargetOpcode::REG_SEQUENCE:
2326  case TargetOpcode::IMPLICIT_DEF:
2327  case TargetOpcode::COPY:
2329  case TargetOpcode::PHI:
2330  return false;
2331  default:
2332  break;
2333  }
2334 
2335  unsigned SchedClass = MI.getDesc().getSchedClass();
2336  return !is_TC1(SchedClass);
2337 }
2338 
2340  // Instructions with iclass A_CVI_VX and attribute A_CVI_LATE uses a multiply
2341  // resource, but all operands can be received late like an ALU instruction.
2342  return getType(MI) == HexagonII::TypeCVI_VX_LATE;
2343 }
2344 
2346  unsigned Opcode = MI.getOpcode();
2347  return Opcode == Hexagon::J2_loop0i ||
2348  Opcode == Hexagon::J2_loop0r ||
2349  Opcode == Hexagon::J2_loop0iext ||
2350  Opcode == Hexagon::J2_loop0rext ||
2351  Opcode == Hexagon::J2_loop1i ||
2352  Opcode == Hexagon::J2_loop1r ||
2353  Opcode == Hexagon::J2_loop1iext ||
2354  Opcode == Hexagon::J2_loop1rext;
2355 }
2356 
2358  switch (MI.getOpcode()) {
2359  default: return false;
2360  case Hexagon::L4_iadd_memopw_io:
2361  case Hexagon::L4_isub_memopw_io:
2362  case Hexagon::L4_add_memopw_io:
2363  case Hexagon::L4_sub_memopw_io:
2364  case Hexagon::L4_and_memopw_io:
2365  case Hexagon::L4_or_memopw_io:
2366  case Hexagon::L4_iadd_memoph_io:
2367  case Hexagon::L4_isub_memoph_io:
2368  case Hexagon::L4_add_memoph_io:
2369  case Hexagon::L4_sub_memoph_io:
2370  case Hexagon::L4_and_memoph_io:
2371  case Hexagon::L4_or_memoph_io:
2372  case Hexagon::L4_iadd_memopb_io:
2373  case Hexagon::L4_isub_memopb_io:
2374  case Hexagon::L4_add_memopb_io:
2375  case Hexagon::L4_sub_memopb_io:
2376  case Hexagon::L4_and_memopb_io:
2377  case Hexagon::L4_or_memopb_io:
2378  case Hexagon::L4_ior_memopb_io:
2379  case Hexagon::L4_ior_memoph_io:
2380  case Hexagon::L4_ior_memopw_io:
2381  case Hexagon::L4_iand_memopb_io:
2382  case Hexagon::L4_iand_memoph_io:
2383  case Hexagon::L4_iand_memopw_io:
2384  return true;
2385  }
2386  return false;
2387 }
2388 
2390  const uint64_t F = MI.getDesc().TSFlags;
2392 }
2393 
2394 bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
2395  const uint64_t F = get(Opcode).TSFlags;
2397 }
2398 
2400  return isNewValueJump(MI) || isNewValueStore(MI);
2401 }
2402 
2404  return isNewValue(MI) && MI.isBranch();
2405 }
2406 
2407 bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
2408  return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
2409 }
2410 
2412  const uint64_t F = MI.getDesc().TSFlags;
2414 }
2415 
2416 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
2417  const uint64_t F = get(Opcode).TSFlags;
2419 }
2420 
2421 // Returns true if a particular operand is extendable for an instruction.
2423  unsigned OperandNum) const {
2424  const uint64_t F = MI.getDesc().TSFlags;
2426  == OperandNum;
2427 }
2428 
2430  const uint64_t F = MI.getDesc().TSFlags;
2431  assert(isPredicated(MI));
2433 }
2434 
2435 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
2436  const uint64_t F = get(Opcode).TSFlags;
2437  assert(isPredicated(Opcode));
2439 }
2440 
2442  const uint64_t F = MI.getDesc().TSFlags;
2443  return !((F >> HexagonII::PredicatedFalsePos) &
2445 }
2446 
2447 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
2448  const uint64_t F = get(Opcode).TSFlags;
2449  // Make sure that the instruction is predicated.
2451  return !((F >> HexagonII::PredicatedFalsePos) &
2453 }
2454 
2455 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
2456  const uint64_t F = get(Opcode).TSFlags;
2458 }
2459 
2460 bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
2461  const uint64_t F = get(Opcode).TSFlags;
2463 }
2464 
2465 bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
2466  const uint64_t F = get(Opcode).TSFlags;
2467  assert(get(Opcode).isBranch() &&
2468  (isPredicatedNew(Opcode) || isNewValue(Opcode)));
2469  return (F >> HexagonII::TakenPos) & HexagonII::TakenMask;
2470 }
2471 
2473  return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2474  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2475  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2476  MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2477 }
2478 
2480  switch (MI.getOpcode()) {
2481  // Byte
2482  case Hexagon::L2_loadrb_io:
2483  case Hexagon::L4_loadrb_ur:
2484  case Hexagon::L4_loadrb_ap:
2485  case Hexagon::L2_loadrb_pr:
2486  case Hexagon::L2_loadrb_pbr:
2487  case Hexagon::L2_loadrb_pi:
2488  case Hexagon::L2_loadrb_pci:
2489  case Hexagon::L2_loadrb_pcr:
2490  case Hexagon::L2_loadbsw2_io:
2491  case Hexagon::L4_loadbsw2_ur:
2492  case Hexagon::L4_loadbsw2_ap:
2493  case Hexagon::L2_loadbsw2_pr:
2494  case Hexagon::L2_loadbsw2_pbr:
2495  case Hexagon::L2_loadbsw2_pi:
2496  case Hexagon::L2_loadbsw2_pci:
2497  case Hexagon::L2_loadbsw2_pcr:
2498  case Hexagon::L2_loadbsw4_io:
2499  case Hexagon::L4_loadbsw4_ur:
2500  case Hexagon::L4_loadbsw4_ap:
2501  case Hexagon::L2_loadbsw4_pr:
2502  case Hexagon::L2_loadbsw4_pbr:
2503  case Hexagon::L2_loadbsw4_pi:
2504  case Hexagon::L2_loadbsw4_pci:
2505  case Hexagon::L2_loadbsw4_pcr:
2506  case Hexagon::L4_loadrb_rr:
2507  case Hexagon::L2_ploadrbt_io:
2508  case Hexagon::L2_ploadrbt_pi:
2509  case Hexagon::L2_ploadrbf_io:
2510  case Hexagon::L2_ploadrbf_pi:
2511  case Hexagon::L2_ploadrbtnew_io:
2512  case Hexagon::L2_ploadrbfnew_io:
2513  case Hexagon::L4_ploadrbt_rr:
2514  case Hexagon::L4_ploadrbf_rr:
2515  case Hexagon::L4_ploadrbtnew_rr:
2516  case Hexagon::L4_ploadrbfnew_rr:
2517  case Hexagon::L2_ploadrbtnew_pi:
2518  case Hexagon::L2_ploadrbfnew_pi:
2519  case Hexagon::L4_ploadrbt_abs:
2520  case Hexagon::L4_ploadrbf_abs:
2521  case Hexagon::L4_ploadrbtnew_abs:
2522  case Hexagon::L4_ploadrbfnew_abs:
2523  case Hexagon::L2_loadrbgp:
2524  // Half
2525  case Hexagon::L2_loadrh_io:
2526  case Hexagon::L4_loadrh_ur:
2527  case Hexagon::L4_loadrh_ap:
2528  case Hexagon::L2_loadrh_pr:
2529  case Hexagon::L2_loadrh_pbr:
2530  case Hexagon::L2_loadrh_pi:
2531  case Hexagon::L2_loadrh_pci:
2532  case Hexagon::L2_loadrh_pcr:
2533  case Hexagon::L4_loadrh_rr:
2534  case Hexagon::L2_ploadrht_io:
2535  case Hexagon::L2_ploadrht_pi:
2536  case Hexagon::L2_ploadrhf_io:
2537  case Hexagon::L2_ploadrhf_pi:
2538  case Hexagon::L2_ploadrhtnew_io:
2539  case Hexagon::L2_ploadrhfnew_io:
2540  case Hexagon::L4_ploadrht_rr:
2541  case Hexagon::L4_ploadrhf_rr:
2542  case Hexagon::L4_ploadrhtnew_rr:
2543  case Hexagon::L4_ploadrhfnew_rr:
2544  case Hexagon::L2_ploadrhtnew_pi:
2545  case Hexagon::L2_ploadrhfnew_pi:
2546  case Hexagon::L4_ploadrht_abs:
2547  case Hexagon::L4_ploadrhf_abs:
2548  case Hexagon::L4_ploadrhtnew_abs:
2549  case Hexagon::L4_ploadrhfnew_abs:
2550  case Hexagon::L2_loadrhgp:
2551  return true;
2552  default:
2553  return false;
2554  }
2555 }
2556 
2558  const uint64_t F = MI.getDesc().TSFlags;
2559  return (F >> HexagonII::SoloPos) & HexagonII::SoloMask;
2560 }
2561 
2563  switch (MI.getOpcode()) {
2564  case Hexagon::STriw_pred:
2565  case Hexagon::LDriw_pred:
2566  return true;
2567  default:
2568  return false;
2569  }
2570 }
2571 
2573  if (!MI.isBranch())
2574  return false;
2575 
2576  for (auto &Op : MI.operands())
2577  if (Op.isGlobal() || Op.isSymbol())
2578  return true;
2579  return false;
2580 }
2581 
2582 // Returns true when SU has a timing class TC1.
2584  unsigned SchedClass = MI.getDesc().getSchedClass();
2585  return is_TC1(SchedClass);
2586 }
2587 
2589  unsigned SchedClass = MI.getDesc().getSchedClass();
2590  return is_TC2(SchedClass);
2591 }
2592 
2594  unsigned SchedClass = MI.getDesc().getSchedClass();
2595  return is_TC2early(SchedClass);
2596 }
2597 
2599  unsigned SchedClass = MI.getDesc().getSchedClass();
2600  return is_TC4x(SchedClass);
2601 }
2602 
2603 // Schedule this ASAP.
2605  const MachineInstr &MI2) const {
2606  if (mayBeCurLoad(MI1)) {
2607  // if (result of SU is used in Next) return true;
2608  unsigned DstReg = MI1.getOperand(0).getReg();
2609  int N = MI2.getNumOperands();
2610  for (int I = 0; I < N; I++)
2611  if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg())
2612  return true;
2613  }
2614  if (mayBeNewStore(MI2))
2615  if (MI2.getOpcode() == Hexagon::V6_vS32b_pi)
2616  if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() &&
2617  MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg())
2618  return true;
2619  return false;
2620 }
2621 
2623  const uint64_t V = getType(MI);
2625 }
2626 
2627 // Check if the Offset is a valid auto-inc imm by Load/Store Type.
2629  int Size = VT.getSizeInBits() / 8;
2630  if (Offset % Size != 0)
2631  return false;
2632  int Count = Offset / Size;
2633 
2634  switch (VT.getSimpleVT().SimpleTy) {
2635  // For scalars the auto-inc is s4
2636  case MVT::i8:
2637  case MVT::i16:
2638  case MVT::i32:
2639  case MVT::i64:
2640  case MVT::f32:
2641  case MVT::f64:
2642  case MVT::v2i16:
2643  case MVT::v2i32:
2644  case MVT::v4i8:
2645  case MVT::v4i16:
2646  case MVT::v8i8:
2647  return isInt<4>(Count);
2648  // For HVX vectors the auto-inc is s3
2649  case MVT::v64i8:
2650  case MVT::v32i16:
2651  case MVT::v16i32:
2652  case MVT::v8i64:
2653  case MVT::v128i8:
2654  case MVT::v64i16:
2655  case MVT::v32i32:
2656  case MVT::v16i64:
2657  return isInt<3>(Count);
2658  default:
2659  break;
2660  }
2661 
2662  llvm_unreachable("Not an valid type!");
2663 }
2664 
2665 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
2666  const TargetRegisterInfo *TRI, bool Extend) const {
2667  // This function is to check whether the "Offset" is in the correct range of
2668  // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
2669  // inserted to calculate the final address. Due to this reason, the function
2670  // assumes that the "Offset" has correct alignment.
2671  // We used to assert if the offset was not properly aligned, however,
2672  // there are cases where a misaligned pointer recast can cause this
2673  // problem, and we need to allow for it. The front end warns of such
2674  // misaligns with respect to load size.
2675  switch (Opcode) {
2676  case Hexagon::PS_vstorerq_ai:
2677  case Hexagon::PS_vstorerw_ai:
2678  case Hexagon::PS_vstorerw_nt_ai:
2679  case Hexagon::PS_vloadrq_ai:
2680  case Hexagon::PS_vloadrw_ai:
2681  case Hexagon::PS_vloadrw_nt_ai:
2682  case Hexagon::V6_vL32b_ai:
2683  case Hexagon::V6_vS32b_ai:
2684  case Hexagon::V6_vL32b_nt_ai:
2685  case Hexagon::V6_vS32b_nt_ai:
2686  case Hexagon::V6_vL32Ub_ai:
2687  case Hexagon::V6_vS32Ub_ai: {
2688  unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass);
2689  assert(isPowerOf2_32(VectorSize));
2690  if (Offset & (VectorSize-1))
2691  return false;
2692  return isInt<4>(Offset >> Log2_32(VectorSize));
2693  }
2694 
2695  case Hexagon::J2_loop0i:
2696  case Hexagon::J2_loop1i:
2697  return isUInt<10>(Offset);
2698 
2699  case Hexagon::S4_storeirb_io:
2700  case Hexagon::S4_storeirbt_io:
2701  case Hexagon::S4_storeirbf_io:
2702  return isUInt<6>(Offset);
2703 
2704  case Hexagon::S4_storeirh_io:
2705  case Hexagon::S4_storeirht_io:
2706  case Hexagon::S4_storeirhf_io:
2707  return isShiftedUInt<6,1>(Offset);
2708 
2709  case Hexagon::S4_storeiri_io:
2710  case Hexagon::S4_storeirit_io:
2711  case Hexagon::S4_storeirif_io:
2712  return isShiftedUInt<6,2>(Offset);
2713  }
2714 
2715  if (Extend)
2716  return true;
2717 
2718  switch (Opcode) {
2719  case Hexagon::L2_loadri_io:
2720  case Hexagon::S2_storeri_io:
2721  return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2722  (Offset <= Hexagon_MEMW_OFFSET_MAX);
2723 
2724  case Hexagon::L2_loadrd_io:
2725  case Hexagon::S2_storerd_io:
2726  return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2727  (Offset <= Hexagon_MEMD_OFFSET_MAX);
2728 
2729  case Hexagon::L2_loadrh_io:
2730  case Hexagon::L2_loadruh_io:
2731  case Hexagon::S2_storerh_io:
2732  case Hexagon::S2_storerf_io:
2733  return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2734  (Offset <= Hexagon_MEMH_OFFSET_MAX);
2735 
2736  case Hexagon::L2_loadrb_io:
2737  case Hexagon::L2_loadrub_io:
2738  case Hexagon::S2_storerb_io:
2739  return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2740  (Offset <= Hexagon_MEMB_OFFSET_MAX);
2741 
2742  case Hexagon::A2_addi:
2743  return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2744  (Offset <= Hexagon_ADDI_OFFSET_MAX);
2745 
2746  case Hexagon::L4_iadd_memopw_io:
2747  case Hexagon::L4_isub_memopw_io:
2748  case Hexagon::L4_add_memopw_io:
2749  case Hexagon::L4_sub_memopw_io:
2750  case Hexagon::L4_and_memopw_io:
2751  case Hexagon::L4_or_memopw_io:
2752  return (0 <= Offset && Offset <= 255);
2753 
2754  case Hexagon::L4_iadd_memoph_io:
2755  case Hexagon::L4_isub_memoph_io:
2756  case Hexagon::L4_add_memoph_io:
2757  case Hexagon::L4_sub_memoph_io:
2758  case Hexagon::L4_and_memoph_io:
2759  case Hexagon::L4_or_memoph_io:
2760  return (0 <= Offset && Offset <= 127);
2761 
2762  case Hexagon::L4_iadd_memopb_io:
2763  case Hexagon::L4_isub_memopb_io:
2764  case Hexagon::L4_add_memopb_io:
2765  case Hexagon::L4_sub_memopb_io:
2766  case Hexagon::L4_and_memopb_io:
2767  case Hexagon::L4_or_memopb_io:
2768  return (0 <= Offset && Offset <= 63);
2769 
2770  // LDriw_xxx and STriw_xxx are pseudo operations, so it has to take offset of
2771  // any size. Later pass knows how to handle it.
2772  case Hexagon::STriw_pred:
2773  case Hexagon::LDriw_pred:
2774  case Hexagon::STriw_ctr:
2775  case Hexagon::LDriw_ctr:
2776  return true;
2777 
2778  case Hexagon::PS_fi:
2779  case Hexagon::PS_fia:
2780  case Hexagon::INLINEASM:
2781  return true;
2782 
2783  case Hexagon::L2_ploadrbt_io:
2784  case Hexagon::L2_ploadrbf_io:
2785  case Hexagon::L2_ploadrubt_io:
2786  case Hexagon::L2_ploadrubf_io:
2787  case Hexagon::S2_pstorerbt_io:
2788  case Hexagon::S2_pstorerbf_io:
2789  return isUInt<6>(Offset);
2790 
2791  case Hexagon::L2_ploadrht_io:
2792  case Hexagon::L2_ploadrhf_io:
2793  case Hexagon::L2_ploadruht_io:
2794  case Hexagon::L2_ploadruhf_io:
2795  case Hexagon::S2_pstorerht_io:
2796  case Hexagon::S2_pstorerhf_io:
2797  return isShiftedUInt<6,1>(Offset);
2798 
2799  case Hexagon::L2_ploadrit_io:
2800  case Hexagon::L2_ploadrif_io:
2801  case Hexagon::S2_pstorerit_io:
2802  case Hexagon::S2_pstorerif_io:
2803  return isShiftedUInt<6,2>(Offset);
2804 
2805  case Hexagon::L2_ploadrdt_io:
2806  case Hexagon::L2_ploadrdf_io:
2807  case Hexagon::S2_pstorerdt_io:
2808  case Hexagon::S2_pstorerdf_io:
2809  return isShiftedUInt<6,3>(Offset);
2810  } // switch
2811 
2812  llvm_unreachable("No offset range is defined for this opcode. "
2813  "Please define it in the above switch statement!");
2814 }
2815 
2817  return isHVXVec(MI) && isAccumulator(MI);
2818 }
2819 
2821  const uint64_t F = get(MI.getOpcode()).TSFlags;
2822  const uint64_t V = ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
2823  return
2824  V == HexagonII::TypeCVI_VA ||
2826 }
2827 
2829  const MachineInstr &ConsMI) const {
2830  if (EnableACCForwarding && isVecAcc(ProdMI) && isVecAcc(ConsMI))
2831  return true;
2832 
2833  if (EnableALUForwarding && (isVecALU(ConsMI) || isLateSourceInstr(ConsMI)))
2834  return true;
2835 
2836  if (mayBeNewStore(ConsMI))
2837  return true;
2838 
2839  return false;
2840 }
2841 
2843  switch (MI.getOpcode()) {
2844  // Byte
2845  case Hexagon::L2_loadrub_io:
2846  case Hexagon::L4_loadrub_ur:
2847  case Hexagon::L4_loadrub_ap:
2848  case Hexagon::L2_loadrub_pr:
2849  case Hexagon::L2_loadrub_pbr:
2850  case Hexagon::L2_loadrub_pi:
2851  case Hexagon::L2_loadrub_pci:
2852  case Hexagon::L2_loadrub_pcr:
2853  case Hexagon::L2_loadbzw2_io:
2854  case Hexagon::L4_loadbzw2_ur:
2855  case Hexagon::L4_loadbzw2_ap:
2856  case Hexagon::L2_loadbzw2_pr:
2857  case Hexagon::L2_loadbzw2_pbr:
2858  case Hexagon::L2_loadbzw2_pi:
2859  case Hexagon::L2_loadbzw2_pci:
2860  case Hexagon::L2_loadbzw2_pcr:
2861  case Hexagon::L2_loadbzw4_io:
2862  case Hexagon::L4_loadbzw4_ur:
2863  case Hexagon::L4_loadbzw4_ap:
2864  case Hexagon::L2_loadbzw4_pr:
2865  case Hexagon::L2_loadbzw4_pbr:
2866  case Hexagon::L2_loadbzw4_pi:
2867  case Hexagon::L2_loadbzw4_pci:
2868  case Hexagon::L2_loadbzw4_pcr:
2869  case Hexagon::L4_loadrub_rr:
2870  case Hexagon::L2_ploadrubt_io:
2871  case Hexagon::L2_ploadrubt_pi:
2872  case Hexagon::L2_ploadrubf_io:
2873  case Hexagon::L2_ploadrubf_pi:
2874  case Hexagon::L2_ploadrubtnew_io:
2875  case Hexagon::L2_ploadrubfnew_io:
2876  case Hexagon::L4_ploadrubt_rr:
2877  case Hexagon::L4_ploadrubf_rr:
2878  case Hexagon::L4_ploadrubtnew_rr:
2879  case Hexagon::L4_ploadrubfnew_rr:
2880  case Hexagon::L2_ploadrubtnew_pi:
2881  case Hexagon::L2_ploadrubfnew_pi:
2882  case Hexagon::L4_ploadrubt_abs:
2883  case Hexagon::L4_ploadrubf_abs:
2884  case Hexagon::L4_ploadrubtnew_abs:
2885  case Hexagon::L4_ploadrubfnew_abs:
2886  case Hexagon::L2_loadrubgp:
2887  // Half
2888  case Hexagon::L2_loadruh_io:
2889  case Hexagon::L4_loadruh_ur:
2890  case Hexagon::L4_loadruh_ap:
2891  case Hexagon::L2_loadruh_pr:
2892  case Hexagon::L2_loadruh_pbr:
2893  case Hexagon::L2_loadruh_pi:
2894  case Hexagon::L2_loadruh_pci:
2895  case Hexagon::L2_loadruh_pcr:
2896  case Hexagon::L4_loadruh_rr:
2897  case Hexagon::L2_ploadruht_io:
2898  case Hexagon::L2_ploadruht_pi:
2899  case Hexagon::L2_ploadruhf_io:
2900  case Hexagon::L2_ploadruhf_pi:
2901  case Hexagon::L2_ploadruhtnew_io:
2902  case Hexagon::L2_ploadruhfnew_io:
2903  case Hexagon::L4_ploadruht_rr:
2904  case Hexagon::L4_ploadruhf_rr:
2905  case Hexagon::L4_ploadruhtnew_rr:
2906  case Hexagon::L4_ploadruhfnew_rr:
2907  case Hexagon::L2_ploadruhtnew_pi:
2908  case Hexagon::L2_ploadruhfnew_pi:
2909  case Hexagon::L4_ploadruht_abs:
2910  case Hexagon::L4_ploadruhf_abs:
2911  case Hexagon::L4_ploadruhtnew_abs:
2912  case Hexagon::L4_ploadruhfnew_abs:
2913  case Hexagon::L2_loadruhgp:
2914  return true;
2915  default:
2916  return false;
2917  }
2918 }
2919 
2920 // Add latency to instruction.
2922  const MachineInstr &MI2) const {
2923  if (isHVXVec(MI1) && isHVXVec(MI2))
2924  if (!isVecUsableNextPacket(MI1, MI2))
2925  return true;
2926  return false;
2927 }
2928 
2929 /// Get the base register and byte offset of a load/store instr.
2931  const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset,
2932  const TargetRegisterInfo *TRI) const {
2933  unsigned AccessSize = 0;
2934  BaseOp = getBaseAndOffset(LdSt, Offset, AccessSize);
2935  assert((!BaseOp || BaseOp->isReg()) &&
2936  "getMemOperandWithOffset only supports base "
2937  "operands of type register.");
2938  return BaseOp != nullptr;
2939 }
2940 
2941 /// Can these instructions execute at the same time in a bundle.
2943  const MachineInstr &Second) const {
2944  if (Second.mayStore() && First.getOpcode() == Hexagon::S2_allocframe) {
2945  const MachineOperand &Op = Second.getOperand(0);
2946  if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29)
2947  return true;
2948  }
2949  if (DisableNVSchedule)
2950  return false;
2951  if (mayBeNewStore(Second)) {
2952  // Make sure the definition of the first instruction is the value being
2953  // stored.
2954  const MachineOperand &Stored =
2955  Second.getOperand(Second.getNumOperands() - 1);
2956  if (!Stored.isReg())
2957  return false;
2958  for (unsigned i = 0, e = First.getNumOperands(); i < e; ++i) {
2959  const MachineOperand &Op = First.getOperand(i);
2960  if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
2961  return true;
2962  }
2963  }
2964  return false;
2965 }
2966 
2968  unsigned Opc = CallMI.getOpcode();
2969  return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
2970 }
2971 
2973  for (auto &I : *B)
2974  if (I.isEHLabel())
2975  return true;
2976  return false;
2977 }
2978 
2979 // Returns true if an instruction can be converted into a non-extended
2980 // equivalent instruction.
2982  short NonExtOpcode;
2983  // Check if the instruction has a register form that uses register in place
2984  // of the extended operand, if so return that as the non-extended form.
2985  if (Hexagon::getRegForm(MI.getOpcode()) >= 0)
2986  return true;
2987 
2988  if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
2989  // Check addressing mode and retrieve non-ext equivalent instruction.
2990 
2991  switch (getAddrMode(MI)) {
2992  case HexagonII::Absolute:
2993  // Load/store with absolute addressing mode can be converted into
2994  // base+offset mode.
2995  NonExtOpcode = Hexagon::changeAddrMode_abs_io(MI.getOpcode());
2996  break;
2998  // Load/store with base+offset addressing mode can be converted into
2999  // base+register offset addressing mode. However left shift operand should
3000  // be set to 0.
3001  NonExtOpcode = Hexagon::changeAddrMode_io_rr(MI.getOpcode());
3002  break;
3004  NonExtOpcode = Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
3005  break;
3006  default:
3007  return false;
3008  }
3009  if (NonExtOpcode < 0)
3010  return false;
3011  return true;
3012  }
3013  return false;
3014 }
3015 
3017  return Hexagon::getRealHWInstr(MI.getOpcode(),
3018  Hexagon::InstrType_Pseudo) >= 0;
3019 }
3020 
3022  const {
3024  while (I != E) {
3025  if (I->isBarrier())
3026  return true;
3027  ++I;
3028  }
3029  return false;
3030 }
3031 
3032 // Returns true, if a LD insn can be promoted to a cur load.
3034  const uint64_t F = MI.getDesc().TSFlags;
3036  Subtarget.hasV60Ops();
3037 }
3038 
3039 // Returns true, if a ST insn can be promoted to a new-value store.
3041  if (MI.mayStore() && !Subtarget.useNewValueStores())
3042  return false;
3043 
3044  const uint64_t F = MI.getDesc().TSFlags;
3046 }
3047 
3049  const MachineInstr &ConsMI) const {
3050  // There is no stall when ProdMI is not a V60 vector.
3051  if (!isHVXVec(ProdMI))
3052  return false;
3053 
3054  // There is no stall when ProdMI and ConsMI are not dependent.
3055  if (!isDependent(ProdMI, ConsMI))
3056  return false;
3057 
3058  // When Forward Scheduling is enabled, there is no stall if ProdMI and ConsMI
3059  // are scheduled in consecutive packets.
3060  if (isVecUsableNextPacket(ProdMI, ConsMI))
3061  return false;
3062 
3063  return true;
3064 }
3065 
3068  // There is no stall when I is not a V60 vector.
3069  if (!isHVXVec(MI))
3070  return false;
3071 
3073  MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end();
3074 
3075  if (!MII->isBundle())
3076  return producesStall(*MII, MI);
3077 
3078  for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
3079  const MachineInstr &J = *MII;
3080  if (producesStall(J, MI))
3081  return true;
3082  }
3083  return false;
3084 }
3085 
3087  unsigned PredReg) const {
3088  for (const MachineOperand &MO : MI.operands()) {
3089  // Predicate register must be explicitly defined.
3090  if (MO.isRegMask() && MO.clobbersPhysReg(PredReg))
3091  return false;
3092  if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
3093  return false;
3094  }
3095 
3096  // Instruction that produce late predicate cannot be used as sources of
3097  // dot-new.
3098  switch (MI.getOpcode()) {
3099  case Hexagon::A4_addp_c:
3100  case Hexagon::A4_subp_c:
3101  case Hexagon::A4_tlbmatch:
3102  case Hexagon::A5_ACS:
3103  case Hexagon::F2_sfinvsqrta:
3104  case Hexagon::F2_sfrecipa:
3105  case Hexagon::J2_endloop0:
3106  case Hexagon::J2_endloop01:
3107  case Hexagon::J2_ploop1si:
3108  case Hexagon::J2_ploop1sr:
3109  case Hexagon::J2_ploop2si:
3110  case Hexagon::J2_ploop2sr:
3111  case Hexagon::J2_ploop3si:
3112  case Hexagon::J2_ploop3sr:
3113  case Hexagon::S2_cabacdecbin:
3114  case Hexagon::S2_storew_locked:
3115  case Hexagon::S4_stored_locked:
3116  return false;
3117  }
3118  return true;
3119 }
3120 
3121 bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
3122  return Opcode == Hexagon::J2_jumpt ||
3123  Opcode == Hexagon::J2_jumptpt ||
3124  Opcode == Hexagon::J2_jumpf ||
3125  Opcode == Hexagon::J2_jumpfpt ||
3126  Opcode == Hexagon::J2_jumptnew ||
3127  Opcode == Hexagon::J2_jumpfnew ||
3128  Opcode == Hexagon::J2_jumptnewpt ||
3129  Opcode == Hexagon::J2_jumpfnewpt;
3130 }
3131 
3133  if (Cond.empty() || !isPredicated(Cond[0].getImm()))
3134  return false;
3135  return !isPredicatedTrue(Cond[0].getImm());
3136 }
3137 
3139  const uint64_t F = MI.getDesc().TSFlags;
3141 }
3142 
3143 // Returns the base register in a memory access (load/store). The offset is
3144 // returned in Offset and the access size is returned in AccessSize.
3145 // If the base operand has a subregister or the offset field does not contain
3146 // an immediate value, return nullptr.
3148  int64_t &Offset,
3149  unsigned &AccessSize) const {
3150  // Return if it is not a base+offset type instruction or a MemOp.
3153  !isMemOp(MI) && !isPostIncrement(MI))
3154  return nullptr;
3155 
3156  AccessSize = getMemAccessSize(MI);
3157 
3158  unsigned BasePos = 0, OffsetPos = 0;
3159  if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
3160  return nullptr;
3161 
3162  // Post increment updates its EA after the mem access,
3163  // so we need to treat its offset as zero.
3164  if (isPostIncrement(MI)) {
3165  Offset = 0;
3166  } else {
3167  const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
3168  if (!OffsetOp.isImm())
3169  return nullptr;
3170  Offset = OffsetOp.getImm();
3171  }
3172 
3173  const MachineOperand &BaseOp = MI.getOperand(BasePos);
3174  if (BaseOp.getSubReg() != 0)
3175  return nullptr;
3176  return &const_cast<MachineOperand&>(BaseOp);
3177 }
3178 
3179 /// Return the position of the base and offset operands for this instruction.
3181  unsigned &BasePos, unsigned &OffsetPos) const {
3182  if (!isAddrModeWithOffset(MI) && !isPostIncrement(MI))
3183  return false;
3184 
3185  // Deal with memops first.
3186  if (isMemOp(MI)) {
3187  BasePos = 0;
3188  OffsetPos = 1;
3189  } else if (MI.mayStore()) {
3190  BasePos = 0;
3191  OffsetPos = 1;
3192  } else if (MI.mayLoad()) {
3193  BasePos = 1;
3194  OffsetPos = 2;
3195  } else
3196  return false;
3197 
3198  if (isPredicated(MI)) {
3199  BasePos++;
3200  OffsetPos++;
3201  }
3202  if (isPostIncrement(MI)) {
3203  BasePos++;
3204  OffsetPos++;
3205  }
3206 
3207  if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
3208  return false;
3209 
3210  return true;
3211 }
3212 
3213 // Inserts branching instructions in reverse order of their occurrence.
3214 // e.g. jump_t t1 (i1)
3215 // jump t2 (i2)
3216 // Jumpers = {i2, i1}
3218  MachineBasicBlock& MBB) const {
3220  // If the block has no terminators, it just falls into the block after it.
3222  if (I == MBB.instr_begin())
3223  return Jumpers;
3224 
3225  // A basic block may looks like this:
3226  //
3227  // [ insn
3228  // EH_LABEL
3229  // insn
3230  // insn
3231  // insn
3232  // EH_LABEL
3233  // insn ]
3234  //
3235  // It has two succs but does not have a terminator
3236  // Don't know how to handle it.
3237  do {
3238  --I;
3239  if (I->isEHLabel())
3240  return Jumpers;
3241  } while (I != MBB.instr_begin());
3242 
3243  I = MBB.instr_end();
3244  --I;
3245 
3246  while (I->isDebugInstr()) {
3247  if (I == MBB.instr_begin())
3248  return Jumpers;
3249  --I;
3250  }
3251  if (!isUnpredicatedTerminator(*I))
3252  return Jumpers;
3253 
3254  // Get the last instruction in the block.
3255  MachineInstr *LastInst = &*I;
3256  Jumpers.push_back(LastInst);
3257  MachineInstr *SecondLastInst = nullptr;
3258  // Find one more terminator if present.
3259  do {
3260  if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
3261  if (!SecondLastInst) {
3262  SecondLastInst = &*I;
3263  Jumpers.push_back(SecondLastInst);
3264  } else // This is a third branch.
3265  return Jumpers;
3266  }
3267  if (I == MBB.instr_begin())
3268  break;
3269  --I;
3270  } while (true);
3271  return Jumpers;
3272 }
3273 
3274 // Returns Operand Index for the constant extended instruction.
3276  const uint64_t F = MI.getDesc().TSFlags;
3278 }
3279 
3280 // See if instruction could potentially be a duplex candidate.
3281 // If so, return its group. Zero otherwise.
3283  const MachineInstr &MI) const {
3284  unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3285 
3286  switch (MI.getOpcode()) {
3287  default:
3288  return HexagonII::HCG_None;
3289  //
3290  // Compound pairs.
3291  // "p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2"
3292  // "Rd16=#U6 ; jump #r9:2"
3293  // "Rd16=Rs16 ; jump #r9:2"
3294  //
3295  case Hexagon::C2_cmpeq:
3296  case Hexagon::C2_cmpgt:
3297  case Hexagon::C2_cmpgtu:
3298  DstReg = MI.getOperand(0).getReg();
3299  Src1Reg = MI.getOperand(1).getReg();
3300  Src2Reg = MI.getOperand(2).getReg();
3301  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3302  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3303  isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
3304  return HexagonII::HCG_A;
3305  break;
3306  case Hexagon::C2_cmpeqi:
3307  case Hexagon::C2_cmpgti:
3308  case Hexagon::C2_cmpgtui:
3309  // P0 = cmp.eq(Rs,#u2)
3310  DstReg = MI.getOperand(0).getReg();
3311  SrcReg = MI.getOperand(1).getReg();
3312  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3313  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3314  isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3315  ((isUInt<5>(MI.getOperand(2).getImm())) ||
3316  (MI.getOperand(2).getImm() == -1)))
3317  return HexagonII::HCG_A;
3318  break;
3319  case Hexagon::A2_tfr:
3320  // Rd = Rs
3321  DstReg = MI.getOperand(0).getReg();
3322  SrcReg = MI.getOperand(1).getReg();
3323  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3324  return HexagonII::HCG_A;
3325  break;
3326  case Hexagon::A2_tfrsi:
3327  // Rd = #u6
3328  // Do not test for #u6 size since the const is getting extended
3329  // regardless and compound could be formed.
3330  DstReg = MI.getOperand(0).getReg();
3331  if (isIntRegForSubInst(DstReg))
3332  return HexagonII::HCG_A;
3333  break;
3334  case Hexagon::S2_tstbit_i:
3335  DstReg = MI.getOperand(0).getReg();
3336  Src1Reg = MI.getOperand(1).getReg();
3337  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3338  (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3339  MI.getOperand(2).isImm() &&
3340  isIntRegForSubInst(Src1Reg) && (MI.getOperand(2).getImm() == 0))
3341  return HexagonII::HCG_A;
3342  break;
3343  // The fact that .new form is used pretty much guarantees
3344  // that predicate register will match. Nevertheless,
3345  // there could be some false positives without additional
3346  // checking.
3347  case Hexagon::J2_jumptnew:
3348  case Hexagon::J2_jumpfnew:
3349  case Hexagon::J2_jumptnewpt:
3350  case Hexagon::J2_jumpfnewpt:
3351  Src1Reg = MI.getOperand(0).getReg();
3352  if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
3353  (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3354  return HexagonII::HCG_B;
3355  break;
3356  // Transfer and jump:
3357  // Rd=#U6 ; jump #r9:2
3358  // Rd=Rs ; jump #r9:2
3359  // Do not test for jump range here.
3360  case Hexagon::J2_jump:
3361  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3362  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3363  return HexagonII::HCG_C;
3364  }
3365 
3366  return HexagonII::HCG_None;
3367 }
3368 
3369 // Returns -1 when there is no opcode found.
3371  const MachineInstr &GB) const {
3374  if ((GA.getOpcode() != Hexagon::C2_cmpeqi) ||
3375  (GB.getOpcode() != Hexagon::J2_jumptnew))
3376  return -1u;
3377  unsigned DestReg = GA.getOperand(0).getReg();
3378  if (!GB.readsRegister(DestReg))
3379  return -1u;
3380  if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1)
3381  return -1u;
3382  // The value compared against must be either u5 or -1.
3383  const MachineOperand &CmpOp = GA.getOperand(2);
3384  if (!CmpOp.isImm())
3385  return -1u;
3386  int V = CmpOp.getImm();
3387  if (V == -1)
3388  return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt
3389  : Hexagon::J4_cmpeqn1_tp1_jump_nt;
3390  if (!isUInt<5>(V))
3391  return -1u;
3392  return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt
3393  : Hexagon::J4_cmpeqi_tp1_jump_nt;
3394 }
3395 
3396 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
3397  enum Hexagon::PredSense inPredSense;
3398  inPredSense = invertPredicate ? Hexagon::PredSense_false :
3399  Hexagon::PredSense_true;
3400  int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
3401  if (CondOpcode >= 0) // Valid Conditional opcode/instruction
3402  return CondOpcode;
3403 
3404  llvm_unreachable("Unexpected predicable instruction");
3405 }
3406 
3407 // Return the cur value instruction for a given store.
3409  switch (MI.getOpcode()) {
3410  default: llvm_unreachable("Unknown .cur type");
3411  case Hexagon::V6_vL32b_pi:
3412  return Hexagon::V6_vL32b_cur_pi;
3413  case Hexagon::V6_vL32b_ai:
3414  return Hexagon::V6_vL32b_cur_ai;
3415  case Hexagon::V6_vL32b_nt_pi:
3416  return Hexagon::V6_vL32b_nt_cur_pi;
3417  case Hexagon::V6_vL32b_nt_ai:
3418  return Hexagon::V6_vL32b_nt_cur_ai;
3419  }
3420  return 0;
3421 }
3422 
3423 // Return the regular version of the .cur instruction.
3425  switch (MI.getOpcode()) {
3426  default: llvm_unreachable("Unknown .cur type");
3427  case Hexagon::V6_vL32b_cur_pi:
3428  return Hexagon::V6_vL32b_pi;
3429  case Hexagon::V6_vL32b_cur_ai:
3430  return Hexagon::V6_vL32b_ai;
3431  case Hexagon::V6_vL32b_nt_cur_pi:
3432  return Hexagon::V6_vL32b_nt_pi;
3433  case Hexagon::V6_vL32b_nt_cur_ai:
3434  return Hexagon::V6_vL32b_nt_ai;
3435  }
3436  return 0;
3437 }
3438 
3439 // The diagram below shows the steps involved in the conversion of a predicated
3440 // store instruction to its .new predicated new-value form.
3441 //
3442 // Note: It doesn't include conditional new-value stores as they can't be
3443 // converted to .new predicate.
3444 //
3445 // p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
3446 // ^ ^
3447 // / \ (not OK. it will cause new-value store to be
3448 // / X conditional on p0.new while R2 producer is
3449 // / \ on p0)
3450 // / \.
3451 // p.new store p.old NV store
3452 // [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
3453 // ^ ^
3454 // \ /
3455 // \ /
3456 // \ /
3457 // p.old store
3458 // [if (p0)memw(R0+#0)=R2]
3459 //
3460 // The following set of instructions further explains the scenario where
3461 // conditional new-value store becomes invalid when promoted to .new predicate
3462 // form.
3463 //
3464 // { 1) if (p0) r0 = add(r1, r2)
3465 // 2) p0 = cmp.eq(r3, #0) }
3466 //
3467 // 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
3468 // the first two instructions because in instr 1, r0 is conditional on old value
3469 // of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
3470 // is not valid for new-value stores.
3471 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
3472 // from the "Conditional Store" list. Because a predicated new value store
3473 // would NOT be promoted to a double dot new store. See diagram below:
3474 // This function returns yes for those stores that are predicated but not
3475 // yet promoted to predicate dot new instructions.
3476 //
3477 // +---------------------+
3478 // /-----| if (p0) memw(..)=r0 |---------\~
3479 // || +---------------------+ ||
3480 // promote || /\ /\ || promote
3481 // || /||\ /||\ ||
3482 // \||/ demote || \||/
3483 // \/ || || \/
3484 // +-------------------------+ || +-------------------------+
3485 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
3486 // +-------------------------+ || +-------------------------+
3487 // || || ||
3488 // || demote \||/
3489 // promote || \/ NOT possible
3490 // || || /\~
3491 // \||/ || /||\~
3492 // \/ || ||
3493 // +-----------------------------+
3494 // | if (p0.new) memw(..)=r0.new |
3495 // +-----------------------------+
3496 // Double Dot New Store
3497 //
3498 // Returns the most basic instruction for the .new predicated instructions and
3499 // new-value stores.
3500 // For example, all of the following instructions will be converted back to the
3501 // same instruction:
3502 // 1) if (p0.new) memw(R0+#0) = R1.new --->
3503 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
3504 // 3) if (p0.new) memw(R0+#0) = R1 --->
3505 //
3506 // To understand the translation of instruction 1 to its original form, consider
3507 // a packet with 3 instructions.
3508 // { p0 = cmp.eq(R0,R1)
3509 // if (p0.new) R2 = add(R3, R4)
3510 // R5 = add (R3, R1)
3511 // }
3512 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
3513 //
3514 // This instruction can be part of the previous packet only if both p0 and R2
3515 // are promoted to .new values. This promotion happens in steps, first
3516 // predicate register is promoted to .new and in the next iteration R2 is
3517 // promoted. Therefore, in case of dependence check failure (due to R5) during
3518 // next iteration, it should be converted back to its most basic form.
3519 
3520 // Return the new value instruction for a given store.
3522  int NVOpcode = Hexagon::getNewValueOpcode(MI.getOpcode());
3523  if (NVOpcode >= 0) // Valid new-value store instruction.
3524  return NVOpcode;
3525 
3526  switch (MI.getOpcode()) {
3527  default:
3528  report_fatal_error(std::string("Unknown .new type: ") +
3529  std::to_string(MI.getOpcode()));
3530  case Hexagon::S4_storerb_ur:
3531  return Hexagon::S4_storerbnew_ur;
3532 
3533  case Hexagon::S2_storerb_pci:
3534  return Hexagon::S2_storerb_pci;
3535 
3536  case Hexagon::S2_storeri_pci:
3537  return Hexagon::S2_storeri_pci;
3538 
3539  case Hexagon::S2_storerh_pci:
3540  return Hexagon::S2_storerh_pci;
3541 
3542  case Hexagon::S2_storerd_pci:
3543  return Hexagon::S2_storerd_pci;
3544 
3545  case Hexagon::S2_storerf_pci:
3546  return Hexagon::S2_storerf_pci;
3547 
3548  case Hexagon::V6_vS32b_ai:
3549  return Hexagon::V6_vS32b_new_ai;
3550 
3551  case Hexagon::V6_vS32b_pi:
3552  return Hexagon::V6_vS32b_new_pi;
3553  }
3554  return 0;
3555 }
3556 
3557 // Returns the opcode to use when converting MI, which is a conditional jump,
3558 // into a conditional instruction which uses the .new value of the predicate.
3559 // We also use branch probabilities to add a hint to the jump.
3560 // If MBPI is null, all edges will be treated as equally likely for the
3561 // purposes of establishing a predication hint.
3563  const MachineBranchProbabilityInfo *MBPI) const {
3564  // We assume that block can have at most two successors.
3565  const MachineBasicBlock *Src = MI.getParent();
3566  const MachineOperand &BrTarget = MI.getOperand(1);
3567  bool Taken = false;
3568  const BranchProbability OneHalf(1, 2);
3569 
3570  auto getEdgeProbability = [MBPI] (const MachineBasicBlock *Src,
3571  const MachineBasicBlock *Dst) {
3572  if (MBPI)
3573  return MBPI->getEdgeProbability(Src, Dst);
3574  return BranchProbability(1, Src->succ_size());
3575  };
3576 
3577  if (BrTarget.isMBB()) {
3578  const MachineBasicBlock *Dst = BrTarget.getMBB();
3579  Taken = getEdgeProbability(Src, Dst) >= OneHalf;
3580  } else {
3581  // The branch target is not a basic block (most likely a function).
3582  // Since BPI only gives probabilities for targets that are basic blocks,
3583  // try to identify another target of this branch (potentially a fall-
3584  // -through) and check the probability of that target.
3585  //
3586  // The only handled branch combinations are:
3587  // - one conditional branch,
3588  // - one conditional branch followed by one unconditional branch.
3589  // Otherwise, assume not-taken.
3591  const MachineBasicBlock &B = *MI.getParent();
3592  bool SawCond = false, Bad = false;
3593  for (const MachineInstr &I : B) {
3594  if (!I.isBranch())
3595  continue;
3596  if (I.isConditionalBranch()) {
3597  SawCond = true;
3598  if (&I != &MI) {
3599  Bad = true;
3600  break;
3601  }
3602  }
3603  if (I.isUnconditionalBranch() && !SawCond) {
3604  Bad = true;
3605  break;
3606  }
3607  }
3608  if (!Bad) {
3610  MachineBasicBlock::const_instr_iterator NextIt = std::next(It);
3611  if (NextIt == B.instr_end()) {
3612  // If this branch is the last, look for the fall-through block.
3613  for (const MachineBasicBlock *SB : B.successors()) {
3614  if (!B.isLayoutSuccessor(SB))
3615  continue;
3616  Taken = getEdgeProbability(Src, SB) < OneHalf;
3617  break;
3618  }
3619  } else {
3620  assert(NextIt->isUnconditionalBranch());
3621  // Find the first MBB operand and assume it's the target.
3622  const MachineBasicBlock *BT = nullptr;
3623  for (const MachineOperand &Op : NextIt->operands()) {
3624  if (!Op.isMBB())
3625  continue;
3626  BT = Op.getMBB();
3627  break;
3628  }
3629  Taken = BT && getEdgeProbability(Src, BT) < OneHalf;
3630  }
3631  } // if (!Bad)
3632  }
3633 
3634  // The Taken flag should be set to something reasonable by this point.
3635 
3636  switch (MI.getOpcode()) {
3637  case Hexagon::J2_jumpt:
3638  return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3639  case Hexagon::J2_jumpf:
3640  return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3641 
3642  default:
3643  llvm_unreachable("Unexpected jump instruction.");
3644  }
3645 }
3646 
3647 // Return .new predicate version for an instruction.
3649  const MachineBranchProbabilityInfo *MBPI) const {
3650  switch (MI.getOpcode()) {
3651  // Condtional Jumps
3652  case Hexagon::J2_jumpt:
3653  case Hexagon::J2_jumpf:
3654  return getDotNewPredJumpOp(MI, MBPI);
3655  }
3656 
3657  int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode());
3658  if (NewOpcode >= 0)
3659  return NewOpcode;
3660  return 0;
3661 }
3662 
3664  int NewOp = MI.getOpcode();
3665  if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
3666  NewOp = Hexagon::getPredOldOpcode(NewOp);
3667  // All Hexagon architectures have prediction bits on dot-new branches,
3668  // but only Hexagon V60+ has prediction bits on dot-old ones. Make sure
3669  // to pick the right opcode when converting back to dot-old.
3670  if (!Subtarget.getFeatureBits()[Hexagon::ArchV60]) {
3671  switch (NewOp) {
3672  case Hexagon::J2_jumptpt:
3673  NewOp = Hexagon::J2_jumpt;
3674  break;
3675  case Hexagon::J2_jumpfpt:
3676  NewOp = Hexagon::J2_jumpf;
3677  break;
3678  case Hexagon::J2_jumprtpt:
3679  NewOp = Hexagon::J2_jumprt;
3680  break;
3681  case Hexagon::J2_jumprfpt:
3682  NewOp = Hexagon::J2_jumprf;
3683  break;
3684  }
3685  }
3686  assert(NewOp >= 0 &&
3687  "Couldn't change predicate new instruction to its old form.");
3688  }
3689 
3690  if (isNewValueStore(NewOp)) { // Convert into non-new-value format
3691  NewOp = Hexagon::getNonNVStore(NewOp);
3692  assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
3693  }
3694 
3695  if (Subtarget.hasV60Ops())
3696  return NewOp;
3697 
3698  // Subtargets prior to V60 didn't support 'taken' forms of predicated jumps.
3699  switch (NewOp) {
3700  case Hexagon::J2_jumpfpt:
3701  return Hexagon::J2_jumpf;
3702  case Hexagon::J2_jumptpt:
3703  return Hexagon::J2_jumpt;
3704  case Hexagon::J2_jumprfpt:
3705  return Hexagon::J2_jumprf;
3706  case Hexagon::J2_jumprtpt:
3707  return Hexagon::J2_jumprt;
3708  }
3709  return NewOp;
3710 }
3711 
3712 // See if instruction could potentially be a duplex candidate.
3713 // If so, return its group. Zero otherwise.
3715  const MachineInstr &MI) const {
3716  unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3717  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
3718 
3719  switch (MI.getOpcode()) {
3720  default:
3721  return HexagonII::HSIG_None;
3722  //
3723  // Group L1:
3724  //
3725  // Rd = memw(Rs+#u4:2)
3726  // Rd = memub(Rs+#u4:0)
3727  case Hexagon::L2_loadri_io:
3728  DstReg = MI.getOperand(0).getReg();
3729  SrcReg = MI.getOperand(1).getReg();
3730  // Special case this one from Group L2.
3731  // Rd = memw(r29+#u5:2)
3732  if (isIntRegForSubInst(DstReg)) {
3733  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3734  HRI.getStackRegister() == SrcReg &&
3735  MI.getOperand(2).isImm() &&
3736  isShiftedUInt<5,2>(MI.getOperand(2).getImm()))
3737  return HexagonII::HSIG_L2;
3738  // Rd = memw(Rs+#u4:2)
3739  if (isIntRegForSubInst(SrcReg) &&
3740  (MI.getOperand(2).isImm() &&
3741  isShiftedUInt<4,2>(MI.getOperand(2).getImm())))
3742  return HexagonII::HSIG_L1;
3743  }
3744  break;
3745  case Hexagon::L2_loadrub_io:
3746  // Rd = memub(Rs+#u4:0)
3747  DstReg = MI.getOperand(0).getReg();
3748  SrcReg = MI.getOperand(1).getReg();
3749  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3750  MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm()))
3751  return HexagonII::HSIG_L1;
3752  break;
3753  //
3754  // Group L2:
3755  //
3756  // Rd = memh/memuh(Rs+#u3:1)
3757  // Rd = memb(Rs+#u3:0)
3758  // Rd = memw(r29+#u5:2) - Handled above.
3759  // Rdd = memd(r29+#u5:3)
3760  // deallocframe
3761  // [if ([!]p0[.new])] dealloc_return
3762  // [if ([!]p0[.new])] jumpr r31
3763  case Hexagon::L2_loadrh_io:
3764  case Hexagon::L2_loadruh_io:
3765  // Rd = memh/memuh(Rs+#u3:1)
3766  DstReg = MI.getOperand(0).getReg();
3767  SrcReg = MI.getOperand(1).getReg();
3768  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3769  MI.getOperand(2).isImm() &&
3770  isShiftedUInt<3,1>(MI.getOperand(2).getImm()))
3771  return HexagonII::HSIG_L2;
3772  break;
3773  case Hexagon::L2_loadrb_io:
3774  // Rd = memb(Rs+#u3:0)
3775  DstReg = MI.getOperand(0).getReg();
3776  SrcReg = MI.getOperand(1).getReg();
3777  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3778  MI.getOperand(2).isImm() &&
3779  isUInt<3>(MI.getOperand(2).getImm()))
3780  return HexagonII::HSIG_L2;
3781  break;
3782  case Hexagon::L2_loadrd_io:
3783  // Rdd = memd(r29+#u5:3)
3784  DstReg = MI.getOperand(0).getReg();
3785  SrcReg = MI.getOperand(1).getReg();
3786  if (isDblRegForSubInst(DstReg, HRI) &&
3787  Hexagon::IntRegsRegClass.contains(SrcReg) &&
3788  HRI.getStackRegister() == SrcReg &&
3789  MI.getOperand(2).isImm() &&
3790  isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
3791  return HexagonII::HSIG_L2;
3792  break;
3793  // dealloc_return is not documented in Hexagon Manual, but marked
3794  // with A_SUBINSN attribute in iset_v4classic.py.
3795  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3796  case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3797  case Hexagon::L4_return:
3798  case Hexagon::L2_deallocframe:
3799  return HexagonII::HSIG_L2;
3800  case Hexagon::EH_RETURN_JMPR:
3801  case Hexagon::PS_jmpret:
3802  case Hexagon::SL2_jumpr31:
3803  // jumpr r31
3804  // Actual form JMPR implicit-def %pc, implicit %r31, implicit internal %r0
3805  DstReg = MI.getOperand(0).getReg();
3806  if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
3807  return HexagonII::HSIG_L2;
3808  break;
3809  case Hexagon::PS_jmprett:
3810  case Hexagon::PS_jmpretf:
3811  case Hexagon::PS_jmprettnewpt:
3812  case Hexagon::PS_jmpretfnewpt:
3813  case Hexagon::PS_jmprettnew:
3814  case Hexagon::PS_jmpretfnew:
3815  case Hexagon::SL2_jumpr31_t:
3816  case Hexagon::SL2_jumpr31_f:
3817  case Hexagon::SL2_jumpr31_tnew:
3818  DstReg = MI.getOperand(1).getReg();
3819  SrcReg = MI.getOperand(0).getReg();
3820  // [if ([!]p0[.new])] jumpr r31
3821  if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
3822  (Hexagon::P0 == SrcReg)) &&
3823  (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
3824  return HexagonII::HSIG_L2;
3825  break;
3826  case Hexagon::L4_return_t:
3827  case Hexagon::L4_return_f:
3828  case Hexagon::L4_return_tnew_pnt:
3829  case Hexagon::L4_return_fnew_pnt:
3830  case Hexagon::L4_return_tnew_pt:
3831  case Hexagon::L4_return_fnew_pt:
3832  // [if ([!]p0[.new])] dealloc_return
3833  SrcReg = MI.getOperand(0).getReg();
3834  if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
3835  return HexagonII::HSIG_L2;
3836  break;
3837  //
3838  // Group S1:
3839  //
3840  // memw(Rs+#u4:2) = Rt
3841  // memb(Rs+#u4:0) = Rt
3842  case Hexagon::S2_storeri_io:
3843  // Special case this one from Group S2.
3844  // memw(r29+#u5:2) = Rt
3845  Src1Reg = MI.getOperand(0).getReg();
3846  Src2Reg = MI.getOperand(2).getReg();
3847  if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3848  isIntRegForSubInst(Src2Reg) &&
3849  HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3850  isShiftedUInt<5,2>(MI.getOperand(1).getImm()))
3851  return HexagonII::HSIG_S2;
3852  // memw(Rs+#u4:2) = Rt
3853  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3854  MI.getOperand(1).isImm() &&
3855  isShiftedUInt<4,2>(MI.getOperand(1).getImm()))
3856  return HexagonII::HSIG_S1;
3857  break;
3858  case Hexagon::S2_storerb_io:
3859  // memb(Rs+#u4:0) = Rt
3860  Src1Reg = MI.getOperand(0).getReg();
3861  Src2Reg = MI.getOperand(2).getReg();
3862  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3863  MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()))
3864  return HexagonII::HSIG_S1;
3865  break;
3866  //
3867  // Group S2:
3868  //
3869  // memh(Rs+#u3:1) = Rt
3870  // memw(r29+#u5:2) = Rt
3871  // memd(r29+#s6:3) = Rtt
3872  // memw(Rs+#u4:2) = #U1
3873  // memb(Rs+#u4) = #U1
3874  // allocframe(#u5:3)
3875  case Hexagon::S2_storerh_io:
3876  // memh(Rs+#u3:1) = Rt
3877  Src1Reg = MI.getOperand(0).getReg();
3878  Src2Reg = MI.getOperand(2).getReg();
3879  if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3880  MI.getOperand(1).isImm() &&
3881  isShiftedUInt<3,1>(MI.getOperand(1).getImm()))
3882  return HexagonII::HSIG_S1;
3883  break;
3884  case Hexagon::S2_storerd_io:
3885  // memd(r29+#s6:3) = Rtt
3886  Src1Reg = MI.getOperand(0).getReg();
3887  Src2Reg = MI.getOperand(2).getReg();
3888  if (isDblRegForSubInst(Src2Reg, HRI) &&
3889  Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3890  HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3891  isShiftedInt<6,3>(MI.getOperand(1).getImm()))
3892  return HexagonII::HSIG_S2;
3893  break;
3894  case Hexagon::S4_storeiri_io:
3895  // memw(Rs+#u4:2) = #U1
3896  Src1Reg = MI.getOperand(0).getReg();
3897  if (isIntRegForSubInst(Src1Reg) && MI.getOperand(1).isImm() &&
3898  isShiftedUInt<4,2>(MI.getOperand(1).getImm()) &&
3899  MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3900  return HexagonII::HSIG_S2;
3901  break;
3902  case Hexagon::S4_storeirb_io:
3903  // memb(Rs+#u4) = #U1
3904  Src1Reg = MI.getOperand(0).getReg();
3905  if (isIntRegForSubInst(Src1Reg) &&
3906  MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()) &&
3907  MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3908  return HexagonII::HSIG_S2;
3909  break;
3910  case Hexagon::S2_allocframe:
3911  if (MI.getOperand(2).isImm() &&
3912  isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
3913  return HexagonII::HSIG_S1;
3914  break;
3915  //
3916  // Group A:
3917  //
3918  // Rx = add(Rx,#s7)
3919  // Rd = Rs
3920  // Rd = #u6
3921  // Rd = #-1
3922  // if ([!]P0[.new]) Rd = #0
3923  // Rd = add(r29,#u6:2)
3924  // Rx = add(Rx,Rs)
3925  // P0 = cmp.eq(Rs,#u2)
3926  // Rdd = combine(#0,Rs)
3927  // Rdd = combine(Rs,#0)
3928  // Rdd = combine(#u2,#U2)
3929  // Rd = add(Rs,#1)
3930  // Rd = add(Rs,#-1)
3931  // Rd = sxth/sxtb/zxtb/zxth(Rs)
3932  // Rd = and(Rs,#1)
3933  case Hexagon::A2_addi:
3934  DstReg = MI.getOperand(0).getReg();
3935  SrcReg = MI.getOperand(1).getReg();
3936  if (isIntRegForSubInst(DstReg)) {
3937  // Rd = add(r29,#u6:2)
3938  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3939  HRI.getStackRegister() == SrcReg && MI.getOperand(2).isImm() &&
3940  isShiftedUInt<6,2>(MI.getOperand(2).getImm()))
3941  return HexagonII::HSIG_A;
3942  // Rx = add(Rx,#s7)
3943  if ((DstReg == SrcReg) && MI.getOperand(2).isImm() &&
3944  isInt<7>(MI.getOperand(2).getImm()))
3945  return HexagonII::HSIG_A;
3946  // Rd = add(Rs,#1)
3947  // Rd = add(Rs,#-1)
3948  if (isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3949  ((MI.getOperand(2).getImm() == 1) ||
3950  (MI.getOperand(2).getImm() == -1)))
3951  return HexagonII::HSIG_A;
3952  }
3953  break;
3954  case Hexagon::A2_add:
3955  // Rx = add(Rx,Rs)
3956  DstReg = MI.getOperand(0).getReg();
3957  Src1Reg = MI.getOperand(1).getReg();
3958  Src2Reg = MI.getOperand(2).getReg();
3959  if (isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&
3960  isIntRegForSubInst(Src2Reg))
3961  return HexagonII::HSIG_A;
3962  break;
3963  case Hexagon::A2_andir:
3964  // Same as zxtb.
3965  // Rd16=and(Rs16,#255)
3966  // Rd16=and(Rs16,#1)
3967  DstReg = MI.getOperand(0).getReg();
3968  SrcReg = MI.getOperand(1).getReg();
3969  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3970  MI.getOperand(2).isImm() &&
3971  ((MI.getOperand(2).getImm() == 1) ||
3972  (MI.getOperand(2).getImm() == 255)))
3973  return HexagonII::HSIG_A;
3974  break;
3975  case Hexagon::A2_tfr:
3976  // Rd = Rs
3977  DstReg = MI.getOperand(0).getReg();
3978  SrcReg = MI.getOperand(1).getReg();
3979  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3980  return HexagonII::HSIG_A;
3981  break;
3982  case Hexagon::A2_tfrsi:
3983  // Rd = #u6
3984  // Do not test for #u6 size since the const is getting extended
3985  // regardless and compound could be formed.
3986  // Rd = #-1
3987  DstReg = MI.getOperand(0).getReg();
3988  if (isIntRegForSubInst(DstReg))
3989  return HexagonII::HSIG_A;
3990  break;
3991  case Hexagon::C2_cmoveit:
3992  case Hexagon::C2_cmovenewit:
3993  case Hexagon::C2_cmoveif:
3994  case Hexagon::C2_cmovenewif:
3995  // if ([!]P0[.new]) Rd = #0
3996  // Actual form:
3997  // %r16 = C2_cmovenewit internal %p0, 0, implicit undef %r16;
3998  DstReg = MI.getOperand(0).getReg();
3999  SrcReg = MI.getOperand(1).getReg();
4000  if (isIntRegForSubInst(DstReg) &&
4001  Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
4002  MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0)
4003  return HexagonII::HSIG_A;
4004  break;
4005  case Hexagon::C2_cmpeqi:
4006  // P0 = cmp.eq(Rs,#u2)
4007  DstReg = MI.getOperand(0).getReg();
4008  SrcReg = MI.getOperand(1).getReg();
4009  if (Hexagon::PredRegsRegClass.contains(DstReg) &&
4010  Hexagon::P0 == DstReg && isIntRegForSubInst(SrcReg) &&
4011  MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm()))
4012  return HexagonII::HSIG_A;
4013  break;
4014  case Hexagon::A2_combineii:
4015  case Hexagon::A4_combineii:
4016  // Rdd = combine(#u2,#U2)
4017  DstReg = MI.getOperand(0).getReg();
4018  if (isDblRegForSubInst(DstReg, HRI) &&
4019  ((MI.getOperand(1).isImm() && isUInt<2>(MI.getOperand(1).getImm())) ||
4020  (MI.getOperand(1).isGlobal() &&
4021  isUInt<2>(MI.getOperand(1).getOffset()))) &&
4022  ((MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) ||
4023  (MI.getOperand(2).isGlobal() &&
4024  isUInt<2>(MI.getOperand(2).getOffset()))))
4025  return HexagonII::HSIG_A;
4026  break;
4027  case Hexagon::A4_combineri:
4028  // Rdd = combine(Rs,#0)
4029  DstReg = MI.getOperand(0).getReg();
4030  SrcReg = MI.getOperand(1).getReg();
4031  if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
4032  ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||
4033  (MI.getOperand(2).isGlobal() && MI.getOperand(2).getOffset() == 0)))
4034  return HexagonII::HSIG_A;
4035  break;
4036  case Hexagon::A4_combineir:
4037  // Rdd = combine(#0,Rs)
4038  DstReg = MI.getOperand(0).getReg();
4039  SrcReg = MI.getOperand(2).getReg();
4040  if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
4041  ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) ||
4042  (MI.getOperand(1).isGlobal() && MI.getOperand(1).getOffset() == 0)))
4043  return HexagonII::HSIG_A;
4044  break;
4045  case Hexagon::A2_sxtb:
4046  case Hexagon::A2_sxth:
4047  case Hexagon::A2_zxtb:
4048  case Hexagon::A2_zxth:
4049  // Rd = sxth/sxtb/zxtb/zxth(Rs)
4050  DstReg = MI.getOperand(0).getReg();
4051  SrcReg = MI.getOperand(1).getReg();
4052  if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
4053  return HexagonII::HSIG_A;
4054  break;
4055  }
4056 
4057  return HexagonII::HSIG_None;
4058 }
4059 
4061  return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Real);
4062 }
4063 
4065  const InstrItineraryData *ItinData, const MachineInstr &MI) const {
4066  // Default to one cycle for no itinerary. However, an "empty" itinerary may
4067  // still have a MinLatency property, which getStageLatency checks.
4068  if (!ItinData)
4069  return getInstrLatency(ItinData, MI);
4070 
4071  if (MI.isTransient())
4072  return 0;
4073  return ItinData->getStageLatency(MI.getDesc().getSchedClass());
4074 }
4075 
4076 /// getOperandLatency - Compute and return the use operand latency of a given
4077 /// pair of def and use.
4078 /// In most cases, the static scheduling itinerary was enough to determine the
4079 /// operand latency. But it may not be possible for instructions with variable
4080 /// number of defs / uses.
4081 ///
4082 /// This is a raw interface to the itinerary that may be directly overriden by
4083 /// a target. Use computeOperandLatency to get the best estimate of latency.
4085  const MachineInstr &DefMI,
4086  unsigned DefIdx,
4087  const MachineInstr &UseMI,
4088  unsigned UseIdx) const {
4089  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4090 
4091  // Get DefIdx and UseIdx for super registers.
4092  const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
4093 
4094  if (DefMO.isReg() && HRI.isPhysicalRegister(DefMO.getReg())) {
4095  if (DefMO.isImplicit()) {
4096  for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) {
4097  int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &HRI);
4098  if (Idx != -1) {
4099  DefIdx = Idx;
4100  break;
4101  }
4102  }
4103  }
4104 
4105  const MachineOperand &UseMO = UseMI.getOperand(UseIdx);
4106  if (UseMO.isImplicit()) {
4107  for (MCSuperRegIterator SR(UseMO.getReg(), &HRI); SR.isValid(); ++SR) {
4108  int Idx = UseMI.findRegisterUseOperandIdx(*SR, false, &HRI);
4109  if (Idx != -1) {
4110  UseIdx = Idx;
4111  break;
4112  }
4113  }
4114  }
4115  }
4116 
4117  int Latency = TargetInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
4118  UseMI, UseIdx);
4119  if (!Latency)
4120  // We should never have 0 cycle latency between two instructions unless
4121  // they can be packetized together. However, this decision can't be made
4122  // here.
4123  Latency = 1;
4124  return Latency;
4125 }
4126 
4127 // inverts the predication logic.
4128 // p -> NotP
4129 // NotP -> P
4131  SmallVectorImpl<MachineOperand> &Cond) const {
4132  if (Cond.empty())
4133  return false;
4134  unsigned Opc = getInvertedPredicatedOpcode(Cond[0].getImm());
4135  Cond[0].setImm(Opc);
4136  return true;
4137 }
4138 
4139 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
4140  int InvPredOpcode;
4141  InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
4142  : Hexagon::getTruePredOpcode(Opc);
4143  if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
4144  return InvPredOpcode;
4145 
4146  llvm_unreachable("Unexpected predicated instruction");
4147 }
4148 
4149 // Returns the max value that doesn't need to be extended.
4151  const uint64_t F = MI.getDesc().TSFlags;
4152  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4154  unsigned bits = (F >> HexagonII::ExtentBitsPos)
4156 
4157  if (isSigned) // if value is signed
4158  return ~(-1U << (bits - 1));
4159  else
4160  return ~(-1U << bits);
4161 }
4162 
4163 
4165  switch (MI.getOpcode()) {
4166  case Hexagon::L2_loadrbgp:
4167  case Hexagon::L2_loadrdgp:
4168  case Hexagon::L2_loadrhgp:
4169  case Hexagon::L2_loadrigp:
4170  case Hexagon::L2_loadrubgp:
4171  case Hexagon::L2_loadruhgp:
4172  case Hexagon::S2_storerbgp:
4173  case Hexagon::S2_storerbnewgp:
4174  case Hexagon::S2_storerhgp:
4175  case Hexagon::S2_storerhnewgp:
4176  case Hexagon::S2_storerigp:
4177  case Hexagon::S2_storerinewgp:
4178  case Hexagon::S2_storerdgp:
4179  case Hexagon::S2_storerfgp:
4180  return true;
4181  }
4182  const uint64_t F = MI.getDesc().TSFlags;
4183  unsigned addrMode =
4185  // Disallow any base+offset instruction. The assembler does not yet reorder
4186  // based up any zero offset instruction.
4187  return (addrMode == HexagonII::BaseRegOffset ||
4188  addrMode == HexagonII::BaseImmOffset ||
4189  addrMode == HexagonII::BaseLongOffset);
4190 }
4191 
4193  using namespace HexagonII;
4194 
4195  const uint64_t F = MI.getDesc().TSFlags;
4196  unsigned S = (F >> MemAccessSizePos) & MemAccesSizeMask;
4198  if (Size != 0)
4199  return Size;
4200 
4201  // Handle vector access sizes.
4202  const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4203  switch (S) {
4205  return HRI.getSpillSize(Hexagon::HvxVRRegClass);
4206  default:
4207  llvm_unreachable("Unexpected instruction");
4208  }
4209 }
4210 
4211 // Returns the min value that doesn't need to be extended.
4213  const uint64_t F = MI.getDesc().TSFlags;
4214  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4216  unsigned bits = (F >> HexagonII::ExtentBitsPos)
4218 
4219  if (isSigned) // if value is signed
4220  return -1U << (bits - 1);
4221  else
4222  return 0;
4223 }
4224 
4225 // Returns opcode of the non-extended equivalent instruction.
4227  // Check if the instruction has a register form that uses register in place
4228  // of the extended operand, if so return that as the non-extended form.
4229  short NonExtOpcode = Hexagon::getRegForm(MI.getOpcode());
4230  if (NonExtOpcode >= 0)
4231  return NonExtOpcode;
4232 
4233  if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
4234  // Check addressing mode and retrieve non-ext equivalent instruction.
4235  switch (getAddrMode(MI)) {
4236  case HexagonII::Absolute:
4237  return Hexagon::changeAddrMode_abs_io(MI.getOpcode());
4239  return Hexagon::changeAddrMode_io_rr(MI.getOpcode());
4241  return Hexagon::changeAddrMode_ur_rr(MI.getOpcode());
4242 
4243  default:
4244  return -1;
4245  }
4246  }
4247  return -1;
4248 }
4249 
4251  unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
4252  if (Cond.empty())
4253  return false;
4254  assert(Cond.size() == 2);
4255  if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
4256  LLVM_DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
4257  return false;
4258  }
4259  PredReg = Cond[1].getReg();
4260  PredRegPos = 1;
4261  // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
4262  PredRegFlags = 0;
4263  if (Cond[1].isImplicit())
4264  PredRegFlags = RegState::Implicit;
4265  if (Cond[1].isUndef())
4266  PredRegFlags |= RegState::Undef;
4267  return true;
4268 }
4269 
4271  return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Pseudo);
4272 }
4273 
4275  return Hexagon::getRegForm(MI.getOpcode());
4276 }
4277 
4278 // Return the number of bytes required to encode the instruction.
4279 // Hexagon instructions are fixed length, 4 bytes, unless they
4280 // use a constant extender, which requires another 4 bytes.
4281 // For debug instructions and prolog labels, return 0.
4283  if (MI.isDebugInstr() || MI.isPosition())
4284  return 0;
4285 
4286  unsigned Size = MI.getDesc().getSize();
4287  if (!Size)
4288  // Assume the default insn size in case it cannot be determined
4289  // for whatever reason.
4290  Size = HEXAGON_INSTR_SIZE;
4291 
4292  if (isConstExtended(MI) || isExtended(MI))
4293  Size += HEXAGON_INSTR_SIZE;
4294 
4295  // Try and compute number of instructions in asm.
4297  const MachineBasicBlock &MBB = *MI.getParent();
4298  const MachineFunction *MF = MBB.getParent();
4299  const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
4300 
4301  // Count the number of register definitions to find the asm string.
4302  unsigned NumDefs = 0;
4303  for (; MI.getOperand(NumDefs).isReg() && MI.getOperand(NumDefs).isDef();
4304  ++NumDefs)
4305  assert(NumDefs != MI.getNumOperands()-2 && "No asm string?");
4306 
4307  assert(MI.getOperand(NumDefs).isSymbol() && "No asm string?");
4308  // Disassemble the AsmStr and approximate number of instructions.
4309  const char *AsmStr = MI.getOperand(NumDefs).getSymbolName();
4310  Size = getInlineAsmLength(AsmStr, *MAI);
4311  }
4312 
4313  return Size;
4314 }
4315 
4317  const uint64_t F = MI.getDesc().TSFlags;
4318  return (F >> HexagonII::TypePos) & HexagonII::TypeMask;
4319 }
4320 
4322  const InstrItineraryData &II = *Subtarget.getInstrItineraryData();
4323  const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
4324 
4325  return IS.getUnits();
4326 }
4327 
4328 // Calculate size of the basic block without debug instructions.
4330  return nonDbgMICount(BB->instr_begin(), BB->instr_end());
4331 }
4332 
4334  MachineBasicBlock::const_iterator BundleHead) const {
4335  assert(BundleHead->isBundle() && "Not a bundle header");
4336  auto MII = BundleHead.getInstrIterator();
4337  // Skip the bundle header.
4338  return nonDbgMICount(++MII, getBundleEnd(BundleHead.getInstrIterator()));
4339 }
4340 
4341 /// immediateExtend - Changes the instruction in place to one using an immediate
4342 /// extender.
4344  assert((isExtendable(MI)||isConstExtended(MI)) &&
4345  "Instruction must be extendable");
4346  // Find which operand is extendable.
4347  short ExtOpNum = getCExtOpNum(MI);
4348  MachineOperand &MO = MI.getOperand(ExtOpNum);
4349  // This needs to be something we understand.
4350  assert((MO.isMBB() || MO.isImm()) &&
4351  "Branch with unknown extendable field type");
4352  // Mark given operand as extended.
4354 }
4355 
4357  MachineInstr &MI, MachineBasicBlock *NewTarget) const {
4358  LLVM_DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to "
4359  << printMBBReference(*NewTarget);
4360  MI.dump(););
4361  assert(MI.isBranch());
4362  unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode());
4363  int TargetPos = MI.getNumOperands() - 1;
4364  // In general branch target is the last operand,
4365  // but some implicit defs added at the end might change it.
4366  while ((TargetPos > -1) && !MI.getOperand(TargetPos).isMBB())
4367  --TargetPos;
4368  assert((TargetPos >= 0) && MI.getOperand(TargetPos).isMBB());
4369  MI.getOperand(TargetPos).setMBB(NewTarget);
4371  NewOpcode = reversePrediction(NewOpcode);
4372  }
4373  MI.setDesc(get(NewOpcode));
4374  return true;
4375 }
4376 
4378  /* +++ The code below is used to generate complete set of Hexagon Insn +++ */
4380  MachineBasicBlock &B = *A;
4382  DebugLoc DL = I->getDebugLoc();
4383  MachineInstr *NewMI;
4384 
4385  for (unsigned insn = TargetOpcode::GENERIC_OP_END+1;
4386  insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
4387  NewMI = BuildMI(B, I, DL, get(insn));
4388  LLVM_DEBUG(dbgs() << "\n"
4389  << getName(NewMI->getOpcode())
4390  << " Class: " << NewMI->getDesc().getSchedClass());
4391  NewMI->eraseFromParent();
4392  }
4393  /* --- The code above is used to generate complete set of Hexagon Insn --- */
4394 }
4395 
4396 // inverts the predication logic.
4397 // p -> NotP
4398 // NotP -> P
4400  LLVM_DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI.dump());
4402  return true;
4403 }
4404 
4405 // Reverse the branch prediction.
4406 unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {
4407  int PredRevOpcode = -1;
4408  if (isPredictedTaken(Opcode))
4409  PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode);
4410  else
4411  PredRevOpcode = Hexagon::takenBranchPrediction(Opcode);
4412  assert(PredRevOpcode > 0);
4413  return PredRevOpcode;
4414 }
4415 
4416 // TODO: Add more rigorous validation.
4418  const {
4419  return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));
4420 }
4421 
4422 void HexagonInstrInfo::
4424  assert(MIB->isBundle());
4425  MachineOperand &Operand = MIB->getOperand(0);
4426  if (Operand.isImm())
4427  Operand.setImm(Operand.getImm() | memShufDisabledMask);
4428  else
4429  MIB->addOperand(MachineOperand::CreateImm(memShufDisabledMask));
4430 }
4431 
4433  assert(MIB.isBundle());
4434  const MachineOperand &Operand = MIB.getOperand(0);
4435  return (Operand.isImm() && (Operand.getImm() & memShufDisabledMask) != 0);
4436 }
4437 
4438 // Addressing mode relations.
4440  return Opc >= 0 ? Hexagon::changeAddrMode_abs_io(Opc) : Opc;
4441 }
4442 
4444  return Opc >= 0 ? Hexagon::changeAddrMode_io_abs(Opc) : Opc;
4445 }
4446 
4448  return Opc >= 0 ? Hexagon::changeAddrMode_io_pi(Opc) : Opc;
4449 }
4450 
4452  return Opc >= 0 ? Hexagon::changeAddrMode_io_rr(Opc) : Opc;
4453 }
4454 
4456  return Opc >= 0 ? Hexagon::changeAddrMode_pi_io(Opc) : Opc;
4457 }
4458 
4460  return Opc >= 0 ? Hexagon::changeAddrMode_rr_io(Opc) : Opc;
4461 }
4462 
4464  return Opc >= 0 ? Hexagon::changeAddrMode_rr_ur(Opc) : Opc;
4465 }
4466 
4468  return Opc >= 0 ? Hexagon::changeAddrMode_ur_rr(Opc) : Opc;
4469 }
static bool isReg(const MCInst &MI, unsigned OpNo)
unsigned getTargetFlags() const
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
short getNonExtOpcode(const MachineInstr &MI) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
bool isVecALU(const MachineInstr &MI) const
const MachineInstrBuilder & add(const MachineOperand &MO) const
bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const override
If the specified instruction defines any predicate or condition code register(s) used for predication...
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:722
short changeAddrMode_rr_io(short Opc) const
static bool isConstant(const MachineInstr &MI)
bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register...
instr_iterator instr_begin()
const int Hexagon_MEMH_OFFSET_MAX
bool is_TC2early(unsigned SchedClass)
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:635
unsigned nonDbgBBSize(const MachineBasicBlock *BB) const
getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Clas...
instr_iterator instr_end()
MachineBasicBlock * getMBB() const
const int Hexagon_ADDI_OFFSET_MAX
unsigned getRegState(const MachineOperand &RegOp)
Get all register state flags from machine operand RegOp.
const int Hexagon_MEMH_OFFSET_MIN
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
const InstrStage * beginStage(unsigned ItinClassIndx) const
Return the first stage of the itinerary.
static void parseOperands(const MachineInstr &MI, SmallVector< unsigned, 4 > &Defs, SmallVector< unsigned, 8 > &Uses)
Gather register def/uses from MI.
static bool mayAlias(MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA)
static cl::opt< bool > UseDFAHazardRec("dfa-hazard-rec", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Use the DFA based hazard recognizer."))
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index...
void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const
short getEquivalentHWInstr(const MachineInstr &MI) const
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override
Create machine specific model for scheduling.
void push_back(const T &Elt)
Definition: SmallVector.h:211
bool isAbsoluteSet(const MachineInstr &MI) const
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:385
bool isJumpR(const MachineInstr &MI) const
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
Returns true if the first specified predicate subsumes the second, e.g.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:164
unsigned getUnits() const
Returns the choice of FUs.
bool isConstExtended(const MachineInstr &MI) const
bool getInvertedPredSense(SmallVectorImpl< MachineOperand > &Cond) const
Address of indexed Jump Table for switch.
unsigned Reg
unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const
unsigned getSubReg() const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
bool isInlineAsm() const
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Reverses the branch condition of the specified condition list, returning false on success and true if...
int getMaxValue(const MachineInstr &MI) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
const int Hexagon_ADDI_OFFSET_MIN
bool reversePredSense(MachineInstr &MI) const
int getDotNewPredOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
demanded bits
MachineBasicBlock reference.
#define HEXAGON_INSTR_SIZE
bool isExpr(unsigned OpType) const
bool isTailCall(const MachineInstr &MI) const override
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
F(f)
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool producesStall(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
MachineInstrBundleIterator< const MachineInstr > const_iterator
const HexagonFrameLowering * getFrameLowering() const override
unsigned getMemAccessSize(const MachineInstr &MI) const
const int Hexagon_MEMD_OFFSET_MAX
unsigned getSize(const MachineInstr &MI) const
int getDotCurOp(const MachineInstr &MI) const
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:399
bool isLateResultInstr(const MachineInstr &MI) const
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:461
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool is_TC1(unsigned SchedClass)
void immediateExtend(MachineInstr &MI) const
immediateExtend - Changes the instruction in place to one using an immediate extender.
int getDotNewPredJumpOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
short changeAddrMode_ur_rr(short Opc) const
bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand *> &Accesses) const override
Check if the instruction or the bundle of instructions has load from stack slots. ...
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
return AArch64::GPR64RegClass contains(Reg)
iterator_range< succ_iterator > successors()
bool isToBeScheduledASAP(const MachineInstr &MI1, const MachineInstr &MI2) const
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert a noop into the instruction stream at the specified point.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
bool isHVXVec(const MachineInstr &MI) const
static cl::opt< bool > BranchRelaxAsmLarge("branch-relax-asm-large", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"))
bool isComplex(const MachineInstr &MI) const
unsigned getSpillAlignment(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class...
static cl::opt< bool > DisableNVSchedule("disable-hexagon-nv-schedule", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable schedule adjustment for new value stores."))
A description of a memory reference used in the backend.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index...
unsigned getInvertedPredicatedOpcode(const int Opc) const
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MCSuperRegIterator enumerates all super-registers of Reg.
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
const HexagonInstrInfo * TII
Register getFrameRegister(const MachineFunction &MF) const override
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:450
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:414
Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
LLVM_NODISCARD size_t count(char C) const
Return the number of occurrences of C in the string.
Definition: StringRef.h:457
unsigned getCompoundOpcode(const MachineInstr &GA, const MachineInstr &GB) const
bool isPredicatedNew(const MachineInstr &MI) const
bool canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const
Can these instructions execute at the same time in a bundle.
bool predOpcodeHasNot(ArrayRef< MachineOperand > Cond) const
const HexagonRegisterInfo * getRegisterInfo() const override
MachineBasicBlock * getBottomBlock()
Return the "bottom" block in the loop, which is the last block in the linear layout, ignoring any parts of the loop not contiguous with the part that contains the header.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
bool isVecUsableNextPacket(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
Name of external global symbol.
static StringRef getName(Value *V)
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool isDotNewInst(const MachineInstr &MI) const
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
bool isDeallocRet(const MachineInstr &MI) const
bool isExtended(const MachineInstr &MI) const
bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand *> &Accesses) const override
Check if the instruction or the bundle of instructions has store to stack slots.
const char * getSymbolName() const
bool is_TC2(unsigned SchedClass)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:695
bool isSolo(const MachineInstr &MI) const
bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI, const MachineInstr &ESMI) const
MachineBasicBlock::instr_iterator expandVGatherPseudo(MachineInstr &MI) const
bool expandPostRAPseudo(MachineInstr &MI) const override
This function is called for all pseudo instructions that remain after register allocation.
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Cond) const override
Convert the instruction into a predicated instruction.
bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const
MachineInstr * findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp, MachineBasicBlock *TargetBB, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
Find the hardware loop instruction used to set-up the specified loop.
SmallVector< MachineInstr *, 2 > getBranchingInstrs(MachineBasicBlock &MBB) const
bool doesNotReturn(const MachineInstr &CallMI) const
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:408
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:665
bool isEndLoopN(unsigned Opcode) const
bool isBundle() const
bool isCompoundBranchInstr(const MachineInstr &MI) const
void clearKillFlags(unsigned Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
short changeAddrMode_io_rr(short Opc) const
bool isPredictedTaken(unsigned Opcode) const
int getMinValue(const MachineInstr &MI) const
bool getBundleNoShuf(const MachineInstr &MIB) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:130
bool isFPImm() const
isFPImm - Tests if this is a MO_FPImmediate operand.
Itinerary data supplied by a subtarget to be used by a target.
short changeAddrMode_io_pi(short Opc) const
bool isTC1(const MachineInstr &MI) const
unsigned getUndefRegState(bool B)
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Compute the instruction latency of a given instruction.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
unsigned getStageLatency(unsigned ItinClassIndx) const
Return the total stage latency of the given class.
short changeAddrMode_rr_ur(short Opc) const
reverse_iterator rbegin()
bool isBranch(QueryType Type=AnyInBundle) const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MachineInstr.h:659
bool getPredReg(ArrayRef< MachineOperand > Cond, unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const
BasicBlockListType::iterator iterator
unsigned getKillRegState(bool B)
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget...
unsigned getCExtOpNum(const MachineInstr &MI) const
const int Hexagon_MEMD_OFFSET_MIN
MachineOperand * getBaseAndOffset(const MachineInstr &MI, int64_t &Offset, unsigned &AccessSize) const
TargetInstrInfo - Interface to description of machine instruction set.
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:625
bool is_TC3x(unsigned SchedClass)
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
static cl::opt< bool > EnableBranchPrediction("hexagon-enable-branch-prediction", cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"))
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Return true if it&#39;s profitable for if-converter to duplicate instructions of specified accumulated in...
The memory access is volatile.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:582
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:822
Address of a global value.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
const int Hexagon_MEMW_OFFSET_MAX
Constants for Hexagon instructions.
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:428
Machine Value Type.
static cl::opt< bool > EnableALUForwarding("enable-alu-forwarding", cl::Hidden, cl::init(true), cl::desc("Enable vec alu forwarding"))
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
Definition: