LLVM 17.0.0git
HexagonMCTargetDesc.h
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1//===-- HexagonMCTargetDesc.h - Hexagon Target Descriptions -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides Hexagon specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
14#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
15
18#include <cstdint>
19#include <string>
20
21#define Hexagon_POINTER_SIZE 4
22
23#define Hexagon_PointerSize (Hexagon_POINTER_SIZE)
24#define Hexagon_PointerSize_Bits (Hexagon_POINTER_SIZE * 8)
25#define Hexagon_WordSize Hexagon_PointerSize
26#define Hexagon_WordSize_Bits Hexagon_PointerSize_Bits
27
28// allocframe saves LR and FP on stack before allocating
29// a new stack frame. This takes 8 bytes.
30#define HEXAGON_LRFP_SIZE 8
31
32// Normal instruction size (in bytes).
33#define HEXAGON_INSTR_SIZE 4
34
35// Maximum number of words and instructions in a packet.
36#define HEXAGON_PACKET_SIZE 4
37#define HEXAGON_MAX_PACKET_SIZE (HEXAGON_PACKET_SIZE * HEXAGON_INSTR_SIZE)
38// Minimum number of instructions in an end-loop packet.
39#define HEXAGON_PACKET_INNER_SIZE 2
40#define HEXAGON_PACKET_OUTER_SIZE 3
41// Maximum number of instructions in a packet before shuffling,
42// including a compound one or a duplex or an extender.
43#define HEXAGON_PRESHUFFLE_PACKET_SIZE (HEXAGON_PACKET_SIZE + 3)
44
45// Name of the global offset table as defined by the Hexagon ABI
46#define HEXAGON_GOT_SYM_NAME "_GLOBAL_OFFSET_TABLE_"
47
48namespace llvm {
49
50struct InstrStage;
51class FeatureBitset;
52class MCAsmBackend;
53class MCCodeEmitter;
54class MCContext;
55class MCInstrInfo;
56class MCObjectTargetWriter;
57class MCRegisterInfo;
58class MCSubtargetInfo;
59class MCTargetOptions;
60class Target;
61class Triple;
62class StringRef;
63
64extern cl::opt<bool> HexagonDisableCompound;
65extern cl::opt<bool> HexagonDisableDuplex;
66extern const InstrStage HexagonStages[];
67
68MCInstrInfo *createHexagonMCInstrInfo();
70
71namespace Hexagon_MC {
73
75 /// Create a Hexagon MCSubtargetInfo instance. This is exposed so Asm parser,
76 /// etc. do not need to go through TargetRegistry.
78 StringRef FS);
80 void addArchSubtarget(MCSubtargetInfo const *STI,
81 StringRef FS);
82 unsigned GetELFFlags(const MCSubtargetInfo &STI);
83
85}
86
88 MCContext &MCT);
89
91 const MCSubtargetInfo &STI,
92 const MCRegisterInfo &MRI,
94
95std::unique_ptr<MCObjectTargetWriter>
96createHexagonELFObjectWriter(uint8_t OSABI, StringRef CPU);
97
98unsigned HexagonGetLastSlot();
99unsigned HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes);
100
101} // End llvm namespace
102
103// Define symbolic names for Hexagon registers. This defines a mapping from
104// register name to register number.
105//
106#define GET_REGINFO_ENUM
107#include "HexagonGenRegisterInfo.inc"
108
109// Defines symbolic names for the Hexagon instructions.
110//
111#define GET_INSTRINFO_ENUM
112#define GET_INSTRINFO_SCHED_ENUM
113#define GET_INSTRINFO_MC_HELPER_DECLS
114#include "HexagonGenInstrInfo.inc"
115
116#define GET_SUBTARGETINFO_ENUM
117#include "HexagonGenSubtargetInfo.inc"
118
119#endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
unsigned const MachineRegisterInfo * MRI
static LVOptions Options
Definition: LVOptions.cpp:25
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Container class for subtarget features.
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:41
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
Context object for machine code objects.
Definition: MCContext.h:76
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::ArrayRef< MCPhysReg > GetVectRegRev()
unsigned GetELFFlags(const MCSubtargetInfo &STI)
MCSubtargetInfo const * getArchSubtarget(MCSubtargetInfo const *STI)
StringRef selectHexagonCPU(StringRef CPU)
void addArchSubtarget(MCSubtargetInfo const *STI, StringRef FS)
FeatureBitset completeHVXFeatures(const FeatureBitset &FB)
MCSubtargetInfo * createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a Hexagon MCSubtargetInfo instance.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
unsigned HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes)
cl::opt< bool > HexagonDisableCompound
MCCodeEmitter * createHexagonMCCodeEmitter(const MCInstrInfo &MCII, MCContext &MCT)
MCRegisterInfo * createHexagonMCRegisterInfo(StringRef TT)
unsigned HexagonGetLastSlot()
std::unique_ptr< MCObjectTargetWriter > createHexagonELFObjectWriter(uint8_t OSABI, StringRef CPU)
MCAsmBackend * createHexagonAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
MCInstrInfo * createHexagonMCInstrInfo()
const InstrStage HexagonStages[]
cl::opt< bool > HexagonDisableDuplex