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HexagonAsmBackend.cpp
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1 //===-- HexagonAsmBackend.cpp - Hexagon Assembler Backend -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "HexagonFixupKinds.h"
16 #include "llvm/MC/MCAsmBackend.h"
17 #include "llvm/MC/MCAsmLayout.h"
18 #include "llvm/MC/MCAssembler.h"
19 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCObjectWriter.h"
25 #include "llvm/MC/TargetRegistry.h"
26 #include "llvm/Support/Debug.h"
28 
29 #include <sstream>
30 
31 using namespace llvm;
32 using namespace Hexagon;
33 
34 #define DEBUG_TYPE "hexagon-asm-backend"
35 
37  ("mno-fixup", cl::desc("Disable fixing up resolved relocations for Hexagon"));
38 
39 namespace {
40 
41 class HexagonAsmBackend : public MCAsmBackend {
42  uint8_t OSABI;
43  StringRef CPU;
44  mutable uint64_t relaxedCnt;
45  std::unique_ptr <MCInstrInfo> MCII;
46  std::unique_ptr <MCInst *> RelaxTarget;
47  MCInst * Extender;
48  unsigned MaxPacketSize;
49 
50  void ReplaceInstruction(MCCodeEmitter &E, MCRelaxableFragment &RF,
51  MCInst &HMB) const {
53  SmallString<256> Code;
54  raw_svector_ostream VecOS(Code);
55  E.encodeInstruction(HMB, VecOS, Fixups, *RF.getSubtargetInfo());
56 
57  // Update the fragment.
58  RF.setInst(HMB);
59  RF.getContents() = Code;
60  RF.getFixups() = Fixups;
61  }
62 
63 public:
64  HexagonAsmBackend(const Target &T, const Triple &TT, uint8_t OSABI,
65  StringRef CPU)
66  : MCAsmBackend(support::little), OSABI(OSABI), CPU(CPU), relaxedCnt(0),
67  MCII(T.createMCInstrInfo()), RelaxTarget(new MCInst *),
68  Extender(nullptr), MaxPacketSize(HexagonMCInstrInfo::packetSize(CPU))
69  {}
70 
71  std::unique_ptr<MCObjectTargetWriter>
72  createObjectTargetWriter() const override {
73  return createHexagonELFObjectWriter(OSABI, CPU);
74  }
75 
76  void setExtender(MCContext &Context) const {
77  if (Extender == nullptr)
78  const_cast<HexagonAsmBackend *>(this)->Extender = Context.createMCInst();
79  }
80 
81  MCInst *takeExtender() const {
82  assert(Extender != nullptr);
83  MCInst * Result = Extender;
84  const_cast<HexagonAsmBackend *>(this)->Extender = nullptr;
85  return Result;
86  }
87 
88  unsigned getNumFixupKinds() const override {
90  }
91 
92  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
93  const static MCFixupKindInfo Infos[Hexagon::NumTargetFixupKinds] = {
94  // This table *must* be in same the order of fixup_* kinds in
95  // HexagonFixupKinds.h.
96  //
97  // namei offset bits flags
98  { "fixup_Hexagon_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
99  { "fixup_Hexagon_B15_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
100  { "fixup_Hexagon_B7_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
101  { "fixup_Hexagon_LO16", 0, 32, 0 },
102  { "fixup_Hexagon_HI16", 0, 32, 0 },
103  { "fixup_Hexagon_32", 0, 32, 0 },
104  { "fixup_Hexagon_16", 0, 32, 0 },
105  { "fixup_Hexagon_8", 0, 32, 0 },
106  { "fixup_Hexagon_GPREL16_0", 0, 32, 0 },
107  { "fixup_Hexagon_GPREL16_1", 0, 32, 0 },
108  { "fixup_Hexagon_GPREL16_2", 0, 32, 0 },
109  { "fixup_Hexagon_GPREL16_3", 0, 32, 0 },
110  { "fixup_Hexagon_HL16", 0, 32, 0 },
111  { "fixup_Hexagon_B13_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
112  { "fixup_Hexagon_B9_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
113  { "fixup_Hexagon_B32_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
114  { "fixup_Hexagon_32_6_X", 0, 32, 0 },
115  { "fixup_Hexagon_B22_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
116  { "fixup_Hexagon_B15_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
117  { "fixup_Hexagon_B13_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
118  { "fixup_Hexagon_B9_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
119  { "fixup_Hexagon_B7_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
120  { "fixup_Hexagon_16_X", 0, 32, 0 },
121  { "fixup_Hexagon_12_X", 0, 32, 0 },
122  { "fixup_Hexagon_11_X", 0, 32, 0 },
123  { "fixup_Hexagon_10_X", 0, 32, 0 },
124  { "fixup_Hexagon_9_X", 0, 32, 0 },
125  { "fixup_Hexagon_8_X", 0, 32, 0 },
126  { "fixup_Hexagon_7_X", 0, 32, 0 },
127  { "fixup_Hexagon_6_X", 0, 32, 0 },
128  { "fixup_Hexagon_32_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
129  { "fixup_Hexagon_COPY", 0, 32, 0 },
130  { "fixup_Hexagon_GLOB_DAT", 0, 32, 0 },
131  { "fixup_Hexagon_JMP_SLOT", 0, 32, 0 },
132  { "fixup_Hexagon_RELATIVE", 0, 32, 0 },
133  { "fixup_Hexagon_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
134  { "fixup_Hexagon_GOTREL_LO16", 0, 32, 0 },
135  { "fixup_Hexagon_GOTREL_HI16", 0, 32, 0 },
136  { "fixup_Hexagon_GOTREL_32", 0, 32, 0 },
137  { "fixup_Hexagon_GOT_LO16", 0, 32, 0 },
138  { "fixup_Hexagon_GOT_HI16", 0, 32, 0 },
139  { "fixup_Hexagon_GOT_32", 0, 32, 0 },
140  { "fixup_Hexagon_GOT_16", 0, 32, 0 },
141  { "fixup_Hexagon_DTPMOD_32", 0, 32, 0 },
142  { "fixup_Hexagon_DTPREL_LO16", 0, 32, 0 },
143  { "fixup_Hexagon_DTPREL_HI16", 0, 32, 0 },
144  { "fixup_Hexagon_DTPREL_32", 0, 32, 0 },
145  { "fixup_Hexagon_DTPREL_16", 0, 32, 0 },
146  { "fixup_Hexagon_GD_PLT_B22_PCREL",0, 32, MCFixupKindInfo::FKF_IsPCRel },
147  { "fixup_Hexagon_LD_PLT_B22_PCREL",0, 32, MCFixupKindInfo::FKF_IsPCRel },
148  { "fixup_Hexagon_GD_GOT_LO16", 0, 32, 0 },
149  { "fixup_Hexagon_GD_GOT_HI16", 0, 32, 0 },
150  { "fixup_Hexagon_GD_GOT_32", 0, 32, 0 },
151  { "fixup_Hexagon_GD_GOT_16", 0, 32, 0 },
152  { "fixup_Hexagon_LD_GOT_LO16", 0, 32, 0 },
153  { "fixup_Hexagon_LD_GOT_HI16", 0, 32, 0 },
154  { "fixup_Hexagon_LD_GOT_32", 0, 32, 0 },
155  { "fixup_Hexagon_LD_GOT_16", 0, 32, 0 },
156  { "fixup_Hexagon_IE_LO16", 0, 32, 0 },
157  { "fixup_Hexagon_IE_HI16", 0, 32, 0 },
158  { "fixup_Hexagon_IE_32", 0, 32, 0 },
159  { "fixup_Hexagon_IE_16", 0, 32, 0 },
160  { "fixup_Hexagon_IE_GOT_LO16", 0, 32, 0 },
161  { "fixup_Hexagon_IE_GOT_HI16", 0, 32, 0 },
162  { "fixup_Hexagon_IE_GOT_32", 0, 32, 0 },
163  { "fixup_Hexagon_IE_GOT_16", 0, 32, 0 },
164  { "fixup_Hexagon_TPREL_LO16", 0, 32, 0 },
165  { "fixup_Hexagon_TPREL_HI16", 0, 32, 0 },
166  { "fixup_Hexagon_TPREL_32", 0, 32, 0 },
167  { "fixup_Hexagon_TPREL_16", 0, 32, 0 },
168  { "fixup_Hexagon_6_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
169  { "fixup_Hexagon_GOTREL_32_6_X", 0, 32, 0 },
170  { "fixup_Hexagon_GOTREL_16_X", 0, 32, 0 },
171  { "fixup_Hexagon_GOTREL_11_X", 0, 32, 0 },
172  { "fixup_Hexagon_GOT_32_6_X", 0, 32, 0 },
173  { "fixup_Hexagon_GOT_16_X", 0, 32, 0 },
174  { "fixup_Hexagon_GOT_11_X", 0, 32, 0 },
175  { "fixup_Hexagon_DTPREL_32_6_X", 0, 32, 0 },
176  { "fixup_Hexagon_DTPREL_16_X", 0, 32, 0 },
177  { "fixup_Hexagon_DTPREL_11_X", 0, 32, 0 },
178  { "fixup_Hexagon_GD_GOT_32_6_X", 0, 32, 0 },
179  { "fixup_Hexagon_GD_GOT_16_X", 0, 32, 0 },
180  { "fixup_Hexagon_GD_GOT_11_X", 0, 32, 0 },
181  { "fixup_Hexagon_LD_GOT_32_6_X", 0, 32, 0 },
182  { "fixup_Hexagon_LD_GOT_16_X", 0, 32, 0 },
183  { "fixup_Hexagon_LD_GOT_11_X", 0, 32, 0 },
184  { "fixup_Hexagon_IE_32_6_X", 0, 32, 0 },
185  { "fixup_Hexagon_IE_16_X", 0, 32, 0 },
186  { "fixup_Hexagon_IE_GOT_32_6_X", 0, 32, 0 },
187  { "fixup_Hexagon_IE_GOT_16_X", 0, 32, 0 },
188  { "fixup_Hexagon_IE_GOT_11_X", 0, 32, 0 },
189  { "fixup_Hexagon_TPREL_32_6_X", 0, 32, 0 },
190  { "fixup_Hexagon_TPREL_16_X", 0, 32, 0 },
191  { "fixup_Hexagon_TPREL_11_X", 0, 32, 0 },
192  { "fixup_Hexagon_GD_PLT_B22_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel },
193  { "fixup_Hexagon_GD_PLT_B32_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel },
194  { "fixup_Hexagon_LD_PLT_B22_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel },
195  { "fixup_Hexagon_LD_PLT_B32_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel }
196  };
197 
200 
201  assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
202  "Invalid kind!");
203  return Infos[Kind - FirstTargetFixupKind];
204  }
205 
206  bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
207  const MCValue &Target) override {
208  switch(Fixup.getTargetKind()) {
209  default:
210  llvm_unreachable("Unknown Fixup Kind!");
211 
212  case fixup_Hexagon_LO16:
213  case fixup_Hexagon_HI16:
214  case fixup_Hexagon_16:
215  case fixup_Hexagon_8:
220  case fixup_Hexagon_HL16:
222  case fixup_Hexagon_16_X:
223  case fixup_Hexagon_12_X:
224  case fixup_Hexagon_11_X:
225  case fixup_Hexagon_10_X:
226  case fixup_Hexagon_9_X:
227  case fixup_Hexagon_8_X:
228  case fixup_Hexagon_7_X:
229  case fixup_Hexagon_6_X:
230  case fixup_Hexagon_COPY:
259  case fixup_Hexagon_IE_32:
260  case fixup_Hexagon_IE_16:
300  // These relocations should always have a relocation recorded
301  return true;
302 
304  //IsResolved = false;
305  break;
306 
317  if (DisableFixup)
318  return true;
319  break;
320 
321  case FK_Data_1:
322  case FK_Data_2:
323  case FK_Data_4:
324  case FK_PCRel_4:
325  case fixup_Hexagon_32:
326  // Leave these relocations alone as they are used for EH.
327  return false;
328  }
329  return false;
330  }
331 
332  /// getFixupKindNumBytes - The number of bytes the fixup may change.
333  static unsigned getFixupKindNumBytes(unsigned Kind) {
334  switch (Kind) {
335  default:
336  return 0;
337 
338  case FK_Data_1:
339  return 1;
340  case FK_Data_2:
341  return 2;
342  case FK_Data_4: // this later gets mapped to R_HEX_32
343  case FK_PCRel_4: // this later gets mapped to R_HEX_32_PCREL
344  case fixup_Hexagon_32:
358  return 4;
359  }
360  }
361 
362  // Make up for left shift when encoding the operand.
364  switch((unsigned)Kind) {
365  default:
366  break;
367 
373  Value >>= 2;
374  break;
375 
381  Value &= 0x3f;
382  break;
383 
387  Value >>= 6;
388  break;
389  }
390  return (Value);
391  }
392 
393  void HandleFixupError(const int bits, const int align_bits,
394  const int64_t FixupValue, const char *fixupStr) const {
395  // Error: value 1124 out of range: -1024-1023 when resolving
396  // symbol in file xprtsock.S
397  const APInt IntMin = APInt::getSignedMinValue(bits+align_bits);
398  const APInt IntMax = APInt::getSignedMaxValue(bits+align_bits);
399  std::stringstream errStr;
400  errStr << "\nError: value " <<
401  FixupValue <<
402  " out of range: " <<
403  IntMin.getSExtValue() <<
404  "-" <<
405  IntMax.getSExtValue() <<
406  " when resolving " <<
407  fixupStr <<
408  " fixup\n";
409  llvm_unreachable(errStr.str().c_str());
410  }
411 
412  /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided
413  /// data fragment, at the offset specified by the fixup and following the
414  /// fixup kind as appropriate.
415  void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
416  const MCValue &Target, MutableArrayRef<char> Data,
417  uint64_t FixupValue, bool IsResolved,
418  const MCSubtargetInfo *STI) const override {
419 
420  // When FixupValue is 0 the relocation is external and there
421  // is nothing for us to do.
422  if (!FixupValue) return;
423 
424  MCFixupKind Kind = Fixup.getKind();
425  uint64_t Value;
426  uint32_t InstMask;
427  uint32_t Reloc;
428 
429  // LLVM gives us an encoded value, we have to convert it back
430  // to a real offset before we can use it.
431  uint32_t Offset = Fixup.getOffset();
432  unsigned NumBytes = getFixupKindNumBytes(Kind);
433  assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
434  char *InstAddr = Data.data() + Offset;
435 
436  Value = adjustFixupValue(Kind, FixupValue);
437  if(!Value)
438  return;
439  int sValue = (int)Value;
440 
441  switch((unsigned)Kind) {
442  default:
443  return;
444 
446  if (!(isIntN(7, sValue)))
447  HandleFixupError(7, 2, (int64_t)FixupValue, "B7_PCREL");
450  InstMask = 0x00001f18; // Word32_B7
451  Reloc = (((Value >> 2) & 0x1f) << 8) | // Value 6-2 = Target 12-8
452  ((Value & 0x3) << 3); // Value 1-0 = Target 4-3
453  break;
454 
456  if (!(isIntN(9, sValue)))
457  HandleFixupError(9, 2, (int64_t)FixupValue, "B9_PCREL");
460  InstMask = 0x003000fe; // Word32_B9
461  Reloc = (((Value >> 7) & 0x3) << 20) | // Value 8-7 = Target 21-20
462  ((Value & 0x7f) << 1); // Value 6-0 = Target 7-1
463  break;
464 
465  // Since the existing branches that use this relocation cannot be
466  // extended, they should only be fixed up if the target is within range.
468  if (!(isIntN(13, sValue)))
469  HandleFixupError(13, 2, (int64_t)FixupValue, "B13_PCREL");
472  InstMask = 0x00202ffe; // Word32_B13
473  Reloc = (((Value >> 12) & 0x1) << 21) | // Value 12 = Target 21
474  (((Value >> 11) & 0x1) << 13) | // Value 11 = Target 13
475  ((Value & 0x7ff) << 1); // Value 10-0 = Target 11-1
476  break;
477 
479  if (!(isIntN(15, sValue)))
480  HandleFixupError(15, 2, (int64_t)FixupValue, "B15_PCREL");
483  InstMask = 0x00df20fe; // Word32_B15
484  Reloc = (((Value >> 13) & 0x3) << 22) | // Value 14-13 = Target 23-22
485  (((Value >> 8) & 0x1f) << 16) | // Value 12-8 = Target 20-16
486  (((Value >> 7) & 0x1) << 13) | // Value 7 = Target 13
487  ((Value & 0x7f) << 1); // Value 6-0 = Target 7-1
488  break;
489 
491  if (!(isIntN(22, sValue)))
492  HandleFixupError(22, 2, (int64_t)FixupValue, "B22_PCREL");
495  InstMask = 0x01ff3ffe; // Word32_B22
496  Reloc = (((Value >> 13) & 0x1ff) << 16) | // Value 21-13 = Target 24-16
497  ((Value & 0x1fff) << 1); // Value 12-0 = Target 13-1
498  break;
499 
501  InstMask = 0x0fff3fff; // Word32_X26
502  Reloc = (((Value >> 14) & 0xfff) << 16) | // Value 25-14 = Target 27-16
503  (Value & 0x3fff); // Value 13-0 = Target 13-0
504  break;
505 
506  case FK_Data_1:
507  case FK_Data_2:
508  case FK_Data_4:
509  case fixup_Hexagon_32:
510  InstMask = 0xffffffff; // Word32
511  Reloc = Value;
512  break;
513  }
514 
515  LLVM_DEBUG(dbgs() << "Name=" << getFixupKindInfo(Kind).Name << "("
516  << (unsigned)Kind << ")\n");
517  LLVM_DEBUG(
518  uint32_t OldData = 0; for (unsigned i = 0; i < NumBytes; i++) OldData |=
519  (InstAddr[i] << (i * 8)) & (0xff << (i * 8));
520  dbgs() << "\tBValue=0x"; dbgs().write_hex(Value) << ": AValue=0x";
521  dbgs().write_hex(FixupValue)
522  << ": Offset=" << Offset << ": Size=" << Data.size() << ": OInst=0x";
523  dbgs().write_hex(OldData) << ": Reloc=0x"; dbgs().write_hex(Reloc););
524 
525  // For each byte of the fragment that the fixup touches, mask in the
526  // bits from the fixup value. The Value has been "split up" into the
527  // appropriate bitfields above.
528  for (unsigned i = 0; i < NumBytes; i++){
529  InstAddr[i] &= uint8_t(~InstMask >> (i * 8)) & 0xff; // Clear reloc bits
530  InstAddr[i] |= uint8_t(Reloc >> (i * 8)) & 0xff; // Apply new reloc
531  }
532 
533  LLVM_DEBUG(uint32_t NewData = 0;
534  for (unsigned i = 0; i < NumBytes; i++) NewData |=
535  (InstAddr[i] << (i * 8)) & (0xff << (i * 8));
536  dbgs() << ": NInst=0x"; dbgs().write_hex(NewData) << "\n";);
537  }
538 
539  bool isInstRelaxable(MCInst const &HMI) const {
540  const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI);
541  bool Relaxable = false;
542  // Branches and loop-setup insns are handled as necessary by relaxation.
545  MCID.isBranch()) ||
547  MCID.isBranch()) ||
549  HMI.getOpcode() != Hexagon::C4_addipc))
550  if (HexagonMCInstrInfo::isExtendable(*MCII, HMI)) {
551  Relaxable = true;
552  MCOperand const &Operand =
555  Relaxable = false;
556  }
557 
558  return Relaxable;
559  }
560 
561  /// MayNeedRelaxation - Check whether the given instruction may need
562  /// relaxation.
563  ///
564  /// \param Inst - The instruction to test.
565  bool mayNeedRelaxation(MCInst const &Inst,
566  const MCSubtargetInfo &STI) const override {
567  return true;
568  }
569 
570  /// fixupNeedsRelaxation - Target specific predicate for whether a given
571  /// fixup requires the associated instruction to be relaxed.
572  bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved,
573  uint64_t Value,
574  const MCRelaxableFragment *DF,
575  const MCAsmLayout &Layout,
576  const bool WasForced) const override {
577  MCInst const &MCB = DF->getInst();
579 
580  *RelaxTarget = nullptr;
581  MCInst &MCI = const_cast<MCInst &>(HexagonMCInstrInfo::instruction(
582  MCB, Fixup.getOffset() / HEXAGON_INSTR_SIZE));
583  bool Relaxable = isInstRelaxable(MCI);
584  if (Relaxable == false)
585  return false;
586  // If we cannot resolve the fixup value, it requires relaxation.
587  if (!Resolved) {
588  switch (Fixup.getTargetKind()) {
590  // GetFixupCount assumes B22 won't relax
592  default:
593  return false;
594  break;
598  case fixup_Hexagon_B7_PCREL: {
600  ++relaxedCnt;
601  *RelaxTarget = &MCI;
602  setExtender(Layout.getAssembler().getContext());
603  return true;
604  } else {
605  return false;
606  }
607  break;
608  }
609  }
610  }
611 
612  MCFixupKind Kind = Fixup.getKind();
613  int64_t sValue = Value;
614  int64_t maxValue;
615 
616  switch ((unsigned)Kind) {
618  maxValue = 1 << 8;
619  break;
621  maxValue = 1 << 10;
622  break;
624  maxValue = 1 << 16;
625  break;
627  maxValue = 1 << 23;
628  break;
629  default:
630  maxValue = INT64_MAX;
631  break;
632  }
633 
634  bool isFarAway = -maxValue > sValue || sValue > maxValue - 1;
635 
636  if (isFarAway) {
638  ++relaxedCnt;
639  *RelaxTarget = &MCI;
640  setExtender(Layout.getAssembler().getContext());
641  return true;
642  }
643  }
644 
645  return false;
646  }
647 
648  /// Simple predicate for targets where !Resolved implies requiring relaxation
649  bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
650  const MCRelaxableFragment *DF,
651  const MCAsmLayout &Layout) const override {
652  llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced");
653  }
654 
655  void relaxInstruction(MCInst &Inst,
656  const MCSubtargetInfo &STI) const override {
658  "Hexagon relaxInstruction only works on bundles");
659 
660  MCInst Res;
661  Res.setOpcode(Hexagon::BUNDLE);
663  // Copy the results into the bundle.
664  bool Update = false;
665  for (auto &I : HexagonMCInstrInfo::bundleInstructions(Inst)) {
666  MCInst &CrntHMI = const_cast<MCInst &>(*I.getInst());
667 
668  // if immediate extender needed, add it in
669  if (*RelaxTarget == &CrntHMI) {
670  Update = true;
672  "No room to insert extender for relaxation");
673 
674  MCInst *HMIx = takeExtender();
676  *MCII, CrntHMI,
679  *RelaxTarget = nullptr;
680  }
681  // now copy over the original instruction(the one we may have extended)
682  Res.addOperand(MCOperand::createInst(I.getInst()));
683  }
684 
685  Inst = std::move(Res);
686  (void)Update;
687  assert(Update && "Didn't find relaxation target");
688  }
689 
690  bool writeNopData(raw_ostream &OS, uint64_t Count,
691  const MCSubtargetInfo *STI) const override {
692  static const uint32_t Nopcode = 0x7f000000, // Hard-coded NOP.
693  ParseIn = 0x00004000, // In packet parse-bits.
694  ParseEnd = 0x0000c000; // End of packet parse-bits.
695 
696  while (Count % HEXAGON_INSTR_SIZE) {
697  LLVM_DEBUG(dbgs() << "Alignment not a multiple of the instruction size:"
698  << Count % HEXAGON_INSTR_SIZE << "/"
699  << HEXAGON_INSTR_SIZE << "\n");
700  --Count;
701  OS << '\0';
702  }
703 
704  while (Count) {
705  Count -= HEXAGON_INSTR_SIZE;
706  // Close the packet whenever a multiple of the maximum packet size remains
707  uint32_t ParseBits = (Count % (MaxPacketSize * HEXAGON_INSTR_SIZE)) ?
708  ParseIn : ParseEnd;
709  support::endian::write<uint32_t>(OS, Nopcode | ParseBits, Endian);
710  }
711  return true;
712  }
713 
714  void finishLayout(MCAssembler const &Asm,
715  MCAsmLayout &Layout) const override {
716  for (auto I : Layout.getSectionOrder()) {
717  auto &Fragments = I->getFragmentList();
718  for (auto &J : Fragments) {
719  switch (J.getKind()) {
720  default:
721  break;
722  case MCFragment::FT_Align: {
723  auto Size = Asm.computeFragmentSize(Layout, J);
724  for (auto K = J.getIterator();
725  K != Fragments.begin() && Size >= HEXAGON_PACKET_SIZE;) {
726  --K;
727  switch (K->getKind()) {
728  default:
729  break;
730  case MCFragment::FT_Align: {
731  // Don't pad before other alignments
732  Size = 0;
733  break;
734  }
736  MCContext &Context = Asm.getContext();
737  auto &RF = cast<MCRelaxableFragment>(*K);
738  auto &Inst = const_cast<MCInst &>(RF.getInst());
739  while (Size > 0 &&
740  HexagonMCInstrInfo::bundleSize(Inst) < MaxPacketSize) {
741  MCInst *Nop = Context.createMCInst();
742  Nop->setOpcode(Hexagon::A2_nop);
744  Size -= 4;
745  if (!HexagonMCChecker(
746  Context, *MCII, *RF.getSubtargetInfo(), Inst,
747  *Context.getRegisterInfo(), false)
748  .check()) {
749  Inst.erase(Inst.end() - 1);
750  Size = 0;
751  }
752  }
753  bool Error = HexagonMCShuffle(Context, true, *MCII,
754  *RF.getSubtargetInfo(), Inst);
755  //assert(!Error);
756  (void)Error;
757  ReplaceInstruction(Asm.getEmitter(), RF, Inst);
758  Layout.invalidateFragmentsFrom(&RF);
759  Size = 0; // Only look back one instruction
760  break;
761  }
762  }
763  }
764  }
765  }
766  }
767  }
768  }
769 }; // class HexagonAsmBackend
770 
771 } // namespace
772 
773 // MCAsmBackend
775  const MCSubtargetInfo &STI,
776  MCRegisterInfo const & /*MRI*/,
777  const MCTargetOptions &Options) {
778  const Triple &TT = STI.getTargetTriple();
779  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
780 
781  StringRef CPUString = Hexagon_MC::selectHexagonCPU(STI.getCPU());
782  return new HexagonAsmBackend(T, TT, OSABI, CPUString);
783 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:76
i
i
Definition: README.txt:29
HexagonMCTargetDesc.h
llvm::Hexagon::fixup_Hexagon_GOTREL_16_X
@ fixup_Hexagon_GOTREL_16_X
Definition: HexagonFixupKinds.h:90
llvm::Hexagon::fixup_Hexagon_DTPREL_LO16
@ fixup_Hexagon_DTPREL_LO16
Definition: HexagonFixupKinds.h:62
llvm::HexagonMCInstrInfo::mustNotExtend
bool mustNotExtend(MCExpr const &Expr)
Definition: HexagonMCInstrInfo.cpp:893
llvm::Hexagon::fixup_Hexagon_TPREL_HI16
@ fixup_Hexagon_TPREL_HI16
Definition: HexagonFixupKinds.h:85
llvm::Hexagon::fixup_Hexagon_B22_PCREL
@ fixup_Hexagon_B22_PCREL
Definition: HexagonFixupKinds.h:18
llvm::Hexagon::fixup_Hexagon_6_PCREL_X
@ fixup_Hexagon_6_PCREL_X
Definition: HexagonFixupKinds.h:88
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::Hexagon::fixup_Hexagon_9_X
@ fixup_Hexagon_9_X
Definition: HexagonFixupKinds.h:44
llvm::HexagonMCInstrInfo::getDesc
const MCInstrDesc & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:255
llvm::MCRelaxableFragment
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:270
llvm::Hexagon::fixup_Hexagon_TPREL_32
@ fixup_Hexagon_TPREL_32
Definition: HexagonFixupKinds.h:86
llvm::Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL_X
@ fixup_Hexagon_LD_PLT_B22_PCREL_X
Definition: HexagonFixupKinds.h:116
llvm::Hexagon::fixup_Hexagon_23_REG
@ fixup_Hexagon_23_REG
Definition: HexagonFixupKinds.h:112
llvm::MCAsmBackend::getFixupKindInfo
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
Definition: MCAsmBackend.cpp:78
llvm::Hexagon::fixup_Hexagon_B32_PCREL_X
@ fixup_Hexagon_B32_PCREL_X
Definition: HexagonFixupKinds.h:33
llvm::WebAssembly::Nop
static const unsigned Nop
Instruction opcodes emitted via means other than CodeGen.
Definition: WebAssemblyMCTargetDesc.h:133
llvm::Hexagon::fixup_Hexagon_GD_GOT_LO16
@ fixup_Hexagon_GD_GOT_LO16
Definition: HexagonFixupKinds.h:68
llvm::Hexagon::fixup_Hexagon_GD_GOT_32_6_X
@ fixup_Hexagon_GD_GOT_32_6_X
Definition: HexagonFixupKinds.h:98
llvm::HexagonII::TypeCR
@ TypeCR
Definition: HexagonDepITypes.h:23
llvm::MCInstrDesc::isBranch
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:304
llvm::Hexagon::fixup_Hexagon_IE_GOT_11_X
@ fixup_Hexagon_IE_GOT_11_X
Definition: HexagonFixupKinds.h:108
T
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:74
llvm::Hexagon::fixup_Hexagon_DTPREL_32_6_X
@ fixup_Hexagon_DTPREL_32_6_X
Definition: HexagonFixupKinds.h:95
llvm::Hexagon::fixup_Hexagon_GD_GOT_32
@ fixup_Hexagon_GD_GOT_32
Definition: HexagonFixupKinds.h:70
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:140
HEXAGON_INSTR_SIZE
#define HEXAGON_INSTR_SIZE
Definition: HexagonMCTargetDesc.h:33
llvm::Hexagon::fixup_Hexagon_IE_GOT_HI16
@ fixup_Hexagon_IE_GOT_HI16
Definition: HexagonFixupKinds.h:81
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::FirstTargetFixupKind
@ FirstTargetFixupKind
Definition: MCFixup.h:45
llvm::APInt::getSExtValue
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1490
llvm::Hexagon::fixup_Hexagon_B9_PCREL_X
@ fixup_Hexagon_B9_PCREL_X
Definition: HexagonFixupKinds.h:38
llvm::Hexagon::fixup_Hexagon_GPREL16_0
@ fixup_Hexagon_GPREL16_0
Definition: HexagonFixupKinds.h:26
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
MCAssembler.h
llvm::HexagonMCShuffle
bool HexagonMCShuffle(MCContext &Context, bool ReportErrors, MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &MCB)
Definition: HexagonMCShuffler.cpp:103
createMCInstrInfo
static MCInstrInfo * createMCInstrInfo()
Definition: WebAssemblyMCTargetDesc.cpp:43
llvm::Hexagon::fixup_Hexagon_LO16
@ fixup_Hexagon_LO16
Definition: HexagonFixupKinds.h:21
llvm::APInt::getSignedMaxValue
static APInt getSignedMaxValue(unsigned numBits)
Gets maximum signed value of APInt for a specific bit width.
Definition: APInt.h:189
llvm::Hexagon::fixup_Hexagon_GLOB_DAT
@ fixup_Hexagon_GLOB_DAT
Definition: HexagonFixupKinds.h:50
llvm::Hexagon::fixup_Hexagon_B13_PCREL_X
@ fixup_Hexagon_B13_PCREL_X
Definition: HexagonFixupKinds.h:37
llvm::Hexagon::fixup_Hexagon_6_X
@ fixup_Hexagon_6_X
Definition: HexagonFixupKinds.h:47
llvm::Hexagon::fixup_Hexagon_LD_GOT_11_X
@ fixup_Hexagon_LD_GOT_11_X
Definition: HexagonFixupKinds.h:103
llvm::Hexagon::fixup_Hexagon_32
@ fixup_Hexagon_32
Definition: HexagonFixupKinds.h:23
MCFixupKindInfo.h
llvm::Hexagon::fixup_Hexagon_HL16
@ fixup_Hexagon_HL16
Definition: HexagonFixupKinds.h:30
llvm::Hexagon::fixup_Hexagon_GOT_32
@ fixup_Hexagon_GOT_32
Definition: HexagonFixupKinds.h:59
llvm::Hexagon::fixup_Hexagon_GOTREL_32
@ fixup_Hexagon_GOTREL_32
Definition: HexagonFixupKinds.h:56
llvm::Hexagon::fixup_Hexagon_LD_GOT_LO16
@ fixup_Hexagon_LD_GOT_LO16
Definition: HexagonFixupKinds.h:72
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::MCEncodedFragmentWithFixups::getFixups
SmallVectorImpl< MCFixup > & getFixups()
Definition: MCFragment.h:222
llvm::Hexagon::fixup_Hexagon_GOTREL_32_6_X
@ fixup_Hexagon_GOTREL_32_6_X
Definition: HexagonFixupKinds.h:89
llvm::Hexagon::Fixups
Fixups
Definition: HexagonFixupKinds.h:16
llvm::Hexagon::fixup_Hexagon_DTPREL_HI16
@ fixup_Hexagon_DTPREL_HI16
Definition: HexagonFixupKinds.h:63
llvm::Hexagon::fixup_Hexagon_DTPREL_16
@ fixup_Hexagon_DTPREL_16
Definition: HexagonFixupKinds.h:65
llvm::Data
@ Data
Definition: SIMachineScheduler.h:55
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
HexagonBaseInfo.h
new
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj * new
Definition: README.txt:125
HexagonFixupKinds.h
llvm::Hexagon::fixup_Hexagon_16
@ fixup_Hexagon_16
Definition: HexagonFixupKinds.h:24
llvm::MCInst::setOpcode
void setOpcode(unsigned Op)
Definition: MCInst.h:197
llvm::Hexagon::fixup_Hexagon_GPREL16_3
@ fixup_Hexagon_GPREL16_3
Definition: HexagonFixupKinds.h:29
llvm::Hexagon::fixup_Hexagon_GD_GOT_16_X
@ fixup_Hexagon_GD_GOT_16_X
Definition: HexagonFixupKinds.h:99
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::Hexagon::fixup_Hexagon_IE_GOT_32_6_X
@ fixup_Hexagon_IE_GOT_32_6_X
Definition: HexagonFixupKinds.h:106
llvm::Hexagon::fixup_Hexagon_8_X
@ fixup_Hexagon_8_X
Definition: HexagonFixupKinds.h:45
llvm::Hexagon::fixup_Hexagon_TPREL_11_X
@ fixup_Hexagon_TPREL_11_X
Definition: HexagonFixupKinds.h:111
x3
In x86 we generate this spiffy xmm0 xmm0 ret in x86 we generate this which could be xmm1 movss xmm1 xmm0 ret In sse4 we could use insertps to make both better Here s another testcase that could use x3
Definition: README-SSE.txt:547
llvm::Hexagon::fixup_Hexagon_TPREL_16
@ fixup_Hexagon_TPREL_16
Definition: HexagonFixupKinds.h:87
HexagonMCShuffler.h
llvm::FK_Data_4
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
llvm::MCAsmBackend
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:42
llvm::Hexagon::fixup_Hexagon_TPREL_LO16
@ fixup_Hexagon_TPREL_LO16
Definition: HexagonFixupKinds.h:84
llvm::Hexagon::fixup_Hexagon_LD_GOT_16_X
@ fixup_Hexagon_LD_GOT_16_X
Definition: HexagonFixupKinds.h:102
MCAsmBackend.h
llvm::MutableArrayRef< char >
llvm::MCAsmLayout::invalidateFragmentsFrom
void invalidateFragmentsFrom(MCFragment *F)
Invalidate the fragments starting with F because it has been resized.
Definition: MCFragment.cpp:70
bits
demanded bits
Definition: DemandedBits.cpp:57
HexagonMCChecker.h
llvm::Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL
@ fixup_Hexagon_GD_PLT_B22_PCREL
Definition: HexagonFixupKinds.h:66
llvm::Hexagon::fixup_Hexagon_IE_HI16
@ fixup_Hexagon_IE_HI16
Definition: HexagonFixupKinds.h:77
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
HexagonMCInstrInfo.h
llvm::support::little
@ little
Definition: Endian.h:27
llvm::MCAssembler::getContext
MCContext & getContext() const
Definition: MCAssembler.h:321
int
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
Definition: README.txt:536
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition: MCSubtargetInfo.h:108
MCContext.h
llvm::HexagonMCInstrInfo::isBundle
bool isBundle(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:539
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::Hexagon::fixup_Hexagon_LD_PLT_B32_PCREL_X
@ fixup_Hexagon_LD_PLT_B32_PCREL_X
Definition: HexagonFixupKinds.h:117
llvm::HexagonMCChecker::check
bool check(bool FullCheck=true)
Definition: HexagonMCChecker.cpp:220
llvm::MCRelaxableFragment::setInst
void setInst(const MCInst &Value)
Definition: MCFragment.h:284
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::HexagonMCInstrInfo::bundleInstructions
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:103
MCSubtargetInfo.h
llvm::MCRelaxableFragment::getInst
const MCInst & getInst() const
Definition: MCFragment.h:283
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::Hexagon::fixup_Hexagon_7_X
@ fixup_Hexagon_7_X
Definition: HexagonFixupKinds.h:46
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:54
llvm::Hexagon::fixup_Hexagon_DTPREL_11_X
@ fixup_Hexagon_DTPREL_11_X
Definition: HexagonFixupKinds.h:97
INT64_MAX
#define INT64_MAX
Definition: DataTypes.h:71
llvm::MCInst::end
iterator end()
Definition: MCInst.h:221
llvm::Hexagon::fixup_Hexagon_DTPREL_32
@ fixup_Hexagon_DTPREL_32
Definition: HexagonFixupKinds.h:64
llvm::isIntN
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:460
llvm::Hexagon::NumTargetFixupKinds
@ NumTargetFixupKinds
Definition: HexagonFixupKinds.h:120
llvm::HexagonMCInstrInfo::bundleSize
size_t bundleSize(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:116
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::MCInst::erase
void erase(iterator I)
Definition: MCInst.h:216
DF
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
llvm::MCOperand::createInst
static MCOperand createInst(const MCInst *Val)
Definition: MCInst.h:169
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::SmallString< 256 >
llvm::Hexagon::fixup_Hexagon_GOT_HI16
@ fixup_Hexagon_GOT_HI16
Definition: HexagonFixupKinds.h:58
llvm::Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL_X
@ fixup_Hexagon_GD_PLT_B22_PCREL_X
Definition: HexagonFixupKinds.h:114
llvm::Hexagon::fixup_Hexagon_GPREL16_1
@ fixup_Hexagon_GPREL16_1
Definition: HexagonFixupKinds.h:27
llvm::Hexagon::fixup_Hexagon_B15_PCREL_X
@ fixup_Hexagon_B15_PCREL_X
Definition: HexagonFixupKinds.h:36
llvm::Hexagon::fixup_Hexagon_LD_GOT_HI16
@ fixup_Hexagon_LD_GOT_HI16
Definition: HexagonFixupKinds.h:73
llvm::MCAsmLayout::getSectionOrder
llvm::SmallVectorImpl< MCSection * > & getSectionOrder()
Definition: MCAsmLayout.h:69
getFixupKindNumBytes
static unsigned getFixupKindNumBytes(unsigned Kind)
The number of bytes the fixup may change.
Definition: AArch64AsmBackend.cpp:108
HexagonMCCodeEmitter.h
llvm::Hexagon::fixup_Hexagon_10_X
@ fixup_Hexagon_10_X
Definition: HexagonFixupKinds.h:43
llvm::cl::opt< bool >
llvm::HexagonMCInstrInfo::packetSize
unsigned packetSize(StringRef CPU)
Definition: HexagonMCInstrInfo.cpp:915
llvm::MCAssembler
Definition: MCAssembler.h:73
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:409
uint64_t
MCELFObjectWriter.h
llvm::Hexagon::fixup_Hexagon_IE_32_6_X
@ fixup_Hexagon_IE_32_6_X
Definition: HexagonFixupKinds.h:104
llvm::Hexagon::fixup_Hexagon_TPREL_32_6_X
@ fixup_Hexagon_TPREL_32_6_X
Definition: HexagonFixupKinds.h:109
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::Hexagon::fixup_Hexagon_GOT_LO16
@ fixup_Hexagon_GOT_LO16
Definition: HexagonFixupKinds.h:57
llvm::MCFixupKindInfo::FKF_IsPCRel
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
Definition: MCFixupKindInfo.h:19
llvm::Hexagon::fixup_Hexagon_GOTREL_HI16
@ fixup_Hexagon_GOTREL_HI16
Definition: HexagonFixupKinds.h:55
llvm::MCSubtargetInfo::getCPU
StringRef getCPU() const
Definition: MCSubtargetInfo.h:109
I
#define I(x, y, z)
Definition: MD5.cpp:58
adjustFixupValue
static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target, uint64_t Value, MCContext &Ctx, const Triple &TheTriple, bool IsResolved)
Definition: AArch64AsmBackend.cpp:151
llvm::Hexagon::fixup_Hexagon_GOT_32_6_X
@ fixup_Hexagon_GOT_32_6_X
Definition: HexagonFixupKinds.h:92
llvm::HexagonMCInstrInfo::deriveExtender
MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst, MCOperand const &MO)
Definition: HexagonMCInstrInfo.cpp:191
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::Hexagon::fixup_Hexagon_GOTREL_LO16
@ fixup_Hexagon_GOTREL_LO16
Definition: HexagonFixupKinds.h:54
llvm::Hexagon::fixup_Hexagon_B9_PCREL
@ fixup_Hexagon_B9_PCREL
Definition: HexagonFixupKinds.h:32
llvm::MCFixupKindInfo
Target independent information on a fixup kind.
Definition: MCFixupKindInfo.h:15
llvm::Hexagon::fixup_Hexagon_GD_GOT_HI16
@ fixup_Hexagon_GD_GOT_HI16
Definition: HexagonFixupKinds.h:69
llvm::FK_Data_1
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
llvm::Hexagon::fixup_Hexagon_B7_PCREL
@ fixup_Hexagon_B7_PCREL
Definition: HexagonFixupKinds.h:20
llvm::FK_PCRel_4
@ FK_PCRel_4
A four-byte pc relative fixup.
Definition: MCFixup.h:30
llvm::MCTargetOptions
Definition: MCTargetOptions.h:36
llvm::Hexagon::fixup_Hexagon_IE_32
@ fixup_Hexagon_IE_32
Definition: HexagonFixupKinds.h:78
llvm::MCFragment::FT_Align
@ FT_Align
Definition: MCFragment.h:35
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MCELFObjectTargetWriter::getOSABI
uint8_t getOSABI() const
Definition: MCELFObjectWriter.h:101
llvm::Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL
@ fixup_Hexagon_LD_PLT_B22_PCREL
Definition: HexagonFixupKinds.h:67
Fixup
PowerPC TLS Dynamic Call Fixup
Definition: PPCTLSDynamicCall.cpp:233
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
uint32_t
llvm::Hexagon::fixup_Hexagon_IE_LO16
@ fixup_Hexagon_IE_LO16
Definition: HexagonFixupKinds.h:76
llvm::Hexagon::fixup_Hexagon_8
@ fixup_Hexagon_8
Definition: HexagonFixupKinds.h:25
llvm::Hexagon::fixup_Hexagon_32_6_X
@ fixup_Hexagon_32_6_X
Definition: HexagonFixupKinds.h:34
llvm::HexagonII::TypeCJ
@ TypeCJ
Definition: HexagonDepITypes.h:22
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:280
llvm::HexagonMCInstrInfo::getExtendableOp
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:316
llvm::Hexagon::fixup_Hexagon_GPREL16_2
@ fixup_Hexagon_GPREL16_2
Definition: HexagonFixupKinds.h:28
llvm::Hexagon::fixup_Hexagon_LD_GOT_32
@ fixup_Hexagon_LD_GOT_32
Definition: HexagonFixupKinds.h:74
llvm::Hexagon::fixup_Hexagon_DTPMOD_32
@ fixup_Hexagon_DTPMOD_32
Definition: HexagonFixupKinds.h:61
DisableFixup
static cl::opt< bool > DisableFixup("mno-fixup", cl::desc("Disable fixing up resolved relocations for Hexagon"))
llvm::Hexagon::fixup_Hexagon_GD_PLT_B32_PCREL_X
@ fixup_Hexagon_GD_PLT_B32_PCREL_X
Definition: HexagonFixupKinds.h:115
MCAsmLayout.h
llvm::Hexagon::fixup_Hexagon_JMP_SLOT
@ fixup_Hexagon_JMP_SLOT
Definition: HexagonFixupKinds.h:51
MCObjectWriter.h
llvm::Hexagon::fixup_Hexagon_GD_GOT_16
@ fixup_Hexagon_GD_GOT_16
Definition: HexagonFixupKinds.h:71
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
EndianStream.h
llvm::Hexagon::fixup_Hexagon_B22_PCREL_X
@ fixup_Hexagon_B22_PCREL_X
Definition: HexagonFixupKinds.h:35
llvm::HexagonMCChecker
Check for a valid bundle.
Definition: HexagonMCChecker.h:34
llvm::HexagonMCInstrInfo::getType
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Return the Hexagon ISA class for the insn.
Definition: HexagonMCInstrInfo.cpp:423
llvm::MCAsmLayout
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
llvm::MCCodeEmitter
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:155
llvm::Hexagon::fixup_Hexagon_B7_PCREL_X
@ fixup_Hexagon_B7_PCREL_X
Definition: HexagonFixupKinds.h:39
llvm::MCEncodedFragment::getSubtargetInfo
const MCSubtargetInfo * getSubtargetInfo() const
Retrieve the MCSubTargetInfo in effect when the instruction was encoded.
Definition: MCFragment.h:172
llvm::Hexagon::fixup_Hexagon_32_PCREL
@ fixup_Hexagon_32_PCREL
Definition: HexagonFixupKinds.h:48
llvm::Hexagon::fixup_Hexagon_IE_16
@ fixup_Hexagon_IE_16
Definition: HexagonFixupKinds.h:79
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition: MCInst.h:114
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::Hexagon::fixup_Hexagon_GOT_16_X
@ fixup_Hexagon_GOT_16_X
Definition: HexagonFixupKinds.h:93
llvm::Hexagon::fixup_Hexagon_IE_16_X
@ fixup_Hexagon_IE_16_X
Definition: HexagonFixupKinds.h:105
llvm::HexagonMCInstrInfo::getExtendableOperand
const MCOperand & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:323
llvm::Hexagon::fixup_Hexagon_IE_GOT_32
@ fixup_Hexagon_IE_GOT_32
Definition: HexagonFixupKinds.h:82
llvm::HexagonMCInstrInfo::instruction
const MCInst & instruction(MCInst const &MCB, size_t Index)
Definition: HexagonMCInstrInfo.cpp:526
llvm::APInt::getSignedMinValue
static APInt getSignedMinValue(unsigned numBits)
Gets minimum signed value of APInt for a specific bit width.
Definition: APInt.h:199
llvm::Hexagon::fixup_Hexagon_PLT_B22_PCREL
@ fixup_Hexagon_PLT_B22_PCREL
Definition: HexagonFixupKinds.h:53
llvm::MCFragment::FT_Relaxable
@ FT_Relaxable
Definition: MCFragment.h:40
llvm::Hexagon::fixup_Hexagon_LD_GOT_16
@ fixup_Hexagon_LD_GOT_16
Definition: HexagonFixupKinds.h:75
llvm::HexagonII::TypeNCJ
@ TypeNCJ
Definition: HexagonDepITypes.h:57
llvm::Hexagon::fixup_Hexagon_LD_GOT_32_6_X
@ fixup_Hexagon_LD_GOT_32_6_X
Definition: HexagonFixupKinds.h:101
llvm::Hexagon::fixup_Hexagon_HI16
@ fixup_Hexagon_HI16
Definition: HexagonFixupKinds.h:22
llvm::MCFixupKind
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
llvm::Hexagon_MC::selectHexagonCPU
StringRef selectHexagonCPU(StringRef CPU)
Definition: HexagonMCTargetDesc.cpp:140
llvm::Hexagon::fixup_Hexagon_GOT_11_X
@ fixup_Hexagon_GOT_11_X
Definition: HexagonFixupKinds.h:94
llvm::Hexagon::fixup_Hexagon_GOT_16
@ fixup_Hexagon_GOT_16
Definition: HexagonFixupKinds.h:60
llvm::Hexagon::fixup_Hexagon_GD_GOT_11_X
@ fixup_Hexagon_GD_GOT_11_X
Definition: HexagonFixupKinds.h:100
llvm::Hexagon::fixup_Hexagon_11_X
@ fixup_Hexagon_11_X
Definition: HexagonFixupKinds.h:42
llvm::Hexagon::fixup_Hexagon_B15_PCREL
@ fixup_Hexagon_B15_PCREL
Definition: HexagonFixupKinds.h:19
llvm::Hexagon::fixup_Hexagon_IE_GOT_LO16
@ fixup_Hexagon_IE_GOT_LO16
Definition: HexagonFixupKinds.h:80
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
support
Reimplement select in terms of SEL *We would really like to support but we need to prove that the add doesn t need to overflow between the two bit chunks *Implement pre post increment support(e.g. PR935) *Implement smarter const ant generation for binops with large immediates. A few ARMv6T2 ops should be pattern matched
Definition: README.txt:10
llvm::Hexagon::fixup_Hexagon_TPREL_16_X
@ fixup_Hexagon_TPREL_16_X
Definition: HexagonFixupKinds.h:110
llvm::raw_svector_ostream
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:662
llvm::Hexagon::fixup_Hexagon_12_X
@ fixup_Hexagon_12_X
Definition: HexagonFixupKinds.h:41
llvm::Hexagon::fixup_Hexagon_B13_PCREL
@ fixup_Hexagon_B13_PCREL
Definition: HexagonFixupKinds.h:31
llvm::Hexagon::fixup_Hexagon_27_REG
@ fixup_Hexagon_27_REG
Definition: HexagonFixupKinds.h:113
llvm::Hexagon::fixup_Hexagon_IE_GOT_16_X
@ fixup_Hexagon_IE_GOT_16_X
Definition: HexagonFixupKinds.h:107
llvm::Hexagon::fixup_Hexagon_RELATIVE
@ fixup_Hexagon_RELATIVE
Definition: HexagonFixupKinds.h:52
llvm::HexagonII::TypeJ
@ TypeJ
Definition: HexagonDepITypes.h:53
llvm::Hexagon::fixup_Hexagon_GOTREL_11_X
@ fixup_Hexagon_GOTREL_11_X
Definition: HexagonFixupKinds.h:91
llvm::HexStyle::Asm
@ Asm
0ffh
Definition: MCInstPrinter.h:34
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::MCAsmLayout::getAssembler
MCAssembler & getAssembler() const
Get the assembler object this is a layout for.
Definition: MCAsmLayout.h:50
llvm::MCValue
This represents an "assembler immediate".
Definition: MCValue.h:36
llvm::cl::desc
Definition: CommandLine.h:405
llvm::Hexagon::fixup_Hexagon_16_X
@ fixup_Hexagon_16_X
Definition: HexagonFixupKinds.h:40
llvm::FK_Data_2
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
HEXAGON_PACKET_SIZE
#define HEXAGON_PACKET_SIZE
Definition: HexagonMCTargetDesc.h:36
llvm::Hexagon::fixup_Hexagon_IE_GOT_16
@ fixup_Hexagon_IE_GOT_16
Definition: HexagonFixupKinds.h:83
TargetRegistry.h
llvm::createHexagonAsmBackend
MCAsmBackend * createHexagonAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: HexagonAsmBackend.cpp:774
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::MCFixup
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
Debug.h
llvm::Hexagon::fixup_Hexagon_COPY
@ fixup_Hexagon_COPY
Definition: HexagonFixupKinds.h:49
llvm::Hexagon::fixup_Hexagon_DTPREL_16_X
@ fixup_Hexagon_DTPREL_16_X
Definition: HexagonFixupKinds.h:96
llvm::MCEncodedFragmentWithContents::getContents
SmallVectorImpl< char > & getContents()
Definition: MCFragment.h:196
llvm::HexagonMCInstrInfo::isExtendable
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:620
llvm::raw_ostream::write_hex
raw_ostream & write_hex(unsigned long long N)
Output N in hexadecimal, without any prefix or padding.
Definition: raw_ostream.cpp:139
llvm::createHexagonELFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createHexagonELFObjectWriter(uint8_t OSABI, StringRef CPU)
Definition: HexagonELFObjectWriter.cpp:301