LLVM  14.0.0git
HexagonAsmBackend.cpp
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1 //===-- HexagonAsmBackend.cpp - Hexagon Assembler Backend -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "HexagonFixupKinds.h"
16 #include "llvm/MC/MCAsmBackend.h"
17 #include "llvm/MC/MCAsmLayout.h"
18 #include "llvm/MC/MCAssembler.h"
19 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCObjectWriter.h"
24 #include "llvm/MC/TargetRegistry.h"
25 #include "llvm/Support/Debug.h"
27 
28 #include <sstream>
29 
30 using namespace llvm;
31 using namespace Hexagon;
32 
33 #define DEBUG_TYPE "hexagon-asm-backend"
34 
36  ("mno-fixup", cl::desc("Disable fixing up resolved relocations for Hexagon"));
37 
38 namespace {
39 
40 class HexagonAsmBackend : public MCAsmBackend {
41  uint8_t OSABI;
42  StringRef CPU;
43  mutable uint64_t relaxedCnt;
44  std::unique_ptr <MCInstrInfo> MCII;
45  std::unique_ptr <MCInst *> RelaxTarget;
46  MCInst * Extender;
47  unsigned MaxPacketSize;
48 
49  void ReplaceInstruction(MCCodeEmitter &E, MCRelaxableFragment &RF,
50  MCInst &HMB) const {
52  SmallString<256> Code;
53  raw_svector_ostream VecOS(Code);
54  E.encodeInstruction(HMB, VecOS, Fixups, *RF.getSubtargetInfo());
55 
56  // Update the fragment.
57  RF.setInst(HMB);
58  RF.getContents() = Code;
59  RF.getFixups() = Fixups;
60  }
61 
62 public:
63  HexagonAsmBackend(const Target &T, const Triple &TT, uint8_t OSABI,
64  StringRef CPU)
65  : MCAsmBackend(support::little), OSABI(OSABI), CPU(CPU), relaxedCnt(0),
66  MCII(T.createMCInstrInfo()), RelaxTarget(new MCInst *),
67  Extender(nullptr), MaxPacketSize(HexagonMCInstrInfo::packetSize(CPU))
68  {}
69 
70  std::unique_ptr<MCObjectTargetWriter>
71  createObjectTargetWriter() const override {
72  return createHexagonELFObjectWriter(OSABI, CPU);
73  }
74 
75  void setExtender(MCContext &Context) const {
76  if (Extender == nullptr)
77  const_cast<HexagonAsmBackend *>(this)->Extender = Context.createMCInst();
78  }
79 
80  MCInst *takeExtender() const {
81  assert(Extender != nullptr);
82  MCInst * Result = Extender;
83  const_cast<HexagonAsmBackend *>(this)->Extender = nullptr;
84  return Result;
85  }
86 
87  unsigned getNumFixupKinds() const override {
89  }
90 
91  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
92  const static MCFixupKindInfo Infos[Hexagon::NumTargetFixupKinds] = {
93  // This table *must* be in same the order of fixup_* kinds in
94  // HexagonFixupKinds.h.
95  //
96  // namei offset bits flags
97  { "fixup_Hexagon_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
98  { "fixup_Hexagon_B15_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
99  { "fixup_Hexagon_B7_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
100  { "fixup_Hexagon_LO16", 0, 32, 0 },
101  { "fixup_Hexagon_HI16", 0, 32, 0 },
102  { "fixup_Hexagon_32", 0, 32, 0 },
103  { "fixup_Hexagon_16", 0, 32, 0 },
104  { "fixup_Hexagon_8", 0, 32, 0 },
105  { "fixup_Hexagon_GPREL16_0", 0, 32, 0 },
106  { "fixup_Hexagon_GPREL16_1", 0, 32, 0 },
107  { "fixup_Hexagon_GPREL16_2", 0, 32, 0 },
108  { "fixup_Hexagon_GPREL16_3", 0, 32, 0 },
109  { "fixup_Hexagon_HL16", 0, 32, 0 },
110  { "fixup_Hexagon_B13_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
111  { "fixup_Hexagon_B9_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
112  { "fixup_Hexagon_B32_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
113  { "fixup_Hexagon_32_6_X", 0, 32, 0 },
114  { "fixup_Hexagon_B22_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
115  { "fixup_Hexagon_B15_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
116  { "fixup_Hexagon_B13_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
117  { "fixup_Hexagon_B9_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
118  { "fixup_Hexagon_B7_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
119  { "fixup_Hexagon_16_X", 0, 32, 0 },
120  { "fixup_Hexagon_12_X", 0, 32, 0 },
121  { "fixup_Hexagon_11_X", 0, 32, 0 },
122  { "fixup_Hexagon_10_X", 0, 32, 0 },
123  { "fixup_Hexagon_9_X", 0, 32, 0 },
124  { "fixup_Hexagon_8_X", 0, 32, 0 },
125  { "fixup_Hexagon_7_X", 0, 32, 0 },
126  { "fixup_Hexagon_6_X", 0, 32, 0 },
127  { "fixup_Hexagon_32_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
128  { "fixup_Hexagon_COPY", 0, 32, 0 },
129  { "fixup_Hexagon_GLOB_DAT", 0, 32, 0 },
130  { "fixup_Hexagon_JMP_SLOT", 0, 32, 0 },
131  { "fixup_Hexagon_RELATIVE", 0, 32, 0 },
132  { "fixup_Hexagon_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
133  { "fixup_Hexagon_GOTREL_LO16", 0, 32, 0 },
134  { "fixup_Hexagon_GOTREL_HI16", 0, 32, 0 },
135  { "fixup_Hexagon_GOTREL_32", 0, 32, 0 },
136  { "fixup_Hexagon_GOT_LO16", 0, 32, 0 },
137  { "fixup_Hexagon_GOT_HI16", 0, 32, 0 },
138  { "fixup_Hexagon_GOT_32", 0, 32, 0 },
139  { "fixup_Hexagon_GOT_16", 0, 32, 0 },
140  { "fixup_Hexagon_DTPMOD_32", 0, 32, 0 },
141  { "fixup_Hexagon_DTPREL_LO16", 0, 32, 0 },
142  { "fixup_Hexagon_DTPREL_HI16", 0, 32, 0 },
143  { "fixup_Hexagon_DTPREL_32", 0, 32, 0 },
144  { "fixup_Hexagon_DTPREL_16", 0, 32, 0 },
145  { "fixup_Hexagon_GD_PLT_B22_PCREL",0, 32, MCFixupKindInfo::FKF_IsPCRel },
146  { "fixup_Hexagon_LD_PLT_B22_PCREL",0, 32, MCFixupKindInfo::FKF_IsPCRel },
147  { "fixup_Hexagon_GD_GOT_LO16", 0, 32, 0 },
148  { "fixup_Hexagon_GD_GOT_HI16", 0, 32, 0 },
149  { "fixup_Hexagon_GD_GOT_32", 0, 32, 0 },
150  { "fixup_Hexagon_GD_GOT_16", 0, 32, 0 },
151  { "fixup_Hexagon_LD_GOT_LO16", 0, 32, 0 },
152  { "fixup_Hexagon_LD_GOT_HI16", 0, 32, 0 },
153  { "fixup_Hexagon_LD_GOT_32", 0, 32, 0 },
154  { "fixup_Hexagon_LD_GOT_16", 0, 32, 0 },
155  { "fixup_Hexagon_IE_LO16", 0, 32, 0 },
156  { "fixup_Hexagon_IE_HI16", 0, 32, 0 },
157  { "fixup_Hexagon_IE_32", 0, 32, 0 },
158  { "fixup_Hexagon_IE_16", 0, 32, 0 },
159  { "fixup_Hexagon_IE_GOT_LO16", 0, 32, 0 },
160  { "fixup_Hexagon_IE_GOT_HI16", 0, 32, 0 },
161  { "fixup_Hexagon_IE_GOT_32", 0, 32, 0 },
162  { "fixup_Hexagon_IE_GOT_16", 0, 32, 0 },
163  { "fixup_Hexagon_TPREL_LO16", 0, 32, 0 },
164  { "fixup_Hexagon_TPREL_HI16", 0, 32, 0 },
165  { "fixup_Hexagon_TPREL_32", 0, 32, 0 },
166  { "fixup_Hexagon_TPREL_16", 0, 32, 0 },
167  { "fixup_Hexagon_6_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
168  { "fixup_Hexagon_GOTREL_32_6_X", 0, 32, 0 },
169  { "fixup_Hexagon_GOTREL_16_X", 0, 32, 0 },
170  { "fixup_Hexagon_GOTREL_11_X", 0, 32, 0 },
171  { "fixup_Hexagon_GOT_32_6_X", 0, 32, 0 },
172  { "fixup_Hexagon_GOT_16_X", 0, 32, 0 },
173  { "fixup_Hexagon_GOT_11_X", 0, 32, 0 },
174  { "fixup_Hexagon_DTPREL_32_6_X", 0, 32, 0 },
175  { "fixup_Hexagon_DTPREL_16_X", 0, 32, 0 },
176  { "fixup_Hexagon_DTPREL_11_X", 0, 32, 0 },
177  { "fixup_Hexagon_GD_GOT_32_6_X", 0, 32, 0 },
178  { "fixup_Hexagon_GD_GOT_16_X", 0, 32, 0 },
179  { "fixup_Hexagon_GD_GOT_11_X", 0, 32, 0 },
180  { "fixup_Hexagon_LD_GOT_32_6_X", 0, 32, 0 },
181  { "fixup_Hexagon_LD_GOT_16_X", 0, 32, 0 },
182  { "fixup_Hexagon_LD_GOT_11_X", 0, 32, 0 },
183  { "fixup_Hexagon_IE_32_6_X", 0, 32, 0 },
184  { "fixup_Hexagon_IE_16_X", 0, 32, 0 },
185  { "fixup_Hexagon_IE_GOT_32_6_X", 0, 32, 0 },
186  { "fixup_Hexagon_IE_GOT_16_X", 0, 32, 0 },
187  { "fixup_Hexagon_IE_GOT_11_X", 0, 32, 0 },
188  { "fixup_Hexagon_TPREL_32_6_X", 0, 32, 0 },
189  { "fixup_Hexagon_TPREL_16_X", 0, 32, 0 },
190  { "fixup_Hexagon_TPREL_11_X", 0, 32, 0 },
191  { "fixup_Hexagon_GD_PLT_B22_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel },
192  { "fixup_Hexagon_GD_PLT_B32_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel },
193  { "fixup_Hexagon_LD_PLT_B22_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel },
194  { "fixup_Hexagon_LD_PLT_B32_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel }
195  };
196 
199 
200  assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
201  "Invalid kind!");
202  return Infos[Kind - FirstTargetFixupKind];
203  }
204 
205  bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
206  const MCValue &Target) override {
207  switch(Fixup.getTargetKind()) {
208  default:
209  llvm_unreachable("Unknown Fixup Kind!");
210 
211  case fixup_Hexagon_LO16:
212  case fixup_Hexagon_HI16:
213  case fixup_Hexagon_16:
214  case fixup_Hexagon_8:
219  case fixup_Hexagon_HL16:
221  case fixup_Hexagon_16_X:
222  case fixup_Hexagon_12_X:
223  case fixup_Hexagon_11_X:
224  case fixup_Hexagon_10_X:
225  case fixup_Hexagon_9_X:
226  case fixup_Hexagon_8_X:
227  case fixup_Hexagon_7_X:
228  case fixup_Hexagon_6_X:
229  case fixup_Hexagon_COPY:
258  case fixup_Hexagon_IE_32:
259  case fixup_Hexagon_IE_16:
299  // These relocations should always have a relocation recorded
300  return true;
301 
303  //IsResolved = false;
304  break;
305 
316  if (DisableFixup)
317  return true;
318  break;
319 
320  case FK_Data_1:
321  case FK_Data_2:
322  case FK_Data_4:
323  case FK_PCRel_4:
324  case fixup_Hexagon_32:
325  // Leave these relocations alone as they are used for EH.
326  return false;
327  }
328  return false;
329  }
330 
331  /// getFixupKindNumBytes - The number of bytes the fixup may change.
332  static unsigned getFixupKindNumBytes(unsigned Kind) {
333  switch (Kind) {
334  default:
335  return 0;
336 
337  case FK_Data_1:
338  return 1;
339  case FK_Data_2:
340  return 2;
341  case FK_Data_4: // this later gets mapped to R_HEX_32
342  case FK_PCRel_4: // this later gets mapped to R_HEX_32_PCREL
343  case fixup_Hexagon_32:
357  return 4;
358  }
359  }
360 
361  // Make up for left shift when encoding the operand.
363  switch((unsigned)Kind) {
364  default:
365  break;
366 
372  Value >>= 2;
373  break;
374 
380  Value &= 0x3f;
381  break;
382 
386  Value >>= 6;
387  break;
388  }
389  return (Value);
390  }
391 
392  void HandleFixupError(const int bits, const int align_bits,
393  const int64_t FixupValue, const char *fixupStr) const {
394  // Error: value 1124 out of range: -1024-1023 when resolving
395  // symbol in file xprtsock.S
396  const APInt IntMin = APInt::getSignedMinValue(bits+align_bits);
397  const APInt IntMax = APInt::getSignedMaxValue(bits+align_bits);
398  std::stringstream errStr;
399  errStr << "\nError: value " <<
400  FixupValue <<
401  " out of range: " <<
402  IntMin.getSExtValue() <<
403  "-" <<
404  IntMax.getSExtValue() <<
405  " when resolving " <<
406  fixupStr <<
407  " fixup\n";
408  llvm_unreachable(errStr.str().c_str());
409  }
410 
411  /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided
412  /// data fragment, at the offset specified by the fixup and following the
413  /// fixup kind as appropriate.
414  void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
415  const MCValue &Target, MutableArrayRef<char> Data,
416  uint64_t FixupValue, bool IsResolved,
417  const MCSubtargetInfo *STI) const override {
418 
419  // When FixupValue is 0 the relocation is external and there
420  // is nothing for us to do.
421  if (!FixupValue) return;
422 
423  MCFixupKind Kind = Fixup.getKind();
424  uint64_t Value;
425  uint32_t InstMask;
426  uint32_t Reloc;
427 
428  // LLVM gives us an encoded value, we have to convert it back
429  // to a real offset before we can use it.
430  uint32_t Offset = Fixup.getOffset();
431  unsigned NumBytes = getFixupKindNumBytes(Kind);
432  assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
433  char *InstAddr = Data.data() + Offset;
434 
435  Value = adjustFixupValue(Kind, FixupValue);
436  if(!Value)
437  return;
438  int sValue = (int)Value;
439 
440  switch((unsigned)Kind) {
441  default:
442  return;
443 
445  if (!(isIntN(7, sValue)))
446  HandleFixupError(7, 2, (int64_t)FixupValue, "B7_PCREL");
449  InstMask = 0x00001f18; // Word32_B7
450  Reloc = (((Value >> 2) & 0x1f) << 8) | // Value 6-2 = Target 12-8
451  ((Value & 0x3) << 3); // Value 1-0 = Target 4-3
452  break;
453 
455  if (!(isIntN(9, sValue)))
456  HandleFixupError(9, 2, (int64_t)FixupValue, "B9_PCREL");
459  InstMask = 0x003000fe; // Word32_B9
460  Reloc = (((Value >> 7) & 0x3) << 20) | // Value 8-7 = Target 21-20
461  ((Value & 0x7f) << 1); // Value 6-0 = Target 7-1
462  break;
463 
464  // Since the existing branches that use this relocation cannot be
465  // extended, they should only be fixed up if the target is within range.
467  if (!(isIntN(13, sValue)))
468  HandleFixupError(13, 2, (int64_t)FixupValue, "B13_PCREL");
471  InstMask = 0x00202ffe; // Word32_B13
472  Reloc = (((Value >> 12) & 0x1) << 21) | // Value 12 = Target 21
473  (((Value >> 11) & 0x1) << 13) | // Value 11 = Target 13
474  ((Value & 0x7ff) << 1); // Value 10-0 = Target 11-1
475  break;
476 
478  if (!(isIntN(15, sValue)))
479  HandleFixupError(15, 2, (int64_t)FixupValue, "B15_PCREL");
482  InstMask = 0x00df20fe; // Word32_B15
483  Reloc = (((Value >> 13) & 0x3) << 22) | // Value 14-13 = Target 23-22
484  (((Value >> 8) & 0x1f) << 16) | // Value 12-8 = Target 20-16
485  (((Value >> 7) & 0x1) << 13) | // Value 7 = Target 13
486  ((Value & 0x7f) << 1); // Value 6-0 = Target 7-1
487  break;
488 
490  if (!(isIntN(22, sValue)))
491  HandleFixupError(22, 2, (int64_t)FixupValue, "B22_PCREL");
494  InstMask = 0x01ff3ffe; // Word32_B22
495  Reloc = (((Value >> 13) & 0x1ff) << 16) | // Value 21-13 = Target 24-16
496  ((Value & 0x1fff) << 1); // Value 12-0 = Target 13-1
497  break;
498 
500  InstMask = 0x0fff3fff; // Word32_X26
501  Reloc = (((Value >> 14) & 0xfff) << 16) | // Value 25-14 = Target 27-16
502  (Value & 0x3fff); // Value 13-0 = Target 13-0
503  break;
504 
505  case FK_Data_1:
506  case FK_Data_2:
507  case FK_Data_4:
508  case fixup_Hexagon_32:
509  InstMask = 0xffffffff; // Word32
510  Reloc = Value;
511  break;
512  }
513 
514  LLVM_DEBUG(dbgs() << "Name=" << getFixupKindInfo(Kind).Name << "("
515  << (unsigned)Kind << ")\n");
516  LLVM_DEBUG(
517  uint32_t OldData = 0; for (unsigned i = 0; i < NumBytes; i++) OldData |=
518  (InstAddr[i] << (i * 8)) & (0xff << (i * 8));
519  dbgs() << "\tBValue=0x"; dbgs().write_hex(Value) << ": AValue=0x";
520  dbgs().write_hex(FixupValue)
521  << ": Offset=" << Offset << ": Size=" << Data.size() << ": OInst=0x";
522  dbgs().write_hex(OldData) << ": Reloc=0x"; dbgs().write_hex(Reloc););
523 
524  // For each byte of the fragment that the fixup touches, mask in the
525  // bits from the fixup value. The Value has been "split up" into the
526  // appropriate bitfields above.
527  for (unsigned i = 0; i < NumBytes; i++){
528  InstAddr[i] &= uint8_t(~InstMask >> (i * 8)) & 0xff; // Clear reloc bits
529  InstAddr[i] |= uint8_t(Reloc >> (i * 8)) & 0xff; // Apply new reloc
530  }
531 
532  LLVM_DEBUG(uint32_t NewData = 0;
533  for (unsigned i = 0; i < NumBytes; i++) NewData |=
534  (InstAddr[i] << (i * 8)) & (0xff << (i * 8));
535  dbgs() << ": NInst=0x"; dbgs().write_hex(NewData) << "\n";);
536  }
537 
538  bool isInstRelaxable(MCInst const &HMI) const {
539  const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI);
540  bool Relaxable = false;
541  // Branches and loop-setup insns are handled as necessary by relaxation.
544  MCID.isBranch()) ||
546  MCID.isBranch()) ||
548  HMI.getOpcode() != Hexagon::C4_addipc))
549  if (HexagonMCInstrInfo::isExtendable(*MCII, HMI)) {
550  Relaxable = true;
551  MCOperand const &Operand =
554  Relaxable = false;
555  }
556 
557  return Relaxable;
558  }
559 
560  /// MayNeedRelaxation - Check whether the given instruction may need
561  /// relaxation.
562  ///
563  /// \param Inst - The instruction to test.
564  bool mayNeedRelaxation(MCInst const &Inst,
565  const MCSubtargetInfo &STI) const override {
566  return true;
567  }
568 
569  /// fixupNeedsRelaxation - Target specific predicate for whether a given
570  /// fixup requires the associated instruction to be relaxed.
571  bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved,
572  uint64_t Value,
573  const MCRelaxableFragment *DF,
574  const MCAsmLayout &Layout,
575  const bool WasForced) const override {
576  MCInst const &MCB = DF->getInst();
578 
579  *RelaxTarget = nullptr;
580  MCInst &MCI = const_cast<MCInst &>(HexagonMCInstrInfo::instruction(
581  MCB, Fixup.getOffset() / HEXAGON_INSTR_SIZE));
582  bool Relaxable = isInstRelaxable(MCI);
583  if (Relaxable == false)
584  return false;
585  // If we cannot resolve the fixup value, it requires relaxation.
586  if (!Resolved) {
587  switch (Fixup.getTargetKind()) {
589  // GetFixupCount assumes B22 won't relax
591  default:
592  return false;
593  break;
597  case fixup_Hexagon_B7_PCREL: {
599  ++relaxedCnt;
600  *RelaxTarget = &MCI;
601  setExtender(Layout.getAssembler().getContext());
602  return true;
603  } else {
604  return false;
605  }
606  break;
607  }
608  }
609  }
610 
611  MCFixupKind Kind = Fixup.getKind();
612  int64_t sValue = Value;
613  int64_t maxValue;
614 
615  switch ((unsigned)Kind) {
617  maxValue = 1 << 8;
618  break;
620  maxValue = 1 << 10;
621  break;
623  maxValue = 1 << 16;
624  break;
626  maxValue = 1 << 23;
627  break;
628  default:
629  maxValue = INT64_MAX;
630  break;
631  }
632 
633  bool isFarAway = -maxValue > sValue || sValue > maxValue - 1;
634 
635  if (isFarAway) {
637  ++relaxedCnt;
638  *RelaxTarget = &MCI;
639  setExtender(Layout.getAssembler().getContext());
640  return true;
641  }
642  }
643 
644  return false;
645  }
646 
647  /// Simple predicate for targets where !Resolved implies requiring relaxation
648  bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
649  const MCRelaxableFragment *DF,
650  const MCAsmLayout &Layout) const override {
651  llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced");
652  }
653 
654  void relaxInstruction(MCInst &Inst,
655  const MCSubtargetInfo &STI) const override {
657  "Hexagon relaxInstruction only works on bundles");
658 
659  MCInst Res;
660  Res.setOpcode(Hexagon::BUNDLE);
662  // Copy the results into the bundle.
663  bool Update = false;
664  for (auto &I : HexagonMCInstrInfo::bundleInstructions(Inst)) {
665  MCInst &CrntHMI = const_cast<MCInst &>(*I.getInst());
666 
667  // if immediate extender needed, add it in
668  if (*RelaxTarget == &CrntHMI) {
669  Update = true;
671  "No room to insert extender for relaxation");
672 
673  MCInst *HMIx = takeExtender();
675  *MCII, CrntHMI,
678  *RelaxTarget = nullptr;
679  }
680  // now copy over the original instruction(the one we may have extended)
681  Res.addOperand(MCOperand::createInst(I.getInst()));
682  }
683 
684  Inst = std::move(Res);
685  (void)Update;
686  assert(Update && "Didn't find relaxation target");
687  }
688 
689  bool writeNopData(raw_ostream &OS, uint64_t Count,
690  const MCSubtargetInfo *STI) const override {
691  static const uint32_t Nopcode = 0x7f000000, // Hard-coded NOP.
692  ParseIn = 0x00004000, // In packet parse-bits.
693  ParseEnd = 0x0000c000; // End of packet parse-bits.
694 
695  while (Count % HEXAGON_INSTR_SIZE) {
696  LLVM_DEBUG(dbgs() << "Alignment not a multiple of the instruction size:"
697  << Count % HEXAGON_INSTR_SIZE << "/"
698  << HEXAGON_INSTR_SIZE << "\n");
699  --Count;
700  OS << '\0';
701  }
702 
703  while (Count) {
704  Count -= HEXAGON_INSTR_SIZE;
705  // Close the packet whenever a multiple of the maximum packet size remains
706  uint32_t ParseBits = (Count % (MaxPacketSize * HEXAGON_INSTR_SIZE)) ?
707  ParseIn : ParseEnd;
708  support::endian::write<uint32_t>(OS, Nopcode | ParseBits, Endian);
709  }
710  return true;
711  }
712 
713  void finishLayout(MCAssembler const &Asm,
714  MCAsmLayout &Layout) const override {
715  for (auto I : Layout.getSectionOrder()) {
716  auto &Fragments = I->getFragmentList();
717  for (auto &J : Fragments) {
718  switch (J.getKind()) {
719  default:
720  break;
721  case MCFragment::FT_Align: {
722  auto Size = Asm.computeFragmentSize(Layout, J);
723  for (auto K = J.getIterator();
724  K != Fragments.begin() && Size >= HEXAGON_PACKET_SIZE;) {
725  --K;
726  switch (K->getKind()) {
727  default:
728  break;
729  case MCFragment::FT_Align: {
730  // Don't pad before other alignments
731  Size = 0;
732  break;
733  }
735  MCContext &Context = Asm.getContext();
736  auto &RF = cast<MCRelaxableFragment>(*K);
737  auto &Inst = const_cast<MCInst &>(RF.getInst());
738  while (Size > 0 &&
739  HexagonMCInstrInfo::bundleSize(Inst) < MaxPacketSize) {
740  MCInst *Nop = Context.createMCInst();
741  Nop->setOpcode(Hexagon::A2_nop);
743  Size -= 4;
744  if (!HexagonMCChecker(
745  Context, *MCII, *RF.getSubtargetInfo(), Inst,
746  *Context.getRegisterInfo(), false)
747  .check()) {
748  Inst.erase(Inst.end() - 1);
749  Size = 0;
750  }
751  }
752  bool Error = HexagonMCShuffle(Context, true, *MCII,
753  *RF.getSubtargetInfo(), Inst);
754  //assert(!Error);
755  (void)Error;
756  ReplaceInstruction(Asm.getEmitter(), RF, Inst);
757  Layout.invalidateFragmentsFrom(&RF);
758  Size = 0; // Only look back one instruction
759  break;
760  }
761  }
762  }
763  }
764  }
765  }
766  }
767  }
768 }; // class HexagonAsmBackend
769 
770 } // namespace
771 
772 // MCAsmBackend
774  const MCSubtargetInfo &STI,
775  MCRegisterInfo const & /*MRI*/,
776  const MCTargetOptions &Options) {
777  const Triple &TT = STI.getTargetTriple();
778  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
779 
780  StringRef CPUString = Hexagon_MC::selectHexagonCPU(STI.getCPU());
781  return new HexagonAsmBackend(T, TT, OSABI, CPUString);
782 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
i
i
Definition: README.txt:29
HexagonMCTargetDesc.h
llvm::Hexagon::fixup_Hexagon_GOTREL_16_X
@ fixup_Hexagon_GOTREL_16_X
Definition: HexagonFixupKinds.h:90
llvm::Hexagon::fixup_Hexagon_DTPREL_LO16
@ fixup_Hexagon_DTPREL_LO16
Definition: HexagonFixupKinds.h:62
llvm::HexagonMCInstrInfo::mustNotExtend
bool mustNotExtend(MCExpr const &Expr)
Definition: HexagonMCInstrInfo.cpp:886
llvm::Hexagon::fixup_Hexagon_TPREL_HI16
@ fixup_Hexagon_TPREL_HI16
Definition: HexagonFixupKinds.h:85
llvm::Hexagon::fixup_Hexagon_B22_PCREL
@ fixup_Hexagon_B22_PCREL
Definition: HexagonFixupKinds.h:18
llvm::Hexagon::fixup_Hexagon_6_PCREL_X
@ fixup_Hexagon_6_PCREL_X
Definition: HexagonFixupKinds.h:88
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::Hexagon::fixup_Hexagon_9_X
@ fixup_Hexagon_9_X
Definition: HexagonFixupKinds.h:44
llvm::HexagonMCInstrInfo::getDesc
const MCInstrDesc & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:248
llvm::MCRelaxableFragment
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:271
llvm::Hexagon::fixup_Hexagon_TPREL_32
@ fixup_Hexagon_TPREL_32
Definition: HexagonFixupKinds.h:86
llvm::Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL_X
@ fixup_Hexagon_LD_PLT_B22_PCREL_X
Definition: HexagonFixupKinds.h:116
llvm::Hexagon::fixup_Hexagon_23_REG
@ fixup_Hexagon_23_REG
Definition: HexagonFixupKinds.h:112
llvm::MCAsmBackend::getFixupKindInfo
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
Definition: MCAsmBackend.cpp:74
llvm::Hexagon::fixup_Hexagon_B32_PCREL_X
@ fixup_Hexagon_B32_PCREL_X
Definition: HexagonFixupKinds.h:33
llvm::WebAssembly::Nop
static const unsigned Nop
Instruction opcodes emitted via means other than CodeGen.
Definition: WebAssemblyMCTargetDesc.h:136
llvm::Hexagon::fixup_Hexagon_GD_GOT_LO16
@ fixup_Hexagon_GD_GOT_LO16
Definition: HexagonFixupKinds.h:68
llvm::Hexagon::fixup_Hexagon_GD_GOT_32_6_X
@ fixup_Hexagon_GD_GOT_32_6_X
Definition: HexagonFixupKinds.h:98
llvm::HexagonII::TypeCR
@ TypeCR
Definition: HexagonDepITypes.h:23
llvm::MCInstrDesc::isBranch
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:298
llvm::Hexagon::fixup_Hexagon_IE_GOT_11_X
@ fixup_Hexagon_IE_GOT_11_X
Definition: HexagonFixupKinds.h:108
T
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::Hexagon::fixup_Hexagon_DTPREL_32_6_X
@ fixup_Hexagon_DTPREL_32_6_X
Definition: HexagonFixupKinds.h:95
llvm::Hexagon::fixup_Hexagon_GD_GOT_32
@ fixup_Hexagon_GD_GOT_32
Definition: HexagonFixupKinds.h:70
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
HEXAGON_INSTR_SIZE
#define HEXAGON_INSTR_SIZE
Definition: HexagonMCTargetDesc.h:33
llvm::Hexagon::fixup_Hexagon_IE_GOT_HI16
@ fixup_Hexagon_IE_GOT_HI16
Definition: HexagonFixupKinds.h:81
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::FirstTargetFixupKind
@ FirstTargetFixupKind
Definition: MCFixup.h:45
llvm::APInt::getSExtValue
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1472
llvm::Hexagon::fixup_Hexagon_B9_PCREL_X
@ fixup_Hexagon_B9_PCREL_X
Definition: HexagonFixupKinds.h:38
llvm::Hexagon::fixup_Hexagon_GPREL16_0
@ fixup_Hexagon_GPREL16_0
Definition: HexagonFixupKinds.h:26
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
MCAssembler.h
createMCInstrInfo
static MCInstrInfo * createMCInstrInfo()
Definition: WebAssemblyMCTargetDesc.cpp:43
llvm::Hexagon::fixup_Hexagon_LO16
@ fixup_Hexagon_LO16
Definition: HexagonFixupKinds.h:21
llvm::APInt::getSignedMaxValue
static APInt getSignedMaxValue(unsigned numBits)
Gets maximum signed value of APInt for a specific bit width.
Definition: APInt.h:189
llvm::Hexagon::fixup_Hexagon_GLOB_DAT
@ fixup_Hexagon_GLOB_DAT
Definition: HexagonFixupKinds.h:50
llvm::Hexagon::fixup_Hexagon_B13_PCREL_X
@ fixup_Hexagon_B13_PCREL_X
Definition: HexagonFixupKinds.h:37
llvm::Hexagon::fixup_Hexagon_6_X
@ fixup_Hexagon_6_X
Definition: HexagonFixupKinds.h:47
llvm::Hexagon::fixup_Hexagon_LD_GOT_11_X
@ fixup_Hexagon_LD_GOT_11_X
Definition: HexagonFixupKinds.h:103
llvm::Hexagon::fixup_Hexagon_32
@ fixup_Hexagon_32
Definition: HexagonFixupKinds.h:23
MCFixupKindInfo.h
llvm::Hexagon::fixup_Hexagon_HL16
@ fixup_Hexagon_HL16
Definition: HexagonFixupKinds.h:30
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::Hexagon::fixup_Hexagon_GOT_32
@ fixup_Hexagon_GOT_32
Definition: HexagonFixupKinds.h:59
llvm::Hexagon::fixup_Hexagon_GOTREL_32
@ fixup_Hexagon_GOTREL_32
Definition: HexagonFixupKinds.h:56
llvm::Hexagon::fixup_Hexagon_LD_GOT_LO16
@ fixup_Hexagon_LD_GOT_LO16
Definition: HexagonFixupKinds.h:72
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::MCEncodedFragmentWithFixups::getFixups
SmallVectorImpl< MCFixup > & getFixups()
Definition: MCFragment.h:223
llvm::Hexagon::fixup_Hexagon_GOTREL_32_6_X
@ fixup_Hexagon_GOTREL_32_6_X
Definition: HexagonFixupKinds.h:89
llvm::Hexagon::Fixups
Fixups
Definition: HexagonFixupKinds.h:16
llvm::Hexagon::fixup_Hexagon_DTPREL_HI16
@ fixup_Hexagon_DTPREL_HI16
Definition: HexagonFixupKinds.h:63
llvm::Hexagon::fixup_Hexagon_DTPREL_16
@ fixup_Hexagon_DTPREL_16
Definition: HexagonFixupKinds.h:65
llvm::Data
@ Data
Definition: SIMachineScheduler.h:55
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
HexagonBaseInfo.h
new
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj * new
Definition: README.txt:125
HexagonFixupKinds.h
llvm::Hexagon::fixup_Hexagon_16
@ fixup_Hexagon_16
Definition: HexagonFixupKinds.h:24
Context
ManagedStatic< detail::RecordContext > Context
Definition: Record.cpp:96
llvm::MCInst::setOpcode
void setOpcode(unsigned Op)
Definition: MCInst.h:197
llvm::Hexagon::fixup_Hexagon_GPREL16_3
@ fixup_Hexagon_GPREL16_3
Definition: HexagonFixupKinds.h:29
llvm::Hexagon::fixup_Hexagon_GD_GOT_16_X
@ fixup_Hexagon_GD_GOT_16_X
Definition: HexagonFixupKinds.h:99
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::Hexagon::fixup_Hexagon_IE_GOT_32_6_X
@ fixup_Hexagon_IE_GOT_32_6_X
Definition: HexagonFixupKinds.h:106
llvm::Hexagon::fixup_Hexagon_8_X
@ fixup_Hexagon_8_X
Definition: HexagonFixupKinds.h:45
llvm::Hexagon::fixup_Hexagon_TPREL_11_X
@ fixup_Hexagon_TPREL_11_X
Definition: HexagonFixupKinds.h:111
x3
In x86 we generate this spiffy xmm0 xmm0 ret in x86 we generate this which could be xmm1 movss xmm1 xmm0 ret In sse4 we could use insertps to make both better Here s another testcase that could use x3
Definition: README-SSE.txt:547
llvm::Hexagon::fixup_Hexagon_TPREL_16
@ fixup_Hexagon_TPREL_16
Definition: HexagonFixupKinds.h:87
HexagonMCShuffler.h
llvm::FK_Data_4
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
llvm::MCAsmBackend
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:36
llvm::Hexagon::fixup_Hexagon_TPREL_LO16
@ fixup_Hexagon_TPREL_LO16
Definition: HexagonFixupKinds.h:84
llvm::Hexagon::fixup_Hexagon_LD_GOT_16_X
@ fixup_Hexagon_LD_GOT_16_X
Definition: HexagonFixupKinds.h:102
MCAsmBackend.h
llvm::MutableArrayRef< char >
llvm::MCAsmLayout::invalidateFragmentsFrom
void invalidateFragmentsFrom(MCFragment *F)
Invalidate the fragments starting with F because it has been resized.
Definition: MCFragment.cpp:70
bits
demanded bits
Definition: DemandedBits.cpp:63
HexagonMCChecker.h
llvm::Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL
@ fixup_Hexagon_GD_PLT_B22_PCREL
Definition: HexagonFixupKinds.h:66
llvm::Hexagon::fixup_Hexagon_IE_HI16
@ fixup_Hexagon_IE_HI16
Definition: HexagonFixupKinds.h:77
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
HexagonMCInstrInfo.h
llvm::support::little
@ little
Definition: Endian.h:27
llvm::MCAssembler::getContext
MCContext & getContext() const
Definition: MCAssembler.h:292
int
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
Definition: README.txt:536
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition: MCSubtargetInfo.h:107
MCContext.h
llvm::HexagonMCInstrInfo::isBundle
bool isBundle(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:532
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
llvm::Hexagon::fixup_Hexagon_LD_PLT_B32_PCREL_X
@ fixup_Hexagon_LD_PLT_B32_PCREL_X
Definition: HexagonFixupKinds.h:117
llvm::HexagonMCChecker::check
bool check(bool FullCheck=true)
Definition: HexagonMCChecker.cpp:214
llvm::MCRelaxableFragment::setInst
void setInst(const MCInst &Value)
Definition: MCFragment.h:285
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::HexagonMCInstrInfo::bundleInstructions
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:103
llvm::MCRelaxableFragment::getInst
const MCInst & getInst() const
Definition: MCFragment.h:284
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::Hexagon::fixup_Hexagon_7_X
@ fixup_Hexagon_7_X
Definition: HexagonFixupKinds.h:46
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::Hexagon::fixup_Hexagon_DTPREL_11_X
@ fixup_Hexagon_DTPREL_11_X
Definition: HexagonFixupKinds.h:97
INT64_MAX
#define INT64_MAX
Definition: DataTypes.h:71
llvm::MCInst::end
iterator end()
Definition: MCInst.h:221
llvm::Hexagon::fixup_Hexagon_DTPREL_32
@ fixup_Hexagon_DTPREL_32
Definition: HexagonFixupKinds.h:64
llvm::isIntN
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:460
llvm::Hexagon::NumTargetFixupKinds
@ NumTargetFixupKinds
Definition: HexagonFixupKinds.h:120
llvm::HexagonMCInstrInfo::bundleSize
size_t bundleSize(MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:116
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::MCInst::erase
void erase(iterator I)
Definition: MCInst.h:216
DF
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
llvm::MCOperand::createInst
static MCOperand createInst(const MCInst *Val)
Definition: MCInst.h:169
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::SmallString< 256 >
llvm::Hexagon::fixup_Hexagon_GOT_HI16
@ fixup_Hexagon_GOT_HI16
Definition: HexagonFixupKinds.h:58
llvm::Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL_X
@ fixup_Hexagon_GD_PLT_B22_PCREL_X
Definition: HexagonFixupKinds.h:114
llvm::Hexagon::fixup_Hexagon_GPREL16_1
@ fixup_Hexagon_GPREL16_1
Definition: HexagonFixupKinds.h:27
llvm::Hexagon::fixup_Hexagon_B15_PCREL_X
@ fixup_Hexagon_B15_PCREL_X
Definition: HexagonFixupKinds.h:36
llvm::Hexagon::fixup_Hexagon_LD_GOT_HI16
@ fixup_Hexagon_LD_GOT_HI16
Definition: HexagonFixupKinds.h:73
llvm::MCAsmLayout::getSectionOrder
llvm::SmallVectorImpl< MCSection * > & getSectionOrder()
Definition: MCAsmLayout.h:69
getFixupKindNumBytes
static unsigned getFixupKindNumBytes(unsigned Kind)
The number of bytes the fixup may change.
Definition: AArch64AsmBackend.cpp:107
HexagonMCCodeEmitter.h
llvm::Hexagon::fixup_Hexagon_10_X
@ fixup_Hexagon_10_X
Definition: HexagonFixupKinds.h:43
llvm::cl::opt< bool >
llvm::HexagonMCInstrInfo::packetSize
unsigned packetSize(StringRef CPU)
Definition: HexagonMCInstrInfo.cpp:908
llvm::MCAssembler
Definition: MCAssembler.h:60
uint64_t
llvm::HexagonMCShuffle
bool HexagonMCShuffle(MCContext &Context, bool Fatal, MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &MCB)
Definition: HexagonMCShuffler.cpp:104
MCELFObjectWriter.h
llvm::Hexagon::fixup_Hexagon_IE_32_6_X
@ fixup_Hexagon_IE_32_6_X
Definition: HexagonFixupKinds.h:104
llvm::Hexagon::fixup_Hexagon_TPREL_32_6_X
@ fixup_Hexagon_TPREL_32_6_X
Definition: HexagonFixupKinds.h:109
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::Hexagon::fixup_Hexagon_GOT_LO16
@ fixup_Hexagon_GOT_LO16
Definition: HexagonFixupKinds.h:57
llvm::MCFixupKindInfo::FKF_IsPCRel
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
Definition: MCFixupKindInfo.h:19
llvm::Hexagon::fixup_Hexagon_GOTREL_HI16
@ fixup_Hexagon_GOTREL_HI16
Definition: HexagonFixupKinds.h:55
llvm::MCSubtargetInfo::getCPU
StringRef getCPU() const
Definition: MCSubtargetInfo.h:108
I
#define I(x, y, z)
Definition: MD5.cpp:59
adjustFixupValue
static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target, uint64_t Value, MCContext &Ctx, const Triple &TheTriple, bool IsResolved)
Definition: AArch64AsmBackend.cpp:150
llvm::Hexagon::fixup_Hexagon_GOT_32_6_X
@ fixup_Hexagon_GOT_32_6_X
Definition: HexagonFixupKinds.h:92
llvm::HexagonMCInstrInfo::deriveExtender
MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst, MCOperand const &MO)
Definition: HexagonMCInstrInfo.cpp:184
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::Hexagon::fixup_Hexagon_GOTREL_LO16
@ fixup_Hexagon_GOTREL_LO16
Definition: HexagonFixupKinds.h:54
llvm::Hexagon::fixup_Hexagon_B9_PCREL
@ fixup_Hexagon_B9_PCREL
Definition: HexagonFixupKinds.h:32
llvm::MCFixupKindInfo
Target independent information on a fixup kind.
Definition: MCFixupKindInfo.h:15
llvm::Hexagon::fixup_Hexagon_GD_GOT_HI16
@ fixup_Hexagon_GD_GOT_HI16
Definition: HexagonFixupKinds.h:69
llvm::FK_Data_1
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
llvm::Hexagon::fixup_Hexagon_B7_PCREL
@ fixup_Hexagon_B7_PCREL
Definition: HexagonFixupKinds.h:20
llvm::FK_PCRel_4
@ FK_PCRel_4
A four-byte pc relative fixup.
Definition: MCFixup.h:30
llvm::MCTargetOptions
Definition: MCTargetOptions.h:36
llvm::Hexagon::fixup_Hexagon_IE_32
@ fixup_Hexagon_IE_32
Definition: HexagonFixupKinds.h:78
llvm::MCFragment::FT_Align
@ FT_Align
Definition: MCFragment.h:36
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MCELFObjectTargetWriter::getOSABI
uint8_t getOSABI() const
Definition: MCELFObjectWriter.h:101
llvm::Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL
@ fixup_Hexagon_LD_PLT_B22_PCREL
Definition: HexagonFixupKinds.h:67
Fixup
PowerPC TLS Dynamic Call Fixup
Definition: PPCTLSDynamicCall.cpp:233
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
uint32_t
llvm::Hexagon::fixup_Hexagon_IE_LO16
@ fixup_Hexagon_IE_LO16
Definition: HexagonFixupKinds.h:76
llvm::Hexagon::fixup_Hexagon_8
@ fixup_Hexagon_8
Definition: HexagonFixupKinds.h:25
llvm::Hexagon::fixup_Hexagon_32_6_X
@ fixup_Hexagon_32_6_X
Definition: HexagonFixupKinds.h:34
llvm::HexagonII::TypeCJ
@ TypeCJ
Definition: HexagonDepITypes.h:22
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:286
llvm::HexagonMCInstrInfo::getExtendableOp
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:309
llvm::Hexagon::fixup_Hexagon_GPREL16_2
@ fixup_Hexagon_GPREL16_2
Definition: HexagonFixupKinds.h:28
llvm::Hexagon::fixup_Hexagon_LD_GOT_32
@ fixup_Hexagon_LD_GOT_32
Definition: HexagonFixupKinds.h:74
llvm::Hexagon::fixup_Hexagon_DTPMOD_32
@ fixup_Hexagon_DTPMOD_32
Definition: HexagonFixupKinds.h:61
DisableFixup
static cl::opt< bool > DisableFixup("mno-fixup", cl::desc("Disable fixing up resolved relocations for Hexagon"))
llvm::Hexagon::fixup_Hexagon_GD_PLT_B32_PCREL_X
@ fixup_Hexagon_GD_PLT_B32_PCREL_X
Definition: HexagonFixupKinds.h:115
MCAsmLayout.h
llvm::Hexagon::fixup_Hexagon_JMP_SLOT
@ fixup_Hexagon_JMP_SLOT
Definition: HexagonFixupKinds.h:51
MCObjectWriter.h
llvm::Hexagon::fixup_Hexagon_GD_GOT_16
@ fixup_Hexagon_GD_GOT_16
Definition: HexagonFixupKinds.h:71
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
EndianStream.h
llvm::Hexagon::fixup_Hexagon_B22_PCREL_X
@ fixup_Hexagon_B22_PCREL_X
Definition: HexagonFixupKinds.h:35
llvm::HexagonMCChecker
Check for a valid bundle.
Definition: HexagonMCChecker.h:34
llvm::HexagonMCInstrInfo::getType
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Return the Hexagon ISA class for the insn.
Definition: HexagonMCInstrInfo.cpp:416
llvm::MCAsmLayout
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
llvm::MCCodeEmitter
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:157
llvm::Hexagon::fixup_Hexagon_B7_PCREL_X
@ fixup_Hexagon_B7_PCREL_X
Definition: HexagonFixupKinds.h:39
llvm::MCEncodedFragment::getSubtargetInfo
const MCSubtargetInfo * getSubtargetInfo() const
Retrieve the MCSubTargetInfo in effect when the instruction was encoded.
Definition: MCFragment.h:173
llvm::Hexagon::fixup_Hexagon_32_PCREL
@ fixup_Hexagon_32_PCREL
Definition: HexagonFixupKinds.h:48
llvm::Hexagon::fixup_Hexagon_IE_16
@ fixup_Hexagon_IE_16
Definition: HexagonFixupKinds.h:79
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition: MCInst.h:114
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::Hexagon::fixup_Hexagon_GOT_16_X
@ fixup_Hexagon_GOT_16_X
Definition: HexagonFixupKinds.h:93
llvm::Hexagon::fixup_Hexagon_IE_16_X
@ fixup_Hexagon_IE_16_X
Definition: HexagonFixupKinds.h:105
llvm::HexagonMCInstrInfo::getExtendableOperand
const MCOperand & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:316
llvm::Hexagon::fixup_Hexagon_IE_GOT_32
@ fixup_Hexagon_IE_GOT_32
Definition: HexagonFixupKinds.h:82
llvm::HexagonMCInstrInfo::instruction
const MCInst & instruction(MCInst const &MCB, size_t Index)
Definition: HexagonMCInstrInfo.cpp:519
llvm::APInt::getSignedMinValue
static APInt getSignedMinValue(unsigned numBits)
Gets minimum signed value of APInt for a specific bit width.
Definition: APInt.h:199
llvm::Hexagon::fixup_Hexagon_PLT_B22_PCREL
@ fixup_Hexagon_PLT_B22_PCREL
Definition: HexagonFixupKinds.h:53
llvm::MCFragment::FT_Relaxable
@ FT_Relaxable
Definition: MCFragment.h:41
llvm::Hexagon::fixup_Hexagon_LD_GOT_16
@ fixup_Hexagon_LD_GOT_16
Definition: HexagonFixupKinds.h:75
llvm::HexagonII::TypeNCJ
@ TypeNCJ
Definition: HexagonDepITypes.h:57
llvm::Hexagon::fixup_Hexagon_LD_GOT_32_6_X
@ fixup_Hexagon_LD_GOT_32_6_X
Definition: HexagonFixupKinds.h:101
llvm::Hexagon::fixup_Hexagon_HI16
@ fixup_Hexagon_HI16
Definition: HexagonFixupKinds.h:22
llvm::MCFixupKind
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
llvm::Hexagon_MC::selectHexagonCPU
StringRef selectHexagonCPU(StringRef CPU)
Definition: HexagonMCTargetDesc.cpp:129
llvm::Hexagon::fixup_Hexagon_GOT_11_X
@ fixup_Hexagon_GOT_11_X
Definition: HexagonFixupKinds.h:94
llvm::Hexagon::fixup_Hexagon_GOT_16
@ fixup_Hexagon_GOT_16
Definition: HexagonFixupKinds.h:60
llvm::Hexagon::fixup_Hexagon_GD_GOT_11_X
@ fixup_Hexagon_GD_GOT_11_X
Definition: HexagonFixupKinds.h:100
llvm::Hexagon::fixup_Hexagon_11_X
@ fixup_Hexagon_11_X
Definition: HexagonFixupKinds.h:42
llvm::Hexagon::fixup_Hexagon_B15_PCREL
@ fixup_Hexagon_B15_PCREL
Definition: HexagonFixupKinds.h:19
llvm::Hexagon::fixup_Hexagon_IE_GOT_LO16
@ fixup_Hexagon_IE_GOT_LO16
Definition: HexagonFixupKinds.h:80
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
support
Reimplement select in terms of SEL *We would really like to support but we need to prove that the add doesn t need to overflow between the two bit chunks *Implement pre post increment support(e.g. PR935) *Implement smarter const ant generation for binops with large immediates. A few ARMv6T2 ops should be pattern matched
Definition: README.txt:10
llvm::Hexagon::fixup_Hexagon_TPREL_16_X
@ fixup_Hexagon_TPREL_16_X
Definition: HexagonFixupKinds.h:110
llvm::raw_svector_ostream
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:658
llvm::Hexagon::fixup_Hexagon_12_X
@ fixup_Hexagon_12_X
Definition: HexagonFixupKinds.h:41
llvm::Hexagon::fixup_Hexagon_B13_PCREL
@ fixup_Hexagon_B13_PCREL
Definition: HexagonFixupKinds.h:31
llvm::Hexagon::fixup_Hexagon_27_REG
@ fixup_Hexagon_27_REG
Definition: HexagonFixupKinds.h:113
llvm::Hexagon::fixup_Hexagon_IE_GOT_16_X
@ fixup_Hexagon_IE_GOT_16_X
Definition: HexagonFixupKinds.h:107
llvm::Hexagon::fixup_Hexagon_RELATIVE
@ fixup_Hexagon_RELATIVE
Definition: HexagonFixupKinds.h:52
llvm::HexagonII::TypeJ
@ TypeJ
Definition: HexagonDepITypes.h:53
llvm::Hexagon::fixup_Hexagon_GOTREL_11_X
@ fixup_Hexagon_GOTREL_11_X
Definition: HexagonFixupKinds.h:91
llvm::HexStyle::Asm
@ Asm
0ffh
Definition: MCInstPrinter.h:34
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::MCAsmLayout::getAssembler
MCAssembler & getAssembler() const
Get the assembler object this is a layout for.
Definition: MCAsmLayout.h:50
llvm::MCValue
This represents an "assembler immediate".
Definition: MCValue.h:37
llvm::cl::desc
Definition: CommandLine.h:412
llvm::Hexagon::fixup_Hexagon_16_X
@ fixup_Hexagon_16_X
Definition: HexagonFixupKinds.h:40
llvm::FK_Data_2
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
HEXAGON_PACKET_SIZE
#define HEXAGON_PACKET_SIZE
Definition: HexagonMCTargetDesc.h:36
llvm::Hexagon::fixup_Hexagon_IE_GOT_16
@ fixup_Hexagon_IE_GOT_16
Definition: HexagonFixupKinds.h:83
TargetRegistry.h
llvm::createHexagonAsmBackend
MCAsmBackend * createHexagonAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: HexagonAsmBackend.cpp:773
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::MCFixup
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
Debug.h
llvm::Hexagon::fixup_Hexagon_COPY
@ fixup_Hexagon_COPY
Definition: HexagonFixupKinds.h:49
llvm::Hexagon::fixup_Hexagon_DTPREL_16_X
@ fixup_Hexagon_DTPREL_16_X
Definition: HexagonFixupKinds.h:96
llvm::MCEncodedFragmentWithContents::getContents
SmallVectorImpl< char > & getContents()
Definition: MCFragment.h:197
llvm::HexagonMCInstrInfo::isExtendable
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
Definition: HexagonMCInstrInfo.cpp:613
llvm::raw_ostream::write_hex
raw_ostream & write_hex(unsigned long long N)
Output N in hexadecimal, without any prefix or padding.
Definition: raw_ostream.cpp:140
llvm::createHexagonELFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createHexagonELFObjectWriter(uint8_t OSABI, StringRef CPU)
Definition: HexagonELFObjectWriter.cpp:301