LLVM  9.0.0svn
Public Member Functions | Protected Member Functions | List of all members
llvm::MCSubtargetInfo Class Reference

Generic base class for all target subtargets. More...

#include "llvm/MC/MCSubtargetInfo.h"

Inheritance diagram for llvm::MCSubtargetInfo:
Inheritance graph
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Public Member Functions

 MCSubtargetInfo (const MCSubtargetInfo &)=default
 
 MCSubtargetInfo (const Triple &TT, StringRef CPU, StringRef FS, ArrayRef< SubtargetFeatureKV > PF, ArrayRef< SubtargetSubTypeKV > PD, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP)
 
 MCSubtargetInfo ()=delete
 
MCSubtargetInfooperator= (const MCSubtargetInfo &)=delete
 
MCSubtargetInfooperator= (MCSubtargetInfo &&)=delete
 
virtual ~MCSubtargetInfo ()=default
 
const TriplegetTargetTriple () const
 
StringRef getCPU () const
 
const FeatureBitsetgetFeatureBits () const
 
void setFeatureBits (const FeatureBitset &FeatureBits_)
 
bool hasFeature (unsigned Feature) const
 
void setDefaultFeatures (StringRef CPU, StringRef FS)
 Set the features to the default for the given CPU with an appended feature string. More...
 
FeatureBitset ToggleFeature (uint64_t FB)
 Toggle a feature and return the re-computed feature bits. More...
 
FeatureBitset ToggleFeature (const FeatureBitset &FB)
 Toggle a feature and return the re-computed feature bits. More...
 
FeatureBitset ToggleFeature (StringRef FS)
 Toggle a set of features and return the re-computed feature bits. More...
 
FeatureBitset ApplyFeatureFlag (StringRef FS)
 Apply a feature flag and return the re-computed feature bits, including all feature bits implied by the flag. More...
 
bool checkFeatures (StringRef FS) const
 Check whether the subtarget features are enabled/disabled as per the provided string, ignoring all other features. More...
 
const MCSchedModelgetSchedModelForCPU (StringRef CPU) const
 Get the machine model of a CPU. More...
 
const MCSchedModelgetSchedModel () const
 Get the machine model for this subtarget's CPU. More...
 
const MCWriteProcResEntrygetWriteProcResBegin (const MCSchedClassDesc *SC) const
 Return an iterator at the first process resource consumed by the given scheduling class. More...
 
const MCWriteProcResEntrygetWriteProcResEnd (const MCSchedClassDesc *SC) const
 
const MCWriteLatencyEntrygetWriteLatencyEntry (const MCSchedClassDesc *SC, unsigned DefIdx) const
 
int getReadAdvanceCycles (const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const
 
ArrayRef< MCReadAdvanceEntrygetReadAdvanceEntries (const MCSchedClassDesc &SC) const
 Return the set of ReadAdvance entries declared by the scheduling class descriptor in input. More...
 
InstrItineraryData getInstrItineraryForCPU (StringRef CPU) const
 Get scheduling itinerary of a CPU. More...
 
void initInstrItins (InstrItineraryData &InstrItins) const
 Initialize an InstrItineraryData instance. More...
 
virtual unsigned resolveVariantSchedClass (unsigned SchedClass, const MCInst *MI, unsigned CPUID) const
 Resolve a variant scheduling class for the given MCInst and CPU. More...
 
bool isCPUStringValid (StringRef CPU) const
 Check whether the CPU string is valid. More...
 

Protected Member Functions

void InitMCProcessorInfo (StringRef CPU, StringRef FS)
 Initialize the scheduling model and feature bits. More...
 

Detailed Description

Generic base class for all target subtargets.

Definition at line 74 of file MCSubtargetInfo.h.

Constructor & Destructor Documentation

◆ MCSubtargetInfo() [1/3]

llvm::MCSubtargetInfo::MCSubtargetInfo ( const MCSubtargetInfo )
default

◆ MCSubtargetInfo() [2/3]

MCSubtargetInfo::MCSubtargetInfo ( const Triple TT,
StringRef  CPU,
StringRef  FS,
ArrayRef< SubtargetFeatureKV PF,
ArrayRef< SubtargetSubTypeKV PD,
const MCWriteProcResEntry WPR,
const MCWriteLatencyEntry WL,
const MCReadAdvanceEntry RA,
const InstrStage IS,
const unsigned OC,
const unsigned FP 
)

Definition at line 176 of file MCSubtargetInfo.cpp.

References InitMCProcessorInfo().

◆ MCSubtargetInfo() [3/3]

llvm::MCSubtargetInfo::MCSubtargetInfo ( )
delete

◆ ~MCSubtargetInfo()

virtual llvm::MCSubtargetInfo::~MCSubtargetInfo ( )
virtualdefault

Member Function Documentation

◆ ApplyFeatureFlag()

FeatureBitset MCSubtargetInfo::ApplyFeatureFlag ( StringRef  FS)

Apply a feature flag and return the re-computed feature bits, including all feature bits implied by the flag.

Definition at line 223 of file MCSubtargetInfo.cpp.

Referenced by checkFeatures(), and llvm::IsCPSRDead< MCInst >().

◆ checkFeatures()

bool MCSubtargetInfo::checkFeatures ( StringRef  FS) const

Check whether the subtarget features are enabled/disabled as per the provided string, ignoring all other features.

Definition at line 228 of file MCSubtargetInfo.cpp.

References ApplyFeatureFlag(), F(), llvm::SubtargetFeatures::getFeatures(), and T.

◆ getCPU()

StringRef llvm::MCSubtargetInfo::getCPU ( ) const
inline

◆ getFeatureBits()

const FeatureBitset& llvm::MCSubtargetInfo::getFeatureBits ( ) const
inline

Definition at line 107 of file MCSubtargetInfo.h.

Referenced by llvm::ARMAsmBackend::adjustFixupValue(), llvm::AMDGPUDisassembler::AMDGPUDisassembler(), llvm::AArch64TTIImpl::areInlineCompatible(), llvm::ARMTTIImpl::areInlineCompatible(), llvm::GCNTTIImpl::areInlineCompatible(), llvm::X86TTIImpl::areInlineCompatible(), llvm::AVRELFStreamer::AVRELFStreamer(), llvm::HexagonMCInstrInfo::canonicalizePacket(), checkFeature(), clearFeature(), llvm::AMDGPUDisassembler::convertMIMGInst(), llvm::AMDGPUDisassembler::convertSDWAInst(), llvm::Hexagon_MC::createHexagonMCSubtargetInfo(), llvm::createR600MCCodeEmitter(), llvm::createRISCVMCCodeEmitter(), DecodeHINTInstruction(), llvm::AMDGPUDisassembler::decodeSDWASrc(), llvm::AMDGPUDisassembler::decodeSDWAVopcDst(), DecodeSETPANInstruction(), DecodeSystemPStateInstruction(), llvm::MipsTargetStreamer::emitNop(), llvm::HexagonMCCodeEmitter::encodeInstruction(), llvm::PPCMCCodeEmitter::encodeInstruction(), ExpandCryptoAEK(), llvm::MipsTargetELFStreamer::finish(), llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs(), getARMLoadDeprecationInfo(), getARMStoreDeprecationInfo(), llvm::AMDGPU::getDefaultAmdhsaKernelDescriptor(), llvm::MCInstrDesc::getDeprecatedInfo(), llvm::AMDGPUDisassembler::getInstruction(), getITDeprecationInfo(), getLit16Encoding(), getLit32Encoding(), getLit64Encoding(), llvm::AMDGPU::IsaInfo::getLocalMemorySize(), llvm::AMDGPUMCAsmInfo::getMaxInstLength(), llvm::AMDGPU::IsaInfo::getMaxNumSGPRs(), getMCRDeprecationInfo(), llvm::AMDGPU::IsaInfo::getMinNumSGPRs(), llvm::AMDGPU::IsaInfo::getNumExtraSGPRs(), llvm::ARMAsmBackend::getRelaxedOpcode(), getRelaxedOpcode(), llvm::AMDGPU::IsaInfo::getWavefrontSize(), llvm::AMDGPU::IsaInfo::hasCodeObjectV3(), llvm::AMDGPU::hasMIMG_R128(), llvm::ARMAsmBackend::hasNOP(), llvm::AMDGPU::hasPackedD16(), llvm::AMDGPU::hasSRAMECC(), llvm::AMDGPU::hasXNACK(), incrementLoc(), llvm::AMDGPU::initDefaultAMDKernelCodeT(), llvm::AMDGPU::isCI(), llvm::IsCPSRDead< MCInst >(), llvm::AMDGPU::isGCN3Encoding(), llvm::AMDGPUDisassembler::isGFX10(), llvm::AMDGPU::isGFX10(), llvm::AMDGPUDisassembler::isGFX9(), llvm::AMDGPU::isGFX9(), llvm::AMDGPU::isSI(), isThumb(), llvm::SparcInstPrinter::isV9(), llvm::AMDGPUDisassembler::isVI(), llvm::AMDGPU::isVI(), LowerLargeShift(), llvm::MipsTargetELFStreamer::MipsTargetELFStreamer(), llvm::RISCVInstPrinter::printCSRSystemRegister(), llvm::X86ATTInstPrinter::printInst(), llvm::X86IntelInstPrinter::printInst(), llvm::PPCInstPrinter::printInst(), llvm::ARMInstPrinter::printMemBOption(), llvm::AArch64InstPrinter::printMRSSystemRegister(), llvm::ARMInstPrinter::printMSRMaskOperand(), llvm::AArch64InstPrinter::printMSRSystemRegister(), llvm::AMDGPUInstPrinter::printRegOperand(), llvm::AArch64InstPrinter::printSysAlias(), llvm::AArch64InstPrinter::printSystemPStateField(), llvm::RISCVAsmBackend::RISCVAsmBackend(), llvm::RISCVTargetELFStreamer::RISCVTargetELFStreamer(), llvm::RISCVAsmBackend::shouldForceRelocation(), llvm::RISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign(), llvm::RISCVAsmBackend::shouldInsertFixupForCodeAlign(), SwapBits(), llvm::RISCVAsmBackend::willForceRelocations(), and llvm::RISCVAsmBackend::writeNopData().

◆ getInstrItineraryForCPU()

InstrItineraryData MCSubtargetInfo::getInstrItineraryForCPU ( StringRef  CPU) const

Get scheduling itinerary of a CPU.

Definition at line 259 of file MCSubtargetInfo.cpp.

References getSchedModelForCPU().

Referenced by getItineraryLatency().

◆ getReadAdvanceCycles()

int llvm::MCSubtargetInfo::getReadAdvanceCycles ( const MCSchedClassDesc SC,
unsigned  UseIdx,
unsigned  WriteResID 
) const
inline

◆ getReadAdvanceEntries()

ArrayRef<MCReadAdvanceEntry> llvm::MCSubtargetInfo::getReadAdvanceEntries ( const MCSchedClassDesc SC) const
inline

Return the set of ReadAdvance entries declared by the scheduling class descriptor in input.

Definition at line 195 of file MCSubtargetInfo.h.

References llvm::MCSchedClassDesc::NumReadAdvanceEntries, and llvm::MCSchedClassDesc::ReadAdvanceIdx.

◆ getSchedModel()

const MCSchedModel& llvm::MCSubtargetInfo::getSchedModel ( ) const
inline

◆ getSchedModelForCPU()

const MCSchedModel & MCSubtargetInfo::getSchedModelForCPU ( StringRef  CPU) const

◆ getTargetTriple()

const Triple& llvm::MCSubtargetInfo::getTargetTriple ( ) const
inline

◆ getWriteLatencyEntry()

const MCWriteLatencyEntry* llvm::MCSubtargetInfo::getWriteLatencyEntry ( const MCSchedClassDesc SC,
unsigned  DefIdx 
) const
inline

◆ getWriteProcResBegin()

const MCWriteProcResEntry* llvm::MCSubtargetInfo::getWriteProcResBegin ( const MCSchedClassDesc SC) const
inline

Return an iterator at the first process resource consumed by the given scheduling class.

Definition at line 156 of file MCSubtargetInfo.h.

References llvm::MCSchedClassDesc::WriteProcResIdx.

Referenced by llvm::TargetSchedModel::computeOutputLatency(), llvm::MCSchedModel::getReciprocalThroughput(), llvm::TargetSchedModel::getWriteProcResBegin(), and llvm::mca::initializeUsedResources().

◆ getWriteProcResEnd()

const MCWriteProcResEntry* llvm::MCSubtargetInfo::getWriteProcResEnd ( const MCSchedClassDesc SC) const
inline

◆ hasFeature()

bool llvm::MCSubtargetInfo::hasFeature ( unsigned  Feature) const
inline

◆ initInstrItins()

void MCSubtargetInfo::initInstrItins ( InstrItineraryData InstrItins) const

Initialize an InstrItineraryData instance.

Definition at line 264 of file MCSubtargetInfo.cpp.

References getSchedModel().

Referenced by llvm::TargetSchedModel::init().

◆ InitMCProcessorInfo()

void MCSubtargetInfo::InitMCProcessorInfo ( StringRef  CPU,
StringRef  FS 
)
protected

Initialize the scheduling model and feature bits.

FIXME: Find a way to stick this in the constructor, since it should only be called during initialization.

Definition at line 164 of file MCSubtargetInfo.cpp.

References llvm::StringRef::empty(), llvm::MCSchedModel::GetDefaultSchedModel(), getFeatures(), and getSchedModelForCPU().

Referenced by MCSubtargetInfo().

◆ isCPUStringValid()

bool llvm::MCSubtargetInfo::isCPUStringValid ( StringRef  CPU) const
inline

Check whether the CPU string is valid.

Definition at line 216 of file MCSubtargetInfo.h.

References llvm::ArrayRef< T >::begin(), llvm::ArrayRef< T >::end(), and llvm::lower_bound().

◆ operator=() [1/2]

MCSubtargetInfo& llvm::MCSubtargetInfo::operator= ( const MCSubtargetInfo )
delete

◆ operator=() [2/2]

MCSubtargetInfo& llvm::MCSubtargetInfo::operator= ( MCSubtargetInfo &&  )
delete

◆ resolveVariantSchedClass()

virtual unsigned llvm::MCSubtargetInfo::resolveVariantSchedClass ( unsigned  SchedClass,
const MCInst MI,
unsigned  CPUID 
) const
inlinevirtual

Resolve a variant scheduling class for the given MCInst and CPU.

Definition at line 210 of file MCSubtargetInfo.h.

Referenced by llvm::MCSchedModel::computeInstrLatency(), llvm::MCSchedModel::getReciprocalThroughput(), and llvm::mca::verifyOperands().

◆ setDefaultFeatures()

void MCSubtargetInfo::setDefaultFeatures ( StringRef  CPU,
StringRef  FS 
)

Set the features to the default for the given CPU with an appended feature string.

Definition at line 172 of file MCSubtargetInfo.cpp.

References getFeatures().

Referenced by ExpandCryptoAEK(), incrementLoc(), and llvm::IsCPSRDead< MCInst >().

◆ setFeatureBits()

void llvm::MCSubtargetInfo::setFeatureBits ( const FeatureBitset FeatureBits_)
inline

◆ ToggleFeature() [1/3]

FeatureBitset MCSubtargetInfo::ToggleFeature ( uint64_t  FB)

Toggle a feature and return the re-computed feature bits.

This version does not change the implied bits.

Definition at line 188 of file MCSubtargetInfo.cpp.

Referenced by clearFeature(), ExpandCryptoAEK(), and incrementLoc().

◆ ToggleFeature() [2/3]

FeatureBitset MCSubtargetInfo::ToggleFeature ( const FeatureBitset FB)

Toggle a feature and return the re-computed feature bits.

This version does not change the implied bits.

Definition at line 193 of file MCSubtargetInfo.cpp.

◆ ToggleFeature() [3/3]

FeatureBitset MCSubtargetInfo::ToggleFeature ( StringRef  FS)

Toggle a set of features and return the re-computed feature bits.

This version will also change all implied bits.

Definition at line 198 of file MCSubtargetInfo.cpp.

References ClearImpliedBits(), llvm::errs(), Find(), llvm::FeatureBitArray::getAsBitset(), llvm::SubtargetFeatureKV::Implies, SetImpliedBits(), llvm::SubtargetFeatures::StripFlag(), and llvm::SubtargetFeatureKV::Value.


The documentation for this class was generated from the following files: