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31 auto checkFixupInRange = [&](int64_t Min, int64_t Max) ->
bool {
32 int64_t SVal = int64_t(
Value);
33 if (SVal < Min || SVal > Max) {
35 " not between " +
Twine(Min) +
36 " and " +
Twine(Max) +
")");
42 auto handlePCRelFixupValue = [&](
unsigned W) ->
uint64_t {
47 return (int64_t)
Value / 2;
50 switch (
unsigned(
Kind)) {
52 return handlePCRelFixupValue(12);
54 return handlePCRelFixupValue(16);
56 return handlePCRelFixupValue(24);
58 return handlePCRelFixupValue(32);
61 if (!checkFixupInRange(0,
maxUIntN(12)))
71 return (DLo << 8) | DHi;
85 SystemZMCAsmBackend(uint8_t osABI)
89 unsigned getNumFixupKinds()
const override {
107 std::unique_ptr<MCObjectTargetWriter>
108 createObjectTargetWriter()
const override {
116 #define ELF_RELOC(X, Y) .Case(#X, Y)
117 #include "llvm/BinaryFormat/ELFRelocs/SystemZ.def"
119 .
Case(
"BFD_RELOC_NONE", ELF::R_390_NONE)
120 .
Case(
"BFD_RELOC_8", ELF::R_390_8)
121 .
Case(
"BFD_RELOC_16", ELF::R_390_16)
122 .
Case(
"BFD_RELOC_32", ELF::R_390_32)
123 .
Case(
"BFD_RELOC_64", ELF::R_390_64)
137 {
"FK_390_TLS_CALL", 0, 0, 0 },
138 {
"FK_390_12", 4, 12, 0 },
139 {
"FK_390_20", 4, 20, 0 }
155 bool SystemZMCAsmBackend::shouldForceRelocation(
const MCAssembler &,
171 unsigned BitSize = getFixupKindInfo(
Kind).TargetSize;
172 unsigned Size = (BitSize + 7) / 8;
174 assert(Offset + Size <=
Data.size() &&
"Invalid fixup offset!");
180 unsigned ShiftValue = (
Size * 8) - 8;
181 for (
unsigned I = 0;
I !=
Size; ++
I) {
200 return new SystemZMCAsmBackend(OSABI);
StringSwitch & Case(StringLiteral S, T Value)
This is an optimization pass for GlobalISel generic memory operations.
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
Context object for machine code objects.
LLVM_NODISCARD R Default(T Value)
Target - Wrapper for Target specific information.
The instances of the Type class are immutable: once they are created, they are never changed.
int64_t maxIntN(int64_t N)
Gets the maximum value for a N-bit signed integer.
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
Generic interface to target specific assembler backends.
const Triple & getTargetTriple() const
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
This class implements an extremely fast bulk output stream that can only output to a stream.
int64_t minIntN(int64_t N)
Gets the minimum value for a N-bit signed integer.
OSType getOS() const
Get the parsed operating system type of this triple.
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Target independent information on a fixup kind.
void reportError(SMLoc L, const Twine &Msg)
std::unique_ptr< MCObjectTargetWriter > createSystemZObjectWriter(uint8_t OSABI)
PowerPC TLS Dynamic Call Fixup
StringRef - Represent a constant reference to a string, i.e.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Error applyFixup(LinkGraph &G, Block &B, const Edge &E, const Symbol *GOTSymbol)
Apply fixup expression for edge to block content.
unsigned const MachineRegisterInfo * MRI
static uint64_t extractBitsForFixup(MCFixupKind Kind, uint64_t Value, const MCFixup &Fixup, MCContext &Ctx)
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Encapsulates the layout of an assembly file at a particular point in time.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
MCAsmBackend * createSystemZMCAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Reimplement select in terms of SEL *We would really like to support but we need to prove that the add doesn t need to overflow between the two bit chunks *Implement pre post increment support(e.g. PR935) *Implement smarter const ant generation for binops with large immediates. A few ARMv6T2 ops should be pattern matched
A switch()-like statement whose cases are string literals.
This represents an "assembler immediate".
uint64_t maxUIntN(uint64_t N)
Gets the maximum value for a N-bit unsigned integer.
Generic base class for all target subtargets.
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
LLVM Value Representation.