- g -

• G : MD5.cpp
• G_00B028_MEM_ORDERED : SIDefines.h
• G_00B128_MEM_ORDERED : SIDefines.h
• G_00B228_MEM_ORDERED : SIDefines.h
• G_00B228_WGP_MODE : SIDefines.h
• G_00B428_MEM_ORDERED : SIDefines.h
• G_00B428_WGP_MODE : SIDefines.h
• G_00B848_DEBUG_MODE : SIDefines.h
• G_00B848_DX10_CLAMP : SIDefines.h
• G_00B848_FLOAT_MODE : SIDefines.h
• G_00B848_FWD_PROGRESS : SIDefines.h
• G_00B848_IEEE_MODE : SIDefines.h
• G_00B848_MEM_ORDERED : SIDefines.h
• G_00B848_PRIORITY : SIDefines.h
• G_00B848_PRIV : SIDefines.h
• G_00B848_RR_WG_MODE : SIDefines.h
• G_00B848_SGPRS : SIDefines.h
• G_00B848_VGPRS : SIDefines.h
• G_00B848_WGP_MODE : SIDefines.h
• G_00B84C_EXCP_EN : SIDefines.h
• G_00B84C_EXCP_EN_MSB : SIDefines.h
• G_00B84C_LDS_SIZE : SIDefines.h
• G_00B84C_SCRATCH_EN : SIDefines.h
• G_00B84C_TG_SIZE_EN : SIDefines.h
• G_00B84C_TGID_X_EN : SIDefines.h
• G_00B84C_TGID_Y_EN : SIDefines.h
• G_00B84C_TGID_Z_EN : SIDefines.h
• G_00B84C_TIDIG_COMP_CNT : SIDefines.h
• G_00B84C_TRAP_HANDLER : SIDefines.h
• G_00B84C_USER_SGPR : SIDefines.h
• GEN_CHECK_COMPRESS_INSTR : RISCVInstrInfo.cpp
• GEN_COMPRESS_INSTR : CSKYAsmParser.cpp, CSKYAsmPrinter.cpp, RISCVBaseInfo.cpp
• GEN_DIRECTIVES_IMPL : ACC.cpp, OMP.cpp
• GEN_HAS_MEMBER : AMDKernelCodeTUtils.cpp
• GEN_UNCOMPRESS_INSTR : RISCVBaseInfo.cpp
• GENBOOLCOMMENT : PPCAsmPrinter.cpp
• GENERATE_RENAMED_GFX9_CASES : SIInstrInfo.cpp
• GENERIC_FIXUP_FUNC : X86Disassembler.cpp
• GENVALUECOMMENT : PPCAsmPrinter.cpp
• GET : MD5.cpp
• GET_AccessQualifier_DECL : SPIRVBaseInfo.h
• GET_AddressingModel_DECL : SPIRVBaseInfo.h
• GET_AMDGPUImageDMaskIntrinsicTable_IMPL : AMDGPUInstCombineIntrinsic.cpp
• GET_ASITagsList_DECL : SparcMCTargetDesc.h
• GET_ASITagsList_IMPL : SparcMCTargetDesc.cpp
• GET_ASSEMBLER_HEADER : MSP430AsmParser.cpp, LanaiAsmParser.cpp, PPCAsmParser.cpp, RISCVAsmParser.cpp, SparcAsmParser.cpp, SystemZAsmParser.cpp, VEAsmParser.cpp, WebAssemblyAsmParser.cpp, X86AsmParser.cpp, XtensaAsmParser.cpp, MipsAsmParser.cpp, M68kAsmParser.cpp, LoongArchAsmParser.cpp, HexagonAsmParser.cpp, CSKYAsmParser.cpp, BPFAsmParser.cpp, AVRAsmParser.cpp, ARMAsmParser.cpp, AMDGPUAsmParser.cpp, AArch64AsmParser.cpp
• GET_AT_DECL : AArch64BaseInfo.h
• GET_AT_IMPL : AArch64BaseInfo.cpp
• GET_AtomicFloatingBuiltins_DECL : SPIRVBuiltins.cpp
• GET_AtomicFloatingBuiltins_IMPL : SPIRVBuiltins.cpp
• GET_ATTR_COMPAT_FUNC : Attributes.cpp
• GET_ATTR_ENUM : Attributes.h
• GET_ATTR_NAMES : LLToken.h, LLLexer.cpp, LLParser.cpp, Attributes.cpp, Verifier.cpp
• GET_ATTR_PROP_TABLE : Attributes.cpp
• GET_BANKEDREG_DECL : ARMBaseInfo.h
• GET_BANKEDREG_IMPL : ARMBaseInfo.cpp
• GET_BTI_DECL : AArch64BaseInfo.h
• GET_BTI_IMPL : AArch64BaseInfo.cpp
• GET_BuiltIn_DECL : SPIRVBaseInfo.h
• GET_BuiltinGroup_DECL : SPIRVBuiltins.cpp, SPIRVEmitIntrinsics.cpp
• GET_BuiltinTypes_DECL : SPIRVBuiltins.cpp
• GET_BuiltinTypes_IMPL : SPIRVBuiltins.cpp
• GET_Capability_DECL : SPIRVBaseInfo.h
• GET_CapabilityEntries_DECL : SPIRVBaseInfo.cpp
• GET_CapabilityEntries_IMPL : SPIRVBaseInfo.cpp
• GET_CC_REGISTER_LISTS : AArch64RegisterInfo.cpp
• GET_CLMemoryFenceFlags_DECL : SPIRVBuiltins.cpp
• GET_CLMemoryScope_DECL : SPIRVBuiltins.cpp
• GET_CLSamplerAddressingMode_DECL : SPIRVBuiltins.cpp
• GET_ConvertBuiltins_DECL : SPIRVBuiltins.cpp
• GET_ConvertBuiltins_IMPL : SPIRVBuiltins.cpp
• GET_CooperativeMatrixLayout_DECL : SPIRVBaseInfo.h
• GET_CooperativeMatrixOperands_DECL : SPIRVBaseInfo.h
• GET_CP_ASYNC_BULK_TENSOR_OPCODE_G2S : NVPTXISelDAGToDAG.cpp
• GET_CP_ASYNC_BULK_TENSOR_OPCODE_PREFETCH : NVPTXISelDAGToDAG.cpp
• GET_CP_ASYNC_BULK_TENSOR_OPCODE_S2G : NVPTXISelDAGToDAG.cpp
• GET_D16ImageDimIntrinsics_IMPL : SIInstrInfo.cpp
• GET_DAGISEL_BODY : HexagonISelDAGToDAG.cpp
• GET_DAGISEL_DECL : HexagonISelDAGToDAG.h
• GET_DB_DECL : AArch64BaseInfo.h
• GET_DB_IMPL : AArch64BaseInfo.cpp
• GET_DBNXS_DECL : AArch64BaseInfo.h
• GET_DBNXS_IMPL : AArch64BaseInfo.cpp
• GET_DC_DECL : AArch64BaseInfo.h
• GET_DC_IMPL : AArch64BaseInfo.cpp
• GET_Decoration_DECL : SPIRVBaseInfo.h
• GET_DemangledBuiltins_DECL : SPIRVBuiltins.cpp
• GET_DemangledBuiltins_IMPL : SPIRVBuiltins.cpp
• GET_Dim_DECL : SPIRVBaseInfo.h
• GET_EGPR_IF_ENABLED : X86DomainReassignment.cpp, X86ExpandPseudo.cpp, X86FastISel.cpp, X86InstrInfo.cpp, X86ISelDAGToDAG.cpp, X86ISelLowering.cpp, X86LowerTileCopy.cpp
• GET_EXACTFPIMM_DECL : AArch64BaseInfo.h
• GET_EXACTFPIMM_IMPL : AArch64BaseInfo.cpp
• GET_ExecutionMode_DECL : SPIRVBaseInfo.h
• GET_ExecutionModel_DECL : SPIRVBaseInfo.h
• GET_ExtendedBuiltins_DECL : SPIRVBaseInfo.cpp, SPIRVBuiltins.cpp
• GET_ExtendedBuiltins_IMPL : SPIRVBaseInfo.cpp
• GET_Extension_DECL : SPIRVBaseInfo.h
• GET_ExtensionEntries_DECL : SPIRVBaseInfo.cpp
• GET_ExtensionEntries_IMPL : SPIRVBaseInfo.cpp
• GET_FIELD : AMDGPUDisassembler.cpp
• GET_FLAG_OPERAND_IDX : R600Defines.h
• GET_FP4FP8DstByteSelTable_DECL : AMDGPUBaseInfo.cpp
• GET_FP4FP8DstByteSelTable_IMPL : AMDGPUBaseInfo.cpp
• GET_FPFastMathMode_DECL : SPIRVBaseInfo.h
• GET_FPRoundingMode_DECL : SPIRVBaseInfo.h
• GET_FunctionControl_DECL : SPIRVBaseInfo.h
• GET_FunctionParameterAttribute_DECL : SPIRVBaseInfo.h
• GET_GetBuiltins_DECL : SPIRVBuiltins.cpp
• GET_GetBuiltins_IMPL : SPIRVBuiltins.cpp
• GET_getMFMA_F8F6F4_WithSize_DECL : AMDGPUBaseInfo.cpp
• GET_getMFMA_F8F6F4_WithSize_IMPL : AMDGPUBaseInfo.cpp
• GET_Gfx10BufferFormat_IMPL : AMDGPUBaseInfo.cpp
• GET_Gfx11PlusBufferFormat_IMPL : AMDGPUBaseInfo.cpp
• GET_Gfx9BufferFormat_IMPL : AMDGPUBaseInfo.cpp
• GET_GICOMBINER_CLASS_MEMBERS : AArch64PostLegalizerCombiner.cpp, RISCVPreLegalizerCombiner.cpp, RISCVPostLegalizerCombiner.cpp, RISCVO0PreLegalizerCombiner.cpp, MipsPostLegalizerCombiner.cpp, AMDGPURegBankCombiner.cpp, AMDGPUPreLegalizerCombiner.cpp, AMDGPUPostLegalizerCombiner.cpp, AArch64PreLegalizerCombiner.cpp, AArch64PostLegalizerLowering.cpp, AArch64O0PreLegalizerCombiner.cpp
• GET_GICOMBINER_CONSTRUCTOR_INITS : AMDGPUPreLegalizerCombiner.cpp, RISCVPreLegalizerCombiner.cpp, RISCVPostLegalizerCombiner.cpp, RISCVO0PreLegalizerCombiner.cpp, MipsPostLegalizerCombiner.cpp, AMDGPURegBankCombiner.cpp, AMDGPUPostLegalizerCombiner.cpp, AArch64PreLegalizerCombiner.cpp, AArch64PostLegalizerLowering.cpp, AArch64PostLegalizerCombiner.cpp, AArch64O0PreLegalizerCombiner.cpp
• GET_GICOMBINER_DEPS : AMDGPURegBankCombiner.cpp, RISCVPreLegalizerCombiner.cpp, RISCVPostLegalizerCombiner.cpp, RISCVO0PreLegalizerCombiner.cpp, MipsPostLegalizerCombiner.cpp, AMDGPUPreLegalizerCombiner.cpp, AMDGPUPostLegalizerCombiner.cpp, AArch64PreLegalizerCombiner.cpp, AArch64PostLegalizerLowering.cpp, AArch64PostLegalizerCombiner.cpp, AArch64O0PreLegalizerCombiner.cpp
• GET_GICOMBINER_IMPL : AArch64O0PreLegalizerCombiner.cpp, RISCVPreLegalizerCombiner.cpp, RISCVPostLegalizerCombiner.cpp, RISCVO0PreLegalizerCombiner.cpp, MipsPostLegalizerCombiner.cpp, AMDGPURegBankCombiner.cpp, AMDGPUPreLegalizerCombiner.cpp, AMDGPUPostLegalizerCombiner.cpp, AArch64PreLegalizerCombiner.cpp, AArch64PostLegalizerLowering.cpp, AArch64PostLegalizerCombiner.cpp
• GET_GICOMBINER_TYPES : RISCVPreLegalizerCombiner.cpp, RISCVPostLegalizerCombiner.cpp, AArch64PostLegalizerLowering.cpp, RISCVO0PreLegalizerCombiner.cpp, MipsPostLegalizerCombiner.cpp, AMDGPURegBankCombiner.cpp, AMDGPUPostLegalizerCombiner.cpp, AMDGPUPreLegalizerCombiner.cpp, AArch64O0PreLegalizerCombiner.cpp, AArch64PreLegalizerCombiner.cpp, AArch64PostLegalizerCombiner.cpp
• GET_GLOBALISEL_IMPL : PPCInstructionSelector.cpp, X86InstructionSelector.cpp, SPIRVInstructionSelector.cpp, RISCVInstructionSelector.cpp, MipsInstructionSelector.cpp, M68kInstructionSelector.cpp, BPFInstructionSelector.cpp, ARMInstructionSelector.cpp, AMDGPUInstructionSelector.cpp, AArch64InstructionSelector.cpp
• GET_GLOBALISEL_PREDICATE_BITSET : AMDGPUInstructionSelector.h, X86InstructionSelector.cpp, SPIRVInstructionSelector.cpp, RISCVInstructionSelector.cpp, PPCInstructionSelector.cpp, MipsInstructionSelector.cpp, M68kInstructionSelector.cpp, BPFInstructionSelector.cpp, ARMInstructionSelector.cpp, AArch64InstructionSelector.cpp
• GET_GLOBALISEL_PREDICATES_DECL : X86InstructionSelector.cpp, SPIRVInstructionSelector.cpp, RISCVInstructionSelector.cpp, PPCInstructionSelector.cpp, MipsInstructionSelector.cpp, BPFInstructionSelector.cpp, ARMInstructionSelector.cpp, AMDGPUInstructionSelector.h, AArch64InstructionSelector.cpp, M68kInstructionSelector.cpp
• GET_GLOBALISEL_PREDICATES_INIT : MipsInstructionSelector.cpp, X86InstructionSelector.cpp, SPIRVInstructionSelector.cpp, RISCVInstructionSelector.cpp, PPCInstructionSelector.cpp, M68kInstructionSelector.cpp, BPFInstructionSelector.cpp, ARMInstructionSelector.cpp, AMDGPUInstructionSelector.cpp, AArch64InstructionSelector.cpp
• GET_GLOBALISEL_TEMPORARIES_DECL : AArch64InstructionSelector.cpp, X86InstructionSelector.cpp, SPIRVInstructionSelector.cpp, RISCVInstructionSelector.cpp, PPCInstructionSelector.cpp, MipsInstructionSelector.cpp, M68kInstructionSelector.cpp, BPFInstructionSelector.cpp, ARMInstructionSelector.cpp, AMDGPUInstructionSelector.h
• GET_GLOBALISEL_TEMPORARIES_INIT : X86InstructionSelector.cpp, SPIRVInstructionSelector.cpp, RISCVInstructionSelector.cpp, PPCInstructionSelector.cpp, MipsInstructionSelector.cpp, BPFInstructionSelector.cpp, M68kInstructionSelector.cpp, AArch64InstructionSelector.cpp, AMDGPUInstructionSelector.cpp, ARMInstructionSelector.cpp
• GET_GLSLExtInst_DECL : SPIRVBaseInfo.h
• GET_GroupBuiltins_DECL : SPIRVBuiltins.cpp
• GET_GroupBuiltins_IMPL : SPIRVBuiltins.cpp
• GET_GroupOperation_DECL : SPIRVBaseInfo.h
• GET_GroupUniformBuiltins_DECL : SPIRVBuiltins.cpp
• GET_GroupUniformBuiltins_IMPL : SPIRVBuiltins.cpp
• GET_HVX_INTRINSICS : HexagonSubtarget.cpp
• GET_IC_DECL : AArch64BaseInfo.h
• GET_IC_IMPL : AArch64BaseInfo.cpp
• GET_ImageChannelDataType_DECL : SPIRVBaseInfo.h
• GET_ImageChannelOrder_DECL : SPIRVBaseInfo.h
• GET_ImageDimIntrinsicTable_IMPL : SIInstrInfo.cpp
• GET_ImageFormat_DECL : SPIRVBaseInfo.h
• GET_ImageOperand_DECL : SPIRVBaseInfo.h
• GET_ImageQueryBuiltins_DECL : SPIRVBuiltins.cpp
• GET_ImageQueryBuiltins_IMPL : SPIRVBuiltins.cpp
• GET_IMPLIED_EXTENSIONS : RISCVISAInfo.cpp
• GET_INSTRINFO_CTOR_DTOR : MipsInstrInfo.cpp, MSP430InstrInfo.cpp, NVPTXInstrInfo.cpp, PPCInstrInfo.cpp, RISCVInstrInfo.cpp, SparcInstrInfo.cpp, SPIRVInstrInfo.cpp, SystemZInstrInfo.cpp, VEInstrInfo.cpp, WebAssemblyInstrInfo.cpp, X86InstrInfo.cpp, XCoreInstrInfo.cpp, XtensaInstrInfo.cpp, DirectXInstrInfo.cpp, LoongArchInstrInfo.cpp, AArch64InstrInfo.cpp, R600InstrInfo.cpp, SIInstrInfo.cpp, ARCInstrInfo.cpp, ARMBaseInstrInfo.cpp, BPFInstrInfo.cpp, CSKYInstrInfo.cpp, AVRInstrInfo.cpp, HexagonInstrInfo.cpp, LanaiInstrInfo.cpp, M68kInstrInfo.cpp
• GET_INSTRINFO_ENUM : NVPTXMCTargetDesc.h, NVPTX.h, PPCMCTargetDesc.h, RISCVMCTargetDesc.h, SparcMCTargetDesc.h, SPIRVMCTargetDesc.h, SystemZMCTargetDesc.h, VEMCTargetDesc.h, WebAssemblyMCTargetDesc.h, WebAssemblyTargetInfo.cpp, X86MCTargetDesc.h, XCoreMCTargetDesc.h, XtensaMCTargetDesc.h, LoongArchMCTargetDesc.h, MipsMCTargetDesc.h, MSP430MCTargetDesc.h, AMDGPUMCTargetDesc.h, R600MCTargetDesc.h, ARCMCTargetDesc.h, ARMMCTargetDesc.h, AVRMCTargetDesc.h, BPFMCTargetDesc.h, DirectXMCTargetDesc.h, HexagonMCTargetDesc.h, LanaiMCTargetDesc.h, AArch64MCTargetDesc.h, M68kMCTargetDesc.h, CSKYMCTargetDesc.h
• GET_INSTRINFO_HEADER : MipsInstrInfo.h, MSP430InstrInfo.h, NVPTXInstrInfo.h, PPCInstrInfo.h, RISCVInstrInfo.h, SparcInstrInfo.h, SPIRVInstrInfo.h, SystemZInstrInfo.h, VEInstrInfo.h, WebAssemblyInstrInfo.h, X86InstrInfo.h, XCoreInstrInfo.h, XtensaInstrInfo.h, LoongArchInstrInfo.h, LanaiInstrInfo.h, HexagonInstrInfo.h, DirectXInstrInfo.h, CSKYInstrInfo.h, BPFInstrInfo.h, AVRInstrInfo.h, ARMBaseInstrInfo.h, ARCInstrInfo.h, SIInstrInfo.h, R600InstrInfo.h, AArch64InstrInfo.h, M68kInstrInfo.h
• GET_INSTRINFO_HELPER_DECLS : AArch64InstrInfo.h, X86InstrInfo.h
• GET_INSTRINFO_HELPERS : AArch64InstrInfo.cpp, X86InstrInfo.cpp
• GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP : M68kBaseInfo.h
• GET_INSTRINFO_MC_DESC : XtensaMCTargetDesc.cpp, XCoreMCTargetDesc.cpp, X86MCTargetDesc.cpp, WebAssemblyMCTargetDesc.cpp, VEMCTargetDesc.cpp, SystemZMCTargetDesc.cpp, SPIRVMCTargetDesc.cpp, SparcMCTargetDesc.cpp, RISCVMCTargetDesc.cpp, PPCMCTargetDesc.cpp, NVPTXMCTargetDesc.cpp, MSP430MCTargetDesc.cpp, MipsMCTargetDesc.cpp, LoongArchMCTargetDesc.cpp, M68kMCTargetDesc.cpp, AArch64MCTargetDesc.cpp, AMDGPUMCTargetDesc.cpp, R600MCTargetDesc.cpp, ARCMCTargetDesc.cpp, ARMMCTargetDesc.cpp, BPFMCTargetDesc.cpp, CSKYMCTargetDesc.cpp, DirectXMCTargetDesc.cpp, HexagonMCTargetDesc.cpp, LanaiMCTargetDesc.cpp, AVRMCTargetDesc.cpp
• GET_INSTRINFO_MC_HELPER_DECLS : MSP430MCTargetDesc.h, NVPTXMCTargetDesc.h, NVPTX.h, PPCMCTargetDesc.h, RISCVMCTargetDesc.h, SparcMCTargetDesc.h, SPIRVMCTargetDesc.h, SystemZMCTargetDesc.h, VEMCTargetDesc.h, WebAssemblyTargetInfo.cpp, X86MCTargetDesc.h, XCoreMCTargetDesc.h, WebAssemblyMCTargetDesc.h, R600MCTargetDesc.h, MipsMCTargetDesc.h, AMDGPUMCTargetDesc.h, ARCMCTargetDesc.h, AArch64MCTargetDesc.h, ARMMCTargetDesc.h, AVRMCTargetDesc.h, CSKYMCTargetDesc.h, M68kMCTargetDesc.h, LoongArchMCTargetDesc.h, LanaiMCTargetDesc.h, HexagonMCTargetDesc.h, DirectXMCTargetDesc.h, BPFMCTargetDesc.h
• GET_INSTRINFO_MC_HELPERS : AArch64MCTargetDesc.cpp, DirectXMCTargetDesc.cpp, X86MCTargetDesc.cpp
• GET_INSTRINFO_MI_OPS_INFO : M68kBaseInfo.h
• GET_INSTRINFO_NAMED_OPS : R600InstrInfo.cpp, AMDGPUBaseInfo.cpp, RISCVInstrInfo.cpp, WebAssemblyInstrInfo.cpp
• GET_INSTRINFO_OPERAND_ENUM : R600MCTargetDesc.h, WebAssemblyInstrInfo.h, AMDGPUMCTargetDesc.h, RISCVInstrInfo.h
• GET_INSTRINFO_OPERAND_TYPES_ENUM : AVRMCCodeEmitter.h, M68kBaseInfo.h
• GET_INSTRINFO_SCHED_ENUM : R600MCTargetDesc.h, HexagonMCTargetDesc.h, PPCMCTargetDesc.h
• GET_INSTRMAP_INFO : AVRMCCodeEmitter.cpp, XtensaMCCodeEmitter.cpp, WebAssemblyTargetInfo.cpp, SystemZInstrInfo.cpp, PPCInstrInfo.cpp, MipsMCCodeEmitter.cpp, LanaiMemAluCombiner.cpp, HexagonInstrInfo.cpp, ARCOptAddrMode.cpp, AMDGPUBaseInfo.cpp, R600InstrInfo.cpp, AArch64InstrInfo.cpp
• GET_INSTRUCTION_NAME : AArch64InstPrinter.cpp, VEInstPrinter.cpp, SparcInstPrinter.cpp, AArch64InstPrinter.cpp, HexagonInstPrinter.cpp
• GET_InstructionSet_DECL : SPIRVBaseInfo.h
• GET_IntelSubgroupsBuiltins_DECL : SPIRVBuiltins.cpp
• GET_IntelSubgroupsBuiltins_IMPL : SPIRVBuiltins.cpp
• GET_INTRINSIC_ARGKIND : Intrinsics.h
• GET_INTRINSIC_ATTRIBUTES : Intrinsics.cpp
• GET_INTRINSIC_ENUM_VALUES : Intrinsics.h
• GET_INTRINSIC_GENERATOR_GLOBAL : Intrinsics.cpp
• GET_INTRINSIC_IITINFO : Intrinsics.cpp
• GET_INTRINSIC_NAME_TABLE : Intrinsics.cpp
• GET_INTRINSIC_OVERLOAD_TABLE : Intrinsics.cpp
• GET_INTRINSIC_TARGET_DATA : Intrinsics.cpp
• GET_ISB_DECL : AArch64BaseInfo.h
• GET_ISB_IMPL : AArch64BaseInfo.cpp
• GET_isCvtScaleF32_F32F16ToF8F4Table_DECL : AMDGPUBaseInfo.h
• GET_isCvtScaleF32_F32F16ToF8F4Table_IMPL : AMDGPUBaseInfo.cpp
• GET_isMFMA_F8F6F4Table_DECL : AMDGPUBaseInfo.h
• GET_isMFMA_F8F6F4Table_IMPL : AMDGPUBaseInfo.cpp
• GET_KernelEnqueueFlags_DECL : SPIRVBaseInfo.h
• GET_KernelProfilingInfo_DECL : SPIRVBaseInfo.h
• GET_LinkageType_DECL : SPIRVBaseInfo.h
• GET_LLVM_INTRINSIC_FOR_CLANG_BUILTIN : Intrinsics.cpp
• GET_LLVM_INTRINSIC_FOR_MS_BUILTIN : Intrinsics.cpp
• GET_LoopControl_DECL : SPIRVBaseInfo.h
• GET_MAIInstInfoTable_DECL : AMDGPUBaseInfo.h
• GET_MAIInstInfoTable_IMPL : AMDGPUBaseInfo.cpp
• GET_MATCHER_IMPLEMENTATION : MSP430AsmParser.cpp, PPCAsmParser.cpp, RISCVAsmParser.cpp, SparcAsmParser.cpp, CSKYAsmParser.cpp, SystemZAsmParser.cpp, VEAsmParser.cpp, WebAssemblyAsmParser.cpp, X86AsmParser.cpp, XtensaAsmParser.cpp, M68kAsmParser.cpp, LoongArchAsmParser.cpp, LanaiAsmParser.cpp, HexagonAsmParser.cpp, BPFAsmParser.cpp, AVRAsmParser.cpp, ARMAsmParser.cpp, AMDGPUAsmParser.cpp, AArch64AsmParser.cpp, MipsAsmParser.cpp
• GET_MCLASSSYSREG_DECL : ARMBaseInfo.h
• GET_MCLASSSYSREG_IMPL : ARMBaseInfo.cpp
• GET_MemoryModel_DECL : SPIRVBaseInfo.h
• GET_MemoryOperand_DECL : SPIRVBaseInfo.h
• GET_MemorySemantics_DECL : SPIRVBaseInfo.h
• GET_MIMGBaseOpcode_DECL : AMDGPUBaseInfo.h
• GET_MIMGBaseOpcodesTable_IMPL : AMDGPUBaseInfo.cpp
• GET_MIMGBiASMapping_DECL : AMDGPUBaseInfo.h
• GET_MIMGBiasMappingTable_IMPL : AMDGPUBaseInfo.cpp
• GET_MIMGDim_DECL : AMDGPUBaseInfo.h
• GET_MIMGDimInfoTable_IMPL : AMDGPUBaseInfo.cpp
• GET_MIMGEncoding_DECL : AMDGPUBaseInfo.h
• GET_MIMGG16MappingTable_IMPL : AMDGPUBaseInfo.cpp
• GET_MIMGInfoTable_IMPL : AMDGPUBaseInfo.cpp
• GET_MIMGLZMapping_DECL : AMDGPUBaseInfo.h
• GET_MIMGLZMappingTable_IMPL : AMDGPUBaseInfo.cpp
• GET_MIMGMIPMapping_DECL : AMDGPUBaseInfo.h
• GET_MIMGMIPMappingTable_IMPL : AMDGPUBaseInfo.cpp
• GET_MIMGOffsetMappingTable_IMPL : AMDGPUBaseInfo.cpp
• GET_MNEMONIC_CHECKER : AMDGPUAsmParser.cpp
• GET_MNEMONIC_SPELL_CHECKER : AArch64AsmParser.cpp, AMDGPUAsmParser.cpp, ARMAsmParser.cpp, CSKYAsmParser.cpp, LoongArchAsmParser.cpp, MipsAsmParser.cpp, PPCAsmParser.cpp, RISCVAsmParser.cpp, SparcAsmParser.cpp, SystemZAsmParser.cpp
• GET_MTBUFInfoTable_DECL : AMDGPUBaseInfo.cpp
• GET_MTBUFInfoTable_IMPL : AMDGPUBaseInfo.cpp
• GET_MUBUFInfoTable_DECL : AMDGPUBaseInfo.cpp
• GET_MUBUFInfoTable_IMPL : AMDGPUBaseInfo.cpp
• GET_NativeBuiltins_DECL : SPIRVBuiltins.cpp
• GET_NativeBuiltins_IMPL : SPIRVBuiltins.cpp
• GET_ND_IF_ENABLED : X86InstrInfo.cpp, X86ISelDAGToDAG.cpp
• GET_NonSemanticExtInst_DECL : SPIRVBaseInfo.h
• GET_Opcode_DECL : SPIRVBaseInfo.h
• GET_OpenCLExtInst_DECL : SPIRVBaseInfo.h
• GET_OpenCLTypes_DECL : SPIRVBuiltins.cpp
• GET_OpenCLTypes_IMPL : SPIRVBuiltins.cpp
• GET_OPERAND_BIT_OFFSET : SystemZMCCodeEmitter.cpp
• GET_OPERAND_DIAGNOSTIC_TYPES : X86AsmParser.cpp, XtensaAsmParser.cpp, RISCVAsmParser.cpp, MipsAsmParser.cpp, CSKYAsmParser.cpp, LoongArchAsmParser.cpp, ARMAsmParser.cpp, AArch64AsmParser.cpp, BPFAsmParser.cpp
• GET_OperandCategory_DECL : SPIRVBaseInfo.h
• GET_OR_DISTINCT : LLParser.cpp, MetadataLoader.cpp
• GET_PASS_REGISTRY : AMDGPUTargetMachine.cpp, BPFTargetMachine.cpp, DirectXTargetMachine.cpp, HexagonTargetMachine.cpp, NVPTXTargetMachine.cpp, SPIRVTargetMachine.cpp, X86CodeGenPassBuilder.cpp
• GET_PHINT_DECL : AArch64BaseInfo.h
• GET_PHINT_IMPL : AArch64BaseInfo.cpp
• GET_PRCTX_DECL : AArch64BaseInfo.h
• GET_PRCTX_IMPL : AArch64BaseInfo.cpp
• GET_PrefetchTagsList_DECL : SparcMCTargetDesc.h
• GET_PrefetchTagsList_IMPL : SparcMCTargetDesc.cpp
• GET_PRFM_DECL : AArch64BaseInfo.h
• GET_PRFM_IMPL : AArch64BaseInfo.cpp
• GET_PSB_DECL : AArch64BaseInfo.h
• GET_PSB_IMPL : AArch64BaseInfo.cpp
• GET_PSTATEIMM0_15_DECL : AArch64BaseInfo.h
• GET_PSTATEIMM0_15_IMPL : AArch64BaseInfo.cpp
• GET_PSTATEIMM0_1_DECL : AArch64BaseInfo.h
• GET_PSTATEIMM0_1_IMPL : AArch64BaseInfo.cpp
• GET_REG_CHAN : R600Defines.h
• GET_REG_INDEX : R600Defines.h
• GET_REGBANK_DECLARATIONS : X86RegisterBankInfo.h, SPIRVRegisterBankInfo.h, RISCVRegisterBankInfo.h, PPCRegisterBankInfo.h, MipsRegisterBankInfo.h, BPFRegisterBankInfo.h, ARMRegisterBankInfo.h, AMDGPURegisterBankInfo.h, AArch64RegisterBankInfo.h, M68kRegisterBankInfo.h
• GET_REGINFO_ENUM : MSP430MCInstLower.cpp, RISCVMCTargetDesc.h, NVPTXMCTargetDesc.h, NVPTX.h, PPCMCTargetDesc.h, SparcMCTargetDesc.h, SPIRVMCTargetDesc.h, SPIRVRegisterBankInfo.cpp, SystemZMCTargetDesc.h, VEMCTargetDesc.h, WebAssemblyMCTargetDesc.h, WebAssemblyTypeUtilities.cpp, X86MCTargetDesc.h, XCoreMCTargetDesc.h, XtensaMCTargetDesc.h, MipsMCTargetDesc.h, AArch64MCTargetDesc.h, AMDGPUMCTargetDesc.h, R600MCTargetDesc.h, ARCMCTargetDesc.h, ARMMCTargetDesc.h, AVRMCTargetDesc.h, BPFMCTargetDesc.h, DirectXMCTargetDesc.h, HexagonMCTargetDesc.h, LanaiMCTargetDesc.h, CSKYMCTargetDesc.h, LoongArchMCTargetDesc.h, M68kMCTargetDesc.h, MSP430MCTargetDesc.h
• GET_REGINFO_HEADER : MSP430RegisterInfo.h, NVPTXRegisterInfo.h, PPCRegisterInfo.h, RISCVRegisterInfo.h, SparcRegisterInfo.h, SPIRVRegisterInfo.h, SystemZRegisterInfo.h, VERegisterInfo.h, WebAssemblyRegisterInfo.h, X86RegisterInfo.h, XCoreRegisterInfo.h, XtensaRegisterInfo.h, SIRegisterInfo.h, M68kRegisterInfo.h, MipsRegisterInfo.h, AArch64RegisterInfo.h, R600RegisterInfo.h, ARCRegisterInfo.h, ARMBaseRegisterInfo.h, AVRRegisterInfo.h, BPFRegisterInfo.h, CSKYRegisterInfo.h, DirectXRegisterInfo.h, HexagonRegisterInfo.h, LanaiRegisterInfo.h, LoongArchRegisterInfo.h
• GET_REGINFO_MC_DESC : MSP430MCTargetDesc.cpp, NVPTXMCTargetDesc.cpp, PPCMCTargetDesc.cpp, RISCVMCTargetDesc.cpp, SparcMCTargetDesc.cpp, SPIRVMCTargetDesc.cpp, SystemZMCTargetDesc.cpp, VEMCTargetDesc.cpp, WebAssemblyMCTargetDesc.cpp, X86MCTargetDesc.cpp, XCoreMCTargetDesc.cpp, XtensaMCTargetDesc.cpp, HexagonMCTargetDesc.cpp, M68kMCTargetDesc.cpp, MipsMCTargetDesc.cpp, AMDGPUMCTargetDesc.cpp, ARCMCTargetDesc.cpp, ARMMCTargetDesc.cpp, AVRMCTargetDesc.cpp, CSKYMCTargetDesc.cpp, DirectXMCTargetDesc.cpp, AArch64MCTargetDesc.cpp, LanaiMCTargetDesc.cpp, LoongArchMCTargetDesc.cpp, BPFMCTargetDesc.cpp
• GET_REGINFO_TARGET_DESC : MipsRegisterInfo.cpp, XCoreRegisterInfo.cpp, MSP430RegisterInfo.cpp, NVPTXRegisterInfo.cpp, PPCRegisterInfo.cpp, RISCVRegisterInfo.cpp, SparcRegisterInfo.cpp, SPIRVRegisterInfo.cpp, SystemZRegisterInfo.cpp, VERegisterInfo.cpp, WebAssemblyRegisterInfo.cpp, X86RegisterInfo.cpp, XtensaRegisterInfo.cpp, LoongArchRegisterInfo.cpp, M68kRegisterInfo.cpp, AArch64RegisterInfo.cpp, R600RegisterInfo.cpp, SIRegisterInfo.cpp, ARCRegisterInfo.cpp, ARMBaseRegisterInfo.cpp, BPFRegisterInfo.cpp, CSKYRegisterInfo.cpp, DirectXRegisterInfo.cpp, HexagonRegisterInfo.cpp, LanaiRegisterInfo.cpp, AVRRegisterInfo.cpp
• GET_REGISTER_MATCHER : MSP430AsmParser.cpp, PPCAsmParser.cpp, PPCISelLowering.cpp, RISCVAsmParser.cpp, HexagonAsmParser.cpp, RISCVISelLowering.cpp, SparcAsmParser.cpp, SystemZAsmParser.cpp, VEAsmParser.cpp, WebAssemblyAsmParser.cpp, X86AsmParser.cpp, XtensaAsmParser.cpp, MipsAsmParser.cpp, M68kAsmParser.cpp, LoongArchISelLowering.cpp, LoongArchAsmParser.cpp, LanaiAsmParser.cpp, CSKYAsmParser.cpp, BPFAsmParser.cpp, AVRAsmParser.cpp, ARMAsmParser.cpp, AMDGPUAsmParser.cpp, AArch64AsmParser.cpp, AArch64ISelLowering.cpp
• GET_RESULT : MachineBasicBlock.cpp, MachineLICM.cpp
• GET_RISCV_MACRO_FUSION_PRED_DECL : RISCVSubtarget.h
• GET_RISCV_MACRO_FUSION_PRED_IMPL : RISCVSubtarget.cpp
• GET_RISCVExtensionBitmaskTable_IMPL : RISCVTargetParser.cpp
• GET_RISCVMaskedPseudosTable_DECL : RISCVInstrInfo.h
• GET_RISCVMaskedPseudosTable_IMPL : RISCVInstrInfo.cpp
• GET_RISCVOpcodesList_DECL : RISCVBaseInfo.h
• GET_RISCVOpcodesList_IMPL : RISCVBaseInfo.cpp
• GET_RISCVTuneInfoTable_DECL : RISCVSubtarget.h
• GET_RISCVTuneInfoTable_IMPL : RISCVSubtarget.cpp
• GET_RISCVVIntrinsicsTable_DECL : RISCVISelLowering.h
• GET_RISCVVIntrinsicsTable_IMPL : RISCVISelLowering.cpp
• GET_RISCVVInversePseudosTable_DECL : RISCVMCTargetDesc.h
• GET_RISCVVInversePseudosTable_IMPL : RISCVMCTargetDesc.cpp
• GET_RISCVVLETable_DECL : RISCVISelDAGToDAG.h
• GET_RISCVVLETable_IMPL : RISCVISelDAGToDAG.cpp
• GET_RISCVVLSEGTable_DECL : RISCVISelDAGToDAG.h
• GET_RISCVVLSEGTable_IMPL : RISCVISelDAGToDAG.cpp
• GET_RISCVVLXSEGTable_DECL : RISCVISelDAGToDAG.h
• GET_RISCVVLXSEGTable_IMPL : RISCVISelDAGToDAG.cpp
• GET_RISCVVLXTable_DECL : RISCVISelDAGToDAG.h
• GET_RISCVVLXTable_IMPL : RISCVISelDAGToDAG.cpp
• GET_RISCVVPseudosTable_DECL : RISCVInstrInfo.h
• GET_RISCVVPseudosTable_IMPL : RISCVInstrInfo.cpp
• GET_RISCVVSETable_DECL : RISCVISelDAGToDAG.h
• GET_RISCVVSETable_IMPL : RISCVISelDAGToDAG.cpp
• GET_RISCVVSSEGTable_DECL : RISCVISelDAGToDAG.h
• GET_RISCVVSSEGTable_IMPL : RISCVISelDAGToDAG.cpp
• GET_RISCVVSXSEGTable_DECL : RISCVISelDAGToDAG.h
• GET_RISCVVSXSEGTable_IMPL : RISCVISelDAGToDAG.cpp
• GET_RISCVVSXTable_DECL : RISCVISelDAGToDAG.h
• GET_RISCVVSXTable_IMPL : RISCVISelDAGToDAG.cpp
• GET_RPRFM_DECL : AArch64BaseInfo.h
• GET_RPRFM_IMPL : AArch64BaseInfo.cpp
• GET_RsrcIntrinsics_IMPL : SIInstrInfo.cpp
• GET_SamplerAddressingMode_DECL : SPIRVBaseInfo.h
• GET_SamplerFilterMode_DECL : SPIRVBaseInfo.h
• GET_SCALAR_INTRINSICS : HexagonSubtarget.cpp
• GET_Scope_DECL : SPIRVBaseInfo.h
• GET_SelectionControl_DECL : SPIRVBaseInfo.h
• GET_SMInfoTable_DECL : AMDGPUBaseInfo.cpp
• GET_SMInfoTable_IMPL : AMDGPUBaseInfo.cpp
• GET_SourceLanguage_DECL : SPIRVBaseInfo.h
• GET_SourcesOfDivergence_IMPL : AMDGPUBaseInfo.cpp
• GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS : X86MCTargetDesc.cpp
• GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS : X86MCTargetDesc.cpp
• GET_StorageClass_DECL : SPIRVBaseInfo.h
• GET_SUBTARGET_FEATURE_NAME : SystemZAsmParser.cpp, X86AsmParser.cpp, WebAssemblyAsmParser.cpp, RISCVAsmParser.cpp, CSKYAsmParser.cpp, ARMAsmParser.cpp, AArch64AsmParser.cpp, LoongArchAsmParser.cpp
• GET_SUBTARGETINFO_CTOR : MSP430Subtarget.cpp, NVPTXSubtarget.cpp, PPCSubtarget.cpp, RISCVSubtarget.cpp, SparcSubtarget.cpp, SPIRVSubtarget.cpp, SystemZSubtarget.cpp, VESubtarget.cpp, WebAssemblySubtarget.cpp, X86Subtarget.cpp, XCoreSubtarget.cpp, XtensaSubtarget.cpp, AArch64Subtarget.cpp, M68kSubtarget.cpp, MipsSubtarget.cpp, GCNSubtarget.cpp, R600Subtarget.cpp, ARCSubtarget.cpp, ARMSubtarget.cpp, AVRSubtarget.cpp, CSKYSubtarget.cpp, DirectXSubtarget.cpp, HexagonSubtarget.cpp, LanaiSubtarget.cpp, LoongArchSubtarget.cpp, BPFSubtarget.cpp
• GET_SUBTARGETINFO_ENUM : MSP430MCTargetDesc.h, PPCMCTargetDesc.h, NVPTXMCTargetDesc.h, NVPTXSubtarget.cpp, RISCVMCTargetDesc.h, SparcMCTargetDesc.h, SPIRVMCTargetDesc.h, SystemZMCTargetDesc.h, VEMCTargetDesc.h, WebAssemblyMCTargetDesc.h, X86MCTargetDesc.h, XCoreMCTargetDesc.h, XtensaMCTargetDesc.h, M68kMCTargetDesc.h, AArch64MCTargetDesc.h, AMDGPUMCTargetDesc.h, R600MCTargetDesc.h, ARCMCTargetDesc.h, ARMMCTargetDesc.h, AVRMCTargetDesc.h, BPFMCTargetDesc.h, DirectXMCTargetDesc.h, HexagonMCTargetDesc.h, CSKYMCTargetDesc.h, LanaiMCTargetDesc.h, LoongArchMCTargetDesc.h, MipsMCTargetDesc.h
• GET_SUBTARGETINFO_HEADER : MipsSubtarget.h, MSP430Subtarget.h, NVPTXSubtarget.h, PPCSubtarget.h, RISCVSubtarget.h, SparcSubtarget.h, SPIRVSubtarget.h, SystemZSubtarget.h, VESubtarget.h, WebAssemblySubtarget.h, X86Subtarget.h, XCoreSubtarget.h, XtensaSubtarget.h, LoongArchSubtarget.h, M68kSubtarget.h, AArch64Subtarget.h, GCNSubtarget.h, R600Subtarget.h, ARCSubtarget.h, ARMSubtarget.h, AVRSubtarget.h, BPFSubtarget.h, CSKYSubtarget.h, DirectXSubtarget.h, HexagonSubtarget.h, LanaiSubtarget.h
• GET_SUBTARGETINFO_MACRO : PPCSubtarget.h, X86Subtarget.h, SystemZSubtarget.h, SparcSubtarget.h, RISCVSubtarget.h, PPCSubtarget.h, LoongArchSubtarget.h, AVRSubtarget.h, ARMSubtarget.h, AArch64Subtarget.h
• GET_SUBTARGETINFO_MC_DESC : MSP430MCTargetDesc.cpp, ARMMCTargetDesc.cpp, NVPTXMCTargetDesc.cpp, PPCMCTargetDesc.cpp, RISCVMCTargetDesc.cpp, SparcMCTargetDesc.cpp, SPIRVMCTargetDesc.cpp, SystemZMCTargetDesc.cpp, VEMCTargetDesc.cpp, WebAssemblyMCTargetDesc.cpp, X86MCTargetDesc.cpp, XCoreMCTargetDesc.cpp, XtensaMCTargetDesc.cpp, M68kMCTargetDesc.cpp, MipsMCTargetDesc.cpp, AArch64MCTargetDesc.cpp, AMDGPUMCTargetDesc.cpp, ARCMCTargetDesc.cpp, AVRMCTargetDesc.cpp, BPFMCTargetDesc.cpp, CSKYMCTargetDesc.cpp, DirectXMCTargetDesc.cpp, HexagonMCTargetDesc.cpp, LanaiMCTargetDesc.cpp, LoongArchMCTargetDesc.cpp
• GET_SUBTARGETINFO_TARGET_DESC : MipsSubtarget.cpp, MSP430Subtarget.cpp, NVPTXSubtarget.cpp, PPCSubtarget.cpp, RISCVSubtarget.cpp, SparcSubtarget.cpp, SPIRVSubtarget.cpp, SystemZSubtarget.cpp, VESubtarget.cpp, WebAssemblySubtarget.cpp, X86Subtarget.cpp, XCoreSubtarget.cpp, XtensaSubtarget.cpp, LoongArchSubtarget.cpp, M68kSubtarget.cpp, AArch64Subtarget.cpp, GCNSubtarget.cpp, R600Subtarget.cpp, ARCSubtarget.cpp, ARMSubtarget.cpp, BPFSubtarget.cpp, AVRSubtarget.cpp, LanaiSubtarget.cpp, HexagonSubtarget.cpp, CSKYSubtarget.cpp, DirectXSubtarget.cpp
• GET_SUPPORTED_EXTENSIONS : RISCVISAInfo.cpp
• GET_SUPPORTED_PROFILES : RISCVISAInfo.cpp
• GET_SVCR_DECL : AArch64BaseInfo.h
• GET_SVCR_IMPL : AArch64BaseInfo.cpp
• GET_SVEPREDPAT_DECL : AArch64BaseInfo.h
• GET_SVEPREDPAT_IMPL : AArch64BaseInfo.cpp
• GET_SVEPRFM_DECL : AArch64BaseInfo.h
• GET_SVEPRFM_IMPL : AArch64BaseInfo.cpp
• GET_SVEVECLENSPECIFIER_DECL : AArch64BaseInfo.h
• GET_SVEVECLENSPECIFIER_IMPL : AArch64BaseInfo.cpp
• GET_SymbolicOperands_DECL : SPIRVBaseInfo.cpp
• GET_SymbolicOperands_IMPL : SPIRVBaseInfo.cpp
• GET_SYSREG_DECL : AArch64BaseInfo.h
• GET_SYSREG_IMPL : AArch64BaseInfo.cpp
• GET_SysRegsList_DECL : RISCVBaseInfo.h
• GET_SysRegsList_IMPL : RISCVBaseInfo.cpp
• GET_TARGET_REGBANK_CLASS : X86RegisterBankInfo.h, SPIRVRegisterBankInfo.h, RISCVRegisterBankInfo.h, PPCRegisterBankInfo.h, MipsRegisterBankInfo.h, BPFRegisterBankInfo.h, ARMRegisterBankInfo.h, AMDGPURegisterBankInfo.h, AArch64RegisterBankInfo.h, M68kRegisterBankInfo.h
• GET_TARGET_REGBANK_IMPL : X86RegisterBankInfo.cpp, SPIRVRegisterBankInfo.cpp, RISCVRegisterBankInfo.cpp, PPCRegisterBankInfo.cpp, MipsRegisterBankInfo.cpp, BPFRegisterBankInfo.cpp, ARMRegisterBankInfo.cpp, AMDGPURegisterBankInfo.cpp, AArch64RegisterBankInfo.cpp, M68kRegisterBankInfo.cpp
• GET_TARGET_REGBANK_INFO_CLASS : X86RegisterBankInfo.h
• GET_TARGET_REGBANK_INFO_IMPL : X86RegisterBankInfo.cpp
• GET_TLBITable_DECL : AArch64BaseInfo.h
• GET_TLBITable_IMPL : AArch64BaseInfo.cpp
• GET_TSB_DECL : AArch64BaseInfo.h
• GET_TSB_IMPL : AArch64BaseInfo.cpp
• GET_UniformIntrinsics_IMPL : AMDGPUBaseInfo.cpp
• GET_VectorLoadStoreBuiltins_DECL : SPIRVBuiltins.cpp
• GET_VectorLoadStoreBuiltins_IMPL : SPIRVBuiltins.cpp
• GET_VLINDEX : VEInstrInfo.h
• GET_VOP1InfoTable_DECL : AMDGPUBaseInfo.cpp
• GET_VOP1InfoTable_IMPL : AMDGPUBaseInfo.cpp
• GET_VOP2InfoTable_DECL : AMDGPUBaseInfo.cpp
• GET_VOP2InfoTable_IMPL : AMDGPUBaseInfo.cpp
• GET_VOP3CAsmOnlyInfoTable_DECL : AMDGPUBaseInfo.cpp
• GET_VOP3CAsmOnlyInfoTable_IMPL : AMDGPUBaseInfo.cpp
• GET_VOP3InfoTable_DECL : AMDGPUBaseInfo.cpp
• GET_VOP3InfoTable_IMPL : AMDGPUBaseInfo.cpp
• GET_VOPC64DPP8Table_DECL : AMDGPUBaseInfo.cpp
• GET_VOPC64DPP8Table_IMPL : AMDGPUBaseInfo.cpp
• GET_VOPC64DPPTable_DECL : AMDGPUBaseInfo.cpp
• GET_VOPC64DPPTable_IMPL : AMDGPUBaseInfo.cpp
• GET_VOPCAsmOnlyInfoTable_DECL : AMDGPUBaseInfo.cpp
• GET_VOPCAsmOnlyInfoTable_IMPL : AMDGPUBaseInfo.cpp
• GET_VOPDComponentTable_DECL : AMDGPUBaseInfo.cpp
• GET_VOPDComponentTable_IMPL : AMDGPUBaseInfo.cpp
• GET_VOPDPairs_DECL : AMDGPUBaseInfo.cpp
• GET_VOPDPairs_IMPL : AMDGPUBaseInfo.cpp
• GET_VOPTrue16Table_DECL : AMDGPUBaseInfo.cpp
• GET_VOPTrue16Table_IMPL : AMDGPUBaseInfo.cpp
• GET_VT_ATTR : MachineValueType.h
• GET_VT_EVT : ValueTypes.cpp
• GET_VT_RANGES : MachineValueType.h
• GET_VT_VECATTR : MachineValueType.h
• GET_WMMAOpcode2AddrMappingTable_DECL : AMDGPUBaseInfo.cpp
• GET_WMMAOpcode2AddrMappingTable_IMPL : AMDGPUBaseInfo.cpp
• GET_WMMAOpcode3AddrMappingTable_DECL : AMDGPUBaseInfo.cpp
• GET_WMMAOpcode3AddrMappingTable_IMPL : AMDGPUBaseInfo.cpp
• GET_X86_COMPRESS_EVEX_TABLE : X86CompressEVEX.cpp
• GET_X86_MNEMONIC_TABLES_CPP : X86MnemonicTables.cpp
• GET_X86_MNEMONIC_TABLES_H : X86MCTargetDesc.h
• GET_X86_ND2NONND_TABLE : X86InstrInfo.cpp
• GET_X86_NF_TRANSFORM_TABLE : X86InstrInfo.cpp
• GET_X86_SSE2AVX_TABLE : X86AsmParser.cpp
• GETBITWITHMASK : XCOFFObjectFile.cpp
• GETBITWITHMASKSHIFT : XCOFFObjectFile.cpp
• GETNEXT : regcomp.c
• getOpcodeForVectorStParam : NVPTXISelDAGToDAG.cpp
• getOpcodeForVectorStParamV2 : NVPTXISelDAGToDAG.cpp
• getOpcodeForVectorStParamV4 : NVPTXISelDAGToDAG.cpp
• getOpcV2H : NVPTXISelDAGToDAG.cpp
• getOpcV2H1 : NVPTXISelDAGToDAG.cpp
• getOpcV4H : NVPTXISelDAGToDAG.cpp
• getOpcV4H1 : NVPTXISelDAGToDAG.cpp
• getOpcV4H2 : NVPTXISelDAGToDAG.cpp
• getOpcV4H3 : NVPTXISelDAGToDAG.cpp
• GETVALUE : XCOFFObjectFile.h
• GETVALUEWITHMASK : XCOFFObjectFile.cpp
• GETVALUEWITHMASKSHIFT : XCOFFObjectFile.cpp
• GISEL_VECREDUCE_CASES_ALL : Utils.h
• GISEL_VECREDUCE_CASES_NONSEQ : Utils.h
• GLOBAL_CACHE_MULTIPLIER : rpmalloc.c
• GOODFLAGS : regcomp.c, regexec.c