LLVM 19.0.0git
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SIInstrInfo.cpp File Reference

SI Implementation of TargetInstrInfo. More...

#include "SIInstrInfo.h"
#include "AMDGPU.h"
#include "AMDGPUInstrInfo.h"
#include "GCNHazardRecognizer.h"
#include "GCNSubtarget.h"
#include "SIMachineFunctionInfo.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/MC/MCContext.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Target/TargetMachine.h"
#include "AMDGPUGenInstrInfo.inc"
#include "AMDGPUGenSearchableTables.inc"

Go to the source code of this file.

Namespaces

namespace  llvm
 This is an optimization pass for GlobalISel generic memory operations.
 
namespace  llvm::AMDGPU
 

Macros

#define DEBUG_TYPE   "si-instr-info"
 
#define GET_INSTRINFO_CTOR_DTOR
 
#define GET_D16ImageDimIntrinsics_IMPL
 
#define GET_ImageDimIntrinsicTable_IMPL
 
#define GET_RsrcIntrinsics_IMPL
 

Functions

static unsigned getNumOperandsNoGlue (SDNode *Node)
 
static bool nodesHaveSameOperandValue (SDNode *N0, SDNode *N1, unsigned OpName)
 Returns true if both nodes have the same value for the given operand Op, or if both nodes do not have this operand.
 
static bool canRemat (const MachineInstr &MI)
 
static bool resultDependsOnExec (const MachineInstr &MI)
 
static bool isStride64 (unsigned Opc)
 
static bool memOpsHaveSameBasePtr (const MachineInstr &MI1, ArrayRef< const MachineOperand * > BaseOps1, const MachineInstr &MI2, ArrayRef< const MachineOperand * > BaseOps2)
 
static void reportIllegalCopy (const SIInstrInfo *TII, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, const char *Msg="illegal VGPR to SGPR copy")
 
static void indirectCopyToAGPR (const SIInstrInfo &TII, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, RegScavenger &RS, bool RegsOverlap, Register ImpDefSuperReg=Register(), Register ImpUseSuperReg=Register())
 Handle copying from SGPR to AGPR, or from AGPR to AGPR on GFX908.
 
static void expandSGPRCopy (const SIInstrInfo &TII, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, const TargetRegisterClass *RC, bool Forward)
 
static unsigned getIndirectVGPRWriteMovRelPseudoOpc (unsigned VecSize)
 
static unsigned getIndirectSGPRWriteMovRelPseudo32 (unsigned VecSize)
 
static unsigned getIndirectSGPRWriteMovRelPseudo64 (unsigned VecSize)
 
static unsigned getSGPRSpillSaveOpcode (unsigned Size)
 
static unsigned getVGPRSpillSaveOpcode (unsigned Size)
 
static unsigned getAGPRSpillSaveOpcode (unsigned Size)
 
static unsigned getAVSpillSaveOpcode (unsigned Size)
 
static unsigned getWWMRegSpillSaveOpcode (unsigned Size, bool IsVectorSuperClass)
 
static unsigned getVectorRegSpillSaveOpcode (Register Reg, const TargetRegisterClass *RC, unsigned Size, const SIRegisterInfo &TRI, const SIMachineFunctionInfo &MFI)
 
static unsigned getSGPRSpillRestoreOpcode (unsigned Size)
 
static unsigned getVGPRSpillRestoreOpcode (unsigned Size)
 
static unsigned getAGPRSpillRestoreOpcode (unsigned Size)
 
static unsigned getAVSpillRestoreOpcode (unsigned Size)
 
static unsigned getWWMRegSpillRestoreOpcode (unsigned Size, bool IsVectorSuperClass)
 
static unsigned getVectorRegSpillRestoreOpcode (Register Reg, const TargetRegisterClass *RC, unsigned Size, const SIRegisterInfo &TRI, const SIMachineFunctionInfo &MFI)
 
static MachineInstrswapRegAndNonRegOperand (MachineInstr &MI, MachineOperand &RegOp, MachineOperand &NonRegOp)
 
static void preserveCondRegFlags (MachineOperand &CondReg, const MachineOperand &OrigCond)
 
static bool memOpsHaveSameBaseOperands (ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2)
 
static bool offsetsDoNotOverlap (LocationSize WidthA, int OffsetA, LocationSize WidthB, int OffsetB)
 
static bool getFoldableImm (Register Reg, const MachineRegisterInfo &MRI, int64_t &Imm, MachineInstr **DefMI=nullptr)
 
static bool getFoldableImm (const MachineOperand *MO, int64_t &Imm, MachineInstr **DefMI=nullptr)
 
static void updateLiveVariables (LiveVariables *LV, MachineInstr &MI, MachineInstr &NewMI)
 
static bool changesVGPRIndexingMode (const MachineInstr &MI)
 
static bool compareMachineOp (const MachineOperand &Op0, const MachineOperand &Op1)
 
static void copyFlagsToImplicitVCC (MachineInstr &MI, const MachineOperand &Orig)
 
static Register findImplicitSGPRRead (const MachineInstr &MI)
 
static bool shouldReadExec (const MachineInstr &MI)
 
static bool isSubRegOf (const SIRegisterInfo &TRI, const MachineOperand &SuperVec, const MachineOperand &SubReg)
 
static const TargetRegisterClassadjustAllocatableRegClass (const GCNSubtarget &ST, const SIRegisterInfo &RI, const MachineRegisterInfo &MRI, const MCInstrDesc &TID, unsigned RCID, bool IsAllocatable)
 
static void emitLoadScalarOpsFromVGPRLoop (const SIInstrInfo &TII, MachineRegisterInfo &MRI, MachineBasicBlock &OrigBB, MachineBasicBlock &LoopBB, MachineBasicBlock &BodyBB, const DebugLoc &DL, ArrayRef< MachineOperand * > ScalarOps)
 
static MachineBasicBlockloadMBUFScalarOperandsFromVGPR (const SIInstrInfo &TII, MachineInstr &MI, ArrayRef< MachineOperand * > ScalarOps, MachineDominatorTree *MDT, MachineBasicBlock::iterator Begin=nullptr, MachineBasicBlock::iterator End=nullptr)
 
static std::tuple< unsigned, unsignedextractRsrcPtr (const SIInstrInfo &TII, MachineInstr &MI, MachineOperand &Rsrc)
 
static unsigned subtargetEncodingFamily (const GCNSubtarget &ST)
 
static TargetInstrInfo::RegSubRegPair getRegOrUndef (const MachineOperand &RegOpnd)
 
static bool followSubRegDef (MachineInstr &MI, TargetInstrInfo::RegSubRegPair &RSR)
 

Variables

static cl::opt< unsignedBranchOffsetBits ("amdgpu-s-branch-bits", cl::ReallyHidden, cl::init(16), cl::desc("Restrict range of branch instructions (DEBUG)"))
 
static cl::opt< boolFix16BitCopies ("amdgpu-fix-16-bit-physreg-copies", cl::desc("Fix copies between 32 and 16 bit registers by extending to 32 bit"), cl::init(true), cl::ReallyHidden)
 
static constexpr unsigned ModifierOpNames []
 

Detailed Description

SI Implementation of TargetInstrInfo.

Definition in file SIInstrInfo.cpp.

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "si-instr-info"

Definition at line 38 of file SIInstrInfo.cpp.

◆ GET_D16ImageDimIntrinsics_IMPL

#define GET_D16ImageDimIntrinsics_IMPL

Definition at line 45 of file SIInstrInfo.cpp.

◆ GET_ImageDimIntrinsicTable_IMPL

#define GET_ImageDimIntrinsicTable_IMPL

Definition at line 46 of file SIInstrInfo.cpp.

◆ GET_INSTRINFO_CTOR_DTOR

#define GET_INSTRINFO_CTOR_DTOR

Definition at line 40 of file SIInstrInfo.cpp.

◆ GET_RsrcIntrinsics_IMPL

#define GET_RsrcIntrinsics_IMPL

Definition at line 47 of file SIInstrInfo.cpp.

Function Documentation

◆ adjustAllocatableRegClass()

static const TargetRegisterClass * adjustAllocatableRegClass ( const GCNSubtarget ST,
const SIRegisterInfo RI,
const MachineRegisterInfo MRI,
const MCInstrDesc TID,
unsigned  RCID,
bool  IsAllocatable 
)
static

◆ canRemat()

static bool canRemat ( const MachineInstr MI)
static

◆ changesVGPRIndexingMode()

static bool changesVGPRIndexingMode ( const MachineInstr MI)
static

Definition at line 4069 of file SIInstrInfo.cpp.

References MI.

Referenced by llvm::SIInstrInfo::isSchedulingBoundary().

◆ compareMachineOp()

static bool compareMachineOp ( const MachineOperand Op0,
const MachineOperand Op1 
)
static

◆ copyFlagsToImplicitVCC()

static void copyFlagsToImplicitVCC ( MachineInstr MI,
const MachineOperand Orig 
)
static

◆ emitLoadScalarOpsFromVGPRLoop()

static void emitLoadScalarOpsFromVGPRLoop ( const SIInstrInfo TII,
MachineRegisterInfo MRI,
MachineBasicBlock OrigBB,
MachineBasicBlock LoopBB,
MachineBasicBlock BodyBB,
const DebugLoc DL,
ArrayRef< MachineOperand * >  ScalarOps 
)
static

◆ expandSGPRCopy()

static void expandSGPRCopy ( const SIInstrInfo TII,
MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
const DebugLoc DL,
MCRegister  DestReg,
MCRegister  SrcReg,
bool  KillSrc,
const TargetRegisterClass RC,
bool  Forward 
)
static

◆ extractRsrcPtr()

static std::tuple< unsigned, unsigned > extractRsrcPtr ( const SIInstrInfo TII,
MachineInstr MI,
MachineOperand Rsrc 
)
static

◆ findImplicitSGPRRead()

static Register findImplicitSGPRRead ( const MachineInstr MI)
static

◆ followSubRegDef()

static bool followSubRegDef ( MachineInstr MI,
TargetInstrInfo::RegSubRegPair RSR 
)
static

◆ getAGPRSpillRestoreOpcode()

static unsigned getAGPRSpillRestoreOpcode ( unsigned  Size)
static

Definition at line 1844 of file SIInstrInfo.cpp.

References llvm_unreachable, and Size.

Referenced by getVectorRegSpillRestoreOpcode().

◆ getAGPRSpillSaveOpcode()

static unsigned getAGPRSpillSaveOpcode ( unsigned  Size)
static

Definition at line 1618 of file SIInstrInfo.cpp.

References llvm_unreachable, and Size.

Referenced by getVectorRegSpillSaveOpcode().

◆ getAVSpillRestoreOpcode()

static unsigned getAVSpillRestoreOpcode ( unsigned  Size)
static

Definition at line 1879 of file SIInstrInfo.cpp.

References llvm_unreachable, and Size.

Referenced by getVectorRegSpillRestoreOpcode().

◆ getAVSpillSaveOpcode()

static unsigned getAVSpillSaveOpcode ( unsigned  Size)
static

Definition at line 1653 of file SIInstrInfo.cpp.

References llvm_unreachable, and Size.

Referenced by getVectorRegSpillSaveOpcode().

◆ getFoldableImm() [1/2]

static bool getFoldableImm ( const MachineOperand MO,
int64_t &  Imm,
MachineInstr **  DefMI = nullptr 
)
static

◆ getFoldableImm() [2/2]

static bool getFoldableImm ( Register  Reg,
const MachineRegisterInfo MRI,
int64_t &  Imm,
MachineInstr **  DefMI = nullptr 
)
static

◆ getIndirectSGPRWriteMovRelPseudo32()

static unsigned getIndirectSGPRWriteMovRelPseudo32 ( unsigned  VecSize)
static

Definition at line 1486 of file SIInstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SIInstrInfo::getIndirectRegWriteMovRelPseudo().

◆ getIndirectSGPRWriteMovRelPseudo64()

static unsigned getIndirectSGPRWriteMovRelPseudo64 ( unsigned  VecSize)
static

Definition at line 1515 of file SIInstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SIInstrInfo::getIndirectRegWriteMovRelPseudo().

◆ getIndirectVGPRWriteMovRelPseudoOpc()

static unsigned getIndirectVGPRWriteMovRelPseudoOpc ( unsigned  VecSize)
static

Definition at line 1457 of file SIInstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SIInstrInfo::getIndirectRegWriteMovRelPseudo().

◆ getNumOperandsNoGlue()

static unsigned getNumOperandsNoGlue ( SDNode Node)
static

Definition at line 76 of file SIInstrInfo.cpp.

References N.

Referenced by llvm::SIInstrInfo::areLoadsFromSameBasePtr().

◆ getRegOrUndef()

static TargetInstrInfo::RegSubRegPair getRegOrUndef ( const MachineOperand RegOpnd)
static

◆ getSGPRSpillRestoreOpcode()

static unsigned getSGPRSpillRestoreOpcode ( unsigned  Size)
static

Definition at line 1774 of file SIInstrInfo.cpp.

References llvm_unreachable, and Size.

Referenced by llvm::SIInstrInfo::loadRegFromStackSlot().

◆ getSGPRSpillSaveOpcode()

static unsigned getSGPRSpillSaveOpcode ( unsigned  Size)
static

Definition at line 1548 of file SIInstrInfo.cpp.

References llvm_unreachable, and Size.

Referenced by llvm::SIInstrInfo::storeRegToStackSlot().

◆ getVectorRegSpillRestoreOpcode()

static unsigned getVectorRegSpillRestoreOpcode ( Register  Reg,
const TargetRegisterClass RC,
unsigned  Size,
const SIRegisterInfo TRI,
const SIMachineFunctionInfo MFI 
)
static

◆ getVectorRegSpillSaveOpcode()

static unsigned getVectorRegSpillSaveOpcode ( Register  Reg,
const TargetRegisterClass RC,
unsigned  Size,
const SIRegisterInfo TRI,
const SIMachineFunctionInfo MFI 
)
static

◆ getVGPRSpillRestoreOpcode()

static unsigned getVGPRSpillRestoreOpcode ( unsigned  Size)
static

Definition at line 1809 of file SIInstrInfo.cpp.

References llvm_unreachable, and Size.

Referenced by getVectorRegSpillRestoreOpcode().

◆ getVGPRSpillSaveOpcode()

static unsigned getVGPRSpillSaveOpcode ( unsigned  Size)
static

Definition at line 1583 of file SIInstrInfo.cpp.

References llvm_unreachable, and Size.

Referenced by getVectorRegSpillSaveOpcode().

◆ getWWMRegSpillRestoreOpcode()

static unsigned getWWMRegSpillRestoreOpcode ( unsigned  Size,
bool  IsVectorSuperClass 
)
static

Definition at line 1914 of file SIInstrInfo.cpp.

References llvm_unreachable, and Size.

Referenced by getVectorRegSpillRestoreOpcode().

◆ getWWMRegSpillSaveOpcode()

static unsigned getWWMRegSpillSaveOpcode ( unsigned  Size,
bool  IsVectorSuperClass 
)
static

Definition at line 1688 of file SIInstrInfo.cpp.

References llvm_unreachable, and Size.

Referenced by getVectorRegSpillSaveOpcode().

◆ indirectCopyToAGPR()

static void indirectCopyToAGPR ( const SIInstrInfo TII,
MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
const DebugLoc DL,
MCRegister  DestReg,
MCRegister  SrcReg,
bool  KillSrc,
RegScavenger RS,
bool  RegsOverlap,
Register  ImpDefSuperReg = Register(),
Register  ImpUseSuperReg = Register() 
)
static

◆ isStride64()

static bool isStride64 ( unsigned  Opc)
static

Definition at line 347 of file SIInstrInfo.cpp.

Referenced by llvm::SIInstrInfo::getMemOperandsWithOffsetWidth().

◆ isSubRegOf()

static bool isSubRegOf ( const SIRegisterInfo TRI,
const MachineOperand SuperVec,
const MachineOperand SubReg 
)
static

Definition at line 4604 of file SIInstrInfo.cpp.

References llvm::MachineOperand::getReg(), SubReg, and TRI.

Referenced by llvm::SIInstrInfo::verifyInstruction().

◆ loadMBUFScalarOperandsFromVGPR()

static MachineBasicBlock * loadMBUFScalarOperandsFromVGPR ( const SIInstrInfo TII,
MachineInstr MI,
ArrayRef< MachineOperand * >  ScalarOps,
MachineDominatorTree MDT,
MachineBasicBlock::iterator  Begin = nullptr,
MachineBasicBlock::iterator  End = nullptr 
)
static

◆ memOpsHaveSameBaseOperands()

static bool memOpsHaveSameBaseOperands ( ArrayRef< const MachineOperand * >  BaseOps1,
ArrayRef< const MachineOperand * >  BaseOps2 
)
static

Definition at line 3685 of file SIInstrInfo.cpp.

References I, and llvm::ArrayRef< T >::size().

◆ memOpsHaveSameBasePtr()

static bool memOpsHaveSameBasePtr ( const MachineInstr MI1,
ArrayRef< const MachineOperand * >  BaseOps1,
const MachineInstr MI2,
ArrayRef< const MachineOperand * >  BaseOps2 
)
static

◆ nodesHaveSameOperandValue()

static bool nodesHaveSameOperandValue ( SDNode N0,
SDNode N1,
unsigned  OpName 
)
static

Returns true if both nodes have the same value for the given operand Op, or if both nodes do not have this operand.

Definition at line 85 of file SIInstrInfo.cpp.

References llvm::SDNode::getMachineOpcode(), llvm::AMDGPU::getNamedOperandIdx(), and llvm::SDNode::getOperand().

Referenced by llvm::SIInstrInfo::areLoadsFromSameBasePtr().

◆ offsetsDoNotOverlap()

static bool offsetsDoNotOverlap ( LocationSize  WidthA,
int  OffsetA,
LocationSize  WidthB,
int  OffsetB 
)
static

◆ preserveCondRegFlags()

static void preserveCondRegFlags ( MachineOperand CondReg,
const MachineOperand OrigCond 
)
static

◆ reportIllegalCopy()

static void reportIllegalCopy ( const SIInstrInfo TII,
MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
const DebugLoc DL,
MCRegister  DestReg,
MCRegister  SrcReg,
bool  KillSrc,
const char Msg = "illegal VGPR to SGPR copy" 
)
static

◆ resultDependsOnExec()

static bool resultDependsOnExec ( const MachineInstr MI)
static

Definition at line 152 of file SIInstrInfo.cpp.

References llvm::Register::isVirtual(), MI, and MRI.

Referenced by llvm::SIInstrInfo::isIgnorableUse().

◆ shouldReadExec()

static bool shouldReadExec ( const MachineInstr MI)
static

◆ subtargetEncodingFamily()

static unsigned subtargetEncodingFamily ( const GCNSubtarget ST)
static

◆ swapRegAndNonRegOperand()

static MachineInstr * swapRegAndNonRegOperand ( MachineInstr MI,
MachineOperand RegOp,
MachineOperand NonRegOp 
)
static

◆ updateLiveVariables()

static void updateLiveVariables ( LiveVariables LV,
MachineInstr MI,
MachineInstr NewMI 
)
static

Variable Documentation

◆ BranchOffsetBits

cl::opt< unsigned > BranchOffsetBits("amdgpu-s-branch-bits", cl::ReallyHidden, cl::init(16), cl::desc("Restrict range of branch instructions (DEBUG)")) ( "amdgpu-s-branch-bits"  ,
cl::ReallyHidden  ,
cl::init(16)  ,
cl::desc("Restrict range of branch instructions (DEBUG)")   
)
static

◆ Fix16BitCopies

cl::opt< bool > Fix16BitCopies("amdgpu-fix-16-bit-physreg-copies", cl::desc("Fix copies between 32 and 16 bit registers by extending to 32 bit"), cl::init(true), cl::ReallyHidden) ( "amdgpu-fix-16-bit-physreg-copies"  ,
cl::desc("Fix copies between 32 and 16 bit registers by extending to 32 bit")  ,
cl::init(true ,
cl::ReallyHidden   
)
static

◆ ModifierOpNames

constexpr unsigned ModifierOpNames[]
staticconstexpr
Initial value:
= {
AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src1_modifiers,
AMDGPU::OpName::src2_modifiers, AMDGPU::OpName::clamp,
AMDGPU::OpName::omod, AMDGPU::OpName::op_sel}

Definition at line 3398 of file SIInstrInfo.cpp.

Referenced by llvm::SIInstrInfo::hasAnyModifiersSet(), and llvm::SIInstrInfo::removeModOperands().