#include "SIInstrInfo.h"
#include "AMDGPU.h"
#include "AMDGPUInstrInfo.h"
#include "GCNHazardRecognizer.h"
#include "GCNSubtarget.h"
#include "SIMachineFunctionInfo.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/MC/MCContext.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Target/TargetMachine.h"
#include "AMDGPUGenInstrInfo.inc"
#include "AMDGPUGenSearchableTables.inc"

Include dependency graph for SIInstrInfo.cpp:

Namespaces
	llvm
	This is an optimization pass for GlobalISel generic memory operations.

	llvm::AMDGPU

Macros
#define	DEBUG_TYPE "si-instr-info"

#define	GET_INSTRINFO_CTOR_DTOR

#define	GET_D16ImageDimIntrinsics_IMPL

#define	GET_ImageDimIntrinsicTable_IMPL

#define	GET_RsrcIntrinsics_IMPL

Enumerations
enum	SIEncodingFamily { SI = 0, VI = 1, SDWA = 2, SDWA9 = 3, GFX80 = 4, GFX9 = 5, GFX10 = 6, SDWA10 = 7, GFX90A = 8, GFX940 = 9, GFX11 = 10 }

Functions
static unsigned	getNumOperandsNoGlue (SDNode *Node)

static bool	nodesHaveSameOperandValue (SDNode N0, SDNode N1, unsigned OpName)
	Returns true if both nodes have the same value for the given operand `Op`, or if both nodes do not have this operand. More...

static bool	resultDependsOnExec (const MachineInstr &MI)

static bool	isStride64 (unsigned Opc)

static bool	memOpsHaveSameBasePtr (const MachineInstr &MI1, ArrayRef< const MachineOperand * > BaseOps1, const MachineInstr &MI2, ArrayRef< const MachineOperand * > BaseOps2)

static void	reportIllegalCopy (const SIInstrInfo TII, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, const char Msg="illegal SGPR to VGPR copy")

static void	indirectCopyToAGPR (const SIInstrInfo &TII, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, RegScavenger &RS, Register ImpDefSuperReg=Register(), Register ImpUseSuperReg=Register())
	Handle copying from SGPR to AGPR, or from AGPR to AGPR on GFX908. More...

static void	expandSGPRCopy (const SIInstrInfo &TII, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, const TargetRegisterClass *RC, bool Forward)

static unsigned	getIndirectVGPRWriteMovRelPseudoOpc (unsigned VecSize)

static unsigned	getIndirectSGPRWriteMovRelPseudo32 (unsigned VecSize)

static unsigned	getIndirectSGPRWriteMovRelPseudo64 (unsigned VecSize)

static unsigned	getSGPRSpillSaveOpcode (unsigned Size)

static unsigned	getVGPRSpillSaveOpcode (unsigned Size)

static unsigned	getAGPRSpillSaveOpcode (unsigned Size)

static unsigned	getAVSpillSaveOpcode (unsigned Size)

static unsigned	getSGPRSpillRestoreOpcode (unsigned Size)

static unsigned	getVGPRSpillRestoreOpcode (unsigned Size)

static unsigned	getAGPRSpillRestoreOpcode (unsigned Size)

static unsigned	getAVSpillRestoreOpcode (unsigned Size)

static MachineInstr *	swapRegAndNonRegOperand (MachineInstr &MI, MachineOperand &RegOp, MachineOperand &NonRegOp)

static void	preserveCondRegFlags (MachineOperand &CondReg, const MachineOperand &OrigCond)

static bool	memOpsHaveSameBaseOperands (ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2)

static bool	offsetsDoNotOverlap (int WidthA, int OffsetA, int WidthB, int OffsetB)

static bool	getFoldableImm (Register Reg, const MachineRegisterInfo &MRI, int64_t &Imm, MachineInstr **DefMI=nullptr)

static bool	getFoldableImm (const MachineOperand MO, int64_t &Imm, MachineInstr *DefMI=nullptr)

static void	updateLiveVariables (LiveVariables *LV, MachineInstr &MI, MachineInstr &NewMI)

static bool	changesVGPRIndexingMode (const MachineInstr &MI)

static bool	compareMachineOp (const MachineOperand &Op0, const MachineOperand &Op1)

static void	copyFlagsToImplicitVCC (MachineInstr &MI, const MachineOperand &Orig)

static Register	findImplicitSGPRRead (const MachineInstr &MI)

static bool	shouldReadExec (const MachineInstr &MI)

static bool	isSubRegOf (const SIRegisterInfo &TRI, const MachineOperand &SuperVec, const MachineOperand &SubReg)

static const TargetRegisterClass *	adjustAllocatableRegClass (const GCNSubtarget &ST, const SIRegisterInfo &RI, const MachineRegisterInfo &MRI, const MCInstrDesc &TID, unsigned RCID, bool IsAllocatable)

static void	emitLoadSRsrcFromVGPRLoop (const SIInstrInfo &TII, MachineRegisterInfo &MRI, MachineBasicBlock &OrigBB, MachineBasicBlock &LoopBB, MachineBasicBlock &BodyBB, const DebugLoc &DL, MachineOperand &Rsrc)

static MachineBasicBlock *	loadSRsrcFromVGPR (const SIInstrInfo &TII, MachineInstr &MI, MachineOperand &Rsrc, MachineDominatorTree *MDT, MachineBasicBlock::iterator Begin=nullptr, MachineBasicBlock::iterator End=nullptr)

static std::tuple< unsigned, unsigned >	extractRsrcPtr (const SIInstrInfo &TII, MachineInstr &MI, MachineOperand &Rsrc)

static SIEncodingFamily	subtargetEncodingFamily (const GCNSubtarget &ST)

static TargetInstrInfo::RegSubRegPair	getRegOrUndef (const MachineOperand &RegOpnd)

static bool	followSubRegDef (MachineInstr &MI, TargetInstrInfo::RegSubRegPair &RSR)

Variables
static cl::opt< unsigned >	BranchOffsetBits ("amdgpu-s-branch-bits", cl::ReallyHidden, cl::init(16), cl::desc("Restrict range of branch instructions (DEBUG)"))

static cl::opt< bool >	Fix16BitCopies ("amdgpu-fix-16-bit-physreg-copies", cl::desc("Fix copies between 32 and 16 bit registers by extending to 32 bit"), cl::init(true), cl::ReallyHidden)

static constexpr unsigned	ModifierOpNames []

Detailed Description

SI Implementation of TargetInstrInfo.

Definition in file SIInstrInfo.cpp.

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE "si-instr-info"

Definition at line 36 of file SIInstrInfo.cpp.

◆ GET_D16ImageDimIntrinsics_IMPL

#define GET_D16ImageDimIntrinsics_IMPL

Definition at line 43 of file SIInstrInfo.cpp.

◆ GET_ImageDimIntrinsicTable_IMPL

#define GET_ImageDimIntrinsicTable_IMPL

Definition at line 44 of file SIInstrInfo.cpp.

◆ GET_INSTRINFO_CTOR_DTOR

#define GET_INSTRINFO_CTOR_DTOR

Definition at line 38 of file SIInstrInfo.cpp.

◆ GET_RsrcIntrinsics_IMPL

#define GET_RsrcIntrinsics_IMPL

Definition at line 45 of file SIInstrInfo.cpp.

Enumeration Type Documentation

◆ SIEncodingFamily

enum SIEncodingFamily

Enumerator
SI
VI
SDWA
SDWA9
GFX80
GFX9
GFX10
SDWA10
GFX90A
GFX940
GFX11

Definition at line 7881 of file SIInstrInfo.cpp.

Function Documentation

◆ adjustAllocatableRegClass()

static const TargetRegisterClass* adjustAllocatableRegClass	(	const GCNSubtarget &	ST,
		const SIRegisterInfo &	RI,
		const MachineRegisterInfo &	MRI,
		const MCInstrDesc &	TID,
		unsigned	RCID,
		bool	IsAllocatable
	)

static

Definition at line 4776 of file SIInstrInfo.cpp.

References llvm::SIInstrFlags::DS, llvm::SIRegisterInfo::getProperlyAlignedRC(), llvm::SIRegisterInfo::getRegClass(), llvm::MCInstrDesc::mayLoad(), llvm::MCInstrDesc::mayStore(), llvm::SIInstrFlags::MIMG, MRI, llvm::MachineRegisterInfo::reservedRegsFrozen(), llvm::MCInstrDesc::TSFlags, and llvm::SIInstrFlags::VGPRSpill.

Referenced by llvm::SIInstrInfo::getOpRegClass(), and llvm::SIInstrInfo::getRegClass().

◆ changesVGPRIndexingMode()

static bool changesVGPRIndexingMode ( const MachineInstr & MI )

static

Definition at line 3486 of file SIInstrInfo.cpp.

References MI.

Referenced by llvm::SIInstrInfo::isSchedulingBoundary().

◆ compareMachineOp()

static bool compareMachineOp	(	const MachineOperand &	Op0,
		const MachineOperand &	Op1
	)

static

Definition at line 3723 of file SIInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getType(), llvm_unreachable, llvm::MachineOperand::MO_Immediate, and llvm::MachineOperand::MO_Register.

Referenced by llvm::SIInstrInfo::verifyInstruction().

◆ copyFlagsToImplicitVCC()

static void copyFlagsToImplicitVCC	(	MachineInstr &	MI,
		const MachineOperand &	Orig
	)

static

Definition at line 3855 of file SIInstrInfo.cpp.

References llvm::MachineOperand::isKill(), llvm::MachineOperand::isUndef(), and MI.

Referenced by llvm::SIInstrInfo::buildShrunkInst().

◆ emitLoadSRsrcFromVGPRLoop()

static void emitLoadSRsrcFromVGPRLoop	(	const SIInstrInfo &	TII,
		MachineRegisterInfo &	MRI,
		MachineBasicBlock &	OrigBB,
		MachineBasicBlock &	LoopBB,
		MachineBasicBlock &	BodyBB,
		const DebugLoc &	DL,
		MachineOperand &	Rsrc
	)

static

◆ expandSGPRCopy()

static void expandSGPRCopy	(	const SIInstrInfo &	TII,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		const DebugLoc &	DL,
		MCRegister	DestReg,
		MCRegister	SrcReg,
		bool	KillSrc,
		const TargetRegisterClass *	RC,
		bool	Forward
	)

static

Definition at line 663 of file SIInstrInfo.cpp.

References llvm::MachineInstr::addOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineOperand::CreateReg(), DL, llvm::SIRegisterInfo::getChannelFromSubReg(), llvm::SIRegisterInfo::getRegSplitParts(), llvm::SIRegisterInfo::getSubRegFromChannel(), I, llvm::RegState::Implicit, MBB, MI, llvm::ArrayRef< T >::size(), std::swap(), and TII.

Referenced by llvm::SIInstrInfo::copyPhysReg().

◆ extractRsrcPtr()

static std::tuple<unsigned, unsigned> extractRsrcPtr	(	const SIInstrInfo &	TII,
		MachineInstr &	MI,
		MachineOperand &	Rsrc
	)

static

Definition at line 5677 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), MBB, MI, MRI, and TII.

◆ findImplicitSGPRRead()

static Register findImplicitSGPRRead ( const MachineInstr & MI )

static

Definition at line 3942 of file SIInstrInfo.cpp.

References llvm::M0(), and MI.

Referenced by llvm::SIInstrInfo::legalizeOperandsVOP2(), and llvm::SIInstrInfo::verifyInstruction().

◆ followSubRegDef()

static bool followSubRegDef	(	MachineInstr &	MI,
		TargetInstrInfo::RegSubRegPair &	RSR
	)

static

Definition at line 8015 of file SIInstrInfo.cpp.

References getRegOrUndef(), llvm::getRegSequenceSubReg(), MI, llvm::TargetInstrInfo::RegSubRegPair::Reg, and llvm::TargetInstrInfo::RegSubRegPair::SubReg.

Referenced by llvm::getVRegSubRegDef().

◆ getAGPRSpillRestoreOpcode()

static unsigned getAGPRSpillRestoreOpcode ( unsigned Size )

static

Definition at line 1627 of file SIInstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SIInstrInfo::loadRegFromStackSlot().

◆ getAGPRSpillSaveOpcode()

static unsigned getAGPRSpillSaveOpcode ( unsigned Size )

static

Definition at line 1460 of file SIInstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SIInstrInfo::storeRegToStackSlot().

◆ getAVSpillRestoreOpcode()

static unsigned getAVSpillRestoreOpcode ( unsigned Size )

static

Definition at line 1654 of file SIInstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SIInstrInfo::loadRegFromStackSlot().

◆ getAVSpillSaveOpcode()

static unsigned getAVSpillSaveOpcode ( unsigned Size )

static

Definition at line 1487 of file SIInstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SIInstrInfo::storeRegToStackSlot().

◆ getFoldableImm() [1/2]

static bool getFoldableImm	(	const MachineOperand *	MO,
		int64_t &	Imm,
		MachineInstr **	DefMI = `nullptr`
	)

static

Definition at line 3247 of file SIInstrInfo.cpp.

References DefMI, getFoldableImm(), llvm::MachineOperand::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::RISCVMatInt::Imm, llvm::MachineOperand::isReg(), and MRI.

◆ getFoldableImm() [2/2]

static bool getFoldableImm	(	Register	Reg,
		const MachineRegisterInfo &	MRI,
		int64_t &	Imm,
		MachineInstr **	DefMI = `nullptr`
	)

static

Definition at line 3233 of file SIInstrInfo.cpp.

References llvm::tgtok::Def, DefMI, llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::RISCVMatInt::Imm, llvm::SIInstrInfo::isFoldableCopy(), and MRI.

Referenced by llvm::SIInstrInfo::convertToThreeAddress(), getFoldableImm(), and llvm::SIInstrInfo::optimizeCompareInstr().

◆ getIndirectSGPRWriteMovRelPseudo32()

static unsigned getIndirectSGPRWriteMovRelPseudo32 ( unsigned VecSize )

static

Definition at line 1352 of file SIInstrInfo.cpp.

References llvm_unreachable, and llvm::ARMII::VecSize.

Referenced by llvm::SIInstrInfo::getIndirectRegWriteMovRelPseudo().

◆ getIndirectSGPRWriteMovRelPseudo64()

static unsigned getIndirectSGPRWriteMovRelPseudo64 ( unsigned VecSize )

static

Definition at line 1373 of file SIInstrInfo.cpp.

References llvm_unreachable, and llvm::ARMII::VecSize.

Referenced by llvm::SIInstrInfo::getIndirectRegWriteMovRelPseudo().

◆ getIndirectVGPRWriteMovRelPseudoOpc()

static unsigned getIndirectVGPRWriteMovRelPseudoOpc ( unsigned VecSize )

static

Definition at line 1331 of file SIInstrInfo.cpp.

References llvm_unreachable, and llvm::ARMII::VecSize.

Referenced by llvm::SIInstrInfo::getIndirectRegWriteMovRelPseudo().

◆ getNumOperandsNoGlue()

static unsigned getNumOperandsNoGlue ( SDNode * Node )

static

Definition at line 74 of file SIInstrInfo.cpp.

Referenced by llvm::SIInstrInfo::areLoadsFromSameBasePtr().

◆ getRegOrUndef()

static TargetInstrInfo::RegSubRegPair getRegOrUndef ( const MachineOperand & RegOpnd )

static

Definition at line 7996 of file SIInstrInfo.cpp.

References assert(), llvm::getRegSubRegPair(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isUndef().

Referenced by followSubRegDef(), and llvm::getRegSequenceSubReg().

◆ getSGPRSpillRestoreOpcode()

static unsigned getSGPRSpillRestoreOpcode ( unsigned Size )

static

Definition at line 1573 of file SIInstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SIInstrInfo::loadRegFromStackSlot().

◆ getSGPRSpillSaveOpcode()

static unsigned getSGPRSpillSaveOpcode ( unsigned Size )

static

Definition at line 1406 of file SIInstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SIInstrInfo::storeRegToStackSlot().

◆ getVGPRSpillRestoreOpcode()

static unsigned getVGPRSpillRestoreOpcode ( unsigned Size )

static

Definition at line 1600 of file SIInstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SIInstrInfo::loadRegFromStackSlot().

◆ getVGPRSpillSaveOpcode()

static unsigned getVGPRSpillSaveOpcode ( unsigned Size )

static

Definition at line 1433 of file SIInstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SIInstrInfo::storeRegToStackSlot().

◆ indirectCopyToAGPR()

static void indirectCopyToAGPR	(	const SIInstrInfo &	TII,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		const DebugLoc &	DL,
		MCRegister	DestReg,
		MCRegister	SrcReg,
		bool	KillSrc,
		RegScavenger &	RS,
		Register	ImpDefSuperReg = `Register()`,
		Register	ImpUseSuperReg = `Register()`
	)

static

Handle copying from SGPR to AGPR, or from AGPR to AGPR on GFX908.

It is not possible to have a direct copy in these cases on GFX908, so an intermediate VGPR copy is required.

Definition at line 553 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::MachineBasicBlock::begin(), Builder, llvm::BuildMI(), contains(), llvm::tgtok::Def, llvm::RegState::Define, DL, E, llvm::RegScavenger::enterBasicBlock(), llvm::RegScavenger::FindUnusedReg(), llvm::RegScavenger::forward(), llvm::SIRegisterInfo::getHWRegIndex(), llvm::MachineFunction::getInfo(), llvm::getKillRegState(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::getRegPressureLimit(), I, llvm::RegState::Implicit, llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::MachineRegisterInfo::isReserved(), llvm::RegState::Kill, MBB, MI, llvm::RegScavenger::scavengeRegister(), llvm::MachineOperand::setIsKill(), llvm::RegScavenger::setRegUsed(), and TII.

Referenced by llvm::SIInstrInfo::copyPhysReg().

◆ isStride64()

static bool isStride64 ( unsigned Opc )

static

Definition at line 282 of file SIInstrInfo.cpp.

Referenced by llvm::SIInstrInfo::getMemOperandsWithOffsetWidth().

◆ isSubRegOf()

static bool isSubRegOf	(	const SIRegisterInfo &	TRI,
		const MachineOperand &	SuperVec,
		const MachineOperand &	SubReg
	)

static

Definition at line 3984 of file SIInstrInfo.cpp.

References llvm::MachineOperand::getReg(), llvm::MCRegisterInfo::isSubRegister(), SubReg, and TRI.

Referenced by llvm::SIInstrInfo::verifyInstruction().

◆ loadSRsrcFromVGPR()

static MachineBasicBlock* loadSRsrcFromVGPR	(	const SIInstrInfo &	TII,
		MachineInstr &	MI,
		MachineOperand &	Rsrc,
		MachineDominatorTree *	MDT,
		MachineBasicBlock::iterator	Begin = `nullptr`,
		MachineBasicBlock::iterator	End = `nullptr`
	)

static

Definition at line 5591 of file SIInstrInfo.cpp.

Referenced by llvm::SIInstrInfo::legalizeOperands().

◆ memOpsHaveSameBaseOperands()

static bool memOpsHaveSameBaseOperands	(	ArrayRef< const MachineOperand * >	BaseOps1,
		ArrayRef< const MachineOperand * >	BaseOps2
	)

static

Definition at line 3140 of file SIInstrInfo.cpp.

References E, I, and llvm::ArrayRef< T >::size().

◆ memOpsHaveSameBasePtr()

static bool memOpsHaveSameBasePtr	(	const MachineInstr &	MI1,
		ArrayRef< const MachineOperand * >	BaseOps1,
		const MachineInstr &	MI2,
		ArrayRef< const MachineOperand * >	BaseOps2
	)

static

Definition at line 450 of file SIInstrInfo.cpp.

References llvm::ArrayRef< T >::front(), llvm::getUnderlyingObject(), llvm::MachineInstr::hasOneMemOperand(), llvm::MachineOperand::isIdenticalTo(), and llvm::MachineInstr::memoperands_begin().

Referenced by llvm::SIInstrInfo::shouldClusterMemOps().

◆ nodesHaveSameOperandValue()

static bool nodesHaveSameOperandValue	(	SDNode *	N0,
		SDNode *	N1,
		unsigned	OpName
	)

static

Returns true if both nodes have the same value for the given operand Op, or if both nodes do not have this operand.

Definition at line 83 of file SIInstrInfo.cpp.

References llvm::SDNode::getMachineOpcode(), llvm::AMDGPU::getNamedOperandIdx(), and llvm::SDNode::getOperand().

Referenced by llvm::SIInstrInfo::areLoadsFromSameBasePtr().

◆ offsetsDoNotOverlap()

static bool offsetsDoNotOverlap	(	int	WidthA,
		int	OffsetA,
		int	WidthB,
		int	OffsetB
	)

static

Definition at line 3151 of file SIInstrInfo.cpp.

◆ preserveCondRegFlags()

static void preserveCondRegFlags	(	MachineOperand &	CondReg,
		const MachineOperand &	OrigCond
	)

static

Definition at line 2656 of file SIInstrInfo.cpp.

References llvm::MachineOperand::isKill(), llvm::MachineOperand::isUndef(), llvm::MachineOperand::setIsKill(), and llvm::MachineOperand::setIsUndef().

Referenced by llvm::SIInstrInfo::insertBranch(), and llvm::SIInstrInfo::insertSelect().

◆ reportIllegalCopy()

static void reportIllegalCopy	(	const SIInstrInfo *	TII,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		const DebugLoc &	DL,
		MCRegister	DestReg,
		MCRegister	SrcReg,
		bool	KillSrc,
		const char *	Msg = `"illegal SGPR to VGPR copy"`
	)

static

Definition at line 536 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::LLVMContext::diagnose(), DL, llvm::DS_Error, llvm::Function::getContext(), llvm::MachineFunction::getFunction(), llvm::getKillRegState(), llvm::MachineBasicBlock::getParent(), MBB, MI, llvm::AMDGPU::SendMsg::Msg, and TII.

Referenced by llvm::SIInstrInfo::copyPhysReg().

◆ resultDependsOnExec()

static bool resultDependsOnExec ( const MachineInstr & MI )

static

Definition at line 131 of file SIInstrInfo.cpp.

References llvm::Register::isVirtual(), MI, MRI, and llvm::MachineRegisterInfo::use_nodbg_instructions().

Referenced by llvm::SIInstrInfo::isIgnorableUse().

◆ shouldReadExec()

static bool shouldReadExec ( const MachineInstr & MI )

static

Definition at line 3964 of file SIInstrInfo.cpp.

References llvm::SIInstrInfo::isSALU(), llvm::SIInstrInfo::isSMRD(), llvm::SIInstrInfo::isVALU(), and MI.

Referenced by llvm::SIInstrInfo::verifyInstruction().

◆ subtargetEncodingFamily()

static SIEncodingFamily subtargetEncodingFamily ( const GCNSubtarget & ST )

static

Definition at line 7895 of file SIInstrInfo.cpp.

References llvm::AMDGPUSubtarget::GFX10, GFX10, llvm::AMDGPUSubtarget::GFX11, GFX11, llvm::AMDGPUSubtarget::GFX9, llvm_unreachable, llvm::AMDGPUSubtarget::SEA_ISLANDS, SI, llvm::AMDGPUSubtarget::SOUTHERN_ISLANDS, VI, and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.

Referenced by llvm::SIInstrInfo::pseudoToMCOpcode().

◆ swapRegAndNonRegOperand()

static MachineInstr* swapRegAndNonRegOperand	(	MachineInstr &	MI,
		MachineOperand &	RegOp,
		MachineOperand &	NonRegOp
	)

static

Definition at line 2258 of file SIInstrInfo.cpp.

Referenced by llvm::SIInstrInfo::commuteInstructionImpl().

◆ updateLiveVariables()

static void updateLiveVariables	(	LiveVariables *	LV,
		MachineInstr &	MI,
		MachineInstr &	NewMI
	)

static

Definition at line 3256 of file SIInstrInfo.cpp.

References I, MI, and llvm::LiveVariables::replaceKillInstruction().

Referenced by llvm::SIInstrInfo::convertToThreeAddress().

Variable Documentation

◆ BranchOffsetBits

cl::opt<unsigned> BranchOffsetBits("amdgpu-s-branch-bits", cl::ReallyHidden, cl::init(16), cl::desc("Restrict range of branch instructions (DEBUG)"))

static

Referenced by llvm::SIInstrInfo::isBranchOffsetInRange().

◆ Fix16BitCopies

cl::opt<bool> Fix16BitCopies("amdgpu-fix-16-bit-physreg-copies", cl::desc("Fix copies between 32 and 16 bit registers by extending to 32 bit"), cl::init(true), cl::ReallyHidden)

static

Referenced by llvm::SIInstrInfo::copyPhysReg().

◆ ModifierOpNames

constexpr unsigned ModifierOpNames[]

staticconstexpr

Initial value:

= {
    AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src1_modifiers,
    AMDGPU::OpName::src2_modifiers, AMDGPU::OpName::clamp,
    AMDGPU::OpName::omod,           AMDGPU::OpName::op_sel}

Definition at line 2904 of file SIInstrInfo.cpp.

Referenced by llvm::SIInstrInfo::hasAnyModifiersSet(), and llvm::SIInstrInfo::removeModOperands().

Namespaces

Macros

Enumerations

Functions

Variables

Detailed Description

Macro Definition Documentation

◆ DEBUG_TYPE

◆ GET_D16ImageDimIntrinsics_IMPL

◆ GET_ImageDimIntrinsicTable_IMPL

◆ GET_INSTRINFO_CTOR_DTOR

◆ GET_RsrcIntrinsics_IMPL

Enumeration Type Documentation

◆ SIEncodingFamily

Function Documentation

◆ adjustAllocatableRegClass()

◆ changesVGPRIndexingMode()

◆ compareMachineOp()

◆ copyFlagsToImplicitVCC()

◆ emitLoadSRsrcFromVGPRLoop()

◆ expandSGPRCopy()

◆ extractRsrcPtr()

◆ findImplicitSGPRRead()

◆ followSubRegDef()

◆ getAGPRSpillRestoreOpcode()

◆ getAGPRSpillSaveOpcode()

◆ getAVSpillRestoreOpcode()

◆ getAVSpillSaveOpcode()

◆ getFoldableImm() [1/2]

◆ getFoldableImm() [2/2]

◆ getIndirectSGPRWriteMovRelPseudo32()

◆ getIndirectSGPRWriteMovRelPseudo64()

◆ getIndirectVGPRWriteMovRelPseudoOpc()

◆ getNumOperandsNoGlue()

◆ getRegOrUndef()

◆ getSGPRSpillRestoreOpcode()

◆ getSGPRSpillSaveOpcode()

◆ getVGPRSpillRestoreOpcode()

◆ getVGPRSpillSaveOpcode()

◆ indirectCopyToAGPR()

◆ isStride64()

◆ isSubRegOf()

◆ loadSRsrcFromVGPR()

◆ memOpsHaveSameBaseOperands()

◆ memOpsHaveSameBasePtr()

◆ nodesHaveSameOperandValue()

◆ offsetsDoNotOverlap()

◆ preserveCondRegFlags()

◆ reportIllegalCopy()

◆ resultDependsOnExec()

◆ shouldReadExec()

◆ subtargetEncodingFamily()

◆ swapRegAndNonRegOperand()

◆ updateLiveVariables()

Variable Documentation

◆ BranchOffsetBits

◆ Fix16BitCopies

◆ ModifierOpNames