LLVM 17.0.0git
SIInstrInfo.h
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1//===- SIInstrInfo.h - SI Instruction Info Interface ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Interface definition for SIInstrInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
15#define LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
16
17#include "AMDGPUMIRFormatter.h"
19#include "SIRegisterInfo.h"
21#include "llvm/ADT/SetVector.h"
24
25#define GET_INSTRINFO_HEADER
26#include "AMDGPUGenInstrInfo.inc"
27
28namespace llvm {
29
30class APInt;
31class GCNSubtarget;
32class LiveVariables;
33class MachineDominatorTree;
34class MachineRegisterInfo;
35class RegScavenger;
36class TargetRegisterClass;
37class ScheduleHazardRecognizer;
38
39/// Mark the MMO of a uniform load if there are no potentially clobbering stores
40/// on any path from the start of an entry function to this load.
43
44class SIInstrInfo final : public AMDGPUGenInstrInfo {
45private:
46 const SIRegisterInfo RI;
47 const GCNSubtarget &ST;
48 TargetSchedModel SchedModel;
49 mutable std::unique_ptr<AMDGPUMIRFormatter> Formatter;
50
51 // The inverse predicate should have the negative value.
52 enum BranchPredicate {
53 INVALID_BR = 0,
54 SCC_TRUE = 1,
55 SCC_FALSE = -1,
56 VCCNZ = 2,
57 VCCZ = -2,
58 EXECNZ = -3,
59 EXECZ = 3
60 };
61
63
64 static unsigned getBranchOpcode(BranchPredicate Cond);
65 static BranchPredicate getBranchPredicate(unsigned Opcode);
66
67public:
70 MachineOperand &SuperReg,
71 const TargetRegisterClass *SuperRC,
72 unsigned SubIdx,
73 const TargetRegisterClass *SubRC) const;
76 MachineOperand &SuperReg,
77 const TargetRegisterClass *SuperRC,
78 unsigned SubIdx,
79 const TargetRegisterClass *SubRC) const;
80private:
81 void swapOperands(MachineInstr &Inst) const;
82
83 std::pair<bool, MachineBasicBlock *>
84 moveScalarAddSub(SetVectorType &Worklist, MachineInstr &Inst,
85 MachineDominatorTree *MDT = nullptr) const;
86
87 void lowerSelect(SetVectorType &Worklist, MachineInstr &Inst,
88 MachineDominatorTree *MDT = nullptr) const;
89
90 void lowerScalarAbs(SetVectorType &Worklist,
91 MachineInstr &Inst) const;
92
93 void lowerScalarXnor(SetVectorType &Worklist,
94 MachineInstr &Inst) const;
95
96 void splitScalarNotBinop(SetVectorType &Worklist,
97 MachineInstr &Inst,
98 unsigned Opcode) const;
99
100 void splitScalarBinOpN2(SetVectorType &Worklist,
101 MachineInstr &Inst,
102 unsigned Opcode) const;
103
104 void splitScalar64BitUnaryOp(SetVectorType &Worklist,
105 MachineInstr &Inst, unsigned Opcode,
106 bool Swap = false) const;
107
108 void splitScalar64BitAddSub(SetVectorType &Worklist, MachineInstr &Inst,
109 MachineDominatorTree *MDT = nullptr) const;
110
111 void splitScalar64BitBinaryOp(SetVectorType &Worklist, MachineInstr &Inst,
112 unsigned Opcode,
113 MachineDominatorTree *MDT = nullptr) const;
114
115 void splitScalar64BitXnor(SetVectorType &Worklist, MachineInstr &Inst,
116 MachineDominatorTree *MDT = nullptr) const;
117
118 void splitScalar64BitBCNT(SetVectorType &Worklist,
119 MachineInstr &Inst) const;
120 void splitScalar64BitBFE(SetVectorType &Worklist,
121 MachineInstr &Inst) const;
122 void movePackToVALU(SetVectorType &Worklist,
124 MachineInstr &Inst) const;
125
126 void addUsersToMoveToVALUWorklist(Register Reg, MachineRegisterInfo &MRI,
127 SetVectorType &Worklist) const;
128
129 void addSCCDefUsersToVALUWorklist(MachineOperand &Op,
130 MachineInstr &SCCDefInst,
131 SetVectorType &Worklist,
132 Register NewCond = Register()) const;
133 void addSCCDefsToVALUWorklist(MachineInstr *SCCUseInst,
134 SetVectorType &Worklist) const;
135
136 const TargetRegisterClass *
137 getDestEquivalentVGPRClass(const MachineInstr &Inst) const;
138
139 bool checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
140 const MachineInstr &MIb) const;
141
142 Register findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
143
144protected:
146 MachineOperand &Src0, unsigned Src0OpName,
147 MachineOperand &Src1, unsigned Src1OpName) const;
148
150 unsigned OpIdx0,
151 unsigned OpIdx1) const override;
152
153public:
155 MO_MASK = 0xf,
156
158 // MO_GOTPCREL -> symbol@GOTPCREL -> R_AMDGPU_GOTPCREL.
160 // MO_GOTPCREL32_LO -> symbol@gotpcrel32@lo -> R_AMDGPU_GOTPCREL32_LO.
163 // MO_GOTPCREL32_HI -> symbol@gotpcrel32@hi -> R_AMDGPU_GOTPCREL32_HI.
165 // MO_REL32_LO -> symbol@rel32@lo -> R_AMDGPU_REL32_LO.
168 // MO_REL32_HI -> symbol@rel32@hi -> R_AMDGPU_REL32_HI.
170
172
175 };
176
177 explicit SIInstrInfo(const GCNSubtarget &ST);
178
180 return RI;
181 }
182
183 const GCNSubtarget &getSubtarget() const {
184 return ST;
185 }
186
187 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
188
189 bool isIgnorableUse(const MachineOperand &MO) const override;
190
191 bool areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, int64_t &Offset0,
192 int64_t &Offset1) const override;
193
195 const MachineInstr &LdSt,
197 bool &OffsetIsScalable, unsigned &Width,
198 const TargetRegisterInfo *TRI) const final;
199
202 unsigned NumLoads, unsigned NumBytes) const override;
203
204 bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
205 int64_t Offset1, unsigned NumLoads) const override;
206
208 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
209 bool KillSrc) const override;
210
213 Register DestReg, int64_t Value) const;
214
216 unsigned Size) const;
217
220 Register SrcReg, int Value) const;
221
224 Register SrcReg, int Value) const;
225
228 bool isKill, int FrameIndex,
229 const TargetRegisterClass *RC,
230 const TargetRegisterInfo *TRI,
231 Register VReg) const override;
232
235 int FrameIndex, const TargetRegisterClass *RC,
236 const TargetRegisterInfo *TRI,
237 Register VReg) const override;
238
239 bool expandPostRAPseudo(MachineInstr &MI) const override;
240
241 // Splits a V_MOV_B64_DPP_PSEUDO opcode into a pair of v_mov_b32_dpp
242 // instructions. Returns a pair of generated instructions.
243 // Can split either post-RA with physical registers or pre-RA with
244 // virtual registers. In latter case IR needs to be in SSA form and
245 // and a REG_SEQUENCE is produced to define original register.
246 std::pair<MachineInstr*, MachineInstr*>
248
249 // Returns an opcode that can be used to move a value to a \p DstRC
250 // register. If there is no hardware instruction that can store to \p
251 // DstRC, then AMDGPU::COPY is returned.
252 unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
253
254 const MCInstrDesc &getIndirectRegWriteMovRelPseudo(unsigned VecSize,
255 unsigned EltSize,
256 bool IsSGPR) const;
257
258 const MCInstrDesc &getIndirectGPRIDXPseudo(unsigned VecSize,
259 bool IsIndirectSrc) const;
261 int commuteOpcode(unsigned Opc) const;
262
264 inline int commuteOpcode(const MachineInstr &MI) const {
265 return commuteOpcode(MI.getOpcode());
266 }
267
268 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx0,
269 unsigned &SrcOpIdx1) const override;
270
271 bool findCommutedOpIndices(const MCInstrDesc &Desc, unsigned &SrcOpIdx0,
272 unsigned &SrcOpIdx1) const;
273
274 bool isBranchOffsetInRange(unsigned BranchOpc,
275 int64_t BrOffset) const override;
276
277 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
278
279 /// Return whether the block terminate with divergent branch.
280 /// Note this only work before lowering the pseudo control flow instructions.
281 bool hasDivergentBranch(const MachineBasicBlock *MBB) const;
282
284 MachineBasicBlock &NewDestBB,
285 MachineBasicBlock &RestoreBB, const DebugLoc &DL,
286 int64_t BrOffset, RegScavenger *RS) const override;
287
291 MachineBasicBlock *&FBB,
293 bool AllowModify) const;
294
296 MachineBasicBlock *&FBB,
298 bool AllowModify = false) const override;
299
301 int *BytesRemoved = nullptr) const override;
302
305 const DebugLoc &DL,
306 int *BytesAdded = nullptr) const override;
307
309 SmallVectorImpl<MachineOperand> &Cond) const override;
310
313 Register TrueReg, Register FalseReg, int &CondCycles,
314 int &TrueCycles, int &FalseCycles) const override;
315
319 Register TrueReg, Register FalseReg) const override;
320
324 Register TrueReg, Register FalseReg) const;
325
326 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
327 Register &SrcReg2, int64_t &CmpMask,
328 int64_t &CmpValue) const override;
329
330 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
331 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
332 const MachineRegisterInfo *MRI) const override;
333
334 bool
336 const MachineInstr &MIb) const override;
337
338 static bool isFoldableCopy(const MachineInstr &MI);
339
340 void removeModOperands(MachineInstr &MI) const;
341
343 MachineRegisterInfo *MRI) const final;
344
345 unsigned getMachineCSELookAheadLimit() const override { return 500; }
346
348 LiveIntervals *LIS) const override;
349
351 const MachineBasicBlock *MBB,
352 const MachineFunction &MF) const override;
353
354 static bool isSALU(const MachineInstr &MI) {
355 return MI.getDesc().TSFlags & SIInstrFlags::SALU;
356 }
357
358 bool isSALU(uint16_t Opcode) const {
359 return get(Opcode).TSFlags & SIInstrFlags::SALU;
360 }
361
362 static bool isVALU(const MachineInstr &MI) {
363 return MI.getDesc().TSFlags & SIInstrFlags::VALU;
364 }
365
366 bool isVALU(uint16_t Opcode) const {
367 return get(Opcode).TSFlags & SIInstrFlags::VALU;
368 }
369
370 static bool isVMEM(const MachineInstr &MI) {
371 return isMUBUF(MI) || isMTBUF(MI) || isMIMG(MI);
372 }
373
374 bool isVMEM(uint16_t Opcode) const {
375 return isMUBUF(Opcode) || isMTBUF(Opcode) || isMIMG(Opcode);
376 }
377
378 static bool isSOP1(const MachineInstr &MI) {
379 return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
380 }
381
382 bool isSOP1(uint16_t Opcode) const {
383 return get(Opcode).TSFlags & SIInstrFlags::SOP1;
384 }
385
386 static bool isSOP2(const MachineInstr &MI) {
387 return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
388 }
389
390 bool isSOP2(uint16_t Opcode) const {
391 return get(Opcode).TSFlags & SIInstrFlags::SOP2;
392 }
393
394 static bool isSOPC(const MachineInstr &MI) {
395 return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
396 }
397
398 bool isSOPC(uint16_t Opcode) const {
399 return get(Opcode).TSFlags & SIInstrFlags::SOPC;
400 }
401
402 static bool isSOPK(const MachineInstr &MI) {
403 return MI.getDesc().TSFlags & SIInstrFlags::SOPK;
404 }
405
406 bool isSOPK(uint16_t Opcode) const {
407 return get(Opcode).TSFlags & SIInstrFlags::SOPK;
408 }
409
410 static bool isSOPP(const MachineInstr &MI) {
411 return MI.getDesc().TSFlags & SIInstrFlags::SOPP;
412 }
413
414 bool isSOPP(uint16_t Opcode) const {
415 return get(Opcode).TSFlags & SIInstrFlags::SOPP;
416 }
417
418 static bool isPacked(const MachineInstr &MI) {
419 return MI.getDesc().TSFlags & SIInstrFlags::IsPacked;
420 }
421
422 bool isPacked(uint16_t Opcode) const {
423 return get(Opcode).TSFlags & SIInstrFlags::IsPacked;
424 }
425
426 static bool isVOP1(const MachineInstr &MI) {
427 return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
428 }
429
430 bool isVOP1(uint16_t Opcode) const {
431 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
432 }
433
434 static bool isVOP2(const MachineInstr &MI) {
435 return MI.getDesc().TSFlags & SIInstrFlags::VOP2;
436 }
437
438 bool isVOP2(uint16_t Opcode) const {
439 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
440 }
441
442 static bool isVOP3(const MachineInstr &MI) {
443 return MI.getDesc().TSFlags & SIInstrFlags::VOP3;
444 }
445
446 bool isVOP3(uint16_t Opcode) const {
447 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
448 }
449
450 static bool isSDWA(const MachineInstr &MI) {
451 return MI.getDesc().TSFlags & SIInstrFlags::SDWA;
452 }
453
454 bool isSDWA(uint16_t Opcode) const {
455 return get(Opcode).TSFlags & SIInstrFlags::SDWA;
456 }
457
458 static bool isVOPC(const MachineInstr &MI) {
459 return MI.getDesc().TSFlags & SIInstrFlags::VOPC;
460 }
461
462 bool isVOPC(uint16_t Opcode) const {
463 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
464 }
465
466 static bool isMUBUF(const MachineInstr &MI) {
467 return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;
468 }
469
470 bool isMUBUF(uint16_t Opcode) const {
471 return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
472 }
473
474 static bool isMTBUF(const MachineInstr &MI) {
475 return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;
476 }
477
478 bool isMTBUF(uint16_t Opcode) const {
479 return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
480 }
481
482 static bool isSMRD(const MachineInstr &MI) {
483 return MI.getDesc().TSFlags & SIInstrFlags::SMRD;
484 }
485
486 bool isSMRD(uint16_t Opcode) const {
487 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
488 }
489
490 bool isBufferSMRD(const MachineInstr &MI) const;
491
492 static bool isDS(const MachineInstr &MI) {
493 return MI.getDesc().TSFlags & SIInstrFlags::DS;
494 }
495
496 bool isDS(uint16_t Opcode) const {
497 return get(Opcode).TSFlags & SIInstrFlags::DS;
498 }
499
500 bool isAlwaysGDS(uint16_t Opcode) const;
501
502 static bool isMIMG(const MachineInstr &MI) {
503 return MI.getDesc().TSFlags & SIInstrFlags::MIMG;
504 }
505
506 bool isMIMG(uint16_t Opcode) const {
507 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
508 }
509
510 static bool isGather4(const MachineInstr &MI) {
511 return MI.getDesc().TSFlags & SIInstrFlags::Gather4;
512 }
513
514 bool isGather4(uint16_t Opcode) const {
515 return get(Opcode).TSFlags & SIInstrFlags::Gather4;
516 }
517
518 static bool isFLAT(const MachineInstr &MI) {
519 return MI.getDesc().TSFlags & SIInstrFlags::FLAT;
520 }
521
522 // Is a FLAT encoded instruction which accesses a specific segment,
523 // i.e. global_* or scratch_*.
525 auto Flags = MI.getDesc().TSFlags;
527 }
528
529 bool isSegmentSpecificFLAT(uint16_t Opcode) const {
530 auto Flags = get(Opcode).TSFlags;
532 }
533
534 static bool isFLATGlobal(const MachineInstr &MI) {
535 return MI.getDesc().TSFlags & SIInstrFlags::FlatGlobal;
536 }
537
538 bool isFLATGlobal(uint16_t Opcode) const {
539 return get(Opcode).TSFlags & SIInstrFlags::FlatGlobal;
540 }
541
542 static bool isFLATScratch(const MachineInstr &MI) {
543 return MI.getDesc().TSFlags & SIInstrFlags::FlatScratch;
544 }
545
546 bool isFLATScratch(uint16_t Opcode) const {
547 return get(Opcode).TSFlags & SIInstrFlags::FlatScratch;
548 }
549
550 // Any FLAT encoded instruction, including global_* and scratch_*.
551 bool isFLAT(uint16_t Opcode) const {
552 return get(Opcode).TSFlags & SIInstrFlags::FLAT;
553 }
554
555 static bool isEXP(const MachineInstr &MI) {
556 return MI.getDesc().TSFlags & SIInstrFlags::EXP;
557 }
558
560 if (!isEXP(MI))
561 return false;
562 unsigned Target = MI.getOperand(0).getImm();
565 }
566
567 bool isEXP(uint16_t Opcode) const {
568 return get(Opcode).TSFlags & SIInstrFlags::EXP;
569 }
570
571 static bool isAtomicNoRet(const MachineInstr &MI) {
572 return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicNoRet;
573 }
574
575 bool isAtomicNoRet(uint16_t Opcode) const {
576 return get(Opcode).TSFlags & SIInstrFlags::IsAtomicNoRet;
577 }
578
579 static bool isAtomicRet(const MachineInstr &MI) {
580 return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicRet;
581 }
582
583 bool isAtomicRet(uint16_t Opcode) const {
584 return get(Opcode).TSFlags & SIInstrFlags::IsAtomicRet;
585 }
586
587 static bool isAtomic(const MachineInstr &MI) {
588 return MI.getDesc().TSFlags & (SIInstrFlags::IsAtomicRet |
590 }
591
592 bool isAtomic(uint16_t Opcode) const {
593 return get(Opcode).TSFlags & (SIInstrFlags::IsAtomicRet |
595 }
596
597 static bool isWQM(const MachineInstr &MI) {
598 return MI.getDesc().TSFlags & SIInstrFlags::WQM;
599 }
600
601 bool isWQM(uint16_t Opcode) const {
602 return get(Opcode).TSFlags & SIInstrFlags::WQM;
603 }
604
605 static bool isDisableWQM(const MachineInstr &MI) {
606 return MI.getDesc().TSFlags & SIInstrFlags::DisableWQM;
607 }
608
609 bool isDisableWQM(uint16_t Opcode) const {
610 return get(Opcode).TSFlags & SIInstrFlags::DisableWQM;
611 }
612
613 static bool isVGPRSpill(const MachineInstr &MI) {
614 return MI.getDesc().TSFlags & SIInstrFlags::VGPRSpill;
615 }
616
617 bool isVGPRSpill(uint16_t Opcode) const {
618 return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;
619 }
620
621 static bool isSGPRSpill(const MachineInstr &MI) {
622 return MI.getDesc().TSFlags & SIInstrFlags::SGPRSpill;
623 }
624
625 bool isSGPRSpill(uint16_t Opcode) const {
626 return get(Opcode).TSFlags & SIInstrFlags::SGPRSpill;
627 }
628
629 static bool isDPP(const MachineInstr &MI) {
630 return MI.getDesc().TSFlags & SIInstrFlags::DPP;
631 }
632
633 bool isDPP(uint16_t Opcode) const {
634 return get(Opcode).TSFlags & SIInstrFlags::DPP;
635 }
636
637 static bool isTRANS(const MachineInstr &MI) {
638 return MI.getDesc().TSFlags & SIInstrFlags::TRANS;
639 }
640
641 bool isTRANS(uint16_t Opcode) const {
642 return get(Opcode).TSFlags & SIInstrFlags::TRANS;
643 }
644
645 static bool isVOP3P(const MachineInstr &MI) {
646 return MI.getDesc().TSFlags & SIInstrFlags::VOP3P;
647 }
648
649 bool isVOP3P(uint16_t Opcode) const {
650 return get(Opcode).TSFlags & SIInstrFlags::VOP3P;
651 }
652
653 static bool isVINTRP(const MachineInstr &MI) {
654 return MI.getDesc().TSFlags & SIInstrFlags::VINTRP;
655 }
656
657 bool isVINTRP(uint16_t Opcode) const {
658 return get(Opcode).TSFlags & SIInstrFlags::VINTRP;
659 }
660
661 static bool isMAI(const MachineInstr &MI) {
662 return MI.getDesc().TSFlags & SIInstrFlags::IsMAI;
663 }
664
665 bool isMAI(uint16_t Opcode) const {
666 return get(Opcode).TSFlags & SIInstrFlags::IsMAI;
667 }
668
669 static bool isMFMA(const MachineInstr &MI) {
670 return isMAI(MI) && MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64 &&
671 MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64;
672 }
673
674 static bool isDOT(const MachineInstr &MI) {
675 return MI.getDesc().TSFlags & SIInstrFlags::IsDOT;
676 }
677
678 static bool isWMMA(const MachineInstr &MI) {
679 return MI.getDesc().TSFlags & SIInstrFlags::IsWMMA;
680 }
681
682 bool isWMMA(uint16_t Opcode) const {
683 return get(Opcode).TSFlags & SIInstrFlags::IsWMMA;
684 }
685
686 static bool isMFMAorWMMA(const MachineInstr &MI) {
687 return isMFMA(MI) || isWMMA(MI);
688 }
689
690 bool isDOT(uint16_t Opcode) const {
691 return get(Opcode).TSFlags & SIInstrFlags::IsDOT;
692 }
693
694 static bool isLDSDIR(const MachineInstr &MI) {
695 return MI.getDesc().TSFlags & SIInstrFlags::LDSDIR;
696 }
697
698 bool isLDSDIR(uint16_t Opcode) const {
699 return get(Opcode).TSFlags & SIInstrFlags::LDSDIR;
700 }
701
702 static bool isVINTERP(const MachineInstr &MI) {
703 return MI.getDesc().TSFlags & SIInstrFlags::VINTERP;
704 }
705
706 bool isVINTERP(uint16_t Opcode) const {
707 return get(Opcode).TSFlags & SIInstrFlags::VINTERP;
708 }
709
710 static bool isScalarUnit(const MachineInstr &MI) {
711 return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD);
712 }
713
714 static bool usesVM_CNT(const MachineInstr &MI) {
715 return MI.getDesc().TSFlags & SIInstrFlags::VM_CNT;
716 }
717
718 static bool usesLGKM_CNT(const MachineInstr &MI) {
719 return MI.getDesc().TSFlags & SIInstrFlags::LGKM_CNT;
720 }
721
722 static bool sopkIsZext(const MachineInstr &MI) {
723 return MI.getDesc().TSFlags & SIInstrFlags::SOPK_ZEXT;
724 }
725
726 bool sopkIsZext(uint16_t Opcode) const {
727 return get(Opcode).TSFlags & SIInstrFlags::SOPK_ZEXT;
728 }
729
730 /// \returns true if this is an s_store_dword* instruction. This is more
731 /// specific than isSMEM && mayStore.
732 static bool isScalarStore(const MachineInstr &MI) {
733 return MI.getDesc().TSFlags & SIInstrFlags::SCALAR_STORE;
734 }
735
736 bool isScalarStore(uint16_t Opcode) const {
737 return get(Opcode).TSFlags & SIInstrFlags::SCALAR_STORE;
738 }
739
740 static bool isFixedSize(const MachineInstr &MI) {
741 return MI.getDesc().TSFlags & SIInstrFlags::FIXED_SIZE;
742 }
743
744 bool isFixedSize(uint16_t Opcode) const {
745 return get(Opcode).TSFlags & SIInstrFlags::FIXED_SIZE;
746 }
747
748 static bool hasFPClamp(const MachineInstr &MI) {
749 return MI.getDesc().TSFlags & SIInstrFlags::FPClamp;
750 }
751
752 bool hasFPClamp(uint16_t Opcode) const {
753 return get(Opcode).TSFlags & SIInstrFlags::FPClamp;
754 }
755
756 static bool hasIntClamp(const MachineInstr &MI) {
757 return MI.getDesc().TSFlags & SIInstrFlags::IntClamp;
758 }
759
761 const uint64_t ClampFlags = SIInstrFlags::FPClamp |
765 return MI.getDesc().TSFlags & ClampFlags;
766 }
767
768 static bool usesFPDPRounding(const MachineInstr &MI) {
769 return MI.getDesc().TSFlags & SIInstrFlags::FPDPRounding;
770 }
771
772 bool usesFPDPRounding(uint16_t Opcode) const {
773 return get(Opcode).TSFlags & SIInstrFlags::FPDPRounding;
774 }
775
776 static bool isFPAtomic(const MachineInstr &MI) {
777 return MI.getDesc().TSFlags & SIInstrFlags::FPAtomic;
778 }
779
780 bool isFPAtomic(uint16_t Opcode) const {
781 return get(Opcode).TSFlags & SIInstrFlags::FPAtomic;
782 }
783
785 return MI.getDesc().TSFlags & SIInstrFlags::TiedSourceNotRead;
786 }
787
788 bool doesNotReadTiedSource(uint16_t Opcode) const {
789 return get(Opcode).TSFlags & SIInstrFlags::TiedSourceNotRead;
790 }
791
792 bool isVGPRCopy(const MachineInstr &MI) const {
793 assert(MI.isCopy());
794 Register Dest = MI.getOperand(0).getReg();
795 const MachineFunction &MF = *MI.getParent()->getParent();
796 const MachineRegisterInfo &MRI = MF.getRegInfo();
797 return !RI.isSGPRReg(MRI, Dest);
798 }
799
800 bool hasVGPRUses(const MachineInstr &MI) const {
801 const MachineFunction &MF = *MI.getParent()->getParent();
802 const MachineRegisterInfo &MRI = MF.getRegInfo();
803 return llvm::any_of(MI.explicit_uses(),
804 [&MRI, this](const MachineOperand &MO) {
805 return MO.isReg() && RI.isVGPR(MRI, MO.getReg());});
806 }
807
808 /// Return true if the instruction modifies the mode register.q
809 static bool modifiesModeRegister(const MachineInstr &MI);
810
811 /// Whether we must prevent this instruction from executing with EXEC = 0.
813
814 /// Returns true if the instruction could potentially depend on the value of
815 /// exec. If false, exec dependencies may safely be ignored.
816 bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const;
817
818 bool isInlineConstant(const APInt &Imm) const;
819
820 bool isInlineConstant(const APFloat &Imm) const {
821 return isInlineConstant(Imm.bitcastToAPInt());
822 }
823
824 // Returns true if this non-register operand definitely does not need to be
825 // encoded as a 32-bit literal. Note that this function handles all kinds of
826 // operands, not just immediates.
827 //
828 // Some operands like FrameIndexes could resolve to an inline immediate value
829 // that will not require an additional 4-bytes; this function assumes that it
830 // will.
831 bool isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const;
832
834 const MCOperandInfo &OpInfo) const {
835 return isInlineConstant(MO, OpInfo.OperandType);
836 }
837
838 /// \p returns true if \p UseMO is substituted with \p DefMO in \p MI it would
839 /// be an inline immediate.
841 const MachineOperand &UseMO,
842 const MachineOperand &DefMO) const {
843 assert(UseMO.getParent() == &MI);
844 int OpIdx = UseMO.getOperandNo();
845 if (OpIdx >= MI.getDesc().NumOperands)
846 return false;
847
848 return isInlineConstant(DefMO, MI.getDesc().operands()[OpIdx]);
849 }
850
851 /// \p returns true if the operand \p OpIdx in \p MI is a valid inline
852 /// immediate.
853 bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const {
854 const MachineOperand &MO = MI.getOperand(OpIdx);
855 return isInlineConstant(MO, MI.getDesc().operands()[OpIdx].OperandType);
856 }
857
858 bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
859 const MachineOperand &MO) const {
860 if (OpIdx >= MI.getDesc().NumOperands)
861 return false;
862
863 if (MI.isCopy()) {
864 unsigned Size = getOpSize(MI, OpIdx);
865 assert(Size == 8 || Size == 4);
866
867 uint8_t OpType = (Size == 8) ?
869 return isInlineConstant(MO, OpType);
870 }
871
872 return isInlineConstant(MO, MI.getDesc().operands()[OpIdx].OperandType);
873 }
874
875 bool isInlineConstant(const MachineOperand &MO) const {
876 return isInlineConstant(*MO.getParent(), MO.getOperandNo());
877 }
878
879 bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
880 const MachineOperand &MO) const;
881
882 /// Return true if this 64-bit VALU instruction has a 32-bit encoding.
883 /// This function will return false if you pass it a 32-bit instruction.
884 bool hasVALU32BitEncoding(unsigned Opcode) const;
885
886 /// Returns true if this operand uses the constant bus.
888 const MachineOperand &MO,
889 const MCOperandInfo &OpInfo) const;
890
891 /// Return true if this instruction has any modifiers.
892 /// e.g. src[012]_mod, omod, clamp.
893 bool hasModifiers(unsigned Opcode) const;
894
895 bool hasModifiersSet(const MachineInstr &MI,
896 unsigned OpName) const;
897 bool hasAnyModifiersSet(const MachineInstr &MI) const;
898
899 bool canShrink(const MachineInstr &MI,
900 const MachineRegisterInfo &MRI) const;
901
903 unsigned NewOpcode) const;
904
906 StringRef &ErrInfo) const override;
907
908 unsigned getVALUOp(const MachineInstr &MI) const;
909
910 /// Return the correct register class for \p OpNo. For target-specific
911 /// instructions, this will return the register class that has been defined
912 /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
913 /// the register class of its machine operand.
914 /// to infer the correct register class base on the other operands.
916 unsigned OpNo) const;
917
918 /// Return the size in bytes of the operand OpNo on the given
919 // instruction opcode.
920 unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
921 const MCOperandInfo &OpInfo = get(Opcode).operands()[OpNo];
922
923 if (OpInfo.RegClass == -1) {
924 // If this is an immediate operand, this must be a 32-bit literal.
926 return 4;
927 }
928
929 return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;
930 }
931
932 /// This form should usually be preferred since it handles operands
933 /// with unknown register classes.
934 unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
935 const MachineOperand &MO = MI.getOperand(OpNo);
936 if (MO.isReg()) {
937 if (unsigned SubReg = MO.getSubReg()) {
938 return RI.getSubRegIdxSize(SubReg) / 8;
939 }
940 }
941 return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
942 }
943
944 /// Legalize the \p OpIndex operand of this instruction by inserting
945 /// a MOV. For example:
946 /// ADD_I32_e32 VGPR0, 15
947 /// to
948 /// MOV VGPR1, 15
949 /// ADD_I32_e32 VGPR0, VGPR1
950 ///
951 /// If the operand being legalized is a register, then a COPY will be used
952 /// instead of MOV.
953 void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const;
954
955 /// Check if \p MO is a legal operand if it was the \p OpIdx Operand
956 /// for \p MI.
957 bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
958 const MachineOperand *MO = nullptr) const;
959
960 /// Check if \p MO would be a valid operand for the given operand
961 /// definition \p OpInfo. Note this does not attempt to validate constant bus
962 /// restrictions (e.g. literal constant usage).
964 const MCOperandInfo &OpInfo,
965 const MachineOperand &MO) const;
966
967 /// Check if \p MO (a register operand) is a legal register for the
968 /// given operand description.
970 const MCOperandInfo &OpInfo,
971 const MachineOperand &MO) const;
972
973 /// Legalize operands in \p MI by either commuting it or inserting a
974 /// copy of src1.
976
977 /// Fix operands in \p MI to satisfy constant bus requirements.
979
980 /// Copy a value from a VGPR (\p SrcReg) to SGPR. This function can only
981 /// be used when it is know that the value in SrcReg is same across all
982 /// threads in the wave.
983 /// \returns The SGPR register that \p SrcReg was copied to.
985 MachineRegisterInfo &MRI) const;
986
989
992 const TargetRegisterClass *DstRC,
994 const DebugLoc &DL) const;
995
996 /// Legalize all operands in this instruction. This function may create new
997 /// instructions and control-flow around \p MI. If present, \p MDT is
998 /// updated.
999 /// \returns A new basic block that contains \p MI if new blocks were created.
1001 legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT = nullptr) const;
1002
1003 /// Change SADDR form of a FLAT \p Inst to its VADDR form if saddr operand
1004 /// was moved to VGPR. \returns true if succeeded.
1005 bool moveFlatAddrToVGPR(MachineInstr &Inst) const;
1006
1007 /// Replace this instruction's opcode with the equivalent VALU
1008 /// opcode. This function will also move the users of \p MI to the
1009 /// VALU if necessary. If present, \p MDT is updated.
1011 MachineDominatorTree *MDT = nullptr) const;
1012
1014 MachineBasicBlock::iterator MI) const override;
1015
1017 unsigned Quantity) const override;
1018
1019 void insertReturn(MachineBasicBlock &MBB) const;
1020 /// Return the number of wait states that result from executing this
1021 /// instruction.
1022 static unsigned getNumWaitStates(const MachineInstr &MI);
1023
1024 /// Returns the operand named \p Op. If \p MI does not have an
1025 /// operand named \c Op, this function returns nullptr.
1027 MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
1028
1031 unsigned OpName) const {
1032 return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
1033 }
1034
1035 /// Get required immediate operand
1036 int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const {
1037 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OpName);
1038 return MI.getOperand(Idx).getImm();
1039 }
1040
1043
1044 bool isLowLatencyInstruction(const MachineInstr &MI) const;
1045 bool isHighLatencyDef(int Opc) const override;
1046
1047 /// Return the descriptor of the target-specific machine instruction
1048 /// that corresponds to the specified pseudo or native opcode.
1049 const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const {
1050 return get(pseudoToMCOpcode(Opcode));
1051 }
1052
1053 unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1054 unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1055
1056 unsigned isLoadFromStackSlot(const MachineInstr &MI,
1057 int &FrameIndex) const override;
1058 unsigned isStoreToStackSlot(const MachineInstr &MI,
1059 int &FrameIndex) const override;
1060
1061 unsigned getInstBundleSize(const MachineInstr &MI) const;
1062 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
1063
1064 bool mayAccessFlatAddressSpace(const MachineInstr &MI) const;
1065
1066 bool isNonUniformBranchInstr(MachineInstr &Instr) const;
1067
1069 MachineBasicBlock *IfEnd) const;
1070
1072 MachineBasicBlock *LoopEnd) const;
1073
1074 std::pair<unsigned, unsigned>
1075 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
1076
1078 getSerializableTargetIndices() const override;
1079
1082
1085
1088 const ScheduleDAG *DAG) const override;
1089
1091 CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const override;
1092
1095 const ScheduleDAGMI *DAG) const override;
1096
1097 bool isBasicBlockPrologue(const MachineInstr &MI) const override;
1098
1101 const DebugLoc &DL, Register Src,
1102 Register Dst) const override;
1103
1106 const DebugLoc &DL, Register Src,
1107 unsigned SrcSubReg,
1108 Register Dst) const override;
1109
1110 bool isWave32() const;
1111
1112 /// Return a partially built integer add instruction without carry.
1113 /// Caller must add source operands.
1114 /// For pre-GFX9 it will generate unused carry destination operand.
1115 /// TODO: After GFX9 it should return a no-carry operation.
1118 const DebugLoc &DL,
1119 Register DestReg) const;
1120
1123 const DebugLoc &DL,
1124 Register DestReg,
1125 RegScavenger &RS) const;
1126
1127 static bool isKillTerminator(unsigned Opcode);
1128 const MCInstrDesc &getKillTerminatorFromPseudo(unsigned Opcode) const;
1129
1130 static bool isLegalMUBUFImmOffset(unsigned Imm) {
1131 return isUInt<12>(Imm);
1132 }
1133
1134 /// Returns if \p Offset is legal for the subtarget as the offset to a FLAT
1135 /// encoded instruction. If \p Signed, this is for an instruction that
1136 /// interprets the offset as signed.
1137 bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace,
1138 uint64_t FlatVariant) const;
1139
1140 /// Split \p COffsetVal into {immediate offset field, remainder offset}
1141 /// values.
1142 std::pair<int64_t, int64_t> splitFlatOffset(int64_t COffsetVal,
1143 unsigned AddrSpace,
1144 uint64_t FlatVariant) const;
1145
1146 /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
1147 /// Return -1 if the target-specific opcode for the pseudo instruction does
1148 /// not exist. If Opcode is not a pseudo instruction, this is identity.
1149 int pseudoToMCOpcode(int Opcode) const;
1150
1151 /// \brief Check if this instruction should only be used by assembler.
1152 /// Return true if this opcode should not be used by codegen.
1153 bool isAsmOnlyOpcode(int MCOp) const;
1154
1155 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
1156 const TargetRegisterInfo *TRI,
1157 const MachineFunction &MF)
1158 const override;
1159
1160 void fixImplicitOperands(MachineInstr &MI) const;
1161
1165 int FrameIndex,
1166 LiveIntervals *LIS = nullptr,
1167 VirtRegMap *VRM = nullptr) const override;
1168
1169 unsigned getInstrLatency(const InstrItineraryData *ItinData,
1170 const MachineInstr &MI,
1171 unsigned *PredCost = nullptr) const override;
1172
1174 getInstructionUniformity(const MachineInstr &MI) const override final;
1175
1178
1179 const MIRFormatter *getMIRFormatter() const override {
1180 if (!Formatter.get())
1181 Formatter = std::make_unique<AMDGPUMIRFormatter>();
1182 return Formatter.get();
1183 }
1184
1185 static unsigned getDSShaderTypeValue(const MachineFunction &MF);
1186
1187 const TargetSchedModel &getSchedModel() const { return SchedModel; }
1188
1189 // Enforce operand's \p OpName even alignment if required by target.
1190 // This is used if an operand is a 32 bit register but needs to be aligned
1191 // regardless.
1192 void enforceOperandRCAlignment(MachineInstr &MI, unsigned OpName) const;
1193};
1194
1195/// \brief Returns true if a reg:subreg pair P has a TRC class
1197 const TargetRegisterClass &TRC,
1199 auto *RC = MRI.getRegClass(P.Reg);
1200 if (!P.SubReg)
1201 return RC == &TRC;
1202 auto *TRI = MRI.getTargetRegisterInfo();
1203 return RC == TRI->getMatchingSuperRegClass(RC, &TRC, P.SubReg);
1204}
1205
1206/// \brief Create RegSubRegPair from a register MachineOperand
1207inline
1209 assert(O.isReg());
1210 return TargetInstrInfo::RegSubRegPair(O.getReg(), O.getSubReg());
1211}
1212
1213/// \brief Return the SubReg component from REG_SEQUENCE
1214TargetInstrInfo::RegSubRegPair getRegSequenceSubReg(MachineInstr &MI,
1215 unsigned SubReg);
1216
1217/// \brief Return the defining instruction for a given reg:subreg pair
1218/// skipping copy like instructions and subreg-manipulation pseudos.
1219/// Following another subreg of a reg:subreg isn't supported.
1220MachineInstr *getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P,
1221 MachineRegisterInfo &MRI);
1222
1223/// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1224/// DefMI and the use at \p UseMI. Should be run on SSA. Currently does not
1225/// attempt to track between blocks.
1226bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI,
1227 Register VReg,
1228 const MachineInstr &DefMI,
1229 const MachineInstr &UseMI);
1230
1231/// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1232/// DefMI and all its uses. Should be run on SSA. Currently does not attempt to
1233/// track between blocks.
1234bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI,
1235 Register VReg,
1236 const MachineInstr &DefMI);
1237
1238namespace AMDGPU {
1239
1241 int getVOPe64(uint16_t Opcode);
1242
1244 int getVOPe32(uint16_t Opcode);
1245
1247 int getSDWAOp(uint16_t Opcode);
1248
1251
1254
1257
1260
1263
1266
1267 /// Check if \p Opcode is an Addr64 opcode.
1268 ///
1269 /// \returns \p Opcode if it is an Addr64 opcode, otherwise -1.
1272
1275
1277 int getSOPKOp(uint16_t Opcode);
1278
1279 /// \returns SADDR form of a FLAT Global instruction given an \p Opcode
1280 /// of a VADDR form.
1283
1284 /// \returns VADDR form of a FLAT Global instruction given an \p Opcode
1285 /// of a SADDR form.
1288
1291
1292 /// \returns ST form with only immediate offset of a FLAT Scratch instruction
1293 /// given an \p Opcode of an SS (SADDR) form.
1296
1297 /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
1298 /// of an SVS (SADDR + VADDR) form.
1301
1302 /// \returns SS (SADDR) form of a FLAT Scratch instruction given an \p Opcode
1303 /// of an SV (VADDR) form.
1306
1307 /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
1308 /// of an SS (SADDR) form.
1311
1312 /// \returns earlyclobber version of a MAC MFMA is exists.
1315
1316 /// \returns v_cmpx version of a v_cmp instruction.
1319
1320 const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
1323 const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23);
1324
1325} // end namespace AMDGPU
1326
1327namespace SI {
1328namespace KernelInputOffsets {
1329
1330/// Offsets in bytes from the start of the input buffer
1340 LOCAL_SIZE_Z = 32
1342
1343} // end namespace KernelInputOffsets
1344} // end namespace SI
1345
1346} // end namespace llvm
1347
1348#endif // LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
unsigned SubReg
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Provides AMDGPU specific target descriptions.
AMDGPU specific overrides of MIRFormatter.
SmallVector< MachineOperand, 4 > Cond
#define LLVM_READONLY
Definition: Compiler.h:196
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
uint64_t Size
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
#define P(N)
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
@ SI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Interface definition for SIRegisterInfo.
This file implements a set that has insertion order iteration characteristics.
Class for arbitrary precision integers.
Definition: APInt.h:75
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A debug info location.
Definition: DebugLoc.h:33
Itinerary data supplied by a subtarget to be used by a target.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:85
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:97
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:91
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
MIRFormater - Interface to format MIR operand based on target.
Definition: MIRFormatter.h:28
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
Definition: MachineInstr.h:68
Flags
Flags values. These may be or'd together.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
unsigned getOperandNo() const
Returns the index of this operand in the instruction that it belongs to.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Represents one node in the SelectionDAG.
bool isFLATGlobal(uint16_t Opcode) const
Definition: SIInstrInfo.h:538
bool isInlineConstant(const APInt &Imm) const
static bool isMAI(const MachineInstr &MI)
Definition: SIInstrInfo.h:661
void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const
Fix operands in MI to satisfy constant bus requirements.
static bool isDS(const MachineInstr &MI)
Definition: SIInstrInfo.h:492
static bool isVMEM(const MachineInstr &MI)
Definition: SIInstrInfo.h:370
MachineBasicBlock * legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
Legalize all operands in this instruction.
bool areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, int64_t &Offset0, int64_t &Offset1) const override
bool isNonUniformBranchInstr(MachineInstr &Instr) const
static bool isVOP3(const MachineInstr &MI)
Definition: SIInstrInfo.h:442
bool isSMRD(uint16_t Opcode) const
Definition: SIInstrInfo.h:486
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const
Return the size in bytes of the operand OpNo on the given.
Definition: SIInstrInfo.h:920
bool isAtomic(uint16_t Opcode) const
Definition: SIInstrInfo.h:592
bool isLDSDIR(uint16_t Opcode) const
Definition: SIInstrInfo.h:698
bool isFLATScratch(uint16_t Opcode) const
Definition: SIInstrInfo.h:546
uint64_t getDefaultRsrcDataFormat() const
static bool isSOPP(const MachineInstr &MI)
Definition: SIInstrInfo.h:410
InstructionUniformity getGenericInstructionUniformity(const MachineInstr &MI) const
bool hasVGPRUses(const MachineInstr &MI) const
Definition: SIInstrInfo.h:800
uint64_t getClampMask(const MachineInstr &MI) const
Definition: SIInstrInfo.h:760
static bool isFLATScratch(const MachineInstr &MI)
Definition: SIInstrInfo.h:542
const MCInstrDesc & getIndirectRegWriteMovRelPseudo(unsigned VecSize, unsigned EltSize, bool IsSGPR) const
MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg) const
Return a partially built integer add instruction without carry.
bool mayAccessFlatAddressSpace(const MachineInstr &MI) const
bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0, int64_t Offset1, unsigned NumLoads) const override
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
static bool isSMRD(const MachineInstr &MI)
Definition: SIInstrInfo.h:482
bool isVGPRSpill(uint16_t Opcode) const
Definition: SIInstrInfo.h:617
bool usesConstantBus(const MachineRegisterInfo &MRI, const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Returns true if this operand uses the constant bus.
void legalizeOperandsFLAT(MachineRegisterInfo &MRI, MachineInstr &MI) const
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const final
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
bool isSegmentSpecificFLAT(uint16_t Opcode) const
Definition: SIInstrInfo.h:529
int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const
Get required immediate operand.
Definition: SIInstrInfo.h:1036
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const final
bool isPacked(uint16_t Opcode) const
Definition: SIInstrInfo.h:422
MachineBasicBlock * moveToVALU(MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
Replace this instruction's opcode with the equivalent VALU opcode.
static bool isMTBUF(const MachineInstr &MI)
Definition: SIInstrInfo.h:474
const MCInstrDesc & getIndirectGPRIDXPseudo(unsigned VecSize, bool IsIndirectSrc) const
void insertReturn(MachineBasicBlock &MBB) const
static bool isEXP(const MachineInstr &MI)
Definition: SIInstrInfo.h:555
static bool isSALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:354
bool sopkIsZext(uint16_t Opcode) const
Definition: SIInstrInfo.h:726
void legalizeGenericOperand(MachineBasicBlock &InsertMBB, MachineBasicBlock::iterator I, const TargetRegisterClass *DstRC, MachineOperand &Op, MachineRegisterInfo &MRI, const DebugLoc &DL) const
MachineInstr * buildShrunkInst(MachineInstr &MI, unsigned NewOpcode) const
unsigned getInstBundleSize(const MachineInstr &MI) const
static bool isVOP2(const MachineInstr &MI)
Definition: SIInstrInfo.h:434
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
static bool isSDWA(const MachineInstr &MI)
Definition: SIInstrInfo.h:450
bool isSOP1(uint16_t Opcode) const
Definition: SIInstrInfo.h:382
bool isInlineConstant(const APFloat &Imm) const
Definition: SIInstrInfo.h:820
const MCInstrDesc & getKillTerminatorFromPseudo(unsigned Opcode) const
void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Quantity) const override
static bool isVINTRP(const MachineInstr &MI)
Definition: SIInstrInfo.h:653
bool isAtomicRet(uint16_t Opcode) const
Definition: SIInstrInfo.h:583
static bool isGather4(const MachineInstr &MI)
Definition: SIInstrInfo.h:510
static bool isMFMAorWMMA(const MachineInstr &MI)
Definition: SIInstrInfo.h:686
static bool isWQM(const MachineInstr &MI)
Definition: SIInstrInfo.h:597
static bool doesNotReadTiedSource(const MachineInstr &MI)
Definition: SIInstrInfo.h:784
bool isLegalVSrcOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO would be a valid operand for the given operand definition OpInfo.
bool isSOPC(uint16_t Opcode) const
Definition: SIInstrInfo.h:398
static bool isDOT(const MachineInstr &MI)
Definition: SIInstrInfo.h:674
unsigned buildExtractSubReg(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
static bool usesFPDPRounding(const MachineInstr &MI)
Definition: SIInstrInfo.h:768
bool isFixedSize(uint16_t Opcode) const
Definition: SIInstrInfo.h:744
MachineInstr * createPHISourceCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, unsigned SrcSubReg, Register Dst) const override
Register readlaneVGPRToSGPR(Register SrcReg, MachineInstr &UseMI, MachineRegisterInfo &MRI) const
Copy a value from a VGPR (SrcReg) to SGPR.
bool isInlineConstant(const MachineOperand &MO) const
Definition: SIInstrInfo.h:875
bool hasModifiers(unsigned Opcode) const
Return true if this instruction has any modifiers.
bool isVOP3(uint16_t Opcode) const
Definition: SIInstrInfo.h:446
ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *II, const ScheduleDAGMI *DAG) const override
bool isDOT(uint16_t Opcode) const
Definition: SIInstrInfo.h:690
bool isWave32() const
bool isHighLatencyDef(int Opc) const override
bool isBasicBlockPrologue(const MachineInstr &MI) const override
void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const
Legalize the OpIndex operand of this instruction by inserting a MOV.
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
static bool isVOPC(const MachineInstr &MI)
Definition: SIInstrInfo.h:458
void removeModOperands(MachineInstr &MI) const
std::pair< int64_t, int64_t > splitFlatOffset(int64_t COffsetVal, unsigned AddrSpace, uint64_t FlatVariant) const
Split COffsetVal into {immediate offset field, remainder offset} values.
bool isGather4(uint16_t Opcode) const
Definition: SIInstrInfo.h:514
bool isFLAT(uint16_t Opcode) const
Definition: SIInstrInfo.h:551
static bool isLDSDIR(const MachineInstr &MI)
Definition: SIInstrInfo.h:694
static bool isSOP2(const MachineInstr &MI)
Definition: SIInstrInfo.h:386
const TargetSchedModel & getSchedModel() const
Definition: SIInstrInfo.h:1187
bool isVOPC(uint16_t Opcode) const
Definition: SIInstrInfo.h:462
bool isInlineConstant(const MachineInstr &MI, const MachineOperand &UseMO, const MachineOperand &DefMO) const
returns true if UseMO is substituted with DefMO in MI it would be an inline immediate.
Definition: SIInstrInfo.h:840
LLVM_READONLY MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
const MIRFormatter * getMIRFormatter() const override
Definition: SIInstrInfo.h:1179
const TargetRegisterClass * getPreferredSelectRegClass(unsigned Size) const
bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override
bool swapSourceModifiers(MachineInstr &MI, MachineOperand &Src0, unsigned Src0OpName, MachineOperand &Src1, unsigned Src1OpName) const
bool isMAI(uint16_t Opcode) const
Definition: SIInstrInfo.h:665
static bool isFLATGlobal(const MachineInstr &MI)
Definition: SIInstrInfo.h:534
unsigned getMachineCSELookAheadLimit() const override
Definition: SIInstrInfo.h:345
static bool isAtomicRet(const MachineInstr &MI)
Definition: SIInstrInfo.h:579
bool isBufferSMRD(const MachineInstr &MI) const
static bool isKillTerminator(unsigned Opcode)
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx0, unsigned &SrcOpIdx1) const override
const GCNSubtarget & getSubtarget() const
Definition: SIInstrInfo.h:183
bool isDS(uint16_t Opcode) const
Definition: SIInstrInfo.h:496
static bool isLegalMUBUFImmOffset(unsigned Imm)
Definition: SIInstrInfo.h:1130
bool isFPAtomic(uint16_t Opcode) const
Definition: SIInstrInfo.h:780
bool hasVALU32BitEncoding(unsigned Opcode) const
Return true if this 64-bit VALU instruction has a 32-bit encoding.
static bool isDisableWQM(const MachineInstr &MI)
Definition: SIInstrInfo.h:605
bool isAtomicNoRet(uint16_t Opcode) const
Definition: SIInstrInfo.h:575
unsigned getMovOpcode(const TargetRegisterClass *DstRC) const
unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const
void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const
Legalize operands in MI by either commuting it or inserting a copy of src1.
static bool isTRANS(const MachineInstr &MI)
Definition: SIInstrInfo.h:637
static bool isSOPK(const MachineInstr &MI)
Definition: SIInstrInfo.h:402
const TargetRegisterClass * getOpRegClass(const MachineInstr &MI, unsigned OpNo) const
Return the correct register class for OpNo.
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const
returns true if the operand OpIdx in MI is a valid inline immediate.
Definition: SIInstrInfo.h:853
static unsigned getDSShaderTypeValue(const MachineFunction &MF)
static bool isFoldableCopy(const MachineInstr &MI)
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo, const MachineOperand &MO) const
bool isIgnorableUse(const MachineOperand &MO) const override
static bool isVINTERP(const MachineInstr &MI)
Definition: SIInstrInfo.h:702
static bool isMUBUF(const MachineInstr &MI)
Definition: SIInstrInfo.h:466
bool expandPostRAPseudo(MachineInstr &MI) const override
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
bool isSALU(uint16_t Opcode) const
Definition: SIInstrInfo.h:358
void convertNonUniformLoopRegion(MachineBasicBlock *LoopEntry, MachineBasicBlock *LoopEnd) const
bool isVOP2(uint16_t Opcode) const
Definition: SIInstrInfo.h:438
static bool hasFPClamp(const MachineInstr &MI)
Definition: SIInstrInfo.h:748
InstructionUniformity getInstructionUniformity(const MachineInstr &MI) const override final
static bool isSegmentSpecificFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:524
bool isSDWA(uint16_t Opcode) const
Definition: SIInstrInfo.h:454
unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const
This form should usually be preferred since it handles operands with unknown register classes.
Definition: SIInstrInfo.h:934
bool isInlineConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Definition: SIInstrInfo.h:833
bool isSOPK(uint16_t Opcode) const
Definition: SIInstrInfo.h:406
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
static bool isDPP(const MachineInstr &MI)
Definition: SIInstrInfo.h:629
bool analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const
static bool isMFMA(const MachineInstr &MI)
Definition: SIInstrInfo.h:669
bool isSGPRSpill(uint16_t Opcode) const
Definition: SIInstrInfo.h:625
bool isLowLatencyInstruction(const MachineInstr &MI) const
static bool isScalarStore(const MachineInstr &MI)
Definition: SIInstrInfo.h:732
static bool sopkIsZext(const MachineInstr &MI)
Definition: SIInstrInfo.h:722
bool isTRANS(uint16_t Opcode) const
Definition: SIInstrInfo.h:641
void materializeImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DestReg, int64_t Value) const
bool isSOP2(uint16_t Opcode) const
Definition: SIInstrInfo.h:390
bool isVALU(uint16_t Opcode) const
Definition: SIInstrInfo.h:366
bool isVOP1(uint16_t Opcode) const
Definition: SIInstrInfo.h:430
bool isAlwaysGDS(uint16_t Opcode) const
bool isMUBUF(uint16_t Opcode) const
Definition: SIInstrInfo.h:470
static bool isFPAtomic(const MachineInstr &MI)
Definition: SIInstrInfo.h:776
static bool usesLGKM_CNT(const MachineInstr &MI)
Definition: SIInstrInfo.h:718
static bool isPacked(const MachineInstr &MI)
Definition: SIInstrInfo.h:418
bool canShrink(const MachineInstr &MI, const MachineRegisterInfo &MRI) const
bool isAsmOnlyOpcode(int MCOp) const
Check if this instruction should only be used by assembler.
bool isWMMA(uint16_t Opcode) const
Definition: SIInstrInfo.h:682
bool isMTBUF(uint16_t Opcode) const
Definition: SIInstrInfo.h:478
bool isDisableWQM(uint16_t Opcode) const
Definition: SIInstrInfo.h:609
static bool isVGPRSpill(const MachineInstr &MI)
Definition: SIInstrInfo.h:613
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
This is used by the post-RA scheduler (SchedulePostRAList.cpp).
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace, uint64_t FlatVariant) const
Returns if Offset is legal for the subtarget as the offset to a FLAT encoded instruction.
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
bool isVMEM(uint16_t Opcode) const
Definition: SIInstrInfo.h:374
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const override
bool isVINTRP(uint16_t Opcode) const
Definition: SIInstrInfo.h:657
bool isVGPRCopy(const MachineInstr &MI) const
Definition: SIInstrInfo.h:792
bool isScalarStore(uint16_t Opcode) const
Definition: SIInstrInfo.h:736
static bool isMIMG(const MachineInstr &MI)
Definition: SIInstrInfo.h:502
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
bool isLegalRegOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO (a register operand) is a legal register for the given operand description.
LLVM_READONLY int commuteOpcode(const MachineInstr &MI) const
Definition: SIInstrInfo.h:264
MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
static unsigned getNumWaitStates(const MachineInstr &MI)
Return the number of wait states that result from executing this instruction.
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const override
static bool isVOP3P(const MachineInstr &MI)
Definition: SIInstrInfo.h:645
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
bool isWQM(uint16_t Opcode) const
Definition: SIInstrInfo.h:601
unsigned getVALUOp(const MachineInstr &MI) const
static bool modifiesModeRegister(const MachineInstr &MI)
Return true if the instruction modifies the mode register.q.
void convertNonUniformIfRegion(MachineBasicBlock *IfEntry, MachineBasicBlock *IfEnd) const
bool hasDivergentBranch(const MachineBasicBlock *MBB) const
Return whether the block terminate with divergent branch.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void fixImplicitOperands(MachineInstr &MI) const
bool moveFlatAddrToVGPR(MachineInstr &Inst) const
Change SADDR form of a FLAT Inst to its VADDR form if saddr operand was moved to VGPR.
bool isVOP3P(uint16_t Opcode) const
Definition: SIInstrInfo.h:649
LLVM_READONLY const MachineOperand * getNamedOperand(const MachineInstr &MI, unsigned OpName) const
Definition: SIInstrInfo.h:1030
bool isEXP(uint16_t Opcode) const
Definition: SIInstrInfo.h:567
Register insertNE(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
static bool isDualSourceBlendEXP(const MachineInstr &MI)
Definition: SIInstrInfo.h:559
bool hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const
Whether we must prevent this instruction from executing with EXEC = 0.
static bool isAtomic(const MachineInstr &MI)
Definition: SIInstrInfo.h:587
bool canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
static bool isSGPRSpill(const MachineInstr &MI)
Definition: SIInstrInfo.h:621
static bool isWMMA(const MachineInstr &MI)
Definition: SIInstrInfo.h:678
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const override
bool isVINTERP(uint16_t Opcode) const
Definition: SIInstrInfo.h:706
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const override
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const
Returns true if the instruction could potentially depend on the value of exec.
void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
bool doesNotReadTiedSource(uint16_t Opcode) const
Definition: SIInstrInfo.h:788
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool isDPP(uint16_t Opcode) const
Definition: SIInstrInfo.h:633
void insertVectorSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
std::pair< MachineInstr *, MachineInstr * > expandMovDPP64(MachineInstr &MI) const
Register insertEQ(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const
static bool isSOP1(const MachineInstr &MI)
Definition: SIInstrInfo.h:378
static bool isSOPC(const MachineInstr &MI)
Definition: SIInstrInfo.h:394
static bool isFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:518
const SIRegisterInfo & getRegisterInfo() const
Definition: SIInstrInfo.h:179
static bool isVALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:362
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx0, unsigned OpIdx1) const override
void enforceOperandRCAlignment(MachineInstr &MI, unsigned OpName) const
static bool hasIntClamp(const MachineInstr &MI)
Definition: SIInstrInfo.h:756
int pseudoToMCOpcode(int Opcode) const
Return a target-specific opcode if Opcode is a pseudo instruction.
const MCInstrDesc & getMCOpcodeFromPseudo(unsigned Opcode) const
Return the descriptor of the target-specific machine instruction that corresponds to the specified ps...
Definition: SIInstrInfo.h:1049
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx, const MachineOperand &MO) const
Definition: SIInstrInfo.h:858
static bool isScalarUnit(const MachineInstr &MI)
Definition: SIInstrInfo.h:710
bool isSOPP(uint16_t Opcode) const
Definition: SIInstrInfo.h:414
bool isMIMG(uint16_t Opcode) const
Definition: SIInstrInfo.h:506
bool hasFPClamp(uint16_t Opcode) const
Definition: SIInstrInfo.h:752
static bool usesVM_CNT(const MachineInstr &MI)
Definition: SIInstrInfo.h:714
bool usesFPDPRounding(uint16_t Opcode) const
Definition: SIInstrInfo.h:772
MachineInstr * createPHIDestinationCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register Dst) const override
bool hasModifiersSet(const MachineInstr &MI, unsigned OpName) const
static bool isFixedSize(const MachineInstr &MI)
Definition: SIInstrInfo.h:740
LLVM_READONLY int commuteOpcode(unsigned Opc) const
uint64_t getScratchRsrcWords23() const
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const
Check if MO is a legal operand if it was the OpIdx Operand for MI.
unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const
static bool isAtomicNoRet(const MachineInstr &MI)
Definition: SIInstrInfo.h:571
static bool isVOP1(const MachineInstr &MI)
Definition: SIInstrInfo.h:426
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
bool hasAnyModifiersSet(const MachineInstr &MI) const
const TargetRegisterClass * getRegClass(unsigned RCID) const
bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
A SetVector that performs no allocations if smaller than a certain size.
Definition: SetVector.h:301
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Provide an instruction scheduling machine model to CodeGen passes.
Target - Wrapper for Target specific information.
LLVM Value Representation.
Definition: Value.h:74
const uint64_t RSRC_DATA_FORMAT
Definition: SIInstrInfo.h:1320
LLVM_READONLY int getBasicFromSDWAOp(uint16_t Opcode)
LLVM_READONLY int getGlobalSaddrOp(uint16_t Opcode)
LLVM_READONLY int getSOPKOp(uint16_t Opcode)
LLVM_READONLY int getVOPe32(uint16_t Opcode)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
LLVM_READONLY int getDPPOp32(uint16_t Opcode)
LLVM_READONLY int getFlatScratchInstSVfromSS(uint16_t Opcode)
LLVM_READONLY int getFlatScratchInstSTfromSS(uint16_t Opcode)
LLVM_READONLY int getGlobalVaddrOp(uint16_t Opcode)
LLVM_READONLY int getAtomicNoRetOp(uint16_t Opcode)
const uint64_t RSRC_ELEMENT_SIZE_SHIFT
Definition: SIInstrInfo.h:1321
LLVM_READONLY int getFlatScratchInstSVfromSVS(uint16_t Opcode)
LLVM_READONLY int getAddr64Inst(uint16_t Opcode)
LLVM_READONLY int getMFMAEarlyClobberOp(uint16_t Opcode)
LLVM_READONLY int getVCMPXOpFromVCMP(uint16_t Opcode)
LLVM_READONLY int getSDWAOp(uint16_t Opcode)
const uint64_t RSRC_TID_ENABLE
Definition: SIInstrInfo.h:1323
LLVM_READONLY int getCommuteRev(uint16_t Opcode)
LLVM_READONLY int getDPPOp64(uint16_t Opcode)
LLVM_READONLY int getVOPe64(uint16_t Opcode)
@ OPERAND_REG_IMM_INT64
Definition: SIDefines.h:158
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition: SIDefines.h:157
LLVM_READONLY int getCommuteOrig(uint16_t Opcode)
const uint64_t RSRC_INDEX_STRIDE_SHIFT
Definition: SIInstrInfo.h:1322
LLVM_READONLY int getFlatScratchInstSSfromSV(uint16_t Opcode)
LLVM_READONLY int getVCMPXNoSDstOp(uint16_t Opcode)
LLVM_READONLY int getIfAddr64Inst(uint16_t Opcode)
Check if Opcode is an Addr64 opcode.
@ OPERAND_IMMEDIATE
Definition: MCInstrDesc.h:60
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1331
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
TargetInstrInfo::RegSubRegPair getRegSubRegPair(const MachineOperand &O)
Create RegSubRegPair from a register MachineOperand.
Definition: SIInstrInfo.h:1208
bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI, Register VReg, const MachineInstr &DefMI, const MachineInstr &UseMI)
Return false if EXEC is not changed between the def of VReg at DefMI and the use at UseMI.
TargetInstrInfo::RegSubRegPair getRegSequenceSubReg(MachineInstr &MI, unsigned SubReg)
Return the SubReg component from REG_SEQUENCE.
static const MachineMemOperand::Flags MONoClobber
Mark the MMO of a uniform load if there are no potentially clobbering stores on any path from the sta...
Definition: SIInstrInfo.h:41
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1742
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
MachineInstr * getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P, MachineRegisterInfo &MRI)
Return the defining instruction for a given reg:subreg pair skipping copy like instructions and subre...
bool isOfRegClass(const TargetInstrInfo::RegSubRegPair &P, const TargetRegisterClass &TRC, MachineRegisterInfo &MRI)
Returns true if a reg:subreg pair P has a TRC class.
Definition: SIInstrInfo.h:1196
InstructionUniformity
Enum describing how instructions behave with respect to uniformity and divergence,...
Definition: Uniformity.h:21
bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI, Register VReg, const MachineInstr &DefMI)
Return false if EXEC is not changed between the def of VReg at DefMI and all its uses.
A pair composed of a register and a sub-register index.