LLVM 20.0.0git
SIInstrInfo.h
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1//===- SIInstrInfo.h - SI Instruction Info Interface ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Interface definition for SIInstrInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
15#define LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
16
17#include "AMDGPUMIRFormatter.h"
19#include "SIRegisterInfo.h"
21#include "llvm/ADT/SetVector.h"
24
25#define GET_INSTRINFO_HEADER
26#include "AMDGPUGenInstrInfo.inc"
27
28namespace llvm {
29
30class APInt;
31class GCNSubtarget;
32class LiveVariables;
33class MachineDominatorTree;
34class MachineRegisterInfo;
35class RegScavenger;
36class TargetRegisterClass;
37class ScheduleHazardRecognizer;
38
39constexpr unsigned DefaultMemoryClusterDWordsLimit = 8;
40
41/// Mark the MMO of a uniform load if there are no potentially clobbering stores
42/// on any path from the start of an entry function to this load.
45
46/// Mark the MMO of a load as the last use.
49
50/// Utility to store machine instructions worklist.
52 SIInstrWorklist() = default;
53
54 void insert(MachineInstr *MI);
55
56 MachineInstr *top() const {
57 const auto *iter = InstrList.begin();
58 return *iter;
59 }
60
61 void erase_top() {
62 const auto *iter = InstrList.begin();
63 InstrList.erase(iter);
64 }
65
66 bool empty() const { return InstrList.empty(); }
67
68 void clear() {
69 InstrList.clear();
70 DeferredList.clear();
71 }
72
74
75 SetVector<MachineInstr *> &getDeferredList() { return DeferredList; }
76
77private:
78 /// InstrList contains the MachineInstrs.
80 /// Deferred instructions are specific MachineInstr
81 /// that will be added by insert method.
82 SetVector<MachineInstr *> DeferredList;
83};
84
85class SIInstrInfo final : public AMDGPUGenInstrInfo {
86private:
87 const SIRegisterInfo RI;
88 const GCNSubtarget &ST;
89 TargetSchedModel SchedModel;
90 mutable std::unique_ptr<AMDGPUMIRFormatter> Formatter;
91
92 // The inverse predicate should have the negative value.
93 enum BranchPredicate {
94 INVALID_BR = 0,
95 SCC_TRUE = 1,
96 SCC_FALSE = -1,
97 VCCNZ = 2,
98 VCCZ = -2,
99 EXECNZ = -3,
100 EXECZ = 3
101 };
102
104
105 static unsigned getBranchOpcode(BranchPredicate Cond);
106 static BranchPredicate getBranchPredicate(unsigned Opcode);
107
108public:
111 const MachineOperand &SuperReg,
112 const TargetRegisterClass *SuperRC,
113 unsigned SubIdx,
114 const TargetRegisterClass *SubRC) const;
117 const MachineOperand &SuperReg, const TargetRegisterClass *SuperRC,
118 unsigned SubIdx, const TargetRegisterClass *SubRC) const;
119
120private:
121 void swapOperands(MachineInstr &Inst) const;
122
123 std::pair<bool, MachineBasicBlock *>
124 moveScalarAddSub(SIInstrWorklist &Worklist, MachineInstr &Inst,
125 MachineDominatorTree *MDT = nullptr) const;
126
127 void lowerSelect(SIInstrWorklist &Worklist, MachineInstr &Inst,
128 MachineDominatorTree *MDT = nullptr) const;
129
130 void lowerScalarAbs(SIInstrWorklist &Worklist, MachineInstr &Inst) const;
131
132 void lowerScalarXnor(SIInstrWorklist &Worklist, MachineInstr &Inst) const;
133
134 void splitScalarNotBinop(SIInstrWorklist &Worklist, MachineInstr &Inst,
135 unsigned Opcode) const;
136
137 void splitScalarBinOpN2(SIInstrWorklist &Worklist, MachineInstr &Inst,
138 unsigned Opcode) const;
139
140 void splitScalar64BitUnaryOp(SIInstrWorklist &Worklist, MachineInstr &Inst,
141 unsigned Opcode, bool Swap = false) const;
142
143 void splitScalar64BitBinaryOp(SIInstrWorklist &Worklist, MachineInstr &Inst,
144 unsigned Opcode,
145 MachineDominatorTree *MDT = nullptr) const;
146
147 void splitScalarSMulU64(SIInstrWorklist &Worklist, MachineInstr &Inst,
148 MachineDominatorTree *MDT) const;
149
150 void splitScalarSMulPseudo(SIInstrWorklist &Worklist, MachineInstr &Inst,
151 MachineDominatorTree *MDT) const;
152
153 void splitScalar64BitXnor(SIInstrWorklist &Worklist, MachineInstr &Inst,
154 MachineDominatorTree *MDT = nullptr) const;
155
156 void splitScalar64BitBCNT(SIInstrWorklist &Worklist,
157 MachineInstr &Inst) const;
158 void splitScalar64BitBFE(SIInstrWorklist &Worklist, MachineInstr &Inst) const;
159 void splitScalar64BitCountOp(SIInstrWorklist &Worklist, MachineInstr &Inst,
160 unsigned Opcode,
161 MachineDominatorTree *MDT = nullptr) const;
162 void movePackToVALU(SIInstrWorklist &Worklist, MachineRegisterInfo &MRI,
163 MachineInstr &Inst) const;
164
165 void addUsersToMoveToVALUWorklist(Register Reg, MachineRegisterInfo &MRI,
166 SIInstrWorklist &Worklist) const;
167
168 void addSCCDefUsersToVALUWorklist(MachineOperand &Op,
169 MachineInstr &SCCDefInst,
170 SIInstrWorklist &Worklist,
171 Register NewCond = Register()) const;
172 void addSCCDefsToVALUWorklist(MachineInstr *SCCUseInst,
173 SIInstrWorklist &Worklist) const;
174
175 const TargetRegisterClass *
176 getDestEquivalentVGPRClass(const MachineInstr &Inst) const;
177
178 bool checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
179 const MachineInstr &MIb) const;
180
181 Register findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
182
183 bool verifyCopy(const MachineInstr &MI, const MachineRegisterInfo &MRI,
184 StringRef &ErrInfo) const;
185
186protected:
187 /// If the specific machine instruction is a instruction that moves/copies
188 /// value from one register to another register return destination and source
189 /// registers as machine operands.
190 std::optional<DestSourcePair>
191 isCopyInstrImpl(const MachineInstr &MI) const override;
192
194 MachineOperand &Src0, unsigned Src0OpName,
195 MachineOperand &Src1, unsigned Src1OpName) const;
196
198 unsigned OpIdx0,
199 unsigned OpIdx1) const override;
200
201public:
203 MO_MASK = 0xf,
204
206 // MO_GOTPCREL -> symbol@GOTPCREL -> R_AMDGPU_GOTPCREL.
208 // MO_GOTPCREL32_LO -> symbol@gotpcrel32@lo -> R_AMDGPU_GOTPCREL32_LO.
211 // MO_GOTPCREL32_HI -> symbol@gotpcrel32@hi -> R_AMDGPU_GOTPCREL32_HI.
213 // MO_REL32_LO -> symbol@rel32@lo -> R_AMDGPU_REL32_LO.
216 // MO_REL32_HI -> symbol@rel32@hi -> R_AMDGPU_REL32_HI.
218
220
223 };
224
225 explicit SIInstrInfo(const GCNSubtarget &ST);
226
228 return RI;
229 }
230
231 const GCNSubtarget &getSubtarget() const {
232 return ST;
233 }
234
235 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
236
237 bool isIgnorableUse(const MachineOperand &MO) const override;
238
239 bool isSafeToSink(MachineInstr &MI, MachineBasicBlock *SuccToSinkTo,
240 MachineCycleInfo *CI) const override;
241
242 bool areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, int64_t &Offset0,
243 int64_t &Offset1) const override;
244
245 bool isGlobalMemoryObject(const MachineInstr *MI) const override;
246
248 const MachineInstr &LdSt,
250 bool &OffsetIsScalable, LocationSize &Width,
251 const TargetRegisterInfo *TRI) const final;
252
254 int64_t Offset1, bool OffsetIsScalable1,
256 int64_t Offset2, bool OffsetIsScalable2,
257 unsigned ClusterSize,
258 unsigned NumBytes) const override;
259
260 bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
261 int64_t Offset1, unsigned NumLoads) const override;
262
264 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
265 bool KillSrc, bool RenamableDest = false,
266 bool RenamableSrc = false) const override;
267
270 Register DestReg, int64_t Value) const;
271
273 unsigned Size) const;
274
277 Register SrcReg, int Value) const;
278
281 Register SrcReg, int Value) const;
282
285 bool isKill, int FrameIndex,
286 const TargetRegisterClass *RC,
287 const TargetRegisterInfo *TRI,
288 Register VReg) const override;
289
292 int FrameIndex, const TargetRegisterClass *RC,
293 const TargetRegisterInfo *TRI,
294 Register VReg) const override;
295
296 bool expandPostRAPseudo(MachineInstr &MI) const override;
297
299 Register DestReg, unsigned SubIdx,
300 const MachineInstr &Orig,
301 const TargetRegisterInfo &TRI) const override;
302
303 // Splits a V_MOV_B64_DPP_PSEUDO opcode into a pair of v_mov_b32_dpp
304 // instructions. Returns a pair of generated instructions.
305 // Can split either post-RA with physical registers or pre-RA with
306 // virtual registers. In latter case IR needs to be in SSA form and
307 // and a REG_SEQUENCE is produced to define original register.
308 std::pair<MachineInstr*, MachineInstr*>
310
311 // Returns an opcode that can be used to move a value to a \p DstRC
312 // register. If there is no hardware instruction that can store to \p
313 // DstRC, then AMDGPU::COPY is returned.
314 unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
315
316 const MCInstrDesc &getIndirectRegWriteMovRelPseudo(unsigned VecSize,
317 unsigned EltSize,
318 bool IsSGPR) const;
319
320 const MCInstrDesc &getIndirectGPRIDXPseudo(unsigned VecSize,
321 bool IsIndirectSrc) const;
323 int commuteOpcode(unsigned Opc) const;
324
326 inline int commuteOpcode(const MachineInstr &MI) const {
327 return commuteOpcode(MI.getOpcode());
328 }
329
330 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx0,
331 unsigned &SrcOpIdx1) const override;
332
333 bool findCommutedOpIndices(const MCInstrDesc &Desc, unsigned &SrcOpIdx0,
334 unsigned &SrcOpIdx1) const;
335
336 bool isBranchOffsetInRange(unsigned BranchOpc,
337 int64_t BrOffset) const override;
338
339 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
340
341 /// Return whether the block terminate with divergent branch.
342 /// Note this only work before lowering the pseudo control flow instructions.
343 bool hasDivergentBranch(const MachineBasicBlock *MBB) const;
344
346 MachineBasicBlock &NewDestBB,
347 MachineBasicBlock &RestoreBB, const DebugLoc &DL,
348 int64_t BrOffset, RegScavenger *RS) const override;
349
353 MachineBasicBlock *&FBB,
355 bool AllowModify) const;
356
358 MachineBasicBlock *&FBB,
360 bool AllowModify = false) const override;
361
363 int *BytesRemoved = nullptr) const override;
364
367 const DebugLoc &DL,
368 int *BytesAdded = nullptr) const override;
369
371 SmallVectorImpl<MachineOperand> &Cond) const override;
372
375 Register TrueReg, Register FalseReg, int &CondCycles,
376 int &TrueCycles, int &FalseCycles) const override;
377
381 Register TrueReg, Register FalseReg) const override;
382
386 Register TrueReg, Register FalseReg) const;
387
388 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
389 Register &SrcReg2, int64_t &CmpMask,
390 int64_t &CmpValue) const override;
391
392 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
393 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
394 const MachineRegisterInfo *MRI) const override;
395
396 bool
398 const MachineInstr &MIb) const override;
399
400 static bool isFoldableCopy(const MachineInstr &MI);
401
402 void removeModOperands(MachineInstr &MI) const;
403
405 MachineRegisterInfo *MRI) const final;
406
407 unsigned getMachineCSELookAheadLimit() const override { return 500; }
408
410 LiveIntervals *LIS) const override;
411
413 const MachineBasicBlock *MBB,
414 const MachineFunction &MF) const override;
415
416 static bool isSALU(const MachineInstr &MI) {
417 return MI.getDesc().TSFlags & SIInstrFlags::SALU;
418 }
419
420 bool isSALU(uint16_t Opcode) const {
421 return get(Opcode).TSFlags & SIInstrFlags::SALU;
422 }
423
424 static bool isVALU(const MachineInstr &MI) {
425 return MI.getDesc().TSFlags & SIInstrFlags::VALU;
426 }
427
428 bool isVALU(uint16_t Opcode) const {
429 return get(Opcode).TSFlags & SIInstrFlags::VALU;
430 }
431
432 static bool isImage(const MachineInstr &MI) {
433 return isMIMG(MI) || isVSAMPLE(MI) || isVIMAGE(MI);
434 }
435
436 bool isImage(uint16_t Opcode) const {
437 return isMIMG(Opcode) || isVSAMPLE(Opcode) || isVIMAGE(Opcode);
438 }
439
440 static bool isVMEM(const MachineInstr &MI) {
441 return isMUBUF(MI) || isMTBUF(MI) || isImage(MI);
442 }
443
444 bool isVMEM(uint16_t Opcode) const {
445 return isMUBUF(Opcode) || isMTBUF(Opcode) || isImage(Opcode);
446 }
447
448 static bool isSOP1(const MachineInstr &MI) {
449 return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
450 }
451
452 bool isSOP1(uint16_t Opcode) const {
453 return get(Opcode).TSFlags & SIInstrFlags::SOP1;
454 }
455
456 static bool isSOP2(const MachineInstr &MI) {
457 return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
458 }
459
460 bool isSOP2(uint16_t Opcode) const {
461 return get(Opcode).TSFlags & SIInstrFlags::SOP2;
462 }
463
464 static bool isSOPC(const MachineInstr &MI) {
465 return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
466 }
467
468 bool isSOPC(uint16_t Opcode) const {
469 return get(Opcode).TSFlags & SIInstrFlags::SOPC;
470 }
471
472 static bool isSOPK(const MachineInstr &MI) {
473 return MI.getDesc().TSFlags & SIInstrFlags::SOPK;
474 }
475
476 bool isSOPK(uint16_t Opcode) const {
477 return get(Opcode).TSFlags & SIInstrFlags::SOPK;
478 }
479
480 static bool isSOPP(const MachineInstr &MI) {
481 return MI.getDesc().TSFlags & SIInstrFlags::SOPP;
482 }
483
484 bool isSOPP(uint16_t Opcode) const {
485 return get(Opcode).TSFlags & SIInstrFlags::SOPP;
486 }
487
488 static bool isPacked(const MachineInstr &MI) {
489 return MI.getDesc().TSFlags & SIInstrFlags::IsPacked;
490 }
491
492 bool isPacked(uint16_t Opcode) const {
493 return get(Opcode).TSFlags & SIInstrFlags::IsPacked;
494 }
495
496 static bool isVOP1(const MachineInstr &MI) {
497 return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
498 }
499
500 bool isVOP1(uint16_t Opcode) const {
501 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
502 }
503
504 static bool isVOP2(const MachineInstr &MI) {
505 return MI.getDesc().TSFlags & SIInstrFlags::VOP2;
506 }
507
508 bool isVOP2(uint16_t Opcode) const {
509 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
510 }
511
512 static bool isVOP3(const MachineInstr &MI) {
513 return MI.getDesc().TSFlags & SIInstrFlags::VOP3;
514 }
515
516 bool isVOP3(uint16_t Opcode) const {
517 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
518 }
519
520 static bool isSDWA(const MachineInstr &MI) {
521 return MI.getDesc().TSFlags & SIInstrFlags::SDWA;
522 }
523
524 bool isSDWA(uint16_t Opcode) const {
525 return get(Opcode).TSFlags & SIInstrFlags::SDWA;
526 }
527
528 static bool isVOPC(const MachineInstr &MI) {
529 return MI.getDesc().TSFlags & SIInstrFlags::VOPC;
530 }
531
532 bool isVOPC(uint16_t Opcode) const {
533 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
534 }
535
536 static bool isMUBUF(const MachineInstr &MI) {
537 return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;
538 }
539
540 bool isMUBUF(uint16_t Opcode) const {
541 return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
542 }
543
544 static bool isMTBUF(const MachineInstr &MI) {
545 return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;
546 }
547
548 bool isMTBUF(uint16_t Opcode) const {
549 return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
550 }
551
552 static bool isSMRD(const MachineInstr &MI) {
553 return MI.getDesc().TSFlags & SIInstrFlags::SMRD;
554 }
555
556 bool isSMRD(uint16_t Opcode) const {
557 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
558 }
559
560 bool isBufferSMRD(const MachineInstr &MI) const;
561
562 static bool isDS(const MachineInstr &MI) {
563 return MI.getDesc().TSFlags & SIInstrFlags::DS;
564 }
565
566 bool isDS(uint16_t Opcode) const {
567 return get(Opcode).TSFlags & SIInstrFlags::DS;
568 }
569
570 static bool isLDSDMA(const MachineInstr &MI) {
571 return isVALU(MI) && (isMUBUF(MI) || isFLAT(MI));
572 }
573
574 bool isLDSDMA(uint16_t Opcode) {
575 return isVALU(Opcode) && (isMUBUF(Opcode) || isFLAT(Opcode));
576 }
577
578 static bool isGWS(const MachineInstr &MI) {
579 return MI.getDesc().TSFlags & SIInstrFlags::GWS;
580 }
581
582 bool isGWS(uint16_t Opcode) const {
583 return get(Opcode).TSFlags & SIInstrFlags::GWS;
584 }
585
586 bool isAlwaysGDS(uint16_t Opcode) const;
587
588 static bool isMIMG(const MachineInstr &MI) {
589 return MI.getDesc().TSFlags & SIInstrFlags::MIMG;
590 }
591
592 bool isMIMG(uint16_t Opcode) const {
593 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
594 }
595
596 static bool isVIMAGE(const MachineInstr &MI) {
597 return MI.getDesc().TSFlags & SIInstrFlags::VIMAGE;
598 }
599
600 bool isVIMAGE(uint16_t Opcode) const {
601 return get(Opcode).TSFlags & SIInstrFlags::VIMAGE;
602 }
603
604 static bool isVSAMPLE(const MachineInstr &MI) {
605 return MI.getDesc().TSFlags & SIInstrFlags::VSAMPLE;
606 }
607
608 bool isVSAMPLE(uint16_t Opcode) const {
609 return get(Opcode).TSFlags & SIInstrFlags::VSAMPLE;
610 }
611
612 static bool isGather4(const MachineInstr &MI) {
613 return MI.getDesc().TSFlags & SIInstrFlags::Gather4;
614 }
615
616 bool isGather4(uint16_t Opcode) const {
617 return get(Opcode).TSFlags & SIInstrFlags::Gather4;
618 }
619
620 static bool isFLAT(const MachineInstr &MI) {
621 return MI.getDesc().TSFlags & SIInstrFlags::FLAT;
622 }
623
624 // Is a FLAT encoded instruction which accesses a specific segment,
625 // i.e. global_* or scratch_*.
627 auto Flags = MI.getDesc().TSFlags;
629 }
630
631 bool isSegmentSpecificFLAT(uint16_t Opcode) const {
632 auto Flags = get(Opcode).TSFlags;
634 }
635
636 static bool isFLATGlobal(const MachineInstr &MI) {
637 return MI.getDesc().TSFlags & SIInstrFlags::FlatGlobal;
638 }
639
640 bool isFLATGlobal(uint16_t Opcode) const {
641 return get(Opcode).TSFlags & SIInstrFlags::FlatGlobal;
642 }
643
644 static bool isFLATScratch(const MachineInstr &MI) {
645 return MI.getDesc().TSFlags & SIInstrFlags::FlatScratch;
646 }
647
648 bool isFLATScratch(uint16_t Opcode) const {
649 return get(Opcode).TSFlags & SIInstrFlags::FlatScratch;
650 }
651
652 // Any FLAT encoded instruction, including global_* and scratch_*.
653 bool isFLAT(uint16_t Opcode) const {
654 return get(Opcode).TSFlags & SIInstrFlags::FLAT;
655 }
656
657 static bool isEXP(const MachineInstr &MI) {
658 return MI.getDesc().TSFlags & SIInstrFlags::EXP;
659 }
660
662 if (!isEXP(MI))
663 return false;
664 unsigned Target = MI.getOperand(0).getImm();
667 }
668
669 bool isEXP(uint16_t Opcode) const {
670 return get(Opcode).TSFlags & SIInstrFlags::EXP;
671 }
672
673 static bool isAtomicNoRet(const MachineInstr &MI) {
674 return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicNoRet;
675 }
676
677 bool isAtomicNoRet(uint16_t Opcode) const {
678 return get(Opcode).TSFlags & SIInstrFlags::IsAtomicNoRet;
679 }
680
681 static bool isAtomicRet(const MachineInstr &MI) {
682 return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicRet;
683 }
684
685 bool isAtomicRet(uint16_t Opcode) const {
686 return get(Opcode).TSFlags & SIInstrFlags::IsAtomicRet;
687 }
688
689 static bool isAtomic(const MachineInstr &MI) {
690 return MI.getDesc().TSFlags & (SIInstrFlags::IsAtomicRet |
692 }
693
694 bool isAtomic(uint16_t Opcode) const {
695 return get(Opcode).TSFlags & (SIInstrFlags::IsAtomicRet |
697 }
698
700 return isLDSDMA(MI) && MI.getOpcode() != AMDGPU::BUFFER_STORE_LDS_DWORD;
701 }
702
703 static bool isWQM(const MachineInstr &MI) {
704 return MI.getDesc().TSFlags & SIInstrFlags::WQM;
705 }
706
707 bool isWQM(uint16_t Opcode) const {
708 return get(Opcode).TSFlags & SIInstrFlags::WQM;
709 }
710
711 static bool isDisableWQM(const MachineInstr &MI) {
712 return MI.getDesc().TSFlags & SIInstrFlags::DisableWQM;
713 }
714
715 bool isDisableWQM(uint16_t Opcode) const {
716 return get(Opcode).TSFlags & SIInstrFlags::DisableWQM;
717 }
718
719 // SI_SPILL_S32_TO_VGPR and SI_RESTORE_S32_FROM_VGPR form a special case of
720 // SGPRs spilling to VGPRs which are SGPR spills but from VALU instructions
721 // therefore we need an explicit check for them since just checking if the
722 // Spill bit is set and what instruction type it came from misclassifies
723 // them.
724 static bool isVGPRSpill(const MachineInstr &MI) {
725 return MI.getOpcode() != AMDGPU::SI_SPILL_S32_TO_VGPR &&
726 MI.getOpcode() != AMDGPU::SI_RESTORE_S32_FROM_VGPR &&
727 (isSpill(MI) && isVALU(MI));
728 }
729
730 bool isVGPRSpill(uint16_t Opcode) const {
731 return Opcode != AMDGPU::SI_SPILL_S32_TO_VGPR &&
732 Opcode != AMDGPU::SI_RESTORE_S32_FROM_VGPR &&
733 (isSpill(Opcode) && isVALU(Opcode));
734 }
735
736 static bool isSGPRSpill(const MachineInstr &MI) {
737 return MI.getOpcode() == AMDGPU::SI_SPILL_S32_TO_VGPR ||
738 MI.getOpcode() == AMDGPU::SI_RESTORE_S32_FROM_VGPR ||
739 (isSpill(MI) && isSALU(MI));
740 }
741
742 bool isSGPRSpill(uint16_t Opcode) const {
743 return Opcode == AMDGPU::SI_SPILL_S32_TO_VGPR ||
744 Opcode == AMDGPU::SI_RESTORE_S32_FROM_VGPR ||
745 (isSpill(Opcode) && isSALU(Opcode));
746 }
747
748 bool isSpill(uint16_t Opcode) const {
749 return get(Opcode).TSFlags & SIInstrFlags::Spill;
750 }
751
752 static bool isSpill(const MachineInstr &MI) {
753 return MI.getDesc().TSFlags & SIInstrFlags::Spill;
754 }
755
756 static bool isWWMRegSpillOpcode(uint16_t Opcode) {
757 return Opcode == AMDGPU::SI_SPILL_WWM_V32_SAVE ||
758 Opcode == AMDGPU::SI_SPILL_WWM_AV32_SAVE ||
759 Opcode == AMDGPU::SI_SPILL_WWM_V32_RESTORE ||
760 Opcode == AMDGPU::SI_SPILL_WWM_AV32_RESTORE;
761 }
762
763 static bool isChainCallOpcode(uint64_t Opcode) {
764 return Opcode == AMDGPU::SI_CS_CHAIN_TC_W32 ||
765 Opcode == AMDGPU::SI_CS_CHAIN_TC_W64;
766 }
767
768 static bool isDPP(const MachineInstr &MI) {
769 return MI.getDesc().TSFlags & SIInstrFlags::DPP;
770 }
771
772 bool isDPP(uint16_t Opcode) const {
773 return get(Opcode).TSFlags & SIInstrFlags::DPP;
774 }
775
776 static bool isTRANS(const MachineInstr &MI) {
777 return MI.getDesc().TSFlags & SIInstrFlags::TRANS;
778 }
779
780 bool isTRANS(uint16_t Opcode) const {
781 return get(Opcode).TSFlags & SIInstrFlags::TRANS;
782 }
783
784 static bool isVOP3P(const MachineInstr &MI) {
785 return MI.getDesc().TSFlags & SIInstrFlags::VOP3P;
786 }
787
788 bool isVOP3P(uint16_t Opcode) const {
789 return get(Opcode).TSFlags & SIInstrFlags::VOP3P;
790 }
791
792 static bool isVINTRP(const MachineInstr &MI) {
793 return MI.getDesc().TSFlags & SIInstrFlags::VINTRP;
794 }
795
796 bool isVINTRP(uint16_t Opcode) const {
797 return get(Opcode).TSFlags & SIInstrFlags::VINTRP;
798 }
799
800 static bool isMAI(const MachineInstr &MI) {
801 return MI.getDesc().TSFlags & SIInstrFlags::IsMAI;
802 }
803
804 bool isMAI(uint16_t Opcode) const {
805 return get(Opcode).TSFlags & SIInstrFlags::IsMAI;
806 }
807
808 static bool isMFMA(const MachineInstr &MI) {
809 return isMAI(MI) && MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64 &&
810 MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64;
811 }
812
813 static bool isDOT(const MachineInstr &MI) {
814 return MI.getDesc().TSFlags & SIInstrFlags::IsDOT;
815 }
816
817 static bool isWMMA(const MachineInstr &MI) {
818 return MI.getDesc().TSFlags & SIInstrFlags::IsWMMA;
819 }
820
821 bool isWMMA(uint16_t Opcode) const {
822 return get(Opcode).TSFlags & SIInstrFlags::IsWMMA;
823 }
824
825 static bool isMFMAorWMMA(const MachineInstr &MI) {
826 return isMFMA(MI) || isWMMA(MI) || isSWMMAC(MI);
827 }
828
829 static bool isSWMMAC(const MachineInstr &MI) {
830 return MI.getDesc().TSFlags & SIInstrFlags::IsSWMMAC;
831 }
832
833 bool isSWMMAC(uint16_t Opcode) const {
834 return get(Opcode).TSFlags & SIInstrFlags::IsSWMMAC;
835 }
836
837 bool isDOT(uint16_t Opcode) const {
838 return get(Opcode).TSFlags & SIInstrFlags::IsDOT;
839 }
840
841 static bool isLDSDIR(const MachineInstr &MI) {
842 return MI.getDesc().TSFlags & SIInstrFlags::LDSDIR;
843 }
844
845 bool isLDSDIR(uint16_t Opcode) const {
846 return get(Opcode).TSFlags & SIInstrFlags::LDSDIR;
847 }
848
849 static bool isVINTERP(const MachineInstr &MI) {
850 return MI.getDesc().TSFlags & SIInstrFlags::VINTERP;
851 }
852
853 bool isVINTERP(uint16_t Opcode) const {
854 return get(Opcode).TSFlags & SIInstrFlags::VINTERP;
855 }
856
857 static bool isScalarUnit(const MachineInstr &MI) {
858 return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD);
859 }
860
861 static bool usesVM_CNT(const MachineInstr &MI) {
862 return MI.getDesc().TSFlags & SIInstrFlags::VM_CNT;
863 }
864
865 static bool usesLGKM_CNT(const MachineInstr &MI) {
866 return MI.getDesc().TSFlags & SIInstrFlags::LGKM_CNT;
867 }
868
869 // Most sopk treat the immediate as a signed 16-bit, however some
870 // use it as unsigned.
871 static bool sopkIsZext(unsigned Opcode) {
872 return Opcode == AMDGPU::S_CMPK_EQ_U32 || Opcode == AMDGPU::S_CMPK_LG_U32 ||
873 Opcode == AMDGPU::S_CMPK_GT_U32 || Opcode == AMDGPU::S_CMPK_GE_U32 ||
874 Opcode == AMDGPU::S_CMPK_LT_U32 || Opcode == AMDGPU::S_CMPK_LE_U32 ||
875 Opcode == AMDGPU::S_GETREG_B32;
876 }
877
878 /// \returns true if this is an s_store_dword* instruction. This is more
879 /// specific than isSMEM && mayStore.
880 static bool isScalarStore(const MachineInstr &MI) {
881 return MI.getDesc().TSFlags & SIInstrFlags::SCALAR_STORE;
882 }
883
884 bool isScalarStore(uint16_t Opcode) const {
885 return get(Opcode).TSFlags & SIInstrFlags::SCALAR_STORE;
886 }
887
888 static bool isFixedSize(const MachineInstr &MI) {
889 return MI.getDesc().TSFlags & SIInstrFlags::FIXED_SIZE;
890 }
891
892 bool isFixedSize(uint16_t Opcode) const {
893 return get(Opcode).TSFlags & SIInstrFlags::FIXED_SIZE;
894 }
895
896 static bool hasFPClamp(const MachineInstr &MI) {
897 return MI.getDesc().TSFlags & SIInstrFlags::FPClamp;
898 }
899
900 bool hasFPClamp(uint16_t Opcode) const {
901 return get(Opcode).TSFlags & SIInstrFlags::FPClamp;
902 }
903
904 static bool hasIntClamp(const MachineInstr &MI) {
905 return MI.getDesc().TSFlags & SIInstrFlags::IntClamp;
906 }
907
909 const uint64_t ClampFlags = SIInstrFlags::FPClamp |
913 return MI.getDesc().TSFlags & ClampFlags;
914 }
915
916 static bool usesFPDPRounding(const MachineInstr &MI) {
917 return MI.getDesc().TSFlags & SIInstrFlags::FPDPRounding;
918 }
919
920 bool usesFPDPRounding(uint16_t Opcode) const {
921 return get(Opcode).TSFlags & SIInstrFlags::FPDPRounding;
922 }
923
924 static bool isFPAtomic(const MachineInstr &MI) {
925 return MI.getDesc().TSFlags & SIInstrFlags::FPAtomic;
926 }
927
928 bool isFPAtomic(uint16_t Opcode) const {
929 return get(Opcode).TSFlags & SIInstrFlags::FPAtomic;
930 }
931
932 static bool isNeverUniform(const MachineInstr &MI) {
933 return MI.getDesc().TSFlags & SIInstrFlags::IsNeverUniform;
934 }
935
936 // Check to see if opcode is for a barrier start. Pre gfx12 this is just the
937 // S_BARRIER, but after support for S_BARRIER_SIGNAL* / S_BARRIER_WAIT we want
938 // to check for the barrier start (S_BARRIER_SIGNAL*)
939 bool isBarrierStart(unsigned Opcode) const {
940 return Opcode == AMDGPU::S_BARRIER ||
941 Opcode == AMDGPU::S_BARRIER_SIGNAL_M0 ||
942 Opcode == AMDGPU::S_BARRIER_SIGNAL_ISFIRST_M0 ||
943 Opcode == AMDGPU::S_BARRIER_SIGNAL_IMM ||
944 Opcode == AMDGPU::S_BARRIER_SIGNAL_ISFIRST_IMM;
945 }
946
947 bool isBarrier(unsigned Opcode) const {
948 return isBarrierStart(Opcode) || Opcode == AMDGPU::S_BARRIER_WAIT ||
949 Opcode == AMDGPU::S_BARRIER_INIT_M0 ||
950 Opcode == AMDGPU::S_BARRIER_INIT_IMM ||
951 Opcode == AMDGPU::S_BARRIER_JOIN_IMM ||
952 Opcode == AMDGPU::S_BARRIER_LEAVE ||
953 Opcode == AMDGPU::S_BARRIER_LEAVE_IMM ||
954 Opcode == AMDGPU::DS_GWS_INIT || Opcode == AMDGPU::DS_GWS_BARRIER;
955 }
956
957 static bool isF16PseudoScalarTrans(unsigned Opcode) {
958 return Opcode == AMDGPU::V_S_EXP_F16_e64 ||
959 Opcode == AMDGPU::V_S_LOG_F16_e64 ||
960 Opcode == AMDGPU::V_S_RCP_F16_e64 ||
961 Opcode == AMDGPU::V_S_RSQ_F16_e64 ||
962 Opcode == AMDGPU::V_S_SQRT_F16_e64;
963 }
964
966 return MI.getDesc().TSFlags & SIInstrFlags::TiedSourceNotRead;
967 }
968
969 bool doesNotReadTiedSource(uint16_t Opcode) const {
970 return get(Opcode).TSFlags & SIInstrFlags::TiedSourceNotRead;
971 }
972
973 bool isIGLP(unsigned Opcode) const {
974 return Opcode == AMDGPU::SCHED_BARRIER ||
975 Opcode == AMDGPU::SCHED_GROUP_BARRIER || Opcode == AMDGPU::IGLP_OPT;
976 }
977
978 bool isIGLP(const MachineInstr &MI) const { return isIGLP(MI.getOpcode()); }
979
980 static unsigned getNonSoftWaitcntOpcode(unsigned Opcode) {
981 switch (Opcode) {
982 case AMDGPU::S_WAITCNT_soft:
983 return AMDGPU::S_WAITCNT;
984 case AMDGPU::S_WAITCNT_VSCNT_soft:
985 return AMDGPU::S_WAITCNT_VSCNT;
986 case AMDGPU::S_WAIT_LOADCNT_soft:
987 return AMDGPU::S_WAIT_LOADCNT;
988 case AMDGPU::S_WAIT_STORECNT_soft:
989 return AMDGPU::S_WAIT_STORECNT;
990 case AMDGPU::S_WAIT_SAMPLECNT_soft:
991 return AMDGPU::S_WAIT_SAMPLECNT;
992 case AMDGPU::S_WAIT_BVHCNT_soft:
993 return AMDGPU::S_WAIT_BVHCNT;
994 case AMDGPU::S_WAIT_DSCNT_soft:
995 return AMDGPU::S_WAIT_DSCNT;
996 case AMDGPU::S_WAIT_KMCNT_soft:
997 return AMDGPU::S_WAIT_KMCNT;
998 default:
999 return Opcode;
1000 }
1001 }
1002
1003 bool isWaitcnt(unsigned Opcode) const {
1004 switch (getNonSoftWaitcntOpcode(Opcode)) {
1005 case AMDGPU::S_WAITCNT:
1006 case AMDGPU::S_WAITCNT_VSCNT:
1007 case AMDGPU::S_WAITCNT_VMCNT:
1008 case AMDGPU::S_WAITCNT_EXPCNT:
1009 case AMDGPU::S_WAITCNT_LGKMCNT:
1010 case AMDGPU::S_WAIT_LOADCNT:
1011 case AMDGPU::S_WAIT_LOADCNT_DSCNT:
1012 case AMDGPU::S_WAIT_STORECNT:
1013 case AMDGPU::S_WAIT_STORECNT_DSCNT:
1014 case AMDGPU::S_WAIT_SAMPLECNT:
1015 case AMDGPU::S_WAIT_BVHCNT:
1016 case AMDGPU::S_WAIT_EXPCNT:
1017 case AMDGPU::S_WAIT_DSCNT:
1018 case AMDGPU::S_WAIT_KMCNT:
1019 case AMDGPU::S_WAIT_IDLE:
1020 return true;
1021 default:
1022 return false;
1023 }
1024 }
1025
1026 bool isVGPRCopy(const MachineInstr &MI) const {
1027 assert(isCopyInstr(MI));
1028 Register Dest = MI.getOperand(0).getReg();
1029 const MachineFunction &MF = *MI.getParent()->getParent();
1030 const MachineRegisterInfo &MRI = MF.getRegInfo();
1031 return !RI.isSGPRReg(MRI, Dest);
1032 }
1033
1034 bool hasVGPRUses(const MachineInstr &MI) const {
1035 const MachineFunction &MF = *MI.getParent()->getParent();
1036 const MachineRegisterInfo &MRI = MF.getRegInfo();
1037 return llvm::any_of(MI.explicit_uses(),
1038 [&MRI, this](const MachineOperand &MO) {
1039 return MO.isReg() && RI.isVGPR(MRI, MO.getReg());});
1040 }
1041
1042 /// Return true if the instruction modifies the mode register.q
1043 static bool modifiesModeRegister(const MachineInstr &MI);
1044
1045 /// This function is used to determine if an instruction can be safely
1046 /// executed under EXEC = 0 without hardware error, indeterminate results,
1047 /// and/or visible effects on future vector execution or outside the shader.
1048 /// Note: as of 2024 the only use of this is SIPreEmitPeephole where it is
1049 /// used in removing branches over short EXEC = 0 sequences.
1050 /// As such it embeds certain assumptions which may not apply to every case
1051 /// of EXEC = 0 execution.
1053
1054 /// Returns true if the instruction could potentially depend on the value of
1055 /// exec. If false, exec dependencies may safely be ignored.
1056 bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const;
1057
1058 bool isInlineConstant(const APInt &Imm) const;
1059
1060 bool isInlineConstant(const APFloat &Imm) const;
1061
1062 // Returns true if this non-register operand definitely does not need to be
1063 // encoded as a 32-bit literal. Note that this function handles all kinds of
1064 // operands, not just immediates.
1065 //
1066 // Some operands like FrameIndexes could resolve to an inline immediate value
1067 // that will not require an additional 4-bytes; this function assumes that it
1068 // will.
1069 bool isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const;
1070
1072 const MCOperandInfo &OpInfo) const {
1073 return isInlineConstant(MO, OpInfo.OperandType);
1074 }
1075
1076 /// \p returns true if \p UseMO is substituted with \p DefMO in \p MI it would
1077 /// be an inline immediate.
1079 const MachineOperand &UseMO,
1080 const MachineOperand &DefMO) const {
1081 assert(UseMO.getParent() == &MI);
1082 int OpIdx = UseMO.getOperandNo();
1083 if (OpIdx >= MI.getDesc().NumOperands)
1084 return false;
1085
1086 return isInlineConstant(DefMO, MI.getDesc().operands()[OpIdx]);
1087 }
1088
1089 /// \p returns true if the operand \p OpIdx in \p MI is a valid inline
1090 /// immediate.
1091 bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const {
1092 const MachineOperand &MO = MI.getOperand(OpIdx);
1093 return isInlineConstant(MO, MI.getDesc().operands()[OpIdx].OperandType);
1094 }
1095
1096 bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
1097 const MachineOperand &MO) const {
1098 if (OpIdx >= MI.getDesc().NumOperands)
1099 return false;
1100
1101 if (isCopyInstr(MI)) {
1102 unsigned Size = getOpSize(MI, OpIdx);
1103 assert(Size == 8 || Size == 4);
1104
1105 uint8_t OpType = (Size == 8) ?
1107 return isInlineConstant(MO, OpType);
1108 }
1109
1110 return isInlineConstant(MO, MI.getDesc().operands()[OpIdx].OperandType);
1111 }
1112
1113 bool isInlineConstant(const MachineOperand &MO) const {
1114 return isInlineConstant(*MO.getParent(), MO.getOperandNo());
1115 }
1116
1117 bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
1118 const MachineOperand &MO) const;
1119
1120 /// Return true if this 64-bit VALU instruction has a 32-bit encoding.
1121 /// This function will return false if you pass it a 32-bit instruction.
1122 bool hasVALU32BitEncoding(unsigned Opcode) const;
1123
1124 /// Returns true if this operand uses the constant bus.
1126 const MachineOperand &MO,
1127 const MCOperandInfo &OpInfo) const;
1128
1130 int OpIdx) const {
1131 return usesConstantBus(MRI, MI.getOperand(OpIdx),
1132 MI.getDesc().operands()[OpIdx]);
1133 }
1134
1135 /// Return true if this instruction has any modifiers.
1136 /// e.g. src[012]_mod, omod, clamp.
1137 bool hasModifiers(unsigned Opcode) const;
1138
1139 bool hasModifiersSet(const MachineInstr &MI,
1140 unsigned OpName) const;
1141 bool hasAnyModifiersSet(const MachineInstr &MI) const;
1142
1143 bool canShrink(const MachineInstr &MI,
1144 const MachineRegisterInfo &MRI) const;
1145
1147 unsigned NewOpcode) const;
1148
1149 bool verifyInstruction(const MachineInstr &MI,
1150 StringRef &ErrInfo) const override;
1151
1152 unsigned getVALUOp(const MachineInstr &MI) const;
1153
1156 const DebugLoc &DL, Register Reg, bool IsSCCLive,
1157 SlotIndexes *Indexes = nullptr) const;
1158
1161 Register Reg, SlotIndexes *Indexes = nullptr) const;
1162
1163 /// Return the correct register class for \p OpNo. For target-specific
1164 /// instructions, this will return the register class that has been defined
1165 /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
1166 /// the register class of its machine operand.
1167 /// to infer the correct register class base on the other operands.
1169 unsigned OpNo) const;
1170
1171 /// Return the size in bytes of the operand OpNo on the given
1172 // instruction opcode.
1173 unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
1174 const MCOperandInfo &OpInfo = get(Opcode).operands()[OpNo];
1175
1176 if (OpInfo.RegClass == -1) {
1177 // If this is an immediate operand, this must be a 32-bit literal.
1179 return 4;
1180 }
1181
1182 return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;
1183 }
1184
1185 /// This form should usually be preferred since it handles operands
1186 /// with unknown register classes.
1187 unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
1188 const MachineOperand &MO = MI.getOperand(OpNo);
1189 if (MO.isReg()) {
1190 if (unsigned SubReg = MO.getSubReg()) {
1191 return RI.getSubRegIdxSize(SubReg) / 8;
1192 }
1193 }
1194 return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
1195 }
1196
1197 /// Legalize the \p OpIndex operand of this instruction by inserting
1198 /// a MOV. For example:
1199 /// ADD_I32_e32 VGPR0, 15
1200 /// to
1201 /// MOV VGPR1, 15
1202 /// ADD_I32_e32 VGPR0, VGPR1
1203 ///
1204 /// If the operand being legalized is a register, then a COPY will be used
1205 /// instead of MOV.
1206 void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const;
1207
1208 /// Check if \p MO is a legal operand if it was the \p OpIdx Operand
1209 /// for \p MI.
1210 bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
1211 const MachineOperand *MO = nullptr) const;
1212
1213 /// Check if \p MO would be a valid operand for the given operand
1214 /// definition \p OpInfo. Note this does not attempt to validate constant bus
1215 /// restrictions (e.g. literal constant usage).
1217 const MCOperandInfo &OpInfo,
1218 const MachineOperand &MO) const;
1219
1220 /// Check if \p MO (a register operand) is a legal register for the
1221 /// given operand description.
1223 const MCOperandInfo &OpInfo,
1224 const MachineOperand &MO) const;
1225
1226 /// Legalize operands in \p MI by either commuting it or inserting a
1227 /// copy of src1.
1229
1230 /// Fix operands in \p MI to satisfy constant bus requirements.
1232
1233 /// Copy a value from a VGPR (\p SrcReg) to SGPR. The desired register class
1234 /// for the dst register (\p DstRC) can be optionally supplied. This function
1235 /// can only be used when it is know that the value in SrcReg is same across
1236 /// all threads in the wave.
1237 /// \returns The SGPR register that \p SrcReg was copied to.
1240 const TargetRegisterClass *DstRC = nullptr) const;
1241
1244
1247 const TargetRegisterClass *DstRC,
1249 const DebugLoc &DL) const;
1250
1251 /// Legalize all operands in this instruction. This function may create new
1252 /// instructions and control-flow around \p MI. If present, \p MDT is
1253 /// updated.
1254 /// \returns A new basic block that contains \p MI if new blocks were created.
1256 legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT = nullptr) const;
1257
1258 /// Change SADDR form of a FLAT \p Inst to its VADDR form if saddr operand
1259 /// was moved to VGPR. \returns true if succeeded.
1260 bool moveFlatAddrToVGPR(MachineInstr &Inst) const;
1261
1262 /// Replace the instructions opcode with the equivalent VALU
1263 /// opcode. This function will also move the users of MachineInstruntions
1264 /// in the \p WorkList to the VALU if necessary. If present, \p MDT is
1265 /// updated.
1266 void moveToVALU(SIInstrWorklist &Worklist, MachineDominatorTree *MDT) const;
1267
1269 MachineInstr &Inst) const;
1270
1272 MachineBasicBlock::iterator MI) const override;
1273
1275 unsigned Quantity) const override;
1276
1277 void insertReturn(MachineBasicBlock &MBB) const;
1278
1279 /// Build instructions that simulate the behavior of a `s_trap 2` instructions
1280 /// for hardware (namely, gfx11) that runs in PRIV=1 mode. There, s_trap is
1281 /// interpreted as a nop.
1285 const DebugLoc &DL) const;
1286
1287 /// Return the number of wait states that result from executing this
1288 /// instruction.
1289 static unsigned getNumWaitStates(const MachineInstr &MI);
1290
1291 /// Returns the operand named \p Op. If \p MI does not have an
1292 /// operand named \c Op, this function returns nullptr.
1294 MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
1295
1298 unsigned OpName) const {
1299 return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
1300 }
1301
1302 /// Get required immediate operand
1303 int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const {
1304 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OpName);
1305 return MI.getOperand(Idx).getImm();
1306 }
1307
1310
1311 bool isLowLatencyInstruction(const MachineInstr &MI) const;
1312 bool isHighLatencyDef(int Opc) const override;
1313
1314 /// Return the descriptor of the target-specific machine instruction
1315 /// that corresponds to the specified pseudo or native opcode.
1316 const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const {
1317 return get(pseudoToMCOpcode(Opcode));
1318 }
1319
1320 unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1321 unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1322
1324 int &FrameIndex) const override;
1326 int &FrameIndex) const override;
1327
1328 unsigned getInstBundleSize(const MachineInstr &MI) const;
1329 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
1330
1331 bool mayAccessFlatAddressSpace(const MachineInstr &MI) const;
1332
1333 std::pair<unsigned, unsigned>
1334 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
1335
1337 getSerializableTargetIndices() const override;
1338
1341
1344
1347 const ScheduleDAG *DAG) const override;
1348
1350 CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const override;
1351
1354 const ScheduleDAGMI *DAG) const override;
1355
1357 const MachineFunction &MF) const override;
1358
1360 Register Reg = Register()) const override;
1361
1364 const DebugLoc &DL, Register Src,
1365 Register Dst) const override;
1366
1369 const DebugLoc &DL, Register Src,
1370 unsigned SrcSubReg,
1371 Register Dst) const override;
1372
1373 bool isWave32() const;
1374
1375 /// Return a partially built integer add instruction without carry.
1376 /// Caller must add source operands.
1377 /// For pre-GFX9 it will generate unused carry destination operand.
1378 /// TODO: After GFX9 it should return a no-carry operation.
1381 const DebugLoc &DL,
1382 Register DestReg) const;
1383
1386 const DebugLoc &DL,
1387 Register DestReg,
1388 RegScavenger &RS) const;
1389
1390 static bool isKillTerminator(unsigned Opcode);
1391 const MCInstrDesc &getKillTerminatorFromPseudo(unsigned Opcode) const;
1392
1393 bool isLegalMUBUFImmOffset(unsigned Imm) const;
1394
1395 static unsigned getMaxMUBUFImmOffset(const GCNSubtarget &ST);
1396
1397 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
1398 Align Alignment = Align(4)) const;
1399
1400 /// Returns if \p Offset is legal for the subtarget as the offset to a FLAT
1401 /// encoded instruction. If \p Signed, this is for an instruction that
1402 /// interprets the offset as signed.
1403 bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace,
1404 uint64_t FlatVariant) const;
1405
1406 /// Split \p COffsetVal into {immediate offset field, remainder offset}
1407 /// values.
1408 std::pair<int64_t, int64_t> splitFlatOffset(int64_t COffsetVal,
1409 unsigned AddrSpace,
1410 uint64_t FlatVariant) const;
1411
1412 /// Returns true if negative offsets are allowed for the given \p FlatVariant.
1413 bool allowNegativeFlatOffset(uint64_t FlatVariant) const;
1414
1415 /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
1416 /// Return -1 if the target-specific opcode for the pseudo instruction does
1417 /// not exist. If Opcode is not a pseudo instruction, this is identity.
1418 int pseudoToMCOpcode(int Opcode) const;
1419
1420 /// \brief Check if this instruction should only be used by assembler.
1421 /// Return true if this opcode should not be used by codegen.
1422 bool isAsmOnlyOpcode(int MCOp) const;
1423
1424 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
1425 const TargetRegisterInfo *TRI,
1426 const MachineFunction &MF)
1427 const override;
1428
1429 void fixImplicitOperands(MachineInstr &MI) const;
1430
1434 int FrameIndex,
1435 LiveIntervals *LIS = nullptr,
1436 VirtRegMap *VRM = nullptr) const override;
1437
1438 unsigned getInstrLatency(const InstrItineraryData *ItinData,
1439 const MachineInstr &MI,
1440 unsigned *PredCost = nullptr) const override;
1441
1443 getInstructionUniformity(const MachineInstr &MI) const override final;
1444
1447
1448 const MIRFormatter *getMIRFormatter() const override {
1449 if (!Formatter)
1450 Formatter = std::make_unique<AMDGPUMIRFormatter>();
1451 return Formatter.get();
1452 }
1453
1454 static unsigned getDSShaderTypeValue(const MachineFunction &MF);
1455
1456 const TargetSchedModel &getSchedModel() const { return SchedModel; }
1457
1458 // Enforce operand's \p OpName even alignment if required by target.
1459 // This is used if an operand is a 32 bit register but needs to be aligned
1460 // regardless.
1461 void enforceOperandRCAlignment(MachineInstr &MI, unsigned OpName) const;
1462};
1463
1464/// \brief Returns true if a reg:subreg pair P has a TRC class
1466 const TargetRegisterClass &TRC,
1468 auto *RC = MRI.getRegClass(P.Reg);
1469 if (!P.SubReg)
1470 return RC == &TRC;
1471 auto *TRI = MRI.getTargetRegisterInfo();
1472 return RC == TRI->getMatchingSuperRegClass(RC, &TRC, P.SubReg);
1473}
1474
1475/// \brief Create RegSubRegPair from a register MachineOperand
1476inline
1478 assert(O.isReg());
1479 return TargetInstrInfo::RegSubRegPair(O.getReg(), O.getSubReg());
1480}
1481
1482/// \brief Return the SubReg component from REG_SEQUENCE
1483TargetInstrInfo::RegSubRegPair getRegSequenceSubReg(MachineInstr &MI,
1484 unsigned SubReg);
1485
1486/// \brief Return the defining instruction for a given reg:subreg pair
1487/// skipping copy like instructions and subreg-manipulation pseudos.
1488/// Following another subreg of a reg:subreg isn't supported.
1489MachineInstr *getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P,
1490 MachineRegisterInfo &MRI);
1491
1492/// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1493/// DefMI and the use at \p UseMI. Should be run on SSA. Currently does not
1494/// attempt to track between blocks.
1495bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI,
1496 Register VReg,
1497 const MachineInstr &DefMI,
1498 const MachineInstr &UseMI);
1499
1500/// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1501/// DefMI and all its uses. Should be run on SSA. Currently does not attempt to
1502/// track between blocks.
1503bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI,
1504 Register VReg,
1505 const MachineInstr &DefMI);
1506
1507namespace AMDGPU {
1508
1510 int getVOPe64(uint16_t Opcode);
1511
1513 int getVOPe32(uint16_t Opcode);
1514
1516 int getSDWAOp(uint16_t Opcode);
1517
1520
1523
1526
1529
1532
1535
1536 /// Check if \p Opcode is an Addr64 opcode.
1537 ///
1538 /// \returns \p Opcode if it is an Addr64 opcode, otherwise -1.
1541
1543 int getSOPKOp(uint16_t Opcode);
1544
1545 /// \returns SADDR form of a FLAT Global instruction given an \p Opcode
1546 /// of a VADDR form.
1549
1550 /// \returns VADDR form of a FLAT Global instruction given an \p Opcode
1551 /// of a SADDR form.
1554
1557
1558 /// \returns ST form with only immediate offset of a FLAT Scratch instruction
1559 /// given an \p Opcode of an SS (SADDR) form.
1562
1563 /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
1564 /// of an SVS (SADDR + VADDR) form.
1567
1568 /// \returns SS (SADDR) form of a FLAT Scratch instruction given an \p Opcode
1569 /// of an SV (VADDR) form.
1572
1573 /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
1574 /// of an SS (SADDR) form.
1577
1578 /// \returns earlyclobber version of a MAC MFMA is exists.
1581
1582 /// \returns Version of an MFMA instruction which uses AGPRs for srcC and
1583 /// vdst, given an \p Opcode of an MFMA which uses VGPRs for srcC/vdst.
1586
1587 /// \returns v_cmpx version of a v_cmp instruction.
1590
1591 const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
1594 const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23);
1595
1596} // end namespace AMDGPU
1597
1598namespace AMDGPU {
1600 // For sgpr to vgpr spill instructions
1603} // namespace AMDGPU
1604
1605namespace SI {
1606namespace KernelInputOffsets {
1607
1608/// Offsets in bytes from the start of the input buffer
1618 LOCAL_SIZE_Z = 32
1620
1621} // end namespace KernelInputOffsets
1622} // end namespace SI
1623
1624} // end namespace llvm
1625
1626#endif // LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
unsigned SubReg
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Provides AMDGPU specific target descriptions.
AMDGPU specific overrides of MIRFormatter.
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
#define LLVM_READONLY
Definition: Compiler.h:306
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
uint64_t Size
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
uint64_t IntrinsicInst * II
#define P(N)
StandardInstrumentations SI(Mod->getContext(), Debug, VerifyEach)
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Interface definition for SIRegisterInfo.
This file implements a set that has insertion order iteration characteristics.
Class for arbitrary precision integers.
Definition: APInt.h:78
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
This class represents an Operation in the Expression.
A debug info location.
Definition: DebugLoc.h:33
Itinerary data supplied by a subtarget to be used by a target.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:85
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:97
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:91
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
MIRFormater - Interface to format MIR operand based on target.
Definition: MIRFormatter.h:32
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
Definition: MachineInstr.h:69
Flags
Flags values. These may be or'd together.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
unsigned getOperandNo() const
Returns the index of this operand in the instruction that it belongs to.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Represents one node in the SelectionDAG.
bool isLegalMUBUFImmOffset(unsigned Imm) const
bool isFLATGlobal(uint16_t Opcode) const
Definition: SIInstrInfo.h:640
bool isInlineConstant(const APInt &Imm) const
static bool isMAI(const MachineInstr &MI)
Definition: SIInstrInfo.h:800
void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const
Fix operands in MI to satisfy constant bus requirements.
static bool isDS(const MachineInstr &MI)
Definition: SIInstrInfo.h:562
static bool isVMEM(const MachineInstr &MI)
Definition: SIInstrInfo.h:440
MachineBasicBlock * legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
Legalize all operands in this instruction.
bool areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, int64_t &Offset0, int64_t &Offset1) const override
static bool isVOP3(const MachineInstr &MI)
Definition: SIInstrInfo.h:512
unsigned getLiveRangeSplitOpcode(Register Reg, const MachineFunction &MF) const override
bool isSMRD(uint16_t Opcode) const
Definition: SIInstrInfo.h:556
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const final
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
static bool isNeverUniform(const MachineInstr &MI)
Definition: SIInstrInfo.h:932
unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const
Return the size in bytes of the operand OpNo on the given.
Definition: SIInstrInfo.h:1173
bool isAtomic(uint16_t Opcode) const
Definition: SIInstrInfo.h:694
bool isBasicBlockPrologue(const MachineInstr &MI, Register Reg=Register()) const override
bool isLDSDIR(uint16_t Opcode) const
Definition: SIInstrInfo.h:845
bool isFLATScratch(uint16_t Opcode) const
Definition: SIInstrInfo.h:648
uint64_t getDefaultRsrcDataFormat() const
static bool isSOPP(const MachineInstr &MI)
Definition: SIInstrInfo.h:480
InstructionUniformity getGenericInstructionUniformity(const MachineInstr &MI) const
bool hasVGPRUses(const MachineInstr &MI) const
Definition: SIInstrInfo.h:1034
uint64_t getClampMask(const MachineInstr &MI) const
Definition: SIInstrInfo.h:908
bool isIGLP(unsigned Opcode) const
Definition: SIInstrInfo.h:973
static bool isFLATScratch(const MachineInstr &MI)
Definition: SIInstrInfo.h:644
const MCInstrDesc & getIndirectRegWriteMovRelPseudo(unsigned VecSize, unsigned EltSize, bool IsSGPR) const
static bool isSpill(const MachineInstr &MI)
Definition: SIInstrInfo.h:752
MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg) const
Return a partially built integer add instruction without carry.
bool mayAccessFlatAddressSpace(const MachineInstr &MI) const
bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0, int64_t Offset1, unsigned NumLoads) const override
bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, Align Alignment=Align(4)) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
void moveToVALU(SIInstrWorklist &Worklist, MachineDominatorTree *MDT) const
Replace the instructions opcode with the equivalent VALU opcode.
static bool isSMRD(const MachineInstr &MI)
Definition: SIInstrInfo.h:552
void restoreExec(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register Reg, SlotIndexes *Indexes=nullptr) const
bool isVGPRSpill(uint16_t Opcode) const
Definition: SIInstrInfo.h:730
bool usesConstantBus(const MachineRegisterInfo &MRI, const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Returns true if this operand uses the constant bus.
static unsigned getMaxMUBUFImmOffset(const GCNSubtarget &ST)
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
void legalizeOperandsFLAT(MachineRegisterInfo &MRI, MachineInstr &MI) const
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
bool isSegmentSpecificFLAT(uint16_t Opcode) const
Definition: SIInstrInfo.h:631
int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const
Get required immediate operand.
Definition: SIInstrInfo.h:1303
bool usesConstantBus(const MachineRegisterInfo &MRI, const MachineInstr &MI, int OpIdx) const
Definition: SIInstrInfo.h:1129
bool isVSAMPLE(uint16_t Opcode) const
Definition: SIInstrInfo.h:608
bool isPacked(uint16_t Opcode) const
Definition: SIInstrInfo.h:492
static bool isMTBUF(const MachineInstr &MI)
Definition: SIInstrInfo.h:544
const MCInstrDesc & getIndirectGPRIDXPseudo(unsigned VecSize, bool IsIndirectSrc) const
void insertReturn(MachineBasicBlock &MBB) const
static bool isEXP(const MachineInstr &MI)
Definition: SIInstrInfo.h:657
static bool isSALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:416
bool isVIMAGE(uint16_t Opcode) const
Definition: SIInstrInfo.h:600
void legalizeGenericOperand(MachineBasicBlock &InsertMBB, MachineBasicBlock::iterator I, const TargetRegisterClass *DstRC, MachineOperand &Op, MachineRegisterInfo &MRI, const DebugLoc &DL) const
MachineInstr * buildShrunkInst(MachineInstr &MI, unsigned NewOpcode) const
unsigned getInstBundleSize(const MachineInstr &MI) const
static bool isVOP2(const MachineInstr &MI)
Definition: SIInstrInfo.h:504
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
static bool isSDWA(const MachineInstr &MI)
Definition: SIInstrInfo.h:520
bool isSOP1(uint16_t Opcode) const
Definition: SIInstrInfo.h:452
const MCInstrDesc & getKillTerminatorFromPseudo(unsigned Opcode) const
static bool mayWriteLDSThroughDMA(const MachineInstr &MI)
Definition: SIInstrInfo.h:699
void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Quantity) const override
static bool isVINTRP(const MachineInstr &MI)
Definition: SIInstrInfo.h:792
bool isSWMMAC(uint16_t Opcode) const
Definition: SIInstrInfo.h:833
bool isAtomicRet(uint16_t Opcode) const
Definition: SIInstrInfo.h:685
static bool isGather4(const MachineInstr &MI)
Definition: SIInstrInfo.h:612
static bool isMFMAorWMMA(const MachineInstr &MI)
Definition: SIInstrInfo.h:825
static bool isWQM(const MachineInstr &MI)
Definition: SIInstrInfo.h:703
static bool doesNotReadTiedSource(const MachineInstr &MI)
Definition: SIInstrInfo.h:965
bool isLegalVSrcOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO would be a valid operand for the given operand definition OpInfo.
bool isSOPC(uint16_t Opcode) const
Definition: SIInstrInfo.h:468
static bool isDOT(const MachineInstr &MI)
Definition: SIInstrInfo.h:813
static bool usesFPDPRounding(const MachineInstr &MI)
Definition: SIInstrInfo.h:916
bool isFixedSize(uint16_t Opcode) const
Definition: SIInstrInfo.h:892
bool isImage(uint16_t Opcode) const
Definition: SIInstrInfo.h:436
MachineInstr * createPHISourceCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, unsigned SrcSubReg, Register Dst) const override
bool isGWS(uint16_t Opcode) const
Definition: SIInstrInfo.h:582
bool isInlineConstant(const MachineOperand &MO) const
Definition: SIInstrInfo.h:1113
bool hasModifiers(unsigned Opcode) const
Return true if this instruction has any modifiers.
bool isVOP3(uint16_t Opcode) const
Definition: SIInstrInfo.h:516
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override
static bool isSWMMAC(const MachineInstr &MI)
Definition: SIInstrInfo.h:829
ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *II, const ScheduleDAGMI *DAG) const override
bool isDOT(uint16_t Opcode) const
Definition: SIInstrInfo.h:837
bool isWave32() const
bool isHighLatencyDef(int Opc) const override
void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const
Legalize the OpIndex operand of this instruction by inserting a MOV.
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
static bool isVOPC(const MachineInstr &MI)
Definition: SIInstrInfo.h:528
void removeModOperands(MachineInstr &MI) const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
std::pair< int64_t, int64_t > splitFlatOffset(int64_t COffsetVal, unsigned AddrSpace, uint64_t FlatVariant) const
Split COffsetVal into {immediate offset field, remainder offset} values.
bool isGather4(uint16_t Opcode) const
Definition: SIInstrInfo.h:616
bool isSpill(uint16_t Opcode) const
Definition: SIInstrInfo.h:748
bool isFLAT(uint16_t Opcode) const
Definition: SIInstrInfo.h:653
static bool isVIMAGE(const MachineInstr &MI)
Definition: SIInstrInfo.h:596
static bool isLDSDIR(const MachineInstr &MI)
Definition: SIInstrInfo.h:841
static bool isSOP2(const MachineInstr &MI)
Definition: SIInstrInfo.h:456
static bool isGWS(const MachineInstr &MI)
Definition: SIInstrInfo.h:578
const TargetSchedModel & getSchedModel() const
Definition: SIInstrInfo.h:1456
bool isVOPC(uint16_t Opcode) const
Definition: SIInstrInfo.h:532
bool isInlineConstant(const MachineInstr &MI, const MachineOperand &UseMO, const MachineOperand &DefMO) const
returns true if UseMO is substituted with DefMO in MI it would be an inline immediate.
Definition: SIInstrInfo.h:1078
LLVM_READONLY MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
const MIRFormatter * getMIRFormatter() const override
Definition: SIInstrInfo.h:1448
const TargetRegisterClass * getPreferredSelectRegClass(unsigned Size) const
bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override
bool swapSourceModifiers(MachineInstr &MI, MachineOperand &Src0, unsigned Src0OpName, MachineOperand &Src1, unsigned Src1OpName) const
bool isMAI(uint16_t Opcode) const
Definition: SIInstrInfo.h:804
static bool isFLATGlobal(const MachineInstr &MI)
Definition: SIInstrInfo.h:636
unsigned getMachineCSELookAheadLimit() const override
Definition: SIInstrInfo.h:407
bool isGlobalMemoryObject(const MachineInstr *MI) const override
static bool isVSAMPLE(const MachineInstr &MI)
Definition: SIInstrInfo.h:604
static bool isAtomicRet(const MachineInstr &MI)
Definition: SIInstrInfo.h:681
bool isBufferSMRD(const MachineInstr &MI) const
static bool isKillTerminator(unsigned Opcode)
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx0, unsigned &SrcOpIdx1) const override
const GCNSubtarget & getSubtarget() const
Definition: SIInstrInfo.h:231
bool isDS(uint16_t Opcode) const
Definition: SIInstrInfo.h:566
void insertScratchExecCopy(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register Reg, bool IsSCCLive, SlotIndexes *Indexes=nullptr) const
bool isFPAtomic(uint16_t Opcode) const
Definition: SIInstrInfo.h:928
bool hasVALU32BitEncoding(unsigned Opcode) const
Return true if this 64-bit VALU instruction has a 32-bit encoding.
static bool isDisableWQM(const MachineInstr &MI)
Definition: SIInstrInfo.h:711
bool isAtomicNoRet(uint16_t Opcode) const
Definition: SIInstrInfo.h:677
unsigned getMovOpcode(const TargetRegisterClass *DstRC) const
unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
unsigned buildExtractSubReg(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, const MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const
Legalize operands in MI by either commuting it or inserting a copy of src1.
bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const final
static bool isTRANS(const MachineInstr &MI)
Definition: SIInstrInfo.h:776
static bool isImage(const MachineInstr &MI)
Definition: SIInstrInfo.h:432
static bool isSOPK(const MachineInstr &MI)
Definition: SIInstrInfo.h:472
const TargetRegisterClass * getOpRegClass(const MachineInstr &MI, unsigned OpNo) const
Return the correct register class for OpNo.
MachineBasicBlock * insertSimulatedTrap(MachineRegisterInfo &MRI, MachineBasicBlock &MBB, MachineInstr &MI, const DebugLoc &DL) const
Build instructions that simulate the behavior of a s_trap 2 instructions for hardware (namely,...
static unsigned getNonSoftWaitcntOpcode(unsigned Opcode)
Definition: SIInstrInfo.h:980
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const
returns true if the operand OpIdx in MI is a valid inline immediate.
Definition: SIInstrInfo.h:1091
static unsigned getDSShaderTypeValue(const MachineFunction &MF)
static bool isFoldableCopy(const MachineInstr &MI)
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo, const MachineOperand &MO) const
bool isIgnorableUse(const MachineOperand &MO) const override
static bool isVINTERP(const MachineInstr &MI)
Definition: SIInstrInfo.h:849
static bool isMUBUF(const MachineInstr &MI)
Definition: SIInstrInfo.h:536
bool expandPostRAPseudo(MachineInstr &MI) const override
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
bool isSALU(uint16_t Opcode) const
Definition: SIInstrInfo.h:420
bool isVOP2(uint16_t Opcode) const
Definition: SIInstrInfo.h:508
static bool hasFPClamp(const MachineInstr &MI)
Definition: SIInstrInfo.h:896
InstructionUniformity getInstructionUniformity(const MachineInstr &MI) const override final
static bool isSegmentSpecificFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:626
bool isSDWA(uint16_t Opcode) const
Definition: SIInstrInfo.h:524
unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const
This form should usually be preferred since it handles operands with unknown register classes.
Definition: SIInstrInfo.h:1187
bool isInlineConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Definition: SIInstrInfo.h:1071
bool isSOPK(uint16_t Opcode) const
Definition: SIInstrInfo.h:476
static bool isF16PseudoScalarTrans(unsigned Opcode)
Definition: SIInstrInfo.h:957
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
static bool isChainCallOpcode(uint64_t Opcode)
Definition: SIInstrInfo.h:763
static bool isDPP(const MachineInstr &MI)
Definition: SIInstrInfo.h:768
bool analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const
static bool isMFMA(const MachineInstr &MI)
Definition: SIInstrInfo.h:808
bool isSGPRSpill(uint16_t Opcode) const
Definition: SIInstrInfo.h:742
bool isLowLatencyInstruction(const MachineInstr &MI) const
bool isIGLP(const MachineInstr &MI) const
Definition: SIInstrInfo.h:978
static bool isScalarStore(const MachineInstr &MI)
Definition: SIInstrInfo.h:880
bool isTRANS(uint16_t Opcode) const
Definition: SIInstrInfo.h:780
void materializeImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DestReg, int64_t Value) const
bool isLDSDMA(uint16_t Opcode)
Definition: SIInstrInfo.h:574
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
bool isSOP2(uint16_t Opcode) const
Definition: SIInstrInfo.h:460
bool isVALU(uint16_t Opcode) const
Definition: SIInstrInfo.h:428
bool isVOP1(uint16_t Opcode) const
Definition: SIInstrInfo.h:500
bool isAlwaysGDS(uint16_t Opcode) const
bool isMUBUF(uint16_t Opcode) const
Definition: SIInstrInfo.h:540
static bool isFPAtomic(const MachineInstr &MI)
Definition: SIInstrInfo.h:924
static bool usesLGKM_CNT(const MachineInstr &MI)
Definition: SIInstrInfo.h:865
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
void moveToVALUImpl(SIInstrWorklist &Worklist, MachineDominatorTree *MDT, MachineInstr &Inst) const
static bool isPacked(const MachineInstr &MI)
Definition: SIInstrInfo.h:488
bool canShrink(const MachineInstr &MI, const MachineRegisterInfo &MRI) const
bool isAsmOnlyOpcode(int MCOp) const
Check if this instruction should only be used by assembler.
bool isWMMA(uint16_t Opcode) const
Definition: SIInstrInfo.h:821
bool isMTBUF(uint16_t Opcode) const
Definition: SIInstrInfo.h:548
bool isDisableWQM(uint16_t Opcode) const
Definition: SIInstrInfo.h:715
static bool isVGPRSpill(const MachineInstr &MI)
Definition: SIInstrInfo.h:724
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
This is used by the post-RA scheduler (SchedulePostRAList.cpp).
bool isWaitcnt(unsigned Opcode) const
Definition: SIInstrInfo.h:1003
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace, uint64_t FlatVariant) const
Returns if Offset is legal for the subtarget as the offset to a FLAT encoded instruction.
static bool isWWMRegSpillOpcode(uint16_t Opcode)
Definition: SIInstrInfo.h:756
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
bool isVMEM(uint16_t Opcode) const
Definition: SIInstrInfo.h:444
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const override
bool isVINTRP(uint16_t Opcode) const
Definition: SIInstrInfo.h:796
bool isVGPRCopy(const MachineInstr &MI) const
Definition: SIInstrInfo.h:1026
bool isScalarStore(uint16_t Opcode) const
Definition: SIInstrInfo.h:884
static bool isMIMG(const MachineInstr &MI)
Definition: SIInstrInfo.h:588
MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, const MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
bool isLegalRegOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO (a register operand) is a legal register for the given operand description.
bool allowNegativeFlatOffset(uint64_t FlatVariant) const
Returns true if negative offsets are allowed for the given FlatVariant.
LLVM_READONLY int commuteOpcode(const MachineInstr &MI) const
Definition: SIInstrInfo.h:326
static unsigned getNumWaitStates(const MachineInstr &MI)
Return the number of wait states that result from executing this instruction.
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const override
static bool isVOP3P(const MachineInstr &MI)
Definition: SIInstrInfo.h:784
bool isWQM(uint16_t Opcode) const
Definition: SIInstrInfo.h:707
unsigned getVALUOp(const MachineInstr &MI) const
static bool modifiesModeRegister(const MachineInstr &MI)
Return true if the instruction modifies the mode register.q.
Register readlaneVGPRToSGPR(Register SrcReg, MachineInstr &UseMI, MachineRegisterInfo &MRI, const TargetRegisterClass *DstRC=nullptr) const
Copy a value from a VGPR (SrcReg) to SGPR.
bool hasDivergentBranch(const MachineBasicBlock *MBB) const
Return whether the block terminate with divergent branch.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void fixImplicitOperands(MachineInstr &MI) const
bool moveFlatAddrToVGPR(MachineInstr &Inst) const
Change SADDR form of a FLAT Inst to its VADDR form if saddr operand was moved to VGPR.
bool isVOP3P(uint16_t Opcode) const
Definition: SIInstrInfo.h:788
LLVM_READONLY const MachineOperand * getNamedOperand(const MachineInstr &MI, unsigned OpName) const
Definition: SIInstrInfo.h:1297
bool isEXP(uint16_t Opcode) const
Definition: SIInstrInfo.h:669
Register insertNE(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
static bool isDualSourceBlendEXP(const MachineInstr &MI)
Definition: SIInstrInfo.h:661
bool hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const
This function is used to determine if an instruction can be safely executed under EXEC = 0 without ha...
static bool isAtomic(const MachineInstr &MI)
Definition: SIInstrInfo.h:689
bool canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const override
static bool sopkIsZext(unsigned Opcode)
Definition: SIInstrInfo.h:871
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
static bool isSGPRSpill(const MachineInstr &MI)
Definition: SIInstrInfo.h:736
static bool isWMMA(const MachineInstr &MI)
Definition: SIInstrInfo.h:817
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const override
bool isVINTERP(uint16_t Opcode) const
Definition: SIInstrInfo.h:853
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const
Returns true if the instruction could potentially depend on the value of exec.
void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
bool doesNotReadTiedSource(uint16_t Opcode) const
Definition: SIInstrInfo.h:969
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool isDPP(uint16_t Opcode) const
Definition: SIInstrInfo.h:772
void insertVectorSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
std::pair< MachineInstr *, MachineInstr * > expandMovDPP64(MachineInstr &MI) const
Register insertEQ(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const
static bool isSOP1(const MachineInstr &MI)
Definition: SIInstrInfo.h:448
static bool isSOPC(const MachineInstr &MI)
Definition: SIInstrInfo.h:464
static bool isFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:620
const SIRegisterInfo & getRegisterInfo() const
Definition: SIInstrInfo.h:227
static bool isVALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:424
bool isBarrier(unsigned Opcode) const
Definition: SIInstrInfo.h:947
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx0, unsigned OpIdx1) const override
void enforceOperandRCAlignment(MachineInstr &MI, unsigned OpName) const
static bool hasIntClamp(const MachineInstr &MI)
Definition: SIInstrInfo.h:904
int pseudoToMCOpcode(int Opcode) const
Return a target-specific opcode if Opcode is a pseudo instruction.
const MCInstrDesc & getMCOpcodeFromPseudo(unsigned Opcode) const
Return the descriptor of the target-specific machine instruction that corresponds to the specified ps...
Definition: SIInstrInfo.h:1316
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx, const MachineOperand &MO) const
Definition: SIInstrInfo.h:1096
static bool isScalarUnit(const MachineInstr &MI)
Definition: SIInstrInfo.h:857
bool isSOPP(uint16_t Opcode) const
Definition: SIInstrInfo.h:484
bool isMIMG(uint16_t Opcode) const
Definition: SIInstrInfo.h:592
bool hasFPClamp(uint16_t Opcode) const
Definition: SIInstrInfo.h:900
static bool usesVM_CNT(const MachineInstr &MI)
Definition: SIInstrInfo.h:861
bool usesFPDPRounding(uint16_t Opcode) const
Definition: SIInstrInfo.h:920
MachineInstr * createPHIDestinationCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register Dst) const override
bool hasModifiersSet(const MachineInstr &MI, unsigned OpName) const
static bool isFixedSize(const MachineInstr &MI)
Definition: SIInstrInfo.h:888
bool isSafeToSink(MachineInstr &MI, MachineBasicBlock *SuccToSinkTo, MachineCycleInfo *CI) const override
LLVM_READONLY int commuteOpcode(unsigned Opc) const
uint64_t getScratchRsrcWords23() const
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const
Check if MO is a legal operand if it was the OpIdx Operand for MI.
bool isBarrierStart(unsigned Opcode) const
Definition: SIInstrInfo.h:939
static bool isLDSDMA(const MachineInstr &MI)
Definition: SIInstrInfo.h:570
unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const
static bool isAtomicNoRet(const MachineInstr &MI)
Definition: SIInstrInfo.h:673
static bool isVOP1(const MachineInstr &MI)
Definition: SIInstrInfo.h:496
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
bool hasAnyModifiersSet(const MachineInstr &MI) const
const TargetRegisterClass * getRegClass(unsigned RCID) const
bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
A vector that has set insertion semantics.
Definition: SetVector.h:57
SlotIndexes pass.
Definition: SlotIndexes.h:297
A SetVector that performs no allocations if smaller than a certain size.
Definition: SetVector.h:370
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:573
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:51
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Provide an instruction scheduling machine model to CodeGen passes.
Target - Wrapper for Target specific information.
LLVM Value Representation.
Definition: Value.h:74
const uint64_t RSRC_DATA_FORMAT
Definition: SIInstrInfo.h:1591
LLVM_READONLY int getBasicFromSDWAOp(uint16_t Opcode)
LLVM_READONLY int getGlobalSaddrOp(uint16_t Opcode)
LLVM_READONLY int getSOPKOp(uint16_t Opcode)
LLVM_READONLY int getVOPe32(uint16_t Opcode)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
LLVM_READONLY int getDPPOp32(uint16_t Opcode)
LLVM_READONLY int getFlatScratchInstSVfromSS(uint16_t Opcode)
LLVM_READONLY int getFlatScratchInstSTfromSS(uint16_t Opcode)
LLVM_READONLY int getGlobalVaddrOp(uint16_t Opcode)
const uint64_t RSRC_ELEMENT_SIZE_SHIFT
Definition: SIInstrInfo.h:1592
LLVM_READONLY int getFlatScratchInstSVfromSVS(uint16_t Opcode)
LLVM_READONLY int getAddr64Inst(uint16_t Opcode)
LLVM_READONLY int getMFMAEarlyClobberOp(uint16_t Opcode)
LLVM_READONLY int getVCMPXOpFromVCMP(uint16_t Opcode)
LLVM_READONLY int getSDWAOp(uint16_t Opcode)
LLVM_READONLY int getMFMASrcCVDstAGPROp(uint16_t Opcode)
const uint64_t RSRC_TID_ENABLE
Definition: SIInstrInfo.h:1594
LLVM_READONLY int getCommuteRev(uint16_t Opcode)
LLVM_READONLY int getDPPOp64(uint16_t Opcode)
LLVM_READONLY int getVOPe64(uint16_t Opcode)
@ OPERAND_REG_IMM_INT64
Definition: SIDefines.h:201
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition: SIDefines.h:200
LLVM_READONLY int getCommuteOrig(uint16_t Opcode)
const uint64_t RSRC_INDEX_STRIDE_SHIFT
Definition: SIInstrInfo.h:1593
LLVM_READONLY int getFlatScratchInstSSfromSV(uint16_t Opcode)
LLVM_READONLY int getVCMPXNoSDstOp(uint16_t Opcode)
LLVM_READONLY int getIfAddr64Inst(uint16_t Opcode)
Check if Opcode is an Addr64 opcode.
@ OPERAND_IMMEDIATE
Definition: MCInstrDesc.h:60
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1609
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
TargetInstrInfo::RegSubRegPair getRegSubRegPair(const MachineOperand &O)
Create RegSubRegPair from a register MachineOperand.
Definition: SIInstrInfo.h:1477
bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI, Register VReg, const MachineInstr &DefMI, const MachineInstr &UseMI)
Return false if EXEC is not changed between the def of VReg at DefMI and the use at UseMI.
TargetInstrInfo::RegSubRegPair getRegSequenceSubReg(MachineInstr &MI, unsigned SubReg)
Return the SubReg component from REG_SEQUENCE.
static const MachineMemOperand::Flags MONoClobber
Mark the MMO of a uniform load if there are no potentially clobbering stores on any path from the sta...
Definition: SIInstrInfo.h:43
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1746
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
MachineInstr * getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P, MachineRegisterInfo &MRI)
Return the defining instruction for a given reg:subreg pair skipping copy like instructions and subre...
constexpr unsigned DefaultMemoryClusterDWordsLimit
Definition: SIInstrInfo.h:39
static const MachineMemOperand::Flags MOLastUse
Mark the MMO of a load as the last use.
Definition: SIInstrInfo.h:47
bool isOfRegClass(const TargetInstrInfo::RegSubRegPair &P, const TargetRegisterClass &TRC, MachineRegisterInfo &MRI)
Returns true if a reg:subreg pair P has a TRC class.
Definition: SIInstrInfo.h:1465
InstructionUniformity
Enum describing how instructions behave with respect to uniformity and divergence,...
Definition: Uniformity.h:18
bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI, Register VReg, const MachineInstr &DefMI)
Return false if EXEC is not changed between the def of VReg at DefMI and all its uses.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Description of the encoding of one expression Op.
Utility to store machine instructions worklist.
Definition: SIInstrInfo.h:51
MachineInstr * top() const
Definition: SIInstrInfo.h:56
bool empty() const
Definition: SIInstrInfo.h:66
bool isDeferred(MachineInstr *MI)
SetVector< MachineInstr * > & getDeferredList()
Definition: SIInstrInfo.h:75
void insert(MachineInstr *MI)
A pair composed of a register and a sub-register index.