LLVM 19.0.0git
SIInstrInfo.h
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1//===- SIInstrInfo.h - SI Instruction Info Interface ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Interface definition for SIInstrInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
15#define LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
16
17#include "AMDGPUMIRFormatter.h"
19#include "SIRegisterInfo.h"
21#include "llvm/ADT/SetVector.h"
24
25#define GET_INSTRINFO_HEADER
26#include "AMDGPUGenInstrInfo.inc"
27
28namespace llvm {
29
30class APInt;
31class GCNSubtarget;
32class LiveVariables;
33class MachineDominatorTree;
34class MachineRegisterInfo;
35class RegScavenger;
36class TargetRegisterClass;
37class ScheduleHazardRecognizer;
38
39/// Mark the MMO of a uniform load if there are no potentially clobbering stores
40/// on any path from the start of an entry function to this load.
43
44/// Mark the MMO of a load as the last use.
47
48/// Utility to store machine instructions worklist.
50 SIInstrWorklist() = default;
51
52 void insert(MachineInstr *MI);
53
54 MachineInstr *top() const {
55 auto iter = InstrList.begin();
56 return *iter;
57 }
58
59 void erase_top() {
60 auto iter = InstrList.begin();
61 InstrList.erase(iter);
62 }
63
64 bool empty() const { return InstrList.empty(); }
65
66 void clear() {
67 InstrList.clear();
68 DeferredList.clear();
69 }
70
72
73 SetVector<MachineInstr *> &getDeferredList() { return DeferredList; }
74
75private:
76 /// InstrList contains the MachineInstrs.
78 /// Deferred instructions are specific MachineInstr
79 /// that will be added by insert method.
80 SetVector<MachineInstr *> DeferredList;
81};
82
83class SIInstrInfo final : public AMDGPUGenInstrInfo {
84private:
85 const SIRegisterInfo RI;
86 const GCNSubtarget &ST;
87 TargetSchedModel SchedModel;
88 mutable std::unique_ptr<AMDGPUMIRFormatter> Formatter;
89
90 // The inverse predicate should have the negative value.
91 enum BranchPredicate {
92 INVALID_BR = 0,
93 SCC_TRUE = 1,
94 SCC_FALSE = -1,
95 VCCNZ = 2,
96 VCCZ = -2,
97 EXECNZ = -3,
98 EXECZ = 3
99 };
100
102
103 static unsigned getBranchOpcode(BranchPredicate Cond);
104 static BranchPredicate getBranchPredicate(unsigned Opcode);
105
106public:
109 const MachineOperand &SuperReg,
110 const TargetRegisterClass *SuperRC,
111 unsigned SubIdx,
112 const TargetRegisterClass *SubRC) const;
115 const MachineOperand &SuperReg, const TargetRegisterClass *SuperRC,
116 unsigned SubIdx, const TargetRegisterClass *SubRC) const;
117
118private:
119 void swapOperands(MachineInstr &Inst) const;
120
121 std::pair<bool, MachineBasicBlock *>
122 moveScalarAddSub(SIInstrWorklist &Worklist, MachineInstr &Inst,
123 MachineDominatorTree *MDT = nullptr) const;
124
125 void lowerSelect(SIInstrWorklist &Worklist, MachineInstr &Inst,
126 MachineDominatorTree *MDT = nullptr) const;
127
128 void lowerScalarAbs(SIInstrWorklist &Worklist, MachineInstr &Inst) const;
129
130 void lowerScalarXnor(SIInstrWorklist &Worklist, MachineInstr &Inst) const;
131
132 void splitScalarNotBinop(SIInstrWorklist &Worklist, MachineInstr &Inst,
133 unsigned Opcode) const;
134
135 void splitScalarBinOpN2(SIInstrWorklist &Worklist, MachineInstr &Inst,
136 unsigned Opcode) const;
137
138 void splitScalar64BitUnaryOp(SIInstrWorklist &Worklist, MachineInstr &Inst,
139 unsigned Opcode, bool Swap = false) const;
140
141 void splitScalar64BitBinaryOp(SIInstrWorklist &Worklist, MachineInstr &Inst,
142 unsigned Opcode,
143 MachineDominatorTree *MDT = nullptr) const;
144
145 void splitScalarSMulU64(SIInstrWorklist &Worklist, MachineInstr &Inst,
146 MachineDominatorTree *MDT) const;
147
148 void splitScalarSMulPseudo(SIInstrWorklist &Worklist, MachineInstr &Inst,
149 MachineDominatorTree *MDT) const;
150
151 void splitScalar64BitXnor(SIInstrWorklist &Worklist, MachineInstr &Inst,
152 MachineDominatorTree *MDT = nullptr) const;
153
154 void splitScalar64BitBCNT(SIInstrWorklist &Worklist,
155 MachineInstr &Inst) const;
156 void splitScalar64BitBFE(SIInstrWorklist &Worklist, MachineInstr &Inst) const;
157 void splitScalar64BitCountOp(SIInstrWorklist &Worklist, MachineInstr &Inst,
158 unsigned Opcode,
159 MachineDominatorTree *MDT = nullptr) const;
160 void movePackToVALU(SIInstrWorklist &Worklist, MachineRegisterInfo &MRI,
161 MachineInstr &Inst) const;
162
163 void addUsersToMoveToVALUWorklist(Register Reg, MachineRegisterInfo &MRI,
164 SIInstrWorklist &Worklist) const;
165
166 void addSCCDefUsersToVALUWorklist(MachineOperand &Op,
167 MachineInstr &SCCDefInst,
168 SIInstrWorklist &Worklist,
169 Register NewCond = Register()) const;
170 void addSCCDefsToVALUWorklist(MachineInstr *SCCUseInst,
171 SIInstrWorklist &Worklist) const;
172
173 const TargetRegisterClass *
174 getDestEquivalentVGPRClass(const MachineInstr &Inst) const;
175
176 bool checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
177 const MachineInstr &MIb) const;
178
179 Register findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
180
181protected:
182 /// If the specific machine instruction is a instruction that moves/copies
183 /// value from one register to another register return destination and source
184 /// registers as machine operands.
185 std::optional<DestSourcePair>
186 isCopyInstrImpl(const MachineInstr &MI) const override;
187
189 MachineOperand &Src0, unsigned Src0OpName,
190 MachineOperand &Src1, unsigned Src1OpName) const;
191
193 unsigned OpIdx0,
194 unsigned OpIdx1) const override;
195
196public:
198 MO_MASK = 0xf,
199
201 // MO_GOTPCREL -> symbol@GOTPCREL -> R_AMDGPU_GOTPCREL.
203 // MO_GOTPCREL32_LO -> symbol@gotpcrel32@lo -> R_AMDGPU_GOTPCREL32_LO.
206 // MO_GOTPCREL32_HI -> symbol@gotpcrel32@hi -> R_AMDGPU_GOTPCREL32_HI.
208 // MO_REL32_LO -> symbol@rel32@lo -> R_AMDGPU_REL32_LO.
211 // MO_REL32_HI -> symbol@rel32@hi -> R_AMDGPU_REL32_HI.
213
215
218 };
219
220 explicit SIInstrInfo(const GCNSubtarget &ST);
221
223 return RI;
224 }
225
226 const GCNSubtarget &getSubtarget() const {
227 return ST;
228 }
229
230 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
231
232 bool isIgnorableUse(const MachineOperand &MO) const override;
233
234 bool isSafeToSink(MachineInstr &MI, MachineBasicBlock *SuccToSinkTo,
235 MachineCycleInfo *CI) const override;
236
237 bool areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, int64_t &Offset0,
238 int64_t &Offset1) const override;
239
241 const MachineInstr &LdSt,
243 bool &OffsetIsScalable, LocationSize &Width,
244 const TargetRegisterInfo *TRI) const final;
245
247 int64_t Offset1, bool OffsetIsScalable1,
249 int64_t Offset2, bool OffsetIsScalable2,
250 unsigned ClusterSize,
251 unsigned NumBytes) const override;
252
253 bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
254 int64_t Offset1, unsigned NumLoads) const override;
255
257 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
258 bool KillSrc) const override;
259
262 Register DestReg, int64_t Value) const;
263
265 unsigned Size) const;
266
269 Register SrcReg, int Value) const;
270
273 Register SrcReg, int Value) const;
274
277 bool isKill, int FrameIndex,
278 const TargetRegisterClass *RC,
279 const TargetRegisterInfo *TRI,
280 Register VReg) const override;
281
284 int FrameIndex, const TargetRegisterClass *RC,
285 const TargetRegisterInfo *TRI,
286 Register VReg) const override;
287
288 bool expandPostRAPseudo(MachineInstr &MI) const override;
289
291 Register DestReg, unsigned SubIdx,
292 const MachineInstr &Orig,
293 const TargetRegisterInfo &TRI) const override;
294
295 // Splits a V_MOV_B64_DPP_PSEUDO opcode into a pair of v_mov_b32_dpp
296 // instructions. Returns a pair of generated instructions.
297 // Can split either post-RA with physical registers or pre-RA with
298 // virtual registers. In latter case IR needs to be in SSA form and
299 // and a REG_SEQUENCE is produced to define original register.
300 std::pair<MachineInstr*, MachineInstr*>
302
303 // Returns an opcode that can be used to move a value to a \p DstRC
304 // register. If there is no hardware instruction that can store to \p
305 // DstRC, then AMDGPU::COPY is returned.
306 unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
307
308 const MCInstrDesc &getIndirectRegWriteMovRelPseudo(unsigned VecSize,
309 unsigned EltSize,
310 bool IsSGPR) const;
311
312 const MCInstrDesc &getIndirectGPRIDXPseudo(unsigned VecSize,
313 bool IsIndirectSrc) const;
315 int commuteOpcode(unsigned Opc) const;
316
318 inline int commuteOpcode(const MachineInstr &MI) const {
319 return commuteOpcode(MI.getOpcode());
320 }
321
322 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx0,
323 unsigned &SrcOpIdx1) const override;
324
325 bool findCommutedOpIndices(const MCInstrDesc &Desc, unsigned &SrcOpIdx0,
326 unsigned &SrcOpIdx1) const;
327
328 bool isBranchOffsetInRange(unsigned BranchOpc,
329 int64_t BrOffset) const override;
330
331 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
332
333 /// Return whether the block terminate with divergent branch.
334 /// Note this only work before lowering the pseudo control flow instructions.
335 bool hasDivergentBranch(const MachineBasicBlock *MBB) const;
336
338 MachineBasicBlock &NewDestBB,
339 MachineBasicBlock &RestoreBB, const DebugLoc &DL,
340 int64_t BrOffset, RegScavenger *RS) const override;
341
345 MachineBasicBlock *&FBB,
347 bool AllowModify) const;
348
350 MachineBasicBlock *&FBB,
352 bool AllowModify = false) const override;
353
355 int *BytesRemoved = nullptr) const override;
356
359 const DebugLoc &DL,
360 int *BytesAdded = nullptr) const override;
361
363 SmallVectorImpl<MachineOperand> &Cond) const override;
364
367 Register TrueReg, Register FalseReg, int &CondCycles,
368 int &TrueCycles, int &FalseCycles) const override;
369
373 Register TrueReg, Register FalseReg) const override;
374
378 Register TrueReg, Register FalseReg) const;
379
380 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
381 Register &SrcReg2, int64_t &CmpMask,
382 int64_t &CmpValue) const override;
383
384 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
385 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
386 const MachineRegisterInfo *MRI) const override;
387
388 bool
390 const MachineInstr &MIb) const override;
391
392 static bool isFoldableCopy(const MachineInstr &MI);
393
394 void removeModOperands(MachineInstr &MI) const;
395
397 MachineRegisterInfo *MRI) const final;
398
399 unsigned getMachineCSELookAheadLimit() const override { return 500; }
400
402 LiveIntervals *LIS) const override;
403
405 const MachineBasicBlock *MBB,
406 const MachineFunction &MF) const override;
407
408 static bool isSALU(const MachineInstr &MI) {
409 return MI.getDesc().TSFlags & SIInstrFlags::SALU;
410 }
411
412 bool isSALU(uint16_t Opcode) const {
413 return get(Opcode).TSFlags & SIInstrFlags::SALU;
414 }
415
416 static bool isVALU(const MachineInstr &MI) {
417 return MI.getDesc().TSFlags & SIInstrFlags::VALU;
418 }
419
420 bool isVALU(uint16_t Opcode) const {
421 return get(Opcode).TSFlags & SIInstrFlags::VALU;
422 }
423
424 static bool isImage(const MachineInstr &MI) {
425 return isMIMG(MI) || isVSAMPLE(MI) || isVIMAGE(MI);
426 }
427
428 bool isImage(uint16_t Opcode) const {
429 return isMIMG(Opcode) || isVSAMPLE(Opcode) || isVIMAGE(Opcode);
430 }
431
432 static bool isVMEM(const MachineInstr &MI) {
433 return isMUBUF(MI) || isMTBUF(MI) || isImage(MI);
434 }
435
436 bool isVMEM(uint16_t Opcode) const {
437 return isMUBUF(Opcode) || isMTBUF(Opcode) || isImage(Opcode);
438 }
439
440 static bool isSOP1(const MachineInstr &MI) {
441 return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
442 }
443
444 bool isSOP1(uint16_t Opcode) const {
445 return get(Opcode).TSFlags & SIInstrFlags::SOP1;
446 }
447
448 static bool isSOP2(const MachineInstr &MI) {
449 return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
450 }
451
452 bool isSOP2(uint16_t Opcode) const {
453 return get(Opcode).TSFlags & SIInstrFlags::SOP2;
454 }
455
456 static bool isSOPC(const MachineInstr &MI) {
457 return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
458 }
459
460 bool isSOPC(uint16_t Opcode) const {
461 return get(Opcode).TSFlags & SIInstrFlags::SOPC;
462 }
463
464 static bool isSOPK(const MachineInstr &MI) {
465 return MI.getDesc().TSFlags & SIInstrFlags::SOPK;
466 }
467
468 bool isSOPK(uint16_t Opcode) const {
469 return get(Opcode).TSFlags & SIInstrFlags::SOPK;
470 }
471
472 static bool isSOPP(const MachineInstr &MI) {
473 return MI.getDesc().TSFlags & SIInstrFlags::SOPP;
474 }
475
476 bool isSOPP(uint16_t Opcode) const {
477 return get(Opcode).TSFlags & SIInstrFlags::SOPP;
478 }
479
480 static bool isPacked(const MachineInstr &MI) {
481 return MI.getDesc().TSFlags & SIInstrFlags::IsPacked;
482 }
483
484 bool isPacked(uint16_t Opcode) const {
485 return get(Opcode).TSFlags & SIInstrFlags::IsPacked;
486 }
487
488 static bool isVOP1(const MachineInstr &MI) {
489 return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
490 }
491
492 bool isVOP1(uint16_t Opcode) const {
493 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
494 }
495
496 static bool isVOP2(const MachineInstr &MI) {
497 return MI.getDesc().TSFlags & SIInstrFlags::VOP2;
498 }
499
500 bool isVOP2(uint16_t Opcode) const {
501 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
502 }
503
504 static bool isVOP3(const MachineInstr &MI) {
505 return MI.getDesc().TSFlags & SIInstrFlags::VOP3;
506 }
507
508 bool isVOP3(uint16_t Opcode) const {
509 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
510 }
511
512 static bool isSDWA(const MachineInstr &MI) {
513 return MI.getDesc().TSFlags & SIInstrFlags::SDWA;
514 }
515
516 bool isSDWA(uint16_t Opcode) const {
517 return get(Opcode).TSFlags & SIInstrFlags::SDWA;
518 }
519
520 static bool isVOPC(const MachineInstr &MI) {
521 return MI.getDesc().TSFlags & SIInstrFlags::VOPC;
522 }
523
524 bool isVOPC(uint16_t Opcode) const {
525 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
526 }
527
528 static bool isMUBUF(const MachineInstr &MI) {
529 return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;
530 }
531
532 bool isMUBUF(uint16_t Opcode) const {
533 return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
534 }
535
536 static bool isMTBUF(const MachineInstr &MI) {
537 return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;
538 }
539
540 bool isMTBUF(uint16_t Opcode) const {
541 return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
542 }
543
544 static bool isSMRD(const MachineInstr &MI) {
545 return MI.getDesc().TSFlags & SIInstrFlags::SMRD;
546 }
547
548 bool isSMRD(uint16_t Opcode) const {
549 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
550 }
551
552 bool isBufferSMRD(const MachineInstr &MI) const;
553
554 static bool isDS(const MachineInstr &MI) {
555 return MI.getDesc().TSFlags & SIInstrFlags::DS;
556 }
557
558 bool isDS(uint16_t Opcode) const {
559 return get(Opcode).TSFlags & SIInstrFlags::DS;
560 }
561
562 static bool isLDSDMA(const MachineInstr &MI) {
563 return isVALU(MI) && (isMUBUF(MI) || isFLAT(MI));
564 }
565
566 bool isLDSDMA(uint16_t Opcode) {
567 return isVALU(Opcode) && (isMUBUF(Opcode) || isFLAT(Opcode));
568 }
569
570 static bool isGWS(const MachineInstr &MI) {
571 return MI.getDesc().TSFlags & SIInstrFlags::GWS;
572 }
573
574 bool isGWS(uint16_t Opcode) const {
575 return get(Opcode).TSFlags & SIInstrFlags::GWS;
576 }
577
578 bool isAlwaysGDS(uint16_t Opcode) const;
579
580 static bool isMIMG(const MachineInstr &MI) {
581 return MI.getDesc().TSFlags & SIInstrFlags::MIMG;
582 }
583
584 bool isMIMG(uint16_t Opcode) const {
585 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
586 }
587
588 static bool isVIMAGE(const MachineInstr &MI) {
589 return MI.getDesc().TSFlags & SIInstrFlags::VIMAGE;
590 }
591
592 bool isVIMAGE(uint16_t Opcode) const {
593 return get(Opcode).TSFlags & SIInstrFlags::VIMAGE;
594 }
595
596 static bool isVSAMPLE(const MachineInstr &MI) {
597 return MI.getDesc().TSFlags & SIInstrFlags::VSAMPLE;
598 }
599
600 bool isVSAMPLE(uint16_t Opcode) const {
601 return get(Opcode).TSFlags & SIInstrFlags::VSAMPLE;
602 }
603
604 static bool isGather4(const MachineInstr &MI) {
605 return MI.getDesc().TSFlags & SIInstrFlags::Gather4;
606 }
607
608 bool isGather4(uint16_t Opcode) const {
609 return get(Opcode).TSFlags & SIInstrFlags::Gather4;
610 }
611
612 static bool isFLAT(const MachineInstr &MI) {
613 return MI.getDesc().TSFlags & SIInstrFlags::FLAT;
614 }
615
616 // Is a FLAT encoded instruction which accesses a specific segment,
617 // i.e. global_* or scratch_*.
619 auto Flags = MI.getDesc().TSFlags;
621 }
622
623 bool isSegmentSpecificFLAT(uint16_t Opcode) const {
624 auto Flags = get(Opcode).TSFlags;
626 }
627
628 static bool isFLATGlobal(const MachineInstr &MI) {
629 return MI.getDesc().TSFlags & SIInstrFlags::FlatGlobal;
630 }
631
632 bool isFLATGlobal(uint16_t Opcode) const {
633 return get(Opcode).TSFlags & SIInstrFlags::FlatGlobal;
634 }
635
636 static bool isFLATScratch(const MachineInstr &MI) {
637 return MI.getDesc().TSFlags & SIInstrFlags::FlatScratch;
638 }
639
640 bool isFLATScratch(uint16_t Opcode) const {
641 return get(Opcode).TSFlags & SIInstrFlags::FlatScratch;
642 }
643
644 // Any FLAT encoded instruction, including global_* and scratch_*.
645 bool isFLAT(uint16_t Opcode) const {
646 return get(Opcode).TSFlags & SIInstrFlags::FLAT;
647 }
648
649 static bool isEXP(const MachineInstr &MI) {
650 return MI.getDesc().TSFlags & SIInstrFlags::EXP;
651 }
652
654 if (!isEXP(MI))
655 return false;
656 unsigned Target = MI.getOperand(0).getImm();
659 }
660
661 bool isEXP(uint16_t Opcode) const {
662 return get(Opcode).TSFlags & SIInstrFlags::EXP;
663 }
664
665 static bool isAtomicNoRet(const MachineInstr &MI) {
666 return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicNoRet;
667 }
668
669 bool isAtomicNoRet(uint16_t Opcode) const {
670 return get(Opcode).TSFlags & SIInstrFlags::IsAtomicNoRet;
671 }
672
673 static bool isAtomicRet(const MachineInstr &MI) {
674 return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicRet;
675 }
676
677 bool isAtomicRet(uint16_t Opcode) const {
678 return get(Opcode).TSFlags & SIInstrFlags::IsAtomicRet;
679 }
680
681 static bool isAtomic(const MachineInstr &MI) {
682 return MI.getDesc().TSFlags & (SIInstrFlags::IsAtomicRet |
684 }
685
686 bool isAtomic(uint16_t Opcode) const {
687 return get(Opcode).TSFlags & (SIInstrFlags::IsAtomicRet |
689 }
690
692 return isLDSDMA(MI) && MI.getOpcode() != AMDGPU::BUFFER_STORE_LDS_DWORD;
693 }
694
695 static bool isWQM(const MachineInstr &MI) {
696 return MI.getDesc().TSFlags & SIInstrFlags::WQM;
697 }
698
699 bool isWQM(uint16_t Opcode) const {
700 return get(Opcode).TSFlags & SIInstrFlags::WQM;
701 }
702
703 static bool isDisableWQM(const MachineInstr &MI) {
704 return MI.getDesc().TSFlags & SIInstrFlags::DisableWQM;
705 }
706
707 bool isDisableWQM(uint16_t Opcode) const {
708 return get(Opcode).TSFlags & SIInstrFlags::DisableWQM;
709 }
710
711 // SI_SPILL_S32_TO_VGPR and SI_RESTORE_S32_FROM_VGPR form a special case of
712 // SGPRs spilling to VGPRs which are SGPR spills but from VALU instructions
713 // therefore we need an explicit check for them since just checking if the
714 // Spill bit is set and what instruction type it came from misclassifies
715 // them.
716 static bool isVGPRSpill(const MachineInstr &MI) {
717 return MI.getOpcode() != AMDGPU::SI_SPILL_S32_TO_VGPR &&
718 MI.getOpcode() != AMDGPU::SI_RESTORE_S32_FROM_VGPR &&
719 (isSpill(MI) && isVALU(MI));
720 }
721
722 bool isVGPRSpill(uint16_t Opcode) const {
723 return Opcode != AMDGPU::SI_SPILL_S32_TO_VGPR &&
724 Opcode != AMDGPU::SI_RESTORE_S32_FROM_VGPR &&
725 (isSpill(Opcode) && isVALU(Opcode));
726 }
727
728 static bool isSGPRSpill(const MachineInstr &MI) {
729 return MI.getOpcode() == AMDGPU::SI_SPILL_S32_TO_VGPR ||
730 MI.getOpcode() == AMDGPU::SI_RESTORE_S32_FROM_VGPR ||
731 (isSpill(MI) && isSALU(MI));
732 }
733
734 bool isSGPRSpill(uint16_t Opcode) const {
735 return Opcode == AMDGPU::SI_SPILL_S32_TO_VGPR ||
736 Opcode == AMDGPU::SI_RESTORE_S32_FROM_VGPR ||
737 (isSpill(Opcode) && isSALU(Opcode));
738 }
739
740 bool isSpill(uint16_t Opcode) const {
741 return get(Opcode).TSFlags & SIInstrFlags::Spill;
742 }
743
744 static bool isSpill(const MachineInstr &MI) {
745 return MI.getDesc().TSFlags & SIInstrFlags::Spill;
746 }
747
748 static bool isWWMRegSpillOpcode(uint16_t Opcode) {
749 return Opcode == AMDGPU::SI_SPILL_WWM_V32_SAVE ||
750 Opcode == AMDGPU::SI_SPILL_WWM_AV32_SAVE ||
751 Opcode == AMDGPU::SI_SPILL_WWM_V32_RESTORE ||
752 Opcode == AMDGPU::SI_SPILL_WWM_AV32_RESTORE;
753 }
754
755 static bool isChainCallOpcode(uint64_t Opcode) {
756 return Opcode == AMDGPU::SI_CS_CHAIN_TC_W32 ||
757 Opcode == AMDGPU::SI_CS_CHAIN_TC_W64;
758 }
759
760 static bool isDPP(const MachineInstr &MI) {
761 return MI.getDesc().TSFlags & SIInstrFlags::DPP;
762 }
763
764 bool isDPP(uint16_t Opcode) const {
765 return get(Opcode).TSFlags & SIInstrFlags::DPP;
766 }
767
768 static bool isTRANS(const MachineInstr &MI) {
769 return MI.getDesc().TSFlags & SIInstrFlags::TRANS;
770 }
771
772 bool isTRANS(uint16_t Opcode) const {
773 return get(Opcode).TSFlags & SIInstrFlags::TRANS;
774 }
775
776 static bool isVOP3P(const MachineInstr &MI) {
777 return MI.getDesc().TSFlags & SIInstrFlags::VOP3P;
778 }
779
780 bool isVOP3P(uint16_t Opcode) const {
781 return get(Opcode).TSFlags & SIInstrFlags::VOP3P;
782 }
783
784 static bool isVINTRP(const MachineInstr &MI) {
785 return MI.getDesc().TSFlags & SIInstrFlags::VINTRP;
786 }
787
788 bool isVINTRP(uint16_t Opcode) const {
789 return get(Opcode).TSFlags & SIInstrFlags::VINTRP;
790 }
791
792 static bool isMAI(const MachineInstr &MI) {
793 return MI.getDesc().TSFlags & SIInstrFlags::IsMAI;
794 }
795
796 bool isMAI(uint16_t Opcode) const {
797 return get(Opcode).TSFlags & SIInstrFlags::IsMAI;
798 }
799
800 static bool isMFMA(const MachineInstr &MI) {
801 return isMAI(MI) && MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64 &&
802 MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64;
803 }
804
805 static bool isDOT(const MachineInstr &MI) {
806 return MI.getDesc().TSFlags & SIInstrFlags::IsDOT;
807 }
808
809 static bool isWMMA(const MachineInstr &MI) {
810 return MI.getDesc().TSFlags & SIInstrFlags::IsWMMA;
811 }
812
813 bool isWMMA(uint16_t Opcode) const {
814 return get(Opcode).TSFlags & SIInstrFlags::IsWMMA;
815 }
816
817 static bool isMFMAorWMMA(const MachineInstr &MI) {
818 return isMFMA(MI) || isWMMA(MI) || isSWMMAC(MI);
819 }
820
821 static bool isSWMMAC(const MachineInstr &MI) {
822 return MI.getDesc().TSFlags & SIInstrFlags::IsSWMMAC;
823 }
824
825 bool isSWMMAC(uint16_t Opcode) const {
826 return get(Opcode).TSFlags & SIInstrFlags::IsSWMMAC;
827 }
828
829 bool isDOT(uint16_t Opcode) const {
830 return get(Opcode).TSFlags & SIInstrFlags::IsDOT;
831 }
832
833 static bool isLDSDIR(const MachineInstr &MI) {
834 return MI.getDesc().TSFlags & SIInstrFlags::LDSDIR;
835 }
836
837 bool isLDSDIR(uint16_t Opcode) const {
838 return get(Opcode).TSFlags & SIInstrFlags::LDSDIR;
839 }
840
841 static bool isVINTERP(const MachineInstr &MI) {
842 return MI.getDesc().TSFlags & SIInstrFlags::VINTERP;
843 }
844
845 bool isVINTERP(uint16_t Opcode) const {
846 return get(Opcode).TSFlags & SIInstrFlags::VINTERP;
847 }
848
849 static bool isScalarUnit(const MachineInstr &MI) {
850 return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD);
851 }
852
853 static bool usesVM_CNT(const MachineInstr &MI) {
854 return MI.getDesc().TSFlags & SIInstrFlags::VM_CNT;
855 }
856
857 static bool usesLGKM_CNT(const MachineInstr &MI) {
858 return MI.getDesc().TSFlags & SIInstrFlags::LGKM_CNT;
859 }
860
861 // Most sopk treat the immediate as a signed 16-bit, however some
862 // use it as unsigned.
863 static bool sopkIsZext(unsigned Opcode) {
864 return Opcode == AMDGPU::S_CMPK_EQ_U32 || Opcode == AMDGPU::S_CMPK_LG_U32 ||
865 Opcode == AMDGPU::S_CMPK_GT_U32 || Opcode == AMDGPU::S_CMPK_GE_U32 ||
866 Opcode == AMDGPU::S_CMPK_LT_U32 || Opcode == AMDGPU::S_CMPK_LE_U32 ||
867 Opcode == AMDGPU::S_GETREG_B32;
868 }
869
870 /// \returns true if this is an s_store_dword* instruction. This is more
871 /// specific than isSMEM && mayStore.
872 static bool isScalarStore(const MachineInstr &MI) {
873 return MI.getDesc().TSFlags & SIInstrFlags::SCALAR_STORE;
874 }
875
876 bool isScalarStore(uint16_t Opcode) const {
877 return get(Opcode).TSFlags & SIInstrFlags::SCALAR_STORE;
878 }
879
880 static bool isFixedSize(const MachineInstr &MI) {
881 return MI.getDesc().TSFlags & SIInstrFlags::FIXED_SIZE;
882 }
883
884 bool isFixedSize(uint16_t Opcode) const {
885 return get(Opcode).TSFlags & SIInstrFlags::FIXED_SIZE;
886 }
887
888 static bool hasFPClamp(const MachineInstr &MI) {
889 return MI.getDesc().TSFlags & SIInstrFlags::FPClamp;
890 }
891
892 bool hasFPClamp(uint16_t Opcode) const {
893 return get(Opcode).TSFlags & SIInstrFlags::FPClamp;
894 }
895
896 static bool hasIntClamp(const MachineInstr &MI) {
897 return MI.getDesc().TSFlags & SIInstrFlags::IntClamp;
898 }
899
901 const uint64_t ClampFlags = SIInstrFlags::FPClamp |
905 return MI.getDesc().TSFlags & ClampFlags;
906 }
907
908 static bool usesFPDPRounding(const MachineInstr &MI) {
909 return MI.getDesc().TSFlags & SIInstrFlags::FPDPRounding;
910 }
911
912 bool usesFPDPRounding(uint16_t Opcode) const {
913 return get(Opcode).TSFlags & SIInstrFlags::FPDPRounding;
914 }
915
916 static bool isFPAtomic(const MachineInstr &MI) {
917 return MI.getDesc().TSFlags & SIInstrFlags::FPAtomic;
918 }
919
920 bool isFPAtomic(uint16_t Opcode) const {
921 return get(Opcode).TSFlags & SIInstrFlags::FPAtomic;
922 }
923
924 static bool isNeverUniform(const MachineInstr &MI) {
925 return MI.getDesc().TSFlags & SIInstrFlags::IsNeverUniform;
926 }
927
928 // Check to see if opcode is for a barrier start. Pre gfx12 this is just the
929 // S_BARRIER, but after support for S_BARRIER_SIGNAL* / S_BARRIER_WAIT we want
930 // to check for the barrier start (S_BARRIER_SIGNAL*)
931 bool isBarrierStart(unsigned Opcode) const {
932 return Opcode == AMDGPU::S_BARRIER ||
933 Opcode == AMDGPU::S_BARRIER_SIGNAL_M0 ||
934 Opcode == AMDGPU::S_BARRIER_SIGNAL_ISFIRST_M0 ||
935 Opcode == AMDGPU::S_BARRIER_SIGNAL_IMM ||
936 Opcode == AMDGPU::S_BARRIER_SIGNAL_ISFIRST_IMM;
937 }
938
940 return MI.getDesc().TSFlags & SIInstrFlags::TiedSourceNotRead;
941 }
942
943 bool doesNotReadTiedSource(uint16_t Opcode) const {
944 return get(Opcode).TSFlags & SIInstrFlags::TiedSourceNotRead;
945 }
946
947 static unsigned getNonSoftWaitcntOpcode(unsigned Opcode) {
948 switch (Opcode) {
949 case AMDGPU::S_WAITCNT_soft:
950 return AMDGPU::S_WAITCNT;
951 case AMDGPU::S_WAITCNT_VSCNT_soft:
952 return AMDGPU::S_WAITCNT_VSCNT;
953 case AMDGPU::S_WAIT_LOADCNT_soft:
954 return AMDGPU::S_WAIT_LOADCNT;
955 case AMDGPU::S_WAIT_STORECNT_soft:
956 return AMDGPU::S_WAIT_STORECNT;
957 case AMDGPU::S_WAIT_SAMPLECNT_soft:
958 return AMDGPU::S_WAIT_SAMPLECNT;
959 case AMDGPU::S_WAIT_BVHCNT_soft:
960 return AMDGPU::S_WAIT_BVHCNT;
961 case AMDGPU::S_WAIT_DSCNT_soft:
962 return AMDGPU::S_WAIT_DSCNT;
963 case AMDGPU::S_WAIT_KMCNT_soft:
964 return AMDGPU::S_WAIT_KMCNT;
965 default:
966 return Opcode;
967 }
968 }
969
970 bool isVGPRCopy(const MachineInstr &MI) const {
971 assert(isCopyInstr(MI));
972 Register Dest = MI.getOperand(0).getReg();
973 const MachineFunction &MF = *MI.getParent()->getParent();
974 const MachineRegisterInfo &MRI = MF.getRegInfo();
975 return !RI.isSGPRReg(MRI, Dest);
976 }
977
978 bool hasVGPRUses(const MachineInstr &MI) const {
979 const MachineFunction &MF = *MI.getParent()->getParent();
980 const MachineRegisterInfo &MRI = MF.getRegInfo();
981 return llvm::any_of(MI.explicit_uses(),
982 [&MRI, this](const MachineOperand &MO) {
983 return MO.isReg() && RI.isVGPR(MRI, MO.getReg());});
984 }
985
986 /// Return true if the instruction modifies the mode register.q
987 static bool modifiesModeRegister(const MachineInstr &MI);
988
989 /// Whether we must prevent this instruction from executing with EXEC = 0.
991
992 /// Returns true if the instruction could potentially depend on the value of
993 /// exec. If false, exec dependencies may safely be ignored.
994 bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const;
995
996 bool isInlineConstant(const APInt &Imm) const;
997
998 bool isInlineConstant(const APFloat &Imm) const;
999
1000 // Returns true if this non-register operand definitely does not need to be
1001 // encoded as a 32-bit literal. Note that this function handles all kinds of
1002 // operands, not just immediates.
1003 //
1004 // Some operands like FrameIndexes could resolve to an inline immediate value
1005 // that will not require an additional 4-bytes; this function assumes that it
1006 // will.
1007 bool isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const;
1008
1010 const MCOperandInfo &OpInfo) const {
1011 return isInlineConstant(MO, OpInfo.OperandType);
1012 }
1013
1014 /// \p returns true if \p UseMO is substituted with \p DefMO in \p MI it would
1015 /// be an inline immediate.
1017 const MachineOperand &UseMO,
1018 const MachineOperand &DefMO) const {
1019 assert(UseMO.getParent() == &MI);
1020 int OpIdx = UseMO.getOperandNo();
1021 if (OpIdx >= MI.getDesc().NumOperands)
1022 return false;
1023
1024 return isInlineConstant(DefMO, MI.getDesc().operands()[OpIdx]);
1025 }
1026
1027 /// \p returns true if the operand \p OpIdx in \p MI is a valid inline
1028 /// immediate.
1029 bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const {
1030 const MachineOperand &MO = MI.getOperand(OpIdx);
1031 return isInlineConstant(MO, MI.getDesc().operands()[OpIdx].OperandType);
1032 }
1033
1034 bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
1035 const MachineOperand &MO) const {
1036 if (OpIdx >= MI.getDesc().NumOperands)
1037 return false;
1038
1039 if (isCopyInstr(MI)) {
1040 unsigned Size = getOpSize(MI, OpIdx);
1041 assert(Size == 8 || Size == 4);
1042
1043 uint8_t OpType = (Size == 8) ?
1045 return isInlineConstant(MO, OpType);
1046 }
1047
1048 return isInlineConstant(MO, MI.getDesc().operands()[OpIdx].OperandType);
1049 }
1050
1051 bool isInlineConstant(const MachineOperand &MO) const {
1052 return isInlineConstant(*MO.getParent(), MO.getOperandNo());
1053 }
1054
1055 bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
1056 const MachineOperand &MO) const;
1057
1058 /// Return true if this 64-bit VALU instruction has a 32-bit encoding.
1059 /// This function will return false if you pass it a 32-bit instruction.
1060 bool hasVALU32BitEncoding(unsigned Opcode) const;
1061
1062 /// Returns true if this operand uses the constant bus.
1064 const MachineOperand &MO,
1065 const MCOperandInfo &OpInfo) const;
1066
1067 /// Return true if this instruction has any modifiers.
1068 /// e.g. src[012]_mod, omod, clamp.
1069 bool hasModifiers(unsigned Opcode) const;
1070
1071 bool hasModifiersSet(const MachineInstr &MI,
1072 unsigned OpName) const;
1073 bool hasAnyModifiersSet(const MachineInstr &MI) const;
1074
1075 bool canShrink(const MachineInstr &MI,
1076 const MachineRegisterInfo &MRI) const;
1077
1079 unsigned NewOpcode) const;
1080
1081 bool verifyInstruction(const MachineInstr &MI,
1082 StringRef &ErrInfo) const override;
1083
1084 unsigned getVALUOp(const MachineInstr &MI) const;
1085
1088 const DebugLoc &DL, Register Reg, bool IsSCCLive,
1089 SlotIndexes *Indexes = nullptr) const;
1090
1093 Register Reg, SlotIndexes *Indexes = nullptr) const;
1094
1095 /// Return the correct register class for \p OpNo. For target-specific
1096 /// instructions, this will return the register class that has been defined
1097 /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
1098 /// the register class of its machine operand.
1099 /// to infer the correct register class base on the other operands.
1101 unsigned OpNo) const;
1102
1103 /// Return the size in bytes of the operand OpNo on the given
1104 // instruction opcode.
1105 unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
1106 const MCOperandInfo &OpInfo = get(Opcode).operands()[OpNo];
1107
1108 if (OpInfo.RegClass == -1) {
1109 // If this is an immediate operand, this must be a 32-bit literal.
1111 return 4;
1112 }
1113
1114 return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;
1115 }
1116
1117 /// This form should usually be preferred since it handles operands
1118 /// with unknown register classes.
1119 unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
1120 const MachineOperand &MO = MI.getOperand(OpNo);
1121 if (MO.isReg()) {
1122 if (unsigned SubReg = MO.getSubReg()) {
1123 return RI.getSubRegIdxSize(SubReg) / 8;
1124 }
1125 }
1126 return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
1127 }
1128
1129 /// Legalize the \p OpIndex operand of this instruction by inserting
1130 /// a MOV. For example:
1131 /// ADD_I32_e32 VGPR0, 15
1132 /// to
1133 /// MOV VGPR1, 15
1134 /// ADD_I32_e32 VGPR0, VGPR1
1135 ///
1136 /// If the operand being legalized is a register, then a COPY will be used
1137 /// instead of MOV.
1138 void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const;
1139
1140 /// Check if \p MO is a legal operand if it was the \p OpIdx Operand
1141 /// for \p MI.
1142 bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
1143 const MachineOperand *MO = nullptr) const;
1144
1145 /// Check if \p MO would be a valid operand for the given operand
1146 /// definition \p OpInfo. Note this does not attempt to validate constant bus
1147 /// restrictions (e.g. literal constant usage).
1149 const MCOperandInfo &OpInfo,
1150 const MachineOperand &MO) const;
1151
1152 /// Check if \p MO (a register operand) is a legal register for the
1153 /// given operand description.
1155 const MCOperandInfo &OpInfo,
1156 const MachineOperand &MO) const;
1157
1158 /// Legalize operands in \p MI by either commuting it or inserting a
1159 /// copy of src1.
1161
1162 /// Fix operands in \p MI to satisfy constant bus requirements.
1164
1165 /// Copy a value from a VGPR (\p SrcReg) to SGPR. This function can only
1166 /// be used when it is know that the value in SrcReg is same across all
1167 /// threads in the wave.
1168 /// \returns The SGPR register that \p SrcReg was copied to.
1170 MachineRegisterInfo &MRI) const;
1171
1174
1177 const TargetRegisterClass *DstRC,
1179 const DebugLoc &DL) const;
1180
1181 /// Legalize all operands in this instruction. This function may create new
1182 /// instructions and control-flow around \p MI. If present, \p MDT is
1183 /// updated.
1184 /// \returns A new basic block that contains \p MI if new blocks were created.
1186 legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT = nullptr) const;
1187
1188 /// Change SADDR form of a FLAT \p Inst to its VADDR form if saddr operand
1189 /// was moved to VGPR. \returns true if succeeded.
1190 bool moveFlatAddrToVGPR(MachineInstr &Inst) const;
1191
1192 /// Replace the instructions opcode with the equivalent VALU
1193 /// opcode. This function will also move the users of MachineInstruntions
1194 /// in the \p WorkList to the VALU if necessary. If present, \p MDT is
1195 /// updated.
1196 void moveToVALU(SIInstrWorklist &Worklist, MachineDominatorTree *MDT) const;
1197
1199 MachineInstr &Inst) const;
1200
1202 MachineBasicBlock::iterator MI) const override;
1203
1205 unsigned Quantity) const override;
1206
1207 void insertReturn(MachineBasicBlock &MBB) const;
1208
1209 /// Build instructions that simulate the behavior of a `s_trap 2` instructions
1210 /// for hardware (namely, gfx11) that runs in PRIV=1 mode. There, s_trap is
1211 /// interpreted as a nop.
1215 const DebugLoc &DL) const;
1216
1217 /// Return the number of wait states that result from executing this
1218 /// instruction.
1219 static unsigned getNumWaitStates(const MachineInstr &MI);
1220
1221 /// Returns the operand named \p Op. If \p MI does not have an
1222 /// operand named \c Op, this function returns nullptr.
1224 MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
1225
1228 unsigned OpName) const {
1229 return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
1230 }
1231
1232 /// Get required immediate operand
1233 int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const {
1234 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OpName);
1235 return MI.getOperand(Idx).getImm();
1236 }
1237
1240
1241 bool isLowLatencyInstruction(const MachineInstr &MI) const;
1242 bool isHighLatencyDef(int Opc) const override;
1243
1244 /// Return the descriptor of the target-specific machine instruction
1245 /// that corresponds to the specified pseudo or native opcode.
1246 const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const {
1247 return get(pseudoToMCOpcode(Opcode));
1248 }
1249
1250 unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1251 unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const;
1252
1254 int &FrameIndex) const override;
1256 int &FrameIndex) const override;
1257
1258 unsigned getInstBundleSize(const MachineInstr &MI) const;
1259 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
1260
1261 bool mayAccessFlatAddressSpace(const MachineInstr &MI) const;
1262
1263 bool isNonUniformBranchInstr(MachineInstr &Instr) const;
1264
1266 MachineBasicBlock *IfEnd) const;
1267
1269 MachineBasicBlock *LoopEnd) const;
1270
1271 std::pair<unsigned, unsigned>
1272 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
1273
1275 getSerializableTargetIndices() const override;
1276
1279
1282
1285 const ScheduleDAG *DAG) const override;
1286
1288 CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const override;
1289
1292 const ScheduleDAGMI *DAG) const override;
1293
1295 const MachineFunction &MF) const override;
1296
1298 Register Reg = Register()) const override;
1299
1302 const DebugLoc &DL, Register Src,
1303 Register Dst) const override;
1304
1307 const DebugLoc &DL, Register Src,
1308 unsigned SrcSubReg,
1309 Register Dst) const override;
1310
1311 bool isWave32() const;
1312
1313 /// Return a partially built integer add instruction without carry.
1314 /// Caller must add source operands.
1315 /// For pre-GFX9 it will generate unused carry destination operand.
1316 /// TODO: After GFX9 it should return a no-carry operation.
1319 const DebugLoc &DL,
1320 Register DestReg) const;
1321
1324 const DebugLoc &DL,
1325 Register DestReg,
1326 RegScavenger &RS) const;
1327
1328 static bool isKillTerminator(unsigned Opcode);
1329 const MCInstrDesc &getKillTerminatorFromPseudo(unsigned Opcode) const;
1330
1331 bool isLegalMUBUFImmOffset(unsigned Imm) const;
1332
1333 static unsigned getMaxMUBUFImmOffset(const GCNSubtarget &ST);
1334
1335 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
1336 Align Alignment = Align(4)) const;
1337
1338 /// Returns if \p Offset is legal for the subtarget as the offset to a FLAT
1339 /// encoded instruction. If \p Signed, this is for an instruction that
1340 /// interprets the offset as signed.
1341 bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace,
1342 uint64_t FlatVariant) const;
1343
1344 /// Split \p COffsetVal into {immediate offset field, remainder offset}
1345 /// values.
1346 std::pair<int64_t, int64_t> splitFlatOffset(int64_t COffsetVal,
1347 unsigned AddrSpace,
1348 uint64_t FlatVariant) const;
1349
1350 /// Returns true if negative offsets are allowed for the given \p FlatVariant.
1351 bool allowNegativeFlatOffset(uint64_t FlatVariant) const;
1352
1353 /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
1354 /// Return -1 if the target-specific opcode for the pseudo instruction does
1355 /// not exist. If Opcode is not a pseudo instruction, this is identity.
1356 int pseudoToMCOpcode(int Opcode) const;
1357
1358 /// \brief Check if this instruction should only be used by assembler.
1359 /// Return true if this opcode should not be used by codegen.
1360 bool isAsmOnlyOpcode(int MCOp) const;
1361
1362 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
1363 const TargetRegisterInfo *TRI,
1364 const MachineFunction &MF)
1365 const override;
1366
1367 void fixImplicitOperands(MachineInstr &MI) const;
1368
1372 int FrameIndex,
1373 LiveIntervals *LIS = nullptr,
1374 VirtRegMap *VRM = nullptr) const override;
1375
1376 unsigned getInstrLatency(const InstrItineraryData *ItinData,
1377 const MachineInstr &MI,
1378 unsigned *PredCost = nullptr) const override;
1379
1381 getInstructionUniformity(const MachineInstr &MI) const override final;
1382
1385
1386 const MIRFormatter *getMIRFormatter() const override {
1387 if (!Formatter.get())
1388 Formatter = std::make_unique<AMDGPUMIRFormatter>();
1389 return Formatter.get();
1390 }
1391
1392 static unsigned getDSShaderTypeValue(const MachineFunction &MF);
1393
1394 const TargetSchedModel &getSchedModel() const { return SchedModel; }
1395
1396 // Enforce operand's \p OpName even alignment if required by target.
1397 // This is used if an operand is a 32 bit register but needs to be aligned
1398 // regardless.
1399 void enforceOperandRCAlignment(MachineInstr &MI, unsigned OpName) const;
1400};
1401
1402/// \brief Returns true if a reg:subreg pair P has a TRC class
1404 const TargetRegisterClass &TRC,
1406 auto *RC = MRI.getRegClass(P.Reg);
1407 if (!P.SubReg)
1408 return RC == &TRC;
1409 auto *TRI = MRI.getTargetRegisterInfo();
1410 return RC == TRI->getMatchingSuperRegClass(RC, &TRC, P.SubReg);
1411}
1412
1413/// \brief Create RegSubRegPair from a register MachineOperand
1414inline
1416 assert(O.isReg());
1417 return TargetInstrInfo::RegSubRegPair(O.getReg(), O.getSubReg());
1418}
1419
1420/// \brief Return the SubReg component from REG_SEQUENCE
1421TargetInstrInfo::RegSubRegPair getRegSequenceSubReg(MachineInstr &MI,
1422 unsigned SubReg);
1423
1424/// \brief Return the defining instruction for a given reg:subreg pair
1425/// skipping copy like instructions and subreg-manipulation pseudos.
1426/// Following another subreg of a reg:subreg isn't supported.
1427MachineInstr *getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P,
1428 MachineRegisterInfo &MRI);
1429
1430/// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1431/// DefMI and the use at \p UseMI. Should be run on SSA. Currently does not
1432/// attempt to track between blocks.
1433bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI,
1434 Register VReg,
1435 const MachineInstr &DefMI,
1436 const MachineInstr &UseMI);
1437
1438/// \brief Return false if EXEC is not changed between the def of \p VReg at \p
1439/// DefMI and all its uses. Should be run on SSA. Currently does not attempt to
1440/// track between blocks.
1441bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI,
1442 Register VReg,
1443 const MachineInstr &DefMI);
1444
1445namespace AMDGPU {
1446
1448 int getVOPe64(uint16_t Opcode);
1449
1451 int getVOPe32(uint16_t Opcode);
1452
1454 int getSDWAOp(uint16_t Opcode);
1455
1458
1461
1464
1467
1470
1473
1474 /// Check if \p Opcode is an Addr64 opcode.
1475 ///
1476 /// \returns \p Opcode if it is an Addr64 opcode, otherwise -1.
1479
1481 int getSOPKOp(uint16_t Opcode);
1482
1483 /// \returns SADDR form of a FLAT Global instruction given an \p Opcode
1484 /// of a VADDR form.
1487
1488 /// \returns VADDR form of a FLAT Global instruction given an \p Opcode
1489 /// of a SADDR form.
1492
1495
1496 /// \returns ST form with only immediate offset of a FLAT Scratch instruction
1497 /// given an \p Opcode of an SS (SADDR) form.
1500
1501 /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
1502 /// of an SVS (SADDR + VADDR) form.
1505
1506 /// \returns SS (SADDR) form of a FLAT Scratch instruction given an \p Opcode
1507 /// of an SV (VADDR) form.
1510
1511 /// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
1512 /// of an SS (SADDR) form.
1515
1516 /// \returns earlyclobber version of a MAC MFMA is exists.
1519
1520 /// \returns v_cmpx version of a v_cmp instruction.
1523
1524 const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
1527 const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23);
1528
1529} // end namespace AMDGPU
1530
1531namespace AMDGPU {
1533 // For sgpr to vgpr spill instructions
1536} // namespace AMDGPU
1537
1538namespace SI {
1539namespace KernelInputOffsets {
1540
1541/// Offsets in bytes from the start of the input buffer
1551 LOCAL_SIZE_Z = 32
1553
1554} // end namespace KernelInputOffsets
1555} // end namespace SI
1556
1557} // end namespace llvm
1558
1559#endif // LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
unsigned SubReg
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Provides AMDGPU specific target descriptions.
AMDGPU specific overrides of MIRFormatter.
#define LLVM_READONLY
Definition: Compiler.h:227
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
uint64_t Size
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
uint64_t IntrinsicInst * II
#define P(N)
StandardInstrumentations SI(Mod->getContext(), Debug, VerifyEach)
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Interface definition for SIRegisterInfo.
This file implements a set that has insertion order iteration characteristics.
Class for arbitrary precision integers.
Definition: APInt.h:77
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
This class represents an Operation in the Expression.
A debug info location.
Definition: DebugLoc.h:33
Itinerary data supplied by a subtarget to be used by a target.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:85
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:97
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:91
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
MIRFormater - Interface to format MIR operand based on target.
Definition: MIRFormatter.h:32
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
Definition: MachineInstr.h:69
Flags
Flags values. These may be or'd together.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
unsigned getOperandNo() const
Returns the index of this operand in the instruction that it belongs to.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Represents one node in the SelectionDAG.
bool isLegalMUBUFImmOffset(unsigned Imm) const
bool isFLATGlobal(uint16_t Opcode) const
Definition: SIInstrInfo.h:632
bool isInlineConstant(const APInt &Imm) const
static bool isMAI(const MachineInstr &MI)
Definition: SIInstrInfo.h:792
void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const
Fix operands in MI to satisfy constant bus requirements.
static bool isDS(const MachineInstr &MI)
Definition: SIInstrInfo.h:554
static bool isVMEM(const MachineInstr &MI)
Definition: SIInstrInfo.h:432
MachineBasicBlock * legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
Legalize all operands in this instruction.
bool areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, int64_t &Offset0, int64_t &Offset1) const override
bool isNonUniformBranchInstr(MachineInstr &Instr) const
static bool isVOP3(const MachineInstr &MI)
Definition: SIInstrInfo.h:504
unsigned getLiveRangeSplitOpcode(Register Reg, const MachineFunction &MF) const override
bool isSMRD(uint16_t Opcode) const
Definition: SIInstrInfo.h:548
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const final
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
static bool isNeverUniform(const MachineInstr &MI)
Definition: SIInstrInfo.h:924
unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const
Return the size in bytes of the operand OpNo on the given.
Definition: SIInstrInfo.h:1105
bool isAtomic(uint16_t Opcode) const
Definition: SIInstrInfo.h:686
bool isBasicBlockPrologue(const MachineInstr &MI, Register Reg=Register()) const override
bool isLDSDIR(uint16_t Opcode) const
Definition: SIInstrInfo.h:837
bool isFLATScratch(uint16_t Opcode) const
Definition: SIInstrInfo.h:640
uint64_t getDefaultRsrcDataFormat() const
static bool isSOPP(const MachineInstr &MI)
Definition: SIInstrInfo.h:472
InstructionUniformity getGenericInstructionUniformity(const MachineInstr &MI) const
bool hasVGPRUses(const MachineInstr &MI) const
Definition: SIInstrInfo.h:978
uint64_t getClampMask(const MachineInstr &MI) const
Definition: SIInstrInfo.h:900
static bool isFLATScratch(const MachineInstr &MI)
Definition: SIInstrInfo.h:636
const MCInstrDesc & getIndirectRegWriteMovRelPseudo(unsigned VecSize, unsigned EltSize, bool IsSGPR) const
static bool isSpill(const MachineInstr &MI)
Definition: SIInstrInfo.h:744
MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg) const
Return a partially built integer add instruction without carry.
bool mayAccessFlatAddressSpace(const MachineInstr &MI) const
bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0, int64_t Offset1, unsigned NumLoads) const override
bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, Align Alignment=Align(4)) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
void moveToVALU(SIInstrWorklist &Worklist, MachineDominatorTree *MDT) const
Replace the instructions opcode with the equivalent VALU opcode.
static bool isSMRD(const MachineInstr &MI)
Definition: SIInstrInfo.h:544
void restoreExec(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register Reg, SlotIndexes *Indexes=nullptr) const
bool isVGPRSpill(uint16_t Opcode) const
Definition: SIInstrInfo.h:722
bool usesConstantBus(const MachineRegisterInfo &MRI, const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Returns true if this operand uses the constant bus.
static unsigned getMaxMUBUFImmOffset(const GCNSubtarget &ST)
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
void legalizeOperandsFLAT(MachineRegisterInfo &MRI, MachineInstr &MI) const
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
bool isSegmentSpecificFLAT(uint16_t Opcode) const
Definition: SIInstrInfo.h:623
int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const
Get required immediate operand.
Definition: SIInstrInfo.h:1233
bool isVSAMPLE(uint16_t Opcode) const
Definition: SIInstrInfo.h:600
bool isPacked(uint16_t Opcode) const
Definition: SIInstrInfo.h:484
static bool isMTBUF(const MachineInstr &MI)
Definition: SIInstrInfo.h:536
const MCInstrDesc & getIndirectGPRIDXPseudo(unsigned VecSize, bool IsIndirectSrc) const
void insertReturn(MachineBasicBlock &MBB) const
static bool isEXP(const MachineInstr &MI)
Definition: SIInstrInfo.h:649
static bool isSALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:408
bool isVIMAGE(uint16_t Opcode) const
Definition: SIInstrInfo.h:592
void legalizeGenericOperand(MachineBasicBlock &InsertMBB, MachineBasicBlock::iterator I, const TargetRegisterClass *DstRC, MachineOperand &Op, MachineRegisterInfo &MRI, const DebugLoc &DL) const
MachineInstr * buildShrunkInst(MachineInstr &MI, unsigned NewOpcode) const
unsigned getInstBundleSize(const MachineInstr &MI) const
static bool isVOP2(const MachineInstr &MI)
Definition: SIInstrInfo.h:496
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
static bool isSDWA(const MachineInstr &MI)
Definition: SIInstrInfo.h:512
bool isSOP1(uint16_t Opcode) const
Definition: SIInstrInfo.h:444
const MCInstrDesc & getKillTerminatorFromPseudo(unsigned Opcode) const
static bool mayWriteLDSThroughDMA(const MachineInstr &MI)
Definition: SIInstrInfo.h:691
void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Quantity) const override
static bool isVINTRP(const MachineInstr &MI)
Definition: SIInstrInfo.h:784
bool isSWMMAC(uint16_t Opcode) const
Definition: SIInstrInfo.h:825
bool isAtomicRet(uint16_t Opcode) const
Definition: SIInstrInfo.h:677
static bool isGather4(const MachineInstr &MI)
Definition: SIInstrInfo.h:604
static bool isMFMAorWMMA(const MachineInstr &MI)
Definition: SIInstrInfo.h:817
static bool isWQM(const MachineInstr &MI)
Definition: SIInstrInfo.h:695
static bool doesNotReadTiedSource(const MachineInstr &MI)
Definition: SIInstrInfo.h:939
bool isLegalVSrcOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO would be a valid operand for the given operand definition OpInfo.
bool isSOPC(uint16_t Opcode) const
Definition: SIInstrInfo.h:460
static bool isDOT(const MachineInstr &MI)
Definition: SIInstrInfo.h:805
static bool usesFPDPRounding(const MachineInstr &MI)
Definition: SIInstrInfo.h:908
bool isFixedSize(uint16_t Opcode) const
Definition: SIInstrInfo.h:884
bool isImage(uint16_t Opcode) const
Definition: SIInstrInfo.h:428
MachineInstr * createPHISourceCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, unsigned SrcSubReg, Register Dst) const override
bool isGWS(uint16_t Opcode) const
Definition: SIInstrInfo.h:574
Register readlaneVGPRToSGPR(Register SrcReg, MachineInstr &UseMI, MachineRegisterInfo &MRI) const
Copy a value from a VGPR (SrcReg) to SGPR.
bool isInlineConstant(const MachineOperand &MO) const
Definition: SIInstrInfo.h:1051
bool hasModifiers(unsigned Opcode) const
Return true if this instruction has any modifiers.
bool isVOP3(uint16_t Opcode) const
Definition: SIInstrInfo.h:508
bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override
static bool isSWMMAC(const MachineInstr &MI)
Definition: SIInstrInfo.h:821
ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *II, const ScheduleDAGMI *DAG) const override
bool isDOT(uint16_t Opcode) const
Definition: SIInstrInfo.h:829
bool isWave32() const
bool isHighLatencyDef(int Opc) const override
void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const
Legalize the OpIndex operand of this instruction by inserting a MOV.
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
static bool isVOPC(const MachineInstr &MI)
Definition: SIInstrInfo.h:520
void removeModOperands(MachineInstr &MI) const
std::pair< int64_t, int64_t > splitFlatOffset(int64_t COffsetVal, unsigned AddrSpace, uint64_t FlatVariant) const
Split COffsetVal into {immediate offset field, remainder offset} values.
bool isGather4(uint16_t Opcode) const
Definition: SIInstrInfo.h:608
bool isSpill(uint16_t Opcode) const
Definition: SIInstrInfo.h:740
bool isFLAT(uint16_t Opcode) const
Definition: SIInstrInfo.h:645
static bool isVIMAGE(const MachineInstr &MI)
Definition: SIInstrInfo.h:588
static bool isLDSDIR(const MachineInstr &MI)
Definition: SIInstrInfo.h:833
static bool isSOP2(const MachineInstr &MI)
Definition: SIInstrInfo.h:448
static bool isGWS(const MachineInstr &MI)
Definition: SIInstrInfo.h:570
const TargetSchedModel & getSchedModel() const
Definition: SIInstrInfo.h:1394
bool isVOPC(uint16_t Opcode) const
Definition: SIInstrInfo.h:524
bool isInlineConstant(const MachineInstr &MI, const MachineOperand &UseMO, const MachineOperand &DefMO) const
returns true if UseMO is substituted with DefMO in MI it would be an inline immediate.
Definition: SIInstrInfo.h:1016
LLVM_READONLY MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
const MIRFormatter * getMIRFormatter() const override
Definition: SIInstrInfo.h:1386
const TargetRegisterClass * getPreferredSelectRegClass(unsigned Size) const
bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override
bool swapSourceModifiers(MachineInstr &MI, MachineOperand &Src0, unsigned Src0OpName, MachineOperand &Src1, unsigned Src1OpName) const
bool isMAI(uint16_t Opcode) const
Definition: SIInstrInfo.h:796
static bool isFLATGlobal(const MachineInstr &MI)
Definition: SIInstrInfo.h:628
unsigned getMachineCSELookAheadLimit() const override
Definition: SIInstrInfo.h:399
static bool isVSAMPLE(const MachineInstr &MI)
Definition: SIInstrInfo.h:596
static bool isAtomicRet(const MachineInstr &MI)
Definition: SIInstrInfo.h:673
bool isBufferSMRD(const MachineInstr &MI) const
static bool isKillTerminator(unsigned Opcode)
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx0, unsigned &SrcOpIdx1) const override
const GCNSubtarget & getSubtarget() const
Definition: SIInstrInfo.h:226
bool isDS(uint16_t Opcode) const
Definition: SIInstrInfo.h:558
void insertScratchExecCopy(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register Reg, bool IsSCCLive, SlotIndexes *Indexes=nullptr) const
bool isFPAtomic(uint16_t Opcode) const
Definition: SIInstrInfo.h:920
bool hasVALU32BitEncoding(unsigned Opcode) const
Return true if this 64-bit VALU instruction has a 32-bit encoding.
static bool isDisableWQM(const MachineInstr &MI)
Definition: SIInstrInfo.h:703
bool isAtomicNoRet(uint16_t Opcode) const
Definition: SIInstrInfo.h:669
unsigned getMovOpcode(const TargetRegisterClass *DstRC) const
unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
unsigned buildExtractSubReg(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, const MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const
Legalize operands in MI by either commuting it or inserting a copy of src1.
bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const final
static bool isTRANS(const MachineInstr &MI)
Definition: SIInstrInfo.h:768
static bool isImage(const MachineInstr &MI)
Definition: SIInstrInfo.h:424
static bool isSOPK(const MachineInstr &MI)
Definition: SIInstrInfo.h:464
const TargetRegisterClass * getOpRegClass(const MachineInstr &MI, unsigned OpNo) const
Return the correct register class for OpNo.
MachineBasicBlock * insertSimulatedTrap(MachineRegisterInfo &MRI, MachineBasicBlock &MBB, MachineInstr &MI, const DebugLoc &DL) const
Build instructions that simulate the behavior of a s_trap 2 instructions for hardware (namely,...
static unsigned getNonSoftWaitcntOpcode(unsigned Opcode)
Definition: SIInstrInfo.h:947
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const
returns true if the operand OpIdx in MI is a valid inline immediate.
Definition: SIInstrInfo.h:1029
static unsigned getDSShaderTypeValue(const MachineFunction &MF)
static bool isFoldableCopy(const MachineInstr &MI)
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo, const MachineOperand &MO) const
bool isIgnorableUse(const MachineOperand &MO) const override
static bool isVINTERP(const MachineInstr &MI)
Definition: SIInstrInfo.h:841
static bool isMUBUF(const MachineInstr &MI)
Definition: SIInstrInfo.h:528
bool expandPostRAPseudo(MachineInstr &MI) const override
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
bool isSALU(uint16_t Opcode) const
Definition: SIInstrInfo.h:412
void convertNonUniformLoopRegion(MachineBasicBlock *LoopEntry, MachineBasicBlock *LoopEnd) const
bool isVOP2(uint16_t Opcode) const
Definition: SIInstrInfo.h:500
static bool hasFPClamp(const MachineInstr &MI)
Definition: SIInstrInfo.h:888
InstructionUniformity getInstructionUniformity(const MachineInstr &MI) const override final
static bool isSegmentSpecificFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:618
bool isSDWA(uint16_t Opcode) const
Definition: SIInstrInfo.h:516
unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const
This form should usually be preferred since it handles operands with unknown register classes.
Definition: SIInstrInfo.h:1119
bool isInlineConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Definition: SIInstrInfo.h:1009
bool isSOPK(uint16_t Opcode) const
Definition: SIInstrInfo.h:468
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
static bool isChainCallOpcode(uint64_t Opcode)
Definition: SIInstrInfo.h:755
static bool isDPP(const MachineInstr &MI)
Definition: SIInstrInfo.h:760
bool analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const
static bool isMFMA(const MachineInstr &MI)
Definition: SIInstrInfo.h:800
bool isSGPRSpill(uint16_t Opcode) const
Definition: SIInstrInfo.h:734
bool isLowLatencyInstruction(const MachineInstr &MI) const
static bool isScalarStore(const MachineInstr &MI)
Definition: SIInstrInfo.h:872
bool isTRANS(uint16_t Opcode) const
Definition: SIInstrInfo.h:772
void materializeImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DestReg, int64_t Value) const
bool isLDSDMA(uint16_t Opcode)
Definition: SIInstrInfo.h:566
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
bool isSOP2(uint16_t Opcode) const
Definition: SIInstrInfo.h:452
bool isVALU(uint16_t Opcode) const
Definition: SIInstrInfo.h:420
bool isVOP1(uint16_t Opcode) const
Definition: SIInstrInfo.h:492
bool isAlwaysGDS(uint16_t Opcode) const
bool isMUBUF(uint16_t Opcode) const
Definition: SIInstrInfo.h:532
static bool isFPAtomic(const MachineInstr &MI)
Definition: SIInstrInfo.h:916
static bool usesLGKM_CNT(const MachineInstr &MI)
Definition: SIInstrInfo.h:857
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
void moveToVALUImpl(SIInstrWorklist &Worklist, MachineDominatorTree *MDT, MachineInstr &Inst) const
static bool isPacked(const MachineInstr &MI)
Definition: SIInstrInfo.h:480
bool canShrink(const MachineInstr &MI, const MachineRegisterInfo &MRI) const
bool isAsmOnlyOpcode(int MCOp) const
Check if this instruction should only be used by assembler.
bool isWMMA(uint16_t Opcode) const
Definition: SIInstrInfo.h:813
bool isMTBUF(uint16_t Opcode) const
Definition: SIInstrInfo.h:540
bool isDisableWQM(uint16_t Opcode) const
Definition: SIInstrInfo.h:707
static bool isVGPRSpill(const MachineInstr &MI)
Definition: SIInstrInfo.h:716
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
This is used by the post-RA scheduler (SchedulePostRAList.cpp).
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
bool isLegalFLATOffset(int64_t Offset, unsigned AddrSpace, uint64_t FlatVariant) const
Returns if Offset is legal for the subtarget as the offset to a FLAT encoded instruction.
static bool isWWMRegSpillOpcode(uint16_t Opcode)
Definition: SIInstrInfo.h:748
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
bool isVMEM(uint16_t Opcode) const
Definition: SIInstrInfo.h:436
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const override
bool isVINTRP(uint16_t Opcode) const
Definition: SIInstrInfo.h:788
bool isVGPRCopy(const MachineInstr &MI) const
Definition: SIInstrInfo.h:970
bool isScalarStore(uint16_t Opcode) const
Definition: SIInstrInfo.h:876
static bool isMIMG(const MachineInstr &MI)
Definition: SIInstrInfo.h:580
MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, const MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
bool isLegalRegOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO (a register operand) is a legal register for the given operand description.
bool allowNegativeFlatOffset(uint64_t FlatVariant) const
Returns true if negative offsets are allowed for the given FlatVariant.
LLVM_READONLY int commuteOpcode(const MachineInstr &MI) const
Definition: SIInstrInfo.h:318
static unsigned getNumWaitStates(const MachineInstr &MI)
Return the number of wait states that result from executing this instruction.
const TargetRegisterClass * getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const override
static bool isVOP3P(const MachineInstr &MI)
Definition: SIInstrInfo.h:776
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
bool isWQM(uint16_t Opcode) const
Definition: SIInstrInfo.h:699
unsigned getVALUOp(const MachineInstr &MI) const
static bool modifiesModeRegister(const MachineInstr &MI)
Return true if the instruction modifies the mode register.q.
void convertNonUniformIfRegion(MachineBasicBlock *IfEntry, MachineBasicBlock *IfEnd) const
bool hasDivergentBranch(const MachineBasicBlock *MBB) const
Return whether the block terminate with divergent branch.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void fixImplicitOperands(MachineInstr &MI) const
bool moveFlatAddrToVGPR(MachineInstr &Inst) const
Change SADDR form of a FLAT Inst to its VADDR form if saddr operand was moved to VGPR.
bool isVOP3P(uint16_t Opcode) const
Definition: SIInstrInfo.h:780
LLVM_READONLY const MachineOperand * getNamedOperand(const MachineInstr &MI, unsigned OpName) const
Definition: SIInstrInfo.h:1227
bool isEXP(uint16_t Opcode) const
Definition: SIInstrInfo.h:661
Register insertNE(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
static bool isDualSourceBlendEXP(const MachineInstr &MI)
Definition: SIInstrInfo.h:653
bool hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const
Whether we must prevent this instruction from executing with EXEC = 0.
static bool isAtomic(const MachineInstr &MI)
Definition: SIInstrInfo.h:681
bool canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const override
static bool sopkIsZext(unsigned Opcode)
Definition: SIInstrInfo.h:863
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
static bool isSGPRSpill(const MachineInstr &MI)
Definition: SIInstrInfo.h:728
static bool isWMMA(const MachineInstr &MI)
Definition: SIInstrInfo.h:809
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const override
bool isVINTERP(uint16_t Opcode) const
Definition: SIInstrInfo.h:845
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const
Returns true if the instruction could potentially depend on the value of exec.
void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
bool doesNotReadTiedSource(uint16_t Opcode) const
Definition: SIInstrInfo.h:943
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool isDPP(uint16_t Opcode) const
Definition: SIInstrInfo.h:764
void insertVectorSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
std::pair< MachineInstr *, MachineInstr * > expandMovDPP64(MachineInstr &MI) const
Register insertEQ(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const
static bool isSOP1(const MachineInstr &MI)
Definition: SIInstrInfo.h:440
static bool isSOPC(const MachineInstr &MI)
Definition: SIInstrInfo.h:456
static bool isFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:612
const SIRegisterInfo & getRegisterInfo() const
Definition: SIInstrInfo.h:222
static bool isVALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:416
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx0, unsigned OpIdx1) const override
void enforceOperandRCAlignment(MachineInstr &MI, unsigned OpName) const
static bool hasIntClamp(const MachineInstr &MI)
Definition: SIInstrInfo.h:896
int pseudoToMCOpcode(int Opcode) const
Return a target-specific opcode if Opcode is a pseudo instruction.
const MCInstrDesc & getMCOpcodeFromPseudo(unsigned Opcode) const
Return the descriptor of the target-specific machine instruction that corresponds to the specified ps...
Definition: SIInstrInfo.h:1246
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx, const MachineOperand &MO) const
Definition: SIInstrInfo.h:1034
static bool isScalarUnit(const MachineInstr &MI)
Definition: SIInstrInfo.h:849
bool isSOPP(uint16_t Opcode) const
Definition: SIInstrInfo.h:476
bool isMIMG(uint16_t Opcode) const
Definition: SIInstrInfo.h:584
bool hasFPClamp(uint16_t Opcode) const
Definition: SIInstrInfo.h:892
static bool usesVM_CNT(const MachineInstr &MI)
Definition: SIInstrInfo.h:853
bool usesFPDPRounding(uint16_t Opcode) const
Definition: SIInstrInfo.h:912
MachineInstr * createPHIDestinationCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register Dst) const override
bool hasModifiersSet(const MachineInstr &MI, unsigned OpName) const
static bool isFixedSize(const MachineInstr &MI)
Definition: SIInstrInfo.h:880
bool isSafeToSink(MachineInstr &MI, MachineBasicBlock *SuccToSinkTo, MachineCycleInfo *CI) const override
LLVM_READONLY int commuteOpcode(unsigned Opc) const
uint64_t getScratchRsrcWords23() const
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const
Check if MO is a legal operand if it was the OpIdx Operand for MI.
bool isBarrierStart(unsigned Opcode) const
Definition: SIInstrInfo.h:931
static bool isLDSDMA(const MachineInstr &MI)
Definition: SIInstrInfo.h:562
unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const
static bool isAtomicNoRet(const MachineInstr &MI)
Definition: SIInstrInfo.h:665
static bool isVOP1(const MachineInstr &MI)
Definition: SIInstrInfo.h:488
void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
bool hasAnyModifiersSet(const MachineInstr &MI) const
const TargetRegisterClass * getRegClass(unsigned RCID) const
bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
A vector that has set insertion semantics.
Definition: SetVector.h:57
SlotIndexes pass.
Definition: SlotIndexes.h:300
A SetVector that performs no allocations if smaller than a certain size.
Definition: SetVector.h:370
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Provide an instruction scheduling machine model to CodeGen passes.
Target - Wrapper for Target specific information.
LLVM Value Representation.
Definition: Value.h:74
const uint64_t RSRC_DATA_FORMAT
Definition: SIInstrInfo.h:1524
LLVM_READONLY int getBasicFromSDWAOp(uint16_t Opcode)
LLVM_READONLY int getGlobalSaddrOp(uint16_t Opcode)
LLVM_READONLY int getSOPKOp(uint16_t Opcode)
LLVM_READONLY int getVOPe32(uint16_t Opcode)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
LLVM_READONLY int getDPPOp32(uint16_t Opcode)
LLVM_READONLY int getFlatScratchInstSVfromSS(uint16_t Opcode)
LLVM_READONLY int getFlatScratchInstSTfromSS(uint16_t Opcode)
LLVM_READONLY int getGlobalVaddrOp(uint16_t Opcode)
const uint64_t RSRC_ELEMENT_SIZE_SHIFT
Definition: SIInstrInfo.h:1525
LLVM_READONLY int getFlatScratchInstSVfromSVS(uint16_t Opcode)
LLVM_READONLY int getAddr64Inst(uint16_t Opcode)
LLVM_READONLY int getMFMAEarlyClobberOp(uint16_t Opcode)
LLVM_READONLY int getVCMPXOpFromVCMP(uint16_t Opcode)
LLVM_READONLY int getSDWAOp(uint16_t Opcode)
const uint64_t RSRC_TID_ENABLE
Definition: SIInstrInfo.h:1527
LLVM_READONLY int getCommuteRev(uint16_t Opcode)
LLVM_READONLY int getDPPOp64(uint16_t Opcode)
LLVM_READONLY int getVOPe64(uint16_t Opcode)
@ OPERAND_REG_IMM_INT64
Definition: SIDefines.h:201
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition: SIDefines.h:200
LLVM_READONLY int getCommuteOrig(uint16_t Opcode)
const uint64_t RSRC_INDEX_STRIDE_SHIFT
Definition: SIInstrInfo.h:1526
LLVM_READONLY int getFlatScratchInstSSfromSV(uint16_t Opcode)
LLVM_READONLY int getVCMPXNoSDstOp(uint16_t Opcode)
LLVM_READONLY int getIfAddr64Inst(uint16_t Opcode)
Check if Opcode is an Addr64 opcode.
@ OPERAND_IMMEDIATE
Definition: MCInstrDesc.h:60
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1542
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
TargetInstrInfo::RegSubRegPair getRegSubRegPair(const MachineOperand &O)
Create RegSubRegPair from a register MachineOperand.
Definition: SIInstrInfo.h:1415
bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI, Register VReg, const MachineInstr &DefMI, const MachineInstr &UseMI)
Return false if EXEC is not changed between the def of VReg at DefMI and the use at UseMI.
TargetInstrInfo::RegSubRegPair getRegSequenceSubReg(MachineInstr &MI, unsigned SubReg)
Return the SubReg component from REG_SEQUENCE.
static const MachineMemOperand::Flags MONoClobber
Mark the MMO of a uniform load if there are no potentially clobbering stores on any path from the sta...
Definition: SIInstrInfo.h:41
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1729
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
MachineInstr * getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P, MachineRegisterInfo &MRI)
Return the defining instruction for a given reg:subreg pair skipping copy like instructions and subre...
static const MachineMemOperand::Flags MOLastUse
Mark the MMO of a load as the last use.
Definition: SIInstrInfo.h:45
bool isOfRegClass(const TargetInstrInfo::RegSubRegPair &P, const TargetRegisterClass &TRC, MachineRegisterInfo &MRI)
Returns true if a reg:subreg pair P has a TRC class.
Definition: SIInstrInfo.h:1403
InstructionUniformity
Enum describing how instructions behave with respect to uniformity and divergence,...
Definition: Uniformity.h:18
bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI, Register VReg, const MachineInstr &DefMI)
Return false if EXEC is not changed between the def of VReg at DefMI and all its uses.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Description of the encoding of one expression Op.
Utility to store machine instructions worklist.
Definition: SIInstrInfo.h:49
MachineInstr * top() const
Definition: SIInstrInfo.h:54
bool empty() const
Definition: SIInstrInfo.h:64
bool isDeferred(MachineInstr *MI)
SetVector< MachineInstr * > & getDeferredList()
Definition: SIInstrInfo.h:73
void insert(MachineInstr *MI)
A pair composed of a register and a sub-register index.