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SIInstrInfo.h
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1 //===- SIInstrInfo.h - SI Instruction Info Interface ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Interface definition for SIInstrInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
16 
17 #include "AMDGPUInstrInfo.h"
18 #include "SIDefines.h"
19 #include "SIRegisterInfo.h"
20 #include "Utils/AMDGPUBaseInfo.h"
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/SetVector.h"
28 #include "llvm/MC/MCInstrDesc.h"
29 #include "llvm/Support/Compiler.h"
30 #include <cassert>
31 #include <cstdint>
32 
33 #define GET_INSTRINFO_HEADER
34 #include "AMDGPUGenInstrInfo.inc"
35 
36 namespace llvm {
37 
38 class APInt;
39 class MachineDominatorTree;
40 class MachineRegisterInfo;
41 class RegScavenger;
42 class GCNSubtarget;
43 class TargetRegisterClass;
44 
45 class SIInstrInfo final : public AMDGPUGenInstrInfo {
46 private:
47  const SIRegisterInfo RI;
48  const GCNSubtarget &ST;
49 
50  // The inverse predicate should have the negative value.
51  enum BranchPredicate {
52  INVALID_BR = 0,
53  SCC_TRUE = 1,
54  SCC_FALSE = -1,
55  VCCNZ = 2,
56  VCCZ = -2,
57  EXECNZ = -3,
58  EXECZ = 3
59  };
60 
62 
63  static unsigned getBranchOpcode(BranchPredicate Cond);
64  static BranchPredicate getBranchPredicate(unsigned Opcode);
65 
66 public:
69  MachineOperand &SuperReg,
70  const TargetRegisterClass *SuperRC,
71  unsigned SubIdx,
72  const TargetRegisterClass *SubRC) const;
75  MachineOperand &SuperReg,
76  const TargetRegisterClass *SuperRC,
77  unsigned SubIdx,
78  const TargetRegisterClass *SubRC) const;
79 private:
80  void swapOperands(MachineInstr &Inst) const;
81 
82  bool moveScalarAddSub(SetVectorType &Worklist, MachineInstr &Inst,
83  MachineDominatorTree *MDT = nullptr) const;
84 
85  void lowerScalarAbs(SetVectorType &Worklist,
86  MachineInstr &Inst) const;
87 
88  void lowerScalarXnor(SetVectorType &Worklist,
89  MachineInstr &Inst) const;
90 
91  void splitScalarNotBinop(SetVectorType &Worklist,
92  MachineInstr &Inst,
93  unsigned Opcode) const;
94 
95  void splitScalarBinOpN2(SetVectorType &Worklist,
96  MachineInstr &Inst,
97  unsigned Opcode) const;
98 
99  void splitScalar64BitUnaryOp(SetVectorType &Worklist,
100  MachineInstr &Inst, unsigned Opcode) const;
101 
102  void splitScalar64BitAddSub(SetVectorType &Worklist, MachineInstr &Inst,
103  MachineDominatorTree *MDT = nullptr) const;
104 
105  void splitScalar64BitBinaryOp(SetVectorType &Worklist, MachineInstr &Inst,
106  unsigned Opcode,
107  MachineDominatorTree *MDT = nullptr) const;
108 
109  void splitScalar64BitXnor(SetVectorType &Worklist, MachineInstr &Inst,
110  MachineDominatorTree *MDT = nullptr) const;
111 
112  void splitScalar64BitBCNT(SetVectorType &Worklist,
113  MachineInstr &Inst) const;
114  void splitScalar64BitBFE(SetVectorType &Worklist,
115  MachineInstr &Inst) const;
116  void movePackToVALU(SetVectorType &Worklist,
117  MachineRegisterInfo &MRI,
118  MachineInstr &Inst) const;
119 
120  void addUsersToMoveToVALUWorklist(unsigned Reg, MachineRegisterInfo &MRI,
121  SetVectorType &Worklist) const;
122 
123  void addSCCDefUsersToVALUWorklist(MachineOperand &Op,
124  MachineInstr &SCCDefInst,
125  SetVectorType &Worklist) const;
126 
127  const TargetRegisterClass *
128  getDestEquivalentVGPRClass(const MachineInstr &Inst) const;
129 
130  bool checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
131  const MachineInstr &MIb) const;
132 
133  unsigned findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
134 
135 protected:
137  MachineOperand &Src0, unsigned Src0OpName,
138  MachineOperand &Src1, unsigned Src1OpName) const;
139 
141  unsigned OpIdx0,
142  unsigned OpIdx1) const override;
143 
144 public:
146  MO_MASK = 0x7,
147 
148  MO_NONE = 0,
149  // MO_GOTPCREL -> symbol@GOTPCREL -> R_AMDGPU_GOTPCREL.
151  // MO_GOTPCREL32_LO -> symbol@gotpcrel32@lo -> R_AMDGPU_GOTPCREL32_LO.
154  // MO_GOTPCREL32_HI -> symbol@gotpcrel32@hi -> R_AMDGPU_GOTPCREL32_HI.
156  // MO_REL32_LO -> symbol@rel32@lo -> R_AMDGPU_REL32_LO.
157  MO_REL32 = 4,
159  // MO_REL32_HI -> symbol@rel32@hi -> R_AMDGPU_REL32_HI.
161  };
162 
163  explicit SIInstrInfo(const GCNSubtarget &ST);
164 
166  return RI;
167  }
168 
170  AliasAnalysis *AA) const override;
171 
172  bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
173  int64_t &Offset1,
174  int64_t &Offset2) const override;
175 
176  bool getMemOperandWithOffset(const MachineInstr &LdSt,
177  const MachineOperand *&BaseOp,
178  int64_t &Offset,
179  const TargetRegisterInfo *TRI) const final;
180 
181  bool shouldClusterMemOps(const MachineOperand &BaseOp1,
182  const MachineOperand &BaseOp2,
183  unsigned NumLoads) const override;
184 
185  bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
186  int64_t Offset1, unsigned NumLoads) const override;
187 
189  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
190  bool KillSrc) const override;
191 
193  RegScavenger *RS, unsigned TmpReg,
194  unsigned Offset, unsigned Size) const;
195 
198  const DebugLoc &DL,
199  unsigned DestReg,
200  int64_t Value) const;
201 
203  unsigned Size) const;
204 
205  unsigned insertNE(MachineBasicBlock *MBB,
207  unsigned SrcReg, int Value) const;
208 
209  unsigned insertEQ(MachineBasicBlock *MBB,
211  unsigned SrcReg, int Value) const;
212 
214  MachineBasicBlock::iterator MI, unsigned SrcReg,
215  bool isKill, int FrameIndex,
216  const TargetRegisterClass *RC,
217  const TargetRegisterInfo *TRI) const override;
218 
220  MachineBasicBlock::iterator MI, unsigned DestReg,
221  int FrameIndex, const TargetRegisterClass *RC,
222  const TargetRegisterInfo *TRI) const override;
223 
224  bool expandPostRAPseudo(MachineInstr &MI) const override;
225 
226  // Returns an opcode that can be used to move a value to a \p DstRC
227  // register. If there is no hardware instruction that can store to \p
228  // DstRC, then AMDGPU::COPY is returned.
229  unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
230 
232  int commuteOpcode(unsigned Opc) const;
233 
235  inline int commuteOpcode(const MachineInstr &MI) const {
236  return commuteOpcode(MI.getOpcode());
237  }
238 
239  bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
240  unsigned &SrcOpIdx2) const override;
241 
242  bool findCommutedOpIndices(MCInstrDesc Desc, unsigned & SrcOpIdx0,
243  unsigned & SrcOpIdx1) const;
244 
245  bool isBranchOffsetInRange(unsigned BranchOpc,
246  int64_t BrOffset) const override;
247 
248  MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
249 
251  MachineBasicBlock &NewDestBB,
252  const DebugLoc &DL,
253  int64_t BrOffset,
254  RegScavenger *RS = nullptr) const override;
255 
258  MachineBasicBlock *&TBB,
259  MachineBasicBlock *&FBB,
261  bool AllowModify) const;
262 
264  MachineBasicBlock *&FBB,
266  bool AllowModify = false) const override;
267 
268  unsigned removeBranch(MachineBasicBlock &MBB,
269  int *BytesRemoved = nullptr) const override;
270 
273  const DebugLoc &DL,
274  int *BytesAdded = nullptr) const override;
275 
277  SmallVectorImpl<MachineOperand> &Cond) const override;
278 
279  bool canInsertSelect(const MachineBasicBlock &MBB,
281  unsigned TrueReg, unsigned FalseReg,
282  int &CondCycles,
283  int &TrueCycles, int &FalseCycles) const override;
284 
287  unsigned DstReg, ArrayRef<MachineOperand> Cond,
288  unsigned TrueReg, unsigned FalseReg) const override;
289 
292  unsigned DstReg, ArrayRef<MachineOperand> Cond,
293  unsigned TrueReg, unsigned FalseReg) const;
294 
296  unsigned Kind) const override;
297 
298  bool
300  const MachineInstr &MIb,
301  AliasAnalysis *AA = nullptr) const override;
302 
303  bool isFoldableCopy(const MachineInstr &MI) const;
304 
305  bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
306  MachineRegisterInfo *MRI) const final;
307 
308  unsigned getMachineCSELookAheadLimit() const override { return 500; }
309 
311  MachineInstr &MI,
312  LiveVariables *LV) const override;
313 
314  bool isSchedulingBoundary(const MachineInstr &MI,
315  const MachineBasicBlock *MBB,
316  const MachineFunction &MF) const override;
317 
318  static bool isSALU(const MachineInstr &MI) {
319  return MI.getDesc().TSFlags & SIInstrFlags::SALU;
320  }
321 
322  bool isSALU(uint16_t Opcode) const {
323  return get(Opcode).TSFlags & SIInstrFlags::SALU;
324  }
325 
326  static bool isVALU(const MachineInstr &MI) {
327  return MI.getDesc().TSFlags & SIInstrFlags::VALU;
328  }
329 
330  bool isVALU(uint16_t Opcode) const {
331  return get(Opcode).TSFlags & SIInstrFlags::VALU;
332  }
333 
334  static bool isVMEM(const MachineInstr &MI) {
335  return isMUBUF(MI) || isMTBUF(MI) || isMIMG(MI);
336  }
337 
338  bool isVMEM(uint16_t Opcode) const {
339  return isMUBUF(Opcode) || isMTBUF(Opcode) || isMIMG(Opcode);
340  }
341 
342  static bool isSOP1(const MachineInstr &MI) {
343  return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
344  }
345 
346  bool isSOP1(uint16_t Opcode) const {
347  return get(Opcode).TSFlags & SIInstrFlags::SOP1;
348  }
349 
350  static bool isSOP2(const MachineInstr &MI) {
351  return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
352  }
353 
354  bool isSOP2(uint16_t Opcode) const {
355  return get(Opcode).TSFlags & SIInstrFlags::SOP2;
356  }
357 
358  static bool isSOPC(const MachineInstr &MI) {
359  return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
360  }
361 
362  bool isSOPC(uint16_t Opcode) const {
363  return get(Opcode).TSFlags & SIInstrFlags::SOPC;
364  }
365 
366  static bool isSOPK(const MachineInstr &MI) {
367  return MI.getDesc().TSFlags & SIInstrFlags::SOPK;
368  }
369 
370  bool isSOPK(uint16_t Opcode) const {
371  return get(Opcode).TSFlags & SIInstrFlags::SOPK;
372  }
373 
374  static bool isSOPP(const MachineInstr &MI) {
375  return MI.getDesc().TSFlags & SIInstrFlags::SOPP;
376  }
377 
378  bool isSOPP(uint16_t Opcode) const {
379  return get(Opcode).TSFlags & SIInstrFlags::SOPP;
380  }
381 
382  static bool isPacked(const MachineInstr &MI) {
383  return MI.getDesc().TSFlags & SIInstrFlags::IsPacked;
384  }
385 
386  bool isPacked(uint16_t Opcode) const {
387  return get(Opcode).TSFlags & SIInstrFlags::IsPacked;
388  }
389 
390  static bool isVOP1(const MachineInstr &MI) {
391  return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
392  }
393 
394  bool isVOP1(uint16_t Opcode) const {
395  return get(Opcode).TSFlags & SIInstrFlags::VOP1;
396  }
397 
398  static bool isVOP2(const MachineInstr &MI) {
399  return MI.getDesc().TSFlags & SIInstrFlags::VOP2;
400  }
401 
402  bool isVOP2(uint16_t Opcode) const {
403  return get(Opcode).TSFlags & SIInstrFlags::VOP2;
404  }
405 
406  static bool isVOP3(const MachineInstr &MI) {
407  return MI.getDesc().TSFlags & SIInstrFlags::VOP3;
408  }
409 
410  bool isVOP3(uint16_t Opcode) const {
411  return get(Opcode).TSFlags & SIInstrFlags::VOP3;
412  }
413 
414  static bool isSDWA(const MachineInstr &MI) {
415  return MI.getDesc().TSFlags & SIInstrFlags::SDWA;
416  }
417 
418  bool isSDWA(uint16_t Opcode) const {
419  return get(Opcode).TSFlags & SIInstrFlags::SDWA;
420  }
421 
422  static bool isVOPC(const MachineInstr &MI) {
423  return MI.getDesc().TSFlags & SIInstrFlags::VOPC;
424  }
425 
426  bool isVOPC(uint16_t Opcode) const {
427  return get(Opcode).TSFlags & SIInstrFlags::VOPC;
428  }
429 
430  static bool isMUBUF(const MachineInstr &MI) {
431  return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;
432  }
433 
434  bool isMUBUF(uint16_t Opcode) const {
435  return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
436  }
437 
438  static bool isMTBUF(const MachineInstr &MI) {
439  return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;
440  }
441 
442  bool isMTBUF(uint16_t Opcode) const {
443  return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
444  }
445 
446  static bool isSMRD(const MachineInstr &MI) {
447  return MI.getDesc().TSFlags & SIInstrFlags::SMRD;
448  }
449 
450  bool isSMRD(uint16_t Opcode) const {
451  return get(Opcode).TSFlags & SIInstrFlags::SMRD;
452  }
453 
454  bool isBufferSMRD(const MachineInstr &MI) const;
455 
456  static bool isDS(const MachineInstr &MI) {
457  return MI.getDesc().TSFlags & SIInstrFlags::DS;
458  }
459 
460  bool isDS(uint16_t Opcode) const {
461  return get(Opcode).TSFlags & SIInstrFlags::DS;
462  }
463 
464  bool isAlwaysGDS(uint16_t Opcode) const;
465 
466  static bool isMIMG(const MachineInstr &MI) {
467  return MI.getDesc().TSFlags & SIInstrFlags::MIMG;
468  }
469 
470  bool isMIMG(uint16_t Opcode) const {
471  return get(Opcode).TSFlags & SIInstrFlags::MIMG;
472  }
473 
474  static bool isGather4(const MachineInstr &MI) {
475  return MI.getDesc().TSFlags & SIInstrFlags::Gather4;
476  }
477 
478  bool isGather4(uint16_t Opcode) const {
479  return get(Opcode).TSFlags & SIInstrFlags::Gather4;
480  }
481 
482  static bool isFLAT(const MachineInstr &MI) {
483  return MI.getDesc().TSFlags & SIInstrFlags::FLAT;
484  }
485 
486  // Is a FLAT encoded instruction which accesses a specific segment,
487  // i.e. global_* or scratch_*.
488  static bool isSegmentSpecificFLAT(const MachineInstr &MI) {
489  auto Flags = MI.getDesc().TSFlags;
490  return (Flags & SIInstrFlags::FLAT) && !(Flags & SIInstrFlags::LGKM_CNT);
491  }
492 
493  // Any FLAT encoded instruction, including global_* and scratch_*.
494  bool isFLAT(uint16_t Opcode) const {
495  return get(Opcode).TSFlags & SIInstrFlags::FLAT;
496  }
497 
498  static bool isEXP(const MachineInstr &MI) {
499  return MI.getDesc().TSFlags & SIInstrFlags::EXP;
500  }
501 
502  bool isEXP(uint16_t Opcode) const {
503  return get(Opcode).TSFlags & SIInstrFlags::EXP;
504  }
505 
506  static bool isWQM(const MachineInstr &MI) {
507  return MI.getDesc().TSFlags & SIInstrFlags::WQM;
508  }
509 
510  bool isWQM(uint16_t Opcode) const {
511  return get(Opcode).TSFlags & SIInstrFlags::WQM;
512  }
513 
514  static bool isDisableWQM(const MachineInstr &MI) {
516  }
517 
518  bool isDisableWQM(uint16_t Opcode) const {
519  return get(Opcode).TSFlags & SIInstrFlags::DisableWQM;
520  }
521 
522  static bool isVGPRSpill(const MachineInstr &MI) {
524  }
525 
526  bool isVGPRSpill(uint16_t Opcode) const {
527  return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;
528  }
529 
530  static bool isSGPRSpill(const MachineInstr &MI) {
532  }
533 
534  bool isSGPRSpill(uint16_t Opcode) const {
535  return get(Opcode).TSFlags & SIInstrFlags::SGPRSpill;
536  }
537 
538  static bool isDPP(const MachineInstr &MI) {
539  return MI.getDesc().TSFlags & SIInstrFlags::DPP;
540  }
541 
542  bool isDPP(uint16_t Opcode) const {
543  return get(Opcode).TSFlags & SIInstrFlags::DPP;
544  }
545 
546  static bool isVOP3P(const MachineInstr &MI) {
547  return MI.getDesc().TSFlags & SIInstrFlags::VOP3P;
548  }
549 
550  bool isVOP3P(uint16_t Opcode) const {
551  return get(Opcode).TSFlags & SIInstrFlags::VOP3P;
552  }
553 
554  static bool isVINTRP(const MachineInstr &MI) {
555  return MI.getDesc().TSFlags & SIInstrFlags::VINTRP;
556  }
557 
558  bool isVINTRP(uint16_t Opcode) const {
559  return get(Opcode).TSFlags & SIInstrFlags::VINTRP;
560  }
561 
562  static bool isScalarUnit(const MachineInstr &MI) {
564  }
565 
566  static bool usesVM_CNT(const MachineInstr &MI) {
567  return MI.getDesc().TSFlags & SIInstrFlags::VM_CNT;
568  }
569 
570  static bool usesLGKM_CNT(const MachineInstr &MI) {
571  return MI.getDesc().TSFlags & SIInstrFlags::LGKM_CNT;
572  }
573 
574  static bool sopkIsZext(const MachineInstr &MI) {
576  }
577 
578  bool sopkIsZext(uint16_t Opcode) const {
579  return get(Opcode).TSFlags & SIInstrFlags::SOPK_ZEXT;
580  }
581 
582  /// \returns true if this is an s_store_dword* instruction. This is more
583  /// specific than than isSMEM && mayStore.
584  static bool isScalarStore(const MachineInstr &MI) {
586  }
587 
588  bool isScalarStore(uint16_t Opcode) const {
589  return get(Opcode).TSFlags & SIInstrFlags::SCALAR_STORE;
590  }
591 
592  static bool isFixedSize(const MachineInstr &MI) {
594  }
595 
596  bool isFixedSize(uint16_t Opcode) const {
597  return get(Opcode).TSFlags & SIInstrFlags::FIXED_SIZE;
598  }
599 
600  static bool hasFPClamp(const MachineInstr &MI) {
601  return MI.getDesc().TSFlags & SIInstrFlags::FPClamp;
602  }
603 
604  bool hasFPClamp(uint16_t Opcode) const {
605  return get(Opcode).TSFlags & SIInstrFlags::FPClamp;
606  }
607 
608  static bool hasIntClamp(const MachineInstr &MI) {
609  return MI.getDesc().TSFlags & SIInstrFlags::IntClamp;
610  }
611 
612  uint64_t getClampMask(const MachineInstr &MI) const {
613  const uint64_t ClampFlags = SIInstrFlags::FPClamp |
617  return MI.getDesc().TSFlags & ClampFlags;
618  }
619 
620  static bool usesFPDPRounding(const MachineInstr &MI) {
622  }
623 
624  bool usesFPDPRounding(uint16_t Opcode) const {
625  return get(Opcode).TSFlags & SIInstrFlags::FPDPRounding;
626  }
627 
628  bool isVGPRCopy(const MachineInstr &MI) const {
629  assert(MI.isCopy());
630  unsigned Dest = MI.getOperand(0).getReg();
631  const MachineFunction &MF = *MI.getParent()->getParent();
632  const MachineRegisterInfo &MRI = MF.getRegInfo();
633  return !RI.isSGPRReg(MRI, Dest);
634  }
635 
636  /// Whether we must prevent this instruction from executing with EXEC = 0.
637  bool hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const;
638 
639  /// Returns true if the instruction could potentially depend on the value of
640  /// exec. If false, exec dependencies may safely be ignored.
641  bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const;
642 
643  bool isInlineConstant(const APInt &Imm) const;
644 
645  bool isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const;
646 
648  const MCOperandInfo &OpInfo) const {
649  return isInlineConstant(MO, OpInfo.OperandType);
650  }
651 
652  /// \p returns true if \p UseMO is substituted with \p DefMO in \p MI it would
653  /// be an inline immediate.
655  const MachineOperand &UseMO,
656  const MachineOperand &DefMO) const {
657  assert(UseMO.getParent() == &MI);
658  int OpIdx = MI.getOperandNo(&UseMO);
659  if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands) {
660  return false;
661  }
662 
663  return isInlineConstant(DefMO, MI.getDesc().OpInfo[OpIdx]);
664  }
665 
666  /// \p returns true if the operand \p OpIdx in \p MI is a valid inline
667  /// immediate.
668  bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const {
669  const MachineOperand &MO = MI.getOperand(OpIdx);
670  return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
671  }
672 
673  bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
674  const MachineOperand &MO) const {
675  if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands)
676  return false;
677 
678  if (MI.isCopy()) {
679  unsigned Size = getOpSize(MI, OpIdx);
680  assert(Size == 8 || Size == 4);
681 
682  uint8_t OpType = (Size == 8) ?
684  return isInlineConstant(MO, OpType);
685  }
686 
687  return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
688  }
689 
690  bool isInlineConstant(const MachineOperand &MO) const {
691  const MachineInstr *Parent = MO.getParent();
692  return isInlineConstant(*Parent, Parent->getOperandNo(&MO));
693  }
694 
696  const MCOperandInfo &OpInfo) const {
697  return MO.isImm() && !isInlineConstant(MO, OpInfo.OperandType);
698  }
699 
700  bool isLiteralConstant(const MachineInstr &MI, int OpIdx) const {
701  const MachineOperand &MO = MI.getOperand(OpIdx);
702  return MO.isImm() && !isInlineConstant(MI, OpIdx);
703  }
704 
705  // Returns true if this operand could potentially require a 32-bit literal
706  // operand, but not necessarily. A FrameIndex for example could resolve to an
707  // inline immediate value that will not require an additional 4-bytes; this
708  // assumes that it will.
709  bool isLiteralConstantLike(const MachineOperand &MO,
710  const MCOperandInfo &OpInfo) const;
711 
712  bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
713  const MachineOperand &MO) const;
714 
715  /// Return true if this 64-bit VALU instruction has a 32-bit encoding.
716  /// This function will return false if you pass it a 32-bit instruction.
717  bool hasVALU32BitEncoding(unsigned Opcode) const;
718 
719  /// Returns true if this operand uses the constant bus.
720  bool usesConstantBus(const MachineRegisterInfo &MRI,
721  const MachineOperand &MO,
722  const MCOperandInfo &OpInfo) const;
723 
724  /// Return true if this instruction has any modifiers.
725  /// e.g. src[012]_mod, omod, clamp.
726  bool hasModifiers(unsigned Opcode) const;
727 
728  bool hasModifiersSet(const MachineInstr &MI,
729  unsigned OpName) const;
730  bool hasAnyModifiersSet(const MachineInstr &MI) const;
731 
732  bool canShrink(const MachineInstr &MI,
733  const MachineRegisterInfo &MRI) const;
734 
736  unsigned NewOpcode) const;
737 
738  bool verifyInstruction(const MachineInstr &MI,
739  StringRef &ErrInfo) const override;
740 
741  unsigned getVALUOp(const MachineInstr &MI) const;
742 
743  /// Return the correct register class for \p OpNo. For target-specific
744  /// instructions, this will return the register class that has been defined
745  /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
746  /// the register class of its machine operand.
747  /// to infer the correct register class base on the other operands.
749  unsigned OpNo) const;
750 
751  /// Return the size in bytes of the operand OpNo on the given
752  // instruction opcode.
753  unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
754  const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
755 
756  if (OpInfo.RegClass == -1) {
757  // If this is an immediate operand, this must be a 32-bit literal.
759  return 4;
760  }
761 
762  return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;
763  }
764 
765  /// This form should usually be preferred since it handles operands
766  /// with unknown register classes.
767  unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
768  const MachineOperand &MO = MI.getOperand(OpNo);
769  if (MO.isReg()) {
770  if (unsigned SubReg = MO.getSubReg()) {
771  assert(RI.getRegSizeInBits(*RI.getSubClassWithSubReg(
772  MI.getParent()->getParent()->getRegInfo().
773  getRegClass(MO.getReg()), SubReg)) >= 32 &&
774  "Sub-dword subregs are not supported");
775  return RI.getSubRegIndexLaneMask(SubReg).getNumLanes() * 4;
776  }
777  }
778  return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
779  }
780 
781  /// Legalize the \p OpIndex operand of this instruction by inserting
782  /// a MOV. For example:
783  /// ADD_I32_e32 VGPR0, 15
784  /// to
785  /// MOV VGPR1, 15
786  /// ADD_I32_e32 VGPR0, VGPR1
787  ///
788  /// If the operand being legalized is a register, then a COPY will be used
789  /// instead of MOV.
790  void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const;
791 
792  /// Check if \p MO is a legal operand if it was the \p OpIdx Operand
793  /// for \p MI.
794  bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
795  const MachineOperand *MO = nullptr) const;
796 
797  /// Check if \p MO would be a valid operand for the given operand
798  /// definition \p OpInfo. Note this does not attempt to validate constant bus
799  /// restrictions (e.g. literal constant usage).
800  bool isLegalVSrcOperand(const MachineRegisterInfo &MRI,
801  const MCOperandInfo &OpInfo,
802  const MachineOperand &MO) const;
803 
804  /// Check if \p MO (a register operand) is a legal register for the
805  /// given operand description.
806  bool isLegalRegOperand(const MachineRegisterInfo &MRI,
807  const MCOperandInfo &OpInfo,
808  const MachineOperand &MO) const;
809 
810  /// Legalize operands in \p MI by either commuting it or inserting a
811  /// copy of src1.
813 
814  /// Fix operands in \p MI to satisfy constant bus requirements.
816 
817  /// Copy a value from a VGPR (\p SrcReg) to SGPR. This function can only
818  /// be used when it is know that the value in SrcReg is same across all
819  /// threads in the wave.
820  /// \returns The SGPR register that \p SrcReg was copied to.
821  unsigned readlaneVGPRToSGPR(unsigned SrcReg, MachineInstr &UseMI,
822  MachineRegisterInfo &MRI) const;
823 
825 
828  const TargetRegisterClass *DstRC,
830  const DebugLoc &DL) const;
831 
832  /// Legalize all operands in this instruction. This function may create new
833  /// instructions and control-flow around \p MI. If present, \p MDT is
834  /// updated.
836  MachineDominatorTree *MDT = nullptr) const;
837 
838  /// Replace this instruction's opcode with the equivalent VALU
839  /// opcode. This function will also move the users of \p MI to the
840  /// VALU if necessary. If present, \p MDT is updated.
841  void moveToVALU(MachineInstr &MI, MachineDominatorTree *MDT = nullptr) const;
842 
844  int Count) const;
845 
846  void insertNoop(MachineBasicBlock &MBB,
847  MachineBasicBlock::iterator MI) const override;
848 
849  void insertReturn(MachineBasicBlock &MBB) const;
850  /// Return the number of wait states that result from executing this
851  /// instruction.
852  static unsigned getNumWaitStates(const MachineInstr &MI);
853 
854  /// Returns the operand named \p Op. If \p MI does not have an
855  /// operand named \c Op, this function returns nullptr.
857  MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
858 
861  unsigned OpName) const {
862  return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
863  }
864 
865  /// Get required immediate operand
866  int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const {
867  int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OpName);
868  return MI.getOperand(Idx).getImm();
869  }
870 
871  uint64_t getDefaultRsrcDataFormat() const;
872  uint64_t getScratchRsrcWords23() const;
873 
874  bool isLowLatencyInstruction(const MachineInstr &MI) const;
875  bool isHighLatencyInstruction(const MachineInstr &MI) const;
876 
877  /// Return the descriptor of the target-specific machine instruction
878  /// that corresponds to the specified pseudo or native opcode.
879  const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const {
880  return get(pseudoToMCOpcode(Opcode));
881  }
882 
883  unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const;
884  unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const;
885 
886  unsigned isLoadFromStackSlot(const MachineInstr &MI,
887  int &FrameIndex) const override;
888  unsigned isStoreToStackSlot(const MachineInstr &MI,
889  int &FrameIndex) const override;
890 
891  unsigned getInstBundleSize(const MachineInstr &MI) const;
892  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
893 
894  bool mayAccessFlatAddressSpace(const MachineInstr &MI) const;
895 
896  bool isNonUniformBranchInstr(MachineInstr &Instr) const;
897 
899  MachineBasicBlock *IfEnd) const;
900 
902  MachineBasicBlock *LoopEnd) const;
903 
904  std::pair<unsigned, unsigned>
905  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
906 
908  getSerializableTargetIndices() const override;
909 
912 
915  const ScheduleDAG *DAG) const override;
916 
918  CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const override;
919 
920  bool isBasicBlockPrologue(const MachineInstr &MI) const override;
921 
922  /// Return a partially built integer add instruction without carry.
923  /// Caller must add source operands.
924  /// For pre-GFX9 it will generate unused carry destination operand.
925  /// TODO: After GFX9 it should return a no-carry operation.
928  const DebugLoc &DL,
929  unsigned DestReg) const;
930 
931  static bool isKillTerminator(unsigned Opcode);
932  const MCInstrDesc &getKillTerminatorFromPseudo(unsigned Opcode) const;
933 
934  static bool isLegalMUBUFImmOffset(unsigned Imm) {
935  return isUInt<12>(Imm);
936  }
937 
938  /// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
939  /// Return -1 if the target-specific opcode for the pseudo instruction does
940  /// not exist. If Opcode is not a pseudo instruction, this is identity.
941  int pseudoToMCOpcode(int Opcode) const;
942 };
943 
944 /// \brief Returns true if a reg:subreg pair P has a TRC class
946  const TargetRegisterClass &TRC,
948  auto *RC = MRI.getRegClass(P.Reg);
949  if (!P.SubReg)
950  return RC == &TRC;
951  auto *TRI = MRI.getTargetRegisterInfo();
952  return RC == TRI->getMatchingSuperRegClass(RC, &TRC, P.SubReg);
953 }
954 
955 /// \brief Create RegSubRegPair from a register MachineOperand
956 inline
958  assert(O.isReg());
960 }
961 
962 /// \brief Return the SubReg component from REG_SEQUENCE
964  unsigned SubReg);
965 
966 /// \brief Return the defining instruction for a given reg:subreg pair
967 /// skipping copy like instructions and subreg-manipulation pseudos.
968 /// Following another subreg of a reg:subreg isn't supported.
971 
972 /// \brief Return true if EXEC mask isnt' changed between the def and
973 /// all uses of VReg. Currently if def and uses are in different BBs -
974 /// simply return false. Should be run on SSA.
975 bool isEXECMaskConstantBetweenDefAndUses(unsigned VReg,
976  MachineRegisterInfo &MRI);
977 
978 namespace AMDGPU {
979 
981  int getVOPe64(uint16_t Opcode);
982 
984  int getVOPe32(uint16_t Opcode);
985 
987  int getSDWAOp(uint16_t Opcode);
988 
990  int getDPPOp32(uint16_t Opcode);
991 
993  int getBasicFromSDWAOp(uint16_t Opcode);
994 
996  int getCommuteRev(uint16_t Opcode);
997 
999  int getCommuteOrig(uint16_t Opcode);
1000 
1002  int getAddr64Inst(uint16_t Opcode);
1003 
1004  /// Check if \p Opcode is an Addr64 opcode.
1005  ///
1006  /// \returns \p Opcode if it is an Addr64 opcode, otherwise -1.
1008  int getIfAddr64Inst(uint16_t Opcode);
1009 
1011  int getMUBUFNoLdsInst(uint16_t Opcode);
1012 
1014  int getAtomicRetOp(uint16_t Opcode);
1015 
1017  int getAtomicNoRetOp(uint16_t Opcode);
1018 
1020  int getSOPKOp(uint16_t Opcode);
1021 
1023  int getGlobalSaddrOp(uint16_t Opcode);
1024 
1026  int getVCMPXNoSDstOp(uint16_t Opcode);
1027 
1028  const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
1029  const uint64_t RSRC_ELEMENT_SIZE_SHIFT = (32 + 19);
1030  const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21);
1031  const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23);
1032 
1033  // For MachineOperands.
1037  };
1038 
1039 } // end namespace AMDGPU
1040 
1041 namespace SI {
1042 namespace KernelInputOffsets {
1043 
1044 /// Offsets in bytes from the start of the input buffer
1045 enum Offsets {
1055 };
1056 
1057 } // end namespace KernelInputOffsets
1058 } // end namespace SI
1059 
1060 } // end namespace llvm
1061 
1062 #endif // LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
bool isFLAT(uint16_t Opcode) const
Definition: SIInstrInfo.h:494
bool isLegalRegOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO (a register operand) is a legal register for the given operand description.
unsigned buildExtractSubReg(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
bool analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const
unsigned getVALUOp(const MachineInstr &MI) const
TargetInstrInfo::RegSubRegPair getRegSequenceSubReg(MachineInstr &MI, unsigned SubReg)
Return the SubReg component from REG_SEQUENCE.
static bool isSGPRSpill(const MachineInstr &MI)
Definition: SIInstrInfo.h:530
Interface definition for SIRegisterInfo.
bool sopkIsZext(uint16_t Opcode) const
Definition: SIInstrInfo.h:578
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
bool isVGPRCopy(const MachineInstr &MI) const
Definition: SIInstrInfo.h:628
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
MachineInstr * getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P, MachineRegisterInfo &MRI)
Return the defining instruction for a given reg:subreg pair skipping copy like instructions and subre...
static bool isScalarStore(const MachineInstr &MI)
Definition: SIInstrInfo.h:584
static bool sopkIsZext(const MachineInstr &MI)
Definition: SIInstrInfo.h:574
uint64_t getDefaultRsrcDataFormat() const
bool isOfRegClass(const TargetInstrInfo::RegSubRegPair &P, const TargetRegisterClass &TRC, MachineRegisterInfo &MRI)
Returns true if a reg:subreg pair P has a TRC class.
Definition: SIInstrInfo.h:945
bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const
Check if MO is a legal operand if it was the OpIdx Operand for MI.
bool isSOPK(uint16_t Opcode) const
Definition: SIInstrInfo.h:370
bool canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const override
bool usesConstantBus(const MachineRegisterInfo &MRI, const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Returns true if this operand uses the constant bus.
bool mayAccessFlatAddressSpace(const MachineInstr &MI) const
unsigned calculateLDSSpillAddress(MachineBasicBlock &MBB, MachineInstr &MI, RegScavenger *RS, unsigned TmpReg, unsigned Offset, unsigned Size) const
bool hasModifiersSet(const MachineInstr &MI, unsigned OpName) const
const TargetRegisterClass * getOpRegClass(const MachineInstr &MI, unsigned OpNo) const
Return the correct register class for OpNo.
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned getReg() const
getReg - Returns the register number.
static bool isVINTRP(const MachineInstr &MI)
Definition: SIInstrInfo.h:554
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:508
unsigned insertNE(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned SrcReg, int Value) const
unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const override
unsigned Reg
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
unsigned getSubReg() const
static bool isSOPK(const MachineInstr &MI)
Definition: SIInstrInfo.h:366
void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const
Legalize operands in MI by either commuting it or inserting a copy of src1.
unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1045
bool isMIMG(uint16_t Opcode) const
Definition: SIInstrInfo.h:470
int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const
Get required immediate operand.
Definition: SIInstrInfo.h:866
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
bool isDPP(uint16_t Opcode) const
Definition: SIInstrInfo.h:542
bool isGather4(uint16_t Opcode) const
Definition: SIInstrInfo.h:478
static bool isSOPP(const MachineInstr &MI)
Definition: SIInstrInfo.h:374
LLVM_READONLY int getAtomicNoRetOp(uint16_t Opcode)
bool isInlineConstant(const APInt &Imm) const
bool isMUBUF(uint16_t Opcode) const
Definition: SIInstrInfo.h:434
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
static bool isSOPC(const MachineInstr &MI)
Definition: SIInstrInfo.h:358
bool hasAnyModifiersSet(const MachineInstr &MI) const
static bool isSMRD(const MachineInstr &MI)
Definition: SIInstrInfo.h:446
void legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
Legalize all operands in this instruction.
const SIRegisterInfo & getRegisterInfo() const
Definition: SIInstrInfo.h:165
LLVM_READONLY int getVOPe64(uint16_t Opcode)
static bool isFixedSize(const MachineInstr &MI)
Definition: SIInstrInfo.h:592
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
static bool isDS(const MachineInstr &MI)
Definition: SIInstrInfo.h:456
bool isEXP(uint16_t Opcode) const
Definition: SIInstrInfo.h:502
bool isSOPP(uint16_t Opcode) const
Definition: SIInstrInfo.h:378
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
LLVM_READONLY int getAtomicRetOp(uint16_t Opcode)
static bool isFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:482
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
uint64_t getScratchRsrcWords23() const
bool isAlwaysGDS(uint16_t Opcode) const
bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const
static bool isGather4(const MachineInstr &MI)
Definition: SIInstrInfo.h:474
static bool isMIMG(const MachineInstr &MI)
Definition: SIInstrInfo.h:466
bool isVINTRP(uint16_t Opcode) const
Definition: SIInstrInfo.h:558
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
unsigned SubReg
MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
static int getRegClass(RegisterKind Is, unsigned RegWidth)
void insertWaitStates(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, int Count) const
LLVM_READONLY int getCommuteOrig(uint16_t Opcode)
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
bool isLiteralConstant(const MachineInstr &MI, int OpIdx) const
Definition: SIInstrInfo.h:700
const MCInstrDesc & getMCOpcodeFromPseudo(unsigned Opcode) const
Return the descriptor of the target-specific machine instruction that corresponds to the specified ps...
Definition: SIInstrInfo.h:879
static bool isVALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:326
void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const
Fix operands in MI to satisfy constant bus requirements.
unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const
Return the size in bytes of the operand OpNo on the given.
Definition: SIInstrInfo.h:753
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:78
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:405
unsigned getInstBundleSize(const MachineInstr &MI) const
static bool isMUBUF(const MachineInstr &MI)
Definition: SIInstrInfo.h:430
LLVM_READONLY MachineOperand * getNamedOperand(MachineInstr &MI, unsigned OperandName) const
Returns the operand named Op.
void convertNonUniformLoopRegion(MachineBasicBlock *LoopEntry, MachineBasicBlock *LoopEnd) const
const uint64_t RSRC_DATA_FORMAT
Definition: SIInstrInfo.h:1028
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx0, unsigned OpIdx1) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
bool isSGPRSpill(uint16_t Opcode) const
Definition: SIInstrInfo.h:534
bool isSDWA(uint16_t Opcode) const
Definition: SIInstrInfo.h:418
Itinerary data supplied by a subtarget to be used by a target.
bool isBasicBlockPrologue(const MachineInstr &MI) const override
bool isInlineConstant(const MachineOperand &MO) const
Definition: SIInstrInfo.h:690
unsigned short NumOperands
Definition: MCInstrDesc.h:166
LLVM_READONLY int getDPPOp32(uint16_t Opcode)
bool isVOP1(uint16_t Opcode) const
Definition: SIInstrInfo.h:394
TargetInstrInfo::RegSubRegPair RegSubRegPair
LLVM_READONLY int getSDWAOp(uint16_t Opcode)
static bool isDPP(const MachineInstr &MI)
Definition: SIInstrInfo.h:538
bool isSOPC(uint16_t Opcode) const
Definition: SIInstrInfo.h:362
#define P(N)
bool isInlineConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Definition: SIInstrInfo.h:647
const TargetRegisterInfo * getTargetRegisterInfo() const
unsigned const MachineRegisterInfo * MRI
const MCInstrDesc & getKillTerminatorFromPseudo(unsigned Opcode) const
bool isEXECMaskConstantBetweenDefAndUses(unsigned VReg, MachineRegisterInfo &MRI)
Return true if EXEC mask isnt&#39; changed between the def and all uses of VReg.
bool isFoldableCopy(const MachineInstr &MI) const
static bool usesVM_CNT(const MachineInstr &MI)
Definition: SIInstrInfo.h:566
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
const TargetRegisterClass * getPreferredSelectRegClass(unsigned Size) const
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
MachineInstrBuilder & UseMI
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const override
LLVM_READONLY int getGlobalSaddrOp(uint16_t Opcode)
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
bool usesFPDPRounding(uint16_t Opcode) const
Definition: SIInstrInfo.h:624
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx, const MachineOperand &MO) const
Definition: SIInstrInfo.h:673
void insertVectorSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const
static bool hasFPClamp(const MachineInstr &MI)
Definition: SIInstrInfo.h:600
bool canShrink(const MachineInstr &MI, const MachineRegisterInfo &MRI) const
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isFixedSize(uint16_t Opcode) const
Definition: SIInstrInfo.h:596
void insertReturn(MachineBasicBlock &MBB) const
LLVM_READONLY int getIfAddr64Inst(uint16_t Opcode)
Check if Opcode is an Addr64 opcode.
bool isDS(uint16_t Opcode) const
Definition: SIInstrInfo.h:460
LLVM_READONLY int commuteOpcode(unsigned Opc) const
bool isVOPC(uint16_t Opcode) const
Definition: SIInstrInfo.h:426
unsigned insertEQ(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned SrcReg, int Value) const
LLVM_READONLY int getSOPKOp(uint16_t Opcode)
bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo, const MachineOperand &MO) const
bool isSOP1(uint16_t Opcode) const
Definition: SIInstrInfo.h:346
bool hasVALU32BitEncoding(unsigned Opcode) const
Return true if this 64-bit VALU instruction has a 32-bit encoding.
static bool isSOP2(const MachineInstr &MI)
Definition: SIInstrInfo.h:350
void materializeImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, int64_t Value) const
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
This is used by the post-RA scheduler (SchedulePostRAList.cpp).
unsigned insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS=nullptr) const override
bool isWQM(uint16_t Opcode) const
Definition: SIInstrInfo.h:510
bool hasFPClamp(uint16_t Opcode) const
Definition: SIInstrInfo.h:604
static bool isVOP2(const MachineInstr &MI)
Definition: SIInstrInfo.h:398
bool isSMRD(uint16_t Opcode) const
Definition: SIInstrInfo.h:450
bool isCopy() const
unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const
static unsigned getNumWaitStates(const MachineInstr &MI)
Return the number of wait states that result from executing this instruction.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool getMemOperandWithOffset(const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, const TargetRegisterInfo *TRI) const final
LLVM_READONLY int getBasicFromSDWAOp(uint16_t Opcode)
bool swapSourceModifiers(MachineInstr &MI, MachineOperand &Src0, unsigned Src0OpName, MachineOperand &Src1, unsigned Src1OpName) const
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
static bool isVOP3P(const MachineInstr &MI)
Definition: SIInstrInfo.h:546
bool isSOP2(uint16_t Opcode) const
Definition: SIInstrInfo.h:354
const uint64_t RSRC_TID_ENABLE
Definition: SIInstrInfo.h:1031
bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const
Returns true if the instruction could potentially depend on the value of exec.
static bool isWQM(const MachineInstr &MI)
Definition: SIInstrInfo.h:506
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const final
bool isPacked(uint16_t Opcode) const
Definition: SIInstrInfo.h:386
static bool isEXP(const MachineInstr &MI)
Definition: SIInstrInfo.h:498
bool isScalarStore(uint16_t Opcode) const
Definition: SIInstrInfo.h:588
static bool usesFPDPRounding(const MachineInstr &MI)
Definition: SIInstrInfo.h:620
int pseudoToMCOpcode(int Opcode) const
Return a target-specific opcode if Opcode is a pseudo instruction.
bool isVOP2(uint16_t Opcode) const
Definition: SIInstrInfo.h:402
A SetVector that performs no allocations if smaller than a certain size.
Definition: SetVector.h:297
Iterator for intrusive lists based on ilist_node.
LLVM_READONLY int getMUBUFNoLdsInst(uint16_t Opcode)
LLVM_READONLY int getVOPe32(uint16_t Opcode)
TargetInstrInfo::RegSubRegPair getRegSubRegPair(const MachineOperand &O)
Create RegSubRegPair from a register MachineOperand.
Definition: SIInstrInfo.h:957
static bool isSALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:318
MachineOperand class - Representation of each machine instruction operand.
Operands with register or 32-bit immediate.
Definition: SIDefines.h:118
bool isLiteralConstantLike(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
A pair composed of a register and a sub-register index.
MachineInstrBuilder MachineInstrBuilder & DefMI
uint64_t getClampMask(const MachineInstr &MI) const
Definition: SIInstrInfo.h:612
MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg) const
Return a partially built integer add instruction without carry.
bool isLegalVSrcOperand(const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
Check if MO would be a valid operand for the given operand definition OpInfo.
const uint64_t RSRC_INDEX_STRIDE_SHIFT
Definition: SIInstrInfo.h:1030
bool isMTBUF(uint16_t Opcode) const
Definition: SIInstrInfo.h:442
bool shouldClusterMemOps(const MachineOperand &BaseOp1, const MachineOperand &BaseOp2, unsigned NumLoads) const override
Represents one node in the SelectionDAG.
LLVM_READONLY int getVCMPXNoSDstOp(uint16_t Opcode)
int64_t getImm() const
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
Class for arbitrary precision integers.
Definition: APInt.h:69
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool isDisableWQM(uint16_t Opcode) const
Definition: SIInstrInfo.h:518
bool hasModifiers(unsigned Opcode) const
Return true if this instruction has any modifiers.
static bool isSegmentSpecificFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:488
static bool isVOP3(const MachineInstr &MI)
Definition: SIInstrInfo.h:406
bool isLiteralConstant(const MachineOperand &MO, const MCOperandInfo &OpInfo) const
Definition: SIInstrInfo.h:695
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:253
Contains the definition of a TargetInstrInfo class that is common to all AMD GPUs.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const
returns true if the operand OpIdx in MI is a valid inline immediate.
Definition: SIInstrInfo.h:668
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
OperandType
Operands are tagged with one of the values of this enum.
Definition: MCInstrDesc.h:43
static bool isMTBUF(const MachineInstr &MI)
Definition: SIInstrInfo.h:438
void moveToVALU(MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
Replace this instruction&#39;s opcode with the equivalent VALU opcode.
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static bool isVOPC(const MachineInstr &MI)
Definition: SIInstrInfo.h:422
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:72
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
#define I(x, y, z)
Definition: MD5.cpp:58
static bool isVMEM(const MachineInstr &MI)
Definition: SIInstrInfo.h:334
MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const override
bool hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const
Whether we must prevent this instruction from executing with EXEC = 0.
bool isHighLatencyInstruction(const MachineInstr &MI) const
LLVM_READONLY int commuteOpcode(const MachineInstr &MI) const
Definition: SIInstrInfo.h:235
bool isLowLatencyInstruction(const MachineInstr &MI) const
uint32_t Size
Definition: Profile.cpp:46
#define LLVM_READONLY
Definition: Compiler.h:183
bool isSALU(uint16_t Opcode) const
Definition: SIInstrInfo.h:322
ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const override
unsigned getMovOpcode(const TargetRegisterClass *DstRC) const
bool isVMEM(uint16_t Opcode) const
Definition: SIInstrInfo.h:338
bool isVOP3P(uint16_t Opcode) const
Definition: SIInstrInfo.h:550
bool isReg() const
isReg - Tests if this is a MO_Register operand.
SIInstrInfo(const GCNSubtarget &ST)
Definition: SIInstrInfo.cpp:86
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
static bool isPacked(const MachineInstr &MI)
Definition: SIInstrInfo.h:382
bool isNonUniformBranchInstr(MachineInstr &Instr) const
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isSOP1(const MachineInstr &MI)
Definition: SIInstrInfo.h:342
void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const
static bool isLegalMUBUFImmOffset(unsigned Imm)
Definition: SIInstrInfo.h:934
const uint64_t RSRC_ELEMENT_SIZE_SHIFT
Definition: SIInstrInfo.h:1029
static bool isScalarUnit(const MachineInstr &MI)
Definition: SIInstrInfo.h:562
unsigned readlaneVGPRToSGPR(unsigned SrcReg, MachineInstr &UseMI, MachineRegisterInfo &MRI) const
Copy a value from a VGPR (SrcReg) to SGPR.
static bool hasIntClamp(const MachineInstr &MI)
Definition: SIInstrInfo.h:608
LLVM Value Representation.
Definition: Value.h:72
static bool isSDWA(const MachineInstr &MI)
Definition: SIInstrInfo.h:414
void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const
Legalize the OpIndex operand of this instruction by inserting a MOV.
MachineInstr * convertToThreeAddress(MachineFunction::iterator &MBB, MachineInstr &MI, LiveVariables *LV) const override
static bool isVGPRSpill(const MachineInstr &MI)
Definition: SIInstrInfo.h:522
unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const
This form should usually be preferred since it handles operands with unknown register classes...
Definition: SIInstrInfo.h:767
unsigned getMachineCSELookAheadLimit() const override
Definition: SIInstrInfo.h:308
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:174
bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0, int64_t Offset1, unsigned NumLoads) const override
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
bool isInlineConstant(const MachineInstr &MI, const MachineOperand &UseMO, const MachineOperand &DefMO) const
returns true if UseMO is substituted with DefMO in MI it would be an inline immediate.
Definition: SIInstrInfo.h:654
void legalizeGenericOperand(MachineBasicBlock &InsertMBB, MachineBasicBlock::iterator I, const TargetRegisterClass *DstRC, MachineOperand &Op, MachineRegisterInfo &MRI, const DebugLoc &DL) const
bool isVOP3(uint16_t Opcode) const
Definition: SIInstrInfo.h:410
static bool isKillTerminator(unsigned Opcode)
LLVM_READONLY int getAddr64Inst(uint16_t Opcode)
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:66
static bool usesLGKM_CNT(const MachineInstr &MI)
Definition: SIInstrInfo.h:570
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
static bool isVOP1(const MachineInstr &MI)
Definition: SIInstrInfo.h:390
MachineInstr * buildShrunkInst(MachineInstr &MI, unsigned NewOpcode) const
void convertNonUniformIfRegion(MachineBasicBlock *IfEntry, MachineBasicBlock *IfEnd) const
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
bool isBufferSMRD(const MachineInstr &MI) const
static bool isDisableWQM(const MachineInstr &MI)
Definition: SIInstrInfo.h:514
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
bool isVALU(uint16_t Opcode) const
Definition: SIInstrInfo.h:330
LLVM_READONLY int getCommuteRev(uint16_t Opcode)
LLVM_READONLY const MachineOperand * getNamedOperand(const MachineInstr &MI, unsigned OpName) const
Definition: SIInstrInfo.h:860
bool isVGPRSpill(uint16_t Opcode) const
Definition: SIInstrInfo.h:526