29#define GET_REGINFO_TARGET_DESC
30#include "AMDGPUGenRegisterInfo.inc"
33 "amdgpu-spill-sgpr-to-vgpr",
34 cl::desc(
"Enable spilling SGPRs to VGPRs"),
38std::array<std::vector<int16_t>, 16> SIRegisterInfo::RegSplitParts;
39std::array<std::array<uint16_t, 32>, 9> SIRegisterInfo::SubRegFromChannelTable;
46 0, 1, 2, 3, 4, 5, 6, 7, 8, 0, 0, 0, 0, 0, 0, 0, 9};
116 MI->getOperand(0).isKill(),
Index,
RS) {}
131 MovOpc = AMDGPU::S_MOV_B32;
132 NotOpc = AMDGPU::S_NOT_B32;
135 MovOpc = AMDGPU::S_MOV_B64;
136 NotOpc = AMDGPU::S_NOT_B64;
141 SuperReg != AMDGPU::EXEC &&
"exec should never spill");
172 assert(
RS &&
"Cannot spill SGPR to memory without RegScavenger");
201 IsWave32 ? AMDGPU::SGPR_32RegClass : AMDGPU::SGPR_64RegClass;
222 MI->emitError(
"unhandled SGPR spill to memory");
232 I->getOperand(2).setIsDead();
267 I->getOperand(2).setIsDead();
297 MI->emitError(
"unhandled SGPR spill to memory");
324 assert(getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() == 3 &&
325 getSubRegIndexLaneMask(AMDGPU::sub31).getAsInteger() == (3ULL << 62) &&
326 (getSubRegIndexLaneMask(AMDGPU::lo16) |
327 getSubRegIndexLaneMask(AMDGPU::hi16)).getAsInteger() ==
328 getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() &&
329 "getNumCoveredRegs() will not work with generated subreg masks!");
331 RegPressureIgnoredUnits.
resize(getNumRegUnits());
333 for (
auto Reg : AMDGPU::VGPR_HI16RegClass)
334 RegPressureIgnoredUnits.
set(*regunits(Reg).begin());
339 static auto InitializeRegSplitPartsOnce = [
this]() {
340 for (
unsigned Idx = 1,
E = getNumSubRegIndices() - 1;
Idx <
E; ++
Idx) {
341 unsigned Size = getSubRegIdxSize(
Idx);
344 std::vector<int16_t> &Vec = RegSplitParts[
Size / 32 - 1];
345 unsigned Pos = getSubRegIdxOffset(
Idx);
350 unsigned MaxNumParts = 1024 /
Size;
351 Vec.resize(MaxNumParts);
359 static auto InitializeSubRegFromChannelTableOnce = [
this]() {
360 for (
auto &Row : SubRegFromChannelTable)
361 Row.fill(AMDGPU::NoSubRegister);
362 for (
unsigned Idx = 1;
Idx < getNumSubRegIndices(); ++
Idx) {
363 unsigned Width = AMDGPUSubRegIdxRanges[
Idx].Size / 32;
364 unsigned Offset = AMDGPUSubRegIdxRanges[
Idx].Offset / 32;
369 unsigned TableIdx = Width - 1;
370 assert(TableIdx < SubRegFromChannelTable.size());
372 SubRegFromChannelTable[TableIdx][
Offset] =
Idx;
376 llvm::call_once(InitializeRegSplitPartsFlag, InitializeRegSplitPartsOnce);
378 InitializeSubRegFromChannelTableOnce);
396 : CSR_AMDGPU_SaveList;
398 return ST.
hasGFX90AInsts() ? CSR_AMDGPU_SI_Gfx_GFX90AInsts_SaveList
399 : CSR_AMDGPU_SI_Gfx_SaveList;
401 return CSR_AMDGPU_CS_ChainPreserve_SaveList;
404 static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister;
405 return &NoCalleeSavedReg;
422 : CSR_AMDGPU_RegMask;
424 return ST.
hasGFX90AInsts() ? CSR_AMDGPU_SI_Gfx_GFX90AInsts_RegMask
425 : CSR_AMDGPU_SI_Gfx_RegMask;
430 return AMDGPU_AllVGPRs_RegMask;
437 return CSR_AMDGPU_NoRegs_RegMask;
441 return VGPR >= AMDGPU::VGPR0 && VGPR < AMDGPU::VGPR8;
452 if (RC == &AMDGPU::VGPR_32RegClass || RC == &AMDGPU::AGPR_32RegClass)
453 return &AMDGPU::AV_32RegClass;
454 if (RC == &AMDGPU::VReg_64RegClass || RC == &AMDGPU::AReg_64RegClass)
455 return &AMDGPU::AV_64RegClass;
456 if (RC == &AMDGPU::VReg_64_Align2RegClass ||
457 RC == &AMDGPU::AReg_64_Align2RegClass)
458 return &AMDGPU::AV_64_Align2RegClass;
459 if (RC == &AMDGPU::VReg_96RegClass || RC == &AMDGPU::AReg_96RegClass)
460 return &AMDGPU::AV_96RegClass;
461 if (RC == &AMDGPU::VReg_96_Align2RegClass ||
462 RC == &AMDGPU::AReg_96_Align2RegClass)
463 return &AMDGPU::AV_96_Align2RegClass;
464 if (RC == &AMDGPU::VReg_128RegClass || RC == &AMDGPU::AReg_128RegClass)
465 return &AMDGPU::AV_128RegClass;
466 if (RC == &AMDGPU::VReg_128_Align2RegClass ||
467 RC == &AMDGPU::AReg_128_Align2RegClass)
468 return &AMDGPU::AV_128_Align2RegClass;
469 if (RC == &AMDGPU::VReg_160RegClass || RC == &AMDGPU::AReg_160RegClass)
470 return &AMDGPU::AV_160RegClass;
471 if (RC == &AMDGPU::VReg_160_Align2RegClass ||
472 RC == &AMDGPU::AReg_160_Align2RegClass)
473 return &AMDGPU::AV_160_Align2RegClass;
474 if (RC == &AMDGPU::VReg_192RegClass || RC == &AMDGPU::AReg_192RegClass)
475 return &AMDGPU::AV_192RegClass;
476 if (RC == &AMDGPU::VReg_192_Align2RegClass ||
477 RC == &AMDGPU::AReg_192_Align2RegClass)
478 return &AMDGPU::AV_192_Align2RegClass;
479 if (RC == &AMDGPU::VReg_256RegClass || RC == &AMDGPU::AReg_256RegClass)
480 return &AMDGPU::AV_256RegClass;
481 if (RC == &AMDGPU::VReg_256_Align2RegClass ||
482 RC == &AMDGPU::AReg_256_Align2RegClass)
483 return &AMDGPU::AV_256_Align2RegClass;
484 if (RC == &AMDGPU::VReg_512RegClass || RC == &AMDGPU::AReg_512RegClass)
485 return &AMDGPU::AV_512RegClass;
486 if (RC == &AMDGPU::VReg_512_Align2RegClass ||
487 RC == &AMDGPU::AReg_512_Align2RegClass)
488 return &AMDGPU::AV_512_Align2RegClass;
489 if (RC == &AMDGPU::VReg_1024RegClass || RC == &AMDGPU::AReg_1024RegClass)
490 return &AMDGPU::AV_1024RegClass;
491 if (RC == &AMDGPU::VReg_1024_Align2RegClass ||
492 RC == &AMDGPU::AReg_1024_Align2RegClass)
493 return &AMDGPU::AV_1024_Align2RegClass;
523 return AMDGPU_AllVGPRs_RegMask;
527 return AMDGPU_AllAGPRs_RegMask;
531 return AMDGPU_AllVectorRegs_RegMask;
535 return AMDGPU_AllAllocatableSRegs_RegMask;
542 assert(NumRegIndex &&
"Not implemented");
543 assert(Channel < SubRegFromChannelTable[NumRegIndex - 1].
size());
544 return SubRegFromChannelTable[NumRegIndex - 1][Channel];
549 const unsigned Align,
552 MCRegister BaseReg(AMDGPU::SGPR_32RegClass.getRegister(BaseIdx));
553 return getMatchingSuperReg(BaseReg, AMDGPU::sub0, RC);
571 reserveRegisterTuples(
Reserved, AMDGPU::EXEC);
572 reserveRegisterTuples(
Reserved, AMDGPU::FLAT_SCR);
575 reserveRegisterTuples(
Reserved, AMDGPU::M0);
578 reserveRegisterTuples(
Reserved, AMDGPU::SRC_VCCZ);
579 reserveRegisterTuples(
Reserved, AMDGPU::SRC_EXECZ);
580 reserveRegisterTuples(
Reserved, AMDGPU::SRC_SCC);
583 reserveRegisterTuples(
Reserved, AMDGPU::SRC_SHARED_BASE);
584 reserveRegisterTuples(
Reserved, AMDGPU::SRC_SHARED_LIMIT);
585 reserveRegisterTuples(
Reserved, AMDGPU::SRC_PRIVATE_BASE);
586 reserveRegisterTuples(
Reserved, AMDGPU::SRC_PRIVATE_LIMIT);
589 reserveRegisterTuples(
Reserved, AMDGPU::SRC_POPS_EXITING_WAVE_ID);
592 reserveRegisterTuples(
Reserved, AMDGPU::XNACK_MASK);
595 reserveRegisterTuples(
Reserved, AMDGPU::LDS_DIRECT);
598 reserveRegisterTuples(
Reserved, AMDGPU::TBA);
599 reserveRegisterTuples(
Reserved, AMDGPU::TMA);
600 reserveRegisterTuples(
Reserved, AMDGPU::TTMP0_TTMP1);
601 reserveRegisterTuples(
Reserved, AMDGPU::TTMP2_TTMP3);
602 reserveRegisterTuples(
Reserved, AMDGPU::TTMP4_TTMP5);
603 reserveRegisterTuples(
Reserved, AMDGPU::TTMP6_TTMP7);
604 reserveRegisterTuples(
Reserved, AMDGPU::TTMP8_TTMP9);
605 reserveRegisterTuples(
Reserved, AMDGPU::TTMP10_TTMP11);
606 reserveRegisterTuples(
Reserved, AMDGPU::TTMP12_TTMP13);
607 reserveRegisterTuples(
Reserved, AMDGPU::TTMP14_TTMP15);
610 reserveRegisterTuples(
Reserved, AMDGPU::SGPR_NULL64);
622 unsigned TotalNumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
623 for (
unsigned i = MaxNumSGPRs; i < TotalNumSGPRs; ++i) {
624 unsigned Reg = AMDGPU::SGPR_32RegClass.getRegister(i);
625 reserveRegisterTuples(
Reserved, Reg);
629 if (ScratchRSrcReg != AMDGPU::NoRegister) {
633 reserveRegisterTuples(
Reserved, ScratchRSrcReg);
637 if (LongBranchReservedReg)
638 reserveRegisterTuples(
Reserved, LongBranchReservedReg);
645 reserveRegisterTuples(
Reserved, StackPtrReg);
646 assert(!isSubRegister(ScratchRSrcReg, StackPtrReg));
651 reserveRegisterTuples(
Reserved, FrameReg);
652 assert(!isSubRegister(ScratchRSrcReg, FrameReg));
657 reserveRegisterTuples(
Reserved, BasePtrReg);
658 assert(!isSubRegister(ScratchRSrcReg, BasePtrReg));
665 reserveRegisterTuples(
Reserved, ExecCopyReg);
670 unsigned MaxNumAGPRs = MaxNumVGPRs;
671 unsigned TotalNumVGPRs = AMDGPU::VGPR_32RegClass.getNumRegs();
684 MaxNumAGPRs = MaxNumVGPRs;
686 if (MaxNumVGPRs > TotalNumVGPRs) {
687 MaxNumAGPRs = MaxNumVGPRs - TotalNumVGPRs;
688 MaxNumVGPRs = TotalNumVGPRs;
694 for (
unsigned i = MaxNumVGPRs; i < TotalNumVGPRs; ++i) {
695 unsigned Reg = AMDGPU::VGPR_32RegClass.getRegister(i);
696 reserveRegisterTuples(
Reserved, Reg);
700 for (
unsigned i = MaxNumAGPRs; i < TotalNumVGPRs; ++i) {
701 unsigned Reg = AMDGPU::AGPR_32RegClass.getRegister(i);
702 reserveRegisterTuples(
Reserved, Reg);
706 for (
MCRegister Reg : AMDGPU::AGPR_32RegClass)
707 reserveRegisterTuples(
Reserved, Reg);
717 reserveRegisterTuples(
Reserved, Reg);
721 reserveRegisterTuples(
Reserved, Reg);
724 reserveRegisterTuples(
Reserved, Reg);
741 if (
Info->isEntryFunction() ||
Info->isChainFunction())
749 if (
Info->isEntryFunction()) {
783 AMDGPU::OpName::offset);
784 return MI->getOperand(OffIdx).getImm();
793 AMDGPU::OpName::vaddr) ||
795 AMDGPU::OpName::saddr))) &&
796 "Should never see frame index on non-address operand");
822 DL = Ins->getDebugLoc();
828 : AMDGPU::V_MOV_B32_e32;
832 : &AMDGPU::VGPR_32RegClass);
840 Register OffsetReg =
MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
844 : &AMDGPU::VGPR_32RegClass);
858 TII->getAddNoCarry(*
MBB, Ins,
DL, BaseReg)
869 bool IsFlat =
TII->isFLATScratch(
MI);
885 TII->getNamedOperand(
MI, IsFlat ? AMDGPU::OpName::saddr
886 : AMDGPU::OpName::vaddr);
891 assert(FIOp && FIOp->
isFI() &&
"frame index must be address operand");
897 "offset should be legal");
899 OffsetOp->
setImm(NewOffset);
909 "offset should be legal");
912 OffsetOp->
setImm(NewOffset);
936 return &AMDGPU::VGPR_32RegClass;
943 if (RC == &AMDGPU::SCC_CLASSRegClass)
952 case AMDGPU::SI_SPILL_S1024_SAVE:
953 case AMDGPU::SI_SPILL_S1024_RESTORE:
954 case AMDGPU::SI_SPILL_V1024_SAVE:
955 case AMDGPU::SI_SPILL_V1024_RESTORE:
956 case AMDGPU::SI_SPILL_A1024_SAVE:
957 case AMDGPU::SI_SPILL_A1024_RESTORE:
958 case AMDGPU::SI_SPILL_AV1024_SAVE:
959 case AMDGPU::SI_SPILL_AV1024_RESTORE:
961 case AMDGPU::SI_SPILL_S512_SAVE:
962 case AMDGPU::SI_SPILL_S512_RESTORE:
963 case AMDGPU::SI_SPILL_V512_SAVE:
964 case AMDGPU::SI_SPILL_V512_RESTORE:
965 case AMDGPU::SI_SPILL_A512_SAVE:
966 case AMDGPU::SI_SPILL_A512_RESTORE:
967 case AMDGPU::SI_SPILL_AV512_SAVE:
968 case AMDGPU::SI_SPILL_AV512_RESTORE:
970 case AMDGPU::SI_SPILL_S384_SAVE:
971 case AMDGPU::SI_SPILL_S384_RESTORE:
972 case AMDGPU::SI_SPILL_V384_SAVE:
973 case AMDGPU::SI_SPILL_V384_RESTORE:
974 case AMDGPU::SI_SPILL_A384_SAVE:
975 case AMDGPU::SI_SPILL_A384_RESTORE:
976 case AMDGPU::SI_SPILL_AV384_SAVE:
977 case AMDGPU::SI_SPILL_AV384_RESTORE:
979 case AMDGPU::SI_SPILL_S352_SAVE:
980 case AMDGPU::SI_SPILL_S352_RESTORE:
981 case AMDGPU::SI_SPILL_V352_SAVE:
982 case AMDGPU::SI_SPILL_V352_RESTORE:
983 case AMDGPU::SI_SPILL_A352_SAVE:
984 case AMDGPU::SI_SPILL_A352_RESTORE:
985 case AMDGPU::SI_SPILL_AV352_SAVE:
986 case AMDGPU::SI_SPILL_AV352_RESTORE:
988 case AMDGPU::SI_SPILL_S320_SAVE:
989 case AMDGPU::SI_SPILL_S320_RESTORE:
990 case AMDGPU::SI_SPILL_V320_SAVE:
991 case AMDGPU::SI_SPILL_V320_RESTORE:
992 case AMDGPU::SI_SPILL_A320_SAVE:
993 case AMDGPU::SI_SPILL_A320_RESTORE:
994 case AMDGPU::SI_SPILL_AV320_SAVE:
995 case AMDGPU::SI_SPILL_AV320_RESTORE:
997 case AMDGPU::SI_SPILL_S288_SAVE:
998 case AMDGPU::SI_SPILL_S288_RESTORE:
999 case AMDGPU::SI_SPILL_V288_SAVE:
1000 case AMDGPU::SI_SPILL_V288_RESTORE:
1001 case AMDGPU::SI_SPILL_A288_SAVE:
1002 case AMDGPU::SI_SPILL_A288_RESTORE:
1003 case AMDGPU::SI_SPILL_AV288_SAVE:
1004 case AMDGPU::SI_SPILL_AV288_RESTORE:
1006 case AMDGPU::SI_SPILL_S256_SAVE:
1007 case AMDGPU::SI_SPILL_S256_RESTORE:
1008 case AMDGPU::SI_SPILL_V256_SAVE:
1009 case AMDGPU::SI_SPILL_V256_RESTORE:
1010 case AMDGPU::SI_SPILL_A256_SAVE:
1011 case AMDGPU::SI_SPILL_A256_RESTORE:
1012 case AMDGPU::SI_SPILL_AV256_SAVE:
1013 case AMDGPU::SI_SPILL_AV256_RESTORE:
1015 case AMDGPU::SI_SPILL_S224_SAVE:
1016 case AMDGPU::SI_SPILL_S224_RESTORE:
1017 case AMDGPU::SI_SPILL_V224_SAVE:
1018 case AMDGPU::SI_SPILL_V224_RESTORE:
1019 case AMDGPU::SI_SPILL_A224_SAVE:
1020 case AMDGPU::SI_SPILL_A224_RESTORE:
1021 case AMDGPU::SI_SPILL_AV224_SAVE:
1022 case AMDGPU::SI_SPILL_AV224_RESTORE:
1024 case AMDGPU::SI_SPILL_S192_SAVE:
1025 case AMDGPU::SI_SPILL_S192_RESTORE:
1026 case AMDGPU::SI_SPILL_V192_SAVE:
1027 case AMDGPU::SI_SPILL_V192_RESTORE:
1028 case AMDGPU::SI_SPILL_A192_SAVE:
1029 case AMDGPU::SI_SPILL_A192_RESTORE:
1030 case AMDGPU::SI_SPILL_AV192_SAVE:
1031 case AMDGPU::SI_SPILL_AV192_RESTORE:
1033 case AMDGPU::SI_SPILL_S160_SAVE:
1034 case AMDGPU::SI_SPILL_S160_RESTORE:
1035 case AMDGPU::SI_SPILL_V160_SAVE:
1036 case AMDGPU::SI_SPILL_V160_RESTORE:
1037 case AMDGPU::SI_SPILL_A160_SAVE:
1038 case AMDGPU::SI_SPILL_A160_RESTORE:
1039 case AMDGPU::SI_SPILL_AV160_SAVE:
1040 case AMDGPU::SI_SPILL_AV160_RESTORE:
1042 case AMDGPU::SI_SPILL_S128_SAVE:
1043 case AMDGPU::SI_SPILL_S128_RESTORE:
1044 case AMDGPU::SI_SPILL_V128_SAVE:
1045 case AMDGPU::SI_SPILL_V128_RESTORE:
1046 case AMDGPU::SI_SPILL_A128_SAVE:
1047 case AMDGPU::SI_SPILL_A128_RESTORE:
1048 case AMDGPU::SI_SPILL_AV128_SAVE:
1049 case AMDGPU::SI_SPILL_AV128_RESTORE:
1051 case AMDGPU::SI_SPILL_S96_SAVE:
1052 case AMDGPU::SI_SPILL_S96_RESTORE:
1053 case AMDGPU::SI_SPILL_V96_SAVE:
1054 case AMDGPU::SI_SPILL_V96_RESTORE:
1055 case AMDGPU::SI_SPILL_A96_SAVE:
1056 case AMDGPU::SI_SPILL_A96_RESTORE:
1057 case AMDGPU::SI_SPILL_AV96_SAVE:
1058 case AMDGPU::SI_SPILL_AV96_RESTORE:
1060 case AMDGPU::SI_SPILL_S64_SAVE:
1061 case AMDGPU::SI_SPILL_S64_RESTORE:
1062 case AMDGPU::SI_SPILL_V64_SAVE:
1063 case AMDGPU::SI_SPILL_V64_RESTORE:
1064 case AMDGPU::SI_SPILL_A64_SAVE:
1065 case AMDGPU::SI_SPILL_A64_RESTORE:
1066 case AMDGPU::SI_SPILL_AV64_SAVE:
1067 case AMDGPU::SI_SPILL_AV64_RESTORE:
1069 case AMDGPU::SI_SPILL_S32_SAVE:
1070 case AMDGPU::SI_SPILL_S32_RESTORE:
1071 case AMDGPU::SI_SPILL_V32_SAVE:
1072 case AMDGPU::SI_SPILL_V32_RESTORE:
1073 case AMDGPU::SI_SPILL_A32_SAVE:
1074 case AMDGPU::SI_SPILL_A32_RESTORE:
1075 case AMDGPU::SI_SPILL_AV32_SAVE:
1076 case AMDGPU::SI_SPILL_AV32_RESTORE:
1077 case AMDGPU::SI_SPILL_WWM_V32_SAVE:
1078 case AMDGPU::SI_SPILL_WWM_V32_RESTORE:
1079 case AMDGPU::SI_SPILL_WWM_AV32_SAVE:
1080 case AMDGPU::SI_SPILL_WWM_AV32_RESTORE:
1088 case AMDGPU::BUFFER_STORE_DWORD_OFFEN:
1089 return AMDGPU::BUFFER_STORE_DWORD_OFFSET;
1090 case AMDGPU::BUFFER_STORE_BYTE_OFFEN:
1091 return AMDGPU::BUFFER_STORE_BYTE_OFFSET;
1092 case AMDGPU::BUFFER_STORE_SHORT_OFFEN:
1093 return AMDGPU::BUFFER_STORE_SHORT_OFFSET;
1094 case AMDGPU::BUFFER_STORE_DWORDX2_OFFEN:
1095 return AMDGPU::BUFFER_STORE_DWORDX2_OFFSET;
1096 case AMDGPU::BUFFER_STORE_DWORDX3_OFFEN:
1097 return AMDGPU::BUFFER_STORE_DWORDX3_OFFSET;
1098 case AMDGPU::BUFFER_STORE_DWORDX4_OFFEN:
1099 return AMDGPU::BUFFER_STORE_DWORDX4_OFFSET;
1100 case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN:
1101 return AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET;
1102 case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN:
1103 return AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET;
1111 case AMDGPU::BUFFER_LOAD_DWORD_OFFEN:
1112 return AMDGPU::BUFFER_LOAD_DWORD_OFFSET;
1113 case AMDGPU::BUFFER_LOAD_UBYTE_OFFEN:
1114 return AMDGPU::BUFFER_LOAD_UBYTE_OFFSET;
1115 case AMDGPU::BUFFER_LOAD_SBYTE_OFFEN:
1116 return AMDGPU::BUFFER_LOAD_SBYTE_OFFSET;
1117 case AMDGPU::BUFFER_LOAD_USHORT_OFFEN:
1118 return AMDGPU::BUFFER_LOAD_USHORT_OFFSET;
1119 case AMDGPU::BUFFER_LOAD_SSHORT_OFFEN:
1120 return AMDGPU::BUFFER_LOAD_SSHORT_OFFSET;
1121 case AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN:
1122 return AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET;
1123 case AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN:
1124 return AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET;
1125 case AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN:
1126 return AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET;
1127 case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN:
1128 return AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET;
1129 case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN:
1130 return AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET;
1131 case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN:
1132 return AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET;
1133 case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN:
1134 return AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET;
1135 case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN:
1136 return AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET;
1137 case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN:
1138 return AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET;
1146 case AMDGPU::BUFFER_STORE_DWORD_OFFSET:
1147 return AMDGPU::BUFFER_STORE_DWORD_OFFEN;
1148 case AMDGPU::BUFFER_STORE_BYTE_OFFSET:
1149 return AMDGPU::BUFFER_STORE_BYTE_OFFEN;
1150 case AMDGPU::BUFFER_STORE_SHORT_OFFSET:
1151 return AMDGPU::BUFFER_STORE_SHORT_OFFEN;
1152 case AMDGPU::BUFFER_STORE_DWORDX2_OFFSET:
1153 return AMDGPU::BUFFER_STORE_DWORDX2_OFFEN;
1154 case AMDGPU::BUFFER_STORE_DWORDX3_OFFSET:
1155 return AMDGPU::BUFFER_STORE_DWORDX3_OFFEN;
1156 case AMDGPU::BUFFER_STORE_DWORDX4_OFFSET:
1157 return AMDGPU::BUFFER_STORE_DWORDX4_OFFEN;
1158 case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET:
1159 return AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN;
1160 case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET:
1161 return AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN;
1169 case AMDGPU::BUFFER_LOAD_DWORD_OFFSET:
1170 return AMDGPU::BUFFER_LOAD_DWORD_OFFEN;
1171 case AMDGPU::BUFFER_LOAD_UBYTE_OFFSET:
1172 return AMDGPU::BUFFER_LOAD_UBYTE_OFFEN;
1173 case AMDGPU::BUFFER_LOAD_SBYTE_OFFSET:
1174 return AMDGPU::BUFFER_LOAD_SBYTE_OFFEN;
1175 case AMDGPU::BUFFER_LOAD_USHORT_OFFSET:
1176 return AMDGPU::BUFFER_LOAD_USHORT_OFFEN;
1177 case AMDGPU::BUFFER_LOAD_SSHORT_OFFSET:
1178 return AMDGPU::BUFFER_LOAD_SSHORT_OFFEN;
1179 case AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET:
1180 return AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN;
1181 case AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET:
1182 return AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN;
1183 case AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET:
1184 return AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN;
1185 case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET:
1186 return AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN;
1187 case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET:
1188 return AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN;
1189 case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET:
1190 return AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN;
1191 case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET:
1192 return AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN;
1193 case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET:
1194 return AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN;
1195 case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET:
1196 return AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN;
1205 int Index,
unsigned Lane,
1206 unsigned ValueReg,
bool IsKill) {
1213 if (Reg == AMDGPU::NoRegister)
1216 bool IsStore =
MI->mayStore();
1220 unsigned Dst = IsStore ? Reg : ValueReg;
1221 unsigned Src = IsStore ? ValueReg : Reg;
1222 bool IsVGPR =
TRI->isVGPR(
MRI, Reg);
1224 if (IsVGPR ==
TRI->isVGPR(
MRI, ValueReg)) {
1234 unsigned Opc = (IsStore ^ IsVGPR) ? AMDGPU::V_ACCVGPR_WRITE_B32_e64
1235 : AMDGPU::V_ACCVGPR_READ_B32_e64;
1253 bool IsStore =
MI->mayStore();
1255 unsigned Opc =
MI->getOpcode();
1256 int LoadStoreOp = IsStore ?
1258 if (LoadStoreOp == -1)
1268 .
add(*
TII->getNamedOperand(*
MI, AMDGPU::OpName::srsrc))
1269 .
add(*
TII->getNamedOperand(*
MI, AMDGPU::OpName::soffset))
1276 AMDGPU::OpName::vdata_in);
1278 NewMI.
add(*VDataIn);
1283 unsigned LoadStoreOp,
1285 bool IsStore =
TII->get(LoadStoreOp).mayStore();
1292 LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORD_SADDR
1293 : AMDGPU::SCRATCH_LOAD_DWORD_SADDR;
1296 LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX2_SADDR
1297 : AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR;
1300 LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX3_SADDR
1301 : AMDGPU::SCRATCH_LOAD_DWORDX3_SADDR;
1304 LoadStoreOp = IsStore ? AMDGPU::SCRATCH_STORE_DWORDX4_SADDR
1305 : AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR;
1321 unsigned LoadStoreOp,
int Index,
Register ValueReg,
bool IsKill,
1324 assert((!RS || !LiveUnits) &&
"Only RS or LiveUnits can be set but not both");
1332 bool IsStore =
Desc->mayStore();
1333 bool IsFlat =
TII->isFLATScratch(LoadStoreOp);
1335 bool CanClobberSCC =
false;
1336 bool Scavenged =
false;
1346 unsigned EltSize = (IsFlat && !IsAGPR) ? std::min(RegWidth, 16u) : 4u;
1347 unsigned NumSubRegs = RegWidth / EltSize;
1348 unsigned Size = NumSubRegs * EltSize;
1349 unsigned RemSize = RegWidth -
Size;
1350 unsigned NumRemSubRegs = RemSize ? 1 : 0;
1352 int64_t MaterializedOffset =
Offset;
1354 int64_t MaxOffset =
Offset +
Size + RemSize - EltSize;
1355 int64_t ScratchOffsetRegDelta = 0;
1357 if (IsFlat && EltSize > 4) {
1359 Desc = &
TII->get(LoadStoreOp);
1366 "unexpected VGPR spill offset");
1373 bool UseVGPROffset =
false;
1380 if (IsFlat && SGPRBase) {
1404 bool IsOffsetLegal =
1419 CanClobberSCC = !RS->
isRegUsed(AMDGPU::SCC);
1420 }
else if (LiveUnits) {
1421 CanClobberSCC = LiveUnits->
available(AMDGPU::SCC);
1422 for (
MCRegister Reg : AMDGPU::SGPR_32RegClass) {
1430 if (ScratchOffsetReg != AMDGPU::NoRegister && !CanClobberSCC)
1434 UseVGPROffset =
true;
1440 for (
MCRegister Reg : AMDGPU::VGPR_32RegClass) {
1442 TmpOffsetVGPR = Reg;
1449 }
else if (!SOffset && CanClobberSCC) {
1460 if (!ScratchOffsetReg)
1462 SOffset = ScratchOffsetReg;
1463 ScratchOffsetRegDelta =
Offset;
1471 if (!IsFlat && !UseVGPROffset)
1474 if (!UseVGPROffset && !SOffset)
1477 if (UseVGPROffset) {
1479 MaterializeVOffset(ScratchOffsetReg, TmpOffsetVGPR,
Offset);
1480 }
else if (ScratchOffsetReg == AMDGPU::NoRegister) {
1485 .
addReg(ScratchOffsetReg)
1487 Add->getOperand(3).setIsDead();
1493 if (IsFlat && SOffset == AMDGPU::NoRegister) {
1495 &&
"Unexpected vaddr for flat scratch with a FI operand");
1497 if (UseVGPROffset) {
1504 Desc = &
TII->get(LoadStoreOp);
1507 for (
unsigned i = 0, e = NumSubRegs + NumRemSubRegs, RegOffset = 0; i != e;
1508 ++i, RegOffset += EltSize) {
1509 if (i == NumSubRegs) {
1513 Desc = &
TII->get(LoadStoreOp);
1515 if (!IsFlat && UseVGPROffset) {
1518 Desc = &
TII->get(NewLoadStoreOp);
1521 if (UseVGPROffset && TmpOffsetVGPR == TmpIntermediateVGPR) {
1528 MaterializeVOffset(ScratchOffsetReg, TmpOffsetVGPR, MaterializedOffset);
1531 unsigned NumRegs = EltSize / 4;
1537 unsigned SOffsetRegState = 0;
1539 const bool IsLastSubReg = i + 1 == e;
1540 const bool IsFirstSubReg = i == 0;
1549 bool NeedSuperRegDef = e > 1 && IsStore && IsFirstSubReg;
1550 bool NeedSuperRegImpOperand = e > 1;
1554 unsigned RemEltSize = EltSize;
1562 for (
int LaneS = (RegOffset + EltSize) / 4 - 1, Lane = LaneS,
1563 LaneE = RegOffset / 4;
1564 Lane >= LaneE; --Lane) {
1565 bool IsSubReg = e > 1 || EltSize > 4;
1570 if (!MIB.getInstr())
1572 if (NeedSuperRegDef || (IsSubReg && IsStore && Lane == LaneS && IsFirstSubReg)) {
1574 NeedSuperRegDef =
false;
1576 if ((IsSubReg || NeedSuperRegImpOperand) && (IsFirstSubReg || IsLastSubReg)) {
1577 NeedSuperRegImpOperand =
true;
1578 unsigned State = SrcDstRegState;
1579 if (!IsLastSubReg || (Lane != LaneE))
1580 State &= ~RegState::Kill;
1581 if (!IsFirstSubReg || (Lane != LaneS))
1582 State &= ~RegState::Define;
1591 if (RemEltSize != EltSize) {
1592 assert(IsFlat && EltSize > 4);
1594 unsigned NumRegs = RemEltSize / 4;
1601 unsigned FinalReg =
SubReg;
1606 if (!TmpIntermediateVGPR) {
1612 TII->get(AMDGPU::V_ACCVGPR_READ_B32_e64),
1613 TmpIntermediateVGPR)
1615 if (NeedSuperRegDef)
1619 SubReg = TmpIntermediateVGPR;
1620 }
else if (UseVGPROffset) {
1622 if (!TmpOffsetVGPR) {
1638 if (UseVGPROffset) {
1647 if (SOffset == AMDGPU::NoRegister) {
1649 if (UseVGPROffset && ScratchOffsetReg) {
1650 MIB.
addReg(ScratchOffsetReg);
1657 MIB.addReg(SOffset, SOffsetRegState);
1659 MIB.addImm(
Offset + RegOffset)
1663 MIB.addMemOperand(NewMMO);
1665 if (!IsAGPR && NeedSuperRegDef)
1668 if (!IsStore && IsAGPR && TmpIntermediateVGPR != AMDGPU::NoRegister) {
1675 if (NeedSuperRegImpOperand && (IsFirstSubReg || IsLastSubReg))
1699 if (!IsStore &&
MI !=
MBB.
end() &&
MI->isReturn() &&
1702 MIB->tieOperands(0, MIB->getNumOperands() - 1);
1706 if (ScratchOffsetRegDelta != 0) {
1710 .
addImm(-ScratchOffsetRegDelta);
1716 bool IsKill)
const {
1734 : AMDGPU::BUFFER_LOAD_DWORD_OFFSET;
1739 : AMDGPU::BUFFER_STORE_DWORD_OFFSET;
1750 bool SpillToPhysVGPRLane)
const {
1756 bool SpillToVGPR = !VGPRSpills.
empty();
1757 if (OnlyToVGPR && !SpillToVGPR)
1766 "Num of VGPR lanes should be equal to num of SGPRs spilled");
1768 for (
unsigned i = 0, e = SB.
NumSubRegs; i < e; ++i) {
1775 bool IsFirstSubreg = i == 0;
1777 bool UseKill = SB.
IsKill && IsLastSubreg;
1783 SB.
TII.get(AMDGPU::SI_SPILL_S32_TO_VGPR), Spill.
VGPR)
1800 if (SB.
NumSubRegs > 1 && (IsFirstSubreg || IsLastSubreg))
1820 for (
unsigned i =
Offset * PVD.PerVGPR,
1830 SB.
TII.get(AMDGPU::SI_SPILL_S32_TO_VGPR), SB.
TmpVGPR)
1847 unsigned SuperKillState = 0;
1861 MI->eraseFromParent();
1873 bool SpillToPhysVGPRLane)
const {
1879 bool SpillToVGPR = !VGPRSpills.
empty();
1880 if (OnlyToVGPR && !SpillToVGPR)
1884 for (
unsigned i = 0, e = SB.
NumSubRegs; i < e; ++i) {
1892 SB.
TII.get(AMDGPU::SI_RESTORE_S32_FROM_VGPR),
SubReg)
1915 for (
unsigned i =
Offset * PVD.PerVGPR,
1923 bool LastSubReg = (i + 1 == e);
1925 SB.
TII.get(AMDGPU::SI_RESTORE_S32_FROM_VGPR),
SubReg)
1942 MI->eraseFromParent();
1962 for (
unsigned i =
Offset * PVD.PerVGPR,
1981 unsigned SuperKillState = 0;
1991 MI = RestoreMBB.
end();
1997 for (
unsigned i =
Offset * PVD.PerVGPR,
2004 bool LastSubReg = (i + 1 == e);
2025 switch (
MI->getOpcode()) {
2026 case AMDGPU::SI_SPILL_S1024_SAVE:
2027 case AMDGPU::SI_SPILL_S512_SAVE:
2028 case AMDGPU::SI_SPILL_S384_SAVE:
2029 case AMDGPU::SI_SPILL_S352_SAVE:
2030 case AMDGPU::SI_SPILL_S320_SAVE:
2031 case AMDGPU::SI_SPILL_S288_SAVE:
2032 case AMDGPU::SI_SPILL_S256_SAVE:
2033 case AMDGPU::SI_SPILL_S224_SAVE:
2034 case AMDGPU::SI_SPILL_S192_SAVE:
2035 case AMDGPU::SI_SPILL_S160_SAVE:
2036 case AMDGPU::SI_SPILL_S128_SAVE:
2037 case AMDGPU::SI_SPILL_S96_SAVE:
2038 case AMDGPU::SI_SPILL_S64_SAVE:
2039 case AMDGPU::SI_SPILL_S32_SAVE:
2040 return spillSGPR(
MI, FI, RS, Indexes, LIS,
true, SpillToPhysVGPRLane);
2041 case AMDGPU::SI_SPILL_S1024_RESTORE:
2042 case AMDGPU::SI_SPILL_S512_RESTORE:
2043 case AMDGPU::SI_SPILL_S384_RESTORE:
2044 case AMDGPU::SI_SPILL_S352_RESTORE:
2045 case AMDGPU::SI_SPILL_S320_RESTORE:
2046 case AMDGPU::SI_SPILL_S288_RESTORE:
2047 case AMDGPU::SI_SPILL_S256_RESTORE:
2048 case AMDGPU::SI_SPILL_S224_RESTORE:
2049 case AMDGPU::SI_SPILL_S192_RESTORE:
2050 case AMDGPU::SI_SPILL_S160_RESTORE:
2051 case AMDGPU::SI_SPILL_S128_RESTORE:
2052 case AMDGPU::SI_SPILL_S96_RESTORE:
2053 case AMDGPU::SI_SPILL_S64_RESTORE:
2054 case AMDGPU::SI_SPILL_S32_RESTORE:
2055 return restoreSGPR(
MI, FI, RS, Indexes, LIS,
true, SpillToPhysVGPRLane);
2062 int SPAdj,
unsigned FIOperandNum,
2071 assert(SPAdj == 0 &&
"unhandled SP adjustment in call sequence?");
2074 int Index =
MI->getOperand(FIOperandNum).getIndex();
2080 switch (
MI->getOpcode()) {
2082 case AMDGPU::SI_SPILL_S1024_SAVE:
2083 case AMDGPU::SI_SPILL_S512_SAVE:
2084 case AMDGPU::SI_SPILL_S384_SAVE:
2085 case AMDGPU::SI_SPILL_S352_SAVE:
2086 case AMDGPU::SI_SPILL_S320_SAVE:
2087 case AMDGPU::SI_SPILL_S288_SAVE:
2088 case AMDGPU::SI_SPILL_S256_SAVE:
2089 case AMDGPU::SI_SPILL_S224_SAVE:
2090 case AMDGPU::SI_SPILL_S192_SAVE:
2091 case AMDGPU::SI_SPILL_S160_SAVE:
2092 case AMDGPU::SI_SPILL_S128_SAVE:
2093 case AMDGPU::SI_SPILL_S96_SAVE:
2094 case AMDGPU::SI_SPILL_S64_SAVE:
2095 case AMDGPU::SI_SPILL_S32_SAVE: {
2100 case AMDGPU::SI_SPILL_S1024_RESTORE:
2101 case AMDGPU::SI_SPILL_S512_RESTORE:
2102 case AMDGPU::SI_SPILL_S384_RESTORE:
2103 case AMDGPU::SI_SPILL_S352_RESTORE:
2104 case AMDGPU::SI_SPILL_S320_RESTORE:
2105 case AMDGPU::SI_SPILL_S288_RESTORE:
2106 case AMDGPU::SI_SPILL_S256_RESTORE:
2107 case AMDGPU::SI_SPILL_S224_RESTORE:
2108 case AMDGPU::SI_SPILL_S192_RESTORE:
2109 case AMDGPU::SI_SPILL_S160_RESTORE:
2110 case AMDGPU::SI_SPILL_S128_RESTORE:
2111 case AMDGPU::SI_SPILL_S96_RESTORE:
2112 case AMDGPU::SI_SPILL_S64_RESTORE:
2113 case AMDGPU::SI_SPILL_S32_RESTORE: {
2118 case AMDGPU::SI_SPILL_V1024_SAVE:
2119 case AMDGPU::SI_SPILL_V512_SAVE:
2120 case AMDGPU::SI_SPILL_V384_SAVE:
2121 case AMDGPU::SI_SPILL_V352_SAVE:
2122 case AMDGPU::SI_SPILL_V320_SAVE:
2123 case AMDGPU::SI_SPILL_V288_SAVE:
2124 case AMDGPU::SI_SPILL_V256_SAVE:
2125 case AMDGPU::SI_SPILL_V224_SAVE:
2126 case AMDGPU::SI_SPILL_V192_SAVE:
2127 case AMDGPU::SI_SPILL_V160_SAVE:
2128 case AMDGPU::SI_SPILL_V128_SAVE:
2129 case AMDGPU::SI_SPILL_V96_SAVE:
2130 case AMDGPU::SI_SPILL_V64_SAVE:
2131 case AMDGPU::SI_SPILL_V32_SAVE:
2132 case AMDGPU::SI_SPILL_A1024_SAVE:
2133 case AMDGPU::SI_SPILL_A512_SAVE:
2134 case AMDGPU::SI_SPILL_A384_SAVE:
2135 case AMDGPU::SI_SPILL_A352_SAVE:
2136 case AMDGPU::SI_SPILL_A320_SAVE:
2137 case AMDGPU::SI_SPILL_A288_SAVE:
2138 case AMDGPU::SI_SPILL_A256_SAVE:
2139 case AMDGPU::SI_SPILL_A224_SAVE:
2140 case AMDGPU::SI_SPILL_A192_SAVE:
2141 case AMDGPU::SI_SPILL_A160_SAVE:
2142 case AMDGPU::SI_SPILL_A128_SAVE:
2143 case AMDGPU::SI_SPILL_A96_SAVE:
2144 case AMDGPU::SI_SPILL_A64_SAVE:
2145 case AMDGPU::SI_SPILL_A32_SAVE:
2146 case AMDGPU::SI_SPILL_AV1024_SAVE:
2147 case AMDGPU::SI_SPILL_AV512_SAVE:
2148 case AMDGPU::SI_SPILL_AV384_SAVE:
2149 case AMDGPU::SI_SPILL_AV352_SAVE:
2150 case AMDGPU::SI_SPILL_AV320_SAVE:
2151 case AMDGPU::SI_SPILL_AV288_SAVE:
2152 case AMDGPU::SI_SPILL_AV256_SAVE:
2153 case AMDGPU::SI_SPILL_AV224_SAVE:
2154 case AMDGPU::SI_SPILL_AV192_SAVE:
2155 case AMDGPU::SI_SPILL_AV160_SAVE:
2156 case AMDGPU::SI_SPILL_AV128_SAVE:
2157 case AMDGPU::SI_SPILL_AV96_SAVE:
2158 case AMDGPU::SI_SPILL_AV64_SAVE:
2159 case AMDGPU::SI_SPILL_AV32_SAVE:
2160 case AMDGPU::SI_SPILL_WWM_V32_SAVE:
2161 case AMDGPU::SI_SPILL_WWM_AV32_SAVE: {
2163 AMDGPU::OpName::vdata);
2164 assert(
TII->getNamedOperand(*
MI, AMDGPU::OpName::soffset)->getReg() ==
2168 : AMDGPU::BUFFER_STORE_DWORD_OFFSET;
2169 auto *
MBB =
MI->getParent();
2170 bool IsWWMRegSpill =
TII->isWWMRegSpillOpcode(
MI->getOpcode());
2171 if (IsWWMRegSpill) {
2177 TII->getNamedOperand(*
MI, AMDGPU::OpName::offset)->getImm(),
2178 *
MI->memoperands_begin(), RS);
2183 MI->eraseFromParent();
2186 case AMDGPU::SI_SPILL_V32_RESTORE:
2187 case AMDGPU::SI_SPILL_V64_RESTORE:
2188 case AMDGPU::SI_SPILL_V96_RESTORE:
2189 case AMDGPU::SI_SPILL_V128_RESTORE:
2190 case AMDGPU::SI_SPILL_V160_RESTORE:
2191 case AMDGPU::SI_SPILL_V192_RESTORE:
2192 case AMDGPU::SI_SPILL_V224_RESTORE:
2193 case AMDGPU::SI_SPILL_V256_RESTORE:
2194 case AMDGPU::SI_SPILL_V288_RESTORE:
2195 case AMDGPU::SI_SPILL_V320_RESTORE:
2196 case AMDGPU::SI_SPILL_V352_RESTORE:
2197 case AMDGPU::SI_SPILL_V384_RESTORE:
2198 case AMDGPU::SI_SPILL_V512_RESTORE:
2199 case AMDGPU::SI_SPILL_V1024_RESTORE:
2200 case AMDGPU::SI_SPILL_A32_RESTORE:
2201 case AMDGPU::SI_SPILL_A64_RESTORE:
2202 case AMDGPU::SI_SPILL_A96_RESTORE:
2203 case AMDGPU::SI_SPILL_A128_RESTORE:
2204 case AMDGPU::SI_SPILL_A160_RESTORE:
2205 case AMDGPU::SI_SPILL_A192_RESTORE:
2206 case AMDGPU::SI_SPILL_A224_RESTORE:
2207 case AMDGPU::SI_SPILL_A256_RESTORE:
2208 case AMDGPU::SI_SPILL_A288_RESTORE:
2209 case AMDGPU::SI_SPILL_A320_RESTORE:
2210 case AMDGPU::SI_SPILL_A352_RESTORE:
2211 case AMDGPU::SI_SPILL_A384_RESTORE:
2212 case AMDGPU::SI_SPILL_A512_RESTORE:
2213 case AMDGPU::SI_SPILL_A1024_RESTORE:
2214 case AMDGPU::SI_SPILL_AV32_RESTORE:
2215 case AMDGPU::SI_SPILL_AV64_RESTORE:
2216 case AMDGPU::SI_SPILL_AV96_RESTORE:
2217 case AMDGPU::SI_SPILL_AV128_RESTORE:
2218 case AMDGPU::SI_SPILL_AV160_RESTORE:
2219 case AMDGPU::SI_SPILL_AV192_RESTORE:
2220 case AMDGPU::SI_SPILL_AV224_RESTORE:
2221 case AMDGPU::SI_SPILL_AV256_RESTORE:
2222 case AMDGPU::SI_SPILL_AV288_RESTORE:
2223 case AMDGPU::SI_SPILL_AV320_RESTORE:
2224 case AMDGPU::SI_SPILL_AV352_RESTORE:
2225 case AMDGPU::SI_SPILL_AV384_RESTORE:
2226 case AMDGPU::SI_SPILL_AV512_RESTORE:
2227 case AMDGPU::SI_SPILL_AV1024_RESTORE:
2228 case AMDGPU::SI_SPILL_WWM_V32_RESTORE:
2229 case AMDGPU::SI_SPILL_WWM_AV32_RESTORE: {
2231 AMDGPU::OpName::vdata);
2232 assert(
TII->getNamedOperand(*
MI, AMDGPU::OpName::soffset)->getReg() ==
2236 : AMDGPU::BUFFER_LOAD_DWORD_OFFSET;
2237 auto *
MBB =
MI->getParent();
2238 bool IsWWMRegSpill =
TII->isWWMRegSpillOpcode(
MI->getOpcode());
2239 if (IsWWMRegSpill) {
2245 TII->getNamedOperand(*
MI, AMDGPU::OpName::offset)->getImm(),
2246 *
MI->memoperands_begin(), RS);
2251 MI->eraseFromParent();
2259 int64_t
Offset = FrameInfo.getObjectOffset(
Index);
2261 if (
TII->isFLATScratch(*
MI)) {
2262 assert((int16_t)FIOperandNum ==
2264 AMDGPU::OpName::saddr));
2274 TII->getNamedOperand(*
MI, AMDGPU::OpName::offset);
2278 OffsetOp->
setImm(NewOffset);
2285 unsigned Opc =
MI->getOpcode();
2299 AMDGPU::OpName::vdst_in);
2300 bool TiedVDst = VDstIn != -1 &&
2301 MI->getOperand(VDstIn).isReg() &&
2302 MI->getOperand(VDstIn).isTied();
2304 MI->untieRegOperand(VDstIn);
2314 assert (NewVDst != -1 && NewVDstIn != -1 &&
"Must be tied!");
2315 MI->tieOperands(NewVDst, NewVDstIn);
2317 MI->setDesc(
TII->get(NewOpc));
2325 if (
TII->isImmOperandLegal(*
MI, FIOperandNum, FIOp))
2332 bool UseSGPR =
TII->isOperandLegal(*
MI, FIOperandNum, &FIOp);
2334 if (!
Offset && FrameReg && UseSGPR) {
2340 : &AMDGPU::VGPR_32RegClass;
2347 if ((!FrameReg || !
Offset) && TmpReg) {
2348 unsigned Opc = UseSGPR ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
2351 MIB.addReg(FrameReg);
2359 RS->
isRegUsed(AMDGPU::SCC) && !
MI->definesRegister(AMDGPU::SCC);
2364 MI,
false, 0, !UseSGPR);
2368 if ((!TmpSReg && !FrameReg) || (!TmpReg && !UseSGPR))
2379 assert(!(
Offset & 0x1) &&
"Flat scratch offset must be aligned!");
2399 if (TmpSReg == FrameReg) {
2401 if (NeedSaveSCC && !
MI->registerDefIsDead(AMDGPU::SCC)) {
2425 bool IsMUBUF =
TII->isMUBUF(*
MI);
2432 RS->
isRegUsed(AMDGPU::SCC) && !
MI->definesRegister(AMDGPU::SCC);
2434 ? &AMDGPU::SReg_32RegClass
2435 : &AMDGPU::VGPR_32RegClass;
2436 bool IsCopy =
MI->getOpcode() == AMDGPU::V_MOV_B32_e32 ||
2437 MI->getOpcode() == AMDGPU::V_MOV_B32_e64;
2439 IsCopy ?
MI->getOperand(0).getReg()
2442 int64_t
Offset = FrameInfo.getObjectOffset(
Index);
2444 unsigned OpCode = IsSALU && !LiveSCC ? AMDGPU::S_LSHR_B32
2445 : AMDGPU::V_LSHRREV_B32_e64;
2447 if (OpCode == AMDGPU::V_LSHRREV_B32_e64)
2453 if (IsSALU && !LiveSCC)
2454 Shift.getInstr()->getOperand(3).setIsDead();
2455 if (IsSALU && LiveSCC) {
2457 AMDGPU::SReg_32RegClass, Shift,
false, 0);
2461 ResultReg = NewDest;
2466 if ((MIB =
TII->getAddNoCarry(*
MBB,
MI,
DL, ResultReg, *RS)) !=
2476 const bool IsVOP2 = MIB->
getOpcode() == AMDGPU::V_ADD_U32_e32;
2487 "Need to reuse carry out register");
2492 ConstOffsetReg = getSubReg(MIB.
getReg(1), AMDGPU::sub0);
2494 ConstOffsetReg = MIB.
getReg(1);
2504 if (!MIB || IsSALU) {
2512 AMDGPU::SReg_32_XM0RegClass,
MI,
false, 0,
false);
2513 Register ScaledReg = TmpScaledReg.
isValid() ? TmpScaledReg : FrameReg;
2525 ResultReg = ScaledReg;
2528 if (!TmpScaledReg.
isValid()) {
2541 MI->eraseFromParent();
2550 assert(
static_cast<int>(FIOperandNum) ==
2552 AMDGPU::OpName::vaddr));
2554 auto &SOffset = *
TII->getNamedOperand(*
MI, AMDGPU::OpName::soffset);
2555 assert((SOffset.isImm() && SOffset.getImm() == 0));
2557 if (FrameReg != AMDGPU::NoRegister)
2558 SOffset.ChangeToRegister(FrameReg,
false);
2560 int64_t
Offset = FrameInfo.getObjectOffset(
Index);
2562 =
TII->getNamedOperand(*
MI, AMDGPU::OpName::offset)->getImm();
2563 int64_t NewOffset = OldImm +
Offset;
2567 MI->eraseFromParent();
2576 if (!
TII->isImmOperandLegal(*
MI, FIOperandNum, FIOp)) {
2599 return &AMDGPU::VReg_64RegClass;
2601 return &AMDGPU::VReg_96RegClass;
2603 return &AMDGPU::VReg_128RegClass;
2605 return &AMDGPU::VReg_160RegClass;
2607 return &AMDGPU::VReg_192RegClass;
2609 return &AMDGPU::VReg_224RegClass;
2611 return &AMDGPU::VReg_256RegClass;
2613 return &AMDGPU::VReg_288RegClass;
2615 return &AMDGPU::VReg_320RegClass;
2617 return &AMDGPU::VReg_352RegClass;
2619 return &AMDGPU::VReg_384RegClass;
2621 return &AMDGPU::VReg_512RegClass;
2623 return &AMDGPU::VReg_1024RegClass;
2631 return &AMDGPU::VReg_64_Align2RegClass;
2633 return &AMDGPU::VReg_96_Align2RegClass;
2635 return &AMDGPU::VReg_128_Align2RegClass;
2637 return &AMDGPU::VReg_160_Align2RegClass;
2639 return &AMDGPU::VReg_192_Align2RegClass;
2641 return &AMDGPU::VReg_224_Align2RegClass;
2643 return &AMDGPU::VReg_256_Align2RegClass;
2645 return &AMDGPU::VReg_288_Align2RegClass;
2647 return &AMDGPU::VReg_320_Align2RegClass;
2649 return &AMDGPU::VReg_352_Align2RegClass;
2651 return &AMDGPU::VReg_384_Align2RegClass;
2653 return &AMDGPU::VReg_512_Align2RegClass;
2655 return &AMDGPU::VReg_1024_Align2RegClass;
2663 return &AMDGPU::VReg_1RegClass;
2665 return &AMDGPU::VGPR_LO16RegClass;
2667 return &AMDGPU::VGPR_32RegClass;
2675 return &AMDGPU::AReg_64RegClass;
2677 return &AMDGPU::AReg_96RegClass;
2679 return &AMDGPU::AReg_128RegClass;
2681 return &AMDGPU::AReg_160RegClass;
2683 return &AMDGPU::AReg_192RegClass;
2685 return &AMDGPU::AReg_224RegClass;
2687 return &AMDGPU::AReg_256RegClass;
2689 return &AMDGPU::AReg_288RegClass;
2691 return &AMDGPU::AReg_320RegClass;
2693 return &AMDGPU::AReg_352RegClass;
2695 return &AMDGPU::AReg_384RegClass;
2697 return &AMDGPU::AReg_512RegClass;
2699 return &AMDGPU::AReg_1024RegClass;
2707 return &AMDGPU::AReg_64_Align2RegClass;
2709 return &AMDGPU::AReg_96_Align2RegClass;
2711 return &AMDGPU::AReg_128_Align2RegClass;
2713 return &AMDGPU::AReg_160_Align2RegClass;
2715 return &AMDGPU::AReg_192_Align2RegClass;
2717 return &AMDGPU::AReg_224_Align2RegClass;
2719 return &AMDGPU::AReg_256_Align2RegClass;
2721 return &AMDGPU::AReg_288_Align2RegClass;
2723 return &AMDGPU::AReg_320_Align2RegClass;
2725 return &AMDGPU::AReg_352_Align2RegClass;
2727 return &AMDGPU::AReg_384_Align2RegClass;
2729 return &AMDGPU::AReg_512_Align2RegClass;
2731 return &AMDGPU::AReg_1024_Align2RegClass;
2739 return &AMDGPU::AGPR_LO16RegClass;
2741 return &AMDGPU::AGPR_32RegClass;
2749 return &AMDGPU::AV_64RegClass;
2751 return &AMDGPU::AV_96RegClass;
2753 return &AMDGPU::AV_128RegClass;
2755 return &AMDGPU::AV_160RegClass;
2757 return &AMDGPU::AV_192RegClass;
2759 return &AMDGPU::AV_224RegClass;
2761 return &AMDGPU::AV_256RegClass;
2763 return &AMDGPU::AV_288RegClass;
2765 return &AMDGPU::AV_320RegClass;
2767 return &AMDGPU::AV_352RegClass;
2769 return &AMDGPU::AV_384RegClass;
2771 return &AMDGPU::AV_512RegClass;
2773 return &AMDGPU::AV_1024RegClass;
2781 return &AMDGPU::AV_64_Align2RegClass;
2783 return &AMDGPU::AV_96_Align2RegClass;
2785 return &AMDGPU::AV_128_Align2RegClass;
2787 return &AMDGPU::AV_160_Align2RegClass;
2789 return &AMDGPU::AV_192_Align2RegClass;
2791 return &AMDGPU::AV_224_Align2RegClass;
2793 return &AMDGPU::AV_256_Align2RegClass;
2795 return &AMDGPU::AV_288_Align2RegClass;
2797 return &AMDGPU::AV_320_Align2RegClass;
2799 return &AMDGPU::AV_352_Align2RegClass;
2801 return &AMDGPU::AV_384_Align2RegClass;
2803 return &AMDGPU::AV_512_Align2RegClass;
2805 return &AMDGPU::AV_1024_Align2RegClass;
2813 return &AMDGPU::VGPR_LO16RegClass;
2815 return &AMDGPU::AV_32RegClass;
2824 return &AMDGPU::SGPR_LO16RegClass;
2826 return &AMDGPU::SReg_32RegClass;
2828 return &AMDGPU::SReg_64RegClass;
2830 return &AMDGPU::SGPR_96RegClass;
2832 return &AMDGPU::SGPR_128RegClass;
2834 return &AMDGPU::SGPR_160RegClass;
2836 return &AMDGPU::SGPR_192RegClass;
2838 return &AMDGPU::SGPR_224RegClass;
2840 return &AMDGPU::SGPR_256RegClass;
2842 return &AMDGPU::SGPR_288RegClass;
2844 return &AMDGPU::SGPR_320RegClass;
2846 return &AMDGPU::SGPR_352RegClass;
2848 return &AMDGPU::SGPR_384RegClass;
2850 return &AMDGPU::SGPR_512RegClass;
2852 return &AMDGPU::SGPR_1024RegClass;
2860 if (Reg.isVirtual())
2861 RC =
MRI.getRegClass(Reg);
2863 RC = getPhysRegBaseClass(Reg);
2869 unsigned Size = getRegSizeInBits(*SRC);
2871 assert(VRC &&
"Invalid register class size");
2877 unsigned Size = getRegSizeInBits(*SRC);
2879 assert(ARC &&
"Invalid register class size");
2885 unsigned Size = getRegSizeInBits(*VRC);
2887 return &AMDGPU::SGPR_32RegClass;
2889 assert(SRC &&
"Invalid register class size");
2896 unsigned SubIdx)
const {
2899 getMatchingSuperRegClass(SuperRC, SubRC, SubIdx);
2900 return MatchRC && MatchRC->
hasSubClassEq(SuperRC) ? MatchRC :
nullptr;
2916 unsigned SrcSubReg)
const {
2933 return getCommonSubClass(DefRC, SrcRC) !=
nullptr;
2949 if (ReserveHighestRegister) {
2951 if (
MRI.isAllocatable(Reg) && !
MRI.isPhysRegUsed(Reg))
2955 if (
MRI.isAllocatable(Reg) && !
MRI.isPhysRegUsed(Reg))
2972 unsigned EltSize)
const {
2974 assert(RegBitWidth >= 32 && RegBitWidth <= 1024);
2976 const unsigned RegDWORDs = RegBitWidth / 32;
2977 const unsigned EltDWORDs = EltSize / 4;
2978 assert(RegSplitParts.size() + 1 >= EltDWORDs);
2980 const std::vector<int16_t> &Parts = RegSplitParts[EltDWORDs - 1];
2981 const unsigned NumParts = RegDWORDs / EltDWORDs;
2983 return ArrayRef(Parts.data(), NumParts);
2989 return Reg.isVirtual() ?
MRI.getRegClass(Reg) : getPhysRegBaseClass(Reg);
2996 return getSubRegisterClass(SrcRC, MO.
getSubReg());
3021 unsigned SrcSize = getRegSizeInBits(*SrcRC);
3022 unsigned DstSize = getRegSizeInBits(*DstRC);
3023 unsigned NewSize = getRegSizeInBits(*NewRC);
3029 if (SrcSize <= 32 || DstSize <= 32)
3032 return NewSize <= DstSize || NewSize <= SrcSize;
3041 switch (RC->
getID()) {
3043 return AMDGPUGenRegisterInfo::getRegPressureLimit(RC, MF);
3044 case AMDGPU::VGPR_32RegClassID:
3045 case AMDGPU::VGPR_LO16RegClassID:
3046 case AMDGPU::VGPR_HI16RegClassID:
3048 case AMDGPU::SGPR_32RegClassID:
3049 case AMDGPU::SGPR_LO16RegClassID:
3055 unsigned Idx)
const {
3056 if (
Idx == AMDGPU::RegisterPressureSets::VGPR_32 ||
3057 Idx == AMDGPU::RegisterPressureSets::AGPR_32)
3061 if (
Idx == AMDGPU::RegisterPressureSets::SReg_32)
3069 static const int Empty[] = { -1 };
3071 if (RegPressureIgnoredUnits[RegUnit])
3074 return AMDGPUGenRegisterInfo::getRegUnitPressureSets(RegUnit);
3079 return AMDGPU::SGPR30_SGPR31;
3085 switch (RB.
getID()) {
3086 case AMDGPU::VGPRRegBankID:
3089 case AMDGPU::VCCRegBankID:
3091 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass
3092 : &AMDGPU::SReg_64_XEXECRegClass;
3093 case AMDGPU::SGPRRegBankID:
3095 case AMDGPU::AGPRRegBankID:
3110 return getAllocatableClass(RC);
3116 return isWave32 ? AMDGPU::VCC_LO : AMDGPU::VCC;
3120 return isWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
3126 : &AMDGPU::VReg_64RegClass;
3131 switch ((
int)RCID) {
3132 case AMDGPU::SReg_1RegClassID:
3134 case AMDGPU::SReg_1_XEXECRegClassID:
3135 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass
3136 : &AMDGPU::SReg_64_XEXECRegClass;
3140 return AMDGPUGenRegisterInfo::getRegClass(RCID);
3153 if (Reg.isVirtual()) {
3158 :
MRI.getMaxLaneMaskForVReg(Reg);
3162 if ((S.LaneMask & SubLanes) == SubLanes) {
3163 V = S.getVNInfoAt(UseIdx);
3175 for (
MCRegUnit Unit : regunits(Reg.asMCReg())) {
3190 if (!Def || !MDT.dominates(Def, &
Use))
3193 assert(Def->modifiesRegister(Reg,
this));
3199 assert(getRegSizeInBits(*getPhysRegBaseClass(Reg)) <= 32);
3202 AMDGPU::SReg_32RegClass,
3203 AMDGPU::AGPR_32RegClass } ) {
3204 if (
MCPhysReg Super = getMatchingSuperReg(Reg, AMDGPU::lo16, &RC))
3207 if (
MCPhysReg Super = getMatchingSuperReg(Reg, AMDGPU::hi16,
3208 &AMDGPU::VGPR_32RegClass)) {
3212 return AMDGPU::NoRegister;
3235 unsigned Size = getRegSizeInBits(*RC);
3269 return std::min(128u, getSubRegIdxSize(
SubReg));
3273 return std::min(32u, getSubRegIdxSize(
SubReg));
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Provides AMDGPU specific target descriptions.
This file declares the targeting of the RegisterBankInfo class for AMDGPU.
static const Function * getParent(const Value *V)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
AMD GCN specific subclass of TargetSubtarget.
const HexagonInstrInfo * TII
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
unsigned const TargetRegisterInfo * TRI
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static int getOffenMUBUFStore(unsigned Opc)
static const TargetRegisterClass * getAnyAGPRClassForBitWidth(unsigned BitWidth)
static int getOffsetMUBUFLoad(unsigned Opc)
static const std::array< unsigned, 17 > SubRegFromChannelTableWidthMap
static const TargetRegisterClass * getAlignedAGPRClassForBitWidth(unsigned BitWidth)
static bool buildMUBUFOffsetLoadStore(const GCNSubtarget &ST, MachineFrameInfo &MFI, MachineBasicBlock::iterator MI, int Index, int64_t Offset)
static unsigned getFlatScratchSpillOpcode(const SIInstrInfo *TII, unsigned LoadStoreOp, unsigned EltSize)
static const TargetRegisterClass * getAlignedVGPRClassForBitWidth(unsigned BitWidth)
static int getOffsetMUBUFStore(unsigned Opc)
static const TargetRegisterClass * getAnyVGPRClassForBitWidth(unsigned BitWidth)
static cl::opt< bool > EnableSpillSGPRToVGPR("amdgpu-spill-sgpr-to-vgpr", cl::desc("Enable spilling SGPRs to VGPRs"), cl::ReallyHidden, cl::init(true))
static unsigned getNumSubRegsForSpillOp(unsigned Op)
static const TargetRegisterClass * getAlignedVectorSuperClassForBitWidth(unsigned BitWidth)
static const TargetRegisterClass * getAnyVectorSuperClassForBitWidth(unsigned BitWidth)
static MachineInstrBuilder spillVGPRtoAGPR(const GCNSubtarget &ST, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, int Index, unsigned Lane, unsigned ValueReg, bool IsKill)
static int getOffenMUBUFLoad(unsigned Opc)
Interface definition for SIRegisterInfo.
static const char * getRegisterName(MCRegister Reg)
uint32_t getLDSSize() const
bool isChainFunction() const
bool isEntryFunction() const
unsigned getOccupancyWithLocalMemSize(uint32_t Bytes, const Function &) const
Inverse of getMaxLocalMemWithWaveCount.
bool useRealTrue16Insts() const
Return true if real (non-fake) variants of True16 instructions using 16-bit registers should be code-...
unsigned getWavefrontSizeLog2() const
unsigned getWavefrontSize() const
bool hasInv2PiInlineImm() const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
This class represents an Operation in the Expression.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
bool hasGFX90AInsts() const
bool hasMFMAInlineLiteralBug() const
const SIInstrInfo * getInstrInfo() const override
unsigned getConstantBusLimit(unsigned Opcode) const
bool needsAlignedVGPRs() const
Return if operations acting on VGPR tuples require even alignment.
bool enableFlatScratch() const
unsigned getMaxNumVGPRs(unsigned WavesPerEU) const
const SIFrameLowering * getFrameLowering() const override
unsigned getMaxNumSGPRs(unsigned WavesPerEU, bool Addressable) const
bool hasFlatScratchSTMode() const
LiveInterval - This class represents the liveness of a register, or stack slot.
bool hasSubRanges() const
Returns true if subregister liveness information is available.
iterator_range< subrange_iterator > subranges()
void removeAllRegUnitsForPhysReg(MCRegister Reg)
Remove associated live ranges for the register units associated with Reg.
bool hasInterval(Register Reg) const
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
LiveRange & getRegUnit(unsigned Unit)
Return the live range for register unit Unit.
LiveInterval & getInterval(Register Reg)
This class represents the liveness of a register, stack slot, etc.
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
A set of register units used to track register liveness.
bool available(MCPhysReg Reg) const
Returns true if no part of physical register Reg is live.
Describe properties that are true of each instruction in the target description file.
MCRegAliasIterator enumerates all registers aliasing Reg.
Wrapper class representing physical registers. Should be passed by value.
static MCRegister from(unsigned Val)
Check the provided unsigned value is a valid MCRegister.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasCalls() const
Return true if the current function has any function calls.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
bool hasStackObjects() const
Return true if there are any stack objects in this function.
uint8_t getStackID(int ObjectIdx) const
unsigned getNumFixedObjects() const
Return the number of fixed objects.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Register getReg(unsigned Idx) const
Get the register for the operand index.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void setAsmPrinterFlag(uint8_t Flag)
Set a flag for the AsmPrinter.
const MachineOperand & getOperand(unsigned i) const
A description of a memory reference used in the backend.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
const MachinePointerInfo & getPointerInfo() const
Flags getFlags() const
Return the raw flags of the source value,.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
void setImm(int64_t immVal)
void setIsDead(bool Val=true)
void setReg(Register Reg)
Change the register this operand corresponds to.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
void setIsKill(bool Val=true)
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value.
Register getReg() const
getReg - Returns the register number.
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
AnalysisType & getAnalysis() const
getAnalysis<AnalysisType>() - This function is used by subclasses to get to the analysis information ...
A discriminated union of two or more pointer types, with the discriminator in the low bit of the poin...
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwise returns null.
bool isRegUsed(Register Reg, bool includeReserved=true) const
Return if a specific register is currently used.
void setRegUsed(Register Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Tell the scavenger a register is used.
void assignRegToScavengingIndex(int FI, Register Reg, MachineInstr *Restore=nullptr)
Record that Reg is in use at scavenging index FI.
Register scavengeRegisterBackwards(const TargetRegisterClass &RC, MachineBasicBlock::iterator To, bool RestoreAfter, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available from the current position backwards to the p...
Holds all the information related to register banks.
virtual bool isDivergentRegBank(const RegisterBank *RB) const
Returns true if the register bank is considered divergent.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
This class implements the register bank concept.
unsigned getID() const
Get the identifier of this register bank.
Wrapper class representing virtual and physical registers.
constexpr bool isValid() const
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
static bool isFLATScratch(const MachineInstr &MI)
static bool isLegalMUBUFImmOffset(unsigned Imm)
static bool isMUBUF(const MachineInstr &MI)
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
bool usesAGPRs(const MachineFunction &MF) const
ArrayRef< MCPhysReg > getAGPRSpillVGPRs() const
MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const
Register getLongBranchReservedReg() const
Register getStackPtrOffsetReg() const
Register getScratchRSrcReg() const
Returns the physical register reserved for use as the resource descriptor for scratch accesses.
ArrayRef< MCPhysReg > getVGPRSpillAGPRs() const
int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI)
ArrayRef< SIRegisterInfo::SpilledReg > getSGPRSpillToVirtualVGPRLanes(int FrameIndex) const
Register getSGPRForEXECCopy() const
ArrayRef< SIRegisterInfo::SpilledReg > getSGPRSpillToPhysicalVGPRLanes(int FrameIndex) const
Register getVGPRForAGPRCopy() const
Register getFrameOffsetReg() const
void addToSpilledVGPRs(unsigned num)
const ReservedRegSet & getWWMReservedRegs() const
void addToSpilledSGPRs(unsigned num)
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
int64_t getScratchInstrOffset(const MachineInstr *MI) const
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
const TargetRegisterClass * getRegClass(unsigned RCID) const
const TargetRegisterClass * getCompatibleSubRegClass(const TargetRegisterClass *SuperRC, const TargetRegisterClass *SubRC, unsigned SubIdx) const
Returns a register class which is compatible with SuperRC, such that a subregister exists with class ...
ArrayRef< MCPhysReg > getAllSGPR64(const MachineFunction &MF) const
Return all SGPR64 which satisfy the waves per execution unit requirement of the subtarget.
MCRegister findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF, bool ReserveHighestVGPR=false) const
Returns a lowest register that is not used at any point in the function.
static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs=1)
MCPhysReg get32BitRegister(MCPhysReg Reg) const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const override
const TargetRegisterClass * getProperlyAlignedRC(const TargetRegisterClass *RC) const
bool shouldRealignStack(const MachineFunction &MF) const override
bool restoreSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr, bool OnlyToVGPR=false, bool SpillToPhysVGPRLane=false) const
bool isProperlyAlignedRC(const TargetRegisterClass &RC) const
const TargetRegisterClass * getEquivalentVGPRClass(const TargetRegisterClass *SRC) const
Register getFrameRegister(const MachineFunction &MF) const override
LLVM_READONLY const TargetRegisterClass * getVectorSuperClassForBitWidth(unsigned BitWidth) const
bool spillEmergencySGPR(MachineBasicBlock::iterator MI, MachineBasicBlock &RestoreMBB, Register SGPR, RegScavenger *RS) const
SIRegisterInfo(const GCNSubtarget &ST)
const uint32_t * getAllVGPRRegMask() const
MCRegister getReturnAddressReg(const MachineFunction &MF) const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
bool hasBasePointer(const MachineFunction &MF) const
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
Returns a legal register class to copy a register in the specified class to or from.
ArrayRef< int16_t > getRegSplitParts(const TargetRegisterClass *RC, unsigned EltSize) const
ArrayRef< MCPhysReg > getAllSGPR32(const MachineFunction &MF) const
Return all SGPR32 which satisfy the waves per execution unit requirement of the subtarget.
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
MCRegister reservedPrivateSegmentBufferReg(const MachineFunction &MF) const
Return the end register initially reserved for the scratch buffer in case spilling is needed.
bool eliminateSGPRToVGPRSpillFrameIndex(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr, bool SpillToPhysVGPRLane=false) const
Special case of eliminateFrameIndex.
bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const
void buildSpillLoadStore(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned LoadStoreOp, int Index, Register ValueReg, bool ValueIsKill, MCRegister ScratchOffsetReg, int64_t InstrOffset, MachineMemOperand *MMO, RegScavenger *RS, LiveRegUnits *LiveUnits=nullptr) const
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
LLVM_READONLY const TargetRegisterClass * getAGPRClassForBitWidth(unsigned BitWidth) const
static bool isChainScratchRegister(Register VGPR)
bool requiresRegisterScavenging(const MachineFunction &Fn) const override
bool opCanUseInlineConstant(unsigned OpType) const
const TargetRegisterClass * getRegClassForSizeOnBank(unsigned Size, const RegisterBank &Bank) const
const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const override
bool isUniformReg(const MachineRegisterInfo &MRI, const RegisterBankInfo &RBI, Register Reg) const override
const uint32_t * getNoPreservedMask() const override
StringRef getRegAsmName(MCRegister Reg) const override
const uint32_t * getAllAllocatableSRegMask() const
MCRegister getAlignedHighSGPRForRC(const MachineFunction &MF, const unsigned Align, const TargetRegisterClass *RC) const
Return the largest available SGPR aligned to Align for the register class RC.
const TargetRegisterClass * getRegClassForReg(const MachineRegisterInfo &MRI, Register Reg) const
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
const uint32_t * getAllVectorRegMask() const
const TargetRegisterClass * getEquivalentAGPRClass(const TargetRegisterClass *SRC) const
static LLVM_READONLY const TargetRegisterClass * getSGPRClassForBitWidth(unsigned BitWidth)
const TargetRegisterClass * getRegClassForTypeOnBank(LLT Ty, const RegisterBank &Bank) const
bool opCanUseLiteralConstant(unsigned OpType) const
Register getBaseRegister() const
LLVM_READONLY const TargetRegisterClass * getVGPRClassForBitWidth(unsigned BitWidth) const
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
static bool isVGPRClass(const TargetRegisterClass *RC)
MachineInstr * findReachingDef(Register Reg, unsigned SubReg, MachineInstr &Use, MachineRegisterInfo &MRI, LiveIntervals *LIS) const
bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const
const TargetRegisterClass * getEquivalentSGPRClass(const TargetRegisterClass *VRC) const
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
ArrayRef< MCPhysReg > getAllSGPR128(const MachineFunction &MF) const
Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget.
unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
const TargetRegisterClass * getRegClassForOperandReg(const MachineRegisterInfo &MRI, const MachineOperand &MO) const
const uint32_t * getAllAGPRRegMask() const
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
const TargetRegisterClass * getBoolRC() const
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
bool spillSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr, bool OnlyToVGPR=false, bool SpillToPhysVGPRLane=false) const
If OnlyToVGPR is true, this will only succeed if this manages to find a free VGPR lane to spill.
MCRegister getExec() const
MCRegister getVCC() const
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
bool isVectorSuperClass(const TargetRegisterClass *RC) const
const TargetRegisterClass * getWaveMaskRegClass() const
unsigned getSubRegAlignmentNumBits(const TargetRegisterClass *RC, unsigned SubReg) const
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override
const TargetRegisterClass * getVGPR64Class() const
void buildVGPRSpillLoadStore(SGPRSpillBuilder &SB, int Index, int Offset, bool IsLoad, bool IsKill=true) const
static bool isSGPRClass(const TargetRegisterClass *RC)
static bool isAGPRClass(const TargetRegisterClass *RC)
const int * getRegUnitPressureSets(unsigned RegUnit) const override
SlotIndex - An opaque wrapper around machine indexes.
bool isValid() const
Returns true if this is a valid index.
SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late=false)
Insert the given machine instruction into the mapping.
SlotIndex replaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)
ReplaceMachineInstrInMaps - Replacing a machine instr with a new one in maps used by register allocat...
StringRef - Represent a constant reference to a string, i.e.
const uint8_t TSFlags
Configurable target specific flags.
unsigned getID() const
Return the register class ID number.
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
virtual bool shouldRealignStack(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
A Use represents the edge between a Value definition and its users.
VNInfo - Value Number Information.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ PRIVATE_ADDRESS
Address space for private memory.
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
LLVM_READONLY int getFlatScratchInstSVfromSS(uint16_t Opcode)
LLVM_READONLY int getFlatScratchInstSTfromSS(uint16_t Opcode)
LLVM_READONLY int getFlatScratchInstSVfromSVS(uint16_t Opcode)
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
LLVM_READONLY bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx)
@ OPERAND_REG_INLINE_AC_FIRST
@ OPERAND_REG_INLINE_AC_LAST
unsigned getRegBitWidth(const TargetRegisterClass &RC)
Get the size in bits of a register from the register class RC.
@ AMDGPU_Gfx
Used for AMD graphics targets.
@ AMDGPU_CS_ChainPreserve
Used on AMDGPUs to give the middle-end more control over argument placement.
@ AMDGPU_CS_Chain
Used on AMDGPUs to give the middle-end more control over argument placement.
@ Cold
Attempts to make code in the caller as efficient as possible under the assumption that the call is no...
@ Fast
Attempts to make calls as fast as possible (e.g.
@ C
The default llvm calling convention, compatible with C.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Kill
The last use of a register.
@ Undef
Value of the register doesn't matter.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
auto reverse(ContainerTy &&C)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
unsigned getDefRegState(bool B)
unsigned getKillRegState(bool B)
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
constexpr unsigned BitWidth
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the largest uint64_t less than or equal to Value and is Skew mod Align.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Description of the encoding of one expression Op.
This class contains a discriminated union of information about pointers in memory operands,...
MachinePointerInfo getWithOffset(int64_t O) const
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
void setMI(MachineBasicBlock *NewMBB, MachineBasicBlock::iterator NewMI)
ArrayRef< int16_t > SplitParts
SIMachineFunctionInfo & MFI
SGPRSpillBuilder(const SIRegisterInfo &TRI, const SIInstrInfo &TII, bool IsWave32, MachineBasicBlock::iterator MI, int Index, RegScavenger *RS)
SGPRSpillBuilder(const SIRegisterInfo &TRI, const SIInstrInfo &TII, bool IsWave32, MachineBasicBlock::iterator MI, Register Reg, bool IsKill, int Index, RegScavenger *RS)
PerVGPRData getPerVGPRData()
MachineBasicBlock::iterator MI
void readWriteTmpVGPR(unsigned Offset, bool IsLoad)
const SIRegisterInfo & TRI
The llvm::once_flag structure.