Holds all the information related to register banks. More...

#include "llvm/CodeGen/RegisterBankInfo.h"

Inheritance diagram for llvm::RegisterBankInfo:

[legend]

Classes
class	InstructionMapping
	Helper class that represents how the value of an instruction may be mapped and what is the related cost of such mapping. More...

class	OperandsMapper
	Helper class used to get/create the virtual registers that will be used to replace the MachineOperand when applying a mapping. More...

struct	PartialMapping
	Helper struct that represents how a value is partially mapped into a register. More...

struct	ValueMapping
	Helper struct that represents how a value is mapped through different register banks. More...

Public Types
using	InstructionMappings = SmallVector< const InstructionMapping *, 4 >
	Convenient type to represent the alternatives for mapping an instruction.

Public Member Functions
const RegisterBank *	getRegBankFromConstraints (const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const MachineRegisterInfo &MRI) const
	Get the register bank for the `OpIdx-th` operand of `MI` form the encoding constraints, if any.

virtual void	applyMappingImpl (MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const
	See applyMapping.

virtual	~RegisterBankInfo ()=default

const RegisterBank &	getRegBank (unsigned ID) const
	Get the register bank identified by `ID`.

unsigned	getMaximumSize (unsigned RegBankID) const
	Get the maximum size in bits that fits in the given register bank.

const RegisterBank *	getRegBank (Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
	Get the register bank of `Reg`.

unsigned	getNumRegBanks () const
	Get the total number of register banks.

virtual bool	isDivergentRegBank (const RegisterBank *RB) const
	Returns true if the register bank is considered divergent.

virtual const RegisterBank &	getRegBankFromRegClass (const TargetRegisterClass &RC, LLT Ty) const
	Get a register bank that covers `RC`.

virtual unsigned	copyCost (const RegisterBank &A, const RegisterBank &B, TypeSize Size) const
	Get the cost of a copy from `B` to `A`, or put differently, get the cost of A = COPY B.

bool	cannotCopy (const RegisterBank &Dst, const RegisterBank &Src, TypeSize Size) const

virtual unsigned	getBreakDownCost (const ValueMapping &ValMapping, const RegisterBank *CurBank=nullptr) const
	Get the cost of using `ValMapping` to decompose a register.

virtual const InstructionMapping &	getInstrMapping (const MachineInstr &MI) const
	Get the mapping of the different operands of `MI` on the register bank.

virtual InstructionMappings	getInstrAlternativeMappings (const MachineInstr &MI) const
	Get the alternative mappings for `MI`.

InstructionMappings	getInstrPossibleMappings (const MachineInstr &MI) const
	Get the possible mapping for `MI`.

void	applyMapping (MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const
	Apply `OpdMapper.getInstrMapping()` to `OpdMapper.getMI()`.

TypeSize	getSizeInBits (Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
	Get the size in bits of `Reg`.

bool	verify (const TargetRegisterInfo &TRI) const
	Check that information hold by this instance make sense for the given `TRI`.

Static Public Member Functions
static void	applyDefaultMapping (const OperandsMapper &OpdMapper)
	Helper method to apply something that is like the default mapping.

static const TargetRegisterClass *	constrainGenericRegister (Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
	Constrain the (possibly generic) virtual register `Reg` to `RC`.

Static Public Attributes
static const unsigned	DefaultMappingID = UINT_MAX
	Identifier used when the related instruction mapping instance is generated by target independent code.

static const unsigned	InvalidMappingID = UINT_MAX - 1
	Identifier used when the related instruction mapping instance is generated by the default constructor.

Protected Member Functions
	RegisterBankInfo (const RegisterBank *RegBanks, unsigned NumRegBanks, const unsigned Sizes, unsigned HwMode)
	Create a RegisterBankInfo that can accommodate up to `NumRegBanks` RegisterBank instances.

	RegisterBankInfo ()
	This constructor is meaningless.

const RegisterBank &	getRegBank (unsigned ID)
	Get the register bank identified by `ID`.

const TargetRegisterClass *	getMinimalPhysRegClass (Register Reg, const TargetRegisterInfo &TRI) const
	Get the MinimalPhysRegClass for Reg.

const InstructionMapping &	getInstrMappingImpl (const MachineInstr &MI) const
	Try to get the mapping of `MI`.

const PartialMapping &	getPartialMapping (unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
	Get the uniquely generated PartialMapping for the given arguments.

Methods to get a uniquely generated ValueMapping.
const ValueMapping &	getValueMapping (unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
	The most common ValueMapping consists of a single PartialMapping.

const ValueMapping &	getValueMapping (const PartialMapping *BreakDown, unsigned NumBreakDowns) const
	Get the ValueMapping for the given arguments.

Methods to get a uniquely generated array of ValueMapping.
template<typename Iterator >
const ValueMapping *	getOperandsMapping (Iterator Begin, Iterator End) const
	Get the uniquely generated array of ValueMapping for the elements of between `Begin` and `End`.

const ValueMapping *	getOperandsMapping (const SmallVectorImpl< const ValueMapping * > &OpdsMapping) const
	Get the uniquely generated array of ValueMapping for the elements of `OpdsMapping`.

const ValueMapping *	getOperandsMapping (std::initializer_list< const ValueMapping * > OpdsMapping) const
	Get the uniquely generated array of ValueMapping for the given arguments.

Protected Attributes
const RegisterBank **	RegBanks
	Hold the set of supported register banks.

unsigned	NumRegBanks
	Total number of register banks.

const unsigned *	Sizes
	Hold the sizes of the register banks for all HwModes.

unsigned	HwMode
	Current HwMode for the target.

DenseMap< hash_code, std::unique_ptr< const PartialMapping > >	MapOfPartialMappings
	Keep dynamically allocated PartialMapping in a separate map.

DenseMap< hash_code, std::unique_ptr< const ValueMapping > >	MapOfValueMappings
	Keep dynamically allocated ValueMapping in a separate map.

DenseMap< hash_code, std::unique_ptr< ValueMapping[]> >	MapOfOperandsMappings
	Keep dynamically allocated array of ValueMapping in a separate map.

DenseMap< hash_code, std::unique_ptr< const InstructionMapping > >	MapOfInstructionMappings
	Keep dynamically allocated InstructionMapping in a separate map.

DenseMap< unsigned, const TargetRegisterClass * >	PhysRegMinimalRCs
	Getting the minimal register class of a physreg is expensive.

Methods to get a uniquely generated InstructionMapping.
const InstructionMapping &	getInstructionMapping (unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
	Method to get a uniquely generated InstructionMapping.

const InstructionMapping &	getInvalidInstructionMapping () const
	Method to get a uniquely generated invalid InstructionMapping.

Detailed Description

Holds all the information related to register banks.

Definition at line 40 of file RegisterBankInfo.h.

Member Typedef Documentation

◆ InstructionMappings

using llvm::RegisterBankInfo::InstructionMappings = SmallVector<const InstructionMapping *, 4>

Convenient type to represent the alternatives for mapping an instruction.

Todo:: When we move to TableGen this should be an array ref.

Definition at line 277 of file RegisterBankInfo.h.

Constructor & Destructor Documentation

◆ RegisterBankInfo() [1/2]

RegisterBankInfo::RegisterBankInfo	(	const RegisterBank **	RegBanks,
		unsigned	NumRegBanks,
		const unsigned *	Sizes,
		unsigned	HwMode
	)

protected

Create a RegisterBankInfo that can accommodate up to NumRegBanks RegisterBank instances.

Definition at line 56 of file RegisterBankInfo.cpp.

References assert(), End, getNumRegBanks(), Idx, and RegBanks.

◆ RegisterBankInfo() [2/2]

llvm::RegisterBankInfo::RegisterBankInfo ( )

inlineprotected

This constructor is meaningless.

It just provides a default constructor that can be used at link time when GlobalISel is not built. That way, targets can still inherit from this class without doing crazy gymnastic to avoid link time failures.

Note: That works because the constructor is inlined.

Definition at line 435 of file RegisterBankInfo.h.

References llvm_unreachable.

◆ ~RegisterBankInfo()

virtual llvm::RegisterBankInfo::~RegisterBankInfo ( )

virtualdefault

Member Function Documentation

◆ applyDefaultMapping()

void RegisterBankInfo::applyDefaultMapping ( const OperandsMapper & OpdMapper )

static

Helper method to apply something that is like the default mapping.

Basically, that means that OpdMapper.getMI() is left untouched aside from the reassignment of the register operand that have been remapped.

The type of all the new registers that have been created by the mapper are properly remapped to the type of the original registers they replace. In other words, the semantic of the instruction does not change, only the register banks.

If the mapping of one of the operand spans several registers, this method will abort as this is not like a default mapping anymore.

Precondition: For OpIdx in {0..OpdMapper.getMI().getNumOperands()) the range OpdMapper.getVRegs(OpIdx) is empty or of size 1.

Definition at line 439 of file RegisterBankInfo.cpp.

References assert(), llvm::iterator_range< IteratorT >::begin(), llvm::dbgs(), llvm::iterator_range< IteratorT >::empty(), llvm::RegisterBankInfo::OperandsMapper::getInstrMapping(), llvm::RegisterBankInfo::OperandsMapper::getMI(), llvm::RegisterBankInfo::OperandsMapper::getMRI(), llvm::RegisterBankInfo::InstructionMapping::getNumOperands(), llvm::MachineOperand::getReg(), llvm::LLT::getSizeInBits(), llvm::RegisterBankInfo::OperandsMapper::getVRegs(), llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownLE(), llvm::MachineOperand::isReg(), llvm::LLT::isValid(), LLVM_DEBUG, MI, MRI, llvm::RegisterBankInfo::ValueMapping::NumBreakDowns, llvm::printReg(), and llvm::MachineOperand::setReg().

Referenced by applyMapping(), llvm::AMDGPURegisterBankInfo::applyMappingBFE(), llvm::AMDGPURegisterBankInfo::applyMappingImage(), llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::MipsRegisterBankInfo::applyMappingImpl(), llvm::X86RegisterBankInfo::applyMappingImpl(), llvm::AMDGPURegisterBankInfo::applyMappingMAD_64_32(), and llvm::AMDGPURegisterBankInfo::applyMappingSMULU64().

◆ applyMapping()

void llvm::RegisterBankInfo::applyMapping	(	MachineIRBuilder &	Builder,
		const OperandsMapper &	OpdMapper
	)		const

inline

Apply OpdMapper.getInstrMapping() to OpdMapper.getMI().

After this call OpdMapper.getMI() may not be valid anymore. OpdMapper.getInstrMapping().getID() carries the information of what has been chosen to map OpdMapper.getMI(). This ID is set by the various getInstrXXXMapping method.

Therefore, getting the mapping and applying it should be kept in sync.

Definition at line 735 of file RegisterBankInfo.h.

References applyDefaultMapping(), applyMappingImpl(), DefaultMappingID, llvm::RegisterBankInfo::InstructionMapping::getID(), and llvm::RegisterBankInfo::OperandsMapper::getInstrMapping().

Referenced by llvm::RegBankSelect::applyMapping().

◆ applyMappingImpl()

virtual void llvm::RegisterBankInfo::applyMappingImpl	(	MachineIRBuilder &	Builder,
		const OperandsMapper &	OpdMapper
	)		const

inlinevirtual

See applyMapping.

Reimplemented in llvm::AMDGPURegisterBankInfo, llvm::MipsRegisterBankInfo, and llvm::X86RegisterBankInfo.

Definition at line 576 of file RegisterBankInfo.h.

References llvm_unreachable.

Referenced by applyMapping().

◆ cannotCopy()

bool llvm::RegisterBankInfo::cannotCopy	(	const RegisterBank &	Dst,
		const RegisterBank &	Src,
		TypeSize	Size
	)		const

inline

Returns: true if emitting a copy from Src to Dst is impossible.

Definition at line 643 of file RegisterBankInfo.h.

References copyCost(), and Size.

Referenced by llvm::AMDGPURegisterBankInfo::getInstrMapping(), and getInstrMappingImpl().

◆ constrainGenericRegister()

const TargetRegisterClass * RegisterBankInfo::constrainGenericRegister	(	Register	Reg,
		const TargetRegisterClass &	RC,
		MachineRegisterInfo &	MRI
	)

static

Constrain the (possibly generic) virtual register Reg to RC.

Precondition: Reg is a virtual register that either has a bank or a class.

Returns: The constrained register class, or nullptr if there is none.

Note: This is a generic variant of MachineRegisterInfo::constrainRegClass; Use MachineRegisterInfo::constrainRegAttrs instead for any non-isel purpose, including non-select passes of GlobalISel

Definition at line 132 of file RegisterBankInfo.cpp.

References llvm::RegisterBank::covers(), and MRI.

Referenced by llvm::AMDGPURegisterBankInfo::buildReadFirstLane(), llvm::AMDGPURegisterBankInfo::buildVCopy(), llvm::constrainRegToClass(), copySubReg(), selectCopy(), and selectDebugInstr().

◆ copyCost()

virtual unsigned llvm::RegisterBankInfo::copyCost	(	const RegisterBank &	A,
		const RegisterBank &	B,
		TypeSize	Size
	)		const

inlinevirtual

Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.

Since register banks may cover different size, Size specifies what will be the size in bits that will be copied around.

Note: Since this is a copy, both registers have the same size.

Reimplemented in llvm::AArch64RegisterBankInfo, and llvm::AMDGPURegisterBankInfo.

Definition at line 633 of file RegisterBankInfo.h.

References A, and B.

Referenced by cannotCopy(), llvm::AArch64RegisterBankInfo::copyCost(), llvm::AMDGPURegisterBankInfo::copyCost(), and llvm::RegBankSelect::getRepairCost().

◆ getBreakDownCost()

virtual unsigned llvm::RegisterBankInfo::getBreakDownCost	(	const ValueMapping &	ValMapping,
		const RegisterBank *	CurBank = `nullptr`
	)		const

inlinevirtual

Get the cost of using ValMapping to decompose a register.

This is similar to copyCost, except for cases where multiple copy-like operations need to be inserted. If the register is used as a source operand and already has a bank assigned, CurBank is non-null.

Reimplemented in llvm::AMDGPURegisterBankInfo.

Definition at line 653 of file RegisterBankInfo.h.

Referenced by llvm::RegBankSelect::getRepairCost().

◆ getInstrAlternativeMappings()

RegisterBankInfo::InstructionMappings RegisterBankInfo::getInstrAlternativeMappings ( const MachineInstr & MI ) const

virtual

Get the alternative mappings for MI.

Alternative in the sense different from getInstrMapping.

Reimplemented in llvm::AArch64RegisterBankInfo, llvm::AMDGPURegisterBankInfo, llvm::PPCRegisterBankInfo, and llvm::X86RegisterBankInfo.

Definition at line 434 of file RegisterBankInfo.cpp.

Referenced by llvm::AArch64RegisterBankInfo::getInstrAlternativeMappings(), llvm::AMDGPURegisterBankInfo::getInstrAlternativeMappings(), llvm::PPCRegisterBankInfo::getInstrAlternativeMappings(), llvm::X86RegisterBankInfo::getInstrAlternativeMappings(), llvm::AMDGPURegisterBankInfo::getInstrAlternativeMappingsIntrinsic(), llvm::AMDGPURegisterBankInfo::getInstrAlternativeMappingsIntrinsicWSideEffects(), and getInstrPossibleMappings().

◆ getInstrMapping()

const RegisterBankInfo::InstructionMapping & RegisterBankInfo::getInstrMapping ( const MachineInstr & MI ) const

virtual

Get the mapping of the different operands of MI on the register bank.

This mapping should be the direct translation of MI. In other words, when MI is mapped with the returned mapping, only the register banks of the operands of MI need to be updated. In particular, neither the opcode nor the type of MI needs to be updated for this direct mapping.

The target independent implementation gives a mapping based on the register classes for the target specific opcode. It uses the ID RegisterBankInfo::DefaultMappingID for that mapping. Make sure you do not use that ID for the alternative mapping for MI. See getInstrAlternativeMappings for the alternative mappings.

For instance, if MI is a vector add, the mapping should not be a scalarization of the add.

Postcondition: returnedVal.verify(MI).

Note: If returnedVal does not verify MI, this would probably mean that the target does not support that instruction.

Reimplemented in llvm::AArch64RegisterBankInfo, llvm::AMDGPURegisterBankInfo, llvm::ARMRegisterBankInfo, llvm::M68kRegisterBankInfo, llvm::MipsRegisterBankInfo, llvm::PPCRegisterBankInfo, llvm::RISCVRegisterBankInfo, and llvm::X86RegisterBankInfo.

Definition at line 407 of file RegisterBankInfo.cpp.

References getInstrMappingImpl(), llvm::RegisterBankInfo::InstructionMapping::isValid(), llvm_unreachable, and MI.

Referenced by llvm::RegBankSelect::assignInstr(), llvm::RegisterBankInfo::OperandsMapper::createVRegs(), getInstrPossibleMappings(), llvm::RegisterBankInfo::OperandsMapper::getVRegs(), llvm::RegisterBankInfo::OperandsMapper::print(), and llvm::RegisterBankInfo::OperandsMapper::setVRegs().

◆ getInstrMappingImpl()

const RegisterBankInfo::InstructionMapping & RegisterBankInfo::getInstrMappingImpl ( const MachineInstr & MI ) const

protected

Try to get the mapping of MI.

See getInstrMapping for more details on what a mapping represents.

Unlike getInstrMapping the returned InstructionMapping may be invalid (isValid() == false). This means that the target independent code is not smart enough to get the mapping of MI and thus, the target has to provide the information for MI.

This implementation is able to get the mapping of:

Target specific instructions by looking at the encoding constraints.
Any instruction if all the register operands have already been assigned a register, a register class, or a register bank.
Copies and phis if at least one of the operands has been assigned a register, a register class, or a register bank. In other words, this method will likely fail to find a mapping for any generic opcode that has not been lowered by target specific code.

Definition at line 162 of file RegisterBankInfo.cpp.

References assert(), cannotCopy(), DefaultMappingID, llvm::TargetSubtargetInfo::getInstrInfo(), getInstructionMapping(), getInvalidInstructionMapping(), getOperandsMapping(), llvm::MachineOperand::getReg(), getRegBank(), getRegBankFromConstraints(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), getSizeInBits(), llvm::MachineFunction::getSubtarget(), getValueMapping(), isCopyLike(), llvm::MachineOperand::isReg(), MI, MRI, Size, TII, and TRI.

Referenced by getInstrMapping(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), llvm::ARMRegisterBankInfo::getInstrMapping(), llvm::M68kRegisterBankInfo::getInstrMapping(), llvm::MipsRegisterBankInfo::getInstrMapping(), llvm::PPCRegisterBankInfo::getInstrMapping(), llvm::RISCVRegisterBankInfo::getInstrMapping(), and llvm::X86RegisterBankInfo::getInstrMapping().

◆ getInstrPossibleMappings()

RegisterBankInfo::InstructionMappings RegisterBankInfo::getInstrPossibleMappings ( const MachineInstr & MI ) const

Get the possible mapping for MI.

A mapping defines where the different operands may live and at what cost. For instance, let us consider: v0(16) = G_ADD <2 x i8> v1, v2 The possible mapping could be:

{/*ID*‍/VectorAdd, /*Cost*‍/1, /*v0*‍/{(0xFFFF, VPR)}, /*v1*‍/{(0xFFFF, VPR)}, /*v2*‍/{(0xFFFF, VPR)}} {/*ID*‍/ScalarAddx2, /*Cost*‍/2, /*v0*‍/{(0x00FF, GPR),(0xFF00, GPR)}, /*v1*‍/{(0x00FF, GPR),(0xFF00, GPR)}, /*v2*‍/{(0x00FF, GPR),(0xFF00, GPR)}}

Note: The first alternative of the returned mapping should be the direct translation of MI current form.

Postcondition: !returnedVal.empty().

Definition at line 415 of file RegisterBankInfo.cpp.

References llvm::append_range(), assert(), getInstrAlternativeMappings(), getInstrMapping(), MI, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by llvm::RegBankSelect::assignInstr().

◆ getInstructionMapping()

const InstructionMapping & llvm::RegisterBankInfo::getInstructionMapping	(	unsigned	ID,
		unsigned	Cost,
		const ValueMapping *	OperandsMapping,
		unsigned	NumOperands
	)		const

inline

Method to get a uniquely generated InstructionMapping.

Definition at line 534 of file RegisterBankInfo.h.

◆ getInvalidInstructionMapping()

const InstructionMapping & llvm::RegisterBankInfo::getInvalidInstructionMapping ( ) const

inline

Method to get a uniquely generated invalid InstructionMapping.

Definition at line 542 of file RegisterBankInfo.h.

Referenced by llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), llvm::ARMRegisterBankInfo::getInstrMapping(), llvm::M68kRegisterBankInfo::getInstrMapping(), llvm::MipsRegisterBankInfo::getInstrMapping(), llvm::PPCRegisterBankInfo::getInstrMapping(), llvm::X86RegisterBankInfo::getInstrMapping(), and getInstrMappingImpl().

◆ getMaximumSize()

unsigned llvm::RegisterBankInfo::getMaximumSize ( unsigned RegBankID ) const

inline

Get the maximum size in bits that fits in the given register bank.

Definition at line 590 of file RegisterBankInfo.h.

References HwMode, NumRegBanks, and Sizes.

Referenced by llvm::AArch64RegisterBankInfo::AArch64RegisterBankInfo(), llvm::ARMRegisterBankInfo::ARMRegisterBankInfo(), llvm::RISCVRegisterBankInfo::getInstrMapping(), llvm::RegisterBankInfo::PartialMapping::verify(), llvm::RegisterBank::verify(), and llvm::X86RegisterBankInfo::X86RegisterBankInfo().

◆ getMinimalPhysRegClass()

const TargetRegisterClass * RegisterBankInfo::getMinimalPhysRegClass	(	Register	Reg,
		const TargetRegisterInfo &	TRI
	)		const

protected

Get the MinimalPhysRegClass for Reg.

Precondition: Reg is a physical register.

Definition at line 103 of file RegisterBankInfo.cpp.

References assert(), PhysRegMinimalRCs, and TRI.

Referenced by getRegBank(), and getSizeInBits().

◆ getNumRegBanks()

unsigned llvm::RegisterBankInfo::getNumRegBanks ( ) const

inline

Get the total number of register banks.

Definition at line 603 of file RegisterBankInfo.h.

References NumRegBanks.

Referenced by getRegBank(), RegisterBankInfo(), and verify().

◆ getOperandsMapping() [1/3]

const RegisterBankInfo::ValueMapping * RegisterBankInfo::getOperandsMapping ( const SmallVectorImpl< const ValueMapping * > & OpdsMapping ) const

protected

Get the uniquely generated array of ValueMapping for the elements of OpdsMapping.

Elements of OpdsMapping that are nullptr will be replaced by invalid ValueMapping (ValueMapping::isValid == false).

Definition at line 362 of file RegisterBankInfo.cpp.

References llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::SmallVectorTemplateCommon< T, typename >::end(), and getOperandsMapping().

◆ getOperandsMapping() [2/3]

template<typename Iterator >

const RegisterBankInfo::ValueMapping * RegisterBankInfo::getOperandsMapping	(	Iterator	Begin,
		Iterator	End
	)		const

protected

Get the uniquely generated array of ValueMapping for the elements of between Begin and End.

Elements that are nullptr will be replaced by invalid ValueMapping (ValueMapping::isValid == false).

Precondition: The pointers on ValueMapping between Begin and End must uniquely identify a ValueMapping. Otherwise, there is no guarantee that the return instance will be unique, i.e., another OperandsMapping could have the same content.

Definition at line 333 of file RegisterBankInfo.cpp.

References End, llvm::hash_combine_range(), Idx, and MapOfOperandsMappings.

◆ getOperandsMapping() [3/3]

const ValueMapping * llvm::RegisterBankInfo::getOperandsMapping ( std::initializer_list< const ValueMapping * > OpdsMapping ) const

protected

Get the uniquely generated array of ValueMapping for the given arguments.

Arguments that are nullptr will be replaced by invalid ValueMapping (ValueMapping::isValid == false).

◆ getPartialMapping()

const RegisterBankInfo::PartialMapping & RegisterBankInfo::getPartialMapping	(	unsigned	StartIdx,
		unsigned	Length,
		const RegisterBank &	RegBank
	)		const

protected

Get the uniquely generated PartialMapping for the given arguments.

Definition at line 281 of file RegisterBankInfo.cpp.

References hashPartialMapping(), llvm::Length, and MapOfPartialMappings.

Referenced by getValueMapping().

◆ getRegBank() [1/3]

const RegisterBank * RegisterBankInfo::getRegBank	(	Register	Reg,
		const MachineRegisterInfo &	MRI,
		const TargetRegisterInfo &	TRI
	)		const

Get the register bank of Reg.

If Reg has not been assigned a register, a register class, or a register bank, then this returns nullptr.

Precondition: Reg != 0 (NoRegister)

Definition at line 84 of file RegisterBankInfo.cpp.

References getMinimalPhysRegClass(), getRegBankFromRegClass(), MRI, and TRI.

◆ getRegBank() [2/3]

const RegisterBank & llvm::RegisterBankInfo::getRegBank ( unsigned ID )

inlineprotected

Get the register bank identified by ID.

Definition at line 440 of file RegisterBankInfo.h.

References assert(), getNumRegBanks(), and RegBanks.

◆ getRegBank() [3/3]

const RegisterBank & llvm::RegisterBankInfo::getRegBank ( unsigned ID ) const

inline

Get the register bank identified by ID.

Definition at line 585 of file RegisterBankInfo.h.

References getRegBank().

◆ getRegBankFromConstraints()

const RegisterBank * RegisterBankInfo::getRegBankFromConstraints	(	const MachineInstr &	MI,
		unsigned	OpIdx,
		const TargetInstrInfo &	TII,
		const MachineRegisterInfo &	MRI
	)		const

Get the register bank for the OpIdx-th operand of MI form the encoding constraints, if any.

Returns: A register bank that covers the register class of the related encoding constraints or nullptr if MI did not provide enough information to deduce it.

Definition at line 112 of file RegisterBankInfo.cpp.

References assert(), llvm::RegisterBank::covers(), getRegBankFromRegClass(), MI, MRI, TII, and TRI.

Referenced by getInstrMappingImpl().

◆ getRegBankFromRegClass()

virtual const RegisterBank & llvm::RegisterBankInfo::getRegBankFromRegClass	(	const TargetRegisterClass &	RC,
		LLT	Ty
	)		const

inlinevirtual

Get a register bank that covers RC.

Precondition: RC is a user-defined register class (as opposed as one generated by TableGen).

Note: The mapping RC -> RegBank could be built while adding the coverage for the register banks. However, we do not do it, because, at least for now, we only need this information for register classes that are used in the description of instruction. In other words, there are just a handful of them and we do not want to waste space.

Todo:: This should be TableGen'ed.

Reimplemented in llvm::AArch64RegisterBankInfo, llvm::PPCRegisterBankInfo, llvm::SPIRVRegisterBankInfo, and llvm::AMDGPURegisterBankInfo.

Definition at line 623 of file RegisterBankInfo.h.

References llvm_unreachable.

Referenced by llvm::GIMatchTableExecutor::executeMatchTable(), getRegBank(), getRegBankFromConstraints(), llvm::AArch64RegisterBankInfo::getRegBankFromRegClass(), and llvm::PPCRegisterBankInfo::getRegBankFromRegClass().

◆ getSizeInBits()

TypeSize RegisterBankInfo::getSizeInBits	(	Register	Reg,
		const MachineRegisterInfo &	MRI,
		const TargetRegisterInfo &	TRI
	)		const

Get the size in bits of Reg.

Utility method to get the size of any registers. Unlike MachineRegisterInfo::getSize, the register does not need to be a virtual register.

Precondition: Reg != 0 (NoRegister).

Definition at line 498 of file RegisterBankInfo.cpp.

References assert(), getMinimalPhysRegClass(), MRI, and TRI.

◆ getValueMapping() [1/2]

const RegisterBankInfo::ValueMapping & RegisterBankInfo::getValueMapping	(	const PartialMapping *	BreakDown,
		unsigned	NumBreakDowns
	)		const

protected

Get the ValueMapping for the given arguments.

Definition at line 315 of file RegisterBankInfo.cpp.

References hashValueMapping(), and MapOfValueMappings.

◆ getValueMapping() [2/2]

const RegisterBankInfo::ValueMapping & RegisterBankInfo::getValueMapping	(	unsigned	StartIdx,
		unsigned	Length,
		const RegisterBank &	RegBank
	)		const

protected

The most common ValueMapping consists of a single PartialMapping.

Feature a method for that.

Definition at line 298 of file RegisterBankInfo.cpp.

References getPartialMapping(), getValueMapping(), and llvm::Length.

Referenced by llvm::AMDGPURegisterBankInfo::getInstrMapping(), getInstrMappingImpl(), and getValueMapping().

◆ isDivergentRegBank()

virtual bool llvm::RegisterBankInfo::isDivergentRegBank ( const RegisterBank * RB ) const

inlinevirtual

Returns true if the register bank is considered divergent.

Reimplemented in llvm::AMDGPURegisterBankInfo.

Definition at line 606 of file RegisterBankInfo.h.

Referenced by llvm::SIRegisterInfo::isUniformReg().

◆ verify()

bool RegisterBankInfo::verify ( const TargetRegisterInfo & TRI ) const

Check that information hold by this instance make sense for the given TRI.

Note: This method does not check anything when assertions are disabled.

Returns: True is the check was successful.

Definition at line 70 of file RegisterBankInfo.cpp.

References assert(), llvm::dbgs(), End, llvm::RegisterBank::getID(), getNumRegBanks(), getRegBank(), Idx, LLVM_DEBUG, TRI, and llvm::RegisterBank::verify().

Member Data Documentation

◆ DefaultMappingID

const unsigned RegisterBankInfo::DefaultMappingID = UINT_MAX

static

Identifier used when the related instruction mapping instance is generated by target independent code.

Make sure not to use that identifier to avoid possible collision.

Definition at line 672 of file RegisterBankInfo.h.

Referenced by applyMapping(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::ARMRegisterBankInfo::getInstrMapping(), llvm::M68kRegisterBankInfo::getInstrMapping(), llvm::MipsRegisterBankInfo::getInstrMapping(), llvm::PPCRegisterBankInfo::getInstrMapping(), llvm::RISCVRegisterBankInfo::getInstrMapping(), llvm::X86RegisterBankInfo::getInstrMapping(), and getInstrMappingImpl().

◆ HwMode

unsigned llvm::RegisterBankInfo::HwMode

protected

Current HwMode for the target.

Definition at line 398 of file RegisterBankInfo.h.

Referenced by getMaximumSize().

◆ InvalidMappingID

const unsigned RegisterBankInfo::InvalidMappingID = UINT_MAX - 1

static

Identifier used when the related instruction mapping instance is generated by the default constructor.

Make sure not to use that identifier.

Definition at line 677 of file RegisterBankInfo.h.

Referenced by llvm::RegisterBankInfo::InstructionMapping::isValid().

◆ MapOfInstructionMappings

DenseMap<hash_code, std::unique_ptr<const InstructionMapping> > llvm::RegisterBankInfo::MapOfInstructionMappings

mutableprotected

Keep dynamically allocated InstructionMapping in a separate map.

This shouldn't be needed when everything gets TableGen'ed.

Definition at line 418 of file RegisterBankInfo.h.

◆ MapOfOperandsMappings

DenseMap<hash_code, std::unique_ptr<ValueMapping[]> > llvm::RegisterBankInfo::MapOfOperandsMappings

mutableprotected

Keep dynamically allocated array of ValueMapping in a separate map.

This shouldn't be needed when everything gets TableGen'ed.

Definition at line 413 of file RegisterBankInfo.h.

Referenced by getOperandsMapping().

◆ MapOfPartialMappings

DenseMap<hash_code, std::unique_ptr<const PartialMapping> > llvm::RegisterBankInfo::MapOfPartialMappings

mutableprotected

Keep dynamically allocated PartialMapping in a separate map.

This shouldn't be needed when everything gets TableGen'ed.

Definition at line 403 of file RegisterBankInfo.h.

Referenced by getPartialMapping().

◆ MapOfValueMappings

DenseMap<hash_code, std::unique_ptr<const ValueMapping> > llvm::RegisterBankInfo::MapOfValueMappings

mutableprotected

Keep dynamically allocated ValueMapping in a separate map.

This shouldn't be needed when everything gets TableGen'ed.

Definition at line 408 of file RegisterBankInfo.h.

Referenced by getValueMapping().

◆ NumRegBanks

unsigned llvm::RegisterBankInfo::NumRegBanks

protected

Total number of register banks.

Definition at line 392 of file RegisterBankInfo.h.

Referenced by getMaximumSize(), and getNumRegBanks().

◆ PhysRegMinimalRCs

DenseMap<unsigned, const TargetRegisterClass *> llvm::RegisterBankInfo::PhysRegMinimalRCs

mutableprotected

Getting the minimal register class of a physreg is expensive.

Cache this information as we get it.

Definition at line 422 of file RegisterBankInfo.h.

Referenced by getMinimalPhysRegClass().

◆ RegBanks

const RegisterBank** llvm::RegisterBankInfo::RegBanks

protected

Hold the set of supported register banks.

Definition at line 389 of file RegisterBankInfo.h.

Referenced by getRegBank(), and RegisterBankInfo().

◆ Sizes

const unsigned* llvm::RegisterBankInfo::Sizes

protected

Hold the sizes of the register banks for all HwModes.

Definition at line 395 of file RegisterBankInfo.h.

Referenced by llvm::AMDGPURegisterBankInfo::addMappingFromTable(), and getMaximumSize().

The documentation for this class was generated from the following files:

include/llvm/CodeGen/RegisterBankInfo.h
lib/CodeGen/RegisterBankInfo.cpp

Classes

Public Types

Public Member Functions

Static Public Member Functions

Static Public Attributes

Protected Member Functions

Protected Attributes

Methods to get a uniquely generated InstructionMapping.

Detailed Description

Member Typedef Documentation

◆ InstructionMappings

Constructor & Destructor Documentation

◆ RegisterBankInfo() [1/2]

◆ RegisterBankInfo() [2/2]

◆ ~RegisterBankInfo()

Member Function Documentation

◆ applyDefaultMapping()

◆ applyMapping()

◆ applyMappingImpl()

◆ cannotCopy()

◆ constrainGenericRegister()

◆ copyCost()

◆ getBreakDownCost()

◆ getInstrAlternativeMappings()

◆ getInstrMapping()

◆ getInstrMappingImpl()

◆ getInstrPossibleMappings()

◆ getInstructionMapping()

◆ getInvalidInstructionMapping()

◆ getMaximumSize()

◆ getMinimalPhysRegClass()

◆ getNumRegBanks()

◆ getOperandsMapping() [1/3]

◆ getOperandsMapping() [2/3]

◆ getOperandsMapping() [3/3]

◆ getPartialMapping()

◆ getRegBank() [1/3]

◆ getRegBank() [2/3]

◆ getRegBank() [3/3]

◆ getRegBankFromConstraints()

◆ getRegBankFromRegClass()

◆ getSizeInBits()

◆ getValueMapping() [1/2]

◆ getValueMapping() [2/2]

◆ isDivergentRegBank()

◆ verify()

Member Data Documentation

◆ DefaultMappingID

◆ HwMode

◆ InvalidMappingID

◆ MapOfInstructionMappings

◆ MapOfOperandsMappings

◆ MapOfPartialMappings

◆ MapOfValueMappings

◆ NumRegBanks

◆ PhysRegMinimalRCs

◆ RegBanks

◆ Sizes