LLVM  12.0.0git
Classes | Public Member Functions | Public Attributes | List of all members
llvm::AMDGPURegisterBankInfo Class Reference

#include "Target/AMDGPU/AMDGPURegisterBankInfo.h"

Inheritance diagram for llvm::AMDGPURegisterBankInfo:
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Collaboration diagram for llvm::AMDGPURegisterBankInfo:
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Classes

struct  OpRegBankEntry
 

Public Member Functions

bool buildVCopy (MachineIRBuilder &B, Register DstReg, Register SrcReg) const
 
bool collectWaterfallOperands (SmallSet< Register, 4 > &SGPROperandRegs, MachineInstr &MI, MachineRegisterInfo &MRI, ArrayRef< unsigned > OpIndices) const
 
bool executeInWaterfallLoop (MachineIRBuilder &B, iterator_range< MachineBasicBlock::iterator > Range, SmallSet< Register, 4 > &SGPROperandRegs, MachineRegisterInfo &MRI) const
 Legalize instruction MI where operands in OpIndices must be SGPRs. More...
 
bool executeInWaterfallLoop (MachineIRBuilder &B, MachineInstr &MI, MachineRegisterInfo &MRI, ArrayRef< unsigned > OpIndices) const
 
bool executeInWaterfallLoop (MachineInstr &MI, MachineRegisterInfo &MRI, ArrayRef< unsigned > OpIndices) const
 
void constrainOpWithReadfirstlane (MachineInstr &MI, MachineRegisterInfo &MRI, unsigned OpIdx) const
 
bool applyMappingDynStackAlloc (MachineInstr &MI, const OperandsMapper &OpdMapper, MachineRegisterInfo &MRI) const
 
bool applyMappingLoad (MachineInstr &MI, const OperandsMapper &OpdMapper, MachineRegisterInfo &MRI) const
 
bool applyMappingImage (MachineInstr &MI, const OperandsMapper &OpdMapper, MachineRegisterInfo &MRI, int RSrcIdx) const
 
bool applyMappingSBufferLoad (const OperandsMapper &OpdMapper) const
 
bool applyMappingBFEIntrinsic (const OperandsMapper &OpdMapper, bool Signed) const
 
void lowerScalarMinMax (MachineIRBuilder &B, MachineInstr &MI) const
 
Register handleD16VData (MachineIRBuilder &B, MachineRegisterInfo &MRI, Register Reg) const
 Handle register layout difference for f16 images for some subtargets. More...
 
std::pair< Register, unsignedsplitBufferOffsets (MachineIRBuilder &B, Register Offset) const
 
MachineInstrselectStoreIntrinsic (MachineIRBuilder &B, MachineInstr &MI) const
 
void applyMappingImpl (const OperandsMapper &OpdMapper) const override
 See RegisterBankInfo::applyMapping. More...
 
const ValueMappinggetValueMappingForPtr (const MachineRegisterInfo &MRI, Register Ptr) const
 Return the mapping for a pointer arugment. More...
 
const RegisterBankInfo::InstructionMappinggetInstrMappingForLoad (const MachineInstr &MI) const
 
unsigned getRegBankID (Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, unsigned Default=AMDGPU::VGPRRegBankID) const
 
const ValueMappinggetSGPROpMapping (Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
 
const ValueMappinggetVGPROpMapping (Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
 
const ValueMappinggetAGPROpMapping (Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
 
void split64BitValueForMapping (MachineIRBuilder &B, SmallVector< Register, 2 > &Regs, LLT HalfTy, Register Reg) const
 Split 64-bit value Reg into two 32-bit halves and populate them into Regs. More...
 
template<unsigned NumOps>
InstructionMappings addMappingFromTable (const MachineInstr &MI, const MachineRegisterInfo &MRI, const std::array< unsigned, NumOps > RegSrcOpIdx, ArrayRef< OpRegBankEntry< NumOps >> Table) const
 
RegisterBankInfo::InstructionMappings getInstrAlternativeMappingsIntrinsic (const MachineInstr &MI, const MachineRegisterInfo &MRI) const
 
RegisterBankInfo::InstructionMappings getInstrAlternativeMappingsIntrinsicWSideEffects (const MachineInstr &MI, const MachineRegisterInfo &MRI) const
 
bool isSALUMapping (const MachineInstr &MI) const
 
const InstructionMappinggetDefaultMappingSOP (const MachineInstr &MI) const
 
const InstructionMappinggetDefaultMappingVOP (const MachineInstr &MI) const
 
const InstructionMappinggetDefaultMappingAllVGPR (const MachineInstr &MI) const
 
const InstructionMappinggetImageMapping (const MachineRegisterInfo &MRI, const MachineInstr &MI, int RsrcIdx) const
 
 AMDGPURegisterBankInfo (const GCNSubtarget &STI)
 
unsigned copyCost (const RegisterBank &A, const RegisterBank &B, unsigned Size) const override
 Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B. More...
 
unsigned getBreakDownCost (const ValueMapping &ValMapping, const RegisterBank *CurBank=nullptr) const override
 Get the cost of using ValMapping to decompose a register. More...
 
const RegisterBankgetRegBankFromRegClass (const TargetRegisterClass &RC, LLT) const override
 Get a register bank that covers RC. More...
 
InstructionMappings getInstrAlternativeMappings (const MachineInstr &MI) const override
 Get the alternative mappings for MI. More...
 
const InstructionMappinggetInstrMapping (const MachineInstr &MI) const override
 This function must return a legal mapping, because AMDGPURegisterBankInfo::getInstrAlternativeMappings() is not called in RegBankSelect::Mode::Fast. More...
 
template<unsigned NumOps>
RegisterBankInfo::InstructionMappings addMappingFromTable (const MachineInstr &MI, const MachineRegisterInfo &MRI, const std::array< unsigned, NumOps > RegSrcOpIdx, ArrayRef< OpRegBankEntry< NumOps >> Table) const
 
- Public Member Functions inherited from llvm::RegisterBankInfo
const RegisterBankgetRegBankFromConstraints (const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const MachineRegisterInfo &MRI) const
 Get the register bank for the OpIdx-th operand of MI form the encoding constraints, if any. More...
 
virtual ~RegisterBankInfo ()=default
 
const RegisterBankgetRegBank (unsigned ID) const
 Get the register bank identified by ID. More...
 
const RegisterBankgetRegBank (Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
 Get the register bank of Reg. More...
 
unsigned getNumRegBanks () const
 Get the total number of register banks. More...
 
bool cannotCopy (const RegisterBank &Dst, const RegisterBank &Src, unsigned Size) const
 
const InstructionMappinggetInstructionMapping (unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
 Method to get a uniquely generated InstructionMapping. More...
 
const InstructionMappinggetInvalidInstructionMapping () const
 Method to get a uniquely generated invalid InstructionMapping. More...
 

Public Attributes

const GCNSubtargetSubtarget
 
const SIRegisterInfoTRI
 
const SIInstrInfoTII
 
- Public Attributes inherited from llvm::RegisterBankInfo
struct llvm::RegisterBankInfo::PartialMapping ScalarAddx2
 
 VectorAdd
 Get the possible mapping for MI. More...
 

Additional Inherited Members

- Public Types inherited from llvm::RegisterBankInfo
using InstructionMappings = SmallVector< const InstructionMapping *, 4 >
 Convenient type to represent the alternatives for mapping an instruction. More...
 
- Static Public Member Functions inherited from llvm::RegisterBankInfo
static void applyDefaultMapping (const OperandsMapper &OpdMapper)
 Helper method to apply something that is like the default mapping. More...
 
static const TargetRegisterClassconstrainGenericRegister (Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
 Constrain the (possibly generic) virtual register Reg to RC. More...
 
- Static Public Attributes inherited from llvm::RegisterBankInfo
static const unsigned DefaultMappingID = UINT_MAX
 Identifier used when the related instruction mapping instance is generated by target independent code. More...
 
static const unsigned InvalidMappingID = UINT_MAX - 1
 Identifier used when the related instruction mapping instance is generated by the default constructor. More...
 
- Protected Member Functions inherited from llvm::RegisterBankInfo
 RegisterBankInfo (RegisterBank **RegBanks, unsigned NumRegBanks)
 Create a RegisterBankInfo that can accommodate up to NumRegBanks RegisterBank instances. More...
 
 RegisterBankInfo ()
 This constructor is meaningless. More...
 
RegisterBankgetRegBank (unsigned ID)
 Get the register bank identified by ID. More...
 
const TargetRegisterClassgetMinimalPhysRegClass (Register Reg, const TargetRegisterInfo &TRI) const
 Get the MinimalPhysRegClass for Reg. More...
 
const InstructionMappinggetInstrMappingImpl (const MachineInstr &MI) const
 Try to get the mapping of MI. More...
 
const PartialMappinggetPartialMapping (unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
 Get the uniquely generated PartialMapping for the given arguments. More...
 
const ValueMappinggetValueMapping (unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
 The most common ValueMapping consists of a single PartialMapping. More...
 
const ValueMappinggetValueMapping (const PartialMapping *BreakDown, unsigned NumBreakDowns) const
 Get the ValueMapping for the given arguments. More...
 
template<typename Iterator >
const ValueMappinggetOperandsMapping (Iterator Begin, Iterator End) const
 Get the uniquely generated array of ValueMapping for the elements of between Begin and End. More...
 
const ValueMappinggetOperandsMapping (const SmallVectorImpl< const ValueMapping *> &OpdsMapping) const
 Get the uniquely generated array of ValueMapping for the elements of OpdsMapping. More...
 
const ValueMappinggetOperandsMapping (std::initializer_list< const ValueMapping *> OpdsMapping) const
 Get the uniquely generated array of ValueMapping for the given arguments. More...
 
- Protected Attributes inherited from llvm::RegisterBankInfo
RegisterBank ** RegBanks
 Hold the set of supported register banks. More...
 
unsigned NumRegBanks
 Total number of register banks. More...
 
DenseMap< unsigned, std::unique_ptr< const PartialMapping > > MapOfPartialMappings
 Keep dynamically allocated PartialMapping in a separate map. More...
 
DenseMap< unsigned, std::unique_ptr< const ValueMapping > > MapOfValueMappings
 Keep dynamically allocated ValueMapping in a separate map. More...
 
DenseMap< unsigned, std::unique_ptr< ValueMapping[]> > MapOfOperandsMappings
 Keep dynamically allocated array of ValueMapping in a separate map. More...
 
DenseMap< unsigned, std::unique_ptr< const InstructionMapping > > MapOfInstructionMappings
 Keep dynamically allocated InstructionMapping in a separate map. More...
 
DenseMap< unsigned, const TargetRegisterClass * > PhysRegMinimalRCs
 Getting the minimal register class of a physreg is expensive. More...
 

Detailed Description

Definition at line 42 of file AMDGPURegisterBankInfo.h.

Constructor & Destructor Documentation

◆ AMDGPURegisterBankInfo()

AMDGPURegisterBankInfo::AMDGPURegisterBankInfo ( const GCNSubtarget STI)

Member Function Documentation

◆ addMappingFromTable() [1/2]

template<unsigned NumOps>
InstructionMappings llvm::AMDGPURegisterBankInfo::addMappingFromTable ( const MachineInstr MI,
const MachineRegisterInfo MRI,
const std::array< unsigned, NumOps >  RegSrcOpIdx,
ArrayRef< OpRegBankEntry< NumOps >>  Table 
) const

◆ addMappingFromTable() [2/2]

template<unsigned NumOps>
RegisterBankInfo::InstructionMappings llvm::AMDGPURegisterBankInfo::addMappingFromTable ( const MachineInstr MI,
const MachineRegisterInfo MRI,
const std::array< unsigned, NumOps >  RegSrcOpIdx,
ArrayRef< OpRegBankEntry< NumOps >>  Table 
) const

◆ applyMappingBFEIntrinsic()

bool AMDGPURegisterBankInfo::applyMappingBFEIntrinsic ( const OperandsMapper OpdMapper,
bool  Signed 
) const

◆ applyMappingDynStackAlloc()

bool AMDGPURegisterBankInfo::applyMappingDynStackAlloc ( MachineInstr MI,
const OperandsMapper OpdMapper,
MachineRegisterInfo MRI 
) const

◆ applyMappingImage()

bool AMDGPURegisterBankInfo::applyMappingImage ( MachineInstr MI,
const OperandsMapper OpdMapper,
MachineRegisterInfo MRI,
int  RSrcIdx 
) const

◆ applyMappingImpl()

void AMDGPURegisterBankInfo::applyMappingImpl ( const OperandsMapper OpdMapper) const
overridevirtual

See RegisterBankInfo::applyMapping.

Reimplemented from llvm::RegisterBankInfo.

Definition at line 2085 of file AMDGPURegisterBankInfo.cpp.

References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addUse(), llvm::RegisterBankInfo::applyDefaultMapping(), applyMappingBFEIntrinsic(), applyMappingDynStackAlloc(), applyMappingImage(), applyMappingLoad(), applyMappingSBufferLoad(), assert(), B, llvm::RegisterBankInfo::ValueMapping::BreakDown, llvm::MachineIRBuilder::buildAdd(), llvm::MachineIRBuilder::buildAnd(), llvm::MachineIRBuilder::buildAnyExtOrTrunc(), llvm::MachineIRBuilder::buildAShr(), llvm::MachineIRBuilder::buildBitcast(), llvm::MachineIRBuilder::buildBuildVectorTrunc(), llvm::MachineIRBuilder::buildConstant(), llvm::MachineIRBuilder::buildCopy(), buildExpandedScalarMinMax(), llvm::MachineIRBuilder::buildExtractVectorElement(), llvm::MachineIRBuilder::buildInstr(), llvm::MachineIRBuilder::buildOr(), llvm::MachineIRBuilder::buildSelect(), llvm::MachineIRBuilder::buildSExtInReg(), llvm::MachineIRBuilder::buildSExtOrTrunc(), llvm::MachineIRBuilder::buildShl(), llvm::MachineIRBuilder::buildTrunc(), buildVCopy(), llvm::MachineIRBuilder::buildZExt(), llvm::MachineIRBuilder::buildZExtOrTrunc(), collectWaterfallOperands(), constrainOpWithReadfirstlane(), llvm::MachineRegisterInfo::createGenericVirtualRegister(), E, llvm::empty(), llvm::MachineInstr::eraseFromParent(), executeInWaterfallLoop(), extendLow32IntoHigh32(), llvm::AMDGPU::getBaseWithConstantOffset(), llvm::MachineBasicBlock::getFirstTerminator(), getHalfSizedType(), llvm::RegisterBank::getID(), llvm::MachineOperand::getImm(), llvm::RegisterBankInfo::OperandsMapper::getInstrMapping(), llvm::MachineInstr::getIntrinsicID(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineIRBuilder::getMBB(), llvm::MachineOperand::getMBB(), llvm::MachineIRBuilder::getMF(), llvm::RegisterBankInfo::OperandsMapper::getMI(), llvm::RegisterBankInfo::OperandsMapper::getMRI(), llvm::LLT::getNumElements(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineInstrBuilder::getReg(), llvm::MachineOperand::getReg(), llvm::RegisterBankInfo::getRegBank(), llvm::LLT::getSizeInBits(), llvm::MachineRegisterInfo::getType(), llvm::RegisterBankInfo::OperandsMapper::getVRegs(), llvm::MipsISD::Hi, I, llvm::AMDGPU::RsrcIntrinsic::IsImage, llvm::LLT::isScalar(), llvm::LLT::isVector(), llvm::LegalizerHelper::Legalized, llvm_unreachable, llvm::MipsISD::Lo, llvm::AMDGPU::lookupRsrcIntrinsic(), lowerScalarMinMax(), llvm::make_range(), MBB, MI, minMaxToCompare(), minMaxToExtend(), llvm::LegalizerHelper::narrowScalar(), llvm::RISCVFenceField::O, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::RegisterBankInfo::PartialMapping::RegBank, reinsertVectorIndexAdd(), llvm::AMDGPU::RsrcIntrinsic::RsrcArg, llvm::LLT::scalar(), llvm::MachineIRBuilder::setChangeObserver(), llvm::MachineIRBuilder::setInsertPt(), llvm::MachineIRBuilder::setInstr(), llvm::MachineOperand::setReg(), llvm::MachineRegisterInfo::setRegBank(), setRegsToType(), llvm::MachineRegisterInfo::setType(), Signed, split64BitValueForMapping(), substituteSimpleCopyRegs(), TRI, unpackV2S16ToS32(), llvm::LLT::vector(), and llvm::LegalizerHelper::widenScalar().

◆ applyMappingLoad()

bool AMDGPURegisterBankInfo::applyMappingLoad ( MachineInstr MI,
const OperandsMapper OpdMapper,
MachineRegisterInfo MRI 
) const

◆ applyMappingSBufferLoad()

bool AMDGPURegisterBankInfo::applyMappingSBufferLoad ( const OperandsMapper OpdMapper) const

Definition at line 1389 of file AMDGPURegisterBankInfo.cpp.

References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addUse(), llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, B, llvm::RegisterBankInfo::ValueMapping::BreakDown, llvm::MachineIRBuilder::buildConcatVectors(), llvm::MachineIRBuilder::buildConstant(), llvm::MachineIRBuilder::buildInstr(), llvm::MachineIRBuilder::buildMerge(), llvm::MachineRegisterInfo::createGenericVirtualRegister(), llvm::LLT::divide(), llvm::MachineInstr::eraseFromParent(), executeInWaterfallLoop(), llvm::RegisterBankInfo::OperandsMapper::getInstrMapping(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineIRBuilder::getMBB(), llvm::MachineIRBuilder::getMF(), llvm::RegisterBankInfo::OperandsMapper::getMI(), llvm::MachineIRBuilder::getMRI(), llvm::RegisterBankInfo::OperandsMapper::getMRI(), llvm::MachineInstr::getOperand(), llvm::MachineInstrBuilder::getReg(), llvm::MachineOperand::getReg(), llvm::LLT::getSizeInBits(), llvm::MachineRegisterInfo::getType(), llvm::SmallSet< T, N, C >::insert(), llvm::LLT::isVector(), llvm::make_range(), MI, llvm::MachineMemOperand::MODereferenceable, llvm::MachineMemOperand::MOInvariant, llvm::MachineMemOperand::MOLoad, MRI, llvm::RegisterBankInfo::PartialMapping::RegBank, llvm::LLT::scalar(), setBufferOffsets(), llvm::MachineIRBuilder::setInstr(), and llvm::MachineRegisterInfo::setRegBank().

Referenced by applyMappingImpl().

◆ buildVCopy()

bool AMDGPURegisterBankInfo::buildVCopy ( MachineIRBuilder B,
Register  DstReg,
Register  SrcReg 
) const

◆ collectWaterfallOperands()

bool AMDGPURegisterBankInfo::collectWaterfallOperands ( SmallSet< Register, 4 > &  SGPROperandRegs,
MachineInstr MI,
MachineRegisterInfo MRI,
ArrayRef< unsigned OpIndices 
) const

◆ constrainOpWithReadfirstlane()

void AMDGPURegisterBankInfo::constrainOpWithReadfirstlane ( MachineInstr MI,
MachineRegisterInfo MRI,
unsigned  OpIdx 
) const

◆ copyCost()

unsigned AMDGPURegisterBankInfo::copyCost ( const RegisterBank A,
const RegisterBank B,
unsigned  Size 
) const
overridevirtual

Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.

Since register banks may cover different size, Size specifies what will be the size in bits that will be copied around.

Note
Since this is a copy, both registers have the same size.

Reimplemented from llvm::RegisterBankInfo.

Definition at line 218 of file AMDGPURegisterBankInfo.cpp.

References llvm::RegisterBankInfo::copyCost(), llvm::RegisterBank::getID(), isVectorRegisterBank(), and llvm::max().

◆ executeInWaterfallLoop() [1/3]

bool AMDGPURegisterBankInfo::executeInWaterfallLoop ( MachineIRBuilder B,
iterator_range< MachineBasicBlock::iterator Range,
SmallSet< Register, 4 > &  SGPROperandRegs,
MachineRegisterInfo MRI 
) const

Legalize instruction MI where operands in OpIndices must be SGPRs.

If any of the required SGPR operands are VGPRs, perform a waterfall loop to execute the instruction for each unique combination of values in all lanes in the wave. The block will be split such that rest of the instructions are moved to a new block.

Essentially performs this loop: Save Execution Mask For (Lane : Wavefront) { Enable Lane, Disable all other lanes SGPR = read SGPR value for current lane from VGPR VGPRResult[Lane] = use_op SGPR } Restore Execution Mask

There is additional complexity to try for compare values to identify the unique values used.

Definition at line 719 of file AMDGPURegisterBankInfo.cpp.

References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), assert(), llvm::iterator_range< IteratorT >::begin(), llvm::MachineBasicBlock::begin(), llvm::MachineIRBuilder::buildBuildVector(), llvm::MachineIRBuilder::buildInstr(), llvm::MachineIRBuilder::buildMerge(), llvm::BuildMI(), llvm::MachineIRBuilder::buildUndef(), llvm::MachineIRBuilder::buildUnmerge(), llvm::RegisterBankInfo::constrainGenericRegister(), llvm::SmallSet< T, N, C >::count(), llvm::MachineRegisterInfo::createGenericVirtualRegister(), llvm::MachineFunction::CreateMachineBasicBlock(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::tgtok::Def, DL, llvm::iterator_range< IteratorT >::end(), llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT, BucketT >, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::MachineBasicBlock::end(), llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT, BucketT >, KeyT, ValueT, KeyInfoT, BucketT >::find(), llvm::MachineIRBuilder::getDL(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineIRBuilder::getMBB(), llvm::MachineIRBuilder::getMF(), llvm::MachineInstrBuilder::getReg(), getReg(), llvm::RegisterBankInfo::getRegBank(), llvm::LLT::getScalarSizeInBits(), llvm::LLT::getSizeInBits(), llvm::MachineRegisterInfo::getType(), llvm::SIRegisterInfo::getWaveMaskRegClass(), I, llvm::DenseMapBase< DenseMap< KeyT, ValueT, KeyInfoT, BucketT >, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::MachineFunction::insert(), llvm::LLT::isVector(), llvm::GCNSubtarget::isWave32(), llvm::RegState::Kill, llvm::make_range(), MBB, MBBI, Merge, MI, MRI, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::LLT::scalar(), llvm::MachineIRBuilder::setInsertPt(), llvm::MachineIRBuilder::setInstr(), llvm::MachineIRBuilder::setMBB(), llvm::MachineRegisterInfo::setRegBank(), llvm::MachineRegisterInfo::setRegClass(), llvm::MachineRegisterInfo::setSimpleHint(), llvm::MachineRegisterInfo::setType(), llvm::MachineBasicBlock::splice(), Subtarget, TII, llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs(), TRI, and llvm::zip().

Referenced by applyMappingImage(), applyMappingImpl(), applyMappingSBufferLoad(), executeInWaterfallLoop(), and selectStoreIntrinsic().

◆ executeInWaterfallLoop() [2/3]

bool AMDGPURegisterBankInfo::executeInWaterfallLoop ( MachineIRBuilder B,
MachineInstr MI,
MachineRegisterInfo MRI,
ArrayRef< unsigned OpIndices 
) const

◆ executeInWaterfallLoop() [3/3]

bool AMDGPURegisterBankInfo::executeInWaterfallLoop ( MachineInstr MI,
MachineRegisterInfo MRI,
ArrayRef< unsigned OpIndices 
) const

Definition at line 1074 of file AMDGPURegisterBankInfo.cpp.

References B, and executeInWaterfallLoop().

◆ getAGPROpMapping()

const RegisterBankInfo::ValueMapping * AMDGPURegisterBankInfo::getAGPROpMapping ( Register  Reg,
const MachineRegisterInfo MRI,
const TargetRegisterInfo TRI 
) const

Definition at line 3343 of file AMDGPURegisterBankInfo.cpp.

References llvm::getSizeInBits(), getValueMapping(), and Size.

Referenced by getInstrMapping().

◆ getBreakDownCost()

unsigned AMDGPURegisterBankInfo::getBreakDownCost ( const ValueMapping ValMapping,
const RegisterBank CurBank = nullptr 
) const
overridevirtual

Get the cost of using ValMapping to decompose a register.

This is similar to copyCost, except for cases where multiple copy-like operations need to be inserted. If the register is used as a source operand and already has a bank assigned, CurBank is non-null.

Reimplemented from llvm::RegisterBankInfo.

Definition at line 249 of file AMDGPURegisterBankInfo.cpp.

References assert(), llvm::RegisterBankInfo::ValueMapping::BreakDown, llvm::RegisterBankInfo::PartialMapping::Length, llvm::RegisterBankInfo::ValueMapping::NumBreakDowns, llvm::RegisterBankInfo::PartialMapping::RegBank, and llvm::RegisterBankInfo::PartialMapping::StartIdx.

◆ getDefaultMappingAllVGPR()

const RegisterBankInfo::InstructionMapping & AMDGPURegisterBankInfo::getDefaultMappingAllVGPR ( const MachineInstr MI) const

◆ getDefaultMappingSOP()

const RegisterBankInfo::InstructionMapping & AMDGPURegisterBankInfo::getDefaultMappingSOP ( const MachineInstr MI) const

◆ getDefaultMappingVOP()

const RegisterBankInfo::InstructionMapping & AMDGPURegisterBankInfo::getDefaultMappingVOP ( const MachineInstr MI) const

◆ getImageMapping()

const RegisterBankInfo::InstructionMapping & AMDGPURegisterBankInfo::getImageMapping ( const MachineRegisterInfo MRI,
const MachineInstr MI,
int  RsrcIdx 
) const

◆ getInstrAlternativeMappings()

RegisterBankInfo::InstructionMappings AMDGPURegisterBankInfo::getInstrAlternativeMappings ( const MachineInstr MI) const
overridevirtual

◆ getInstrAlternativeMappingsIntrinsic()

RegisterBankInfo::InstructionMappings AMDGPURegisterBankInfo::getInstrAlternativeMappingsIntrinsic ( const MachineInstr MI,
const MachineRegisterInfo MRI 
) const

◆ getInstrAlternativeMappingsIntrinsicWSideEffects()

RegisterBankInfo::InstructionMappings AMDGPURegisterBankInfo::getInstrAlternativeMappingsIntrinsicWSideEffects ( const MachineInstr MI,
const MachineRegisterInfo MRI 
) const

◆ getInstrMapping()

const RegisterBankInfo::InstructionMapping & AMDGPURegisterBankInfo::getInstrMapping ( const MachineInstr MI) const
overridevirtual

This function must return a legal mapping, because AMDGPURegisterBankInfo::getInstrAlternativeMappings() is not called in RegBankSelect::Mode::Fast.

Any mapping that would cause a VGPR to SGPR generated is illegal.

Reimplemented from llvm::RegisterBankInfo.

Definition at line 3360 of file AMDGPURegisterBankInfo.cpp.

References assert(), llvm::RegisterBankInfo::ValueMapping::BreakDown, llvm::RegisterBankInfo::cannotCopy(), llvm::numbers::e, E, getAGPROpMapping(), getDefaultMappingAllVGPR(), getDefaultMappingSOP(), getDefaultMappingVOP(), llvm::RegisterBank::getID(), getImageMapping(), getInstrMappingForLoad(), llvm::RegisterBankInfo::getInstrMappingImpl(), llvm::RegisterBankInfo::getInstructionMapping(), llvm::MachineInstr::getIntrinsicID(), llvm::RegisterBankInfo::getInvalidInstructionMapping(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::RegisterBankInfo::getOperandsMapping(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getPredicate(), llvm::MachineOperand::getReg(), llvm::RegisterBankInfo::getRegBank(), getRegBankID(), llvm::MachineFunction::getRegInfo(), getSGPROpMapping(), llvm::LLT::getSizeInBits(), llvm::getSizeInBits(), llvm::MachineRegisterInfo::getType(), llvm::RegisterBankInfo::getValueMapping(), getValueMapping(), getValueMappingForPtr(), getVGPROpMapping(), llvm::GCNSubtarget::hasScalarCompareEq64(), llvm::GCNSubtarget::hasScalarMulHiInsts(), I, llvm::CmpInst::ICMP_EQ, llvm::CmpInst::ICMP_NE, llvm::MachineInstr::isCopy(), llvm::AMDGPU::RsrcIntrinsic::IsImage, llvm::MachineOperand::isReg(), llvm::MachineInstr::isRegSequence(), isSALUMapping(), llvm::RegisterBankInfo::InstructionMapping::isValid(), LLVM_FALLTHROUGH, llvm::AMDGPU::lookupRsrcIntrinsic(), MRI, Reg, llvm::RegisterBankInfo::PartialMapping::RegBank, regBankBoolUnion(), regBankUnion(), llvm::AMDGPU::RsrcIntrinsic::RsrcArg, Size, Subtarget, TRI, and llvm::LLT::vector().

◆ getInstrMappingForLoad()

const RegisterBankInfo::InstructionMapping & AMDGPURegisterBankInfo::getInstrMappingForLoad ( const MachineInstr MI) const

◆ getRegBankFromRegClass()

const RegisterBank & AMDGPURegisterBankInfo::getRegBankFromRegClass ( const TargetRegisterClass RC,
LLT  Ty 
) const
overridevirtual

Get a register bank that covers RC.

Precondition
RC is a user-defined register class (as opposed as one generated by TableGen).
Note
The mapping RC -> RegBank could be built while adding the coverage for the register banks. However, we do not do it, because, at least for now, we only need this information for register classes that are used in the description of instruction. In other words, there are just a handful of them and we do not want to waste space.
Todo:
This should be TableGen'ed.

Reimplemented from llvm::RegisterBankInfo.

Definition at line 275 of file AMDGPURegisterBankInfo.cpp.

References llvm::SIRegisterInfo::isAGPRClass(), llvm::SIRegisterInfo::isSGPRClass(), llvm::LLT::isValid(), llvm::LLT::scalar(), and TRI.

Referenced by shouldUseAndMask().

◆ getRegBankID()

unsigned AMDGPURegisterBankInfo::getRegBankID ( Register  Reg,
const MachineRegisterInfo MRI,
const TargetRegisterInfo TRI,
unsigned  Default = AMDGPU::VGPRRegBankID 
) const

◆ getSGPROpMapping()

const RegisterBankInfo::ValueMapping * AMDGPURegisterBankInfo::getSGPROpMapping ( Register  Reg,
const MachineRegisterInfo MRI,
const TargetRegisterInfo TRI 
) const

Definition at line 3324 of file AMDGPURegisterBankInfo.cpp.

References getRegBankID(), llvm::getSizeInBits(), getValueMapping(), and Size.

Referenced by getInstrMapping().

◆ getValueMappingForPtr()

const RegisterBankInfo::ValueMapping * AMDGPURegisterBankInfo::getValueMappingForPtr ( const MachineRegisterInfo MRI,
Register  Ptr 
) const

◆ getVGPROpMapping()

const RegisterBankInfo::ValueMapping * AMDGPURegisterBankInfo::getVGPROpMapping ( Register  Reg,
const MachineRegisterInfo MRI,
const TargetRegisterInfo TRI 
) const

Definition at line 3335 of file AMDGPURegisterBankInfo.cpp.

References llvm::getSizeInBits(), getValueMapping(), and Size.

Referenced by getInstrMapping().

◆ handleD16VData()

Register AMDGPURegisterBankInfo::handleD16VData ( MachineIRBuilder B,
MachineRegisterInfo MRI,
Register  Reg 
) const

◆ isSALUMapping()

bool AMDGPURegisterBankInfo::isSALUMapping ( const MachineInstr MI) const

◆ lowerScalarMinMax()

void AMDGPURegisterBankInfo::lowerScalarMinMax ( MachineIRBuilder B,
MachineInstr MI 
) const

◆ selectStoreIntrinsic()

MachineInstr * AMDGPURegisterBankInfo::selectStoreIntrinsic ( MachineIRBuilder B,
MachineInstr MI 
) const

◆ split64BitValueForMapping()

void AMDGPURegisterBankInfo::split64BitValueForMapping ( MachineIRBuilder B,
SmallVector< Register, 2 > &  Regs,
LLT  HalfTy,
Register  Reg 
) const

Split 64-bit value Reg into two 32-bit halves and populate them into Regs.

This appropriately sets the regbank of the new registers.

Definition at line 660 of file AMDGPURegisterBankInfo.cpp.

References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addUse(), assert(), llvm::MachineIRBuilder::buildInstr(), llvm::MachineIRBuilder::getMRI(), llvm::RegisterBankInfo::getRegBank(), llvm::LLT::getSizeInBits(), MRI, llvm::SmallVectorTemplateBase< T >::push_back(), and TRI.

Referenced by applyMappingImpl().

◆ splitBufferOffsets()

std::pair< Register, unsigned > AMDGPURegisterBankInfo::splitBufferOffsets ( MachineIRBuilder B,
Register  Offset 
) const

Member Data Documentation

◆ Subtarget

const GCNSubtarget& llvm::AMDGPURegisterBankInfo::Subtarget

◆ TII

const SIInstrInfo* llvm::AMDGPURegisterBankInfo::TII

◆ TRI

const SIRegisterInfo* llvm::AMDGPURegisterBankInfo::TRI

The documentation for this class was generated from the following files: