LLVM 20.0.0git
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#include "Target/AMDGPU/AMDGPURegisterBankInfo.h"
Classes | |
struct | OpRegBankEntry |
Public Attributes | |
const GCNSubtarget & | Subtarget |
const SIRegisterInfo * | TRI |
const SIInstrInfo * | TII |
Additional Inherited Members | |
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using | InstructionMappings = SmallVector< const InstructionMapping *, 4 > |
Convenient type to represent the alternatives for mapping an instruction. | |
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static void | applyDefaultMapping (const OperandsMapper &OpdMapper) |
Helper method to apply something that is like the default mapping. | |
static const TargetRegisterClass * | constrainGenericRegister (Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI) |
Constrain the (possibly generic) virtual register Reg to RC . | |
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static const unsigned | DefaultMappingID = UINT_MAX |
Identifier used when the related instruction mapping instance is generated by target independent code. | |
static const unsigned | InvalidMappingID = UINT_MAX - 1 |
Identifier used when the related instruction mapping instance is generated by the default constructor. | |
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RegisterBankInfo (const RegisterBank **RegBanks, unsigned NumRegBanks, const unsigned *Sizes, unsigned HwMode) | |
Create a RegisterBankInfo that can accommodate up to NumRegBanks RegisterBank instances. | |
RegisterBankInfo () | |
This constructor is meaningless. | |
const RegisterBank & | getRegBank (unsigned ID) |
Get the register bank identified by ID . | |
const TargetRegisterClass * | getMinimalPhysRegClass (Register Reg, const TargetRegisterInfo &TRI) const |
Get the MinimalPhysRegClass for Reg. | |
const InstructionMapping & | getInstrMappingImpl (const MachineInstr &MI) const |
Try to get the mapping of MI . | |
const PartialMapping & | getPartialMapping (unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const |
Get the uniquely generated PartialMapping for the given arguments. | |
const ValueMapping & | getValueMapping (unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const |
The most common ValueMapping consists of a single PartialMapping. | |
const ValueMapping & | getValueMapping (const PartialMapping *BreakDown, unsigned NumBreakDowns) const |
Get the ValueMapping for the given arguments. | |
template<typename Iterator > | |
const ValueMapping * | getOperandsMapping (Iterator Begin, Iterator End) const |
Get the uniquely generated array of ValueMapping for the elements of between Begin and End . | |
const ValueMapping * | getOperandsMapping (const SmallVectorImpl< const ValueMapping * > &OpdsMapping) const |
Get the uniquely generated array of ValueMapping for the elements of OpdsMapping . | |
const ValueMapping * | getOperandsMapping (std::initializer_list< const ValueMapping * > OpdsMapping) const |
Get the uniquely generated array of ValueMapping for the given arguments. | |
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const RegisterBank ** | RegBanks |
Hold the set of supported register banks. | |
unsigned | NumRegBanks |
Total number of register banks. | |
const unsigned * | Sizes |
Hold the sizes of the register banks for all HwModes. | |
unsigned | HwMode |
Current HwMode for the target. | |
DenseMap< hash_code, std::unique_ptr< const PartialMapping > > | MapOfPartialMappings |
Keep dynamically allocated PartialMapping in a separate map. | |
DenseMap< hash_code, std::unique_ptr< const ValueMapping > > | MapOfValueMappings |
Keep dynamically allocated ValueMapping in a separate map. | |
DenseMap< hash_code, std::unique_ptr< ValueMapping[]> > | MapOfOperandsMappings |
Keep dynamically allocated array of ValueMapping in a separate map. | |
DenseMap< hash_code, std::unique_ptr< const InstructionMapping > > | MapOfInstructionMappings |
Keep dynamically allocated InstructionMapping in a separate map. | |
DenseMap< unsigned, const TargetRegisterClass * > | PhysRegMinimalRCs |
Getting the minimal register class of a physreg is expensive. | |
Definition at line 42 of file AMDGPURegisterBankInfo.h.
AMDGPURegisterBankInfo::AMDGPURegisterBankInfo | ( | const GCNSubtarget & | STI | ) |
Definition at line 204 of file AMDGPURegisterBankInfo.cpp.
References assert(), llvm::call_once(), and llvm::RegisterBankInfo::getRegBank().
RegisterBankInfo::InstructionMappings llvm::AMDGPURegisterBankInfo::addMappingFromTable | ( | const MachineInstr & | MI, |
const MachineRegisterInfo & | MRI, | ||
const std::array< unsigned, NumOps > | RegSrcOpIdx, | ||
ArrayRef< OpRegBankEntry< NumOps > > | Table | ||
) | const |
Definition at line 309 of file AMDGPURegisterBankInfo.cpp.
References llvm::RegisterBankInfo::getInstructionMapping(), llvm::RegisterBankInfo::getOperandsMapping(), llvm::RegisterBankInfo::getSizeInBits(), I, MI, MRI, Operands, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::RegisterBankInfo::Sizes, and TRI.
InstructionMappings llvm::AMDGPURegisterBankInfo::addMappingFromTable | ( | const MachineInstr & | MI, |
const MachineRegisterInfo & | MRI, | ||
const std::array< unsigned, NumOps > | RegSrcOpIdx, | ||
ArrayRef< OpRegBankEntry< NumOps > > | Table | ||
) | const |
bool AMDGPURegisterBankInfo::applyMappingBFE | ( | MachineIRBuilder & | B, |
const OperandsMapper & | OpdMapper, | ||
bool | Signed | ||
) | const |
Definition at line 1451 of file AMDGPURegisterBankInfo.cpp.
References llvm::RegisterBankInfo::applyDefaultMapping(), B, llvm::RegisterBankInfo::ValueMapping::BreakDown, llvm::constrainSelectedInstRegOperands(), llvm::getIConstantVRegValWithLookThrough(), llvm::RegisterBankInfo::OperandsMapper::getInstrMapping(), llvm::RegisterBankInfo::OperandsMapper::getMI(), llvm::RegisterBankInfo::OperandsMapper::getMRI(), llvm_unreachable, MI, MRI, llvm::RegisterBankInfo::PartialMapping::RegBank, S32, S64, llvm::LLT::scalar(), Signed, TII, and TRI.
Referenced by applyMappingImpl().
bool AMDGPURegisterBankInfo::applyMappingDynStackAlloc | ( | MachineIRBuilder & | B, |
const OperandsMapper & | OpdMapper, | ||
MachineInstr & | MI | ||
) | const |
Definition at line 1173 of file AMDGPURegisterBankInfo.cpp.
References llvm::assumeAligned(), B, llvm::MachineFunction::getInfo(), llvm::RegisterBankInfo::getRegBank(), llvm::LLT::getSizeInBits(), llvm::MachineFunction::getSubtarget(), Info, llvm::Log2(), MI, MRI, llvm::LLT::scalar(), llvm::TargetFrameLowering::StackGrowsDown, and TRI.
Referenced by applyMappingImpl().
bool AMDGPURegisterBankInfo::applyMappingImage | ( | MachineIRBuilder & | B, |
MachineInstr & | MI, | ||
const OperandsMapper & | OpdMapper, | ||
int | RSrcIdx | ||
) | const |
Definition at line 1220 of file AMDGPURegisterBankInfo.cpp.
References llvm::RegisterBankInfo::applyDefaultMapping(), B, executeInWaterfallLoop(), I, MI, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
Referenced by applyMappingImpl().
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overridevirtual |
See RegisterBankInfo::applyMapping.
Reimplemented from llvm::RegisterBankInfo.
Definition at line 2180 of file AMDGPURegisterBankInfo.cpp.
References llvm::RegisterBankInfo::applyDefaultMapping(), applyMappingBFE(), applyMappingDynStackAlloc(), applyMappingImage(), applyMappingLoad(), applyMappingMAD_64_32(), applyMappingSBufferLoad(), applyMappingSMULU64(), assert(), B, llvm::MachineInstrSpan::begin(), llvm::RegisterBankInfo::ValueMapping::BreakDown, buildVCopy(), llvm::SmallVectorImpl< T >::clear(), collectWaterfallOperands(), llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, constrainOpWithReadfirstlane(), DL, llvm::SmallVectorBase< Size_T >::empty(), llvm::MachineInstrSpan::end(), End, executeInWaterfallLoop(), extendLow32IntoHigh32(), llvm::LLT::fixed_vector(), llvm::AMDGPU::getBaseWithConstantOffset(), getExtendOp(), llvm::MachineBasicBlock::getFirstTerminator(), getHalfSizedType(), llvm::RegisterBank::getID(), llvm::MachineFunction::getInfo(), llvm::RegisterBankInfo::OperandsMapper::getInstrMapping(), llvm::Type::getInt32Ty(), llvm::AMDGPU::getIntrinsicID(), getIntrinsicID(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::RegisterBankInfo::OperandsMapper::getMI(), llvm::RegisterBankInfo::OperandsMapper::getMRI(), llvm::LLT::getNumElements(), llvm::MachineBasicBlock::getParent(), llvm::RegisterBankInfo::getRegBank(), getRegBankID(), llvm::LLT::getSizeInBits(), llvm::RegisterBankInfo::OperandsMapper::getVRegs(), llvm::GCNSubtarget::hasPrefetch(), llvm::GCNSubtarget::hasSALUFloatInsts(), llvm::Hi, I, Idx, Info, llvm::AMDGPU::isFlatGlobalAddrSpace(), llvm::AMDGPU::RsrcIntrinsic::IsImage, llvm::LLT::isScalar(), llvm::LLT::isVector(), llvm::LegalizerHelper::Legalized, llvm_unreachable, llvm::Lo, llvm::AMDGPU::lookupRsrcIntrinsic(), llvm::LegalizerHelper::lowerAbsToMaxNeg(), llvm::make_range(), MBB, MI, MRI, N, llvm::LegalizerHelper::narrowScalar(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::RegisterBankInfo::PartialMapping::RegBank, reinsertVectorIndexAdd(), llvm::SmallVectorImpl< T >::resize(), llvm::reverse(), llvm::AMDGPU::RsrcIntrinsic::RsrcArg, S32, S64, llvm::LLT::scalar(), setRegsToType(), Signed, llvm::SmallVectorBase< Size_T >::size(), llvm::MachineBasicBlock::splice(), split64BitValueForMapping(), substituteSimpleCopyRegs(), Subtarget, TII, TRI, unpackV2S16ToS32(), llvm::LegalizerHelper::widenScalar(), X, and Y.
bool AMDGPURegisterBankInfo::applyMappingLoad | ( | MachineIRBuilder & | B, |
const OperandsMapper & | OpdMapper, | ||
MachineInstr & | MI | ||
) | const |
Definition at line 1054 of file AMDGPURegisterBankInfo.cpp.
References assert(), B, llvm::RegisterBankInfo::ValueMapping::BreakDown, llvm::AMDGPUAS::BUFFER_RESOURCE, llvm::LLT::divide(), llvm::SmallVectorBase< Size_T >::empty(), llvm::LegalizerHelper::fewerElementsVector(), llvm::MachineMemOperand::getAddrSpace(), llvm::MachineMemOperand::getAlign(), llvm::GCNSubtarget::getGeneration(), llvm::RegisterBankInfo::OperandsMapper::getInstrMapping(), llvm::MachineMemOperand::getSize(), llvm::LLT::getSizeInBits(), llvm::LocationSize::getValue(), llvm::RegisterBankInfo::OperandsMapper::getVRegs(), llvm::AMDGPUSubtarget::GFX12, llvm::GCNSubtarget::hasScalarDwordx3Loads(), llvm::AMDGPU::isExtendedGlobalAddrSpace(), llvm::LLT::isScalar(), isScalarLoadLegal(), llvm::LLT::isVector(), llvm::LegalizerHelper::Legalized, MI, MRI, llvm::LegalizerHelper::narrowScalar(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::LegalizerHelper::reduceLoadStoreWidth(), llvm::RegisterBankInfo::PartialMapping::RegBank, S32, llvm::LLT::scalar(), splitUnequalType(), Subtarget, and widen96To128().
Referenced by applyMappingImpl().
bool AMDGPURegisterBankInfo::applyMappingMAD_64_32 | ( | MachineIRBuilder & | B, |
const OperandsMapper & | OpdMapper | ||
) | const |
Definition at line 1557 of file AMDGPURegisterBankInfo.cpp.
References llvm::RegisterBankInfo::applyDefaultMapping(), B, buildReadFirstLane(), llvm::RegisterBankInfo::OperandsMapper::getMI(), llvm::RegisterBankInfo::OperandsMapper::getMRI(), llvm::AMDGPUSubtarget::hasSMulHi(), llvm::CmpInst::ICMP_SLT, llvm::PatternMatch::m_ZeroInt(), MI, llvm::MIPatternMatch::mi_match(), MRI, S1, S32, llvm::LLT::scalar(), and Subtarget.
Referenced by applyMappingImpl().
bool AMDGPURegisterBankInfo::applyMappingSBufferLoad | ( | MachineIRBuilder & | B, |
const OperandsMapper & | OpdMapper | ||
) | const |
Definition at line 1333 of file AMDGPURegisterBankInfo.cpp.
References B, llvm::MachineInstrSpan::begin(), llvm::RegisterBankInfo::ValueMapping::BreakDown, llvm::LLT::divide(), llvm::MachineInstrSpan::end(), executeInWaterfallLoop(), llvm::RegisterBankInfo::OperandsMapper::getInstrMapping(), llvm::MachineFunction::getMachineMemOperand(), llvm::RegisterBankInfo::OperandsMapper::getMI(), llvm::RegisterBankInfo::OperandsMapper::getMRI(), llvm::LLT::getSizeInBits(), llvm::SmallSet< T, N, C >::insert(), llvm::LLT::isVector(), llvm::make_range(), MI, llvm::MachineMemOperand::MODereferenceable, llvm::MachineMemOperand::MOInvariant, llvm::MachineMemOperand::MOLoad, MRI, llvm::RegisterBankInfo::PartialMapping::RegBank, S32, llvm::LLT::scalar(), and setBufferOffsets().
Referenced by applyMappingImpl().
void AMDGPURegisterBankInfo::applyMappingSMULU64 | ( | MachineIRBuilder & | B, |
const OperandsMapper & | OpdMapper | ||
) | const |
Definition at line 2113 of file AMDGPURegisterBankInfo.cpp.
References llvm::Add, llvm::RegisterBankInfo::applyDefaultMapping(), assert(), B, llvm::SmallVectorBase< Size_T >::empty(), llvm::RegisterBankInfo::OperandsMapper::getMI(), llvm::RegisterBankInfo::OperandsMapper::getMRI(), llvm::RegisterBankInfo::OperandsMapper::getVRegs(), llvm::Hi, MI, MRI, llvm::LLT::scalar(), setRegsToType(), llvm::SmallVectorBase< Size_T >::size(), and split64BitValueForMapping().
Referenced by applyMappingImpl().
Register AMDGPURegisterBankInfo::buildReadFirstLane | ( | MachineIRBuilder & | B, |
MachineRegisterInfo & | MRI, | ||
Register | Src | ||
) | const |
Definition at line 703 of file AMDGPURegisterBankInfo.cpp.
References assert(), B, llvm::RegisterBankInfo::constrainGenericRegister(), llvm::RegisterBankInfo::getRegBank(), llvm::LLT::getSizeInBits(), MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), S32, llvm::LLT::scalar(), and TRI.
Referenced by applyMappingMAD_64_32(), constrainOpWithReadfirstlane(), and executeInWaterfallLoop().
bool AMDGPURegisterBankInfo::buildVCopy | ( | MachineIRBuilder & | B, |
Register | DstReg, | ||
Register | SrcReg | ||
) | const |
Definition at line 1845 of file AMDGPURegisterBankInfo.cpp.
References B, llvm::RegisterBankInfo::constrainGenericRegister(), llvm::LLT::getSizeInBits(), and MRI.
Referenced by applyMappingImpl().
bool AMDGPURegisterBankInfo::collectWaterfallOperands | ( | SmallSet< Register, 4 > & | SGPROperandRegs, |
MachineInstr & | MI, | ||
MachineRegisterInfo & | MRI, | ||
ArrayRef< unsigned > | OpIndices | ||
) | const |
Definition at line 985 of file AMDGPURegisterBankInfo.cpp.
References assert(), llvm::SmallSet< T, N, C >::empty(), llvm::RegisterBank::getID(), llvm::RegisterBankInfo::getRegBank(), llvm::SmallSet< T, N, C >::insert(), MI, MRI, and TRI.
Referenced by applyMappingImpl(), and executeInWaterfallLoop().
void AMDGPURegisterBankInfo::constrainOpWithReadfirstlane | ( | MachineIRBuilder & | B, |
MachineInstr & | MI, | ||
unsigned | OpIdx | ||
) | const |
Definition at line 1015 of file AMDGPURegisterBankInfo.cpp.
References B, buildReadFirstLane(), llvm::RegisterBankInfo::getRegBank(), MI, MRI, and TRI.
Referenced by applyMappingImpl().
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overridevirtual |
Get the cost of a copy from B
to A
, or put differently, get the cost of A = COPY B.
Since register banks may cover different size, Size
specifies what will be the size in bits that will be copied around.
Reimplemented from llvm::RegisterBankInfo.
Definition at line 230 of file AMDGPURegisterBankInfo.cpp.
References llvm::RegisterBankInfo::copyCost(), isVectorRegisterBank(), and Size.
bool AMDGPURegisterBankInfo::executeInWaterfallLoop | ( | MachineIRBuilder & | B, |
iterator_range< MachineBasicBlock::iterator > | Range, | ||
SmallSet< Register, 4 > & | SGPROperandRegs | ||
) | const |
Legalize instruction MI
where operands in OpIndices
must be SGPRs.
If any of the required SGPR operands are VGPRs, perform a waterfall loop to execute the instruction for each unique combination of values in all lanes in the wave. The block will be split such that rest of the instructions are moved to a new block.
Essentially performs this loop: Save Execution Mask For (Lane : Wavefront) { Enable Lane, Disable all other lanes SGPR = read SGPR value for current lane from VGPR VGPRResult[Lane] = use_op SGPR } Restore Execution Mask
There is additional complexity to try for compare values to identify the unique values used.
Definition at line 775 of file AMDGPURegisterBankInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), assert(), B, llvm::MachineBasicBlock::begin(), llvm::BuildMI(), buildReadFirstLane(), llvm::SmallSet< T, N, C >::count(), llvm::MachineFunction::CreateMachineBasicBlock(), DL, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::MachineBasicBlock::end(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::RegisterBankInfo::getRegBank(), llvm::LLT::getSizeInBits(), llvm::SIRegisterInfo::getWaveMaskRegClass(), llvm::CmpInst::ICMP_EQ, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::MachineFunction::insert(), llvm::GCNSubtarget::isWave32(), llvm::RegState::Kill, llvm::make_range(), MBB, MBBI, MI, MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), Range, S1, llvm::LLT::scalar(), llvm::MachineBasicBlock::splice(), Subtarget, TII, llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs(), and TRI.
Referenced by applyMappingImage(), applyMappingImpl(), applyMappingSBufferLoad(), and executeInWaterfallLoop().
bool AMDGPURegisterBankInfo::executeInWaterfallLoop | ( | MachineIRBuilder & | B, |
MachineInstr & | MI, | ||
ArrayRef< unsigned > | OpIndices | ||
) | const |
Definition at line 1000 of file AMDGPURegisterBankInfo.cpp.
References B, collectWaterfallOperands(), executeInWaterfallLoop(), I, llvm::make_range(), and MI.
const RegisterBankInfo::ValueMapping * AMDGPURegisterBankInfo::getAGPROpMapping | ( | Register | Reg, |
const MachineRegisterInfo & | MRI, | ||
const TargetRegisterInfo & | TRI | ||
) | const |
Definition at line 3720 of file AMDGPURegisterBankInfo.cpp.
References llvm::RegisterBankInfo::getSizeInBits(), MRI, Size, and TRI.
Referenced by getInstrMapping().
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overridevirtual |
Get the cost of using ValMapping
to decompose a register.
This is similar to copyCost, except for cases where multiple copy-like operations need to be inserted. If the register is used as a source operand and already has a bank assigned, CurBank
is non-null.
Reimplemented from llvm::RegisterBankInfo.
Definition at line 261 of file AMDGPURegisterBankInfo.cpp.
References assert(), llvm::RegisterBankInfo::ValueMapping::BreakDown, llvm::RegisterBankInfo::PartialMapping::Length, llvm::RegisterBankInfo::ValueMapping::NumBreakDowns, llvm::RegisterBankInfo::PartialMapping::RegBank, and llvm::RegisterBankInfo::PartialMapping::StartIdx.
const RegisterBankInfo::InstructionMapping & AMDGPURegisterBankInfo::getDefaultMappingAllVGPR | ( | const MachineInstr & | MI | ) | const |
Definition at line 3568 of file AMDGPURegisterBankInfo.cpp.
References llvm::RegisterBankInfo::getInstructionMapping(), llvm::RegisterBankInfo::getOperandsMapping(), llvm::MachineFunction::getRegInfo(), llvm::RegisterBankInfo::getSizeInBits(), I, MI, MRI, Size, and TRI.
Referenced by getInstrMapping().
const RegisterBankInfo::InstructionMapping & AMDGPURegisterBankInfo::getDefaultMappingSOP | ( | const MachineInstr & | MI | ) | const |
Definition at line 3526 of file AMDGPURegisterBankInfo.cpp.
References llvm::RegisterBankInfo::getInstructionMapping(), llvm::RegisterBankInfo::getOperandsMapping(), llvm::SrcOp::getReg(), llvm::MachineFunction::getRegInfo(), llvm::RegisterBankInfo::getSizeInBits(), MI, MRI, Size, and TRI.
Referenced by getInstrMapping().
const RegisterBankInfo::InstructionMapping & AMDGPURegisterBankInfo::getDefaultMappingVOP | ( | const MachineInstr & | MI | ) | const |
Definition at line 3544 of file AMDGPURegisterBankInfo.cpp.
References llvm::RegisterBankInfo::getInstructionMapping(), llvm::RegisterBankInfo::getOperandsMapping(), llvm::MachineFunction::getRegInfo(), llvm::RegisterBankInfo::getSizeInBits(), MI, MRI, Size, and TRI.
Referenced by getInstrMapping().
const RegisterBankInfo::InstructionMapping & AMDGPURegisterBankInfo::getImageMapping | ( | const MachineRegisterInfo & | MRI, |
const MachineInstr & | MI, | ||
int | RsrcIdx | ||
) | const |
Definition at line 3587 of file AMDGPURegisterBankInfo.cpp.
References llvm::RegisterBankInfo::getInstructionMapping(), llvm::RegisterBankInfo::getOperandsMapping(), getRegBankID(), llvm::RegisterBankInfo::getSizeInBits(), I, MI, MRI, Size, and TRI.
Referenced by getInstrMapping().
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overridevirtual |
Get the alternative mappings for MI
.
Alternative in the sense different from getInstrMapping.
Reimplemented from llvm::RegisterBankInfo.
Definition at line 470 of file AMDGPURegisterBankInfo.cpp.
References assert(), llvm::LLT::getAddressSpace(), llvm::RegisterBankInfo::getInstrAlternativeMappings(), getInstrAlternativeMappingsIntrinsic(), getInstrAlternativeMappingsIntrinsicWSideEffects(), llvm::RegisterBankInfo::getInstructionMapping(), llvm::RegisterBankInfo::getOperandsMapping(), llvm::MachineFunction::getRegInfo(), llvm::LLT::getSizeInBits(), llvm::RegisterBankInfo::getSizeInBits(), isScalarLoadLegal(), llvm::AMDGPUAS::LOCAL_ADDRESS, MI, MRI, llvm::AMDGPUAS::PRIVATE_ADDRESS, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::AMDGPUAS::REGION_ADDRESS, Size, and TRI.
RegisterBankInfo::InstructionMappings AMDGPURegisterBankInfo::getInstrAlternativeMappingsIntrinsic | ( | const MachineInstr & | MI, |
const MachineRegisterInfo & | MRI | ||
) | const |
Definition at line 346 of file AMDGPURegisterBankInfo.cpp.
References llvm::RegisterBankInfo::getInstrAlternativeMappings(), getIntrinsicID(), MI, and MRI.
Referenced by getInstrAlternativeMappings().
RegisterBankInfo::InstructionMappings AMDGPURegisterBankInfo::getInstrAlternativeMappingsIntrinsicWSideEffects | ( | const MachineInstr & | MI, |
const MachineRegisterInfo & | MRI | ||
) | const |
Definition at line 386 of file AMDGPURegisterBankInfo.cpp.
References llvm::RegisterBankInfo::getInstrAlternativeMappings(), getIntrinsicID(), MI, and MRI.
Referenced by getInstrAlternativeMappings().
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overridevirtual |
This function must return a legal mapping, because AMDGPURegisterBankInfo::getInstrAlternativeMappings() is not called in RegBankSelect::Mode::Fast.
Any mapping that would cause a VGPR to SGPR generated is illegal.
Reimplemented from llvm::RegisterBankInfo.
Definition at line 3737 of file AMDGPURegisterBankInfo.cpp.
References assert(), llvm::RegisterBankInfo::cannotCopy(), llvm::LLT::fixed_vector(), getAGPROpMapping(), getDefaultMappingAllVGPR(), getDefaultMappingSOP(), getDefaultMappingVOP(), llvm::TypeSize::getFixed(), llvm::RegisterBank::getID(), getImageMapping(), llvm::MachineFunction::getInfo(), getInstrMappingForLoad(), llvm::RegisterBankInfo::getInstrMappingImpl(), llvm::RegisterBankInfo::getInstructionMapping(), llvm::AMDGPU::getIntrinsicID(), getIntrinsicID(), llvm::RegisterBankInfo::getInvalidInstructionMapping(), getMappingType(), llvm::RegisterBankInfo::getOperandsMapping(), llvm::RegisterBankInfo::getRegBank(), getRegBankID(), llvm::MachineFunction::getRegInfo(), getSGPROpMapping(), llvm::LLT::getSizeInBits(), llvm::RegisterBankInfo::getSizeInBits(), llvm::RegisterBankInfo::getValueMapping(), getValueMappingForPtr(), getVGPROpMapping(), llvm::GCNSubtarget::hasFullRate64Ops(), llvm::GCNSubtarget::hasPseudoScalarTrans(), llvm::GCNSubtarget::hasSALUFloatInsts(), llvm::GCNSubtarget::hasScalarCompareEq64(), llvm::GCNSubtarget::hasScalarMulHiInsts(), I, llvm::CmpInst::ICMP_EQ, llvm::CmpInst::ICMP_NE, Info, llvm::AMDGPU::RsrcIntrinsic::IsImage, isReg(), isSALUMapping(), llvm::LLT::isScalar(), llvm::RegisterBankInfo::InstructionMapping::isValid(), llvm::Register::isVirtual(), llvm::AMDGPU::lookupRsrcIntrinsic(), MI, MRI, N, PHI, regBankBoolUnion(), regBankUnion(), llvm::AMDGPU::RsrcIntrinsic::RsrcArg, llvm::LLT::scalar(), Size, Subtarget, and TRI.
const RegisterBankInfo::InstructionMapping & AMDGPURegisterBankInfo::getInstrMappingForLoad | ( | const MachineInstr & | MI | ) | const |
Definition at line 3646 of file AMDGPURegisterBankInfo.cpp.
References llvm::LLT::getAddressSpace(), llvm::RegisterBankInfo::getInstructionMapping(), llvm::RegisterBankInfo::getOperandsMapping(), llvm::RegisterBankInfo::getRegBank(), llvm::MachineFunction::getRegInfo(), llvm::LLT::getSizeInBits(), llvm::RegisterBankInfo::getSizeInBits(), llvm::AMDGPU::isFlatGlobalAddrSpace(), isScalarLoadLegal(), MI, MRI, Size, Subtarget, TRI, and llvm::GCNSubtarget::useFlatForGlobal().
Referenced by getInstrMapping().
unsigned AMDGPURegisterBankInfo::getMappingType | ( | const MachineRegisterInfo & | MRI, |
const MachineInstr & | MI | ||
) | const |
Definition at line 3492 of file AMDGPURegisterBankInfo.cpp.
References llvm::RegisterBankInfo::getRegBank(), MI, MRI, regBankUnion(), and TRI.
Referenced by getInstrMapping().
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overridevirtual |
Get a register bank that covers RC
.
RC
is a user-defined register class (as opposed as one generated by TableGen).Reimplemented from llvm::RegisterBankInfo.
Definition at line 287 of file AMDGPURegisterBankInfo.cpp.
References llvm::SIRegisterInfo::isAGPRClass(), llvm::SIRegisterInfo::isSGPRClass(), llvm::LLT::isValid(), llvm::LLT::scalar(), and TRI.
unsigned AMDGPURegisterBankInfo::getRegBankID | ( | Register | Reg, |
const MachineRegisterInfo & | MRI, | ||
unsigned | Default = AMDGPU::VGPRRegBankID |
||
) | const |
Definition at line 3693 of file AMDGPURegisterBankInfo.cpp.
References llvm::Default, llvm::RegisterBank::getID(), llvm::RegisterBankInfo::getRegBank(), MRI, and TRI.
Referenced by applyMappingImpl(), getImageMapping(), getInstrMapping(), and getSGPROpMapping().
const RegisterBankInfo::ValueMapping * AMDGPURegisterBankInfo::getSGPROpMapping | ( | Register | Reg, |
const MachineRegisterInfo & | MRI, | ||
const TargetRegisterInfo & | TRI | ||
) | const |
Definition at line 3701 of file AMDGPURegisterBankInfo.cpp.
References getRegBankID(), llvm::RegisterBankInfo::getSizeInBits(), MRI, Size, and TRI.
Referenced by getInstrMapping().
const RegisterBankInfo::ValueMapping * AMDGPURegisterBankInfo::getValueMappingForPtr | ( | const MachineRegisterInfo & | MRI, |
Register | Ptr | ||
) | const |
Return the mapping for a pointer argument.
Definition at line 3631 of file AMDGPURegisterBankInfo.cpp.
References llvm::LLT::getAddressSpace(), llvm::RegisterBank::getID(), llvm::RegisterBankInfo::getRegBank(), llvm::LLT::getSizeInBits(), llvm::AMDGPU::isFlatGlobalAddrSpace(), MRI, Size, Subtarget, TRI, and llvm::GCNSubtarget::useFlatForGlobal().
Referenced by getInstrMapping().
const RegisterBankInfo::ValueMapping * AMDGPURegisterBankInfo::getVGPROpMapping | ( | Register | Reg, |
const MachineRegisterInfo & | MRI, | ||
const TargetRegisterInfo & | TRI | ||
) | const |
Definition at line 3712 of file AMDGPURegisterBankInfo.cpp.
References llvm::RegisterBankInfo::getSizeInBits(), MRI, Size, and TRI.
Referenced by getInstrMapping().
Register AMDGPURegisterBankInfo::handleD16VData | ( | MachineIRBuilder & | B, |
MachineRegisterInfo & | MRI, | ||
Register | Reg | ||
) | const |
Handle register layout difference for f16 images for some subtargets.
Definition at line 1760 of file AMDGPURegisterBankInfo.cpp.
References B, llvm::LLT::fixed_vector(), llvm::LLT::getElementType(), llvm::LLT::getNumElements(), llvm::GCNSubtarget::hasUnpackedD16VMem(), I, llvm::LLT::isVector(), MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), S16, S32, llvm::LLT::scalar(), and Subtarget.
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overridevirtual |
Returns true if the register bank is considered divergent.
Reimplemented from llvm::RegisterBankInfo.
Definition at line 226 of file AMDGPURegisterBankInfo.cpp.
bool AMDGPURegisterBankInfo::isSALUMapping | ( | const MachineInstr & | MI | ) | const |
Definition at line 3510 of file AMDGPURegisterBankInfo.cpp.
References llvm::RegisterBankInfo::getRegBank(), llvm::MachineFunction::getRegInfo(), MI, MRI, and TRI.
Referenced by getInstrMapping().
bool AMDGPURegisterBankInfo::isScalarLoadLegal | ( | const MachineInstr & | MI | ) | const |
Definition at line 444 of file AMDGPURegisterBankInfo.cpp.
References llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::MachineMemOperand::getAddrSpace(), llvm::MachineMemOperand::getAlign(), llvm::MachineMemOperand::getFlags(), llvm::MachineMemOperand::getSize(), llvm::LocationSize::getValue(), llvm::GCNSubtarget::hasScalarSubwordLoads(), llvm::MachineMemOperand::isAtomic(), llvm::MachineMemOperand::isInvariant(), llvm::AMDGPUInstrInfo::isUniformMMO(), llvm::MachineMemOperand::isVolatile(), MI, llvm::MONoClobber, and Subtarget.
Referenced by applyMappingLoad(), getInstrAlternativeMappings(), and getInstrMappingForLoad().
unsigned AMDGPURegisterBankInfo::setBufferOffsets | ( | MachineIRBuilder & | B, |
Register | CombinedOffset, | ||
Register & | VOffsetReg, | ||
Register & | SOffsetReg, | ||
int64_t & | InstOffsetVal, | ||
Align | Alignment | ||
) | const |
Definition at line 1250 of file AMDGPURegisterBankInfo.cpp.
References llvm::Add, B, llvm::sampleprof::Base, llvm::AMDGPU::getBaseWithConstantOffset(), llvm::getIConstantVRegSExtVal(), llvm::getOpcodeDef(), llvm::RegisterBankInfo::getRegBank(), llvm::getSrcRegIgnoringCopies(), MRI, llvm::Offset, S32, llvm::LLT::scalar(), llvm::SIInstrInfo::splitMUBUFOffset(), TII, and TRI.
Referenced by applyMappingSBufferLoad().
void AMDGPURegisterBankInfo::split64BitValueForMapping | ( | MachineIRBuilder & | B, |
SmallVector< Register, 2 > & | Regs, | ||
LLT | HalfTy, | ||
Register | Reg | ||
) | const |
Split 64-bit value Reg
into two 32-bit halves and populate them into Regs
.
This appropriately sets the regbank of the new registers.
Definition at line 659 of file AMDGPURegisterBankInfo.cpp.
References assert(), B, llvm::RegisterBankInfo::getRegBank(), llvm::LLT::getSizeInBits(), MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TRI.
Referenced by applyMappingImpl(), and applyMappingSMULU64().
std::pair< Register, unsigned > AMDGPURegisterBankInfo::splitBufferOffsets | ( | MachineIRBuilder & | B, |
Register | Offset | ||
) | const |
Definition at line 1800 of file AMDGPURegisterBankInfo.cpp.
References B, getBaseWithConstantOffset(), llvm::SIInstrInfo::getMaxMUBUFImmOffset(), S32, llvm::LLT::scalar(), and Subtarget.
const GCNSubtarget& llvm::AMDGPURegisterBankInfo::Subtarget |
Definition at line 44 of file AMDGPURegisterBankInfo.h.
Referenced by applyMappingImpl(), applyMappingLoad(), applyMappingMAD_64_32(), executeInWaterfallLoop(), getInstrMapping(), getInstrMappingForLoad(), getValueMappingForPtr(), handleD16VData(), isScalarLoadLegal(), and splitBufferOffsets().
const SIInstrInfo* llvm::AMDGPURegisterBankInfo::TII |
Definition at line 46 of file AMDGPURegisterBankInfo.h.
Referenced by applyMappingBFE(), applyMappingImpl(), executeInWaterfallLoop(), and setBufferOffsets().
const SIRegisterInfo* llvm::AMDGPURegisterBankInfo::TRI |
Definition at line 45 of file AMDGPURegisterBankInfo.h.
Referenced by addMappingFromTable(), applyMappingBFE(), applyMappingDynStackAlloc(), applyMappingImpl(), buildReadFirstLane(), collectWaterfallOperands(), constrainOpWithReadfirstlane(), executeInWaterfallLoop(), getAGPROpMapping(), getDefaultMappingAllVGPR(), getDefaultMappingSOP(), getDefaultMappingVOP(), getImageMapping(), getInstrAlternativeMappings(), getInstrMapping(), getInstrMappingForLoad(), getMappingType(), getRegBankFromRegClass(), getRegBankID(), getSGPROpMapping(), getValueMappingForPtr(), getVGPROpMapping(), isSALUMapping(), setBufferOffsets(), and split64BitValueForMapping().