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14 #ifndef LLVM_CODEGEN_REGISTERBANKINFO_H
15 #define LLVM_CODEGEN_REGISTERBANKINFO_H
25 #include <initializer_list>
31 class MachineRegisterInfo;
34 class TargetInstrInfo;
35 class TargetRegisterClass;
36 class TargetRegisterInfo;
178 bool verify(
unsigned MeaningfulBitWidth)
const;
202 unsigned NumOperands = 0;
206 return OperandsMapping[
i];
218 unsigned NumOperands)
219 :
ID(
ID), Cost(Cost), OperandsMapping(OperandsMapping),
220 NumOperands(NumOperands) {}
248 OperandsMapping = OpdsMapping;
299 static const int DontKnowIdx;
308 getVRegsMem(
unsigned OpIdx);
314 getNewVRegsEnd(
unsigned StartIdx,
unsigned NumVal)
const;
376 getVRegs(
unsigned OpIdx,
bool ForDebug =
false)
const;
470 const ValueMapping &
getValueMapping(
unsigned StartIdx,
unsigned Length,
475 unsigned NumBreakDowns)
const;
491 template <
typename Iterator>
508 std::initializer_list<const ValueMapping *> OpdsMapping)
const;
516 const InstructionMapping &
519 const ValueMapping *OperandsMapping =
nullptr,
520 unsigned NumOperands = 0)
const;
524 const InstructionMapping &
527 unsigned NumOperands)
const {
528 return getInstructionMappingImpl(
false,
ID, Cost,
529 OperandsMapping, NumOperands);
534 return getInstructionMappingImpl(
true);
614 unsigned Size)
const {
624 unsigned Size)
const {
746 PartMapping.
print(OS);
752 ValMapping.
print(OS);
759 InstrMapping.
print(OS);
765 OpdMapper.
print(OS,
false);
771 hash_code
hash_value(
const RegisterBankInfo::PartialMapping &PartMapping);
775 #endif // LLVM_CODEGEN_REGISTERBANKINFO_H
This is an optimization pass for GlobalISel generic memory operations.
void dump() const
Print this on dbgs() stream.
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
unsigned getHighBitIdx() const
bool verify(const TargetRegisterInfo &TRI) const
Check that information hold by this instance make sense for the given TRI.
MachineRegisterInfo & getMRI() const
The MachineRegisterInfo we used to realize the mapping.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
bool verify(const MachineInstr &MI) const
Verifiy that this mapping makes sense for MI.
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
Reg
All possible values of the reg field in the ModR/M byte.
static void applyDefaultMapping(const OperandsMapper &OpdMapper)
Helper method to apply something that is like the default mapping.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isValid() const
Check if this ValueMapping is valid.
const InstructionMapping & getInstrMapping() const
The final mapping of the instruction.
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
bool isValid() const
Check whether this object is valid.
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
DenseMap< unsigned, const TargetRegisterClass * > PhysRegMinimalRCs
Getting the minimal register class of a physreg is expensive.
unsigned const TargetRegisterInfo * TRI
const ValueMapping & getValueMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
The most common ValueMapping consists of a single PartialMapping.
bool verify(unsigned MeaningfulBitWidth) const
Verify that this mapping makes sense for a value of MeaningfulBitWidth.
const PartialMapping * BreakDown
How the value is broken down between the different register banks.
unsigned getID() const
Get the ID.
bool partsAllUniform() const
InstructionMapping()=default
Default constructor.
virtual unsigned getBreakDownCost(const ValueMapping &ValMapping, const RegisterBank *CurBank=nullptr) const
Get the cost of using ValMapping to decompose a register.
DenseMap< unsigned, std::unique_ptr< const ValueMapping > > MapOfValueMappings
Keep dynamically allocated ValueMapping in a separate map.
TargetInstrInfo - Interface to description of machine instruction set.
This class implements the register bank concept.
bool verify() const
Check that the Mask is compatible with the RegBank.
DenseMap< unsigned, std::unique_ptr< const InstructionMapping > > MapOfInstructionMappings
Keep dynamically allocated InstructionMapping in a separate map.
void applyMapping(const OperandsMapper &OpdMapper) const
Apply OpdMapper.getInstrMapping() to OpdMapper.getMI().
Helper struct that represents how a value is partially mapped into a register.
InstructionMappings getInstrPossibleMappings(const MachineInstr &MI) const
Get the possible mapping for MI.
const HexagonInstrInfo * TII
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static const unsigned InvalidMappingID
Identifier used when the related instruction mapping instance is generated by the default constructor...
void dump() const
Print this partial mapping on dbgs() stream.
DenseMap< unsigned, std::unique_ptr< const PartialMapping > > MapOfPartialMappings
Keep dynamically allocated PartialMapping in a separate map.
void print(raw_ostream &OS, bool ForDebug=false) const
Print this operands mapper on OS stream.
InstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands)
Constructor for the mapping of an instruction.
ValueMapping(const PartialMapping *BreakDown, unsigned NumBreakDowns)
Initialize a ValueMapping with the given parameter.
This class implements an extremely fast bulk output stream that can only output to a stream.
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
unsigned NumRegBanks
Total number of register banks.
RegisterBank ** RegBanks
Hold the set of supported register banks.
void setOperandsMapping(const ValueMapping *OpdsMapping)
Set the mapping for all the operands.
void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, Register NewVReg)
Set the virtual register of the PartialMapIdx-th partial mapping of the OpIdx-th operand to NewVReg.
void dump() const
Print this on dbgs() stream.
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
static const TargetRegisterClass * constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
void dump() const
Print this operands mapper on dbgs() stream.
void print(raw_ostream &OS) const
Print this on OS;.
virtual ~RegisterBankInfo()=default
unsigned StartIdx
Number of bits at which this partial mapping starts in the original value.
unsigned getNumRegBanks() const
Get the total number of register banks.
Holds all the information related to register banks.
PartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank)
Provide a shortcut for quickly building PartialMapping.
iterator_range< SmallVectorImpl< Register >::const_iterator > getVRegs(unsigned OpIdx, bool ForDebug=false) const
Get all the virtual registers required to map the OpIdx-th operand of the instruction.
Representation of each machine instruction.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
unsigned getNumOperands() const
Get the number of operands.
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
bool cannotCopy(const RegisterBank &Dst, const RegisterBank &Src, unsigned Size) const
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
RegisterBankInfo()
This constructor is meaningless.
typename SuperClass::const_iterator const_iterator
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ValueMapping()
The default constructor creates an invalid (isValid() == false) instance.
const PartialMapping * end() const
MachineInstr & getMI() const
unsigned getCost() const
Get the cost.
const RegisterBank * RegBank
Register bank where the partial value lives.
void createVRegs(unsigned OpIdx)
Create as many new virtual registers as needed for the mapping of the OpIdx-th operand.
const PartialMapping & getPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
Get the uniquely generated PartialMapping for the given arguments.
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
Helper struct that represents how a value is mapped through different register banks.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const ValueMapping & getOperandMapping(unsigned i) const
Get the value mapping of the ith operand.
void print(raw_ostream &OS) const
Print this on OS;.
unsigned Length
Length of this mapping in bits.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
virtual const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const
Get a register bank that covers RC.
const RegisterBank & getRegBank(unsigned ID) const
Get the register bank identified by ID.
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, unsigned Size) const
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
virtual const InstructionMapping & getInstrMapping(const MachineInstr &MI) const
Get the mapping of the different operands of MI on the register bank.
const PartialMapping * begin() const
Iterators through the PartialMappings.
OperandsMapper(MachineInstr &MI, const InstructionMapping &InstrMapping, MachineRegisterInfo &MRI)
Create an OperandsMapper that will hold the information to apply InstrMapping to MI.
const RegisterBank * getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const MachineRegisterInfo &MRI) const
Get the register bank for the OpIdx-th operand of MI form the encoding constraints,...
unsigned NumBreakDowns
Number of partial mapping to break down this value.
typename SuperClass::iterator iterator
A range adaptor for a pair of iterators.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void print(raw_ostream &OS) const
Print this partial mapping on OS;.
const TargetRegisterClass & getMinimalPhysRegClass(Register Reg, const TargetRegisterInfo &TRI) const
Get the MinimalPhysRegClass for Reg.
DenseMap< unsigned, std::unique_ptr< ValueMapping[]> > MapOfOperandsMappings
Keep dynamically allocated array of ValueMapping in a separate map.
virtual void applyMappingImpl(const OperandsMapper &OpdMapper) const
See ::applyMapping.