LLVM 20.0.0git
RegisterBankInfo.h
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1//===- llvm/CodeGen/RegisterBankInfo.h --------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file This file declares the API for the register bank info.
10/// This API is responsible for handling the register banks.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_REGISTERBANKINFO_H
15#define LLVM_CODEGEN_REGISTERBANKINFO_H
16
17#include "llvm/ADT/DenseMap.h"
18#include "llvm/ADT/Hashing.h"
25#include <cassert>
26#include <initializer_list>
27#include <memory>
28
29namespace llvm {
30
31class MachineInstr;
32class MachineIRBuilder;
33class MachineRegisterInfo;
34class raw_ostream;
35class TargetInstrInfo;
36class TargetRegisterClass;
37class TargetRegisterInfo;
38
39/// Holds all the information related to register banks.
41public:
42 /// Helper struct that represents how a value is partially mapped
43 /// into a register.
44 /// The StartIdx and Length represent what region of the orginal
45 /// value this partial mapping covers.
46 /// This can be represented as a Mask of contiguous bit starting
47 /// at StartIdx bit and spanning Length bits.
48 /// StartIdx is the number of bits from the less significant bits.
50 /// Number of bits at which this partial mapping starts in the
51 /// original value. The bits are counted from less significant
52 /// bits to most significant bits.
53 unsigned StartIdx;
54
55 /// Length of this mapping in bits. This is how many bits this
56 /// partial mapping covers in the original value:
57 /// from StartIdx to StartIdx + Length -1.
58 unsigned Length;
59
60 /// Register bank where the partial value lives.
62
63 PartialMapping() = default;
64
65 /// Provide a shortcut for quickly building PartialMapping.
66 constexpr PartialMapping(unsigned StartIdx, unsigned Length,
67 const RegisterBank &RegBank)
69
70 /// \return the index of in the original value of the most
71 /// significant bit that this partial mapping covers.
72 unsigned getHighBitIdx() const { return StartIdx + Length - 1; }
73
74 /// Print this partial mapping on dbgs() stream.
75 void dump() const;
76
77 /// Print this partial mapping on \p OS;
78 void print(raw_ostream &OS) const;
79
80 /// Check that the Mask is compatible with the RegBank.
81 /// Indeed, if the RegBank cannot accomadate the "active bits" of the mask,
82 /// there is no way this mapping is valid.
83 ///
84 /// \note This method does not check anything when assertions are disabled.
85 ///
86 /// \return True is the check was successful.
87 bool verify(const RegisterBankInfo &RBI) const;
88 };
89
90 /// Helper struct that represents how a value is mapped through
91 /// different register banks.
92 ///
93 /// \note: So far we do not have any users of the complex mappings
94 /// (mappings with more than one partial mapping), but when we do,
95 /// we would have needed to duplicate partial mappings.
96 /// The alternative could be to use an array of pointers of partial
97 /// mapping (i.e., PartialMapping **BreakDown) and duplicate the
98 /// pointers instead.
99 ///
100 /// E.g.,
101 /// Let say we have a 32-bit add and a <2 x 32-bit> vadd. We
102 /// can expand the
103 /// <2 x 32-bit> add into 2 x 32-bit add.
104 ///
105 /// Currently the TableGen-like file would look like:
106 /// \code
107 /// PartialMapping[] = {
108 /// /*32-bit add*/ {0, 32, GPR}, // Scalar entry repeated for first
109 /// // vec elt.
110 /// /*2x32-bit add*/ {0, 32, GPR}, {32, 32, GPR},
111 /// /*<2x32-bit> vadd*/ {0, 64, VPR}
112 /// }; // PartialMapping duplicated.
113 ///
114 /// ValueMapping[] {
115 /// /*plain 32-bit add*/ {&PartialMapping[0], 1},
116 /// /*expanded vadd on 2xadd*/ {&PartialMapping[1], 2},
117 /// /*plain <2x32-bit> vadd*/ {&PartialMapping[3], 1}
118 /// };
119 /// \endcode
120 ///
121 /// With the array of pointer, we would have:
122 /// \code
123 /// PartialMapping[] = {
124 /// /*32-bit add lower */ { 0, 32, GPR},
125 /// /*32-bit add upper */ {32, 32, GPR},
126 /// /*<2x32-bit> vadd */ { 0, 64, VPR}
127 /// }; // No more duplication.
128 ///
129 /// BreakDowns[] = {
130 /// /*AddBreakDown*/ &PartialMapping[0],
131 /// /*2xAddBreakDown*/ &PartialMapping[0], &PartialMapping[1],
132 /// /*VAddBreakDown*/ &PartialMapping[2]
133 /// }; // Addresses of PartialMapping duplicated (smaller).
134 ///
135 /// ValueMapping[] {
136 /// /*plain 32-bit add*/ {&BreakDowns[0], 1},
137 /// /*expanded vadd on 2xadd*/ {&BreakDowns[1], 2},
138 /// /*plain <2x32-bit> vadd*/ {&BreakDowns[3], 1}
139 /// };
140 /// \endcode
141 ///
142 /// Given that a PartialMapping is actually small, the code size
143 /// impact is actually a degradation. Moreover the compile time will
144 /// be hit by the additional indirection.
145 /// If PartialMapping gets bigger we may reconsider.
147 /// How the value is broken down between the different register banks.
149
150 /// Number of partial mapping to break down this value.
152
153 /// The default constructor creates an invalid (isValid() == false)
154 /// instance.
155 ValueMapping() : ValueMapping(nullptr, 0) {}
156
157 /// Initialize a ValueMapping with the given parameter.
158 /// \p BreakDown needs to have a life time at least as long
159 /// as this instance.
161 unsigned NumBreakDowns)
163
164 /// Iterators through the PartialMappings.
165 const PartialMapping *begin() const { return BreakDown; }
166 const PartialMapping *end() const { return BreakDown + NumBreakDowns; }
167
168 /// \return true if all partial mappings are the same size and register
169 /// bank.
170 bool partsAllUniform() const;
171
172 /// Check if this ValueMapping is valid.
173 bool isValid() const { return BreakDown && NumBreakDowns; }
174
175 /// Verify that this mapping makes sense for a value of
176 /// \p MeaningfulBitWidth.
177 /// \note This method does not check anything when assertions are disabled.
178 ///
179 /// \return True is the check was successful.
180 bool verify(const RegisterBankInfo &RBI, TypeSize MeaningfulBitWidth) const;
181
182 /// Print this on dbgs() stream.
183 void dump() const;
184
185 /// Print this on \p OS;
186 void print(raw_ostream &OS) const;
187 };
188
189 /// Helper class that represents how the value of an instruction may be
190 /// mapped and what is the related cost of such mapping.
192 /// Identifier of the mapping.
193 /// This is used to communicate between the target and the optimizers
194 /// which mapping should be realized.
195 unsigned ID = InvalidMappingID;
196
197 /// Cost of this mapping.
198 unsigned Cost = 0;
199
200 /// Mapping of all the operands.
201 const ValueMapping *OperandsMapping = nullptr;
202
203 /// Number of operands.
204 unsigned NumOperands = 0;
205
206 const ValueMapping &getOperandMapping(unsigned i) {
207 assert(i < getNumOperands() && "Out of bound operand");
208 return OperandsMapping[i];
209 }
210
211 public:
212 /// Constructor for the mapping of an instruction.
213 /// \p NumOperands must be equal to number of all the operands of
214 /// the related instruction.
215 /// The rationale is that it is more efficient for the optimizers
216 /// to be able to assume that the mapping of the ith operand is
217 /// at the index i.
218 InstructionMapping(unsigned ID, unsigned Cost,
219 const ValueMapping *OperandsMapping,
220 unsigned NumOperands)
221 : ID(ID), Cost(Cost), OperandsMapping(OperandsMapping),
222 NumOperands(NumOperands) {}
223
224 /// Default constructor.
225 /// Use this constructor to express that the mapping is invalid.
227
228 /// Get the cost.
229 unsigned getCost() const { return Cost; }
230
231 /// Get the ID.
232 unsigned getID() const { return ID; }
233
234 /// Get the number of operands.
235 unsigned getNumOperands() const { return NumOperands; }
236
237 /// Get the value mapping of the ith operand.
238 /// \pre The mapping for the ith operand has been set.
239 /// \pre The ith operand is a register.
240 const ValueMapping &getOperandMapping(unsigned i) const {
241 const ValueMapping &ValMapping =
242 const_cast<InstructionMapping *>(this)->getOperandMapping(i);
243 return ValMapping;
244 }
245
246 /// Set the mapping for all the operands.
247 /// In other words, OpdsMapping should hold at least getNumOperands
248 /// ValueMapping.
249 void setOperandsMapping(const ValueMapping *OpdsMapping) {
250 OperandsMapping = OpdsMapping;
251 }
252
253 /// Check whether this object is valid.
254 /// This is a lightweight check for obvious wrong instance.
255 bool isValid() const {
256 return getID() != InvalidMappingID && OperandsMapping;
257 }
258
259 /// Verifiy that this mapping makes sense for \p MI.
260 /// \pre \p MI must be connected to a MachineFunction.
261 ///
262 /// \note This method does not check anything when assertions are disabled.
263 ///
264 /// \return True is the check was successful.
265 bool verify(const MachineInstr &MI) const;
266
267 /// Print this on dbgs() stream.
268 void dump() const;
269
270 /// Print this on \p OS;
271 void print(raw_ostream &OS) const;
272 };
273
274 /// Convenient type to represent the alternatives for mapping an
275 /// instruction.
276 /// \todo When we move to TableGen this should be an array ref.
278
279 /// Helper class used to get/create the virtual registers that will be used
280 /// to replace the MachineOperand when applying a mapping.
282 /// The OpIdx-th cell contains the index in NewVRegs where the VRegs of the
283 /// OpIdx-th operand starts. -1 means we do not have such mapping yet.
284 /// Note: We use a SmallVector to avoid heap allocation for most cases.
285 SmallVector<int, 8> OpToNewVRegIdx;
286
287 /// Hold the registers that will be used to map MI with InstrMapping.
289
290 /// Current MachineRegisterInfo, used to create new virtual registers.
292
293 /// Instruction being remapped.
294 MachineInstr &MI;
295
296 /// New mapping of the instruction.
297 const InstructionMapping &InstrMapping;
298
299 /// Constant value identifying that the index in OpToNewVRegIdx
300 /// for an operand has not been set yet.
301 static const int DontKnowIdx;
302
303 /// Get the range in NewVRegs to store all the partial
304 /// values for the \p OpIdx-th operand.
305 ///
306 /// \return The iterator range for the space created.
307 //
308 /// \pre getMI().getOperand(OpIdx).isReg()
310 getVRegsMem(unsigned OpIdx);
311
312 /// Get the end iterator for a range starting at \p StartIdx and
313 /// spannig \p NumVal in NewVRegs.
314 /// \pre StartIdx + NumVal <= NewVRegs.size()
316 getNewVRegsEnd(unsigned StartIdx, unsigned NumVal) const;
317 SmallVectorImpl<Register>::iterator getNewVRegsEnd(unsigned StartIdx,
318 unsigned NumVal);
319
320 public:
321 /// Create an OperandsMapper that will hold the information to apply \p
322 /// InstrMapping to \p MI.
323 /// \pre InstrMapping.verify(MI)
324 OperandsMapper(MachineInstr &MI, const InstructionMapping &InstrMapping,
326
327 /// \name Getters.
328 /// @{
329 /// The MachineInstr being remapped.
330 MachineInstr &getMI() const { return MI; }
331
332 /// The final mapping of the instruction.
333 const InstructionMapping &getInstrMapping() const { return InstrMapping; }
334
335 /// The MachineRegisterInfo we used to realize the mapping.
336 MachineRegisterInfo &getMRI() const { return MRI; }
337 /// @}
338
339 /// Create as many new virtual registers as needed for the mapping of the \p
340 /// OpIdx-th operand.
341 /// The number of registers is determined by the number of breakdown for the
342 /// related operand in the instruction mapping.
343 /// The type of the new registers is a plain scalar of the right size.
344 /// The proper type is expected to be set when the mapping is applied to
345 /// the instruction(s) that realizes the mapping.
346 ///
347 /// \pre getMI().getOperand(OpIdx).isReg()
348 ///
349 /// \post All the partial mapping of the \p OpIdx-th operand have been
350 /// assigned a new virtual register.
351 void createVRegs(unsigned OpIdx);
352
353 /// Set the virtual register of the \p PartialMapIdx-th partial mapping of
354 /// the OpIdx-th operand to \p NewVReg.
355 ///
356 /// \pre getMI().getOperand(OpIdx).isReg()
357 /// \pre getInstrMapping().getOperandMapping(OpIdx).BreakDown.size() >
358 /// PartialMapIdx
359 /// \pre NewReg != 0
360 ///
361 /// \post the \p PartialMapIdx-th register of the value mapping of the \p
362 /// OpIdx-th operand has been set.
363 void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, Register NewVReg);
364
365 /// Get all the virtual registers required to map the \p OpIdx-th operand of
366 /// the instruction.
367 ///
368 /// This return an empty range when createVRegs or setVRegs has not been
369 /// called.
370 /// The iterator may be invalidated by a call to setVRegs or createVRegs.
371 ///
372 /// When \p ForDebug is true, we will not check that the list of new virtual
373 /// registers does not contain uninitialized values.
374 ///
375 /// \pre getMI().getOperand(OpIdx).isReg()
376 /// \pre ForDebug || All partial mappings have been set a register
378 getVRegs(unsigned OpIdx, bool ForDebug = false) const;
379
380 /// Print this operands mapper on dbgs() stream.
381 void dump() const;
382
383 /// Print this operands mapper on \p OS stream.
384 void print(raw_ostream &OS, bool ForDebug = false) const;
385 };
386
387protected:
388 /// Hold the set of supported register banks.
390
391 /// Total number of register banks.
392 unsigned NumRegBanks;
393
394 /// Hold the sizes of the register banks for all HwModes.
395 const unsigned *Sizes;
396
397 /// Current HwMode for the target.
398 unsigned HwMode;
399
400 /// Keep dynamically allocated PartialMapping in a separate map.
401 /// This shouldn't be needed when everything gets TableGen'ed.
404
405 /// Keep dynamically allocated ValueMapping in a separate map.
406 /// This shouldn't be needed when everything gets TableGen'ed.
409
410 /// Keep dynamically allocated array of ValueMapping in a separate map.
411 /// This shouldn't be needed when everything gets TableGen'ed.
414
415 /// Keep dynamically allocated InstructionMapping in a separate map.
416 /// This shouldn't be needed when everything gets TableGen'ed.
419
420 /// Getting the minimal register class of a physreg is expensive.
421 /// Cache this information as we get it.
423
424 /// Create a RegisterBankInfo that can accommodate up to \p NumRegBanks
425 /// RegisterBank instances.
427 const unsigned *Sizes, unsigned HwMode);
428
429 /// This constructor is meaningless.
430 /// It just provides a default constructor that can be used at link time
431 /// when GlobalISel is not built.
432 /// That way, targets can still inherit from this class without doing
433 /// crazy gymnastic to avoid link time failures.
434 /// \note That works because the constructor is inlined.
436 llvm_unreachable("This constructor should not be executed");
437 }
438
439 /// Get the register bank identified by \p ID.
440 const RegisterBank &getRegBank(unsigned ID) {
441 assert(ID < getNumRegBanks() && "Accessing an unknown register bank");
442 return *RegBanks[ID];
443 }
444
445 /// Get the MinimalPhysRegClass for Reg.
446 /// \pre Reg is a physical register.
447 const TargetRegisterClass *
449
450 /// Try to get the mapping of \p MI.
451 /// See getInstrMapping for more details on what a mapping represents.
452 ///
453 /// Unlike getInstrMapping the returned InstructionMapping may be invalid
454 /// (isValid() == false).
455 /// This means that the target independent code is not smart enough
456 /// to get the mapping of \p MI and thus, the target has to provide the
457 /// information for \p MI.
458 ///
459 /// This implementation is able to get the mapping of:
460 /// - Target specific instructions by looking at the encoding constraints.
461 /// - Any instruction if all the register operands have already been assigned
462 /// a register, a register class, or a register bank.
463 /// - Copies and phis if at least one of the operands has been assigned a
464 /// register, a register class, or a register bank.
465 /// In other words, this method will likely fail to find a mapping for
466 /// any generic opcode that has not been lowered by target specific code.
467 const InstructionMapping &getInstrMappingImpl(const MachineInstr &MI) const;
468
469 /// Get the uniquely generated PartialMapping for the
470 /// given arguments.
471 const PartialMapping &getPartialMapping(unsigned StartIdx, unsigned Length,
472 const RegisterBank &RegBank) const;
473
474 /// \name Methods to get a uniquely generated ValueMapping.
475 /// @{
476
477 /// The most common ValueMapping consists of a single PartialMapping.
478 /// Feature a method for that.
479 const ValueMapping &getValueMapping(unsigned StartIdx, unsigned Length,
480 const RegisterBank &RegBank) const;
481
482 /// Get the ValueMapping for the given arguments.
483 const ValueMapping &getValueMapping(const PartialMapping *BreakDown,
484 unsigned NumBreakDowns) const;
485 /// @}
486
487 /// \name Methods to get a uniquely generated array of ValueMapping.
488 /// @{
489
490 /// Get the uniquely generated array of ValueMapping for the
491 /// elements of between \p Begin and \p End.
492 ///
493 /// Elements that are nullptr will be replaced by
494 /// invalid ValueMapping (ValueMapping::isValid == false).
495 ///
496 /// \pre The pointers on ValueMapping between \p Begin and \p End
497 /// must uniquely identify a ValueMapping. Otherwise, there is no
498 /// guarantee that the return instance will be unique, i.e., another
499 /// OperandsMapping could have the same content.
500 template <typename Iterator>
501 const ValueMapping *getOperandsMapping(Iterator Begin, Iterator End) const;
502
503 /// Get the uniquely generated array of ValueMapping for the
504 /// elements of \p OpdsMapping.
505 ///
506 /// Elements of \p OpdsMapping that are nullptr will be replaced by
507 /// invalid ValueMapping (ValueMapping::isValid == false).
508 const ValueMapping *getOperandsMapping(
509 const SmallVectorImpl<const ValueMapping *> &OpdsMapping) const;
510
511 /// Get the uniquely generated array of ValueMapping for the
512 /// given arguments.
513 ///
514 /// Arguments that are nullptr will be replaced by invalid
515 /// ValueMapping (ValueMapping::isValid == false).
517 std::initializer_list<const ValueMapping *> OpdsMapping) const;
518 /// @}
519
520 /// \name Methods to get a uniquely generated InstructionMapping.
521 /// @{
522
523private:
524 /// Method to get a uniquely generated InstructionMapping.
525 const InstructionMapping &
526 getInstructionMappingImpl(bool IsInvalid, unsigned ID = InvalidMappingID,
527 unsigned Cost = 0,
528 const ValueMapping *OperandsMapping = nullptr,
529 unsigned NumOperands = 0) const;
530
531public:
532 /// Method to get a uniquely generated InstructionMapping.
533 const InstructionMapping &
534 getInstructionMapping(unsigned ID, unsigned Cost,
535 const ValueMapping *OperandsMapping,
536 unsigned NumOperands) const {
537 return getInstructionMappingImpl(/*IsInvalid*/ false, ID, Cost,
538 OperandsMapping, NumOperands);
539 }
540
541 /// Method to get a uniquely generated invalid InstructionMapping.
543 return getInstructionMappingImpl(/*IsInvalid*/ true);
544 }
545 /// @}
546
547 /// Get the register bank for the \p OpIdx-th operand of \p MI form
548 /// the encoding constraints, if any.
549 ///
550 /// \return A register bank that covers the register class of the
551 /// related encoding constraints or nullptr if \p MI did not provide
552 /// enough information to deduce it.
553 const RegisterBank *
554 getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx,
555 const TargetInstrInfo &TII,
556 const MachineRegisterInfo &MRI) const;
557
558 /// Helper method to apply something that is like the default mapping.
559 /// Basically, that means that \p OpdMapper.getMI() is left untouched
560 /// aside from the reassignment of the register operand that have been
561 /// remapped.
562 ///
563 /// The type of all the new registers that have been created by the
564 /// mapper are properly remapped to the type of the original registers
565 /// they replace. In other words, the semantic of the instruction does
566 /// not change, only the register banks.
567 ///
568 /// If the mapping of one of the operand spans several registers, this
569 /// method will abort as this is not like a default mapping anymore.
570 ///
571 /// \pre For OpIdx in {0..\p OpdMapper.getMI().getNumOperands())
572 /// the range OpdMapper.getVRegs(OpIdx) is empty or of size 1.
573 static void applyDefaultMapping(const OperandsMapper &OpdMapper);
574
575 /// See ::applyMapping.
576 virtual void applyMappingImpl(MachineIRBuilder &Builder,
577 const OperandsMapper &OpdMapper) const {
578 llvm_unreachable("The target has to implement this");
579 }
580
581public:
582 virtual ~RegisterBankInfo() = default;
583
584 /// Get the register bank identified by \p ID.
585 const RegisterBank &getRegBank(unsigned ID) const {
586 return const_cast<RegisterBankInfo *>(this)->getRegBank(ID);
587 }
588
589 /// Get the maximum size in bits that fits in the given register bank.
590 unsigned getMaximumSize(unsigned RegBankID) const {
591 return Sizes[RegBankID + HwMode * NumRegBanks];
592 }
593
594 /// Get the register bank of \p Reg.
595 /// If Reg has not been assigned a register, a register class,
596 /// or a register bank, then this returns nullptr.
597 ///
598 /// \pre Reg != 0 (NoRegister)
600 const TargetRegisterInfo &TRI) const;
601
602 /// Get the total number of register banks.
603 unsigned getNumRegBanks() const { return NumRegBanks; }
604
605 /// Returns true if the register bank is considered divergent.
606 virtual bool isDivergentRegBank(const RegisterBank *RB) const {
607 return false;
608 }
609
610 /// Get a register bank that covers \p RC.
611 ///
612 /// \pre \p RC is a user-defined register class (as opposed as one
613 /// generated by TableGen).
614 ///
615 /// \note The mapping RC -> RegBank could be built while adding the
616 /// coverage for the register banks. However, we do not do it, because,
617 /// at least for now, we only need this information for register classes
618 /// that are used in the description of instruction. In other words,
619 /// there are just a handful of them and we do not want to waste space.
620 ///
621 /// \todo This should be TableGen'ed.
622 virtual const RegisterBank &
624 llvm_unreachable("The target must override this method");
625 }
626
627 /// Get the cost of a copy from \p B to \p A, or put differently,
628 /// get the cost of A = COPY B. Since register banks may cover
629 /// different size, \p Size specifies what will be the size in bits
630 /// that will be copied around.
631 ///
632 /// \note Since this is a copy, both registers have the same size.
633 virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
634 TypeSize Size) const {
635 // Optimistically assume that copies are coalesced. I.e., when
636 // they are on the same bank, they are free.
637 // Otherwise assume a non-zero cost of 1. The targets are supposed
638 // to override that properly anyway if they care.
639 return &A != &B;
640 }
641
642 /// \returns true if emitting a copy from \p Src to \p Dst is impossible.
643 bool cannotCopy(const RegisterBank &Dst, const RegisterBank &Src,
644 TypeSize Size) const {
645 return copyCost(Dst, Src, Size) == std::numeric_limits<unsigned>::max();
646 }
647
648 /// Get the cost of using \p ValMapping to decompose a register. This is
649 /// similar to ::copyCost, except for cases where multiple copy-like
650 /// operations need to be inserted. If the register is used as a source
651 /// operand and already has a bank assigned, \p CurBank is non-null.
652 virtual unsigned
654 const RegisterBank *CurBank = nullptr) const {
655 return std::numeric_limits<unsigned>::max();
656 }
657
658 /// Constrain the (possibly generic) virtual register \p Reg to \p RC.
659 ///
660 /// \pre \p Reg is a virtual register that either has a bank or a class.
661 /// \returns The constrained register class, or nullptr if there is none.
662 /// \note This is a generic variant of MachineRegisterInfo::constrainRegClass
663 /// \note Use MachineRegisterInfo::constrainRegAttrs instead for any non-isel
664 /// purpose, including non-select passes of GlobalISel
665 static const TargetRegisterClass *
668
669 /// Identifier used when the related instruction mapping instance
670 /// is generated by target independent code.
671 /// Make sure not to use that identifier to avoid possible collision.
672 static const unsigned DefaultMappingID;
673
674 /// Identifier used when the related instruction mapping instance
675 /// is generated by the default constructor.
676 /// Make sure not to use that identifier.
677 static const unsigned InvalidMappingID;
678
679 /// Get the mapping of the different operands of \p MI
680 /// on the register bank.
681 /// This mapping should be the direct translation of \p MI.
682 /// In other words, when \p MI is mapped with the returned mapping,
683 /// only the register banks of the operands of \p MI need to be updated.
684 /// In particular, neither the opcode nor the type of \p MI needs to be
685 /// updated for this direct mapping.
686 ///
687 /// The target independent implementation gives a mapping based on
688 /// the register classes for the target specific opcode.
689 /// It uses the ID RegisterBankInfo::DefaultMappingID for that mapping.
690 /// Make sure you do not use that ID for the alternative mapping
691 /// for MI. See getInstrAlternativeMappings for the alternative
692 /// mappings.
693 ///
694 /// For instance, if \p MI is a vector add, the mapping should
695 /// not be a scalarization of the add.
696 ///
697 /// \post returnedVal.verify(MI).
698 ///
699 /// \note If returnedVal does not verify MI, this would probably mean
700 /// that the target does not support that instruction.
701 virtual const InstructionMapping &
702 getInstrMapping(const MachineInstr &MI) const;
703
704 /// Get the alternative mappings for \p MI.
705 /// Alternative in the sense different from getInstrMapping.
706 virtual InstructionMappings
708
709 /// Get the possible mapping for \p MI.
710 /// A mapping defines where the different operands may live and at what cost.
711 /// For instance, let us consider:
712 /// v0(16) = G_ADD <2 x i8> v1, v2
713 /// The possible mapping could be:
714 ///
715 /// {/*ID*/VectorAdd, /*Cost*/1, /*v0*/{(0xFFFF, VPR)}, /*v1*/{(0xFFFF, VPR)},
716 /// /*v2*/{(0xFFFF, VPR)}}
717 /// {/*ID*/ScalarAddx2, /*Cost*/2, /*v0*/{(0x00FF, GPR),(0xFF00, GPR)},
718 /// /*v1*/{(0x00FF, GPR),(0xFF00, GPR)},
719 /// /*v2*/{(0x00FF, GPR),(0xFF00, GPR)}}
720 ///
721 /// \note The first alternative of the returned mapping should be the
722 /// direct translation of \p MI current form.
723 ///
724 /// \post !returnedVal.empty().
726
727 /// Apply \p OpdMapper.getInstrMapping() to \p OpdMapper.getMI().
728 /// After this call \p OpdMapper.getMI() may not be valid anymore.
729 /// \p OpdMapper.getInstrMapping().getID() carries the information of
730 /// what has been chosen to map \p OpdMapper.getMI(). This ID is set
731 /// by the various getInstrXXXMapping method.
732 ///
733 /// Therefore, getting the mapping and applying it should be kept in
734 /// sync.
736 const OperandsMapper &OpdMapper) const {
737 // The only mapping we know how to handle is the default mapping.
738 if (OpdMapper.getInstrMapping().getID() == DefaultMappingID)
739 return applyDefaultMapping(OpdMapper);
740 // For other mapping, the target needs to do the right thing.
741 // If that means calling applyDefaultMapping, fine, but this
742 // must be explicitly stated.
743 applyMappingImpl(Builder, OpdMapper);
744 }
745
746 /// Get the size in bits of \p Reg.
747 /// Utility method to get the size of any registers. Unlike
748 /// MachineRegisterInfo::getSize, the register does not need to be a
749 /// virtual register.
750 ///
751 /// \pre \p Reg != 0 (NoRegister).
753 const TargetRegisterInfo &TRI) const;
754
755 /// Check that information hold by this instance make sense for the
756 /// given \p TRI.
757 ///
758 /// \note This method does not check anything when assertions are disabled.
759 ///
760 /// \return True is the check was successful.
761 bool verify(const TargetRegisterInfo &TRI) const;
762};
763
766 const RegisterBankInfo::PartialMapping &PartMapping) {
767 PartMapping.print(OS);
768 return OS;
769}
770
773 ValMapping.print(OS);
774 return OS;
775}
776
779 const RegisterBankInfo::InstructionMapping &InstrMapping) {
780 InstrMapping.print(OS);
781 return OS;
782}
783
786 OpdMapper.print(OS, /*ForDebug*/ false);
787 return OS;
788}
789
790/// Hashing function for PartialMapping.
791/// It is required for the hashing of ValueMapping.
792hash_code hash_value(const RegisterBankInfo::PartialMapping &PartMapping);
793
794} // end namespace llvm
795
796#endif // LLVM_CODEGEN_REGISTERBANKINFO_H
unsigned const MachineRegisterInfo * MRI
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
This file defines the DenseMap class.
uint64_t Size
bool End
Definition: ELF_riscv.cpp:480
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
Implement a low-level type suitable for MachineInstr level instruction selection.
unsigned const TargetRegisterInfo * TRI
unsigned Reg
ppc ctr loops verify
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
This file defines the SmallVector class.
Helper class to build MachineInstr.
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Helper class that represents how the value of an instruction may be mapped and what is the related co...
unsigned getNumOperands() const
Get the number of operands.
unsigned getCost() const
Get the cost.
InstructionMapping()=default
Default constructor.
void setOperandsMapping(const ValueMapping *OpdsMapping)
Set the mapping for all the operands.
void dump() const
Print this on dbgs() stream.
void print(raw_ostream &OS) const
Print this on OS;.
InstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands)
Constructor for the mapping of an instruction.
const ValueMapping & getOperandMapping(unsigned i) const
Get the value mapping of the ith operand.
bool isValid() const
Check whether this object is valid.
Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...
const InstructionMapping & getInstrMapping() const
The final mapping of the instruction.
void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, Register NewVReg)
Set the virtual register of the PartialMapIdx-th partial mapping of the OpIdx-th operand to NewVReg.
void print(raw_ostream &OS, bool ForDebug=false) const
Print this operands mapper on OS stream.
void createVRegs(unsigned OpIdx)
Create as many new virtual registers as needed for the mapping of the OpIdx-th operand.
MachineRegisterInfo & getMRI() const
The MachineRegisterInfo we used to realize the mapping.
void dump() const
Print this operands mapper on dbgs() stream.
iterator_range< SmallVectorImpl< Register >::const_iterator > getVRegs(unsigned OpIdx, bool ForDebug=false) const
Get all the virtual registers required to map the OpIdx-th operand of the instruction.
Holds all the information related to register banks.
virtual bool isDivergentRegBank(const RegisterBank *RB) const
Returns true if the register bank is considered divergent.
const PartialMapping & getPartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
Get the uniquely generated PartialMapping for the given arguments.
void applyMapping(MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const
Apply OpdMapper.getInstrMapping() to OpdMapper.getMI().
virtual InstructionMappings getInstrAlternativeMappings(const MachineInstr &MI) const
Get the alternative mappings for MI.
virtual ~RegisterBankInfo()=default
static const TargetRegisterClass * constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
DenseMap< hash_code, std::unique_ptr< const InstructionMapping > > MapOfInstructionMappings
Keep dynamically allocated InstructionMapping in a separate map.
const RegisterBank ** RegBanks
Hold the set of supported register banks.
RegisterBankInfo()
This constructor is meaningless.
DenseMap< hash_code, std::unique_ptr< const PartialMapping > > MapOfPartialMappings
Keep dynamically allocated PartialMapping in a separate map.
virtual const InstructionMapping & getInstrMapping(const MachineInstr &MI) const
Get the mapping of the different operands of MI on the register bank.
virtual void applyMappingImpl(MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const
See applyMapping.
unsigned NumRegBanks
Total number of register banks.
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
static void applyDefaultMapping(const OperandsMapper &OpdMapper)
Helper method to apply something that is like the default mapping.
DenseMap< hash_code, std::unique_ptr< const ValueMapping > > MapOfValueMappings
Keep dynamically allocated ValueMapping in a separate map.
const TargetRegisterClass * getMinimalPhysRegClass(Register Reg, const TargetRegisterInfo &TRI) const
Get the MinimalPhysRegClass for Reg.
const ValueMapping & getValueMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const
The most common ValueMapping consists of a single PartialMapping.
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
DenseMap< hash_code, std::unique_ptr< ValueMapping[]> > MapOfOperandsMappings
Keep dynamically allocated array of ValueMapping in a separate map.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
const unsigned * Sizes
Hold the sizes of the register banks for all HwModes.
bool cannotCopy(const RegisterBank &Dst, const RegisterBank &Src, TypeSize Size) const
unsigned getMaximumSize(unsigned RegBankID) const
Get the maximum size in bits that fits in the given register bank.
unsigned getNumRegBanks() const
Get the total number of register banks.
const RegisterBank * getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const MachineRegisterInfo &MRI) const
Get the register bank for the OpIdx-th operand of MI form the encoding constraints,...
TypeSize getSizeInBits(Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const
Get the size in bits of Reg.
virtual const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT Ty) const
Get a register bank that covers RC.
InstructionMappings getInstrPossibleMappings(const MachineInstr &MI) const
Get the possible mapping for MI.
DenseMap< unsigned, const TargetRegisterClass * > PhysRegMinimalRCs
Getting the minimal register class of a physreg is expensive.
const RegisterBank & getRegBank(unsigned ID) const
Get the register bank identified by ID.
static const unsigned InvalidMappingID
Identifier used when the related instruction mapping instance is generated by the default constructor...
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
unsigned HwMode
Current HwMode for the target.
const ValueMapping * getOperandsMapping(std::initializer_list< const ValueMapping * > OpdsMapping) const
Get the uniquely generated array of ValueMapping for the given arguments.
virtual unsigned copyCost(const RegisterBank &A, const RegisterBank &B, TypeSize Size) const
Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B.
virtual unsigned getBreakDownCost(const ValueMapping &ValMapping, const RegisterBank *CurBank=nullptr) const
Get the cost of using ValMapping to decompose a register.
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
This class implements the register bank concept.
Definition: RegisterBank.h:28
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:587
typename SuperClass::const_iterator const_iterator
Definition: SmallVector.h:592
typename SuperClass::iterator iterator
Definition: SmallVector.h:591
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1210
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
A range adaptor for a pair of iterators.
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Length
Definition: DWP.cpp:480
hash_code hash_value(const FixedPointSemantics &Val)
Definition: APFixedPoint.h:128
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:293
Helper struct that represents how a value is partially mapped into a register.
void print(raw_ostream &OS) const
Print this partial mapping on OS;.
constexpr PartialMapping(unsigned StartIdx, unsigned Length, const RegisterBank &RegBank)
Provide a shortcut for quickly building PartialMapping.
unsigned StartIdx
Number of bits at which this partial mapping starts in the original value.
void dump() const
Print this partial mapping on dbgs() stream.
const RegisterBank * RegBank
Register bank where the partial value lives.
unsigned Length
Length of this mapping in bits.
Helper struct that represents how a value is mapped through different register banks.
constexpr ValueMapping(const PartialMapping *BreakDown, unsigned NumBreakDowns)
Initialize a ValueMapping with the given parameter.
const PartialMapping * begin() const
Iterators through the PartialMappings.
const PartialMapping * end() const
void print(raw_ostream &OS) const
Print this on OS;.
bool isValid() const
Check if this ValueMapping is valid.
unsigned NumBreakDowns
Number of partial mapping to break down this value.
ValueMapping()
The default constructor creates an invalid (isValid() == false) instance.
void dump() const
Print this on dbgs() stream.
const PartialMapping * BreakDown
How the value is broken down between the different register banks.