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MachineIRBuilder.h
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1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the MachineIRBuilder class.
10 /// This is a helper class to build MachineInstr.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
14 #define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
15 
18 
23 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/DebugLoc.h"
25 
26 
27 namespace llvm {
28 
29 // Forward declarations.
30 class MachineFunction;
31 class MachineInstr;
32 class TargetInstrInfo;
33 class GISelChangeObserver;
34 
35 /// Class which stores all the state required in a MachineIRBuilder.
36 /// Since MachineIRBuilders will only store state in this object, it allows
37 /// to transfer BuilderState between different kinds of MachineIRBuilders.
39  /// MachineFunction under construction.
41  /// Information used to access the description of the opcodes.
43  /// Information used to verify types are consistent and to create virtual registers.
45  /// Debug location to be set to any instruction we create.
47 
48  /// \name Fields describing the insertion point.
49  /// @{
52  /// @}
53 
55 
57 };
58 
59 class DstOp {
60  union {
64  };
65 
66 public:
67  enum class DstType { Ty_LLT, Ty_Reg, Ty_RC };
68  DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {}
69  DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {}
70  DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {}
71  DstOp(const LLT &T) : LLTTy(T), Ty(DstType::Ty_LLT) {}
72  DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {}
73 
75  switch (Ty) {
76  case DstType::Ty_Reg:
77  MIB.addDef(Reg);
78  break;
79  case DstType::Ty_LLT:
80  MIB.addDef(MRI.createGenericVirtualRegister(LLTTy));
81  break;
82  case DstType::Ty_RC:
83  MIB.addDef(MRI.createVirtualRegister(RC));
84  break;
85  }
86  }
87 
89  switch (Ty) {
90  case DstType::Ty_RC:
91  return LLT{};
92  case DstType::Ty_LLT:
93  return LLTTy;
94  case DstType::Ty_Reg:
95  return MRI.getType(Reg);
96  }
97  llvm_unreachable("Unrecognised DstOp::DstType enum");
98  }
99 
100  Register getReg() const {
101  assert(Ty == DstType::Ty_Reg && "Not a register");
102  return Reg;
103  }
104 
106  switch (Ty) {
107  case DstType::Ty_RC:
108  return RC;
109  default:
110  llvm_unreachable("Not a RC Operand");
111  }
112  }
113 
114  DstType getDstOpKind() const { return Ty; }
115 
116 private:
117  DstType Ty;
118 };
119 
120 class SrcOp {
121  union {
125  };
126 
127 public:
128  enum class SrcType { Ty_Reg, Ty_MIB, Ty_Predicate };
129  SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {}
130  SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {}
131  SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {}
132  SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {}
133 
134  void addSrcToMIB(MachineInstrBuilder &MIB) const {
135  switch (Ty) {
136  case SrcType::Ty_Predicate:
137  MIB.addPredicate(Pred);
138  break;
139  case SrcType::Ty_Reg:
140  MIB.addUse(Reg);
141  break;
142  case SrcType::Ty_MIB:
143  MIB.addUse(SrcMIB->getOperand(0).getReg());
144  break;
145  }
146  }
147 
149  switch (Ty) {
150  case SrcType::Ty_Predicate:
151  llvm_unreachable("Not a register operand");
152  case SrcType::Ty_Reg:
153  return MRI.getType(Reg);
154  case SrcType::Ty_MIB:
155  return MRI.getType(SrcMIB->getOperand(0).getReg());
156  }
157  llvm_unreachable("Unrecognised SrcOp::SrcType enum");
158  }
159 
160  Register getReg() const {
161  switch (Ty) {
162  case SrcType::Ty_Predicate:
163  llvm_unreachable("Not a register operand");
164  case SrcType::Ty_Reg:
165  return Reg;
166  case SrcType::Ty_MIB:
167  return SrcMIB->getOperand(0).getReg();
168  }
169  llvm_unreachable("Unrecognised SrcOp::SrcType enum");
170  }
171 
173  switch (Ty) {
174  case SrcType::Ty_Predicate:
175  return Pred;
176  default:
177  llvm_unreachable("Not a register operand");
178  }
179  }
180 
181  SrcType getSrcOpKind() const { return Ty; }
182 
183 private:
184  SrcType Ty;
185 };
186 
187 class FlagsOp {
188  Optional<unsigned> Flags;
189 
190 public:
191  explicit FlagsOp(unsigned F) : Flags(F) {}
192  FlagsOp() : Flags(None) {}
193  Optional<unsigned> getFlags() const { return Flags; }
194 };
195 /// Helper class to build MachineInstr.
196 /// It keeps internally the insertion point and debug location for all
197 /// the new instructions we want to create.
198 /// This information can be modify via the related setters.
200 
201  MachineIRBuilderState State;
202 
203 protected:
204  void validateTruncExt(const LLT &Dst, const LLT &Src, bool IsExtend);
205 
206  void validateBinaryOp(const LLT &Res, const LLT &Op0, const LLT &Op1);
207  void validateShiftOp(const LLT &Res, const LLT &Op0, const LLT &Op1);
208 
209  void validateSelectOp(const LLT &ResTy, const LLT &TstTy, const LLT &Op0Ty,
210  const LLT &Op1Ty);
211  void recordInsertion(MachineInstr *MI) const;
212 
213 public:
214  /// Some constructors for easy use.
215  MachineIRBuilder() = default;
218  setInstr(MI);
219  }
220 
221  virtual ~MachineIRBuilder() = default;
222 
223  MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {}
224 
226  assert(State.TII && "TargetInstrInfo is not set");
227  return *State.TII;
228  }
229 
230  /// Getter for the function we currently build.
232  assert(State.MF && "MachineFunction is not set");
233  return *State.MF;
234  }
235 
236  const MachineFunction &getMF() const {
237  assert(State.MF && "MachineFunction is not set");
238  return *State.MF;
239  }
240 
241  const DataLayout &getDataLayout() const {
242  return getMF().getFunction().getParent()->getDataLayout();
243  }
244 
245  /// Getter for DebugLoc
246  const DebugLoc &getDL() { return State.DL; }
247 
248  /// Getter for MRI
249  MachineRegisterInfo *getMRI() { return State.MRI; }
250  const MachineRegisterInfo *getMRI() const { return State.MRI; }
251 
252  /// Getter for the State
253  MachineIRBuilderState &getState() { return State; }
254 
255  /// Getter for the basic block we currently build.
256  const MachineBasicBlock &getMBB() const {
257  assert(State.MBB && "MachineBasicBlock is not set");
258  return *State.MBB;
259  }
260 
262  return const_cast<MachineBasicBlock &>(
263  const_cast<const MachineIRBuilder *>(this)->getMBB());
264  }
265 
266  GISelCSEInfo *getCSEInfo() { return State.CSEInfo; }
267  const GISelCSEInfo *getCSEInfo() const { return State.CSEInfo; }
268 
269  /// Current insertion point for new instructions.
271 
272  /// Set the insertion point before the specified position.
273  /// \pre MBB must be in getMF().
274  /// \pre II must be a valid iterator in MBB.
276  /// @}
277 
278  void setCSEInfo(GISelCSEInfo *Info);
279 
280  /// \name Setters for the insertion point.
281  /// @{
282  /// Set the MachineFunction where to build instructions.
283  void setMF(MachineFunction &MF);
284 
285  /// Set the insertion point to the end of \p MBB.
286  /// \pre \p MBB must be contained by getMF().
287  void setMBB(MachineBasicBlock &MBB);
288 
289  /// Set the insertion point to before MI.
290  /// \pre MI must be in getMF().
291  void setInstr(MachineInstr &MI);
292  /// @}
293 
294  void setChangeObserver(GISelChangeObserver &Observer);
295  void stopObservingChanges();
296  /// @}
297 
298  /// Set the debug location to \p DL for all the next build instructions.
299  void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; }
300 
301  /// Get the current instruction's debug location.
302  DebugLoc getDebugLoc() { return State.DL; }
303 
304  /// Build and insert <empty> = \p Opcode <empty>.
305  /// The insertion point is the one set by the last call of either
306  /// setBasicBlock or setMI.
307  ///
308  /// \pre setBasicBlock or setMI must have been called.
309  ///
310  /// \return a MachineInstrBuilder for the newly created instruction.
311  MachineInstrBuilder buildInstr(unsigned Opcode);
312 
313  /// Build but don't insert <empty> = \p Opcode <empty>.
314  ///
315  /// \pre setMF, setBasicBlock or setMI must have been called.
316  ///
317  /// \return a MachineInstrBuilder for the newly created instruction.
318  MachineInstrBuilder buildInstrNoInsert(unsigned Opcode);
319 
320  /// Insert an existing instruction at the insertion point.
321  MachineInstrBuilder insertInstr(MachineInstrBuilder MIB);
322 
323  /// Build and insert a DBG_VALUE instruction expressing the fact that the
324  /// associated \p Variable lives in \p Reg (suitably modified by \p Expr).
325  MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable,
326  const MDNode *Expr);
327 
328  /// Build and insert a DBG_VALUE instruction expressing the fact that the
329  /// associated \p Variable lives in memory at \p Reg (suitably modified by \p
330  /// Expr).
331  MachineInstrBuilder buildIndirectDbgValue(Register Reg,
332  const MDNode *Variable,
333  const MDNode *Expr);
334 
335  /// Build and insert a DBG_VALUE instruction expressing the fact that the
336  /// associated \p Variable lives in the stack slot specified by \p FI
337  /// (suitably modified by \p Expr).
338  MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable,
339  const MDNode *Expr);
340 
341  /// Build and insert a DBG_VALUE instructions specifying that \p Variable is
342  /// given by \p C (suitably modified by \p Expr).
343  MachineInstrBuilder buildConstDbgValue(const Constant &C,
344  const MDNode *Variable,
345  const MDNode *Expr);
346 
347  /// Build and insert a DBG_LABEL instructions specifying that \p Label is
348  /// given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label".
349  MachineInstrBuilder buildDbgLabel(const MDNode *Label);
350 
351  /// Build and insert \p Res = G_FRAME_INDEX \p Idx
352  ///
353  /// G_FRAME_INDEX materializes the address of an alloca value or other
354  /// stack-based object.
355  ///
356  /// \pre setBasicBlock or setMI must have been called.
357  /// \pre \p Res must be a generic virtual register with pointer type.
358  ///
359  /// \return a MachineInstrBuilder for the newly created instruction.
360  MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx);
361 
362  /// Build and insert \p Res = G_GLOBAL_VALUE \p GV
363  ///
364  /// G_GLOBAL_VALUE materializes the address of the specified global
365  /// into \p Res.
366  ///
367  /// \pre setBasicBlock or setMI must have been called.
368  /// \pre \p Res must be a generic virtual register with pointer type
369  /// in the same address space as \p GV.
370  ///
371  /// \return a MachineInstrBuilder for the newly created instruction.
372  MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV);
373 
374  /// Build and insert \p Res = G_GEP \p Op0, \p Op1
375  ///
376  /// G_GEP adds \p Op1 bytes to the pointer specified by \p Op0,
377  /// storing the resulting pointer in \p Res.
378  ///
379  /// \pre setBasicBlock or setMI must have been called.
380  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
381  /// type.
382  /// \pre \p Op1 must be a generic virtual register with scalar type.
383  ///
384  /// \return a MachineInstrBuilder for the newly created instruction.
385  MachineInstrBuilder buildGEP(const DstOp &Res, const SrcOp &Op0,
386  const SrcOp &Op1);
387 
388  /// Materialize and insert \p Res = G_GEP \p Op0, (G_CONSTANT \p Value)
389  ///
390  /// G_GEP adds \p Value bytes to the pointer specified by \p Op0,
391  /// storing the resulting pointer in \p Res. If \p Value is zero then no
392  /// G_GEP or G_CONSTANT will be created and \pre Op0 will be assigned to
393  /// \p Res.
394  ///
395  /// \pre setBasicBlock or setMI must have been called.
396  /// \pre \p Op0 must be a generic virtual register with pointer type.
397  /// \pre \p ValueTy must be a scalar type.
398  /// \pre \p Res must be 0. This is to detect confusion between
399  /// materializeGEP() and buildGEP().
400  /// \post \p Res will either be a new generic virtual register of the same
401  /// type as \p Op0 or \p Op0 itself.
402  ///
403  /// \return a MachineInstrBuilder for the newly created instruction.
404  Optional<MachineInstrBuilder> materializeGEP(Register &Res, Register Op0,
405  const LLT &ValueTy,
406  uint64_t Value);
407 
408  /// Build and insert \p Res = G_PTR_MASK \p Op0, \p NumBits
409  ///
410  /// G_PTR_MASK clears the low bits of a pointer operand without destroying its
411  /// pointer properties. This has the effect of rounding the address *down* to
412  /// a specified alignment in bits.
413  ///
414  /// \pre setBasicBlock or setMI must have been called.
415  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
416  /// type.
417  /// \pre \p NumBits must be an integer representing the number of low bits to
418  /// be cleared in \p Op0.
419  ///
420  /// \return a MachineInstrBuilder for the newly created instruction.
421  MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0,
422  uint32_t NumBits);
423 
424  /// Build and insert \p Res, \p CarryOut = G_UADDO \p Op0, \p Op1
425  ///
426  /// G_UADDO sets \p Res to \p Op0 + \p Op1 (truncated to the bit width) and
427  /// sets \p CarryOut to 1 if the result overflowed in unsigned arithmetic.
428  ///
429  /// \pre setBasicBlock or setMI must have been called.
430  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers with the
431  /// same scalar type.
432  ////\pre \p CarryOut must be generic virtual register with scalar type
433  ///(typically s1)
434  ///
435  /// \return The newly created instruction.
436  MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut,
437  const SrcOp &Op0, const SrcOp &Op1);
438 
439  /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0,
440  /// \p Op1, \p CarryIn
441  ///
442  /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit
443  /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned
444  /// arithmetic.
445  ///
446  /// \pre setBasicBlock or setMI must have been called.
447  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
448  /// with the same scalar type.
449  /// \pre \p CarryOut and \p CarryIn must be generic virtual
450  /// registers with the same scalar type (typically s1)
451  ///
452  /// \return The newly created instruction.
453  MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut,
454  const SrcOp &Op0, const SrcOp &Op1,
455  const SrcOp &CarryIn);
456 
457  /// Build and insert \p Res = G_ANYEXT \p Op0
458  ///
459  /// G_ANYEXT produces a register of the specified width, with bits 0 to
460  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified
461  /// (i.e. this is neither zero nor sign-extension). For a vector register,
462  /// each element is extended individually.
463  ///
464  /// \pre setBasicBlock or setMI must have been called.
465  /// \pre \p Res must be a generic virtual register with scalar or vector type.
466  /// \pre \p Op must be a generic virtual register with scalar or vector type.
467  /// \pre \p Op must be smaller than \p Res
468  ///
469  /// \return The newly created instruction.
470 
471  MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);
472 
473  /// Build and insert \p Res = G_SEXT \p Op
474  ///
475  /// G_SEXT produces a register of the specified width, with bits 0 to
476  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the
477  /// high bit of \p Op (i.e. 2s-complement sign extended).
478  ///
479  /// \pre setBasicBlock or setMI must have been called.
480  /// \pre \p Res must be a generic virtual register with scalar or vector type.
481  /// \pre \p Op must be a generic virtual register with scalar or vector type.
482  /// \pre \p Op must be smaller than \p Res
483  ///
484  /// \return The newly created instruction.
485  MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op);
486 
487  /// Build and insert a G_PTRTOINT instruction.
488  MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src) {
489  return buildInstr(TargetOpcode::G_PTRTOINT, {Dst}, {Src});
490  }
491 
492  /// Build and insert \p Dst = G_BITCAST \p Src
493  MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) {
494  return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src});
495  }
496 
497  /// \return The opcode of the extension the target wants to use for boolean
498  /// values.
499  unsigned getBoolExtOp(bool IsVec, bool IsFP) const;
500 
501  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_SEXT \p Op, or \p Res
502  // = G_ZEXT \p Op depending on how the target wants to extend boolean values.
503  MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op,
504  bool IsFP);
505 
506  /// Build and insert \p Res = G_ZEXT \p Op
507  ///
508  /// G_ZEXT produces a register of the specified width, with bits 0 to
509  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector
510  /// register, each element is extended individually.
511  ///
512  /// \pre setBasicBlock or setMI must have been called.
513  /// \pre \p Res must be a generic virtual register with scalar or vector type.
514  /// \pre \p Op must be a generic virtual register with scalar or vector type.
515  /// \pre \p Op must be smaller than \p Res
516  ///
517  /// \return The newly created instruction.
518  MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op);
519 
520  /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or
521  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
522  /// ///
523  /// \pre setBasicBlock or setMI must have been called.
524  /// \pre \p Res must be a generic virtual register with scalar or vector type.
525  /// \pre \p Op must be a generic virtual register with scalar or vector type.
526  ///
527  /// \return The newly created instruction.
528  MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op);
529 
530  /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or
531  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
532  /// ///
533  /// \pre setBasicBlock or setMI must have been called.
534  /// \pre \p Res must be a generic virtual register with scalar or vector type.
535  /// \pre \p Op must be a generic virtual register with scalar or vector type.
536  ///
537  /// \return The newly created instruction.
538  MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op);
539 
540  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or
541  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
542  /// ///
543  /// \pre setBasicBlock or setMI must have been called.
544  /// \pre \p Res must be a generic virtual register with scalar or vector type.
545  /// \pre \p Op must be a generic virtual register with scalar or vector type.
546  ///
547  /// \return The newly created instruction.
548  MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op);
549 
550  /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p
551  /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and
552  /// \p Op.
553  /// ///
554  /// \pre setBasicBlock or setMI must have been called.
555  /// \pre \p Res must be a generic virtual register with scalar or vector type.
556  /// \pre \p Op must be a generic virtual register with scalar or vector type.
557  ///
558  /// \return The newly created instruction.
559  MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
560  const SrcOp &Op);
561 
562  /// Build and insert an appropriate cast between two registers of equal size.
563  MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src);
564 
565  /// Build and insert G_BR \p Dest
566  ///
567  /// G_BR is an unconditional branch to \p Dest.
568  ///
569  /// \pre setBasicBlock or setMI must have been called.
570  ///
571  /// \return a MachineInstrBuilder for the newly created instruction.
572  MachineInstrBuilder buildBr(MachineBasicBlock &Dest);
573 
574  /// Build and insert G_BRCOND \p Tst, \p Dest
575  ///
576  /// G_BRCOND is a conditional branch to \p Dest.
577  ///
578  /// \pre setBasicBlock or setMI must have been called.
579  /// \pre \p Tst must be a generic virtual register with scalar
580  /// type. At the beginning of legalization, this will be a single
581  /// bit (s1). Targets with interesting flags registers may change
582  /// this. For a wider type, whether the branch is taken must only
583  /// depend on bit 0 (for now).
584  ///
585  /// \return The newly created instruction.
586  MachineInstrBuilder buildBrCond(Register Tst, MachineBasicBlock &Dest);
587 
588  /// Build and insert G_BRINDIRECT \p Tgt
589  ///
590  /// G_BRINDIRECT is an indirect branch to \p Tgt.
591  ///
592  /// \pre setBasicBlock or setMI must have been called.
593  /// \pre \p Tgt must be a generic virtual register with pointer type.
594  ///
595  /// \return a MachineInstrBuilder for the newly created instruction.
596  MachineInstrBuilder buildBrIndirect(Register Tgt);
597 
598  /// Build and insert G_BRJT \p TablePtr, \p JTI, \p IndexReg
599  ///
600  /// G_BRJT is a jump table branch using a table base pointer \p TablePtr,
601  /// jump table index \p JTI and index \p IndexReg
602  ///
603  /// \pre setBasicBlock or setMI must have been called.
604  /// \pre \p TablePtr must be a generic virtual register with pointer type.
605  /// \pre \p JTI must be be a jump table index.
606  /// \pre \p IndexReg must be a generic virtual register with pointer type.
607  ///
608  /// \return a MachineInstrBuilder for the newly created instruction.
609  MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI,
610  Register IndexReg);
611 
612  /// Build and insert \p Res = G_CONSTANT \p Val
613  ///
614  /// G_CONSTANT is an integer constant with the specified size and value. \p
615  /// Val will be extended or truncated to the size of \p Reg.
616  ///
617  /// \pre setBasicBlock or setMI must have been called.
618  /// \pre \p Res must be a generic virtual register with scalar or pointer
619  /// type.
620  ///
621  /// \return The newly created instruction.
622  virtual MachineInstrBuilder buildConstant(const DstOp &Res,
623  const ConstantInt &Val);
624 
625  /// Build and insert \p Res = G_CONSTANT \p Val
626  ///
627  /// G_CONSTANT is an integer constant with the specified size and value.
628  ///
629  /// \pre setBasicBlock or setMI must have been called.
630  /// \pre \p Res must be a generic virtual register with scalar type.
631  ///
632  /// \return The newly created instruction.
633  MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val);
634  MachineInstrBuilder buildConstant(const DstOp &Res, const APInt &Val);
635 
636  /// Build and insert \p Res = G_FCONSTANT \p Val
637  ///
638  /// G_FCONSTANT is a floating-point constant with the specified size and
639  /// value.
640  ///
641  /// \pre setBasicBlock or setMI must have been called.
642  /// \pre \p Res must be a generic virtual register with scalar type.
643  ///
644  /// \return The newly created instruction.
645  virtual MachineInstrBuilder buildFConstant(const DstOp &Res,
646  const ConstantFP &Val);
647 
648  MachineInstrBuilder buildFConstant(const DstOp &Res, double Val);
649  MachineInstrBuilder buildFConstant(const DstOp &Res, const APFloat &Val);
650 
651  /// Build and insert \p Res = COPY Op
652  ///
653  /// Register-to-register COPY sets \p Res to \p Op.
654  ///
655  /// \pre setBasicBlock or setMI must have been called.
656  ///
657  /// \return a MachineInstrBuilder for the newly created instruction.
658  MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);
659 
660  /// Build and insert `Res = G_LOAD Addr, MMO`.
661  ///
662  /// Loads the value stored at \p Addr. Puts the result in \p Res.
663  ///
664  /// \pre setBasicBlock or setMI must have been called.
665  /// \pre \p Res must be a generic virtual register.
666  /// \pre \p Addr must be a generic virtual register with pointer type.
667  ///
668  /// \return a MachineInstrBuilder for the newly created instruction.
669  MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr,
670  MachineMemOperand &MMO);
671 
672  /// Build and insert `Res = <opcode> Addr, MMO`.
673  ///
674  /// Loads the value stored at \p Addr. Puts the result in \p Res.
675  ///
676  /// \pre setBasicBlock or setMI must have been called.
677  /// \pre \p Res must be a generic virtual register.
678  /// \pre \p Addr must be a generic virtual register with pointer type.
679  ///
680  /// \return a MachineInstrBuilder for the newly created instruction.
681  MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res,
682  const SrcOp &Addr, MachineMemOperand &MMO);
683 
684  /// Build and insert `G_STORE Val, Addr, MMO`.
685  ///
686  /// Stores the value \p Val to \p Addr.
687  ///
688  /// \pre setBasicBlock or setMI must have been called.
689  /// \pre \p Val must be a generic virtual register.
690  /// \pre \p Addr must be a generic virtual register with pointer type.
691  ///
692  /// \return a MachineInstrBuilder for the newly created instruction.
693  MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr,
694  MachineMemOperand &MMO);
695 
696  /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.
697  ///
698  /// \pre setBasicBlock or setMI must have been called.
699  /// \pre \p Res and \p Src must be generic virtual registers.
700  ///
701  /// \return a MachineInstrBuilder for the newly created instruction.
702  MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index);
703 
704  /// Build and insert \p Res = IMPLICIT_DEF.
705  MachineInstrBuilder buildUndef(const DstOp &Res);
706 
707  /// Build and insert instructions to put \p Ops together at the specified p
708  /// Indices to form a larger register.
709  ///
710  /// If the types of the input registers are uniform and cover the entirity of
711  /// \p Res then a G_MERGE_VALUES will be produced. Otherwise an IMPLICIT_DEF
712  /// followed by a sequence of G_INSERT instructions.
713  ///
714  /// \pre setBasicBlock or setMI must have been called.
715  /// \pre The final element of the sequence must not extend past the end of the
716  /// destination register.
717  /// \pre The bits defined by each Op (derived from index and scalar size) must
718  /// not overlap.
719  /// \pre \p Indices must be in ascending order of bit position.
720  void buildSequence(Register Res, ArrayRef<Register> Ops,
721  ArrayRef<uint64_t> Indices);
722 
723  /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
724  ///
725  /// G_MERGE_VALUES combines the input elements contiguously into a larger
726  /// register.
727  ///
728  /// \pre setBasicBlock or setMI must have been called.
729  /// \pre The entire register \p Res (and no more) must be covered by the input
730  /// registers.
731  /// \pre The type of all \p Ops registers must be identical.
732  ///
733  /// \return a MachineInstrBuilder for the newly created instruction.
734  MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef<Register> Ops);
735 
736  /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op
737  ///
738  /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple
739  ///
740  /// \pre setBasicBlock or setMI must have been called.
741  /// \pre The entire register \p Res (and no more) must be covered by the input
742  /// registers.
743  /// \pre The type of all \p Res registers must be identical.
744  ///
745  /// \return a MachineInstrBuilder for the newly created instruction.
746  MachineInstrBuilder buildUnmerge(ArrayRef<LLT> Res, const SrcOp &Op);
747  MachineInstrBuilder buildUnmerge(ArrayRef<Register> Res, const SrcOp &Op);
748 
749  /// Build and insert an unmerge of \p Res sized pieces to cover \p Op
750  MachineInstrBuilder buildUnmerge(LLT Res, const SrcOp &Op);
751 
752  /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ...
753  ///
754  /// G_BUILD_VECTOR creates a vector value from multiple scalar registers.
755  /// \pre setBasicBlock or setMI must have been called.
756  /// \pre The entire register \p Res (and no more) must be covered by the
757  /// input scalar registers.
758  /// \pre The type of all \p Ops registers must be identical.
759  ///
760  /// \return a MachineInstrBuilder for the newly created instruction.
761  MachineInstrBuilder buildBuildVector(const DstOp &Res,
762  ArrayRef<Register> Ops);
763 
764  /// Build and insert \p Res = G_BUILD_VECTOR with \p Src replicated to fill
765  /// the number of elements
766  MachineInstrBuilder buildSplatVector(const DstOp &Res,
767  const SrcOp &Src);
768 
769  /// Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ...
770  ///
771  /// G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers
772  /// which have types larger than the destination vector element type, and
773  /// truncates the values to fit.
774  ///
775  /// If the operands given are already the same size as the vector elt type,
776  /// then this method will instead create a G_BUILD_VECTOR instruction.
777  ///
778  /// \pre setBasicBlock or setMI must have been called.
779  /// \pre The type of all \p Ops registers must be identical.
780  ///
781  /// \return a MachineInstrBuilder for the newly created instruction.
782  MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res,
783  ArrayRef<Register> Ops);
784 
785  /// Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ...
786  ///
787  /// G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more
788  /// vectors.
789  ///
790  /// \pre setBasicBlock or setMI must have been called.
791  /// \pre The entire register \p Res (and no more) must be covered by the input
792  /// registers.
793  /// \pre The type of all source operands must be identical.
794  ///
795  /// \return a MachineInstrBuilder for the newly created instruction.
796  MachineInstrBuilder buildConcatVectors(const DstOp &Res,
797  ArrayRef<Register> Ops);
798 
799  MachineInstrBuilder buildInsert(Register Res, Register Src,
800  Register Op, unsigned Index);
801 
802  /// Build and insert either a G_INTRINSIC (if \p HasSideEffects is false) or
803  /// G_INTRINSIC_W_SIDE_EFFECTS instruction. Its first operand will be the
804  /// result register definition unless \p Reg is NoReg (== 0). The second
805  /// operand will be the intrinsic's ID.
806  ///
807  /// Callers are expected to add the required definitions and uses afterwards.
808  ///
809  /// \pre setBasicBlock or setMI must have been called.
810  ///
811  /// \return a MachineInstrBuilder for the newly created instruction.
813  bool HasSideEffects);
814  MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<DstOp> Res,
815  bool HasSideEffects);
816 
817  /// Build and insert \p Res = G_FPTRUNC \p Op
818  ///
819  /// G_FPTRUNC converts a floating-point value into one with a smaller type.
820  ///
821  /// \pre setBasicBlock or setMI must have been called.
822  /// \pre \p Res must be a generic virtual register with scalar or vector type.
823  /// \pre \p Op must be a generic virtual register with scalar or vector type.
824  /// \pre \p Res must be smaller than \p Op
825  ///
826  /// \return The newly created instruction.
827  MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op);
828 
829  /// Build and insert \p Res = G_TRUNC \p Op
830  ///
831  /// G_TRUNC extracts the low bits of a type. For a vector type each element is
832  /// truncated independently before being packed into the destination.
833  ///
834  /// \pre setBasicBlock or setMI must have been called.
835  /// \pre \p Res must be a generic virtual register with scalar or vector type.
836  /// \pre \p Op must be a generic virtual register with scalar or vector type.
837  /// \pre \p Res must be smaller than \p Op
838  ///
839  /// \return The newly created instruction.
840  MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op);
841 
842  /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1
843  ///
844  /// \pre setBasicBlock or setMI must have been called.
845 
846  /// \pre \p Res must be a generic virtual register with scalar or
847  /// vector type. Typically this starts as s1 or <N x s1>.
848  /// \pre \p Op0 and Op1 must be generic virtual registers with the
849  /// same number of elements as \p Res. If \p Res is a scalar,
850  /// \p Op0 must be either a scalar or pointer.
851  /// \pre \p Pred must be an integer predicate.
852  ///
853  /// \return a MachineInstrBuilder for the newly created instruction.
854  MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res,
855  const SrcOp &Op0, const SrcOp &Op1);
856 
857  /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1
858  ///
859  /// \pre setBasicBlock or setMI must have been called.
860 
861  /// \pre \p Res must be a generic virtual register with scalar or
862  /// vector type. Typically this starts as s1 or <N x s1>.
863  /// \pre \p Op0 and Op1 must be generic virtual registers with the
864  /// same number of elements as \p Res (or scalar, if \p Res is
865  /// scalar).
866  /// \pre \p Pred must be a floating-point predicate.
867  ///
868  /// \return a MachineInstrBuilder for the newly created instruction.
869  MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res,
870  const SrcOp &Op0, const SrcOp &Op1);
871 
872  /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1
873  ///
874  /// \pre setBasicBlock or setMI must have been called.
875  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
876  /// with the same type.
877  /// \pre \p Tst must be a generic virtual register with scalar, pointer or
878  /// vector type. If vector then it must have the same number of
879  /// elements as the other parameters.
880  ///
881  /// \return a MachineInstrBuilder for the newly created instruction.
882  MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,
883  const SrcOp &Op0, const SrcOp &Op1);
884 
885  /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val,
886  /// \p Elt, \p Idx
887  ///
888  /// \pre setBasicBlock or setMI must have been called.
889  /// \pre \p Res and \p Val must be a generic virtual register
890  // with the same vector type.
891  /// \pre \p Elt and \p Idx must be a generic virtual register
892  /// with scalar type.
893  ///
894  /// \return The newly created instruction.
895  MachineInstrBuilder buildInsertVectorElement(const DstOp &Res,
896  const SrcOp &Val,
897  const SrcOp &Elt,
898  const SrcOp &Idx);
899 
900  /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
901  ///
902  /// \pre setBasicBlock or setMI must have been called.
903  /// \pre \p Res must be a generic virtual register with scalar type.
904  /// \pre \p Val must be a generic virtual register with vector type.
905  /// \pre \p Idx must be a generic virtual register with scalar type.
906  ///
907  /// \return The newly created instruction.
908  MachineInstrBuilder buildExtractVectorElement(const DstOp &Res,
909  const SrcOp &Val,
910  const SrcOp &Idx);
911 
912  /// Build and insert `OldValRes<def>, SuccessRes<def> =
913  /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`.
914  ///
915  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
916  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
917  /// Addr in \p Res, along with an s1 indicating whether it was replaced.
918  ///
919  /// \pre setBasicBlock or setMI must have been called.
920  /// \pre \p OldValRes must be a generic virtual register of scalar type.
921  /// \pre \p SuccessRes must be a generic virtual register of scalar type. It
922  /// will be assigned 0 on failure and 1 on success.
923  /// \pre \p Addr must be a generic virtual register with pointer type.
924  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
925  /// registers of the same type.
926  ///
927  /// \return a MachineInstrBuilder for the newly created instruction.
929  buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes,
930  Register Addr, Register CmpVal, Register NewVal,
931  MachineMemOperand &MMO);
932 
933  /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal,
934  /// MMO`.
935  ///
936  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
937  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
938  /// Addr in \p Res.
939  ///
940  /// \pre setBasicBlock or setMI must have been called.
941  /// \pre \p OldValRes must be a generic virtual register of scalar type.
942  /// \pre \p Addr must be a generic virtual register with pointer type.
943  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
944  /// registers of the same type.
945  ///
946  /// \return a MachineInstrBuilder for the newly created instruction.
947  MachineInstrBuilder buildAtomicCmpXchg(Register OldValRes, Register Addr,
948  Register CmpVal, Register NewVal,
949  MachineMemOperand &MMO);
950 
951  /// Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`.
952  ///
953  /// Atomically read-modify-update the value at \p Addr with \p Val. Puts the
954  /// original value from \p Addr in \p OldValRes. The modification is
955  /// determined by the opcode.
956  ///
957  /// \pre setBasicBlock or setMI must have been called.
958  /// \pre \p OldValRes must be a generic virtual register.
959  /// \pre \p Addr must be a generic virtual register with pointer type.
960  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
961  /// same type.
962  ///
963  /// \return a MachineInstrBuilder for the newly created instruction.
964  MachineInstrBuilder buildAtomicRMW(unsigned Opcode, Register OldValRes,
965  Register Addr, Register Val,
966  MachineMemOperand &MMO);
967 
968  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`.
969  ///
970  /// Atomically replace the value at \p Addr with \p Val. Puts the original
971  /// value from \p Addr in \p OldValRes.
972  ///
973  /// \pre setBasicBlock or setMI must have been called.
974  /// \pre \p OldValRes must be a generic virtual register.
975  /// \pre \p Addr must be a generic virtual register with pointer type.
976  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
977  /// same type.
978  ///
979  /// \return a MachineInstrBuilder for the newly created instruction.
980  MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr,
981  Register Val, MachineMemOperand &MMO);
982 
983  /// Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`.
984  ///
985  /// Atomically replace the value at \p Addr with the addition of \p Val and
986  /// the original value. Puts the original value from \p Addr in \p OldValRes.
987  ///
988  /// \pre setBasicBlock or setMI must have been called.
989  /// \pre \p OldValRes must be a generic virtual register.
990  /// \pre \p Addr must be a generic virtual register with pointer type.
991  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
992  /// same type.
993  ///
994  /// \return a MachineInstrBuilder for the newly created instruction.
995  MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr,
996  Register Val, MachineMemOperand &MMO);
997 
998  /// Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`.
999  ///
1000  /// Atomically replace the value at \p Addr with the subtraction of \p Val and
1001  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1002  ///
1003  /// \pre setBasicBlock or setMI must have been called.
1004  /// \pre \p OldValRes must be a generic virtual register.
1005  /// \pre \p Addr must be a generic virtual register with pointer type.
1006  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1007  /// same type.
1008  ///
1009  /// \return a MachineInstrBuilder for the newly created instruction.
1010  MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr,
1011  Register Val, MachineMemOperand &MMO);
1012 
1013  /// Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`.
1014  ///
1015  /// Atomically replace the value at \p Addr with the bitwise and of \p Val and
1016  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1017  ///
1018  /// \pre setBasicBlock or setMI must have been called.
1019  /// \pre \p OldValRes must be a generic virtual register.
1020  /// \pre \p Addr must be a generic virtual register with pointer type.
1021  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1022  /// same type.
1023  ///
1024  /// \return a MachineInstrBuilder for the newly created instruction.
1025  MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr,
1026  Register Val, MachineMemOperand &MMO);
1027 
1028  /// Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`.
1029  ///
1030  /// Atomically replace the value at \p Addr with the bitwise nand of \p Val
1031  /// and the original value. Puts the original value from \p Addr in \p
1032  /// OldValRes.
1033  ///
1034  /// \pre setBasicBlock or setMI must have been called.
1035  /// \pre \p OldValRes must be a generic virtual register.
1036  /// \pre \p Addr must be a generic virtual register with pointer type.
1037  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1038  /// same type.
1039  ///
1040  /// \return a MachineInstrBuilder for the newly created instruction.
1041  MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr,
1042  Register Val, MachineMemOperand &MMO);
1043 
1044  /// Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`.
1045  ///
1046  /// Atomically replace the value at \p Addr with the bitwise or of \p Val and
1047  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1048  ///
1049  /// \pre setBasicBlock or setMI must have been called.
1050  /// \pre \p OldValRes must be a generic virtual register.
1051  /// \pre \p Addr must be a generic virtual register with pointer type.
1052  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1053  /// same type.
1054  ///
1055  /// \return a MachineInstrBuilder for the newly created instruction.
1056  MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr,
1057  Register Val, MachineMemOperand &MMO);
1058 
1059  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`.
1060  ///
1061  /// Atomically replace the value at \p Addr with the bitwise xor of \p Val and
1062  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1063  ///
1064  /// \pre setBasicBlock or setMI must have been called.
1065  /// \pre \p OldValRes must be a generic virtual register.
1066  /// \pre \p Addr must be a generic virtual register with pointer type.
1067  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1068  /// same type.
1069  ///
1070  /// \return a MachineInstrBuilder for the newly created instruction.
1071  MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr,
1072  Register Val, MachineMemOperand &MMO);
1073 
1074  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`.
1075  ///
1076  /// Atomically replace the value at \p Addr with the signed maximum of \p
1077  /// Val and the original value. Puts the original value from \p Addr in \p
1078  /// OldValRes.
1079  ///
1080  /// \pre setBasicBlock or setMI must have been called.
1081  /// \pre \p OldValRes must be a generic virtual register.
1082  /// \pre \p Addr must be a generic virtual register with pointer type.
1083  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1084  /// same type.
1085  ///
1086  /// \return a MachineInstrBuilder for the newly created instruction.
1087  MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr,
1088  Register Val, MachineMemOperand &MMO);
1089 
1090  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`.
1091  ///
1092  /// Atomically replace the value at \p Addr with the signed minimum of \p
1093  /// Val and the original value. Puts the original value from \p Addr in \p
1094  /// OldValRes.
1095  ///
1096  /// \pre setBasicBlock or setMI must have been called.
1097  /// \pre \p OldValRes must be a generic virtual register.
1098  /// \pre \p Addr must be a generic virtual register with pointer type.
1099  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1100  /// same type.
1101  ///
1102  /// \return a MachineInstrBuilder for the newly created instruction.
1103  MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr,
1104  Register Val, MachineMemOperand &MMO);
1105 
1106  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`.
1107  ///
1108  /// Atomically replace the value at \p Addr with the unsigned maximum of \p
1109  /// Val and the original value. Puts the original value from \p Addr in \p
1110  /// OldValRes.
1111  ///
1112  /// \pre setBasicBlock or setMI must have been called.
1113  /// \pre \p OldValRes must be a generic virtual register.
1114  /// \pre \p Addr must be a generic virtual register with pointer type.
1115  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1116  /// same type.
1117  ///
1118  /// \return a MachineInstrBuilder for the newly created instruction.
1119  MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr,
1120  Register Val, MachineMemOperand &MMO);
1121 
1122  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`.
1123  ///
1124  /// Atomically replace the value at \p Addr with the unsigned minimum of \p
1125  /// Val and the original value. Puts the original value from \p Addr in \p
1126  /// OldValRes.
1127  ///
1128  /// \pre setBasicBlock or setMI must have been called.
1129  /// \pre \p OldValRes must be a generic virtual register.
1130  /// \pre \p Addr must be a generic virtual register with pointer type.
1131  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1132  /// same type.
1133  ///
1134  /// \return a MachineInstrBuilder for the newly created instruction.
1135  MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr,
1136  Register Val, MachineMemOperand &MMO);
1137 
1138  /// Build and insert `G_FENCE Ordering, Scope`.
1139  MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope);
1140 
1141  /// Build and insert \p Res = G_BLOCK_ADDR \p BA
1142  ///
1143  /// G_BLOCK_ADDR computes the address of a basic block.
1144  ///
1145  /// \pre setBasicBlock or setMI must have been called.
1146  /// \pre \p Res must be a generic virtual register of a pointer type.
1147  ///
1148  /// \return The newly created instruction.
1149  MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA);
1150 
1151  /// Build and insert \p Res = G_ADD \p Op0, \p Op1
1152  ///
1153  /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1154  /// truncated to their width.
1155  ///
1156  /// \pre setBasicBlock or setMI must have been called.
1157  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1158  /// with the same (scalar or vector) type).
1159  ///
1160  /// \return a MachineInstrBuilder for the newly created instruction.
1161 
1162  MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,
1163  const SrcOp &Src1,
1164  Optional<unsigned> Flags = None) {
1165  return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1166  }
1167 
1168  /// Build and insert \p Res = G_SUB \p Op0, \p Op1
1169  ///
1170  /// G_SUB sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1171  /// truncated to their width.
1172  ///
1173  /// \pre setBasicBlock or setMI must have been called.
1174  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1175  /// with the same (scalar or vector) type).
1176  ///
1177  /// \return a MachineInstrBuilder for the newly created instruction.
1178 
1179  MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0,
1180  const SrcOp &Src1,
1181  Optional<unsigned> Flags = None) {
1182  return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1183  }
1184 
1185  /// Build and insert \p Res = G_MUL \p Op0, \p Op1
1186  ///
1187  /// G_MUL sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1188  /// truncated to their width.
1189  ///
1190  /// \pre setBasicBlock or setMI must have been called.
1191  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1192  /// with the same (scalar or vector) type).
1193  ///
1194  /// \return a MachineInstrBuilder for the newly created instruction.
1195  MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
1196  const SrcOp &Src1,
1197  Optional<unsigned> Flags = None) {
1198  return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1199  }
1200 
1201  MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0,
1202  const SrcOp &Src1,
1203  Optional<unsigned> Flags = None) {
1204  return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags);
1205  }
1206 
1207  MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0,
1208  const SrcOp &Src1,
1209  Optional<unsigned> Flags = None) {
1210  return buildInstr(TargetOpcode::G_SMULH, {Dst}, {Src0, Src1}, Flags);
1211  }
1212 
1213  MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0,
1214  const SrcOp &Src1,
1215  Optional<unsigned> Flags = None) {
1216  return buildInstr(TargetOpcode::G_SHL, {Dst}, {Src0, Src1}, Flags);
1217  }
1218 
1219  MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0,
1220  const SrcOp &Src1,
1221  Optional<unsigned> Flags = None) {
1222  return buildInstr(TargetOpcode::G_LSHR, {Dst}, {Src0, Src1}, Flags);
1223  }
1224 
1225  MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0,
1226  const SrcOp &Src1,
1227  Optional<unsigned> Flags = None) {
1228  return buildInstr(TargetOpcode::G_ASHR, {Dst}, {Src0, Src1}, Flags);
1229  }
1230 
1231  /// Build and insert \p Res = G_AND \p Op0, \p Op1
1232  ///
1233  /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p
1234  /// Op1.
1235  ///
1236  /// \pre setBasicBlock or setMI must have been called.
1237  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1238  /// with the same (scalar or vector) type).
1239  ///
1240  /// \return a MachineInstrBuilder for the newly created instruction.
1241 
1242  MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0,
1243  const SrcOp &Src1) {
1244  return buildInstr(TargetOpcode::G_AND, {Dst}, {Src0, Src1});
1245  }
1246 
1247  /// Build and insert \p Res = G_OR \p Op0, \p Op1
1248  ///
1249  /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
1250  /// Op1.
1251  ///
1252  /// \pre setBasicBlock or setMI must have been called.
1253  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1254  /// with the same (scalar or vector) type).
1255  ///
1256  /// \return a MachineInstrBuilder for the newly created instruction.
1257  MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0,
1258  const SrcOp &Src1) {
1259  return buildInstr(TargetOpcode::G_OR, {Dst}, {Src0, Src1});
1260  }
1261 
1262  /// Build and insert \p Res = G_XOR \p Op0, \p Op1
1263  MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0,
1264  const SrcOp &Src1) {
1265  return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, Src1});
1266  }
1267 
1268  /// Build and insert a bitwise not,
1269  /// \p NegOne = G_CONSTANT -1
1270  /// \p Res = G_OR \p Op0, NegOne
1271  MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) {
1272  auto NegOne = buildConstant(Dst.getLLTTy(*getMRI()), -1);
1273  return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, NegOne});
1274  }
1275 
1276  /// Build and insert \p Res = G_CTPOP \p Op0, \p Src0
1277  MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0) {
1278  return buildInstr(TargetOpcode::G_CTPOP, {Dst}, {Src0});
1279  }
1280 
1281  /// Build and insert \p Res = G_CTLZ \p Op0, \p Src0
1282  MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0) {
1283  return buildInstr(TargetOpcode::G_CTLZ, {Dst}, {Src0});
1284  }
1285 
1286  /// Build and insert \p Res = G_CTLZ_ZERO_UNDEF \p Op0, \p Src0
1288  return buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {Dst}, {Src0});
1289  }
1290 
1291  /// Build and insert \p Res = G_CTTZ \p Op0, \p Src0
1292  MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0) {
1293  return buildInstr(TargetOpcode::G_CTTZ, {Dst}, {Src0});
1294  }
1295 
1296  /// Build and insert \p Res = G_CTTZ_ZERO_UNDEF \p Op0, \p Src0
1298  return buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, {Dst}, {Src0});
1299  }
1300 
1301  /// Build and insert \p Res = G_FADD \p Op0, \p Op1
1302  MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0,
1303  const SrcOp &Src1) {
1304  return buildInstr(TargetOpcode::G_FADD, {Dst}, {Src0, Src1});
1305  }
1306 
1307  /// Build and insert \p Res = G_FSUB \p Op0, \p Op1
1308  MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0,
1309  const SrcOp &Src1) {
1310  return buildInstr(TargetOpcode::G_FSUB, {Dst}, {Src0, Src1});
1311  }
1312 
1313  /// Build and insert \p Res = G_FMA \p Op0, \p Op1, \p Op2
1314  MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0,
1315  const SrcOp &Src1, const SrcOp &Src2) {
1316  return buildInstr(TargetOpcode::G_FMA, {Dst}, {Src0, Src1, Src2});
1317  }
1318 
1319  /// Build and insert \p Res = G_FNEG \p Op0
1320  MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0) {
1321  return buildInstr(TargetOpcode::G_FNEG, {Dst}, {Src0});
1322  }
1323 
1324  /// Build and insert \p Res = G_FABS \p Op0
1325  MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0) {
1326  return buildInstr(TargetOpcode::G_FABS, {Dst}, {Src0});
1327  }
1328 
1329  /// Build and insert \p Dst = G_FCANONICALIZE \p Src0
1331  Optional<unsigned> Flags = None) {
1332  return buildInstr(TargetOpcode::G_FCANONICALIZE, {Dst}, {Src0}, Flags);
1333  }
1334 
1335  /// Build and insert \p Res = G_FCOPYSIGN \p Op0, \p Op1
1337  const SrcOp &Src1) {
1338  return buildInstr(TargetOpcode::G_FCOPYSIGN, {Dst}, {Src0, Src1});
1339  }
1340 
1341  /// Build and insert \p Res = G_UITOFP \p Src0
1342  MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0) {
1343  return buildInstr(TargetOpcode::G_UITOFP, {Dst}, {Src0});
1344  }
1345 
1346  /// Build and insert \p Res = G_SITOFP \p Src0
1347  MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0) {
1348  return buildInstr(TargetOpcode::G_SITOFP, {Dst}, {Src0});
1349  }
1350 
1351  /// Build and insert \p Res = G_FPTOUI \p Src0
1352  MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0) {
1353  return buildInstr(TargetOpcode::G_FPTOUI, {Dst}, {Src0});
1354  }
1355 
1356  /// Build and insert \p Res = G_FPTOSI \p Src0
1357  MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0) {
1358  return buildInstr(TargetOpcode::G_FPTOSI, {Dst}, {Src0});
1359  }
1360 
1361  /// Build and insert \p Res = G_SMIN \p Op0, \p Op1
1362  MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0,
1363  const SrcOp &Src1) {
1364  return buildInstr(TargetOpcode::G_SMIN, {Dst}, {Src0, Src1});
1365  }
1366 
1367  /// Build and insert \p Res = G_SMAX \p Op0, \p Op1
1368  MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0,
1369  const SrcOp &Src1) {
1370  return buildInstr(TargetOpcode::G_SMAX, {Dst}, {Src0, Src1});
1371  }
1372 
1373  /// Build and insert \p Res = G_UMIN \p Op0, \p Op1
1374  MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0,
1375  const SrcOp &Src1) {
1376  return buildInstr(TargetOpcode::G_UMIN, {Dst}, {Src0, Src1});
1377  }
1378 
1379  /// Build and insert \p Res = G_UMAX \p Op0, \p Op1
1380  MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0,
1381  const SrcOp &Src1) {
1382  return buildInstr(TargetOpcode::G_UMAX, {Dst}, {Src0, Src1});
1383  }
1384 
1385  /// Build and insert \p Res = G_JUMP_TABLE \p JTI
1386  ///
1387  /// G_JUMP_TABLE sets \p Res to the address of the jump table specified by
1388  /// the jump table index \p JTI.
1389  ///
1390  /// \return a MachineInstrBuilder for the newly created instruction.
1391  MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI);
1392 
1393  virtual MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
1394  ArrayRef<SrcOp> SrcOps,
1395  Optional<unsigned> Flags = None);
1396 };
1397 
1398 } // End namespace llvm.
1399 #endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
MachineBasicBlock & getMBB()
uint64_t CallInst * C
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
const TargetRegisterClass * RC
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
The CSE Analysis object.
Definition: CSEInfo.h:71
MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_XOR Op0, Op1.
CmpInst::Predicate Pred
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
DstType getDstOpKind() const
DstOp(Register R)
MachineIRBuilder(const MachineIRBuilderState &BState)
GISelChangeObserver * Observer
unsigned Reg
void setDebugLoc(const DebugLoc &DL)
Set the debug location to DL for all the next build instructions.
const MachineFunction & getMF() const
MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_OR Op0, Op1.
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
void addSrcToMIB(MachineInstrBuilder &MIB) const
const MachineInstrBuilder & addPredicate(CmpInst::Predicate Pred) const
A debug info location.
Definition: DebugLoc.h:33
Metadata node.
Definition: Metadata.h:863
F(f)
MachineIRBuilder(MachineInstr &MI)
MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2)
Build and insert Res = G_FMA Op0, Op1, Op2.
SrcOp(Register R)
The address of a basic block.
Definition: Constants.h:839
MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ Op0, Src0.
A description of a memory reference used in the backend.
MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ_ZERO_UNDEF Op0, Src0.
GISelCSEInfo * getCSEInfo()
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
MachineBasicBlock::iterator II
SrcType getSrcOpKind() const
DstOp(const TargetRegisterClass *TRC)
DstOp(unsigned R)
MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_SITOFP Src0.
MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_FSUB Op0, Op1.
SrcOp(const CmpInst::Predicate P)
MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FNEG Op0.
MachineFunction & getMF()
Getter for the function we currently build.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_SUB Op0, Op1.
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Optional< unsigned > getFlags() const
TargetInstrInfo - Interface to description of machine instruction set.
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
#define P(N)
MachineRegisterInfo * getMRI()
Getter for MRI.
Abstract class that contains various methods for clients to notify about changes. ...
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
FlagsOp(unsigned F)
MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ_ZERO_UNDEF Op0, Src0.
This is an important base class in LLVM.
Definition: Constant.h:41
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Class which stores all the state required in a MachineIRBuilder.
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
Helper class to build MachineInstr.
MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_FADD Op0, Op1.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:732
DebugLoc DL
Debug location to be set to any instruction we create.
MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOSI Src0.
MachineIRBuilder(MachineFunction &MF)
SrcOp(const MachineInstrBuilder &MIB)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_UITOFP Src0.
DstOp(const MachineOperand &Op)
const MachineRegisterInfo * getMRI() const
MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTPOP Op0, Src0.
MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_MUL Op0, Op1.
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
const GISelCSEInfo * getCSEInfo() const
MachineOperand class - Representation of each machine instruction operand.
Register getReg() const
MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOUI Src0.
const TargetInstrInfo & getTII()
DebugLoc getDebugLoc()
Get the current instruction&#39;s debug location.
SrcOp(const MachineOperand &Op)
LLT getLLTTy(const MachineRegisterInfo &MRI) const
MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
This file describes high level types that are used by several passes or APIs involved in the GlobalIS...
Class for arbitrary precision integers.
Definition: APInt.h:69
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Register getReg() const
LLT getLLTTy(const MachineRegisterInfo &MRI) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMAX Op0, Op1.
MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ Op0, Src0.
DstOp(const LLT &T)
Representation of each machine instruction.
Definition: MachineInstr.h:64
MachineIRBuilderState & getState()
Getter for the State.
MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
const TargetRegisterClass * getRegClass() const
MachineInstrBuilder buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
Build and insert Dst = G_FCANONICALIZE Src0.
MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_ADD Op0, Op1.
MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FABS Op0.
MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0)
Build and insert a bitwise not, NegOne = G_CONSTANT -1 Res = G_OR Op0, NegOne.
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_PTRTOINT instruction.
MachineInstrBuilder buildFCopysign(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_FCOPYSIGN Op0, Op1.
MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMAX Op0, Op1.
const DataLayout & getDataLayout() const
MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITCAST Src.
MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMIN Op0, Op1.
CmpInst::Predicate getPredicate() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:72
static Value * buildGEP(IRBuilderTy &IRB, Value *BasePtr, SmallVectorImpl< Value *> &Indices, Twine NamePrefix)
Build a GEP out of a base pointer and indices.
Definition: SROA.cpp:1395
MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMIN Op0, Op1.
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
IRTranslator LLVM IR MI
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
MachineFunction * MF
MachineFunction under construction.
const DebugLoc & getDL()
Getter for DebugLoc.
MachineInstrBuilder SrcMIB
Wrapper class representing virtual and physical registers.
Definition: Register.h:18
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.