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MachineIRBuilder.h
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1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the MachineIRBuilder class.
10 /// This is a helper class to build MachineInstr.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
14 #define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
15 
18 
23 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/DebugLoc.h"
25 
26 
27 namespace llvm {
28 
29 // Forward declarations.
30 class MachineFunction;
31 class MachineInstr;
32 class TargetInstrInfo;
33 class GISelChangeObserver;
34 
35 /// Class which stores all the state required in a MachineIRBuilder.
36 /// Since MachineIRBuilders will only store state in this object, it allows
37 /// to transfer BuilderState between different kinds of MachineIRBuilders.
39  /// MachineFunction under construction.
41  /// Information used to access the description of the opcodes.
43  /// Information used to verify types are consistent and to create virtual registers.
45  /// Debug location to be set to any instruction we create.
47 
48  /// \name Fields describing the insertion point.
49  /// @{
52  /// @}
53 
55 
57 };
58 
59 class DstOp {
60  union {
62  unsigned Reg;
64  };
65 
66 public:
67  enum class DstType { Ty_LLT, Ty_Reg, Ty_RC };
68  DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {}
69  DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {}
70  DstOp(const LLT &T) : LLTTy(T), Ty(DstType::Ty_LLT) {}
71  DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {}
72 
74  switch (Ty) {
75  case DstType::Ty_Reg:
76  MIB.addDef(Reg);
77  break;
78  case DstType::Ty_LLT:
79  MIB.addDef(MRI.createGenericVirtualRegister(LLTTy));
80  break;
81  case DstType::Ty_RC:
82  MIB.addDef(MRI.createVirtualRegister(RC));
83  break;
84  }
85  }
86 
88  switch (Ty) {
89  case DstType::Ty_RC:
90  return LLT{};
91  case DstType::Ty_LLT:
92  return LLTTy;
93  case DstType::Ty_Reg:
94  return MRI.getType(Reg);
95  }
96  llvm_unreachable("Unrecognised DstOp::DstType enum");
97  }
98 
99  unsigned getReg() const {
100  assert(Ty == DstType::Ty_Reg && "Not a register");
101  return Reg;
102  }
103 
105  switch (Ty) {
106  case DstType::Ty_RC:
107  return RC;
108  default:
109  llvm_unreachable("Not a RC Operand");
110  }
111  }
112 
113  DstType getDstOpKind() const { return Ty; }
114 
115 private:
116  DstType Ty;
117 };
118 
119 class SrcOp {
120  union {
122  unsigned Reg;
124  };
125 
126 public:
127  enum class SrcType { Ty_Reg, Ty_MIB, Ty_Predicate };
128  SrcOp(unsigned R) : Reg(R), Ty(SrcType::Ty_Reg) {}
129  SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {}
130  SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {}
131  SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {}
132 
133  void addSrcToMIB(MachineInstrBuilder &MIB) const {
134  switch (Ty) {
135  case SrcType::Ty_Predicate:
136  MIB.addPredicate(Pred);
137  break;
138  case SrcType::Ty_Reg:
139  MIB.addUse(Reg);
140  break;
141  case SrcType::Ty_MIB:
142  MIB.addUse(SrcMIB->getOperand(0).getReg());
143  break;
144  }
145  }
146 
148  switch (Ty) {
149  case SrcType::Ty_Predicate:
150  llvm_unreachable("Not a register operand");
151  case SrcType::Ty_Reg:
152  return MRI.getType(Reg);
153  case SrcType::Ty_MIB:
154  return MRI.getType(SrcMIB->getOperand(0).getReg());
155  }
156  llvm_unreachable("Unrecognised SrcOp::SrcType enum");
157  }
158 
159  unsigned getReg() const {
160  switch (Ty) {
161  case SrcType::Ty_Predicate:
162  llvm_unreachable("Not a register operand");
163  case SrcType::Ty_Reg:
164  return Reg;
165  case SrcType::Ty_MIB:
166  return SrcMIB->getOperand(0).getReg();
167  }
168  llvm_unreachable("Unrecognised SrcOp::SrcType enum");
169  }
170 
172  switch (Ty) {
173  case SrcType::Ty_Predicate:
174  return Pred;
175  default:
176  llvm_unreachable("Not a register operand");
177  }
178  }
179 
180  SrcType getSrcOpKind() const { return Ty; }
181 
182 private:
183  SrcType Ty;
184 };
185 
186 class FlagsOp {
187  Optional<unsigned> Flags;
188 
189 public:
190  explicit FlagsOp(unsigned F) : Flags(F) {}
191  FlagsOp() : Flags(None) {}
192  Optional<unsigned> getFlags() const { return Flags; }
193 };
194 /// Helper class to build MachineInstr.
195 /// It keeps internally the insertion point and debug location for all
196 /// the new instructions we want to create.
197 /// This information can be modify via the related setters.
199 
200  MachineIRBuilderState State;
201 
202 protected:
203  void validateTruncExt(const LLT &Dst, const LLT &Src, bool IsExtend);
204 
205  void validateBinaryOp(const LLT &Res, const LLT &Op0, const LLT &Op1);
206  void validateShiftOp(const LLT &Res, const LLT &Op0, const LLT &Op1);
207 
208  void validateSelectOp(const LLT &ResTy, const LLT &TstTy, const LLT &Op0Ty,
209  const LLT &Op1Ty);
210  void recordInsertion(MachineInstr *MI) const;
211 
212 public:
213  /// Some constructors for easy use.
214  MachineIRBuilder() = default;
217  setInstr(MI);
218  }
219 
220  virtual ~MachineIRBuilder() = default;
221 
222  MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {}
223 
225  assert(State.TII && "TargetInstrInfo is not set");
226  return *State.TII;
227  }
228 
229  /// Getter for the function we currently build.
231  assert(State.MF && "MachineFunction is not set");
232  return *State.MF;
233  }
234 
235  const MachineFunction &getMF() const {
236  assert(State.MF && "MachineFunction is not set");
237  return *State.MF;
238  }
239 
240  const DataLayout &getDataLayout() const {
241  return getMF().getFunction().getParent()->getDataLayout();
242  }
243 
244  /// Getter for DebugLoc
245  const DebugLoc &getDL() { return State.DL; }
246 
247  /// Getter for MRI
248  MachineRegisterInfo *getMRI() { return State.MRI; }
249  const MachineRegisterInfo *getMRI() const { return State.MRI; }
250 
251  /// Getter for the State
252  MachineIRBuilderState &getState() { return State; }
253 
254  /// Getter for the basic block we currently build.
255  const MachineBasicBlock &getMBB() const {
256  assert(State.MBB && "MachineBasicBlock is not set");
257  return *State.MBB;
258  }
259 
261  return const_cast<MachineBasicBlock &>(
262  const_cast<const MachineIRBuilder *>(this)->getMBB());
263  }
264 
265  GISelCSEInfo *getCSEInfo() { return State.CSEInfo; }
266  const GISelCSEInfo *getCSEInfo() const { return State.CSEInfo; }
267 
268  /// Current insertion point for new instructions.
270 
271  /// Set the insertion point before the specified position.
272  /// \pre MBB must be in getMF().
273  /// \pre II must be a valid iterator in MBB.
275  /// @}
276 
277  void setCSEInfo(GISelCSEInfo *Info);
278 
279  /// \name Setters for the insertion point.
280  /// @{
281  /// Set the MachineFunction where to build instructions.
282  void setMF(MachineFunction &MF);
283 
284  /// Set the insertion point to the end of \p MBB.
285  /// \pre \p MBB must be contained by getMF().
286  void setMBB(MachineBasicBlock &MBB);
287 
288  /// Set the insertion point to before MI.
289  /// \pre MI must be in getMF().
290  void setInstr(MachineInstr &MI);
291  /// @}
292 
293  void setChangeObserver(GISelChangeObserver &Observer);
294  void stopObservingChanges();
295  /// @}
296 
297  /// Set the debug location to \p DL for all the next build instructions.
298  void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; }
299 
300  /// Get the current instruction's debug location.
301  DebugLoc getDebugLoc() { return State.DL; }
302 
303  /// Build and insert <empty> = \p Opcode <empty>.
304  /// The insertion point is the one set by the last call of either
305  /// setBasicBlock or setMI.
306  ///
307  /// \pre setBasicBlock or setMI must have been called.
308  ///
309  /// \return a MachineInstrBuilder for the newly created instruction.
310  MachineInstrBuilder buildInstr(unsigned Opcode);
311 
312  /// Build but don't insert <empty> = \p Opcode <empty>.
313  ///
314  /// \pre setMF, setBasicBlock or setMI must have been called.
315  ///
316  /// \return a MachineInstrBuilder for the newly created instruction.
317  MachineInstrBuilder buildInstrNoInsert(unsigned Opcode);
318 
319  /// Insert an existing instruction at the insertion point.
320  MachineInstrBuilder insertInstr(MachineInstrBuilder MIB);
321 
322  /// Build and insert a DBG_VALUE instruction expressing the fact that the
323  /// associated \p Variable lives in \p Reg (suitably modified by \p Expr).
324  MachineInstrBuilder buildDirectDbgValue(unsigned Reg, const MDNode *Variable,
325  const MDNode *Expr);
326 
327  /// Build and insert a DBG_VALUE instruction expressing the fact that the
328  /// associated \p Variable lives in memory at \p Reg (suitably modified by \p
329  /// Expr).
330  MachineInstrBuilder buildIndirectDbgValue(unsigned Reg,
331  const MDNode *Variable,
332  const MDNode *Expr);
333 
334  /// Build and insert a DBG_VALUE instruction expressing the fact that the
335  /// associated \p Variable lives in the stack slot specified by \p FI
336  /// (suitably modified by \p Expr).
337  MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable,
338  const MDNode *Expr);
339 
340  /// Build and insert a DBG_VALUE instructions specifying that \p Variable is
341  /// given by \p C (suitably modified by \p Expr).
342  MachineInstrBuilder buildConstDbgValue(const Constant &C,
343  const MDNode *Variable,
344  const MDNode *Expr);
345 
346  /// Build and insert a DBG_LABEL instructions specifying that \p Label is
347  /// given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label".
348  MachineInstrBuilder buildDbgLabel(const MDNode *Label);
349 
350  /// Build and insert \p Res = G_FRAME_INDEX \p Idx
351  ///
352  /// G_FRAME_INDEX materializes the address of an alloca value or other
353  /// stack-based object.
354  ///
355  /// \pre setBasicBlock or setMI must have been called.
356  /// \pre \p Res must be a generic virtual register with pointer type.
357  ///
358  /// \return a MachineInstrBuilder for the newly created instruction.
359  MachineInstrBuilder buildFrameIndex(unsigned Res, int Idx);
360 
361  /// Build and insert \p Res = G_GLOBAL_VALUE \p GV
362  ///
363  /// G_GLOBAL_VALUE materializes the address of the specified global
364  /// into \p Res.
365  ///
366  /// \pre setBasicBlock or setMI must have been called.
367  /// \pre \p Res must be a generic virtual register with pointer type
368  /// in the same address space as \p GV.
369  ///
370  /// \return a MachineInstrBuilder for the newly created instruction.
371  MachineInstrBuilder buildGlobalValue(unsigned Res, const GlobalValue *GV);
372 
373 
374  /// Build and insert \p Res = G_GEP \p Op0, \p Op1
375  ///
376  /// G_GEP adds \p Op1 bytes to the pointer specified by \p Op0,
377  /// storing the resulting pointer in \p Res.
378  ///
379  /// \pre setBasicBlock or setMI must have been called.
380  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
381  /// type.
382  /// \pre \p Op1 must be a generic virtual register with scalar type.
383  ///
384  /// \return a MachineInstrBuilder for the newly created instruction.
385  MachineInstrBuilder buildGEP(unsigned Res, unsigned Op0,
386  unsigned Op1);
387 
388  /// Materialize and insert \p Res = G_GEP \p Op0, (G_CONSTANT \p Value)
389  ///
390  /// G_GEP adds \p Value bytes to the pointer specified by \p Op0,
391  /// storing the resulting pointer in \p Res. If \p Value is zero then no
392  /// G_GEP or G_CONSTANT will be created and \pre Op0 will be assigned to
393  /// \p Res.
394  ///
395  /// \pre setBasicBlock or setMI must have been called.
396  /// \pre \p Op0 must be a generic virtual register with pointer type.
397  /// \pre \p ValueTy must be a scalar type.
398  /// \pre \p Res must be 0. This is to detect confusion between
399  /// materializeGEP() and buildGEP().
400  /// \post \p Res will either be a new generic virtual register of the same
401  /// type as \p Op0 or \p Op0 itself.
402  ///
403  /// \return a MachineInstrBuilder for the newly created instruction.
404  Optional<MachineInstrBuilder> materializeGEP(unsigned &Res, unsigned Op0,
405  const LLT &ValueTy,
406  uint64_t Value);
407 
408  /// Build and insert \p Res = G_PTR_MASK \p Op0, \p NumBits
409  ///
410  /// G_PTR_MASK clears the low bits of a pointer operand without destroying its
411  /// pointer properties. This has the effect of rounding the address *down* to
412  /// a specified alignment in bits.
413  ///
414  /// \pre setBasicBlock or setMI must have been called.
415  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
416  /// type.
417  /// \pre \p NumBits must be an integer representing the number of low bits to
418  /// be cleared in \p Op0.
419  ///
420  /// \return a MachineInstrBuilder for the newly created instruction.
421  MachineInstrBuilder buildPtrMask(unsigned Res, unsigned Op0,
422  uint32_t NumBits);
423 
424  /// Build and insert \p Res, \p CarryOut = G_UADDO \p Op0, \p Op1
425  ///
426  /// G_UADDO sets \p Res to \p Op0 + \p Op1 (truncated to the bit width) and
427  /// sets \p CarryOut to 1 if the result overflowed in unsigned arithmetic.
428  ///
429  /// \pre setBasicBlock or setMI must have been called.
430  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers with the
431  /// same scalar type.
432  ////\pre \p CarryOut must be generic virtual register with scalar type
433  ///(typically s1)
434  ///
435  /// \return The newly created instruction.
436  MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut,
437  const SrcOp &Op0, const SrcOp &Op1);
438 
439  /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0,
440  /// \p Op1, \p CarryIn
441  ///
442  /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit
443  /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned
444  /// arithmetic.
445  ///
446  /// \pre setBasicBlock or setMI must have been called.
447  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
448  /// with the same scalar type.
449  /// \pre \p CarryOut and \p CarryIn must be generic virtual
450  /// registers with the same scalar type (typically s1)
451  ///
452  /// \return The newly created instruction.
453  MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut,
454  const SrcOp &Op0, const SrcOp &Op1,
455  const SrcOp &CarryIn);
456 
457  /// Build and insert \p Res = G_ANYEXT \p Op0
458  ///
459  /// G_ANYEXT produces a register of the specified width, with bits 0 to
460  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified
461  /// (i.e. this is neither zero nor sign-extension). For a vector register,
462  /// each element is extended individually.
463  ///
464  /// \pre setBasicBlock or setMI must have been called.
465  /// \pre \p Res must be a generic virtual register with scalar or vector type.
466  /// \pre \p Op must be a generic virtual register with scalar or vector type.
467  /// \pre \p Op must be smaller than \p Res
468  ///
469  /// \return The newly created instruction.
470 
471  MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);
472 
473  /// Build and insert \p Res = G_SEXT \p Op
474  ///
475  /// G_SEXT produces a register of the specified width, with bits 0 to
476  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the
477  /// high bit of \p Op (i.e. 2s-complement sign extended).
478  ///
479  /// \pre setBasicBlock or setMI must have been called.
480  /// \pre \p Res must be a generic virtual register with scalar or vector type.
481  /// \pre \p Op must be a generic virtual register with scalar or vector type.
482  /// \pre \p Op must be smaller than \p Res
483  ///
484  /// \return The newly created instruction.
485  MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op);
486 
487  /// Build and insert a G_PTRTOINT instruction.
488  MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src) {
489  return buildInstr(TargetOpcode::G_PTRTOINT, {Dst}, {Src});
490  }
491 
492  /// Build and insert \p Dst = G_BITCAST \p Src
493  MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) {
494  return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src});
495  }
496 
497  /// \return The opcode of the extension the target wants to use for boolean
498  /// values.
499  unsigned getBoolExtOp(bool IsVec, bool IsFP) const;
500 
501  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_SEXT \p Op, or \p Res
502  // = G_ZEXT \p Op depending on how the target wants to extend boolean values.
503  MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op,
504  bool IsFP);
505 
506  /// Build and insert \p Res = G_ZEXT \p Op
507  ///
508  /// G_ZEXT produces a register of the specified width, with bits 0 to
509  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector
510  /// register, each element is extended individually.
511  ///
512  /// \pre setBasicBlock or setMI must have been called.
513  /// \pre \p Res must be a generic virtual register with scalar or vector type.
514  /// \pre \p Op must be a generic virtual register with scalar or vector type.
515  /// \pre \p Op must be smaller than \p Res
516  ///
517  /// \return The newly created instruction.
518  MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op);
519 
520  /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or
521  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
522  /// ///
523  /// \pre setBasicBlock or setMI must have been called.
524  /// \pre \p Res must be a generic virtual register with scalar or vector type.
525  /// \pre \p Op must be a generic virtual register with scalar or vector type.
526  ///
527  /// \return The newly created instruction.
528  MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op);
529 
530  /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or
531  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
532  /// ///
533  /// \pre setBasicBlock or setMI must have been called.
534  /// \pre \p Res must be a generic virtual register with scalar or vector type.
535  /// \pre \p Op must be a generic virtual register with scalar or vector type.
536  ///
537  /// \return The newly created instruction.
538  MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op);
539 
540  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or
541  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
542  /// ///
543  /// \pre setBasicBlock or setMI must have been called.
544  /// \pre \p Res must be a generic virtual register with scalar or vector type.
545  /// \pre \p Op must be a generic virtual register with scalar or vector type.
546  ///
547  /// \return The newly created instruction.
548  MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op);
549 
550  /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p
551  /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and
552  /// \p Op.
553  /// ///
554  /// \pre setBasicBlock or setMI must have been called.
555  /// \pre \p Res must be a generic virtual register with scalar or vector type.
556  /// \pre \p Op must be a generic virtual register with scalar or vector type.
557  ///
558  /// \return The newly created instruction.
559  MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
560  const SrcOp &Op);
561 
562  /// Build and insert an appropriate cast between two registers of equal size.
563  MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src);
564 
565  /// Build and insert G_BR \p Dest
566  ///
567  /// G_BR is an unconditional branch to \p Dest.
568  ///
569  /// \pre setBasicBlock or setMI must have been called.
570  ///
571  /// \return a MachineInstrBuilder for the newly created instruction.
572  MachineInstrBuilder buildBr(MachineBasicBlock &Dest);
573 
574  /// Build and insert G_BRCOND \p Tst, \p Dest
575  ///
576  /// G_BRCOND is a conditional branch to \p Dest.
577  ///
578  /// \pre setBasicBlock or setMI must have been called.
579  /// \pre \p Tst must be a generic virtual register with scalar
580  /// type. At the beginning of legalization, this will be a single
581  /// bit (s1). Targets with interesting flags registers may change
582  /// this. For a wider type, whether the branch is taken must only
583  /// depend on bit 0 (for now).
584  ///
585  /// \return The newly created instruction.
586  MachineInstrBuilder buildBrCond(unsigned Tst, MachineBasicBlock &Dest);
587 
588  /// Build and insert G_BRINDIRECT \p Tgt
589  ///
590  /// G_BRINDIRECT is an indirect branch to \p Tgt.
591  ///
592  /// \pre setBasicBlock or setMI must have been called.
593  /// \pre \p Tgt must be a generic virtual register with pointer type.
594  ///
595  /// \return a MachineInstrBuilder for the newly created instruction.
596  MachineInstrBuilder buildBrIndirect(unsigned Tgt);
597 
598  /// Build and insert \p Res = G_CONSTANT \p Val
599  ///
600  /// G_CONSTANT is an integer constant with the specified size and value. \p
601  /// Val will be extended or truncated to the size of \p Reg.
602  ///
603  /// \pre setBasicBlock or setMI must have been called.
604  /// \pre \p Res must be a generic virtual register with scalar or pointer
605  /// type.
606  ///
607  /// \return The newly created instruction.
608  virtual MachineInstrBuilder buildConstant(const DstOp &Res,
609  const ConstantInt &Val);
610 
611  /// Build and insert \p Res = G_CONSTANT \p Val
612  ///
613  /// G_CONSTANT is an integer constant with the specified size and value.
614  ///
615  /// \pre setBasicBlock or setMI must have been called.
616  /// \pre \p Res must be a generic virtual register with scalar type.
617  ///
618  /// \return The newly created instruction.
619  MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val);
620  MachineInstrBuilder buildConstant(const DstOp &Res, const APInt &Val);
621 
622  /// Build and insert \p Res = G_FCONSTANT \p Val
623  ///
624  /// G_FCONSTANT is a floating-point constant with the specified size and
625  /// value.
626  ///
627  /// \pre setBasicBlock or setMI must have been called.
628  /// \pre \p Res must be a generic virtual register with scalar type.
629  ///
630  /// \return The newly created instruction.
631  virtual MachineInstrBuilder buildFConstant(const DstOp &Res,
632  const ConstantFP &Val);
633 
634  MachineInstrBuilder buildFConstant(const DstOp &Res, double Val);
635  MachineInstrBuilder buildFConstant(const DstOp &Res, const APFloat &Val);
636 
637  /// Build and insert \p Res = COPY Op
638  ///
639  /// Register-to-register COPY sets \p Res to \p Op.
640  ///
641  /// \pre setBasicBlock or setMI must have been called.
642  ///
643  /// \return a MachineInstrBuilder for the newly created instruction.
644  MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);
645 
646  /// Build and insert `Res = G_LOAD Addr, MMO`.
647  ///
648  /// Loads the value stored at \p Addr. Puts the result in \p Res.
649  ///
650  /// \pre setBasicBlock or setMI must have been called.
651  /// \pre \p Res must be a generic virtual register.
652  /// \pre \p Addr must be a generic virtual register with pointer type.
653  ///
654  /// \return a MachineInstrBuilder for the newly created instruction.
655  MachineInstrBuilder buildLoad(unsigned Res, unsigned Addr,
656  MachineMemOperand &MMO);
657 
658  /// Build and insert `Res = <opcode> Addr, MMO`.
659  ///
660  /// Loads the value stored at \p Addr. Puts the result in \p Res.
661  ///
662  /// \pre setBasicBlock or setMI must have been called.
663  /// \pre \p Res must be a generic virtual register.
664  /// \pre \p Addr must be a generic virtual register with pointer type.
665  ///
666  /// \return a MachineInstrBuilder for the newly created instruction.
667  MachineInstrBuilder buildLoadInstr(unsigned Opcode, unsigned Res,
668  unsigned Addr, MachineMemOperand &MMO);
669 
670  /// Build and insert `G_STORE Val, Addr, MMO`.
671  ///
672  /// Stores the value \p Val to \p Addr.
673  ///
674  /// \pre setBasicBlock or setMI must have been called.
675  /// \pre \p Val must be a generic virtual register.
676  /// \pre \p Addr must be a generic virtual register with pointer type.
677  ///
678  /// \return a MachineInstrBuilder for the newly created instruction.
679  MachineInstrBuilder buildStore(unsigned Val, unsigned Addr,
680  MachineMemOperand &MMO);
681 
682  /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.
683  ///
684  /// \pre setBasicBlock or setMI must have been called.
685  /// \pre \p Res and \p Src must be generic virtual registers.
686  ///
687  /// \return a MachineInstrBuilder for the newly created instruction.
688  MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index);
689 
690  /// Build and insert \p Res = IMPLICIT_DEF.
691  MachineInstrBuilder buildUndef(const DstOp &Res);
692 
693  /// Build and insert instructions to put \p Ops together at the specified p
694  /// Indices to form a larger register.
695  ///
696  /// If the types of the input registers are uniform and cover the entirity of
697  /// \p Res then a G_MERGE_VALUES will be produced. Otherwise an IMPLICIT_DEF
698  /// followed by a sequence of G_INSERT instructions.
699  ///
700  /// \pre setBasicBlock or setMI must have been called.
701  /// \pre The final element of the sequence must not extend past the end of the
702  /// destination register.
703  /// \pre The bits defined by each Op (derived from index and scalar size) must
704  /// not overlap.
705  /// \pre \p Indices must be in ascending order of bit position.
706  void buildSequence(unsigned Res, ArrayRef<unsigned> Ops,
707  ArrayRef<uint64_t> Indices);
708 
709  /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
710  ///
711  /// G_MERGE_VALUES combines the input elements contiguously into a larger
712  /// register.
713  ///
714  /// \pre setBasicBlock or setMI must have been called.
715  /// \pre The entire register \p Res (and no more) must be covered by the input
716  /// registers.
717  /// \pre The type of all \p Ops registers must be identical.
718  ///
719  /// \return a MachineInstrBuilder for the newly created instruction.
720  MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef<unsigned> Ops);
721 
722  /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op
723  ///
724  /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple
725  ///
726  /// \pre setBasicBlock or setMI must have been called.
727  /// \pre The entire register \p Res (and no more) must be covered by the input
728  /// registers.
729  /// \pre The type of all \p Res registers must be identical.
730  ///
731  /// \return a MachineInstrBuilder for the newly created instruction.
732  MachineInstrBuilder buildUnmerge(ArrayRef<LLT> Res, const SrcOp &Op);
733  MachineInstrBuilder buildUnmerge(ArrayRef<unsigned> Res, const SrcOp &Op);
734 
735  /// Build and insert an unmerge of \p Res sized pieces to cover \p Op
736  MachineInstrBuilder buildUnmerge(LLT Res, const SrcOp &Op);
737 
738  /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ...
739  ///
740  /// G_BUILD_VECTOR creates a vector value from multiple scalar registers.
741  /// \pre setBasicBlock or setMI must have been called.
742  /// \pre The entire register \p Res (and no more) must be covered by the
743  /// input scalar registers.
744  /// \pre The type of all \p Ops registers must be identical.
745  ///
746  /// \return a MachineInstrBuilder for the newly created instruction.
747  MachineInstrBuilder buildBuildVector(const DstOp &Res,
748  ArrayRef<unsigned> Ops);
749 
750  /// Build and insert \p Res = G_BUILD_VECTOR with \p Src replicated to fill
751  /// the number of elements
752  MachineInstrBuilder buildSplatVector(const DstOp &Res,
753  const SrcOp &Src);
754 
755  /// Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ...
756  ///
757  /// G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers
758  /// which have types larger than the destination vector element type, and
759  /// truncates the values to fit.
760  ///
761  /// If the operands given are already the same size as the vector elt type,
762  /// then this method will instead create a G_BUILD_VECTOR instruction.
763  ///
764  /// \pre setBasicBlock or setMI must have been called.
765  /// \pre The type of all \p Ops registers must be identical.
766  ///
767  /// \return a MachineInstrBuilder for the newly created instruction.
768  MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res,
769  ArrayRef<unsigned> Ops);
770 
771  /// Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ...
772  ///
773  /// G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more
774  /// vectors.
775  ///
776  /// \pre setBasicBlock or setMI must have been called.
777  /// \pre The entire register \p Res (and no more) must be covered by the input
778  /// registers.
779  /// \pre The type of all source operands must be identical.
780  ///
781  /// \return a MachineInstrBuilder for the newly created instruction.
782  MachineInstrBuilder buildConcatVectors(const DstOp &Res,
783  ArrayRef<unsigned> Ops);
784 
785  MachineInstrBuilder buildInsert(unsigned Res, unsigned Src,
786  unsigned Op, unsigned Index);
787 
788  /// Build and insert either a G_INTRINSIC (if \p HasSideEffects is false) or
789  /// G_INTRINSIC_W_SIDE_EFFECTS instruction. Its first operand will be the
790  /// result register definition unless \p Reg is NoReg (== 0). The second
791  /// operand will be the intrinsic's ID.
792  ///
793  /// Callers are expected to add the required definitions and uses afterwards.
794  ///
795  /// \pre setBasicBlock or setMI must have been called.
796  ///
797  /// \return a MachineInstrBuilder for the newly created instruction.
799  bool HasSideEffects);
800  MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<DstOp> Res,
801  bool HasSideEffects);
802 
803  /// Build and insert \p Res = G_FPTRUNC \p Op
804  ///
805  /// G_FPTRUNC converts a floating-point value into one with a smaller type.
806  ///
807  /// \pre setBasicBlock or setMI must have been called.
808  /// \pre \p Res must be a generic virtual register with scalar or vector type.
809  /// \pre \p Op must be a generic virtual register with scalar or vector type.
810  /// \pre \p Res must be smaller than \p Op
811  ///
812  /// \return The newly created instruction.
813  MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op);
814 
815  /// Build and insert \p Res = G_TRUNC \p Op
816  ///
817  /// G_TRUNC extracts the low bits of a type. For a vector type each element is
818  /// truncated independently before being packed into the destination.
819  ///
820  /// \pre setBasicBlock or setMI must have been called.
821  /// \pre \p Res must be a generic virtual register with scalar or vector type.
822  /// \pre \p Op must be a generic virtual register with scalar or vector type.
823  /// \pre \p Res must be smaller than \p Op
824  ///
825  /// \return The newly created instruction.
826  MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op);
827 
828  /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1
829  ///
830  /// \pre setBasicBlock or setMI must have been called.
831 
832  /// \pre \p Res must be a generic virtual register with scalar or
833  /// vector type. Typically this starts as s1 or <N x s1>.
834  /// \pre \p Op0 and Op1 must be generic virtual registers with the
835  /// same number of elements as \p Res. If \p Res is a scalar,
836  /// \p Op0 must be either a scalar or pointer.
837  /// \pre \p Pred must be an integer predicate.
838  ///
839  /// \return a MachineInstrBuilder for the newly created instruction.
840  MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res,
841  const SrcOp &Op0, const SrcOp &Op1);
842 
843  /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1
844  ///
845  /// \pre setBasicBlock or setMI must have been called.
846 
847  /// \pre \p Res must be a generic virtual register with scalar or
848  /// vector type. Typically this starts as s1 or <N x s1>.
849  /// \pre \p Op0 and Op1 must be generic virtual registers with the
850  /// same number of elements as \p Res (or scalar, if \p Res is
851  /// scalar).
852  /// \pre \p Pred must be a floating-point predicate.
853  ///
854  /// \return a MachineInstrBuilder for the newly created instruction.
855  MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res,
856  const SrcOp &Op0, const SrcOp &Op1);
857 
858  /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1
859  ///
860  /// \pre setBasicBlock or setMI must have been called.
861  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
862  /// with the same type.
863  /// \pre \p Tst must be a generic virtual register with scalar, pointer or
864  /// vector type. If vector then it must have the same number of
865  /// elements as the other parameters.
866  ///
867  /// \return a MachineInstrBuilder for the newly created instruction.
868  MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,
869  const SrcOp &Op0, const SrcOp &Op1);
870 
871  /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val,
872  /// \p Elt, \p Idx
873  ///
874  /// \pre setBasicBlock or setMI must have been called.
875  /// \pre \p Res and \p Val must be a generic virtual register
876  // with the same vector type.
877  /// \pre \p Elt and \p Idx must be a generic virtual register
878  /// with scalar type.
879  ///
880  /// \return The newly created instruction.
881  MachineInstrBuilder buildInsertVectorElement(const DstOp &Res,
882  const SrcOp &Val,
883  const SrcOp &Elt,
884  const SrcOp &Idx);
885 
886  /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
887  ///
888  /// \pre setBasicBlock or setMI must have been called.
889  /// \pre \p Res must be a generic virtual register with scalar type.
890  /// \pre \p Val must be a generic virtual register with vector type.
891  /// \pre \p Idx must be a generic virtual register with scalar type.
892  ///
893  /// \return The newly created instruction.
894  MachineInstrBuilder buildExtractVectorElement(const DstOp &Res,
895  const SrcOp &Val,
896  const SrcOp &Idx);
897 
898  /// Build and insert `OldValRes<def>, SuccessRes<def> =
899  /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`.
900  ///
901  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
902  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
903  /// Addr in \p Res, along with an s1 indicating whether it was replaced.
904  ///
905  /// \pre setBasicBlock or setMI must have been called.
906  /// \pre \p OldValRes must be a generic virtual register of scalar type.
907  /// \pre \p SuccessRes must be a generic virtual register of scalar type. It
908  /// will be assigned 0 on failure and 1 on success.
909  /// \pre \p Addr must be a generic virtual register with pointer type.
910  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
911  /// registers of the same type.
912  ///
913  /// \return a MachineInstrBuilder for the newly created instruction.
915  buildAtomicCmpXchgWithSuccess(unsigned OldValRes, unsigned SuccessRes,
916  unsigned Addr, unsigned CmpVal, unsigned NewVal,
917  MachineMemOperand &MMO);
918 
919  /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal,
920  /// MMO`.
921  ///
922  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
923  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
924  /// Addr in \p Res.
925  ///
926  /// \pre setBasicBlock or setMI must have been called.
927  /// \pre \p OldValRes must be a generic virtual register of scalar type.
928  /// \pre \p Addr must be a generic virtual register with pointer type.
929  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
930  /// registers of the same type.
931  ///
932  /// \return a MachineInstrBuilder for the newly created instruction.
933  MachineInstrBuilder buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr,
934  unsigned CmpVal, unsigned NewVal,
935  MachineMemOperand &MMO);
936 
937  /// Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`.
938  ///
939  /// Atomically read-modify-update the value at \p Addr with \p Val. Puts the
940  /// original value from \p Addr in \p OldValRes. The modification is
941  /// determined by the opcode.
942  ///
943  /// \pre setBasicBlock or setMI must have been called.
944  /// \pre \p OldValRes must be a generic virtual register.
945  /// \pre \p Addr must be a generic virtual register with pointer type.
946  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
947  /// same type.
948  ///
949  /// \return a MachineInstrBuilder for the newly created instruction.
950  MachineInstrBuilder buildAtomicRMW(unsigned Opcode, unsigned OldValRes,
951  unsigned Addr, unsigned Val,
952  MachineMemOperand &MMO);
953 
954  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`.
955  ///
956  /// Atomically replace the value at \p Addr with \p Val. Puts the original
957  /// value from \p Addr in \p OldValRes.
958  ///
959  /// \pre setBasicBlock or setMI must have been called.
960  /// \pre \p OldValRes must be a generic virtual register.
961  /// \pre \p Addr must be a generic virtual register with pointer type.
962  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
963  /// same type.
964  ///
965  /// \return a MachineInstrBuilder for the newly created instruction.
966  MachineInstrBuilder buildAtomicRMWXchg(unsigned OldValRes, unsigned Addr,
967  unsigned Val, MachineMemOperand &MMO);
968 
969  /// Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`.
970  ///
971  /// Atomically replace the value at \p Addr with the addition of \p Val and
972  /// the original value. Puts the original value from \p Addr in \p OldValRes.
973  ///
974  /// \pre setBasicBlock or setMI must have been called.
975  /// \pre \p OldValRes must be a generic virtual register.
976  /// \pre \p Addr must be a generic virtual register with pointer type.
977  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
978  /// same type.
979  ///
980  /// \return a MachineInstrBuilder for the newly created instruction.
981  MachineInstrBuilder buildAtomicRMWAdd(unsigned OldValRes, unsigned Addr,
982  unsigned Val, MachineMemOperand &MMO);
983 
984  /// Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`.
985  ///
986  /// Atomically replace the value at \p Addr with the subtraction of \p Val and
987  /// the original value. Puts the original value from \p Addr in \p OldValRes.
988  ///
989  /// \pre setBasicBlock or setMI must have been called.
990  /// \pre \p OldValRes must be a generic virtual register.
991  /// \pre \p Addr must be a generic virtual register with pointer type.
992  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
993  /// same type.
994  ///
995  /// \return a MachineInstrBuilder for the newly created instruction.
996  MachineInstrBuilder buildAtomicRMWSub(unsigned OldValRes, unsigned Addr,
997  unsigned Val, MachineMemOperand &MMO);
998 
999  /// Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`.
1000  ///
1001  /// Atomically replace the value at \p Addr with the bitwise and of \p Val and
1002  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1003  ///
1004  /// \pre setBasicBlock or setMI must have been called.
1005  /// \pre \p OldValRes must be a generic virtual register.
1006  /// \pre \p Addr must be a generic virtual register with pointer type.
1007  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1008  /// same type.
1009  ///
1010  /// \return a MachineInstrBuilder for the newly created instruction.
1011  MachineInstrBuilder buildAtomicRMWAnd(unsigned OldValRes, unsigned Addr,
1012  unsigned Val, MachineMemOperand &MMO);
1013 
1014  /// Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`.
1015  ///
1016  /// Atomically replace the value at \p Addr with the bitwise nand of \p Val
1017  /// and the original value. Puts the original value from \p Addr in \p
1018  /// OldValRes.
1019  ///
1020  /// \pre setBasicBlock or setMI must have been called.
1021  /// \pre \p OldValRes must be a generic virtual register.
1022  /// \pre \p Addr must be a generic virtual register with pointer type.
1023  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1024  /// same type.
1025  ///
1026  /// \return a MachineInstrBuilder for the newly created instruction.
1027  MachineInstrBuilder buildAtomicRMWNand(unsigned OldValRes, unsigned Addr,
1028  unsigned Val, MachineMemOperand &MMO);
1029 
1030  /// Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`.
1031  ///
1032  /// Atomically replace the value at \p Addr with the bitwise or of \p Val and
1033  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1034  ///
1035  /// \pre setBasicBlock or setMI must have been called.
1036  /// \pre \p OldValRes must be a generic virtual register.
1037  /// \pre \p Addr must be a generic virtual register with pointer type.
1038  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1039  /// same type.
1040  ///
1041  /// \return a MachineInstrBuilder for the newly created instruction.
1042  MachineInstrBuilder buildAtomicRMWOr(unsigned OldValRes, unsigned Addr,
1043  unsigned Val, MachineMemOperand &MMO);
1044 
1045  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`.
1046  ///
1047  /// Atomically replace the value at \p Addr with the bitwise xor of \p Val and
1048  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1049  ///
1050  /// \pre setBasicBlock or setMI must have been called.
1051  /// \pre \p OldValRes must be a generic virtual register.
1052  /// \pre \p Addr must be a generic virtual register with pointer type.
1053  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1054  /// same type.
1055  ///
1056  /// \return a MachineInstrBuilder for the newly created instruction.
1057  MachineInstrBuilder buildAtomicRMWXor(unsigned OldValRes, unsigned Addr,
1058  unsigned Val, MachineMemOperand &MMO);
1059 
1060  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`.
1061  ///
1062  /// Atomically replace the value at \p Addr with the signed maximum of \p
1063  /// Val and the original value. Puts the original value from \p Addr in \p
1064  /// OldValRes.
1065  ///
1066  /// \pre setBasicBlock or setMI must have been called.
1067  /// \pre \p OldValRes must be a generic virtual register.
1068  /// \pre \p Addr must be a generic virtual register with pointer type.
1069  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1070  /// same type.
1071  ///
1072  /// \return a MachineInstrBuilder for the newly created instruction.
1073  MachineInstrBuilder buildAtomicRMWMax(unsigned OldValRes, unsigned Addr,
1074  unsigned Val, MachineMemOperand &MMO);
1075 
1076  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`.
1077  ///
1078  /// Atomically replace the value at \p Addr with the signed minimum of \p
1079  /// Val and the original value. Puts the original value from \p Addr in \p
1080  /// OldValRes.
1081  ///
1082  /// \pre setBasicBlock or setMI must have been called.
1083  /// \pre \p OldValRes must be a generic virtual register.
1084  /// \pre \p Addr must be a generic virtual register with pointer type.
1085  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1086  /// same type.
1087  ///
1088  /// \return a MachineInstrBuilder for the newly created instruction.
1089  MachineInstrBuilder buildAtomicRMWMin(unsigned OldValRes, unsigned Addr,
1090  unsigned Val, MachineMemOperand &MMO);
1091 
1092  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`.
1093  ///
1094  /// Atomically replace the value at \p Addr with the unsigned maximum of \p
1095  /// Val and the original value. Puts the original value from \p Addr in \p
1096  /// OldValRes.
1097  ///
1098  /// \pre setBasicBlock or setMI must have been called.
1099  /// \pre \p OldValRes must be a generic virtual register.
1100  /// \pre \p Addr must be a generic virtual register with pointer type.
1101  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1102  /// same type.
1103  ///
1104  /// \return a MachineInstrBuilder for the newly created instruction.
1105  MachineInstrBuilder buildAtomicRMWUmax(unsigned OldValRes, unsigned Addr,
1106  unsigned Val, MachineMemOperand &MMO);
1107 
1108  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`.
1109  ///
1110  /// Atomically replace the value at \p Addr with the unsigned minimum of \p
1111  /// Val and the original value. Puts the original value from \p Addr in \p
1112  /// OldValRes.
1113  ///
1114  /// \pre setBasicBlock or setMI must have been called.
1115  /// \pre \p OldValRes must be a generic virtual register.
1116  /// \pre \p Addr must be a generic virtual register with pointer type.
1117  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1118  /// same type.
1119  ///
1120  /// \return a MachineInstrBuilder for the newly created instruction.
1121  MachineInstrBuilder buildAtomicRMWUmin(unsigned OldValRes, unsigned Addr,
1122  unsigned Val, MachineMemOperand &MMO);
1123 
1124  /// Build and insert \p Res = G_BLOCK_ADDR \p BA
1125  ///
1126  /// G_BLOCK_ADDR computes the address of a basic block.
1127  ///
1128  /// \pre setBasicBlock or setMI must have been called.
1129  /// \pre \p Res must be a generic virtual register of a pointer type.
1130  ///
1131  /// \return The newly created instruction.
1132  MachineInstrBuilder buildBlockAddress(unsigned Res, const BlockAddress *BA);
1133 
1134  /// Build and insert \p Res = G_ADD \p Op0, \p Op1
1135  ///
1136  /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1137  /// truncated to their width.
1138  ///
1139  /// \pre setBasicBlock or setMI must have been called.
1140  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1141  /// with the same (scalar or vector) type).
1142  ///
1143  /// \return a MachineInstrBuilder for the newly created instruction.
1144 
1145  MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,
1146  const SrcOp &Src1,
1147  Optional<unsigned> Flags = None) {
1148  return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1149  }
1150 
1151  /// Build and insert \p Res = G_SUB \p Op0, \p Op1
1152  ///
1153  /// G_SUB sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1154  /// truncated to their width.
1155  ///
1156  /// \pre setBasicBlock or setMI must have been called.
1157  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1158  /// with the same (scalar or vector) type).
1159  ///
1160  /// \return a MachineInstrBuilder for the newly created instruction.
1161 
1162  MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0,
1163  const SrcOp &Src1,
1164  Optional<unsigned> Flags = None) {
1165  return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1166  }
1167 
1168  /// Build and insert \p Res = G_MUL \p Op0, \p Op1
1169  ///
1170  /// G_MUL sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1171  /// truncated to their width.
1172  ///
1173  /// \pre setBasicBlock or setMI must have been called.
1174  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1175  /// with the same (scalar or vector) type).
1176  ///
1177  /// \return a MachineInstrBuilder for the newly created instruction.
1178  MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
1179  const SrcOp &Src1,
1180  Optional<unsigned> Flags = None) {
1181  return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1182  }
1183 
1184  MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0,
1185  const SrcOp &Src1,
1186  Optional<unsigned> Flags = None) {
1187  return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags);
1188  }
1189 
1190  MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0,
1191  const SrcOp &Src1,
1192  Optional<unsigned> Flags = None) {
1193  return buildInstr(TargetOpcode::G_SMULH, {Dst}, {Src0, Src1}, Flags);
1194  }
1195 
1196  MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0,
1197  const SrcOp &Src1,
1198  Optional<unsigned> Flags = None) {
1199  return buildInstr(TargetOpcode::G_SHL, {Dst}, {Src0, Src1}, Flags);
1200  }
1201 
1202  MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0,
1203  const SrcOp &Src1,
1204  Optional<unsigned> Flags = None) {
1205  return buildInstr(TargetOpcode::G_LSHR, {Dst}, {Src0, Src1}, Flags);
1206  }
1207 
1208  MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0,
1209  const SrcOp &Src1,
1210  Optional<unsigned> Flags = None) {
1211  return buildInstr(TargetOpcode::G_ASHR, {Dst}, {Src0, Src1}, Flags);
1212  }
1213 
1214  /// Build and insert \p Res = G_AND \p Op0, \p Op1
1215  ///
1216  /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p
1217  /// Op1.
1218  ///
1219  /// \pre setBasicBlock or setMI must have been called.
1220  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1221  /// with the same (scalar or vector) type).
1222  ///
1223  /// \return a MachineInstrBuilder for the newly created instruction.
1224 
1225  MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0,
1226  const SrcOp &Src1) {
1227  return buildInstr(TargetOpcode::G_AND, {Dst}, {Src0, Src1});
1228  }
1229 
1230  /// Build and insert \p Res = G_OR \p Op0, \p Op1
1231  ///
1232  /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
1233  /// Op1.
1234  ///
1235  /// \pre setBasicBlock or setMI must have been called.
1236  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1237  /// with the same (scalar or vector) type).
1238  ///
1239  /// \return a MachineInstrBuilder for the newly created instruction.
1240  MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0,
1241  const SrcOp &Src1) {
1242  return buildInstr(TargetOpcode::G_OR, {Dst}, {Src0, Src1});
1243  }
1244 
1245  /// Build and insert \p Res = G_XOR \p Op0, \p Op1
1246  MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0,
1247  const SrcOp &Src1) {
1248  return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, Src1});
1249  }
1250 
1251  /// Build and insert a bitwise not,
1252  /// \p NegOne = G_CONSTANT -1
1253  /// \p Res = G_OR \p Op0, NegOne
1254  MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) {
1255  auto NegOne = buildConstant(Dst.getLLTTy(*getMRI()), -1);
1256  return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, NegOne});
1257  }
1258 
1259  /// Build and insert \p Res = G_CTPOP \p Op0, \p Src0
1260  MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0) {
1261  return buildInstr(TargetOpcode::G_CTPOP, {Dst}, {Src0});
1262  }
1263 
1264  /// Build and insert \p Res = G_CTLZ \p Op0, \p Src0
1265  MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0) {
1266  return buildInstr(TargetOpcode::G_CTLZ, {Dst}, {Src0});
1267  }
1268 
1269  /// Build and insert \p Res = G_CTLZ_ZERO_UNDEF \p Op0, \p Src0
1271  return buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {Dst}, {Src0});
1272  }
1273 
1274  /// Build and insert \p Res = G_CTTZ \p Op0, \p Src0
1275  MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0) {
1276  return buildInstr(TargetOpcode::G_CTTZ, {Dst}, {Src0});
1277  }
1278 
1279  /// Build and insert \p Res = G_CTTZ_ZERO_UNDEF \p Op0, \p Src0
1281  return buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, {Dst}, {Src0});
1282  }
1283 
1284  /// Build and insert \p Res = G_FADD \p Op0, \p Op1
1285  MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0,
1286  const SrcOp &Src1) {
1287  return buildInstr(TargetOpcode::G_FADD, {Dst}, {Src0, Src1});
1288  }
1289 
1290  /// Build and insert \p Res = G_FSUB \p Op0, \p Op1
1291  MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0,
1292  const SrcOp &Src1) {
1293  return buildInstr(TargetOpcode::G_FSUB, {Dst}, {Src0, Src1});
1294  }
1295 
1296  /// Build and insert \p Res = G_FMA \p Op0, \p Op1, \p Op2
1297  MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0,
1298  const SrcOp &Src1, const SrcOp &Src2) {
1299  return buildInstr(TargetOpcode::G_FMA, {Dst}, {Src0, Src1, Src2});
1300  }
1301 
1302  /// Build and insert \p Res = G_FNEG \p Op0
1303  MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0) {
1304  return buildInstr(TargetOpcode::G_FNEG, {Dst}, {Src0});
1305  }
1306 
1307  /// Build and insert \p Res = G_FABS \p Op0
1308  MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0) {
1309  return buildInstr(TargetOpcode::G_FABS, {Dst}, {Src0});
1310  }
1311 
1312  /// Build and insert \p Res = G_FCOPYSIGN \p Op0, \p Op1
1314  const SrcOp &Src1) {
1315  return buildInstr(TargetOpcode::G_FCOPYSIGN, {Dst}, {Src0, Src1});
1316  }
1317 
1318  /// Build and insert \p Res = G_UITOFP \p Src0
1319  MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0) {
1320  return buildInstr(TargetOpcode::G_UITOFP, {Dst}, {Src0});
1321  }
1322 
1323  /// Build and insert \p Res = G_SITOFP \p Src0
1324  MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0) {
1325  return buildInstr(TargetOpcode::G_SITOFP, {Dst}, {Src0});
1326  }
1327 
1328  /// Build and insert \p Res = G_FPTOUI \p Src0
1329  MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0) {
1330  return buildInstr(TargetOpcode::G_FPTOUI, {Dst}, {Src0});
1331  }
1332 
1333  /// Build and insert \p Res = G_FPTOSI \p Src0
1334  MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0) {
1335  return buildInstr(TargetOpcode::G_FPTOSI, {Dst}, {Src0});
1336  }
1337 
1338  /// Build and insert \p Res = G_SMIN \p Op0, \p Op1
1339  MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0,
1340  const SrcOp &Src1) {
1341  return buildInstr(TargetOpcode::G_SMIN, {Dst}, {Src0, Src1});
1342  }
1343 
1344  /// Build and insert \p Res = G_SMAX \p Op0, \p Op1
1345  MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0,
1346  const SrcOp &Src1) {
1347  return buildInstr(TargetOpcode::G_SMAX, {Dst}, {Src0, Src1});
1348  }
1349 
1350  /// Build and insert \p Res = G_UMIN \p Op0, \p Op1
1351  MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0,
1352  const SrcOp &Src1) {
1353  return buildInstr(TargetOpcode::G_UMIN, {Dst}, {Src0, Src1});
1354  }
1355 
1356  /// Build and insert \p Res = G_UMAX \p Op0, \p Op1
1357  MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0,
1358  const SrcOp &Src1) {
1359  return buildInstr(TargetOpcode::G_UMAX, {Dst}, {Src0, Src1});
1360  }
1361 
1362  virtual MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
1363  ArrayRef<SrcOp> SrcOps,
1364  Optional<unsigned> Flags = None);
1365 };
1366 
1367 } // End namespace llvm.
1368 #endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
MachineBasicBlock & getMBB()
uint64_t CallInst * C
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
const TargetRegisterClass * RC
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
The CSE Analysis object.
Definition: CSEInfo.h:71
MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_XOR Op0, Op1.
CmpInst::Predicate Pred
unsigned getReg() const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
DstType getDstOpKind() const
MachineIRBuilder(const MachineIRBuilderState &BState)
GISelChangeObserver * Observer
unsigned Reg
void setDebugLoc(const DebugLoc &DL)
Set the debug location to DL for all the next build instructions.
const MachineFunction & getMF() const
MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_OR Op0, Op1.
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
void addSrcToMIB(MachineInstrBuilder &MIB) const
const MachineInstrBuilder & addPredicate(CmpInst::Predicate Pred) const
A debug info location.
Definition: DebugLoc.h:33
Metadata node.
Definition: Metadata.h:863
F(f)
MachineIRBuilder(MachineInstr &MI)
MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2)
Build and insert Res = G_FMA Op0, Op1, Op2.
The address of a basic block.
Definition: Constants.h:839
MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ Op0, Src0.
A description of a memory reference used in the backend.
MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ_ZERO_UNDEF Op0, Src0.
GISelCSEInfo * getCSEInfo()
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
MachineBasicBlock::iterator II
SrcType getSrcOpKind() const
DstOp(const TargetRegisterClass *TRC)
DstOp(unsigned R)
MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_SITOFP Src0.
MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_FSUB Op0, Op1.
SrcOp(const CmpInst::Predicate P)
MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FNEG Op0.
MachineFunction & getMF()
Getter for the function we currently build.
MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_SUB Op0, Op1.
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Optional< unsigned > getFlags() const
TargetInstrInfo - Interface to description of machine instruction set.
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
#define P(N)
MachineRegisterInfo * getMRI()
Getter for MRI.
Abstract class that contains various methods for clients to notify about changes. ...
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
FlagsOp(unsigned F)
unsigned getReg() const
MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ_ZERO_UNDEF Op0, Src0.
This is an important base class in LLVM.
Definition: Constant.h:41
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Class which stores all the state required in a MachineIRBuilder.
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:263
Helper class to build MachineInstr.
MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_FADD Op0, Op1.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:709
DebugLoc DL
Debug location to be set to any instruction we create.
MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOSI Src0.
MachineIRBuilder(MachineFunction &MF)
SrcOp(const MachineInstrBuilder &MIB)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_UITOFP Src0.
DstOp(const MachineOperand &Op)
unsigned createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
const MachineRegisterInfo * getMRI() const
MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTPOP Op0, Src0.
MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_MUL Op0, Op1.
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
const GISelCSEInfo * getCSEInfo() const
MachineOperand class - Representation of each machine instruction operand.
MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOUI Src0.
const TargetInstrInfo & getTII()
DebugLoc getDebugLoc()
Get the current instruction&#39;s debug location.
SrcOp(const MachineOperand &Op)
LLT getLLTTy(const MachineRegisterInfo &MRI) const
MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
This file describes high level types that are used by several passes or APIs involved in the GlobalIS...
Class for arbitrary precision integers.
Definition: APInt.h:69
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
LLT getLLTTy(const MachineRegisterInfo &MRI) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMAX Op0, Op1.
MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ Op0, Src0.
DstOp(const LLT &T)
Representation of each machine instruction.
Definition: MachineInstr.h:63
MachineIRBuilderState & getState()
Getter for the State.
SrcOp(unsigned R)
MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
const TargetRegisterClass * getRegClass() const
MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_ADD Op0, Op1.
MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FABS Op0.
MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0)
Build and insert a bitwise not, NegOne = G_CONSTANT -1 Res = G_OR Op0, NegOne.
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_PTRTOINT instruction.
MachineInstrBuilder buildFCopysign(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_FCOPYSIGN Op0, Op1.
MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMAX Op0, Op1.
const DataLayout & getDataLayout() const
MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITCAST Src.
MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMIN Op0, Op1.
CmpInst::Predicate getPredicate() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:72
static Value * buildGEP(IRBuilderTy &IRB, Value *BasePtr, SmallVectorImpl< Value *> &Indices, Twine NamePrefix)
Build a GEP out of a base pointer and indices.
Definition: SROA.cpp:1364
MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMIN Op0, Op1.
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
IRTranslator LLVM IR MI
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
MachineFunction * MF
MachineFunction under construction.
const DebugLoc & getDL()
Getter for DebugLoc.
MachineInstrBuilder SrcMIB
unsigned createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.