LLVM 17.0.0git
MachineIRBuilder.h
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1//===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the MachineIRBuilder class.
10/// This is a helper class to build MachineInstr.
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
14#define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
15
21#include "llvm/IR/DebugLoc.h"
22#include "llvm/IR/Module.h"
23
24namespace llvm {
25
26// Forward declarations.
27class APInt;
28class BlockAddress;
29class Constant;
30class ConstantFP;
31class ConstantInt;
32class DataLayout;
33class GISelCSEInfo;
34class GlobalValue;
35class TargetRegisterClass;
36class MachineFunction;
37class MachineInstr;
38class TargetInstrInfo;
39class GISelChangeObserver;
40
41/// Class which stores all the state required in a MachineIRBuilder.
42/// Since MachineIRBuilders will only store state in this object, it allows
43/// to transfer BuilderState between different kinds of MachineIRBuilders.
45 /// MachineFunction under construction.
46 MachineFunction *MF = nullptr;
47 /// Information used to access the description of the opcodes.
48 const TargetInstrInfo *TII = nullptr;
49 /// Information used to verify types are consistent and to create virtual registers.
51 /// Debug location to be set to any instruction we create.
53 /// PC sections metadata to be set to any instruction we create.
54 MDNode *PCSections = nullptr;
55
56 /// \name Fields describing the insertion point.
57 /// @{
60 /// @}
61
63
65};
66
67class DstOp {
68 union {
72 };
73
74public:
75 enum class DstType { Ty_LLT, Ty_Reg, Ty_RC };
76 DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {}
77 DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {}
78 DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {}
79 DstOp(const LLT T) : LLTTy(T), Ty(DstType::Ty_LLT) {}
80 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {}
81
83 switch (Ty) {
84 case DstType::Ty_Reg:
85 MIB.addDef(Reg);
86 break;
87 case DstType::Ty_LLT:
88 MIB.addDef(MRI.createGenericVirtualRegister(LLTTy));
89 break;
90 case DstType::Ty_RC:
91 MIB.addDef(MRI.createVirtualRegister(RC));
92 break;
93 }
94 }
95
97 switch (Ty) {
98 case DstType::Ty_RC:
99 return LLT{};
100 case DstType::Ty_LLT:
101 return LLTTy;
102 case DstType::Ty_Reg:
103 return MRI.getType(Reg);
104 }
105 llvm_unreachable("Unrecognised DstOp::DstType enum");
106 }
107
108 Register getReg() const {
109 assert(Ty == DstType::Ty_Reg && "Not a register");
110 return Reg;
111 }
112
114 switch (Ty) {
115 case DstType::Ty_RC:
116 return RC;
117 default:
118 llvm_unreachable("Not a RC Operand");
119 }
120 }
121
122 DstType getDstOpKind() const { return Ty; }
123
124private:
125 DstType Ty;
126};
127
128class SrcOp {
129 union {
133 int64_t Imm;
134 };
135
136public:
138 SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {}
139 SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {}
140 SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {}
142 /// Use of registers held in unsigned integer variables (or more rarely signed
143 /// integers) is no longer permitted to avoid ambiguity with upcoming support
144 /// for immediates.
145 SrcOp(unsigned) = delete;
146 SrcOp(int) = delete;
147 SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
148 SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
149
151 switch (Ty) {
153 MIB.addPredicate(Pred);
154 break;
155 case SrcType::Ty_Reg:
156 MIB.addUse(Reg);
157 break;
158 case SrcType::Ty_MIB:
159 MIB.addUse(SrcMIB->getOperand(0).getReg());
160 break;
161 case SrcType::Ty_Imm:
162 MIB.addImm(Imm);
163 break;
164 }
165 }
166
168 switch (Ty) {
170 case SrcType::Ty_Imm:
171 llvm_unreachable("Not a register operand");
172 case SrcType::Ty_Reg:
173 return MRI.getType(Reg);
174 case SrcType::Ty_MIB:
175 return MRI.getType(SrcMIB->getOperand(0).getReg());
176 }
177 llvm_unreachable("Unrecognised SrcOp::SrcType enum");
178 }
179
180 Register getReg() const {
181 switch (Ty) {
183 case SrcType::Ty_Imm:
184 llvm_unreachable("Not a register operand");
185 case SrcType::Ty_Reg:
186 return Reg;
187 case SrcType::Ty_MIB:
188 return SrcMIB->getOperand(0).getReg();
189 }
190 llvm_unreachable("Unrecognised SrcOp::SrcType enum");
191 }
192
194 switch (Ty) {
196 return Pred;
197 default:
198 llvm_unreachable("Not a register operand");
199 }
200 }
201
202 int64_t getImm() const {
203 switch (Ty) {
204 case SrcType::Ty_Imm:
205 return Imm;
206 default:
207 llvm_unreachable("Not an immediate");
208 }
209 }
210
211 SrcType getSrcOpKind() const { return Ty; }
212
213private:
214 SrcType Ty;
215};
216
217/// Helper class to build MachineInstr.
218/// It keeps internally the insertion point and debug location for all
219/// the new instructions we want to create.
220/// This information can be modified via the related setters.
222
224
225 unsigned getOpcodeForMerge(const DstOp &DstOp, ArrayRef<SrcOp> SrcOps) const;
226
227protected:
228 void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend);
229
230 void validateUnaryOp(const LLT Res, const LLT Op0);
231 void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1);
232 void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1);
233
234 void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty,
235 const LLT Op1Ty);
236
237 void recordInsertion(MachineInstr *InsertedInstr) const {
238 if (State.Observer)
239 State.Observer->createdInstr(*InsertedInstr);
240 }
241
242public:
243 /// Some constructors for easy use.
244 MachineIRBuilder() = default;
246
248 setMF(*MBB.getParent());
249 setInsertPt(MBB, InsPt);
250 }
251
253 MachineIRBuilder(*MI.getParent(), MI.getIterator()) {
254 setInstr(MI);
255 setDebugLoc(MI.getDebugLoc());
256 }
257
260 setChangeObserver(Observer);
261 }
262
263 virtual ~MachineIRBuilder() = default;
264
265 MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {}
266
268 assert(State.TII && "TargetInstrInfo is not set");
269 return *State.TII;
270 }
271
272 /// Getter for the function we currently build.
274 assert(State.MF && "MachineFunction is not set");
275 return *State.MF;
276 }
277
278 const MachineFunction &getMF() const {
279 assert(State.MF && "MachineFunction is not set");
280 return *State.MF;
281 }
282
283 const DataLayout &getDataLayout() const {
285 }
286
287 /// Getter for DebugLoc
288 const DebugLoc &getDL() { return State.DL; }
289
290 /// Getter for MRI
291 MachineRegisterInfo *getMRI() { return State.MRI; }
292 const MachineRegisterInfo *getMRI() const { return State.MRI; }
293
294 /// Getter for the State
295 MachineIRBuilderState &getState() { return State; }
296
297 /// Getter for the basic block we currently build.
298 const MachineBasicBlock &getMBB() const {
299 assert(State.MBB && "MachineBasicBlock is not set");
300 return *State.MBB;
301 }
302
304 return const_cast<MachineBasicBlock &>(
305 const_cast<const MachineIRBuilder *>(this)->getMBB());
306 }
307
308 GISelCSEInfo *getCSEInfo() { return State.CSEInfo; }
309 const GISelCSEInfo *getCSEInfo() const { return State.CSEInfo; }
310
311 /// Current insertion point for new instructions.
313
314 /// Set the insertion point before the specified position.
315 /// \pre MBB must be in getMF().
316 /// \pre II must be a valid iterator in MBB.
318 assert(MBB.getParent() == &getMF() &&
319 "Basic block is in a different function");
320 State.MBB = &MBB;
321 State.II = II;
322 }
323
324 /// @}
325
327
328 /// \name Setters for the insertion point.
329 /// @{
330 /// Set the MachineFunction where to build instructions.
331 void setMF(MachineFunction &MF);
332
333 /// Set the insertion point to the end of \p MBB.
334 /// \pre \p MBB must be contained by getMF().
336 State.MBB = &MBB;
337 State.II = MBB.end();
338 assert(&getMF() == MBB.getParent() &&
339 "Basic block is in a different function");
340 }
341
342 /// Set the insertion point to before MI.
343 /// \pre MI must be in getMF().
345 assert(MI.getParent() && "Instruction is not part of a basic block");
346 setMBB(*MI.getParent());
347 State.II = MI.getIterator();
348 setPCSections(MI.getPCSections());
349 }
350 /// @}
351
352 /// Set the insertion point to before MI, and set the debug loc to MI's loc.
353 /// \pre MI must be in getMF().
355 setInstr(MI);
356 setDebugLoc(MI.getDebugLoc());
357 }
358
360 State.Observer = &Observer;
361 }
362
363 void stopObservingChanges() { State.Observer = nullptr; }
364 /// @}
365
366 /// Set the debug location to \p DL for all the next build instructions.
367 void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; }
368
369 /// Get the current instruction's debug location.
370 const DebugLoc &getDebugLoc() { return State.DL; }
371
372 /// Set the PC sections metadata to \p MD for all the next build instructions.
373 void setPCSections(MDNode *MD) { State.PCSections = MD; }
374
375 /// Get the current instruction's PC sections metadata.
376 MDNode *getPCSections() { return State.PCSections; }
377
378 /// Build and insert <empty> = \p Opcode <empty>.
379 /// The insertion point is the one set by the last call of either
380 /// setBasicBlock or setMI.
381 ///
382 /// \pre setBasicBlock or setMI must have been called.
383 ///
384 /// \return a MachineInstrBuilder for the newly created instruction.
386 return insertInstr(buildInstrNoInsert(Opcode));
387 }
388
389 /// Build but don't insert <empty> = \p Opcode <empty>.
390 ///
391 /// \pre setMF, setBasicBlock or setMI must have been called.
392 ///
393 /// \return a MachineInstrBuilder for the newly created instruction.
395
396 /// Insert an existing instruction at the insertion point.
398
399 /// Build and insert a DBG_VALUE instruction expressing the fact that the
400 /// associated \p Variable lives in \p Reg (suitably modified by \p Expr).
402 const MDNode *Expr);
403
404 /// Build and insert a DBG_VALUE instruction expressing the fact that the
405 /// associated \p Variable lives in memory at \p Reg (suitably modified by \p
406 /// Expr).
408 const MDNode *Variable,
409 const MDNode *Expr);
410
411 /// Build and insert a DBG_VALUE instruction expressing the fact that the
412 /// associated \p Variable lives in the stack slot specified by \p FI
413 /// (suitably modified by \p Expr).
414 MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable,
415 const MDNode *Expr);
416
417 /// Build and insert a DBG_VALUE instructions specifying that \p Variable is
418 /// given by \p C (suitably modified by \p Expr).
420 const MDNode *Variable,
421 const MDNode *Expr);
422
423 /// Build and insert a DBG_LABEL instructions specifying that \p Label is
424 /// given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label".
426
427 /// Build and insert \p Res = G_DYN_STACKALLOC \p Size, \p Align
428 ///
429 /// G_DYN_STACKALLOC does a dynamic stack allocation and writes the address of
430 /// the allocated memory into \p Res.
431 /// \pre setBasicBlock or setMI must have been called.
432 /// \pre \p Res must be a generic virtual register with pointer type.
433 ///
434 /// \return a MachineInstrBuilder for the newly created instruction.
436 Align Alignment);
437
438 /// Build and insert \p Res = G_FRAME_INDEX \p Idx
439 ///
440 /// G_FRAME_INDEX materializes the address of an alloca value or other
441 /// stack-based object.
442 ///
443 /// \pre setBasicBlock or setMI must have been called.
444 /// \pre \p Res must be a generic virtual register with pointer type.
445 ///
446 /// \return a MachineInstrBuilder for the newly created instruction.
448
449 /// Build and insert \p Res = G_GLOBAL_VALUE \p GV
450 ///
451 /// G_GLOBAL_VALUE materializes the address of the specified global
452 /// into \p Res.
453 ///
454 /// \pre setBasicBlock or setMI must have been called.
455 /// \pre \p Res must be a generic virtual register with pointer type
456 /// in the same address space as \p GV.
457 ///
458 /// \return a MachineInstrBuilder for the newly created instruction.
460
461 /// Build and insert \p Res = G_CONSTANT_POOL \p Idx
462 ///
463 /// G_CONSTANT_POOL materializes the address of an object in the constant
464 /// pool.
465 ///
466 /// \pre setBasicBlock or setMI must have been called.
467 /// \pre \p Res must be a generic virtual register with pointer type.
468 ///
469 /// \return a MachineInstrBuilder for the newly created instruction.
470 MachineInstrBuilder buildConstantPool(const DstOp &Res, unsigned Idx);
471
472 /// Build and insert \p Res = G_PTR_ADD \p Op0, \p Op1
473 ///
474 /// G_PTR_ADD adds \p Op1 addressible units to the pointer specified by \p Op0,
475 /// storing the resulting pointer in \p Res. Addressible units are typically
476 /// bytes but this can vary between targets.
477 ///
478 /// \pre setBasicBlock or setMI must have been called.
479 /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
480 /// type.
481 /// \pre \p Op1 must be a generic virtual register with scalar type.
482 ///
483 /// \return a MachineInstrBuilder for the newly created instruction.
484 MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0,
485 const SrcOp &Op1);
486
487 /// Materialize and insert \p Res = G_PTR_ADD \p Op0, (G_CONSTANT \p Value)
488 ///
489 /// G_PTR_ADD adds \p Value bytes to the pointer specified by \p Op0,
490 /// storing the resulting pointer in \p Res. If \p Value is zero then no
491 /// G_PTR_ADD or G_CONSTANT will be created and \pre Op0 will be assigned to
492 /// \p Res.
493 ///
494 /// \pre setBasicBlock or setMI must have been called.
495 /// \pre \p Op0 must be a generic virtual register with pointer type.
496 /// \pre \p ValueTy must be a scalar type.
497 /// \pre \p Res must be 0. This is to detect confusion between
498 /// materializePtrAdd() and buildPtrAdd().
499 /// \post \p Res will either be a new generic virtual register of the same
500 /// type as \p Op0 or \p Op0 itself.
501 ///
502 /// \return a MachineInstrBuilder for the newly created instruction.
503 std::optional<MachineInstrBuilder> materializePtrAdd(Register &Res,
504 Register Op0,
505 const LLT ValueTy,
507
508 /// Build and insert \p Res = G_PTRMASK \p Op0, \p Op1
510 const SrcOp &Op1) {
511 return buildInstr(TargetOpcode::G_PTRMASK, {Res}, {Op0, Op1});
512 }
513
514 /// Build and insert \p Res = G_PTRMASK \p Op0, \p G_CONSTANT (1 << NumBits) - 1
515 ///
516 /// This clears the low bits of a pointer operand without destroying its
517 /// pointer properties. This has the effect of rounding the address *down* to
518 /// a specified alignment in bits.
519 ///
520 /// \pre setBasicBlock or setMI must have been called.
521 /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
522 /// type.
523 /// \pre \p NumBits must be an integer representing the number of low bits to
524 /// be cleared in \p Op0.
525 ///
526 /// \return a MachineInstrBuilder for the newly created instruction.
527 MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0,
528 uint32_t NumBits);
529
530 /// Build and insert
531 /// a, b, ..., x = G_UNMERGE_VALUES \p Op0
532 /// \p Res = G_BUILD_VECTOR a, b, ..., x, undef, ..., undef
533 ///
534 /// Pad \p Op0 with undef elements to match number of elements in \p Res.
535 ///
536 /// \pre setBasicBlock or setMI must have been called.
537 /// \pre \p Res and \p Op0 must be generic virtual registers with vector type,
538 /// same vector element type and Op0 must have fewer elements then Res.
539 ///
540 /// \return a MachineInstrBuilder for the newly created build vector instr.
542 const SrcOp &Op0);
543
544 /// Build and insert
545 /// a, b, ..., x, y, z = G_UNMERGE_VALUES \p Op0
546 /// \p Res = G_BUILD_VECTOR a, b, ..., x
547 ///
548 /// Delete trailing elements in \p Op0 to match number of elements in \p Res.
549 ///
550 /// \pre setBasicBlock or setMI must have been called.
551 /// \pre \p Res and \p Op0 must be generic virtual registers with vector type,
552 /// same vector element type and Op0 must have more elements then Res.
553 ///
554 /// \return a MachineInstrBuilder for the newly created build vector instr.
556 const SrcOp &Op0);
557
558 /// Build and insert \p Res, \p CarryOut = G_UADDO \p Op0, \p Op1
559 ///
560 /// G_UADDO sets \p Res to \p Op0 + \p Op1 (truncated to the bit width) and
561 /// sets \p CarryOut to 1 if the result overflowed in unsigned arithmetic.
562 ///
563 /// \pre setBasicBlock or setMI must have been called.
564 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers with the
565 /// same scalar type.
566 ////\pre \p CarryOut must be generic virtual register with scalar type
567 ///(typically s1)
568 ///
569 /// \return The newly created instruction.
570 MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut,
571 const SrcOp &Op0, const SrcOp &Op1) {
572 return buildInstr(TargetOpcode::G_UADDO, {Res, CarryOut}, {Op0, Op1});
573 }
574
575 /// Build and insert \p Res, \p CarryOut = G_USUBO \p Op0, \p Op1
576 MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut,
577 const SrcOp &Op0, const SrcOp &Op1) {
578 return buildInstr(TargetOpcode::G_USUBO, {Res, CarryOut}, {Op0, Op1});
579 }
580
581 /// Build and insert \p Res, \p CarryOut = G_SADDO \p Op0, \p Op1
582 MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut,
583 const SrcOp &Op0, const SrcOp &Op1) {
584 return buildInstr(TargetOpcode::G_SADDO, {Res, CarryOut}, {Op0, Op1});
585 }
586
587 /// Build and insert \p Res, \p CarryOut = G_SUBO \p Op0, \p Op1
588 MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut,
589 const SrcOp &Op0, const SrcOp &Op1) {
590 return buildInstr(TargetOpcode::G_SSUBO, {Res, CarryOut}, {Op0, Op1});
591 }
592
593 /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0,
594 /// \p Op1, \p CarryIn
595 ///
596 /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit
597 /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned
598 /// arithmetic.
599 ///
600 /// \pre setBasicBlock or setMI must have been called.
601 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
602 /// with the same scalar type.
603 /// \pre \p CarryOut and \p CarryIn must be generic virtual
604 /// registers with the same scalar type (typically s1)
605 ///
606 /// \return The newly created instruction.
607 MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut,
608 const SrcOp &Op0, const SrcOp &Op1,
609 const SrcOp &CarryIn) {
610 return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut},
611 {Op0, Op1, CarryIn});
612 }
613
614 /// Build and insert \p Res, \p CarryOut = G_USUBE \p Op0, \p Op1, \p CarryInp
615 MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut,
616 const SrcOp &Op0, const SrcOp &Op1,
617 const SrcOp &CarryIn) {
618 return buildInstr(TargetOpcode::G_USUBE, {Res, CarryOut},
619 {Op0, Op1, CarryIn});
620 }
621
622 /// Build and insert \p Res, \p CarryOut = G_SADDE \p Op0, \p Op1, \p CarryInp
623 MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut,
624 const SrcOp &Op0, const SrcOp &Op1,
625 const SrcOp &CarryIn) {
626 return buildInstr(TargetOpcode::G_SADDE, {Res, CarryOut},
627 {Op0, Op1, CarryIn});
628 }
629
630 /// Build and insert \p Res, \p CarryOut = G_SSUBE \p Op0, \p Op1, \p CarryInp
631 MachineInstrBuilder buildSSube(const DstOp &Res, const DstOp &CarryOut,
632 const SrcOp &Op0, const SrcOp &Op1,
633 const SrcOp &CarryIn) {
634 return buildInstr(TargetOpcode::G_SSUBE, {Res, CarryOut},
635 {Op0, Op1, CarryIn});
636 }
637
638 /// Build and insert \p Res = G_ANYEXT \p Op0
639 ///
640 /// G_ANYEXT produces a register of the specified width, with bits 0 to
641 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified
642 /// (i.e. this is neither zero nor sign-extension). For a vector register,
643 /// each element is extended individually.
644 ///
645 /// \pre setBasicBlock or setMI must have been called.
646 /// \pre \p Res must be a generic virtual register with scalar or vector type.
647 /// \pre \p Op must be a generic virtual register with scalar or vector type.
648 /// \pre \p Op must be smaller than \p Res
649 ///
650 /// \return The newly created instruction.
651
652 MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);
653
654 /// Build and insert \p Res = G_SEXT \p Op
655 ///
656 /// G_SEXT produces a register of the specified width, with bits 0 to
657 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the
658 /// high bit of \p Op (i.e. 2s-complement sign extended).
659 ///
660 /// \pre setBasicBlock or setMI must have been called.
661 /// \pre \p Res must be a generic virtual register with scalar or vector type.
662 /// \pre \p Op must be a generic virtual register with scalar or vector type.
663 /// \pre \p Op must be smaller than \p Res
664 ///
665 /// \return The newly created instruction.
666 MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op);
667
668 /// Build and insert \p Res = G_SEXT_INREG \p Op, ImmOp
669 MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp) {
670 return buildInstr(TargetOpcode::G_SEXT_INREG, {Res}, {Op, SrcOp(ImmOp)});
671 }
672
673 /// Build and insert \p Res = G_FPEXT \p Op
675 std::optional<unsigned> Flags = std::nullopt) {
676 return buildInstr(TargetOpcode::G_FPEXT, {Res}, {Op}, Flags);
677 }
678
679 /// Build and insert a G_PTRTOINT instruction.
681 return buildInstr(TargetOpcode::G_PTRTOINT, {Dst}, {Src});
682 }
683
684 /// Build and insert a G_INTTOPTR instruction.
686 return buildInstr(TargetOpcode::G_INTTOPTR, {Dst}, {Src});
687 }
688
689 /// Build and insert \p Dst = G_BITCAST \p Src
690 MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) {
691 return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src});
692 }
693
694 /// Build and insert \p Dst = G_ADDRSPACE_CAST \p Src
696 return buildInstr(TargetOpcode::G_ADDRSPACE_CAST, {Dst}, {Src});
697 }
698
699 /// \return The opcode of the extension the target wants to use for boolean
700 /// values.
701 unsigned getBoolExtOp(bool IsVec, bool IsFP) const;
702
703 // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_SEXT \p Op, or \p Res
704 // = G_ZEXT \p Op depending on how the target wants to extend boolean values.
705 MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op,
706 bool IsFP);
707
708 // Build and insert \p Res = G_SEXT_INREG \p Op, 1 or \p Res = G_AND \p Op, 1,
709 // or COPY depending on how the target wants to extend boolean values, using
710 // the original register size.
711 MachineInstrBuilder buildBoolExtInReg(const DstOp &Res, const SrcOp &Op,
712 bool IsVector,
713 bool IsFP);
714
715 /// Build and insert \p Res = G_ZEXT \p Op
716 ///
717 /// G_ZEXT produces a register of the specified width, with bits 0 to
718 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector
719 /// register, each element is extended individually.
720 ///
721 /// \pre setBasicBlock or setMI must have been called.
722 /// \pre \p Res must be a generic virtual register with scalar or vector type.
723 /// \pre \p Op must be a generic virtual register with scalar or vector type.
724 /// \pre \p Op must be smaller than \p Res
725 ///
726 /// \return The newly created instruction.
727 MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op);
728
729 /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or
730 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
731 /// ///
732 /// \pre setBasicBlock or setMI must have been called.
733 /// \pre \p Res must be a generic virtual register with scalar or vector type.
734 /// \pre \p Op must be a generic virtual register with scalar or vector type.
735 ///
736 /// \return The newly created instruction.
737 MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op);
738
739 /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or
740 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
741 /// ///
742 /// \pre setBasicBlock or setMI must have been called.
743 /// \pre \p Res must be a generic virtual register with scalar or vector type.
744 /// \pre \p Op must be a generic virtual register with scalar or vector type.
745 ///
746 /// \return The newly created instruction.
747 MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op);
748
749 // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or
750 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
751 /// ///
752 /// \pre setBasicBlock or setMI must have been called.
753 /// \pre \p Res must be a generic virtual register with scalar or vector type.
754 /// \pre \p Op must be a generic virtual register with scalar or vector type.
755 ///
756 /// \return The newly created instruction.
757 MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op);
758
759 /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p
760 /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and
761 /// \p Op.
762 /// ///
763 /// \pre setBasicBlock or setMI must have been called.
764 /// \pre \p Res must be a generic virtual register with scalar or vector type.
765 /// \pre \p Op must be a generic virtual register with scalar or vector type.
766 ///
767 /// \return The newly created instruction.
768 MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
769 const SrcOp &Op);
770
771 /// Build and inserts \p Res = \p G_AND \p Op, \p LowBitsSet(ImmOp)
772 /// Since there is no G_ZEXT_INREG like G_SEXT_INREG, the instruction is
773 /// emulated using G_AND.
774 MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op,
775 int64_t ImmOp);
776
777 /// Build and insert an appropriate cast between two registers of equal size.
778 MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src);
779
780 /// Build and insert G_BR \p Dest
781 ///
782 /// G_BR is an unconditional branch to \p Dest.
783 ///
784 /// \pre setBasicBlock or setMI must have been called.
785 ///
786 /// \return a MachineInstrBuilder for the newly created instruction.
788
789 /// Build and insert G_BRCOND \p Tst, \p Dest
790 ///
791 /// G_BRCOND is a conditional branch to \p Dest.
792 ///
793 /// \pre setBasicBlock or setMI must have been called.
794 /// \pre \p Tst must be a generic virtual register with scalar
795 /// type. At the beginning of legalization, this will be a single
796 /// bit (s1). Targets with interesting flags registers may change
797 /// this. For a wider type, whether the branch is taken must only
798 /// depend on bit 0 (for now).
799 ///
800 /// \return The newly created instruction.
802
803 /// Build and insert G_BRINDIRECT \p Tgt
804 ///
805 /// G_BRINDIRECT is an indirect branch to \p Tgt.
806 ///
807 /// \pre setBasicBlock or setMI must have been called.
808 /// \pre \p Tgt must be a generic virtual register with pointer type.
809 ///
810 /// \return a MachineInstrBuilder for the newly created instruction.
812
813 /// Build and insert G_BRJT \p TablePtr, \p JTI, \p IndexReg
814 ///
815 /// G_BRJT is a jump table branch using a table base pointer \p TablePtr,
816 /// jump table index \p JTI and index \p IndexReg
817 ///
818 /// \pre setBasicBlock or setMI must have been called.
819 /// \pre \p TablePtr must be a generic virtual register with pointer type.
820 /// \pre \p JTI must be be a jump table index.
821 /// \pre \p IndexReg must be a generic virtual register with pointer type.
822 ///
823 /// \return a MachineInstrBuilder for the newly created instruction.
824 MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI,
825 Register IndexReg);
826
827 /// Build and insert \p Res = G_CONSTANT \p Val
828 ///
829 /// G_CONSTANT is an integer constant with the specified size and value. \p
830 /// Val will be extended or truncated to the size of \p Reg.
831 ///
832 /// \pre setBasicBlock or setMI must have been called.
833 /// \pre \p Res must be a generic virtual register with scalar or pointer
834 /// type.
835 ///
836 /// \return The newly created instruction.
837 virtual MachineInstrBuilder buildConstant(const DstOp &Res,
838 const ConstantInt &Val);
839
840 /// Build and insert \p Res = G_CONSTANT \p Val
841 ///
842 /// G_CONSTANT is an integer constant with the specified size and value.
843 ///
844 /// \pre setBasicBlock or setMI must have been called.
845 /// \pre \p Res must be a generic virtual register with scalar type.
846 ///
847 /// \return The newly created instruction.
848 MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val);
849 MachineInstrBuilder buildConstant(const DstOp &Res, const APInt &Val);
850
851 /// Build and insert \p Res = G_FCONSTANT \p Val
852 ///
853 /// G_FCONSTANT is a floating-point constant with the specified size and
854 /// value.
855 ///
856 /// \pre setBasicBlock or setMI must have been called.
857 /// \pre \p Res must be a generic virtual register with scalar type.
858 ///
859 /// \return The newly created instruction.
860 virtual MachineInstrBuilder buildFConstant(const DstOp &Res,
861 const ConstantFP &Val);
862
863 MachineInstrBuilder buildFConstant(const DstOp &Res, double Val);
864 MachineInstrBuilder buildFConstant(const DstOp &Res, const APFloat &Val);
865
866 /// Build and insert \p Res = COPY Op
867 ///
868 /// Register-to-register COPY sets \p Res to \p Op.
869 ///
870 /// \pre setBasicBlock or setMI must have been called.
871 ///
872 /// \return a MachineInstrBuilder for the newly created instruction.
873 MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);
874
875
876 /// Build and insert G_ASSERT_SEXT, G_ASSERT_ZEXT, or G_ASSERT_ALIGN
877 ///
878 /// \return a MachineInstrBuilder for the newly created instruction.
880 const SrcOp &Op, unsigned Val) {
881 return buildInstr(Opc, Res, Op).addImm(Val);
882 }
883
884 /// Build and insert \p Res = G_ASSERT_ZEXT Op, Size
885 ///
886 /// \return a MachineInstrBuilder for the newly created instruction.
888 unsigned Size) {
889 return buildAssertInstr(TargetOpcode::G_ASSERT_ZEXT, Res, Op, Size);
890 }
891
892 /// Build and insert \p Res = G_ASSERT_SEXT Op, Size
893 ///
894 /// \return a MachineInstrBuilder for the newly created instruction.
896 unsigned Size) {
897 return buildAssertInstr(TargetOpcode::G_ASSERT_SEXT, Res, Op, Size);
898 }
899
900 /// Build and insert \p Res = G_ASSERT_ALIGN Op, AlignVal
901 ///
902 /// \return a MachineInstrBuilder for the newly created instruction.
904 Align AlignVal) {
905 return buildAssertInstr(TargetOpcode::G_ASSERT_ALIGN, Res, Op,
906 AlignVal.value());
907 }
908
909 /// Build and insert `Res = G_LOAD Addr, MMO`.
910 ///
911 /// Loads the value stored at \p Addr. Puts the result in \p Res.
912 ///
913 /// \pre setBasicBlock or setMI must have been called.
914 /// \pre \p Res must be a generic virtual register.
915 /// \pre \p Addr must be a generic virtual register with pointer type.
916 ///
917 /// \return a MachineInstrBuilder for the newly created instruction.
919 MachineMemOperand &MMO) {
920 return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO);
921 }
922
923 /// Build and insert a G_LOAD instruction, while constructing the
924 /// MachineMemOperand.
926 buildLoad(const DstOp &Res, const SrcOp &Addr, MachinePointerInfo PtrInfo,
927 Align Alignment,
929 const AAMDNodes &AAInfo = AAMDNodes());
930
931 /// Build and insert `Res = <opcode> Addr, MMO`.
932 ///
933 /// Loads the value stored at \p Addr. Puts the result in \p Res.
934 ///
935 /// \pre setBasicBlock or setMI must have been called.
936 /// \pre \p Res must be a generic virtual register.
937 /// \pre \p Addr must be a generic virtual register with pointer type.
938 ///
939 /// \return a MachineInstrBuilder for the newly created instruction.
940 MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res,
941 const SrcOp &Addr, MachineMemOperand &MMO);
942
943 /// Helper to create a load from a constant offset given a base address. Load
944 /// the type of \p Dst from \p Offset from the given base address and memory
945 /// operand.
947 const SrcOp &BasePtr,
948 MachineMemOperand &BaseMMO,
949 int64_t Offset);
950
951 /// Build and insert `G_STORE Val, Addr, MMO`.
952 ///
953 /// Stores the value \p Val to \p Addr.
954 ///
955 /// \pre setBasicBlock or setMI must have been called.
956 /// \pre \p Val must be a generic virtual register.
957 /// \pre \p Addr must be a generic virtual register with pointer type.
958 ///
959 /// \return a MachineInstrBuilder for the newly created instruction.
960 MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr,
961 MachineMemOperand &MMO);
962
963 /// Build and insert a G_STORE instruction, while constructing the
964 /// MachineMemOperand.
966 buildStore(const SrcOp &Val, const SrcOp &Addr, MachinePointerInfo PtrInfo,
967 Align Alignment,
969 const AAMDNodes &AAInfo = AAMDNodes());
970
971 /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.
972 ///
973 /// \pre setBasicBlock or setMI must have been called.
974 /// \pre \p Res and \p Src must be generic virtual registers.
975 ///
976 /// \return a MachineInstrBuilder for the newly created instruction.
977 MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index);
978
979 /// Build and insert \p Res = IMPLICIT_DEF.
981
982 /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
983 ///
984 /// G_MERGE_VALUES combines the input elements contiguously into a larger
985 /// register. It should only be used when the destination register is not a
986 /// vector.
987 ///
988 /// \pre setBasicBlock or setMI must have been called.
989 /// \pre The entire register \p Res (and no more) must be covered by the input
990 /// registers.
991 /// \pre The type of all \p Ops registers must be identical.
992 ///
993 /// \return a MachineInstrBuilder for the newly created instruction.
996
997 /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
998 /// or \p Res = G_BUILD_VECTOR \p Op0, ...
999 /// or \p Res = G_CONCAT_VECTORS \p Op0, ...
1000 ///
1001 /// G_MERGE_VALUES combines the input elements contiguously into a larger
1002 /// register. It is used when the destination register is not a vector.
1003 /// G_BUILD_VECTOR combines scalar inputs into a vector register.
1004 /// G_CONCAT_VECTORS combines vector inputs into a vector register.
1005 ///
1006 /// \pre setBasicBlock or setMI must have been called.
1007 /// \pre The entire register \p Res (and no more) must be covered by the input
1008 /// registers.
1009 /// \pre The type of all \p Ops registers must be identical.
1010 ///
1011 /// \return a MachineInstrBuilder for the newly created instruction. The
1012 /// opcode of the new instruction will depend on the types of both
1013 /// the destination and the sources.
1015 ArrayRef<Register> Ops);
1017 std::initializer_list<SrcOp> Ops);
1018
1019 /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op
1020 ///
1021 /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple
1022 ///
1023 /// \pre setBasicBlock or setMI must have been called.
1024 /// \pre The entire register \p Res (and no more) must be covered by the input
1025 /// registers.
1026 /// \pre The type of all \p Res registers must be identical.
1027 ///
1028 /// \return a MachineInstrBuilder for the newly created instruction.
1031
1032 /// Build and insert an unmerge of \p Res sized pieces to cover \p Op
1033 MachineInstrBuilder buildUnmerge(LLT Res, const SrcOp &Op);
1034
1035 /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ...
1036 ///
1037 /// G_BUILD_VECTOR creates a vector value from multiple scalar registers.
1038 /// \pre setBasicBlock or setMI must have been called.
1039 /// \pre The entire register \p Res (and no more) must be covered by the
1040 /// input scalar registers.
1041 /// \pre The type of all \p Ops registers must be identical.
1042 ///
1043 /// \return a MachineInstrBuilder for the newly created instruction.
1045 ArrayRef<Register> Ops);
1046
1047 /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ... where each OpN is
1048 /// built with G_CONSTANT.
1050 ArrayRef<APInt> Ops);
1051
1052 /// Build and insert \p Res = G_BUILD_VECTOR with \p Src replicated to fill
1053 /// the number of elements
1055 const SrcOp &Src);
1056
1057 /// Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ...
1058 ///
1059 /// G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers
1060 /// which have types larger than the destination vector element type, and
1061 /// truncates the values to fit.
1062 ///
1063 /// If the operands given are already the same size as the vector elt type,
1064 /// then this method will instead create a G_BUILD_VECTOR instruction.
1065 ///
1066 /// \pre setBasicBlock or setMI must have been called.
1067 /// \pre The type of all \p Ops registers must be identical.
1068 ///
1069 /// \return a MachineInstrBuilder for the newly created instruction.
1071 ArrayRef<Register> Ops);
1072
1073 /// Build and insert a vector splat of a scalar \p Src using a
1074 /// G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idiom.
1075 ///
1076 /// \pre setBasicBlock or setMI must have been called.
1077 /// \pre \p Src must have the same type as the element type of \p Dst
1078 ///
1079 /// \return a MachineInstrBuilder for the newly created instruction.
1080 MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src);
1081
1082 /// Build and insert \p Res = G_SHUFFLE_VECTOR \p Src1, \p Src2, \p Mask
1083 ///
1084 /// \pre setBasicBlock or setMI must have been called.
1085 ///
1086 /// \return a MachineInstrBuilder for the newly created instruction.
1087 MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1,
1088 const SrcOp &Src2, ArrayRef<int> Mask);
1089
1090 /// Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ...
1091 ///
1092 /// G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more
1093 /// vectors.
1094 ///
1095 /// \pre setBasicBlock or setMI must have been called.
1096 /// \pre The entire register \p Res (and no more) must be covered by the input
1097 /// registers.
1098 /// \pre The type of all source operands must be identical.
1099 ///
1100 /// \return a MachineInstrBuilder for the newly created instruction.
1102 ArrayRef<Register> Ops);
1103
1104 MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src,
1105 const SrcOp &Op, unsigned Index);
1106
1107 /// Build and insert either a G_INTRINSIC (if \p HasSideEffects is false) or
1108 /// G_INTRINSIC_W_SIDE_EFFECTS instruction. Its first operand will be the
1109 /// result register definition unless \p Reg is NoReg (== 0). The second
1110 /// operand will be the intrinsic's ID.
1111 ///
1112 /// Callers are expected to add the required definitions and uses afterwards.
1113 ///
1114 /// \pre setBasicBlock or setMI must have been called.
1115 ///
1116 /// \return a MachineInstrBuilder for the newly created instruction.
1118 bool HasSideEffects);
1120 bool HasSideEffects);
1121
1122 /// Build and insert \p Res = G_FPTRUNC \p Op
1123 ///
1124 /// G_FPTRUNC converts a floating-point value into one with a smaller type.
1125 ///
1126 /// \pre setBasicBlock or setMI must have been called.
1127 /// \pre \p Res must be a generic virtual register with scalar or vector type.
1128 /// \pre \p Op must be a generic virtual register with scalar or vector type.
1129 /// \pre \p Res must be smaller than \p Op
1130 ///
1131 /// \return The newly created instruction.
1133 buildFPTrunc(const DstOp &Res, const SrcOp &Op,
1134 std::optional<unsigned> Flags = std::nullopt);
1135
1136 /// Build and insert \p Res = G_TRUNC \p Op
1137 ///
1138 /// G_TRUNC extracts the low bits of a type. For a vector type each element is
1139 /// truncated independently before being packed into the destination.
1140 ///
1141 /// \pre setBasicBlock or setMI must have been called.
1142 /// \pre \p Res must be a generic virtual register with scalar or vector type.
1143 /// \pre \p Op must be a generic virtual register with scalar or vector type.
1144 /// \pre \p Res must be smaller than \p Op
1145 ///
1146 /// \return The newly created instruction.
1147 MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op);
1148
1149 /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1
1150 ///
1151 /// \pre setBasicBlock or setMI must have been called.
1152
1153 /// \pre \p Res must be a generic virtual register with scalar or
1154 /// vector type. Typically this starts as s1 or <N x s1>.
1155 /// \pre \p Op0 and Op1 must be generic virtual registers with the
1156 /// same number of elements as \p Res. If \p Res is a scalar,
1157 /// \p Op0 must be either a scalar or pointer.
1158 /// \pre \p Pred must be an integer predicate.
1159 ///
1160 /// \return a MachineInstrBuilder for the newly created instruction.
1162 const SrcOp &Op0, const SrcOp &Op1);
1163
1164 /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1
1165 ///
1166 /// \pre setBasicBlock or setMI must have been called.
1167
1168 /// \pre \p Res must be a generic virtual register with scalar or
1169 /// vector type. Typically this starts as s1 or <N x s1>.
1170 /// \pre \p Op0 and Op1 must be generic virtual registers with the
1171 /// same number of elements as \p Res (or scalar, if \p Res is
1172 /// scalar).
1173 /// \pre \p Pred must be a floating-point predicate.
1174 ///
1175 /// \return a MachineInstrBuilder for the newly created instruction.
1177 const SrcOp &Op0, const SrcOp &Op1,
1178 std::optional<unsigned> Flags = std::nullopt);
1179
1180 /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1
1181 ///
1182 /// \pre setBasicBlock or setMI must have been called.
1183 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1184 /// with the same type.
1185 /// \pre \p Tst must be a generic virtual register with scalar, pointer or
1186 /// vector type. If vector then it must have the same number of
1187 /// elements as the other parameters.
1188 ///
1189 /// \return a MachineInstrBuilder for the newly created instruction.
1190 MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,
1191 const SrcOp &Op0, const SrcOp &Op1,
1192 std::optional<unsigned> Flags = std::nullopt);
1193
1194 /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val,
1195 /// \p Elt, \p Idx
1196 ///
1197 /// \pre setBasicBlock or setMI must have been called.
1198 /// \pre \p Res and \p Val must be a generic virtual register
1199 // with the same vector type.
1200 /// \pre \p Elt and \p Idx must be a generic virtual register
1201 /// with scalar type.
1202 ///
1203 /// \return The newly created instruction.
1205 const SrcOp &Val,
1206 const SrcOp &Elt,
1207 const SrcOp &Idx);
1208
1209 /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
1210 ///
1211 /// \pre setBasicBlock or setMI must have been called.
1212 /// \pre \p Res must be a generic virtual register with scalar type.
1213 /// \pre \p Val must be a generic virtual register with vector type.
1214 ///
1215 /// \return The newly created instruction.
1217 const SrcOp &Val,
1218 const int Idx) {
1219 return buildExtractVectorElement(Res, Val,
1221 }
1222
1223 /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
1224 ///
1225 /// \pre setBasicBlock or setMI must have been called.
1226 /// \pre \p Res must be a generic virtual register with scalar type.
1227 /// \pre \p Val must be a generic virtual register with vector type.
1228 /// \pre \p Idx must be a generic virtual register with scalar type.
1229 ///
1230 /// \return The newly created instruction.
1232 const SrcOp &Val,
1233 const SrcOp &Idx);
1234
1235 /// Build and insert `OldValRes<def>, SuccessRes<def> =
1236 /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`.
1237 ///
1238 /// Atomically replace the value at \p Addr with \p NewVal if it is currently
1239 /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
1240 /// Addr in \p Res, along with an s1 indicating whether it was replaced.
1241 ///
1242 /// \pre setBasicBlock or setMI must have been called.
1243 /// \pre \p OldValRes must be a generic virtual register of scalar type.
1244 /// \pre \p SuccessRes must be a generic virtual register of scalar type. It
1245 /// will be assigned 0 on failure and 1 on success.
1246 /// \pre \p Addr must be a generic virtual register with pointer type.
1247 /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
1248 /// registers of the same type.
1249 ///
1250 /// \return a MachineInstrBuilder for the newly created instruction.
1252 buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes,
1253 Register Addr, Register CmpVal, Register NewVal,
1254 MachineMemOperand &MMO);
1255
1256 /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal,
1257 /// MMO`.
1258 ///
1259 /// Atomically replace the value at \p Addr with \p NewVal if it is currently
1260 /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
1261 /// Addr in \p Res.
1262 ///
1263 /// \pre setBasicBlock or setMI must have been called.
1264 /// \pre \p OldValRes must be a generic virtual register of scalar type.
1265 /// \pre \p Addr must be a generic virtual register with pointer type.
1266 /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
1267 /// registers of the same type.
1268 ///
1269 /// \return a MachineInstrBuilder for the newly created instruction.
1271 Register CmpVal, Register NewVal,
1272 MachineMemOperand &MMO);
1273
1274 /// Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`.
1275 ///
1276 /// Atomically read-modify-update the value at \p Addr with \p Val. Puts the
1277 /// original value from \p Addr in \p OldValRes. The modification is
1278 /// determined by the opcode.
1279 ///
1280 /// \pre setBasicBlock or setMI must have been called.
1281 /// \pre \p OldValRes must be a generic virtual register.
1282 /// \pre \p Addr must be a generic virtual register with pointer type.
1283 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1284 /// same type.
1285 ///
1286 /// \return a MachineInstrBuilder for the newly created instruction.
1287 MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes,
1288 const SrcOp &Addr, const SrcOp &Val,
1289 MachineMemOperand &MMO);
1290
1291 /// Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`.
1292 ///
1293 /// Atomically replace the value at \p Addr with \p Val. Puts the original
1294 /// value from \p Addr in \p OldValRes.
1295 ///
1296 /// \pre setBasicBlock or setMI must have been called.
1297 /// \pre \p OldValRes must be a generic virtual register.
1298 /// \pre \p Addr must be a generic virtual register with pointer type.
1299 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1300 /// same type.
1301 ///
1302 /// \return a MachineInstrBuilder for the newly created instruction.
1304 Register Val, MachineMemOperand &MMO);
1305
1306 /// Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`.
1307 ///
1308 /// Atomically replace the value at \p Addr with the addition of \p Val and
1309 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1310 ///
1311 /// \pre setBasicBlock or setMI must have been called.
1312 /// \pre \p OldValRes must be a generic virtual register.
1313 /// \pre \p Addr must be a generic virtual register with pointer type.
1314 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1315 /// same type.
1316 ///
1317 /// \return a MachineInstrBuilder for the newly created instruction.
1319 Register Val, MachineMemOperand &MMO);
1320
1321 /// Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`.
1322 ///
1323 /// Atomically replace the value at \p Addr with the subtraction of \p Val and
1324 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1325 ///
1326 /// \pre setBasicBlock or setMI must have been called.
1327 /// \pre \p OldValRes must be a generic virtual register.
1328 /// \pre \p Addr must be a generic virtual register with pointer type.
1329 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1330 /// same type.
1331 ///
1332 /// \return a MachineInstrBuilder for the newly created instruction.
1334 Register Val, MachineMemOperand &MMO);
1335
1336 /// Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`.
1337 ///
1338 /// Atomically replace the value at \p Addr with the bitwise and of \p Val and
1339 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1340 ///
1341 /// \pre setBasicBlock or setMI must have been called.
1342 /// \pre \p OldValRes must be a generic virtual register.
1343 /// \pre \p Addr must be a generic virtual register with pointer type.
1344 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1345 /// same type.
1346 ///
1347 /// \return a MachineInstrBuilder for the newly created instruction.
1349 Register Val, MachineMemOperand &MMO);
1350
1351 /// Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`.
1352 ///
1353 /// Atomically replace the value at \p Addr with the bitwise nand of \p Val
1354 /// and the original value. Puts the original value from \p Addr in \p
1355 /// OldValRes.
1356 ///
1357 /// \pre setBasicBlock or setMI must have been called.
1358 /// \pre \p OldValRes must be a generic virtual register.
1359 /// \pre \p Addr must be a generic virtual register with pointer type.
1360 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1361 /// same type.
1362 ///
1363 /// \return a MachineInstrBuilder for the newly created instruction.
1365 Register Val, MachineMemOperand &MMO);
1366
1367 /// Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`.
1368 ///
1369 /// Atomically replace the value at \p Addr with the bitwise or of \p Val and
1370 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1371 ///
1372 /// \pre setBasicBlock or setMI must have been called.
1373 /// \pre \p OldValRes must be a generic virtual register.
1374 /// \pre \p Addr must be a generic virtual register with pointer type.
1375 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1376 /// same type.
1377 ///
1378 /// \return a MachineInstrBuilder for the newly created instruction.
1380 Register Val, MachineMemOperand &MMO);
1381
1382 /// Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`.
1383 ///
1384 /// Atomically replace the value at \p Addr with the bitwise xor of \p Val and
1385 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1386 ///
1387 /// \pre setBasicBlock or setMI must have been called.
1388 /// \pre \p OldValRes must be a generic virtual register.
1389 /// \pre \p Addr must be a generic virtual register with pointer type.
1390 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1391 /// same type.
1392 ///
1393 /// \return a MachineInstrBuilder for the newly created instruction.
1395 Register Val, MachineMemOperand &MMO);
1396
1397 /// Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`.
1398 ///
1399 /// Atomically replace the value at \p Addr with the signed maximum of \p
1400 /// Val and the original value. Puts the original value from \p Addr in \p
1401 /// OldValRes.
1402 ///
1403 /// \pre setBasicBlock or setMI must have been called.
1404 /// \pre \p OldValRes must be a generic virtual register.
1405 /// \pre \p Addr must be a generic virtual register with pointer type.
1406 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1407 /// same type.
1408 ///
1409 /// \return a MachineInstrBuilder for the newly created instruction.
1411 Register Val, MachineMemOperand &MMO);
1412
1413 /// Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`.
1414 ///
1415 /// Atomically replace the value at \p Addr with the signed minimum of \p
1416 /// Val and the original value. Puts the original value from \p Addr in \p
1417 /// OldValRes.
1418 ///
1419 /// \pre setBasicBlock or setMI must have been called.
1420 /// \pre \p OldValRes must be a generic virtual register.
1421 /// \pre \p Addr must be a generic virtual register with pointer type.
1422 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1423 /// same type.
1424 ///
1425 /// \return a MachineInstrBuilder for the newly created instruction.
1427 Register Val, MachineMemOperand &MMO);
1428
1429 /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`.
1430 ///
1431 /// Atomically replace the value at \p Addr with the unsigned maximum of \p
1432 /// Val and the original value. Puts the original value from \p Addr in \p
1433 /// OldValRes.
1434 ///
1435 /// \pre setBasicBlock or setMI must have been called.
1436 /// \pre \p OldValRes must be a generic virtual register.
1437 /// \pre \p Addr must be a generic virtual register with pointer type.
1438 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1439 /// same type.
1440 ///
1441 /// \return a MachineInstrBuilder for the newly created instruction.
1443 Register Val, MachineMemOperand &MMO);
1444
1445 /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`.
1446 ///
1447 /// Atomically replace the value at \p Addr with the unsigned minimum of \p
1448 /// Val and the original value. Puts the original value from \p Addr in \p
1449 /// OldValRes.
1450 ///
1451 /// \pre setBasicBlock or setMI must have been called.
1452 /// \pre \p OldValRes must be a generic virtual register.
1453 /// \pre \p Addr must be a generic virtual register with pointer type.
1454 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1455 /// same type.
1456 ///
1457 /// \return a MachineInstrBuilder for the newly created instruction.
1459 Register Val, MachineMemOperand &MMO);
1460
1461 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO`.
1463 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1464 MachineMemOperand &MMO);
1465
1466 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO`.
1468 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1469 MachineMemOperand &MMO);
1470
1471 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FMAX Addr, Val, MMO`.
1472 ///
1473 /// Atomically replace the value at \p Addr with the floating point maximum of
1474 /// \p Val and the original value. Puts the original value from \p Addr in \p
1475 /// OldValRes.
1476 ///
1477 /// \pre setBasicBlock or setMI must have been called.
1478 /// \pre \p OldValRes must be a generic virtual register.
1479 /// \pre \p Addr must be a generic virtual register with pointer type.
1480 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1481 /// same type.
1482 ///
1483 /// \return a MachineInstrBuilder for the newly created instruction.
1485 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1486 MachineMemOperand &MMO);
1487
1488 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FMIN Addr, Val, MMO`.
1489 ///
1490 /// Atomically replace the value at \p Addr with the floating point minimum of
1491 /// \p Val and the original value. Puts the original value from \p Addr in \p
1492 /// OldValRes.
1493 ///
1494 /// \pre setBasicBlock or setMI must have been called.
1495 /// \pre \p OldValRes must be a generic virtual register.
1496 /// \pre \p Addr must be a generic virtual register with pointer type.
1497 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1498 /// same type.
1499 ///
1500 /// \return a MachineInstrBuilder for the newly created instruction.
1502 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1503 MachineMemOperand &MMO);
1504
1505 /// Build and insert `G_FENCE Ordering, Scope`.
1506 MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope);
1507
1508 /// Build and insert \p Dst = G_FREEZE \p Src
1509 MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src) {
1510 return buildInstr(TargetOpcode::G_FREEZE, {Dst}, {Src});
1511 }
1512
1513 /// Build and insert \p Res = G_BLOCK_ADDR \p BA
1514 ///
1515 /// G_BLOCK_ADDR computes the address of a basic block.
1516 ///
1517 /// \pre setBasicBlock or setMI must have been called.
1518 /// \pre \p Res must be a generic virtual register of a pointer type.
1519 ///
1520 /// \return The newly created instruction.
1522
1523 /// Build and insert \p Res = G_ADD \p Op0, \p Op1
1524 ///
1525 /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1526 /// truncated to their width.
1527 ///
1528 /// \pre setBasicBlock or setMI must have been called.
1529 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1530 /// with the same (scalar or vector) type).
1531 ///
1532 /// \return a MachineInstrBuilder for the newly created instruction.
1533
1534 MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,
1535 const SrcOp &Src1,
1536 std::optional<unsigned> Flags = std::nullopt) {
1537 return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1538 }
1539
1540 /// Build and insert \p Res = G_SUB \p Op0, \p Op1
1541 ///
1542 /// G_SUB sets \p Res to the difference of integer parameters \p Op0 and
1543 /// \p Op1, truncated to their width.
1544 ///
1545 /// \pre setBasicBlock or setMI must have been called.
1546 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1547 /// with the same (scalar or vector) type).
1548 ///
1549 /// \return a MachineInstrBuilder for the newly created instruction.
1550
1551 MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0,
1552 const SrcOp &Src1,
1553 std::optional<unsigned> Flags = std::nullopt) {
1554 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1555 }
1556
1557 /// Build and insert \p Res = G_MUL \p Op0, \p Op1
1558 ///
1559 /// G_MUL sets \p Res to the product of integer parameters \p Op0 and \p Op1,
1560 /// truncated to their width.
1561 ///
1562 /// \pre setBasicBlock or setMI must have been called.
1563 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1564 /// with the same (scalar or vector) type).
1565 ///
1566 /// \return a MachineInstrBuilder for the newly created instruction.
1567 MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
1568 const SrcOp &Src1,
1569 std::optional<unsigned> Flags = std::nullopt) {
1570 return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1571 }
1572
1574 const SrcOp &Src1,
1575 std::optional<unsigned> Flags = std::nullopt) {
1576 return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags);
1577 }
1578
1580 const SrcOp &Src1,
1581 std::optional<unsigned> Flags = std::nullopt) {
1582 return buildInstr(TargetOpcode::G_SMULH, {Dst}, {Src0, Src1}, Flags);
1583 }
1584
1585 /// Build and insert \p Res = G_UREM \p Op0, \p Op1
1586 MachineInstrBuilder buildURem(const DstOp &Dst, const SrcOp &Src0,
1587 const SrcOp &Src1,
1588 std::optional<unsigned> Flags = std::nullopt) {
1589 return buildInstr(TargetOpcode::G_UREM, {Dst}, {Src0, Src1}, Flags);
1590 }
1591
1592 MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0,
1593 const SrcOp &Src1,
1594 std::optional<unsigned> Flags = std::nullopt) {
1595 return buildInstr(TargetOpcode::G_FMUL, {Dst}, {Src0, Src1}, Flags);
1596 }
1597
1599 buildFMinNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1600 std::optional<unsigned> Flags = std::nullopt) {
1601 return buildInstr(TargetOpcode::G_FMINNUM, {Dst}, {Src0, Src1}, Flags);
1602 }
1603
1605 buildFMaxNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1606 std::optional<unsigned> Flags = std::nullopt) {
1607 return buildInstr(TargetOpcode::G_FMAXNUM, {Dst}, {Src0, Src1}, Flags);
1608 }
1609
1611 buildFMinNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1612 std::optional<unsigned> Flags = std::nullopt) {
1613 return buildInstr(TargetOpcode::G_FMINNUM_IEEE, {Dst}, {Src0, Src1}, Flags);
1614 }
1615
1617 buildFMaxNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1618 std::optional<unsigned> Flags = std::nullopt) {
1619 return buildInstr(TargetOpcode::G_FMAXNUM_IEEE, {Dst}, {Src0, Src1}, Flags);
1620 }
1621
1622 MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0,
1623 const SrcOp &Src1,
1624 std::optional<unsigned> Flags = std::nullopt) {
1625 return buildInstr(TargetOpcode::G_SHL, {Dst}, {Src0, Src1}, Flags);
1626 }
1627
1628 MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0,
1629 const SrcOp &Src1,
1630 std::optional<unsigned> Flags = std::nullopt) {
1631 return buildInstr(TargetOpcode::G_LSHR, {Dst}, {Src0, Src1}, Flags);
1632 }
1633
1634 MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0,
1635 const SrcOp &Src1,
1636 std::optional<unsigned> Flags = std::nullopt) {
1637 return buildInstr(TargetOpcode::G_ASHR, {Dst}, {Src0, Src1}, Flags);
1638 }
1639
1640 /// Build and insert \p Res = G_AND \p Op0, \p Op1
1641 ///
1642 /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p
1643 /// Op1.
1644 ///
1645 /// \pre setBasicBlock or setMI must have been called.
1646 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1647 /// with the same (scalar or vector) type).
1648 ///
1649 /// \return a MachineInstrBuilder for the newly created instruction.
1650
1651 MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0,
1652 const SrcOp &Src1) {
1653 return buildInstr(TargetOpcode::G_AND, {Dst}, {Src0, Src1});
1654 }
1655
1656 /// Build and insert \p Res = G_OR \p Op0, \p Op1
1657 ///
1658 /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
1659 /// Op1.
1660 ///
1661 /// \pre setBasicBlock or setMI must have been called.
1662 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1663 /// with the same (scalar or vector) type).
1664 ///
1665 /// \return a MachineInstrBuilder for the newly created instruction.
1666 MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0,
1667 const SrcOp &Src1,
1668 std::optional<unsigned> Flags = std::nullopt) {
1669 return buildInstr(TargetOpcode::G_OR, {Dst}, {Src0, Src1}, Flags);
1670 }
1671
1672 /// Build and insert \p Res = G_XOR \p Op0, \p Op1
1673 MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0,
1674 const SrcOp &Src1) {
1675 return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, Src1});
1676 }
1677
1678 /// Build and insert a bitwise not,
1679 /// \p NegOne = G_CONSTANT -1
1680 /// \p Res = G_OR \p Op0, NegOne
1681 MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) {
1682 auto NegOne = buildConstant(Dst.getLLTTy(*getMRI()), -1);
1683 return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, NegOne});
1684 }
1685
1686 /// Build and insert integer negation
1687 /// \p Zero = G_CONSTANT 0
1688 /// \p Res = G_SUB Zero, \p Op0
1689 MachineInstrBuilder buildNeg(const DstOp &Dst, const SrcOp &Src0) {
1690 auto Zero = buildConstant(Dst.getLLTTy(*getMRI()), 0);
1691 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Zero, Src0});
1692 }
1693
1694 /// Build and insert \p Res = G_CTPOP \p Op0, \p Src0
1695 MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0) {
1696 return buildInstr(TargetOpcode::G_CTPOP, {Dst}, {Src0});
1697 }
1698
1699 /// Build and insert \p Res = G_CTLZ \p Op0, \p Src0
1700 MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0) {
1701 return buildInstr(TargetOpcode::G_CTLZ, {Dst}, {Src0});
1702 }
1703
1704 /// Build and insert \p Res = G_CTLZ_ZERO_UNDEF \p Op0, \p Src0
1706 return buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {Dst}, {Src0});
1707 }
1708
1709 /// Build and insert \p Res = G_CTTZ \p Op0, \p Src0
1710 MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0) {
1711 return buildInstr(TargetOpcode::G_CTTZ, {Dst}, {Src0});
1712 }
1713
1714 /// Build and insert \p Res = G_CTTZ_ZERO_UNDEF \p Op0, \p Src0
1716 return buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, {Dst}, {Src0});
1717 }
1718
1719 /// Build and insert \p Dst = G_BSWAP \p Src0
1720 MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0) {
1721 return buildInstr(TargetOpcode::G_BSWAP, {Dst}, {Src0});
1722 }
1723
1724 /// Build and insert \p Res = G_FADD \p Op0, \p Op1
1725 MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0,
1726 const SrcOp &Src1,
1727 std::optional<unsigned> Flags = std::nullopt) {
1728 return buildInstr(TargetOpcode::G_FADD, {Dst}, {Src0, Src1}, Flags);
1729 }
1730
1731 /// Build and insert \p Res = G_STRICT_FADD \p Op0, \p Op1
1733 buildStrictFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1734 std::optional<unsigned> Flags = std::nullopt) {
1735 return buildInstr(TargetOpcode::G_STRICT_FADD, {Dst}, {Src0, Src1}, Flags);
1736 }
1737
1738 /// Build and insert \p Res = G_FSUB \p Op0, \p Op1
1739 MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0,
1740 const SrcOp &Src1,
1741 std::optional<unsigned> Flags = std::nullopt) {
1742 return buildInstr(TargetOpcode::G_FSUB, {Dst}, {Src0, Src1}, Flags);
1743 }
1744
1745 /// Build and insert \p Res = G_FDIV \p Op0, \p Op1
1746 MachineInstrBuilder buildFDiv(const DstOp &Dst, const SrcOp &Src0,
1747 const SrcOp &Src1,
1748 std::optional<unsigned> Flags = std::nullopt) {
1749 return buildInstr(TargetOpcode::G_FDIV, {Dst}, {Src0, Src1}, Flags);
1750 }
1751
1752 /// Build and insert \p Res = G_FMA \p Op0, \p Op1, \p Op2
1753 MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0,
1754 const SrcOp &Src1, const SrcOp &Src2,
1755 std::optional<unsigned> Flags = std::nullopt) {
1756 return buildInstr(TargetOpcode::G_FMA, {Dst}, {Src0, Src1, Src2}, Flags);
1757 }
1758
1759 /// Build and insert \p Res = G_FMAD \p Op0, \p Op1, \p Op2
1760 MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0,
1761 const SrcOp &Src1, const SrcOp &Src2,
1762 std::optional<unsigned> Flags = std::nullopt) {
1763 return buildInstr(TargetOpcode::G_FMAD, {Dst}, {Src0, Src1, Src2}, Flags);
1764 }
1765
1766 /// Build and insert \p Res = G_FNEG \p Op0
1767 MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0,
1768 std::optional<unsigned> Flags = std::nullopt) {
1769 return buildInstr(TargetOpcode::G_FNEG, {Dst}, {Src0}, Flags);
1770 }
1771
1772 /// Build and insert \p Res = G_FABS \p Op0
1773 MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0,
1774 std::optional<unsigned> Flags = std::nullopt) {
1775 return buildInstr(TargetOpcode::G_FABS, {Dst}, {Src0}, Flags);
1776 }
1777
1778 /// Build and insert \p Dst = G_FCANONICALIZE \p Src0
1780 buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0,
1781 std::optional<unsigned> Flags = std::nullopt) {
1782 return buildInstr(TargetOpcode::G_FCANONICALIZE, {Dst}, {Src0}, Flags);
1783 }
1784
1785 /// Build and insert \p Dst = G_INTRINSIC_TRUNC \p Src0
1787 buildIntrinsicTrunc(const DstOp &Dst, const SrcOp &Src0,
1788 std::optional<unsigned> Flags = std::nullopt) {
1789 return buildInstr(TargetOpcode::G_INTRINSIC_TRUNC, {Dst}, {Src0}, Flags);
1790 }
1791
1792 /// Build and insert \p Res = GFFLOOR \p Op0, \p Op1
1794 buildFFloor(const DstOp &Dst, const SrcOp &Src0,
1795 std::optional<unsigned> Flags = std::nullopt) {
1796 return buildInstr(TargetOpcode::G_FFLOOR, {Dst}, {Src0}, Flags);
1797 }
1798
1799 /// Build and insert \p Dst = G_FLOG \p Src
1801 std::optional<unsigned> Flags = std::nullopt) {
1802 return buildInstr(TargetOpcode::G_FLOG, {Dst}, {Src}, Flags);
1803 }
1804
1805 /// Build and insert \p Dst = G_FLOG2 \p Src
1807 std::optional<unsigned> Flags = std::nullopt) {
1808 return buildInstr(TargetOpcode::G_FLOG2, {Dst}, {Src}, Flags);
1809 }
1810
1811 /// Build and insert \p Dst = G_FEXP2 \p Src
1813 std::optional<unsigned> Flags = std::nullopt) {
1814 return buildInstr(TargetOpcode::G_FEXP2, {Dst}, {Src}, Flags);
1815 }
1816
1817 /// Build and insert \p Dst = G_FPOW \p Src0, \p Src1
1818 MachineInstrBuilder buildFPow(const DstOp &Dst, const SrcOp &Src0,
1819 const SrcOp &Src1,
1820 std::optional<unsigned> Flags = std::nullopt) {
1821 return buildInstr(TargetOpcode::G_FPOW, {Dst}, {Src0, Src1}, Flags);
1822 }
1823
1824 /// Build and insert \p Res = G_FCOPYSIGN \p Op0, \p Op1
1826 const SrcOp &Src1) {
1827 return buildInstr(TargetOpcode::G_FCOPYSIGN, {Dst}, {Src0, Src1});
1828 }
1829
1830 /// Build and insert \p Res = G_UITOFP \p Src0
1831 MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0) {
1832 return buildInstr(TargetOpcode::G_UITOFP, {Dst}, {Src0});
1833 }
1834
1835 /// Build and insert \p Res = G_SITOFP \p Src0
1836 MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0) {
1837 return buildInstr(TargetOpcode::G_SITOFP, {Dst}, {Src0});
1838 }
1839
1840 /// Build and insert \p Res = G_FPTOUI \p Src0
1841 MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0) {
1842 return buildInstr(TargetOpcode::G_FPTOUI, {Dst}, {Src0});
1843 }
1844
1845 /// Build and insert \p Res = G_FPTOSI \p Src0
1846 MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0) {
1847 return buildInstr(TargetOpcode::G_FPTOSI, {Dst}, {Src0});
1848 }
1849
1850 /// Build and insert \p Res = G_SMIN \p Op0, \p Op1
1851 MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0,
1852 const SrcOp &Src1) {
1853 return buildInstr(TargetOpcode::G_SMIN, {Dst}, {Src0, Src1});
1854 }
1855
1856 /// Build and insert \p Res = G_SMAX \p Op0, \p Op1
1857 MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0,
1858 const SrcOp &Src1) {
1859 return buildInstr(TargetOpcode::G_SMAX, {Dst}, {Src0, Src1});
1860 }
1861
1862 /// Build and insert \p Res = G_UMIN \p Op0, \p Op1
1863 MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0,
1864 const SrcOp &Src1) {
1865 return buildInstr(TargetOpcode::G_UMIN, {Dst}, {Src0, Src1});
1866 }
1867
1868 /// Build and insert \p Res = G_UMAX \p Op0, \p Op1
1869 MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0,
1870 const SrcOp &Src1) {
1871 return buildInstr(TargetOpcode::G_UMAX, {Dst}, {Src0, Src1});
1872 }
1873
1874 /// Build and insert \p Dst = G_ABS \p Src
1875 MachineInstrBuilder buildAbs(const DstOp &Dst, const SrcOp &Src) {
1876 return buildInstr(TargetOpcode::G_ABS, {Dst}, {Src});
1877 }
1878
1879 /// Build and insert \p Res = G_JUMP_TABLE \p JTI
1880 ///
1881 /// G_JUMP_TABLE sets \p Res to the address of the jump table specified by
1882 /// the jump table index \p JTI.
1883 ///
1884 /// \return a MachineInstrBuilder for the newly created instruction.
1885 MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI);
1886
1887 /// Build and insert \p Res = G_VECREDUCE_SEQ_FADD \p ScalarIn, \p VecIn
1888 ///
1889 /// \p ScalarIn is the scalar accumulator input to start the sequential
1890 /// reduction operation of \p VecIn.
1892 const SrcOp &ScalarIn,
1893 const SrcOp &VecIn) {
1894 return buildInstr(TargetOpcode::G_VECREDUCE_SEQ_FADD, {Dst},
1895 {ScalarIn, {VecIn}});
1896 }
1897
1898 /// Build and insert \p Res = G_VECREDUCE_SEQ_FMUL \p ScalarIn, \p VecIn
1899 ///
1900 /// \p ScalarIn is the scalar accumulator input to start the sequential
1901 /// reduction operation of \p VecIn.
1903 const SrcOp &ScalarIn,
1904 const SrcOp &VecIn) {
1905 return buildInstr(TargetOpcode::G_VECREDUCE_SEQ_FMUL, {Dst},
1906 {ScalarIn, {VecIn}});
1907 }
1908
1909 /// Build and insert \p Res = G_VECREDUCE_FADD \p Src
1910 ///
1911 /// \p ScalarIn is the scalar accumulator input to the reduction operation of
1912 /// \p VecIn.
1914 const SrcOp &ScalarIn,
1915 const SrcOp &VecIn) {
1916 return buildInstr(TargetOpcode::G_VECREDUCE_FADD, {Dst}, {ScalarIn, VecIn});
1917 }
1918
1919 /// Build and insert \p Res = G_VECREDUCE_FMUL \p Src
1920 ///
1921 /// \p ScalarIn is the scalar accumulator input to the reduction operation of
1922 /// \p VecIn.
1924 const SrcOp &ScalarIn,
1925 const SrcOp &VecIn) {
1926 return buildInstr(TargetOpcode::G_VECREDUCE_FMUL, {Dst}, {ScalarIn, VecIn});
1927 }
1928
1929 /// Build and insert \p Res = G_VECREDUCE_FMAX \p Src
1931 return buildInstr(TargetOpcode::G_VECREDUCE_FMAX, {Dst}, {Src});
1932 }
1933
1934 /// Build and insert \p Res = G_VECREDUCE_FMIN \p Src
1936 return buildInstr(TargetOpcode::G_VECREDUCE_FMIN, {Dst}, {Src});
1937 }
1938 /// Build and insert \p Res = G_VECREDUCE_ADD \p Src
1940 return buildInstr(TargetOpcode::G_VECREDUCE_ADD, {Dst}, {Src});
1941 }
1942
1943 /// Build and insert \p Res = G_VECREDUCE_MUL \p Src
1945 return buildInstr(TargetOpcode::G_VECREDUCE_MUL, {Dst}, {Src});
1946 }
1947
1948 /// Build and insert \p Res = G_VECREDUCE_AND \p Src
1950 return buildInstr(TargetOpcode::G_VECREDUCE_AND, {Dst}, {Src});
1951 }
1952
1953 /// Build and insert \p Res = G_VECREDUCE_OR \p Src
1955 return buildInstr(TargetOpcode::G_VECREDUCE_OR, {Dst}, {Src});
1956 }
1957
1958 /// Build and insert \p Res = G_VECREDUCE_XOR \p Src
1960 return buildInstr(TargetOpcode::G_VECREDUCE_XOR, {Dst}, {Src});
1961 }
1962
1963 /// Build and insert \p Res = G_VECREDUCE_SMAX \p Src
1965 return buildInstr(TargetOpcode::G_VECREDUCE_SMAX, {Dst}, {Src});
1966 }
1967
1968 /// Build and insert \p Res = G_VECREDUCE_SMIN \p Src
1970 return buildInstr(TargetOpcode::G_VECREDUCE_SMIN, {Dst}, {Src});
1971 }
1972
1973 /// Build and insert \p Res = G_VECREDUCE_UMAX \p Src
1975 return buildInstr(TargetOpcode::G_VECREDUCE_UMAX, {Dst}, {Src});
1976 }
1977
1978 /// Build and insert \p Res = G_VECREDUCE_UMIN \p Src
1980 return buildInstr(TargetOpcode::G_VECREDUCE_UMIN, {Dst}, {Src});
1981 }
1982
1983 /// Build and insert G_MEMCPY or G_MEMMOVE
1984 MachineInstrBuilder buildMemTransferInst(unsigned Opcode, const SrcOp &DstPtr,
1985 const SrcOp &SrcPtr,
1986 const SrcOp &Size,
1987 MachineMemOperand &DstMMO,
1988 MachineMemOperand &SrcMMO) {
1989 auto MIB = buildInstr(
1990 Opcode, {}, {DstPtr, SrcPtr, Size, SrcOp(INT64_C(0) /*isTailCall*/)});
1991 MIB.addMemOperand(&DstMMO);
1992 MIB.addMemOperand(&SrcMMO);
1993 return MIB;
1994 }
1995
1996 MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr,
1997 const SrcOp &Size, MachineMemOperand &DstMMO,
1998 MachineMemOperand &SrcMMO) {
1999 return buildMemTransferInst(TargetOpcode::G_MEMCPY, DstPtr, SrcPtr, Size,
2000 DstMMO, SrcMMO);
2001 }
2002
2003 /// Build and insert \p Dst = G_SBFX \p Src, \p LSB, \p Width.
2005 const SrcOp &LSB, const SrcOp &Width) {
2006 return buildInstr(TargetOpcode::G_SBFX, {Dst}, {Src, LSB, Width});
2007 }
2008
2009 /// Build and insert \p Dst = G_UBFX \p Src, \p LSB, \p Width.
2011 const SrcOp &LSB, const SrcOp &Width) {
2012 return buildInstr(TargetOpcode::G_UBFX, {Dst}, {Src, LSB, Width});
2013 }
2014
2015 /// Build and insert \p Dst = G_ROTR \p Src, \p Amt
2017 const SrcOp &Amt) {
2018 return buildInstr(TargetOpcode::G_ROTR, {Dst}, {Src, Amt});
2019 }
2020
2021 /// Build and insert \p Dst = G_ROTL \p Src, \p Amt
2023 const SrcOp &Amt) {
2024 return buildInstr(TargetOpcode::G_ROTL, {Dst}, {Src, Amt});
2025 }
2026
2027 /// Build and insert \p Dst = G_BITREVERSE \p Src
2029 return buildInstr(TargetOpcode::G_BITREVERSE, {Dst}, {Src});
2030 }
2031
2032 virtual MachineInstrBuilder
2033 buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps, ArrayRef<SrcOp> SrcOps,
2034 std::optional<unsigned> Flags = std::nullopt);
2035};
2036
2037} // End namespace llvm.
2038#endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static const Function * getParent(const Value *V)
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
uint64_t Addr
uint64_t Size
This contains common code to allow clients to notify changes to machine instr.
IRTranslator LLVM IR MI
unsigned Reg
Module.h This file contains the declarations for the Module class.
#define P(N)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
@ Flags
Definition: TextStubV5.cpp:93
Class for arbitrary precision integers.
Definition: APInt.h:75
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
The address of a basic block.
Definition: Constants.h:879
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:718
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:260
This is the shared class of boolean and integer constants.
Definition: Constants.h:78
This is an important base class in LLVM.
Definition: Constant.h:41
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
A debug info location.
Definition: DebugLoc.h:33
DstOp(const LLT T)
DstOp(unsigned R)
DstOp(Register R)
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
LLT getLLTTy(const MachineRegisterInfo &MRI) const
DstOp(const MachineOperand &Op)
DstType getDstOpKind() const
const TargetRegisterClass * RC
const TargetRegisterClass * getRegClass() const
DstOp(const TargetRegisterClass *TRC)
Register getReg() const
The CSE Analysis object.
Definition: CSEInfo.h:69
Abstract class that contains various methods for clients to notify about changes.
virtual void createdInstr(MachineInstr &MI)=0
An instruction has been created and inserted into the function.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:652
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Metadata node.
Definition: Metadata.h:943
Function & getFunction()
Return the LLVM function that this machine code represents.
Helper class to build MachineInstr.
MachineInstrBuilder buildLoadFromOffset(const DstOp &Dst, const SrcOp &BasePtr, MachineMemOperand &BaseMMO, int64_t Offset)
Helper to create a load from a constant offset given a base address.
MachineInstrBuilder buildAtomicRMWFMin(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FMIN Addr, Val, MMO.
MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FSUB Op0, Op1.
MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOSI Src0.
MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildBoolExtInReg(const DstOp &Res, const SrcOp &Op, bool IsVector, bool IsFP)
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_FREEZE Src.
MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO.
MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
MachineInstrBuilder buildBr(MachineBasicBlock &Dest)
Build and insert G_BR Dest.
void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II)
Set the insertion point before the specified position.
const MachineFunction & getMF() const
std::optional< MachineInstrBuilder > materializePtrAdd(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value)
Materialize and insert Res = G_PTR_ADD Op0, (G_CONSTANT Value)
MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_ADD Op0, Op1.
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
MachineInstrBuilder buildFPExt(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FPEXT Op.
MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0)
Build and insert a bitwise not, NegOne = G_CONSTANT -1 Res = G_OR Op0, NegOne.
MachineInstrBuilder buildVecReduceSeqFAdd(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_SEQ_FADD ScalarIn, VecIn.
MachineInstrBuilder buildRotateRight(const DstOp &Dst, const SrcOp &Src, const SrcOp &Amt)
Build and insert Dst = G_ROTR Src, Amt.
MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ Op0, Src0.
virtual ~MachineIRBuilder()=default
MachineInstrBuilder buildVecReduceOr(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_OR Src.
MachineInstrBuilder buildFLog2(const DstOp &Dst, const SrcOp &Src, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FLOG2 Src.
MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildConstantPool(const DstOp &Res, unsigned Idx)
Build and insert Res = G_CONSTANT_POOL Idx.
MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI)
Build and insert Res = G_JUMP_TABLE JTI.
MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op, bool IsFP)
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ... = G_UNMERGE_VALUES Op.
MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FABS Op0.
MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope)
Build and insert G_FENCE Ordering, Scope.
MachineInstrBuilder buildFMinNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FMA Op0, Op1, Op2.
MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO.
MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and inserts Res = G_AND Op, LowBitsSet(ImmOp) Since there is no G_ZEXT_INREG like G_SEXT_INREG,...
MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
GISelCSEInfo * getCSEInfo()
MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO.
MachineInstrBuilder buildVecReduceFMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_FMAX Src.
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert Res0, ... = G_EXTRACT Src, Idx0.
MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_MUL Op0, Op1.
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src)
Build and insert an appropriate cast between two registers of equal size.
const TargetInstrInfo & getTII()
MachineInstrBuilder buildAtomicRMWFAdd(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO.
MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_SADDE Op0, Op1, CarryInp.
MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO.
MachineInstrBuilder buildURem(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_UREM Op0, Op1.
MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_SADDO Op0, Op1.
MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOUI Src0.
MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildFPow(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FPOW Src0, Src1.
MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Res = COPY Op depending on the differing sizes of Res and Op.
MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op.
MachineInstrBuilder buildIntrinsicTrunc(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_INTRINSIC_TRUNC Src0.
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src)
Build and insert a vector splat of a scalar Src using a G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idio...
MachineInstrBuilder buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr,...
MachineInstrBuilder buildConcatVectors(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_CONCAT_VECTORS Op0, ...
MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.
MachineInstrBuilder buildVecReduceSeqFMul(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_SEQ_FMUL ScalarIn, VecIn.
MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_SUB Op0, Op1.
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
MDNode * getPCSections()
Get the current instruction's PC sections metadata.
MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0)
Build and insert Dst = G_BSWAP Src0.
MachineInstrBuilder buildVecReduceFMul(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_FMUL Src.
MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ_ZERO_UNDEF Op0, Src0.
MachineInstrBuilder buildAddrSpaceCast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_ADDRSPACE_CAST Src.
MachineInstrBuilder buildFExp2(const DstOp &Dst, const SrcOp &Src, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FEXP2 Src.
MachineInstrBuilder buildIntToPtr(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_INTTOPTR instruction.
MachineInstrBuilder buildIndirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...
unsigned getBoolExtOp(bool IsVec, bool IsFP) const
MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_USUBO Op0, Op1.
MachineInstrBuilder buildVecReduceFAdd(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_FADD Src.
MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO.
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
MachineIRBuilder(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt)
MachineInstrBuilder buildNeg(const DstOp &Dst, const SrcOp &Src0)
Build and insert integer negation Zero = G_CONSTANT 0 Res = G_SUB Zero, Op0.
MachineInstrBuilder buildVecReduceSMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_SMIN Src.
MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ Op0, Src0.
MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMAX Op0, Op1.
MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...
MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_ZEXT Op, Size.
void recordInsertion(MachineInstr *InsertedInstr) const
MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildStrictFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_STRICT_FADD Op0, Op1.
MachineInstrBuilder buildBrCond(const SrcOp &Tst, MachineBasicBlock &Dest)
Build and insert G_BRCOND Tst, Dest.
MachineInstrBuilder buildVecReduceXor(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_XOR Src.
MachineInstrBuilder buildVecReduceFMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_FMIN Src.
MachineInstrBuilder buildFDiv(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FDIV Op0, Op1.
MachineInstrBuilder buildMergeLikeInstr(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ... or Res = G_BUILD_VECTOR Op0, ... or Res = G_CONCAT_VEC...
const GISelCSEInfo * getCSEInfo() const
MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR_TRUNC Op0, ...
MachineBasicBlock & getMBB()
MachineIRBuilder(MachineInstr &MI)
MachineInstrBuilder buildExtractVectorElementConstant(const DstOp &Res, const SrcOp &Val, const int Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ_ZERO_UNDEF Op0, Src0.
virtual MachineInstrBuilder buildFConstant(const DstOp &Res, const ConstantFP &Val)
Build and insert Res = G_FCONSTANT Val.
MachineInstrBuilder buildBitReverse(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITREVERSE Src.
MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTR_ADD Op0, Op1.
MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_UITOFP Src0.
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
MachineInstrBuilder buildAtomicCmpXchg(Register OldValRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_SITOFP Src0.
MachineIRBuilder(MachineInstr &MI, GISelChangeObserver &Observer)
MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FMAD Op0, Op1, Op2.
MachineInstrBuilder buildPadVectorWithUndefElements(const DstOp &Res, const SrcOp &Op0)
Build and insert a, b, ..., x = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a, b, .....
MachineInstrBuilder buildFLog(const DstOp &Dst, const SrcOp &Src, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FLOG Src.
void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty, const LLT Op1Ty)
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
MachineInstrBuilder buildVecReduceUMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_UMAX Src.
MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...
const DebugLoc & getDL()
Getter for DebugLoc.
MachineInstrBuilder buildUbfx(const DstOp &Dst, const SrcOp &Src, const SrcOp &LSB, const SrcOp &Width)
Build and insert Dst = G_UBFX Src, LSB, Width.
const MachineRegisterInfo * getMRI() const
MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTPOP Op0, Src0.
MachineInstrBuilder buildAbs(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_ABS Src.
MachineInstrBuilder buildBuildVectorConstant(const DstOp &Res, ArrayRef< APInt > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ... where each OpN is built with G_CONSTANT.
MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO.
void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1)
MachineInstrBuilder buildVecReduceAnd(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_AND Src.
void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1)
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
MachineFunction & getMF()
Getter for the function we currently build.
MachineIRBuilder(MachineFunction &MF)
MachineIRBuilder(const MachineIRBuilderState &BState)
MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr, const SrcOp &Size, MachineMemOperand &DstMMO, MachineMemOperand &SrcMMO)
MachineInstrBuilder buildAssertAlign(const DstOp &Res, const SrcOp &Op, Align AlignVal)
Build and insert Res = G_ASSERT_ALIGN Op, AlignVal.
MachineInstrBuilder buildSbfx(const DstOp &Dst, const SrcOp &Src, const SrcOp &LSB, const SrcOp &Width)
Build and insert Dst = G_SBFX Src, LSB, Width.
MachineInstrBuilder buildFMaxNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMIN Op0, Op1.
MachineInstrBuilder buildFMinNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildDbgLabel(const MDNode *Label)
Build and insert a DBG_LABEL instructions specifying that Label is given.
MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI, Register IndexReg)
Build and insert G_BRJT TablePtr, JTI, IndexReg.
MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src, const SrcOp &Op, unsigned Index)
MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size, Align Alignment)
Build and insert Res = G_DYN_STACKALLOC Size, Align.
MachineInstrBuilder buildVecReduceUMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_UMIN Src.
MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in th...
void setInstrAndDebugLoc(MachineInstr &MI)
Set the insertion point to before MI, and set the debug loc to MI's loc.
MachineInstrBuilder buildSSube(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_SSUBE Op0, Op1, CarryInp.
void setPCSections(MDNode *MD)
Set the PC sections metadata to MD for all the next build instructions.
MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, const SrcOp &Op)
Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of...
MachineInstrBuilder buildVecReduceAdd(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_ADD Src.
MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO.
MachineInstrBuilder buildMergeValues(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_UADDE Op0, Op1, CarryIn.
MachineInstrBuilder buildAtomicRMWFMax(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FMAX Addr, Val, MMO.
void setDebugLoc(const DebugLoc &DL)
Set the debug location to DL for all the next build instructions.
MachineInstrBuilder buildFCopysign(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_FCOPYSIGN Op0, Op1.
MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Src)
Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.
MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_SUBO Op0, Op1.
MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO.
MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_USUBE Op0, Op1, CarryInp.
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FNEG Op0.
MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects)
Build and insert either a G_INTRINSIC (if HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS inst...
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITCAST Src.
const DebugLoc & getDebugLoc()
Get the current instruction's debug location.
MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_UADDO Op0, Op1.
void setCSEInfo(GISelCSEInfo *Info)
MachineInstrBuilder buildFMaxNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
MachineInstrBuilder buildFFloor(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = GFFLOOR Op0, Op1.
MachineIRBuilder()=default
Some constructors for easy use.
MachineInstrBuilder buildDeleteTrailingVectorElements(const DstOp &Res, const SrcOp &Op0)
Build and insert a, b, ..., x, y, z = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a,...
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO.
MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FPTRUNC Op.
MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_OR Op0, Op1.
MachineIRBuilderState & getState()
Getter for the State.
MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1, const SrcOp &Src2, ArrayRef< int > Mask)
Build and insert Res = G_SHUFFLE_VECTOR Src1, Src2, Mask.
MachineInstrBuilder buildAssertInstr(unsigned Opc, const DstOp &Res, const SrcOp &Op, unsigned Val)
Build and insert G_ASSERT_SEXT, G_ASSERT_ZEXT, or G_ASSERT_ALIGN.
void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend)
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTRMASK Op0, Op1.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
MachineInstrBuilder buildVecReduceSMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_SMAX Src.
MachineInstrBuilder buildMemTransferInst(unsigned Opcode, const SrcOp &DstPtr, const SrcOp &SrcPtr, const SrcOp &Size, MachineMemOperand &DstMMO, MachineMemOperand &SrcMMO)
Build and insert G_MEMCPY or G_MEMMOVE.
void validateUnaryOp(const LLT Res, const LLT Op0)
MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA)
Build and insert Res = G_BLOCK_ADDR BA.
MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO.
const DataLayout & getDataLayout() const
MachineInstrBuilder buildBrIndirect(Register Tgt)
Build and insert G_BRINDIRECT Tgt.
MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = <opcode> Addr, MMO.
void setMF(MachineFunction &MF)
MachineInstrBuilder buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO.
MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_SEXT Op, Size.
MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_XOR Op0, Op1.
MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO.
void setChangeObserver(GISelChangeObserver &Observer)
MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0, uint32_t NumBits)
Build and insert Res = G_PTRMASK Op0, G_CONSTANT (1 << NumBits) - 1.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
MachineInstrBuilder buildVecReduceMul(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_MUL Src.
MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMIN Op0, Op1.
MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMAX Op0, Op1.
MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert a Res = G_FCMP PredOp0, Op1.
MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FADD Op0, Op1.
MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_PTRTOINT instruction.
MachineInstrBuilder buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FCANONICALIZE Src0.
MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and insert Res = G_SEXT_INREG Op, ImmOp.
MachineInstrBuilder buildRotateLeft(const DstOp &Dst, const SrcOp &Src, const SrcOp &Amt)
Build and insert Dst = G_ROTL Src, Amt.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addPredicate(CmpInst::Predicate Pred) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
Definition: MachineInstr.h:68
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
A description of a memory reference used in the backend.
Flags
Flags values. These may be or'd together.
MachineOperand class - Representation of each machine instruction operand.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const DataLayout & getDataLayout() const
Get the data layout for the module's target platform.
Definition: Module.cpp:398
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
SrcOp(const MachineInstrBuilder &MIB)
SrcOp(int64_t V)
SrcOp(const CmpInst::Predicate P)
SrcOp(uint64_t V)
SrcOp(int)=delete
MachineInstrBuilder SrcMIB
CmpInst::Predicate getPredicate() const
SrcType getSrcOpKind() const
CmpInst::Predicate Pred
int64_t getImm() const
LLT getLLTTy(const MachineRegisterInfo &MRI) const
SrcOp(const MachineOperand &Op)
void addSrcToMIB(MachineInstrBuilder &MIB) const
SrcOp(unsigned)=delete
Use of registers held in unsigned integer variables (or more rarely signed integers) is no longer per...
Register getReg() const
SrcOp(Register R)
TargetInstrInfo - Interface to description of machine instruction set.
LLVM Value Representation.
Definition: Value.h:74
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ ConstantFP
Definition: ISDOpcodes.h:77
@ BlockAddress
Definition: ISDOpcodes.h:84
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:651
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
Class which stores all the state required in a MachineIRBuilder.
MachineFunction * MF
MachineFunction under construction.
DebugLoc DL
Debug location to be set to any instruction we create.
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
MDNode * PCSections
PC sections metadata to be set to any instruction we create.
MachineBasicBlock::iterator II
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.
GISelChangeObserver * Observer
This class contains a discriminated union of information about pointers in memory operands,...