LLVM 18.0.0git
MachineIRBuilder.h
Go to the documentation of this file.
1//===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the MachineIRBuilder class.
10/// This is a helper class to build MachineInstr.
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
14#define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
15
21#include "llvm/IR/DebugLoc.h"
22#include "llvm/IR/Module.h"
23
24namespace llvm {
25
26// Forward declarations.
27class APInt;
28class BlockAddress;
29class Constant;
30class ConstantFP;
31class ConstantInt;
32class DataLayout;
33class GISelCSEInfo;
34class GlobalValue;
35class TargetRegisterClass;
36class MachineFunction;
37class MachineInstr;
38class TargetInstrInfo;
39class GISelChangeObserver;
40
41/// Class which stores all the state required in a MachineIRBuilder.
42/// Since MachineIRBuilders will only store state in this object, it allows
43/// to transfer BuilderState between different kinds of MachineIRBuilders.
45 /// MachineFunction under construction.
46 MachineFunction *MF = nullptr;
47 /// Information used to access the description of the opcodes.
48 const TargetInstrInfo *TII = nullptr;
49 /// Information used to verify types are consistent and to create virtual registers.
51 /// Debug location to be set to any instruction we create.
53 /// PC sections metadata to be set to any instruction we create.
54 MDNode *PCSections = nullptr;
55
56 /// \name Fields describing the insertion point.
57 /// @{
60 /// @}
61
63
65};
66
67class DstOp {
68 union {
72 };
73
74public:
75 enum class DstType { Ty_LLT, Ty_Reg, Ty_RC };
76 DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {}
77 DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {}
79 DstOp(const LLT T) : LLTTy(T), Ty(DstType::Ty_LLT) {}
80 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {}
81
83 switch (Ty) {
84 case DstType::Ty_Reg:
85 MIB.addDef(Reg);
86 break;
87 case DstType::Ty_LLT:
88 MIB.addDef(MRI.createGenericVirtualRegister(LLTTy));
89 break;
90 case DstType::Ty_RC:
91 MIB.addDef(MRI.createVirtualRegister(RC));
92 break;
93 }
94 }
95
97 switch (Ty) {
98 case DstType::Ty_RC:
99 return LLT{};
100 case DstType::Ty_LLT:
101 return LLTTy;
102 case DstType::Ty_Reg:
103 return MRI.getType(Reg);
104 }
105 llvm_unreachable("Unrecognised DstOp::DstType enum");
106 }
107
108 Register getReg() const {
109 assert(Ty == DstType::Ty_Reg && "Not a register");
110 return Reg;
111 }
112
114 switch (Ty) {
115 case DstType::Ty_RC:
116 return RC;
117 default:
118 llvm_unreachable("Not a RC Operand");
119 }
120 }
121
122 DstType getDstOpKind() const { return Ty; }
123
124private:
125 DstType Ty;
126};
127
128class SrcOp {
129 union {
133 int64_t Imm;
134 };
135
136public:
138 SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {}
140 SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {}
142 /// Use of registers held in unsigned integer variables (or more rarely signed
143 /// integers) is no longer permitted to avoid ambiguity with upcoming support
144 /// for immediates.
145 SrcOp(unsigned) = delete;
146 SrcOp(int) = delete;
147 SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
148 SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
149
151 switch (Ty) {
153 MIB.addPredicate(Pred);
154 break;
155 case SrcType::Ty_Reg:
156 MIB.addUse(Reg);
157 break;
158 case SrcType::Ty_MIB:
159 MIB.addUse(SrcMIB->getOperand(0).getReg());
160 break;
161 case SrcType::Ty_Imm:
162 MIB.addImm(Imm);
163 break;
164 }
165 }
166
168 switch (Ty) {
170 case SrcType::Ty_Imm:
171 llvm_unreachable("Not a register operand");
172 case SrcType::Ty_Reg:
173 return MRI.getType(Reg);
174 case SrcType::Ty_MIB:
175 return MRI.getType(SrcMIB->getOperand(0).getReg());
176 }
177 llvm_unreachable("Unrecognised SrcOp::SrcType enum");
178 }
179
180 Register getReg() const {
181 switch (Ty) {
183 case SrcType::Ty_Imm:
184 llvm_unreachable("Not a register operand");
185 case SrcType::Ty_Reg:
186 return Reg;
187 case SrcType::Ty_MIB:
188 return SrcMIB->getOperand(0).getReg();
189 }
190 llvm_unreachable("Unrecognised SrcOp::SrcType enum");
191 }
192
194 switch (Ty) {
196 return Pred;
197 default:
198 llvm_unreachable("Not a register operand");
199 }
200 }
201
202 int64_t getImm() const {
203 switch (Ty) {
204 case SrcType::Ty_Imm:
205 return Imm;
206 default:
207 llvm_unreachable("Not an immediate");
208 }
209 }
210
211 SrcType getSrcOpKind() const { return Ty; }
212
213private:
214 SrcType Ty;
215};
216
217/// Helper class to build MachineInstr.
218/// It keeps internally the insertion point and debug location for all
219/// the new instructions we want to create.
220/// This information can be modified via the related setters.
222
224
225 unsigned getOpcodeForMerge(const DstOp &DstOp, ArrayRef<SrcOp> SrcOps) const;
226
227protected:
228 void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend);
229
230 void validateUnaryOp(const LLT Res, const LLT Op0);
231 void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1);
232 void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1);
233
234 void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty,
235 const LLT Op1Ty);
236
237 void recordInsertion(MachineInstr *InsertedInstr) const {
238 if (State.Observer)
239 State.Observer->createdInstr(*InsertedInstr);
240 }
241
242public:
243 /// Some constructors for easy use.
244 MachineIRBuilder() = default;
246
248 setMF(*MBB.getParent());
249 setInsertPt(MBB, InsPt);
250 }
251
253 MachineIRBuilder(*MI.getParent(), MI.getIterator()) {
254 setInstr(MI);
255 setDebugLoc(MI.getDebugLoc());
256 }
257
260 setChangeObserver(Observer);
261 }
262
263 virtual ~MachineIRBuilder() = default;
264
265 MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {}
266
268 assert(State.TII && "TargetInstrInfo is not set");
269 return *State.TII;
270 }
271
272 /// Getter for the function we currently build.
274 assert(State.MF && "MachineFunction is not set");
275 return *State.MF;
276 }
277
278 const MachineFunction &getMF() const {
279 assert(State.MF && "MachineFunction is not set");
280 return *State.MF;
281 }
282
283 const DataLayout &getDataLayout() const {
285 }
286
288 return getMF().getFunction().getContext();
289 }
290
291 /// Getter for DebugLoc
292 const DebugLoc &getDL() { return State.DL; }
293
294 /// Getter for MRI
295 MachineRegisterInfo *getMRI() { return State.MRI; }
296 const MachineRegisterInfo *getMRI() const { return State.MRI; }
297
298 /// Getter for the State
299 MachineIRBuilderState &getState() { return State; }
300
301 /// Getter for the basic block we currently build.
302 const MachineBasicBlock &getMBB() const {
303 assert(State.MBB && "MachineBasicBlock is not set");
304 return *State.MBB;
305 }
306
308 return const_cast<MachineBasicBlock &>(
309 const_cast<const MachineIRBuilder *>(this)->getMBB());
310 }
311
312 GISelCSEInfo *getCSEInfo() { return State.CSEInfo; }
313 const GISelCSEInfo *getCSEInfo() const { return State.CSEInfo; }
314
315 /// Current insertion point for new instructions.
317
318 /// Set the insertion point before the specified position.
319 /// \pre MBB must be in getMF().
320 /// \pre II must be a valid iterator in MBB.
322 assert(MBB.getParent() == &getMF() &&
323 "Basic block is in a different function");
324 State.MBB = &MBB;
325 State.II = II;
326 }
327
328 /// @}
329
331
332 /// \name Setters for the insertion point.
333 /// @{
334 /// Set the MachineFunction where to build instructions.
335 void setMF(MachineFunction &MF);
336
337 /// Set the insertion point to the end of \p MBB.
338 /// \pre \p MBB must be contained by getMF().
340 State.MBB = &MBB;
341 State.II = MBB.end();
342 assert(&getMF() == MBB.getParent() &&
343 "Basic block is in a different function");
344 }
345
346 /// Set the insertion point to before MI.
347 /// \pre MI must be in getMF().
349 assert(MI.getParent() && "Instruction is not part of a basic block");
350 setMBB(*MI.getParent());
351 State.II = MI.getIterator();
352 setPCSections(MI.getPCSections());
353 }
354 /// @}
355
356 /// Set the insertion point to before MI, and set the debug loc to MI's loc.
357 /// \pre MI must be in getMF().
359 setInstr(MI);
360 setDebugLoc(MI.getDebugLoc());
361 }
362
364 State.Observer = &Observer;
365 }
366
368
369 void stopObservingChanges() { State.Observer = nullptr; }
370
371 bool isObservingChanges() const { return State.Observer != nullptr; }
372 /// @}
373
374 /// Set the debug location to \p DL for all the next build instructions.
375 void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; }
376
377 /// Get the current instruction's debug location.
378 const DebugLoc &getDebugLoc() { return State.DL; }
379
380 /// Set the PC sections metadata to \p MD for all the next build instructions.
381 void setPCSections(MDNode *MD) { State.PCSections = MD; }
382
383 /// Get the current instruction's PC sections metadata.
384 MDNode *getPCSections() { return State.PCSections; }
385
386 /// Build and insert <empty> = \p Opcode <empty>.
387 /// The insertion point is the one set by the last call of either
388 /// setBasicBlock or setMI.
389 ///
390 /// \pre setBasicBlock or setMI must have been called.
391 ///
392 /// \return a MachineInstrBuilder for the newly created instruction.
394 return insertInstr(buildInstrNoInsert(Opcode));
395 }
396
397 /// Build but don't insert <empty> = \p Opcode <empty>.
398 ///
399 /// \pre setMF, setBasicBlock or setMI must have been called.
400 ///
401 /// \return a MachineInstrBuilder for the newly created instruction.
403
404 /// Insert an existing instruction at the insertion point.
406
407 /// Build and insert a DBG_VALUE instruction expressing the fact that the
408 /// associated \p Variable lives in \p Reg (suitably modified by \p Expr).
410 const MDNode *Expr);
411
412 /// Build and insert a DBG_VALUE instruction expressing the fact that the
413 /// associated \p Variable lives in memory at \p Reg (suitably modified by \p
414 /// Expr).
416 const MDNode *Variable,
417 const MDNode *Expr);
418
419 /// Build and insert a DBG_VALUE instruction expressing the fact that the
420 /// associated \p Variable lives in the stack slot specified by \p FI
421 /// (suitably modified by \p Expr).
422 MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable,
423 const MDNode *Expr);
424
425 /// Build and insert a DBG_VALUE instructions specifying that \p Variable is
426 /// given by \p C (suitably modified by \p Expr).
428 const MDNode *Variable,
429 const MDNode *Expr);
430
431 /// Build and insert a DBG_LABEL instructions specifying that \p Label is
432 /// given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label".
434
435 /// Build and insert \p Res = G_DYN_STACKALLOC \p Size, \p Align
436 ///
437 /// G_DYN_STACKALLOC does a dynamic stack allocation and writes the address of
438 /// the allocated memory into \p Res.
439 /// \pre setBasicBlock or setMI must have been called.
440 /// \pre \p Res must be a generic virtual register with pointer type.
441 ///
442 /// \return a MachineInstrBuilder for the newly created instruction.
444 Align Alignment);
445
446 /// Build and insert \p Res = G_FRAME_INDEX \p Idx
447 ///
448 /// G_FRAME_INDEX materializes the address of an alloca value or other
449 /// stack-based object.
450 ///
451 /// \pre setBasicBlock or setMI must have been called.
452 /// \pre \p Res must be a generic virtual register with pointer type.
453 ///
454 /// \return a MachineInstrBuilder for the newly created instruction.
456
457 /// Build and insert \p Res = G_GLOBAL_VALUE \p GV
458 ///
459 /// G_GLOBAL_VALUE materializes the address of the specified global
460 /// into \p Res.
461 ///
462 /// \pre setBasicBlock or setMI must have been called.
463 /// \pre \p Res must be a generic virtual register with pointer type
464 /// in the same address space as \p GV.
465 ///
466 /// \return a MachineInstrBuilder for the newly created instruction.
468
469 /// Build and insert \p Res = G_CONSTANT_POOL \p Idx
470 ///
471 /// G_CONSTANT_POOL materializes the address of an object in the constant
472 /// pool.
473 ///
474 /// \pre setBasicBlock or setMI must have been called.
475 /// \pre \p Res must be a generic virtual register with pointer type.
476 ///
477 /// \return a MachineInstrBuilder for the newly created instruction.
478 MachineInstrBuilder buildConstantPool(const DstOp &Res, unsigned Idx);
479
480 /// Build and insert \p Res = G_PTR_ADD \p Op0, \p Op1
481 ///
482 /// G_PTR_ADD adds \p Op1 addressible units to the pointer specified by \p Op0,
483 /// storing the resulting pointer in \p Res. Addressible units are typically
484 /// bytes but this can vary between targets.
485 ///
486 /// \pre setBasicBlock or setMI must have been called.
487 /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
488 /// type.
489 /// \pre \p Op1 must be a generic virtual register with scalar type.
490 ///
491 /// \return a MachineInstrBuilder for the newly created instruction.
492 MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0,
493 const SrcOp &Op1,
494 std::optional<unsigned> Flags = std::nullopt);
495
496 /// Materialize and insert \p Res = G_PTR_ADD \p Op0, (G_CONSTANT \p Value)
497 ///
498 /// G_PTR_ADD adds \p Value bytes to the pointer specified by \p Op0,
499 /// storing the resulting pointer in \p Res. If \p Value is zero then no
500 /// G_PTR_ADD or G_CONSTANT will be created and \pre Op0 will be assigned to
501 /// \p Res.
502 ///
503 /// \pre setBasicBlock or setMI must have been called.
504 /// \pre \p Op0 must be a generic virtual register with pointer type.
505 /// \pre \p ValueTy must be a scalar type.
506 /// \pre \p Res must be 0. This is to detect confusion between
507 /// materializePtrAdd() and buildPtrAdd().
508 /// \post \p Res will either be a new generic virtual register of the same
509 /// type as \p Op0 or \p Op0 itself.
510 ///
511 /// \return a MachineInstrBuilder for the newly created instruction.
512 std::optional<MachineInstrBuilder> materializePtrAdd(Register &Res,
513 Register Op0,
514 const LLT ValueTy,
516
517 /// Build and insert \p Res = G_PTRMASK \p Op0, \p Op1
519 const SrcOp &Op1) {
520 return buildInstr(TargetOpcode::G_PTRMASK, {Res}, {Op0, Op1});
521 }
522
523 /// Build and insert \p Res = G_PTRMASK \p Op0, \p G_CONSTANT (1 << NumBits) - 1
524 ///
525 /// This clears the low bits of a pointer operand without destroying its
526 /// pointer properties. This has the effect of rounding the address *down* to
527 /// a specified alignment in bits.
528 ///
529 /// \pre setBasicBlock or setMI must have been called.
530 /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
531 /// type.
532 /// \pre \p NumBits must be an integer representing the number of low bits to
533 /// be cleared in \p Op0.
534 ///
535 /// \return a MachineInstrBuilder for the newly created instruction.
536 MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0,
537 uint32_t NumBits);
538
539 /// Build and insert
540 /// a, b, ..., x = G_UNMERGE_VALUES \p Op0
541 /// \p Res = G_BUILD_VECTOR a, b, ..., x, undef, ..., undef
542 ///
543 /// Pad \p Op0 with undef elements to match number of elements in \p Res.
544 ///
545 /// \pre setBasicBlock or setMI must have been called.
546 /// \pre \p Res and \p Op0 must be generic virtual registers with vector type,
547 /// same vector element type and Op0 must have fewer elements then Res.
548 ///
549 /// \return a MachineInstrBuilder for the newly created build vector instr.
551 const SrcOp &Op0);
552
553 /// Build and insert
554 /// a, b, ..., x, y, z = G_UNMERGE_VALUES \p Op0
555 /// \p Res = G_BUILD_VECTOR a, b, ..., x
556 ///
557 /// Delete trailing elements in \p Op0 to match number of elements in \p Res.
558 ///
559 /// \pre setBasicBlock or setMI must have been called.
560 /// \pre \p Res and \p Op0 must be generic virtual registers with vector type,
561 /// same vector element type and Op0 must have more elements then Res.
562 ///
563 /// \return a MachineInstrBuilder for the newly created build vector instr.
565 const SrcOp &Op0);
566
567 /// Build and insert \p Res, \p CarryOut = G_UADDO \p Op0, \p Op1
568 ///
569 /// G_UADDO sets \p Res to \p Op0 + \p Op1 (truncated to the bit width) and
570 /// sets \p CarryOut to 1 if the result overflowed in unsigned arithmetic.
571 ///
572 /// \pre setBasicBlock or setMI must have been called.
573 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers with the
574 /// same scalar type.
575 ////\pre \p CarryOut must be generic virtual register with scalar type
576 ///(typically s1)
577 ///
578 /// \return The newly created instruction.
579 MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut,
580 const SrcOp &Op0, const SrcOp &Op1) {
581 return buildInstr(TargetOpcode::G_UADDO, {Res, CarryOut}, {Op0, Op1});
582 }
583
584 /// Build and insert \p Res, \p CarryOut = G_USUBO \p Op0, \p Op1
585 MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut,
586 const SrcOp &Op0, const SrcOp &Op1) {
587 return buildInstr(TargetOpcode::G_USUBO, {Res, CarryOut}, {Op0, Op1});
588 }
589
590 /// Build and insert \p Res, \p CarryOut = G_SADDO \p Op0, \p Op1
591 MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut,
592 const SrcOp &Op0, const SrcOp &Op1) {
593 return buildInstr(TargetOpcode::G_SADDO, {Res, CarryOut}, {Op0, Op1});
594 }
595
596 /// Build and insert \p Res, \p CarryOut = G_SUBO \p Op0, \p Op1
597 MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut,
598 const SrcOp &Op0, const SrcOp &Op1) {
599 return buildInstr(TargetOpcode::G_SSUBO, {Res, CarryOut}, {Op0, Op1});
600 }
601
602 /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0,
603 /// \p Op1, \p CarryIn
604 ///
605 /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit
606 /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned
607 /// arithmetic.
608 ///
609 /// \pre setBasicBlock or setMI must have been called.
610 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
611 /// with the same scalar type.
612 /// \pre \p CarryOut and \p CarryIn must be generic virtual
613 /// registers with the same scalar type (typically s1)
614 ///
615 /// \return The newly created instruction.
616 MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut,
617 const SrcOp &Op0, const SrcOp &Op1,
618 const SrcOp &CarryIn) {
619 return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut},
620 {Op0, Op1, CarryIn});
621 }
622
623 /// Build and insert \p Res, \p CarryOut = G_USUBE \p Op0, \p Op1, \p CarryInp
624 MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut,
625 const SrcOp &Op0, const SrcOp &Op1,
626 const SrcOp &CarryIn) {
627 return buildInstr(TargetOpcode::G_USUBE, {Res, CarryOut},
628 {Op0, Op1, CarryIn});
629 }
630
631 /// Build and insert \p Res, \p CarryOut = G_SADDE \p Op0, \p Op1, \p CarryInp
632 MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut,
633 const SrcOp &Op0, const SrcOp &Op1,
634 const SrcOp &CarryIn) {
635 return buildInstr(TargetOpcode::G_SADDE, {Res, CarryOut},
636 {Op0, Op1, CarryIn});
637 }
638
639 /// Build and insert \p Res, \p CarryOut = G_SSUBE \p Op0, \p Op1, \p CarryInp
640 MachineInstrBuilder buildSSube(const DstOp &Res, const DstOp &CarryOut,
641 const SrcOp &Op0, const SrcOp &Op1,
642 const SrcOp &CarryIn) {
643 return buildInstr(TargetOpcode::G_SSUBE, {Res, CarryOut},
644 {Op0, Op1, CarryIn});
645 }
646
647 /// Build and insert \p Res = G_ANYEXT \p Op0
648 ///
649 /// G_ANYEXT produces a register of the specified width, with bits 0 to
650 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified
651 /// (i.e. this is neither zero nor sign-extension). For a vector register,
652 /// each element is extended individually.
653 ///
654 /// \pre setBasicBlock or setMI must have been called.
655 /// \pre \p Res must be a generic virtual register with scalar or vector type.
656 /// \pre \p Op must be a generic virtual register with scalar or vector type.
657 /// \pre \p Op must be smaller than \p Res
658 ///
659 /// \return The newly created instruction.
660
661 MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);
662
663 /// Build and insert \p Res = G_SEXT \p Op
664 ///
665 /// G_SEXT produces a register of the specified width, with bits 0 to
666 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the
667 /// high bit of \p Op (i.e. 2s-complement sign extended).
668 ///
669 /// \pre setBasicBlock or setMI must have been called.
670 /// \pre \p Res must be a generic virtual register with scalar or vector type.
671 /// \pre \p Op must be a generic virtual register with scalar or vector type.
672 /// \pre \p Op must be smaller than \p Res
673 ///
674 /// \return The newly created instruction.
675 MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op);
676
677 /// Build and insert \p Res = G_SEXT_INREG \p Op, ImmOp
678 MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp) {
679 return buildInstr(TargetOpcode::G_SEXT_INREG, {Res}, {Op, SrcOp(ImmOp)});
680 }
681
682 /// Build and insert \p Res = G_FPEXT \p Op
684 std::optional<unsigned> Flags = std::nullopt) {
685 return buildInstr(TargetOpcode::G_FPEXT, {Res}, {Op}, Flags);
686 }
687
688 /// Build and insert a G_PTRTOINT instruction.
690 return buildInstr(TargetOpcode::G_PTRTOINT, {Dst}, {Src});
691 }
692
693 /// Build and insert a G_INTTOPTR instruction.
695 return buildInstr(TargetOpcode::G_INTTOPTR, {Dst}, {Src});
696 }
697
698 /// Build and insert \p Dst = G_BITCAST \p Src
699 MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) {
700 return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src});
701 }
702
703 /// Build and insert \p Dst = G_ADDRSPACE_CAST \p Src
705 return buildInstr(TargetOpcode::G_ADDRSPACE_CAST, {Dst}, {Src});
706 }
707
708 /// \return The opcode of the extension the target wants to use for boolean
709 /// values.
710 unsigned getBoolExtOp(bool IsVec, bool IsFP) const;
711
712 // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_SEXT \p Op, or \p Res
713 // = G_ZEXT \p Op depending on how the target wants to extend boolean values.
714 MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op,
715 bool IsFP);
716
717 // Build and insert \p Res = G_SEXT_INREG \p Op, 1 or \p Res = G_AND \p Op, 1,
718 // or COPY depending on how the target wants to extend boolean values, using
719 // the original register size.
721 bool IsVector,
722 bool IsFP);
723
724 /// Build and insert \p Res = G_ZEXT \p Op
725 ///
726 /// G_ZEXT produces a register of the specified width, with bits 0 to
727 /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector
728 /// register, each element is extended individually.
729 ///
730 /// \pre setBasicBlock or setMI must have been called.
731 /// \pre \p Res must be a generic virtual register with scalar or vector type.
732 /// \pre \p Op must be a generic virtual register with scalar or vector type.
733 /// \pre \p Op must be smaller than \p Res
734 ///
735 /// \return The newly created instruction.
736 MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op);
737
738 /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or
739 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
740 /// ///
741 /// \pre setBasicBlock or setMI must have been called.
742 /// \pre \p Res must be a generic virtual register with scalar or vector type.
743 /// \pre \p Op must be a generic virtual register with scalar or vector type.
744 ///
745 /// \return The newly created instruction.
747
748 /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or
749 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
750 /// ///
751 /// \pre setBasicBlock or setMI must have been called.
752 /// \pre \p Res must be a generic virtual register with scalar or vector type.
753 /// \pre \p Op must be a generic virtual register with scalar or vector type.
754 ///
755 /// \return The newly created instruction.
757
758 // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or
759 /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
760 /// ///
761 /// \pre setBasicBlock or setMI must have been called.
762 /// \pre \p Res must be a generic virtual register with scalar or vector type.
763 /// \pre \p Op must be a generic virtual register with scalar or vector type.
764 ///
765 /// \return The newly created instruction.
767
768 /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p
769 /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and
770 /// \p Op.
771 /// ///
772 /// \pre setBasicBlock or setMI must have been called.
773 /// \pre \p Res must be a generic virtual register with scalar or vector type.
774 /// \pre \p Op must be a generic virtual register with scalar or vector type.
775 ///
776 /// \return The newly created instruction.
777 MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
778 const SrcOp &Op);
779
780 /// Build and inserts \p Res = \p G_AND \p Op, \p LowBitsSet(ImmOp)
781 /// Since there is no G_ZEXT_INREG like G_SEXT_INREG, the instruction is
782 /// emulated using G_AND.
784 int64_t ImmOp);
785
786 /// Build and insert an appropriate cast between two registers of equal size.
787 MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src);
788
789 /// Build and insert G_BR \p Dest
790 ///
791 /// G_BR is an unconditional branch to \p Dest.
792 ///
793 /// \pre setBasicBlock or setMI must have been called.
794 ///
795 /// \return a MachineInstrBuilder for the newly created instruction.
797
798 /// Build and insert G_BRCOND \p Tst, \p Dest
799 ///
800 /// G_BRCOND is a conditional branch to \p Dest.
801 ///
802 /// \pre setBasicBlock or setMI must have been called.
803 /// \pre \p Tst must be a generic virtual register with scalar
804 /// type. At the beginning of legalization, this will be a single
805 /// bit (s1). Targets with interesting flags registers may change
806 /// this. For a wider type, whether the branch is taken must only
807 /// depend on bit 0 (for now).
808 ///
809 /// \return The newly created instruction.
811
812 /// Build and insert G_BRINDIRECT \p Tgt
813 ///
814 /// G_BRINDIRECT is an indirect branch to \p Tgt.
815 ///
816 /// \pre setBasicBlock or setMI must have been called.
817 /// \pre \p Tgt must be a generic virtual register with pointer type.
818 ///
819 /// \return a MachineInstrBuilder for the newly created instruction.
821
822 /// Build and insert G_BRJT \p TablePtr, \p JTI, \p IndexReg
823 ///
824 /// G_BRJT is a jump table branch using a table base pointer \p TablePtr,
825 /// jump table index \p JTI and index \p IndexReg
826 ///
827 /// \pre setBasicBlock or setMI must have been called.
828 /// \pre \p TablePtr must be a generic virtual register with pointer type.
829 /// \pre \p JTI must be a jump table index.
830 /// \pre \p IndexReg must be a generic virtual register with pointer type.
831 ///
832 /// \return a MachineInstrBuilder for the newly created instruction.
833 MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI,
834 Register IndexReg);
835
836 /// Build and insert \p Res = G_CONSTANT \p Val
837 ///
838 /// G_CONSTANT is an integer constant with the specified size and value. \p
839 /// Val will be extended or truncated to the size of \p Reg.
840 ///
841 /// \pre setBasicBlock or setMI must have been called.
842 /// \pre \p Res must be a generic virtual register with scalar or pointer
843 /// type.
844 ///
845 /// \return The newly created instruction.
846 virtual MachineInstrBuilder buildConstant(const DstOp &Res,
847 const ConstantInt &Val);
848
849 /// Build and insert \p Res = G_CONSTANT \p Val
850 ///
851 /// G_CONSTANT is an integer constant with the specified size and value.
852 ///
853 /// \pre setBasicBlock or setMI must have been called.
854 /// \pre \p Res must be a generic virtual register with scalar type.
855 ///
856 /// \return The newly created instruction.
857 MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val);
858 MachineInstrBuilder buildConstant(const DstOp &Res, const APInt &Val);
859
860 /// Build and insert \p Res = G_FCONSTANT \p Val
861 ///
862 /// G_FCONSTANT is a floating-point constant with the specified size and
863 /// value.
864 ///
865 /// \pre setBasicBlock or setMI must have been called.
866 /// \pre \p Res must be a generic virtual register with scalar type.
867 ///
868 /// \return The newly created instruction.
869 virtual MachineInstrBuilder buildFConstant(const DstOp &Res,
870 const ConstantFP &Val);
871
872 MachineInstrBuilder buildFConstant(const DstOp &Res, double Val);
873 MachineInstrBuilder buildFConstant(const DstOp &Res, const APFloat &Val);
874
875 /// Build and insert \p Res = COPY Op
876 ///
877 /// Register-to-register COPY sets \p Res to \p Op.
878 ///
879 /// \pre setBasicBlock or setMI must have been called.
880 ///
881 /// \return a MachineInstrBuilder for the newly created instruction.
882 MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);
883
884
885 /// Build and insert G_ASSERT_SEXT, G_ASSERT_ZEXT, or G_ASSERT_ALIGN
886 ///
887 /// \return a MachineInstrBuilder for the newly created instruction.
889 const SrcOp &Op, unsigned Val) {
890 return buildInstr(Opc, Res, Op).addImm(Val);
891 }
892
893 /// Build and insert \p Res = G_ASSERT_ZEXT Op, Size
894 ///
895 /// \return a MachineInstrBuilder for the newly created instruction.
897 unsigned Size) {
898 return buildAssertInstr(TargetOpcode::G_ASSERT_ZEXT, Res, Op, Size);
899 }
900
901 /// Build and insert \p Res = G_ASSERT_SEXT Op, Size
902 ///
903 /// \return a MachineInstrBuilder for the newly created instruction.
905 unsigned Size) {
906 return buildAssertInstr(TargetOpcode::G_ASSERT_SEXT, Res, Op, Size);
907 }
908
909 /// Build and insert \p Res = G_ASSERT_ALIGN Op, AlignVal
910 ///
911 /// \return a MachineInstrBuilder for the newly created instruction.
913 Align AlignVal) {
914 return buildAssertInstr(TargetOpcode::G_ASSERT_ALIGN, Res, Op,
915 AlignVal.value());
916 }
917
918 /// Build and insert `Res = G_LOAD Addr, MMO`.
919 ///
920 /// Loads the value stored at \p Addr. Puts the result in \p Res.
921 ///
922 /// \pre setBasicBlock or setMI must have been called.
923 /// \pre \p Res must be a generic virtual register.
924 /// \pre \p Addr must be a generic virtual register with pointer type.
925 ///
926 /// \return a MachineInstrBuilder for the newly created instruction.
928 MachineMemOperand &MMO) {
929 return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO);
930 }
931
932 /// Build and insert a G_LOAD instruction, while constructing the
933 /// MachineMemOperand.
935 buildLoad(const DstOp &Res, const SrcOp &Addr, MachinePointerInfo PtrInfo,
936 Align Alignment,
938 const AAMDNodes &AAInfo = AAMDNodes());
939
940 /// Build and insert `Res = <opcode> Addr, MMO`.
941 ///
942 /// Loads the value stored at \p Addr. Puts the result in \p Res.
943 ///
944 /// \pre setBasicBlock or setMI must have been called.
945 /// \pre \p Res must be a generic virtual register.
946 /// \pre \p Addr must be a generic virtual register with pointer type.
947 ///
948 /// \return a MachineInstrBuilder for the newly created instruction.
949 MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res,
950 const SrcOp &Addr, MachineMemOperand &MMO);
951
952 /// Helper to create a load from a constant offset given a base address. Load
953 /// the type of \p Dst from \p Offset from the given base address and memory
954 /// operand.
956 const SrcOp &BasePtr,
957 MachineMemOperand &BaseMMO,
958 int64_t Offset);
959
960 /// Build and insert `G_STORE Val, Addr, MMO`.
961 ///
962 /// Stores the value \p Val to \p Addr.
963 ///
964 /// \pre setBasicBlock or setMI must have been called.
965 /// \pre \p Val must be a generic virtual register.
966 /// \pre \p Addr must be a generic virtual register with pointer type.
967 ///
968 /// \return a MachineInstrBuilder for the newly created instruction.
969 MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr,
970 MachineMemOperand &MMO);
971
972 /// Build and insert a G_STORE instruction, while constructing the
973 /// MachineMemOperand.
975 buildStore(const SrcOp &Val, const SrcOp &Addr, MachinePointerInfo PtrInfo,
976 Align Alignment,
978 const AAMDNodes &AAInfo = AAMDNodes());
979
980 /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.
981 ///
982 /// \pre setBasicBlock or setMI must have been called.
983 /// \pre \p Res and \p Src must be generic virtual registers.
984 ///
985 /// \return a MachineInstrBuilder for the newly created instruction.
986 MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index);
987
988 /// Build and insert \p Res = IMPLICIT_DEF.
990
991 /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
992 ///
993 /// G_MERGE_VALUES combines the input elements contiguously into a larger
994 /// register. It should only be used when the destination register is not a
995 /// vector.
996 ///
997 /// \pre setBasicBlock or setMI must have been called.
998 /// \pre The entire register \p Res (and no more) must be covered by the input
999 /// registers.
1000 /// \pre The type of all \p Ops registers must be identical.
1001 ///
1002 /// \return a MachineInstrBuilder for the newly created instruction.
1004 ArrayRef<Register> Ops);
1005
1006 /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
1007 /// or \p Res = G_BUILD_VECTOR \p Op0, ...
1008 /// or \p Res = G_CONCAT_VECTORS \p Op0, ...
1009 ///
1010 /// G_MERGE_VALUES combines the input elements contiguously into a larger
1011 /// register. It is used when the destination register is not a vector.
1012 /// G_BUILD_VECTOR combines scalar inputs into a vector register.
1013 /// G_CONCAT_VECTORS combines vector inputs into a vector register.
1014 ///
1015 /// \pre setBasicBlock or setMI must have been called.
1016 /// \pre The entire register \p Res (and no more) must be covered by the input
1017 /// registers.
1018 /// \pre The type of all \p Ops registers must be identical.
1019 ///
1020 /// \return a MachineInstrBuilder for the newly created instruction. The
1021 /// opcode of the new instruction will depend on the types of both
1022 /// the destination and the sources.
1024 ArrayRef<Register> Ops);
1026 std::initializer_list<SrcOp> Ops);
1027
1028 /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op
1029 ///
1030 /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple
1031 ///
1032 /// \pre setBasicBlock or setMI must have been called.
1033 /// \pre The entire register \p Res (and no more) must be covered by the input
1034 /// registers.
1035 /// \pre The type of all \p Res registers must be identical.
1036 ///
1037 /// \return a MachineInstrBuilder for the newly created instruction.
1040
1041 /// Build and insert an unmerge of \p Res sized pieces to cover \p Op
1043
1044 /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ...
1045 ///
1046 /// G_BUILD_VECTOR creates a vector value from multiple scalar registers.
1047 /// \pre setBasicBlock or setMI must have been called.
1048 /// \pre The entire register \p Res (and no more) must be covered by the
1049 /// input scalar registers.
1050 /// \pre The type of all \p Ops registers must be identical.
1051 ///
1052 /// \return a MachineInstrBuilder for the newly created instruction.
1054 ArrayRef<Register> Ops);
1055
1056 /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ... where each OpN is
1057 /// built with G_CONSTANT.
1059 ArrayRef<APInt> Ops);
1060
1061 /// Build and insert \p Res = G_BUILD_VECTOR with \p Src replicated to fill
1062 /// the number of elements
1064 const SrcOp &Src);
1065
1066 /// Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ...
1067 ///
1068 /// G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers
1069 /// which have types larger than the destination vector element type, and
1070 /// truncates the values to fit.
1071 ///
1072 /// If the operands given are already the same size as the vector elt type,
1073 /// then this method will instead create a G_BUILD_VECTOR instruction.
1074 ///
1075 /// \pre setBasicBlock or setMI must have been called.
1076 /// \pre The type of all \p Ops registers must be identical.
1077 ///
1078 /// \return a MachineInstrBuilder for the newly created instruction.
1080 ArrayRef<Register> Ops);
1081
1082 /// Build and insert a vector splat of a scalar \p Src using a
1083 /// G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idiom.
1084 ///
1085 /// \pre setBasicBlock or setMI must have been called.
1086 /// \pre \p Src must have the same type as the element type of \p Dst
1087 ///
1088 /// \return a MachineInstrBuilder for the newly created instruction.
1089 MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src);
1090
1091 /// Build and insert \p Res = G_SHUFFLE_VECTOR \p Src1, \p Src2, \p Mask
1092 ///
1093 /// \pre setBasicBlock or setMI must have been called.
1094 ///
1095 /// \return a MachineInstrBuilder for the newly created instruction.
1096 MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1,
1097 const SrcOp &Src2, ArrayRef<int> Mask);
1098
1099 /// Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ...
1100 ///
1101 /// G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more
1102 /// vectors.
1103 ///
1104 /// \pre setBasicBlock or setMI must have been called.
1105 /// \pre The entire register \p Res (and no more) must be covered by the input
1106 /// registers.
1107 /// \pre The type of all source operands must be identical.
1108 ///
1109 /// \return a MachineInstrBuilder for the newly created instruction.
1111 ArrayRef<Register> Ops);
1112
1113 MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src,
1114 const SrcOp &Op, unsigned Index);
1115
1116 /// Build and insert a G_INTRINSIC instruction.
1117 ///
1118 /// There are four different opcodes based on combinations of whether the
1119 /// intrinsic has side effects and whether it is convergent. These properties
1120 /// can be specified as explicit parameters, or else they are retrieved from
1121 /// the MCID for the intrinsic.
1122 ///
1123 /// The parameter \p Res provides the Registers or MOs that will be defined by
1124 /// this instruction.
1125 ///
1126 /// \pre setBasicBlock or setMI must have been called.
1127 ///
1128 /// \return a MachineInstrBuilder for the newly created instruction.
1130 bool HasSideEffects, bool isConvergent);
1133 bool HasSideEffects, bool isConvergent);
1135
1136 /// Build and insert \p Res = G_FPTRUNC \p Op
1137 ///
1138 /// G_FPTRUNC converts a floating-point value into one with a smaller type.
1139 ///
1140 /// \pre setBasicBlock or setMI must have been called.
1141 /// \pre \p Res must be a generic virtual register with scalar or vector type.
1142 /// \pre \p Op must be a generic virtual register with scalar or vector type.
1143 /// \pre \p Res must be smaller than \p Op
1144 ///
1145 /// \return The newly created instruction.
1147 buildFPTrunc(const DstOp &Res, const SrcOp &Op,
1148 std::optional<unsigned> Flags = std::nullopt);
1149
1150 /// Build and insert \p Res = G_TRUNC \p Op
1151 ///
1152 /// G_TRUNC extracts the low bits of a type. For a vector type each element is
1153 /// truncated independently before being packed into the destination.
1154 ///
1155 /// \pre setBasicBlock or setMI must have been called.
1156 /// \pre \p Res must be a generic virtual register with scalar or vector type.
1157 /// \pre \p Op must be a generic virtual register with scalar or vector type.
1158 /// \pre \p Res must be smaller than \p Op
1159 ///
1160 /// \return The newly created instruction.
1161 MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op);
1162
1163 /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1
1164 ///
1165 /// \pre setBasicBlock or setMI must have been called.
1166
1167 /// \pre \p Res must be a generic virtual register with scalar or
1168 /// vector type. Typically this starts as s1 or <N x s1>.
1169 /// \pre \p Op0 and Op1 must be generic virtual registers with the
1170 /// same number of elements as \p Res. If \p Res is a scalar,
1171 /// \p Op0 must be either a scalar or pointer.
1172 /// \pre \p Pred must be an integer predicate.
1173 ///
1174 /// \return a MachineInstrBuilder for the newly created instruction.
1176 const SrcOp &Op0, const SrcOp &Op1);
1177
1178 /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1
1179 ///
1180 /// \pre setBasicBlock or setMI must have been called.
1181
1182 /// \pre \p Res must be a generic virtual register with scalar or
1183 /// vector type. Typically this starts as s1 or <N x s1>.
1184 /// \pre \p Op0 and Op1 must be generic virtual registers with the
1185 /// same number of elements as \p Res (or scalar, if \p Res is
1186 /// scalar).
1187 /// \pre \p Pred must be a floating-point predicate.
1188 ///
1189 /// \return a MachineInstrBuilder for the newly created instruction.
1191 const SrcOp &Op0, const SrcOp &Op1,
1192 std::optional<unsigned> Flags = std::nullopt);
1193
1194 /// Build and insert a \p Res = G_IS_FPCLASS \p Pred, \p Src, \p Mask
1196 unsigned Mask) {
1197 return buildInstr(TargetOpcode::G_IS_FPCLASS, {Res},
1198 {Src, SrcOp(static_cast<int64_t>(Mask))});
1199 }
1200
1201 /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1
1202 ///
1203 /// \pre setBasicBlock or setMI must have been called.
1204 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1205 /// with the same type.
1206 /// \pre \p Tst must be a generic virtual register with scalar, pointer or
1207 /// vector type. If vector then it must have the same number of
1208 /// elements as the other parameters.
1209 ///
1210 /// \return a MachineInstrBuilder for the newly created instruction.
1211 MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,
1212 const SrcOp &Op0, const SrcOp &Op1,
1213 std::optional<unsigned> Flags = std::nullopt);
1214
1215 /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val,
1216 /// \p Elt, \p Idx
1217 ///
1218 /// \pre setBasicBlock or setMI must have been called.
1219 /// \pre \p Res and \p Val must be a generic virtual register
1220 // with the same vector type.
1221 /// \pre \p Elt and \p Idx must be a generic virtual register
1222 /// with scalar type.
1223 ///
1224 /// \return The newly created instruction.
1226 const SrcOp &Val,
1227 const SrcOp &Elt,
1228 const SrcOp &Idx);
1229
1230 /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
1231 ///
1232 /// \pre setBasicBlock or setMI must have been called.
1233 /// \pre \p Res must be a generic virtual register with scalar type.
1234 /// \pre \p Val must be a generic virtual register with vector type.
1235 ///
1236 /// \return The newly created instruction.
1238 const SrcOp &Val,
1239 const int Idx) {
1240 return buildExtractVectorElement(Res, Val,
1242 }
1243
1244 /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
1245 ///
1246 /// \pre setBasicBlock or setMI must have been called.
1247 /// \pre \p Res must be a generic virtual register with scalar type.
1248 /// \pre \p Val must be a generic virtual register with vector type.
1249 /// \pre \p Idx must be a generic virtual register with scalar type.
1250 ///
1251 /// \return The newly created instruction.
1253 const SrcOp &Val,
1254 const SrcOp &Idx);
1255
1256 /// Build and insert `OldValRes<def>, SuccessRes<def> =
1257 /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`.
1258 ///
1259 /// Atomically replace the value at \p Addr with \p NewVal if it is currently
1260 /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
1261 /// Addr in \p Res, along with an s1 indicating whether it was replaced.
1262 ///
1263 /// \pre setBasicBlock or setMI must have been called.
1264 /// \pre \p OldValRes must be a generic virtual register of scalar type.
1265 /// \pre \p SuccessRes must be a generic virtual register of scalar type. It
1266 /// will be assigned 0 on failure and 1 on success.
1267 /// \pre \p Addr must be a generic virtual register with pointer type.
1268 /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
1269 /// registers of the same type.
1270 ///
1271 /// \return a MachineInstrBuilder for the newly created instruction.
1273 buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes,
1274 Register Addr, Register CmpVal, Register NewVal,
1275 MachineMemOperand &MMO);
1276
1277 /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal,
1278 /// MMO`.
1279 ///
1280 /// Atomically replace the value at \p Addr with \p NewVal if it is currently
1281 /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
1282 /// Addr in \p Res.
1283 ///
1284 /// \pre setBasicBlock or setMI must have been called.
1285 /// \pre \p OldValRes must be a generic virtual register of scalar type.
1286 /// \pre \p Addr must be a generic virtual register with pointer type.
1287 /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
1288 /// registers of the same type.
1289 ///
1290 /// \return a MachineInstrBuilder for the newly created instruction.
1292 Register CmpVal, Register NewVal,
1293 MachineMemOperand &MMO);
1294
1295 /// Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`.
1296 ///
1297 /// Atomically read-modify-update the value at \p Addr with \p Val. Puts the
1298 /// original value from \p Addr in \p OldValRes. The modification is
1299 /// determined by the opcode.
1300 ///
1301 /// \pre setBasicBlock or setMI must have been called.
1302 /// \pre \p OldValRes must be a generic virtual register.
1303 /// \pre \p Addr must be a generic virtual register with pointer type.
1304 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1305 /// same type.
1306 ///
1307 /// \return a MachineInstrBuilder for the newly created instruction.
1308 MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes,
1309 const SrcOp &Addr, const SrcOp &Val,
1310 MachineMemOperand &MMO);
1311
1312 /// Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`.
1313 ///
1314 /// Atomically replace the value at \p Addr with \p Val. Puts the original
1315 /// value from \p Addr in \p OldValRes.
1316 ///
1317 /// \pre setBasicBlock or setMI must have been called.
1318 /// \pre \p OldValRes must be a generic virtual register.
1319 /// \pre \p Addr must be a generic virtual register with pointer type.
1320 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1321 /// same type.
1322 ///
1323 /// \return a MachineInstrBuilder for the newly created instruction.
1325 Register Val, MachineMemOperand &MMO);
1326
1327 /// Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`.
1328 ///
1329 /// Atomically replace the value at \p Addr with the addition of \p Val and
1330 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1331 ///
1332 /// \pre setBasicBlock or setMI must have been called.
1333 /// \pre \p OldValRes must be a generic virtual register.
1334 /// \pre \p Addr must be a generic virtual register with pointer type.
1335 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1336 /// same type.
1337 ///
1338 /// \return a MachineInstrBuilder for the newly created instruction.
1340 Register Val, MachineMemOperand &MMO);
1341
1342 /// Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`.
1343 ///
1344 /// Atomically replace the value at \p Addr with the subtraction of \p Val and
1345 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1346 ///
1347 /// \pre setBasicBlock or setMI must have been called.
1348 /// \pre \p OldValRes must be a generic virtual register.
1349 /// \pre \p Addr must be a generic virtual register with pointer type.
1350 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1351 /// same type.
1352 ///
1353 /// \return a MachineInstrBuilder for the newly created instruction.
1355 Register Val, MachineMemOperand &MMO);
1356
1357 /// Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`.
1358 ///
1359 /// Atomically replace the value at \p Addr with the bitwise and of \p Val and
1360 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1361 ///
1362 /// \pre setBasicBlock or setMI must have been called.
1363 /// \pre \p OldValRes must be a generic virtual register.
1364 /// \pre \p Addr must be a generic virtual register with pointer type.
1365 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1366 /// same type.
1367 ///
1368 /// \return a MachineInstrBuilder for the newly created instruction.
1370 Register Val, MachineMemOperand &MMO);
1371
1372 /// Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`.
1373 ///
1374 /// Atomically replace the value at \p Addr with the bitwise nand of \p Val
1375 /// and the original value. Puts the original value from \p Addr in \p
1376 /// OldValRes.
1377 ///
1378 /// \pre setBasicBlock or setMI must have been called.
1379 /// \pre \p OldValRes must be a generic virtual register.
1380 /// \pre \p Addr must be a generic virtual register with pointer type.
1381 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1382 /// same type.
1383 ///
1384 /// \return a MachineInstrBuilder for the newly created instruction.
1386 Register Val, MachineMemOperand &MMO);
1387
1388 /// Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`.
1389 ///
1390 /// Atomically replace the value at \p Addr with the bitwise or of \p Val and
1391 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1392 ///
1393 /// \pre setBasicBlock or setMI must have been called.
1394 /// \pre \p OldValRes must be a generic virtual register.
1395 /// \pre \p Addr must be a generic virtual register with pointer type.
1396 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1397 /// same type.
1398 ///
1399 /// \return a MachineInstrBuilder for the newly created instruction.
1401 Register Val, MachineMemOperand &MMO);
1402
1403 /// Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`.
1404 ///
1405 /// Atomically replace the value at \p Addr with the bitwise xor of \p Val and
1406 /// the original value. Puts the original value from \p Addr in \p OldValRes.
1407 ///
1408 /// \pre setBasicBlock or setMI must have been called.
1409 /// \pre \p OldValRes must be a generic virtual register.
1410 /// \pre \p Addr must be a generic virtual register with pointer type.
1411 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1412 /// same type.
1413 ///
1414 /// \return a MachineInstrBuilder for the newly created instruction.
1416 Register Val, MachineMemOperand &MMO);
1417
1418 /// Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`.
1419 ///
1420 /// Atomically replace the value at \p Addr with the signed maximum of \p
1421 /// Val and the original value. Puts the original value from \p Addr in \p
1422 /// OldValRes.
1423 ///
1424 /// \pre setBasicBlock or setMI must have been called.
1425 /// \pre \p OldValRes must be a generic virtual register.
1426 /// \pre \p Addr must be a generic virtual register with pointer type.
1427 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1428 /// same type.
1429 ///
1430 /// \return a MachineInstrBuilder for the newly created instruction.
1432 Register Val, MachineMemOperand &MMO);
1433
1434 /// Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`.
1435 ///
1436 /// Atomically replace the value at \p Addr with the signed minimum of \p
1437 /// Val and the original value. Puts the original value from \p Addr in \p
1438 /// OldValRes.
1439 ///
1440 /// \pre setBasicBlock or setMI must have been called.
1441 /// \pre \p OldValRes must be a generic virtual register.
1442 /// \pre \p Addr must be a generic virtual register with pointer type.
1443 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1444 /// same type.
1445 ///
1446 /// \return a MachineInstrBuilder for the newly created instruction.
1448 Register Val, MachineMemOperand &MMO);
1449
1450 /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`.
1451 ///
1452 /// Atomically replace the value at \p Addr with the unsigned maximum of \p
1453 /// Val and the original value. Puts the original value from \p Addr in \p
1454 /// OldValRes.
1455 ///
1456 /// \pre setBasicBlock or setMI must have been called.
1457 /// \pre \p OldValRes must be a generic virtual register.
1458 /// \pre \p Addr must be a generic virtual register with pointer type.
1459 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1460 /// same type.
1461 ///
1462 /// \return a MachineInstrBuilder for the newly created instruction.
1464 Register Val, MachineMemOperand &MMO);
1465
1466 /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`.
1467 ///
1468 /// Atomically replace the value at \p Addr with the unsigned minimum of \p
1469 /// Val and the original value. Puts the original value from \p Addr in \p
1470 /// OldValRes.
1471 ///
1472 /// \pre setBasicBlock or setMI must have been called.
1473 /// \pre \p OldValRes must be a generic virtual register.
1474 /// \pre \p Addr must be a generic virtual register with pointer type.
1475 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1476 /// same type.
1477 ///
1478 /// \return a MachineInstrBuilder for the newly created instruction.
1480 Register Val, MachineMemOperand &MMO);
1481
1482 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO`.
1484 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1485 MachineMemOperand &MMO);
1486
1487 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO`.
1489 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1490 MachineMemOperand &MMO);
1491
1492 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FMAX Addr, Val, MMO`.
1493 ///
1494 /// Atomically replace the value at \p Addr with the floating point maximum of
1495 /// \p Val and the original value. Puts the original value from \p Addr in \p
1496 /// OldValRes.
1497 ///
1498 /// \pre setBasicBlock or setMI must have been called.
1499 /// \pre \p OldValRes must be a generic virtual register.
1500 /// \pre \p Addr must be a generic virtual register with pointer type.
1501 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1502 /// same type.
1503 ///
1504 /// \return a MachineInstrBuilder for the newly created instruction.
1506 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1507 MachineMemOperand &MMO);
1508
1509 /// Build and insert `OldValRes<def> = G_ATOMICRMW_FMIN Addr, Val, MMO`.
1510 ///
1511 /// Atomically replace the value at \p Addr with the floating point minimum of
1512 /// \p Val and the original value. Puts the original value from \p Addr in \p
1513 /// OldValRes.
1514 ///
1515 /// \pre setBasicBlock or setMI must have been called.
1516 /// \pre \p OldValRes must be a generic virtual register.
1517 /// \pre \p Addr must be a generic virtual register with pointer type.
1518 /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1519 /// same type.
1520 ///
1521 /// \return a MachineInstrBuilder for the newly created instruction.
1523 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1524 MachineMemOperand &MMO);
1525
1526 /// Build and insert `G_FENCE Ordering, Scope`.
1527 MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope);
1528
1529 /// Build and insert \p Dst = G_FREEZE \p Src
1530 MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src) {
1531 return buildInstr(TargetOpcode::G_FREEZE, {Dst}, {Src});
1532 }
1533
1534 /// Build and insert \p Res = G_BLOCK_ADDR \p BA
1535 ///
1536 /// G_BLOCK_ADDR computes the address of a basic block.
1537 ///
1538 /// \pre setBasicBlock or setMI must have been called.
1539 /// \pre \p Res must be a generic virtual register of a pointer type.
1540 ///
1541 /// \return The newly created instruction.
1543
1544 /// Build and insert \p Res = G_ADD \p Op0, \p Op1
1545 ///
1546 /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1547 /// truncated to their width.
1548 ///
1549 /// \pre setBasicBlock or setMI must have been called.
1550 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1551 /// with the same (scalar or vector) type).
1552 ///
1553 /// \return a MachineInstrBuilder for the newly created instruction.
1554
1555 MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,
1556 const SrcOp &Src1,
1557 std::optional<unsigned> Flags = std::nullopt) {
1558 return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1559 }
1560
1561 /// Build and insert \p Res = G_SUB \p Op0, \p Op1
1562 ///
1563 /// G_SUB sets \p Res to the difference of integer parameters \p Op0 and
1564 /// \p Op1, truncated to their width.
1565 ///
1566 /// \pre setBasicBlock or setMI must have been called.
1567 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1568 /// with the same (scalar or vector) type).
1569 ///
1570 /// \return a MachineInstrBuilder for the newly created instruction.
1571
1572 MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0,
1573 const SrcOp &Src1,
1574 std::optional<unsigned> Flags = std::nullopt) {
1575 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1576 }
1577
1578 /// Build and insert \p Res = G_MUL \p Op0, \p Op1
1579 ///
1580 /// G_MUL sets \p Res to the product of integer parameters \p Op0 and \p Op1,
1581 /// truncated to their width.
1582 ///
1583 /// \pre setBasicBlock or setMI must have been called.
1584 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1585 /// with the same (scalar or vector) type).
1586 ///
1587 /// \return a MachineInstrBuilder for the newly created instruction.
1588 MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
1589 const SrcOp &Src1,
1590 std::optional<unsigned> Flags = std::nullopt) {
1591 return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1592 }
1593
1595 const SrcOp &Src1,
1596 std::optional<unsigned> Flags = std::nullopt) {
1597 return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags);
1598 }
1599
1601 const SrcOp &Src1,
1602 std::optional<unsigned> Flags = std::nullopt) {
1603 return buildInstr(TargetOpcode::G_SMULH, {Dst}, {Src0, Src1}, Flags);
1604 }
1605
1606 /// Build and insert \p Res = G_UREM \p Op0, \p Op1
1607 MachineInstrBuilder buildURem(const DstOp &Dst, const SrcOp &Src0,
1608 const SrcOp &Src1,
1609 std::optional<unsigned> Flags = std::nullopt) {
1610 return buildInstr(TargetOpcode::G_UREM, {Dst}, {Src0, Src1}, Flags);
1611 }
1612
1613 MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0,
1614 const SrcOp &Src1,
1615 std::optional<unsigned> Flags = std::nullopt) {
1616 return buildInstr(TargetOpcode::G_FMUL, {Dst}, {Src0, Src1}, Flags);
1617 }
1618
1620 buildFMinNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1621 std::optional<unsigned> Flags = std::nullopt) {
1622 return buildInstr(TargetOpcode::G_FMINNUM, {Dst}, {Src0, Src1}, Flags);
1623 }
1624
1626 buildFMaxNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1627 std::optional<unsigned> Flags = std::nullopt) {
1628 return buildInstr(TargetOpcode::G_FMAXNUM, {Dst}, {Src0, Src1}, Flags);
1629 }
1630
1632 buildFMinNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1633 std::optional<unsigned> Flags = std::nullopt) {
1634 return buildInstr(TargetOpcode::G_FMINNUM_IEEE, {Dst}, {Src0, Src1}, Flags);
1635 }
1636
1638 buildFMaxNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1639 std::optional<unsigned> Flags = std::nullopt) {
1640 return buildInstr(TargetOpcode::G_FMAXNUM_IEEE, {Dst}, {Src0, Src1}, Flags);
1641 }
1642
1643 MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0,
1644 const SrcOp &Src1,
1645 std::optional<unsigned> Flags = std::nullopt) {
1646 return buildInstr(TargetOpcode::G_SHL, {Dst}, {Src0, Src1}, Flags);
1647 }
1648
1649 MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0,
1650 const SrcOp &Src1,
1651 std::optional<unsigned> Flags = std::nullopt) {
1652 return buildInstr(TargetOpcode::G_LSHR, {Dst}, {Src0, Src1}, Flags);
1653 }
1654
1655 MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0,
1656 const SrcOp &Src1,
1657 std::optional<unsigned> Flags = std::nullopt) {
1658 return buildInstr(TargetOpcode::G_ASHR, {Dst}, {Src0, Src1}, Flags);
1659 }
1660
1661 /// Build and insert \p Res = G_AND \p Op0, \p Op1
1662 ///
1663 /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p
1664 /// Op1.
1665 ///
1666 /// \pre setBasicBlock or setMI must have been called.
1667 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1668 /// with the same (scalar or vector) type).
1669 ///
1670 /// \return a MachineInstrBuilder for the newly created instruction.
1671
1672 MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0,
1673 const SrcOp &Src1) {
1674 return buildInstr(TargetOpcode::G_AND, {Dst}, {Src0, Src1});
1675 }
1676
1677 /// Build and insert \p Res = G_OR \p Op0, \p Op1
1678 ///
1679 /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
1680 /// Op1.
1681 ///
1682 /// \pre setBasicBlock or setMI must have been called.
1683 /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1684 /// with the same (scalar or vector) type).
1685 ///
1686 /// \return a MachineInstrBuilder for the newly created instruction.
1687 MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0,
1688 const SrcOp &Src1,
1689 std::optional<unsigned> Flags = std::nullopt) {
1690 return buildInstr(TargetOpcode::G_OR, {Dst}, {Src0, Src1}, Flags);
1691 }
1692
1693 /// Build and insert \p Res = G_XOR \p Op0, \p Op1
1694 MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0,
1695 const SrcOp &Src1) {
1696 return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, Src1});
1697 }
1698
1699 /// Build and insert a bitwise not,
1700 /// \p NegOne = G_CONSTANT -1
1701 /// \p Res = G_OR \p Op0, NegOne
1702 MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) {
1703 auto NegOne = buildConstant(Dst.getLLTTy(*getMRI()), -1);
1704 return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, NegOne});
1705 }
1706
1707 /// Build and insert integer negation
1708 /// \p Zero = G_CONSTANT 0
1709 /// \p Res = G_SUB Zero, \p Op0
1710 MachineInstrBuilder buildNeg(const DstOp &Dst, const SrcOp &Src0) {
1711 auto Zero = buildConstant(Dst.getLLTTy(*getMRI()), 0);
1712 return buildInstr(TargetOpcode::G_SUB, {Dst}, {Zero, Src0});
1713 }
1714
1715 /// Build and insert \p Res = G_CTPOP \p Op0, \p Src0
1716 MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0) {
1717 return buildInstr(TargetOpcode::G_CTPOP, {Dst}, {Src0});
1718 }
1719
1720 /// Build and insert \p Res = G_CTLZ \p Op0, \p Src0
1721 MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0) {
1722 return buildInstr(TargetOpcode::G_CTLZ, {Dst}, {Src0});
1723 }
1724
1725 /// Build and insert \p Res = G_CTLZ_ZERO_UNDEF \p Op0, \p Src0
1727 return buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {Dst}, {Src0});
1728 }
1729
1730 /// Build and insert \p Res = G_CTTZ \p Op0, \p Src0
1731 MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0) {
1732 return buildInstr(TargetOpcode::G_CTTZ, {Dst}, {Src0});
1733 }
1734
1735 /// Build and insert \p Res = G_CTTZ_ZERO_UNDEF \p Op0, \p Src0
1737 return buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, {Dst}, {Src0});
1738 }
1739
1740 /// Build and insert \p Dst = G_BSWAP \p Src0
1741 MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0) {
1742 return buildInstr(TargetOpcode::G_BSWAP, {Dst}, {Src0});
1743 }
1744
1745 /// Build and insert \p Res = G_FADD \p Op0, \p Op1
1746 MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0,
1747 const SrcOp &Src1,
1748 std::optional<unsigned> Flags = std::nullopt) {
1749 return buildInstr(TargetOpcode::G_FADD, {Dst}, {Src0, Src1}, Flags);
1750 }
1751
1752 /// Build and insert \p Res = G_STRICT_FADD \p Op0, \p Op1
1754 buildStrictFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1755 std::optional<unsigned> Flags = std::nullopt) {
1756 return buildInstr(TargetOpcode::G_STRICT_FADD, {Dst}, {Src0, Src1}, Flags);
1757 }
1758
1759 /// Build and insert \p Res = G_FSUB \p Op0, \p Op1
1760 MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0,
1761 const SrcOp &Src1,
1762 std::optional<unsigned> Flags = std::nullopt) {
1763 return buildInstr(TargetOpcode::G_FSUB, {Dst}, {Src0, Src1}, Flags);
1764 }
1765
1766 /// Build and insert \p Res = G_FDIV \p Op0, \p Op1
1767 MachineInstrBuilder buildFDiv(const DstOp &Dst, const SrcOp &Src0,
1768 const SrcOp &Src1,
1769 std::optional<unsigned> Flags = std::nullopt) {
1770 return buildInstr(TargetOpcode::G_FDIV, {Dst}, {Src0, Src1}, Flags);
1771 }
1772
1773 /// Build and insert \p Res = G_FMA \p Op0, \p Op1, \p Op2
1774 MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0,
1775 const SrcOp &Src1, const SrcOp &Src2,
1776 std::optional<unsigned> Flags = std::nullopt) {
1777 return buildInstr(TargetOpcode::G_FMA, {Dst}, {Src0, Src1, Src2}, Flags);
1778 }
1779
1780 /// Build and insert \p Res = G_FMAD \p Op0, \p Op1, \p Op2
1781 MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0,
1782 const SrcOp &Src1, const SrcOp &Src2,
1783 std::optional<unsigned> Flags = std::nullopt) {
1784 return buildInstr(TargetOpcode::G_FMAD, {Dst}, {Src0, Src1, Src2}, Flags);
1785 }
1786
1787 /// Build and insert \p Res = G_FNEG \p Op0
1788 MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0,
1789 std::optional<unsigned> Flags = std::nullopt) {
1790 return buildInstr(TargetOpcode::G_FNEG, {Dst}, {Src0}, Flags);
1791 }
1792
1793 /// Build and insert \p Res = G_FABS \p Op0
1794 MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0,
1795 std::optional<unsigned> Flags = std::nullopt) {
1796 return buildInstr(TargetOpcode::G_FABS, {Dst}, {Src0}, Flags);
1797 }
1798
1799 /// Build and insert \p Dst = G_FCANONICALIZE \p Src0
1801 buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0,
1802 std::optional<unsigned> Flags = std::nullopt) {
1803 return buildInstr(TargetOpcode::G_FCANONICALIZE, {Dst}, {Src0}, Flags);
1804 }
1805
1806 /// Build and insert \p Dst = G_INTRINSIC_TRUNC \p Src0
1808 buildIntrinsicTrunc(const DstOp &Dst, const SrcOp &Src0,
1809 std::optional<unsigned> Flags = std::nullopt) {
1810 return buildInstr(TargetOpcode::G_INTRINSIC_TRUNC, {Dst}, {Src0}, Flags);
1811 }
1812
1813 /// Build and insert \p Res = GFFLOOR \p Op0, \p Op1
1815 buildFFloor(const DstOp &Dst, const SrcOp &Src0,
1816 std::optional<unsigned> Flags = std::nullopt) {
1817 return buildInstr(TargetOpcode::G_FFLOOR, {Dst}, {Src0}, Flags);
1818 }
1819
1820 /// Build and insert \p Dst = G_FLOG \p Src
1822 std::optional<unsigned> Flags = std::nullopt) {
1823 return buildInstr(TargetOpcode::G_FLOG, {Dst}, {Src}, Flags);
1824 }
1825
1826 /// Build and insert \p Dst = G_FLOG2 \p Src
1828 std::optional<unsigned> Flags = std::nullopt) {
1829 return buildInstr(TargetOpcode::G_FLOG2, {Dst}, {Src}, Flags);
1830 }
1831
1832 /// Build and insert \p Dst = G_FEXP2 \p Src
1834 std::optional<unsigned> Flags = std::nullopt) {
1835 return buildInstr(TargetOpcode::G_FEXP2, {Dst}, {Src}, Flags);
1836 }
1837
1838 /// Build and insert \p Dst = G_FPOW \p Src0, \p Src1
1839 MachineInstrBuilder buildFPow(const DstOp &Dst, const SrcOp &Src0,
1840 const SrcOp &Src1,
1841 std::optional<unsigned> Flags = std::nullopt) {
1842 return buildInstr(TargetOpcode::G_FPOW, {Dst}, {Src0, Src1}, Flags);
1843 }
1844
1845 /// Build and insert \p Dst = G_FLDEXP \p Src0, \p Src1
1847 buildFLdexp(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1,
1848 std::optional<unsigned> Flags = std::nullopt) {
1849 return buildInstr(TargetOpcode::G_FLDEXP, {Dst}, {Src0, Src1}, Flags);
1850 }
1851
1852 /// Build and insert \p Fract, \p Exp = G_FFREXP \p Src
1854 buildFFrexp(const DstOp &Fract, const DstOp &Exp, const SrcOp &Src,
1855 std::optional<unsigned> Flags = std::nullopt) {
1856 return buildInstr(TargetOpcode::G_FFREXP, {Fract, Exp}, {Src}, Flags);
1857 }
1858
1859 /// Build and insert \p Res = G_FCOPYSIGN \p Op0, \p Op1
1861 const SrcOp &Src1) {
1862 return buildInstr(TargetOpcode::G_FCOPYSIGN, {Dst}, {Src0, Src1});
1863 }
1864
1865 /// Build and insert \p Res = G_UITOFP \p Src0
1866 MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0) {
1867 return buildInstr(TargetOpcode::G_UITOFP, {Dst}, {Src0});
1868 }
1869
1870 /// Build and insert \p Res = G_SITOFP \p Src0
1871 MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0) {
1872 return buildInstr(TargetOpcode::G_SITOFP, {Dst}, {Src0});
1873 }
1874
1875 /// Build and insert \p Res = G_FPTOUI \p Src0
1876 MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0) {
1877 return buildInstr(TargetOpcode::G_FPTOUI, {Dst}, {Src0});
1878 }
1879
1880 /// Build and insert \p Res = G_FPTOSI \p Src0
1881 MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0) {
1882 return buildInstr(TargetOpcode::G_FPTOSI, {Dst}, {Src0});
1883 }
1884
1885 /// Build and insert \p Dst = G_FRINT \p Src0, \p Src1
1887 std::optional<unsigned> Flags = std::nullopt) {
1888 return buildInstr(TargetOpcode::G_FRINT, {Dst}, {Src0}, Flags);
1889 }
1890
1891 /// Build and insert \p Res = G_SMIN \p Op0, \p Op1
1892 MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0,
1893 const SrcOp &Src1) {
1894 return buildInstr(TargetOpcode::G_SMIN, {Dst}, {Src0, Src1});
1895 }
1896
1897 /// Build and insert \p Res = G_SMAX \p Op0, \p Op1
1898 MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0,
1899 const SrcOp &Src1) {
1900 return buildInstr(TargetOpcode::G_SMAX, {Dst}, {Src0, Src1});
1901 }
1902
1903 /// Build and insert \p Res = G_UMIN \p Op0, \p Op1
1904 MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0,
1905 const SrcOp &Src1) {
1906 return buildInstr(TargetOpcode::G_UMIN, {Dst}, {Src0, Src1});
1907 }
1908
1909 /// Build and insert \p Res = G_UMAX \p Op0, \p Op1
1910 MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0,
1911 const SrcOp &Src1) {
1912 return buildInstr(TargetOpcode::G_UMAX, {Dst}, {Src0, Src1});
1913 }
1914
1915 /// Build and insert \p Dst = G_ABS \p Src
1916 MachineInstrBuilder buildAbs(const DstOp &Dst, const SrcOp &Src) {
1917 return buildInstr(TargetOpcode::G_ABS, {Dst}, {Src});
1918 }
1919
1920 /// Build and insert \p Res = G_JUMP_TABLE \p JTI
1921 ///
1922 /// G_JUMP_TABLE sets \p Res to the address of the jump table specified by
1923 /// the jump table index \p JTI.
1924 ///
1925 /// \return a MachineInstrBuilder for the newly created instruction.
1926 MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI);
1927
1928 /// Build and insert \p Res = G_VECREDUCE_SEQ_FADD \p ScalarIn, \p VecIn
1929 ///
1930 /// \p ScalarIn is the scalar accumulator input to start the sequential
1931 /// reduction operation of \p VecIn.
1933 const SrcOp &ScalarIn,
1934 const SrcOp &VecIn) {
1935 return buildInstr(TargetOpcode::G_VECREDUCE_SEQ_FADD, {Dst},
1936 {ScalarIn, {VecIn}});
1937 }
1938
1939 /// Build and insert \p Res = G_VECREDUCE_SEQ_FMUL \p ScalarIn, \p VecIn
1940 ///
1941 /// \p ScalarIn is the scalar accumulator input to start the sequential
1942 /// reduction operation of \p VecIn.
1944 const SrcOp &ScalarIn,
1945 const SrcOp &VecIn) {
1946 return buildInstr(TargetOpcode::G_VECREDUCE_SEQ_FMUL, {Dst},
1947 {ScalarIn, {VecIn}});
1948 }
1949
1950 /// Build and insert \p Res = G_VECREDUCE_FADD \p Src
1951 ///
1952 /// \p ScalarIn is the scalar accumulator input to the reduction operation of
1953 /// \p VecIn.
1955 const SrcOp &ScalarIn,
1956 const SrcOp &VecIn) {
1957 return buildInstr(TargetOpcode::G_VECREDUCE_FADD, {Dst}, {ScalarIn, VecIn});
1958 }
1959
1960 /// Build and insert \p Res = G_VECREDUCE_FMUL \p Src
1961 ///
1962 /// \p ScalarIn is the scalar accumulator input to the reduction operation of
1963 /// \p VecIn.
1965 const SrcOp &ScalarIn,
1966 const SrcOp &VecIn) {
1967 return buildInstr(TargetOpcode::G_VECREDUCE_FMUL, {Dst}, {ScalarIn, VecIn});
1968 }
1969
1970 /// Build and insert \p Res = G_VECREDUCE_FMAX \p Src
1972 return buildInstr(TargetOpcode::G_VECREDUCE_FMAX, {Dst}, {Src});
1973 }
1974
1975 /// Build and insert \p Res = G_VECREDUCE_FMIN \p Src
1977 return buildInstr(TargetOpcode::G_VECREDUCE_FMIN, {Dst}, {Src});
1978 }
1979
1980 /// Build and insert \p Res = G_VECREDUCE_FMAXIMUM \p Src
1982 const SrcOp &Src) {
1983 return buildInstr(TargetOpcode::G_VECREDUCE_FMAXIMUM, {Dst}, {Src});
1984 }
1985
1986 /// Build and insert \p Res = G_VECREDUCE_FMINIMUM \p Src
1988 const SrcOp &Src) {
1989 return buildInstr(TargetOpcode::G_VECREDUCE_FMINIMUM, {Dst}, {Src});
1990 }
1991
1992 /// Build and insert \p Res = G_VECREDUCE_ADD \p Src
1994 return buildInstr(TargetOpcode::G_VECREDUCE_ADD, {Dst}, {Src});
1995 }
1996
1997 /// Build and insert \p Res = G_VECREDUCE_MUL \p Src
1999 return buildInstr(TargetOpcode::G_VECREDUCE_MUL, {Dst}, {Src});
2000 }
2001
2002 /// Build and insert \p Res = G_VECREDUCE_AND \p Src
2004 return buildInstr(TargetOpcode::G_VECREDUCE_AND, {Dst}, {Src});
2005 }
2006
2007 /// Build and insert \p Res = G_VECREDUCE_OR \p Src
2009 return buildInstr(TargetOpcode::G_VECREDUCE_OR, {Dst}, {Src});
2010 }
2011
2012 /// Build and insert \p Res = G_VECREDUCE_XOR \p Src
2014 return buildInstr(TargetOpcode::G_VECREDUCE_XOR, {Dst}, {Src});
2015 }
2016
2017 /// Build and insert \p Res = G_VECREDUCE_SMAX \p Src
2019 return buildInstr(TargetOpcode::G_VECREDUCE_SMAX, {Dst}, {Src});
2020 }
2021
2022 /// Build and insert \p Res = G_VECREDUCE_SMIN \p Src
2024 return buildInstr(TargetOpcode::G_VECREDUCE_SMIN, {Dst}, {Src});
2025 }
2026
2027 /// Build and insert \p Res = G_VECREDUCE_UMAX \p Src
2029 return buildInstr(TargetOpcode::G_VECREDUCE_UMAX, {Dst}, {Src});
2030 }
2031
2032 /// Build and insert \p Res = G_VECREDUCE_UMIN \p Src
2034 return buildInstr(TargetOpcode::G_VECREDUCE_UMIN, {Dst}, {Src});
2035 }
2036
2037 /// Build and insert G_MEMCPY or G_MEMMOVE
2038 MachineInstrBuilder buildMemTransferInst(unsigned Opcode, const SrcOp &DstPtr,
2039 const SrcOp &SrcPtr,
2040 const SrcOp &Size,
2041 MachineMemOperand &DstMMO,
2042 MachineMemOperand &SrcMMO) {
2043 auto MIB = buildInstr(
2044 Opcode, {}, {DstPtr, SrcPtr, Size, SrcOp(INT64_C(0) /*isTailCall*/)});
2045 MIB.addMemOperand(&DstMMO);
2046 MIB.addMemOperand(&SrcMMO);
2047 return MIB;
2048 }
2049
2050 MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr,
2051 const SrcOp &Size, MachineMemOperand &DstMMO,
2052 MachineMemOperand &SrcMMO) {
2053 return buildMemTransferInst(TargetOpcode::G_MEMCPY, DstPtr, SrcPtr, Size,
2054 DstMMO, SrcMMO);
2055 }
2056
2057 /// Build and insert \p Dst = G_SBFX \p Src, \p LSB, \p Width.
2059 const SrcOp &LSB, const SrcOp &Width) {
2060 return buildInstr(TargetOpcode::G_SBFX, {Dst}, {Src, LSB, Width});
2061 }
2062
2063 /// Build and insert \p Dst = G_UBFX \p Src, \p LSB, \p Width.
2065 const SrcOp &LSB, const SrcOp &Width) {
2066 return buildInstr(TargetOpcode::G_UBFX, {Dst}, {Src, LSB, Width});
2067 }
2068
2069 /// Build and insert \p Dst = G_ROTR \p Src, \p Amt
2071 const SrcOp &Amt) {
2072 return buildInstr(TargetOpcode::G_ROTR, {Dst}, {Src, Amt});
2073 }
2074
2075 /// Build and insert \p Dst = G_ROTL \p Src, \p Amt
2077 const SrcOp &Amt) {
2078 return buildInstr(TargetOpcode::G_ROTL, {Dst}, {Src, Amt});
2079 }
2080
2081 /// Build and insert \p Dst = G_BITREVERSE \p Src
2083 return buildInstr(TargetOpcode::G_BITREVERSE, {Dst}, {Src});
2084 }
2085
2086 virtual MachineInstrBuilder
2087 buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps, ArrayRef<SrcOp> SrcOps,
2088 std::optional<unsigned> Flags = std::nullopt);
2089};
2090
2091} // End namespace llvm.
2092#endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static const Function * getParent(const Value *V)
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
uint64_t Addr
uint64_t Size
This contains common code to allow clients to notify changes to machine instr.
IRTranslator LLVM IR MI
unsigned Reg
Module.h This file contains the declarations for the Module class.
#define P(N)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Class for arbitrary precision integers.
Definition: APInt.h:76
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
The address of a basic block.
Definition: Constants.h:874
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:711
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:260
This is the shared class of boolean and integer constants.
Definition: Constants.h:78
This is an important base class in LLVM.
Definition: Constant.h:41
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
A debug info location.
Definition: DebugLoc.h:33
DstOp(const LLT T)
DstOp(unsigned R)
DstOp(Register R)
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
LLT getLLTTy(const MachineRegisterInfo &MRI) const
DstOp(const MachineOperand &Op)
DstType getDstOpKind() const
const TargetRegisterClass * RC
const TargetRegisterClass * getRegClass() const
DstOp(const TargetRegisterClass *TRC)
Register getReg() const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:320
The CSE Analysis object.
Definition: CSEInfo.h:69
Abstract class that contains various methods for clients to notify about changes.
virtual void createdInstr(MachineInstr &MI)=0
An instruction has been created and inserted into the function.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:652
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelType.h:42
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
Metadata node.
Definition: Metadata.h:950
Function & getFunction()
Return the LLVM function that this machine code represents.
Helper class to build MachineInstr.
MachineInstrBuilder buildLoadFromOffset(const DstOp &Dst, const SrcOp &BasePtr, MachineMemOperand &BaseMMO, int64_t Offset)
Helper to create a load from a constant offset given a base address.
MachineInstrBuilder buildAtomicRMWFMin(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FMIN Addr, Val, MMO.
MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FSUB Op0, Op1.
MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOSI Src0.
GISelChangeObserver * getObserver()
MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildBoolExtInReg(const DstOp &Res, const SrcOp &Op, bool IsVector, bool IsFP)
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
MachineInstrBuilder buildFLdexp(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FLDEXP Src0, Src1.
MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_FREEZE Src.
MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO.
MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
MachineInstrBuilder buildBr(MachineBasicBlock &Dest)
Build and insert G_BR Dest.
void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II)
Set the insertion point before the specified position.
const MachineFunction & getMF() const
std::optional< MachineInstrBuilder > materializePtrAdd(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value)
Materialize and insert Res = G_PTR_ADD Op0, (G_CONSTANT Value)
LLVMContext & getContext() const
MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_ADD Op0, Op1.
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
MachineInstrBuilder buildFPExt(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FPEXT Op.
MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0)
Build and insert a bitwise not, NegOne = G_CONSTANT -1 Res = G_OR Op0, NegOne.
MachineInstrBuilder buildVecReduceSeqFAdd(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_SEQ_FADD ScalarIn, VecIn.
MachineInstrBuilder buildRotateRight(const DstOp &Dst, const SrcOp &Src, const SrcOp &Amt)
Build and insert Dst = G_ROTR Src, Amt.
MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ Op0, Src0.
virtual ~MachineIRBuilder()=default
MachineInstrBuilder buildVecReduceOr(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_OR Src.
MachineInstrBuilder buildFLog2(const DstOp &Dst, const SrcOp &Src, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FLOG2 Src.
MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildConstantPool(const DstOp &Res, unsigned Idx)
Build and insert Res = G_CONSTANT_POOL Idx.
MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI)
Build and insert Res = G_JUMP_TABLE JTI.
MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op, bool IsFP)
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ... = G_UNMERGE_VALUES Op.
MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FABS Op0.
MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope)
Build and insert G_FENCE Ordering, Scope.
MachineInstrBuilder buildFMinNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FMA Op0, Op1, Op2.
MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO.
MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and inserts Res = G_AND Op, LowBitsSet(ImmOp) Since there is no G_ZEXT_INREG like G_SEXT_INREG,...
MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
GISelCSEInfo * getCSEInfo()
MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO.
MachineInstrBuilder buildVecReduceFMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_FMAX Src.
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert Res0, ... = G_EXTRACT Src, Idx0.
MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_MUL Op0, Op1.
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src)
Build and insert an appropriate cast between two registers of equal size.
const TargetInstrInfo & getTII()
MachineInstrBuilder buildAtomicRMWFAdd(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO.
MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_SADDE Op0, Op1, CarryInp.
MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO.
MachineInstrBuilder buildURem(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_UREM Op0, Op1.
MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_SADDO Op0, Op1.
MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOUI Src0.
MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildFPow(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FPOW Src0, Src1.
MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Res = COPY Op depending on the differing sizes of Res and Op.
MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op.
MachineInstrBuilder buildIntrinsicTrunc(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_INTRINSIC_TRUNC Src0.
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src)
Build and insert a vector splat of a scalar Src using a G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idio...
MachineInstrBuilder buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr,...
MachineInstrBuilder buildConcatVectors(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_CONCAT_VECTORS Op0, ...
MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.
MachineInstrBuilder buildVecReduceSeqFMul(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_SEQ_FMUL ScalarIn, VecIn.
MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_SUB Op0, Op1.
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects, bool isConvergent)
Build and insert a G_INTRINSIC instruction.
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
MDNode * getPCSections()
Get the current instruction's PC sections metadata.
MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0)
Build and insert Dst = G_BSWAP Src0.
MachineInstrBuilder buildVecReduceFMul(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_FMUL Src.
MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ_ZERO_UNDEF Op0, Src0.
MachineInstrBuilder buildAddrSpaceCast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_ADDRSPACE_CAST Src.
MachineInstrBuilder buildFExp2(const DstOp &Dst, const SrcOp &Src, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FEXP2 Src.
MachineInstrBuilder buildIntToPtr(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_INTTOPTR instruction.
MachineInstrBuilder buildIndirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...
unsigned getBoolExtOp(bool IsVec, bool IsFP) const
MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_USUBO Op0, Op1.
MachineInstrBuilder buildVecReduceFAdd(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_FADD Src.
MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO.
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
MachineIRBuilder(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt)
MachineInstrBuilder buildVecReduceFMinimum(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_FMINIMUM Src.
MachineInstrBuilder buildNeg(const DstOp &Dst, const SrcOp &Src0)
Build and insert integer negation Zero = G_CONSTANT 0 Res = G_SUB Zero, Op0.
MachineInstrBuilder buildVecReduceSMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_SMIN Src.
MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ Op0, Src0.
MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMAX Op0, Op1.
MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...
MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_ZEXT Op, Size.
void recordInsertion(MachineInstr *InsertedInstr) const
MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildStrictFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_STRICT_FADD Op0, Op1.
MachineInstrBuilder buildBrCond(const SrcOp &Tst, MachineBasicBlock &Dest)
Build and insert G_BRCOND Tst, Dest.
MachineInstrBuilder buildVecReduceXor(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_XOR Src.
MachineInstrBuilder buildVecReduceFMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_FMIN Src.
MachineInstrBuilder buildFDiv(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FDIV Op0, Op1.
MachineInstrBuilder buildMergeLikeInstr(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ... or Res = G_BUILD_VECTOR Op0, ... or Res = G_CONCAT_VEC...
const GISelCSEInfo * getCSEInfo() const
MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_PTR_ADD Op0, Op1.
MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR_TRUNC Op0, ...
MachineBasicBlock & getMBB()
MachineIRBuilder(MachineInstr &MI)
MachineInstrBuilder buildExtractVectorElementConstant(const DstOp &Res, const SrcOp &Val, const int Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ_ZERO_UNDEF Op0, Src0.
virtual MachineInstrBuilder buildFConstant(const DstOp &Res, const ConstantFP &Val)
Build and insert Res = G_FCONSTANT Val.
MachineInstrBuilder buildBitReverse(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITREVERSE Src.
MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_UITOFP Src0.
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
MachineInstrBuilder buildAtomicCmpXchg(Register OldValRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_SITOFP Src0.
MachineIRBuilder(MachineInstr &MI, GISelChangeObserver &Observer)
MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FMAD Op0, Op1, Op2.
MachineInstrBuilder buildPadVectorWithUndefElements(const DstOp &Res, const SrcOp &Op0)
Build and insert a, b, ..., x = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a, b, .....
MachineInstrBuilder buildFLog(const DstOp &Dst, const SrcOp &Src, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FLOG Src.
void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty, const LLT Op1Ty)
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
MachineInstrBuilder buildVecReduceUMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_UMAX Src.
MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...
const DebugLoc & getDL()
Getter for DebugLoc.
MachineInstrBuilder buildUbfx(const DstOp &Dst, const SrcOp &Src, const SrcOp &LSB, const SrcOp &Width)
Build and insert Dst = G_UBFX Src, LSB, Width.
const MachineRegisterInfo * getMRI() const
MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTPOP Op0, Src0.
MachineInstrBuilder buildAbs(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_ABS Src.
MachineInstrBuilder buildBuildVectorConstant(const DstOp &Res, ArrayRef< APInt > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ... where each OpN is built with G_CONSTANT.
MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO.
void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1)
MachineInstrBuilder buildVecReduceAnd(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_AND Src.
MachineInstrBuilder buildVecReduceFMaximum(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_FMAXIMUM Src.
void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1)
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
MachineFunction & getMF()
Getter for the function we currently build.
MachineIRBuilder(MachineFunction &MF)
MachineIRBuilder(const MachineIRBuilderState &BState)
MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr, const SrcOp &Size, MachineMemOperand &DstMMO, MachineMemOperand &SrcMMO)
MachineInstrBuilder buildAssertAlign(const DstOp &Res, const SrcOp &Op, Align AlignVal)
Build and insert Res = G_ASSERT_ALIGN Op, AlignVal.
MachineInstrBuilder buildFRint(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FRINT Src0, Src1.
MachineInstrBuilder buildSbfx(const DstOp &Dst, const SrcOp &Src, const SrcOp &LSB, const SrcOp &Width)
Build and insert Dst = G_SBFX Src, LSB, Width.
MachineInstrBuilder buildFMaxNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMIN Op0, Op1.
MachineInstrBuilder buildFMinNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildDbgLabel(const MDNode *Label)
Build and insert a DBG_LABEL instructions specifying that Label is given.
MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI, Register IndexReg)
Build and insert G_BRJT TablePtr, JTI, IndexReg.
MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src, const SrcOp &Op, unsigned Index)
MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size, Align Alignment)
Build and insert Res = G_DYN_STACKALLOC Size, Align.
MachineInstrBuilder buildVecReduceUMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_UMIN Src.
MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in th...
void setInstrAndDebugLoc(MachineInstr &MI)
Set the insertion point to before MI, and set the debug loc to MI's loc.
MachineInstrBuilder buildSSube(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_SSUBE Op0, Op1, CarryInp.
void setPCSections(MDNode *MD)
Set the PC sections metadata to MD for all the next build instructions.
MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, const SrcOp &Op)
Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of...
MachineInstrBuilder buildVecReduceAdd(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_ADD Src.
MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO.
MachineInstrBuilder buildIsFPClass(const DstOp &Res, const SrcOp &Src, unsigned Mask)
Build and insert a Res = G_IS_FPCLASS Pred, Src, Mask.
MachineInstrBuilder buildMergeValues(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_UADDE Op0, Op1, CarryIn.
MachineInstrBuilder buildAtomicRMWFMax(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FMAX Addr, Val, MMO.
void setDebugLoc(const DebugLoc &DL)
Set the debug location to DL for all the next build instructions.
MachineInstrBuilder buildFCopysign(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_FCOPYSIGN Op0, Op1.
MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Src)
Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.
MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_SUBO Op0, Op1.
MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO.
bool isObservingChanges() const
MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_USUBE Op0, Op1, CarryInp.
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FNEG Op0.
MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITCAST Src.
const DebugLoc & getDebugLoc()
Get the current instruction's debug location.
MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_UADDO Op0, Op1.
void setCSEInfo(GISelCSEInfo *Info)
MachineInstrBuilder buildFMaxNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
MachineInstrBuilder buildFFloor(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = GFFLOOR Op0, Op1.
MachineInstrBuilder buildFFrexp(const DstOp &Fract, const DstOp &Exp, const SrcOp &Src, std::optional< unsigned > Flags=std::nullopt)
Build and insert Fract, Exp = G_FFREXP Src.
MachineIRBuilder()=default
Some constructors for easy use.
MachineInstrBuilder buildDeleteTrailingVectorElements(const DstOp &Res, const SrcOp &Op0)
Build and insert a, b, ..., x, y, z = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a,...
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO.
MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FPTRUNC Op.
MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_OR Op0, Op1.
MachineIRBuilderState & getState()
Getter for the State.
MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1, const SrcOp &Src2, ArrayRef< int > Mask)
Build and insert Res = G_SHUFFLE_VECTOR Src1, Src2, Mask.
MachineInstrBuilder buildAssertInstr(unsigned Opc, const DstOp &Res, const SrcOp &Op, unsigned Val)
Build and insert G_ASSERT_SEXT, G_ASSERT_ZEXT, or G_ASSERT_ALIGN.
void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend)
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTRMASK Op0, Op1.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
MachineInstrBuilder buildVecReduceSMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_SMAX Src.
MachineInstrBuilder buildMemTransferInst(unsigned Opcode, const SrcOp &DstPtr, const SrcOp &SrcPtr, const SrcOp &Size, MachineMemOperand &DstMMO, MachineMemOperand &SrcMMO)
Build and insert G_MEMCPY or G_MEMMOVE.
void validateUnaryOp(const LLT Res, const LLT Op0)
MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA)
Build and insert Res = G_BLOCK_ADDR BA.
MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO.
const DataLayout & getDataLayout() const
MachineInstrBuilder buildBrIndirect(Register Tgt)
Build and insert G_BRINDIRECT Tgt.
MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = <opcode> Addr, MMO.
void setMF(MachineFunction &MF)
MachineInstrBuilder buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO.
MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_SEXT Op, Size.
MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_XOR Op0, Op1.
MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO.
void setChangeObserver(GISelChangeObserver &Observer)
MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0, uint32_t NumBits)
Build and insert Res = G_PTRMASK Op0, G_CONSTANT (1 << NumBits) - 1.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
MachineInstrBuilder buildVecReduceMul(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_MUL Src.
MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMIN Op0, Op1.
MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMAX Op0, Op1.
MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert a Res = G_FCMP PredOp0, Op1.
MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_FADD Op0, Op1.
MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_PTRTOINT instruction.
MachineInstrBuilder buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0, std::optional< unsigned > Flags=std::nullopt)
Build and insert Dst = G_FCANONICALIZE Src0.
MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and insert Res = G_SEXT_INREG Op, ImmOp.
MachineInstrBuilder buildRotateLeft(const DstOp &Dst, const SrcOp &Src, const SrcOp &Amt)
Build and insert Dst = G_ROTL Src, Amt.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addPredicate(CmpInst::Predicate Pred) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
Definition: MachineInstr.h:68
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:553
A description of a memory reference used in the backend.
Flags
Flags values. These may be or'd together.
MachineOperand class - Representation of each machine instruction operand.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const DataLayout & getDataLayout() const
Get the data layout for the module's target platform.
Definition: Module.h:254
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
SrcOp(const MachineInstrBuilder &MIB)
SrcOp(int64_t V)
SrcOp(const CmpInst::Predicate P)
SrcOp(uint64_t V)
SrcOp(int)=delete
MachineInstrBuilder SrcMIB
CmpInst::Predicate getPredicate() const
SrcType getSrcOpKind() const
CmpInst::Predicate Pred
int64_t getImm() const
LLT getLLTTy(const MachineRegisterInfo &MRI) const
SrcOp(const MachineOperand &Op)
void addSrcToMIB(MachineInstrBuilder &MIB) const
SrcOp(unsigned)=delete
Use of registers held in unsigned integer variables (or more rarely signed integers) is no longer per...
Register getReg() const
SrcOp(Register R)
TargetInstrInfo - Interface to description of machine instruction set.
LLVM Value Representation.
Definition: Value.h:74
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ ConstantFP
Definition: ISDOpcodes.h:77
@ BlockAddress
Definition: ISDOpcodes.h:84
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:440
DWARFExpression::Operation Op
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:651
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
Class which stores all the state required in a MachineIRBuilder.
MachineFunction * MF
MachineFunction under construction.
DebugLoc DL
Debug location to be set to any instruction we create.
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
MDNode * PCSections
PC sections metadata to be set to any instruction we create.
MachineBasicBlock::iterator II
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.
GISelChangeObserver * Observer
This class contains a discriminated union of information about pointers in memory operands,...