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MachineIRBuilder.h
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1 //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.h - MIBuilder --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the MachineIRBuilder class.
10 /// This is a helper class to build MachineInstr.
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
14 #define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
15 
22 #include "llvm/IR/Constants.h"
23 #include "llvm/IR/DebugLoc.h"
24 #include "llvm/IR/Module.h"
25 
26 namespace llvm {
27 
28 // Forward declarations.
29 class MachineFunction;
30 class MachineInstr;
31 class TargetInstrInfo;
32 class GISelChangeObserver;
33 
34 /// Class which stores all the state required in a MachineIRBuilder.
35 /// Since MachineIRBuilders will only store state in this object, it allows
36 /// to transfer BuilderState between different kinds of MachineIRBuilders.
38  /// MachineFunction under construction.
39  MachineFunction *MF = nullptr;
40  /// Information used to access the description of the opcodes.
41  const TargetInstrInfo *TII = nullptr;
42  /// Information used to verify types are consistent and to create virtual registers.
44  /// Debug location to be set to any instruction we create.
46 
47  /// \name Fields describing the insertion point.
48  /// @{
49  MachineBasicBlock *MBB = nullptr;
51  /// @}
52 
54 
55  GISelCSEInfo *CSEInfo = nullptr;
56 };
57 
58 class DstOp {
59  union {
63  };
64 
65 public:
66  enum class DstType { Ty_LLT, Ty_Reg, Ty_RC };
67  DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {}
68  DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {}
69  DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {}
70  DstOp(const LLT T) : LLTTy(T), Ty(DstType::Ty_LLT) {}
71  DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {}
72 
74  switch (Ty) {
75  case DstType::Ty_Reg:
76  MIB.addDef(Reg);
77  break;
78  case DstType::Ty_LLT:
79  MIB.addDef(MRI.createGenericVirtualRegister(LLTTy));
80  break;
81  case DstType::Ty_RC:
82  MIB.addDef(MRI.createVirtualRegister(RC));
83  break;
84  }
85  }
86 
88  switch (Ty) {
89  case DstType::Ty_RC:
90  return LLT{};
91  case DstType::Ty_LLT:
92  return LLTTy;
93  case DstType::Ty_Reg:
94  return MRI.getType(Reg);
95  }
96  llvm_unreachable("Unrecognised DstOp::DstType enum");
97  }
98 
99  Register getReg() const {
100  assert(Ty == DstType::Ty_Reg && "Not a register");
101  return Reg;
102  }
103 
105  switch (Ty) {
106  case DstType::Ty_RC:
107  return RC;
108  default:
109  llvm_unreachable("Not a RC Operand");
110  }
111  }
112 
113  DstType getDstOpKind() const { return Ty; }
114 
115 private:
116  DstType Ty;
117 };
118 
119 class SrcOp {
120  union {
124  int64_t Imm;
125  };
126 
127 public:
129  SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {}
130  SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {}
131  SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {}
132  SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {}
133  /// Use of registers held in unsigned integer variables (or more rarely signed
134  /// integers) is no longer permitted to avoid ambiguity with upcoming support
135  /// for immediates.
136  SrcOp(unsigned) = delete;
137  SrcOp(int) = delete;
138  SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
139  SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
140 
141  void addSrcToMIB(MachineInstrBuilder &MIB) const {
142  switch (Ty) {
144  MIB.addPredicate(Pred);
145  break;
146  case SrcType::Ty_Reg:
147  MIB.addUse(Reg);
148  break;
149  case SrcType::Ty_MIB:
150  MIB.addUse(SrcMIB->getOperand(0).getReg());
151  break;
152  case SrcType::Ty_Imm:
153  MIB.addImm(Imm);
154  break;
155  }
156  }
157 
159  switch (Ty) {
161  case SrcType::Ty_Imm:
162  llvm_unreachable("Not a register operand");
163  case SrcType::Ty_Reg:
164  return MRI.getType(Reg);
165  case SrcType::Ty_MIB:
166  return MRI.getType(SrcMIB->getOperand(0).getReg());
167  }
168  llvm_unreachable("Unrecognised SrcOp::SrcType enum");
169  }
170 
171  Register getReg() const {
172  switch (Ty) {
174  case SrcType::Ty_Imm:
175  llvm_unreachable("Not a register operand");
176  case SrcType::Ty_Reg:
177  return Reg;
178  case SrcType::Ty_MIB:
179  return SrcMIB->getOperand(0).getReg();
180  }
181  llvm_unreachable("Unrecognised SrcOp::SrcType enum");
182  }
183 
185  switch (Ty) {
187  return Pred;
188  default:
189  llvm_unreachable("Not a register operand");
190  }
191  }
192 
193  int64_t getImm() const {
194  switch (Ty) {
195  case SrcType::Ty_Imm:
196  return Imm;
197  default:
198  llvm_unreachable("Not an immediate");
199  }
200  }
201 
202  SrcType getSrcOpKind() const { return Ty; }
203 
204 private:
205  SrcType Ty;
206 };
207 
208 /// Helper class to build MachineInstr.
209 /// It keeps internally the insertion point and debug location for all
210 /// the new instructions we want to create.
211 /// This information can be modify via the related setters.
213 
214  MachineIRBuilderState State;
215 
216 protected:
217  void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend);
218 
219  void validateUnaryOp(const LLT Res, const LLT Op0);
220  void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1);
221  void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1);
222 
223  void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty,
224  const LLT Op1Ty);
225 
226  void recordInsertion(MachineInstr *InsertedInstr) const {
227  if (State.Observer)
228  State.Observer->createdInstr(*InsertedInstr);
229  }
230 
231 public:
232  /// Some constructors for easy use.
233  MachineIRBuilder() = default;
235 
237  setMF(*MBB.getParent());
238  setInsertPt(MBB, InsPt);
239  }
240 
242  MachineIRBuilder(*MI.getParent(), MI.getIterator()) {
243  setInstr(MI);
244  setDebugLoc(MI.getDebugLoc());
245  }
246 
249  setChangeObserver(Observer);
250  }
251 
252  virtual ~MachineIRBuilder() = default;
253 
254  MachineIRBuilder(const MachineIRBuilderState &BState) : State(BState) {}
255 
257  assert(State.TII && "TargetInstrInfo is not set");
258  return *State.TII;
259  }
260 
261  /// Getter for the function we currently build.
263  assert(State.MF && "MachineFunction is not set");
264  return *State.MF;
265  }
266 
267  const MachineFunction &getMF() const {
268  assert(State.MF && "MachineFunction is not set");
269  return *State.MF;
270  }
271 
272  const DataLayout &getDataLayout() const {
273  return getMF().getFunction().getParent()->getDataLayout();
274  }
275 
276  /// Getter for DebugLoc
277  const DebugLoc &getDL() { return State.DL; }
278 
279  /// Getter for MRI
280  MachineRegisterInfo *getMRI() { return State.MRI; }
281  const MachineRegisterInfo *getMRI() const { return State.MRI; }
282 
283  /// Getter for the State
284  MachineIRBuilderState &getState() { return State; }
285 
286  /// Getter for the basic block we currently build.
287  const MachineBasicBlock &getMBB() const {
288  assert(State.MBB && "MachineBasicBlock is not set");
289  return *State.MBB;
290  }
291 
293  return const_cast<MachineBasicBlock &>(
294  const_cast<const MachineIRBuilder *>(this)->getMBB());
295  }
296 
297  GISelCSEInfo *getCSEInfo() { return State.CSEInfo; }
298  const GISelCSEInfo *getCSEInfo() const { return State.CSEInfo; }
299 
300  /// Current insertion point for new instructions.
302 
303  /// Set the insertion point before the specified position.
304  /// \pre MBB must be in getMF().
305  /// \pre II must be a valid iterator in MBB.
307  assert(MBB.getParent() == &getMF() &&
308  "Basic block is in a different function");
309  State.MBB = &MBB;
310  State.II = II;
311  }
312 
313  /// @}
314 
316 
317  /// \name Setters for the insertion point.
318  /// @{
319  /// Set the MachineFunction where to build instructions.
320  void setMF(MachineFunction &MF);
321 
322  /// Set the insertion point to the end of \p MBB.
323  /// \pre \p MBB must be contained by getMF().
325  State.MBB = &MBB;
326  State.II = MBB.end();
327  assert(&getMF() == MBB.getParent() &&
328  "Basic block is in a different function");
329  }
330 
331  /// Set the insertion point to before MI.
332  /// \pre MI must be in getMF().
334  assert(MI.getParent() && "Instruction is not part of a basic block");
335  setMBB(*MI.getParent());
336  State.II = MI.getIterator();
337  }
338  /// @}
339 
340  /// Set the insertion point to before MI, and set the debug loc to MI's loc.
341  /// \pre MI must be in getMF().
343  setInstr(MI);
344  setDebugLoc(MI.getDebugLoc());
345  }
346 
348  State.Observer = &Observer;
349  }
350 
351  void stopObservingChanges() { State.Observer = nullptr; }
352  /// @}
353 
354  /// Set the debug location to \p DL for all the next build instructions.
355  void setDebugLoc(const DebugLoc &DL) { this->State.DL = DL; }
356 
357  /// Get the current instruction's debug location.
358  const DebugLoc &getDebugLoc() { return State.DL; }
359 
360  /// Build and insert <empty> = \p Opcode <empty>.
361  /// The insertion point is the one set by the last call of either
362  /// setBasicBlock or setMI.
363  ///
364  /// \pre setBasicBlock or setMI must have been called.
365  ///
366  /// \return a MachineInstrBuilder for the newly created instruction.
367  MachineInstrBuilder buildInstr(unsigned Opcode) {
368  return insertInstr(buildInstrNoInsert(Opcode));
369  }
370 
371  /// Build but don't insert <empty> = \p Opcode <empty>.
372  ///
373  /// \pre setMF, setBasicBlock or setMI must have been called.
374  ///
375  /// \return a MachineInstrBuilder for the newly created instruction.
376  MachineInstrBuilder buildInstrNoInsert(unsigned Opcode);
377 
378  /// Insert an existing instruction at the insertion point.
380 
381  /// Build and insert a DBG_VALUE instruction expressing the fact that the
382  /// associated \p Variable lives in \p Reg (suitably modified by \p Expr).
384  const MDNode *Expr);
385 
386  /// Build and insert a DBG_VALUE instruction expressing the fact that the
387  /// associated \p Variable lives in memory at \p Reg (suitably modified by \p
388  /// Expr).
390  const MDNode *Variable,
391  const MDNode *Expr);
392 
393  /// Build and insert a DBG_VALUE instruction expressing the fact that the
394  /// associated \p Variable lives in the stack slot specified by \p FI
395  /// (suitably modified by \p Expr).
396  MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable,
397  const MDNode *Expr);
398 
399  /// Build and insert a DBG_VALUE instructions specifying that \p Variable is
400  /// given by \p C (suitably modified by \p Expr).
402  const MDNode *Variable,
403  const MDNode *Expr);
404 
405  /// Build and insert a DBG_LABEL instructions specifying that \p Label is
406  /// given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label".
408 
409  /// Build and insert \p Res = G_DYN_STACKALLOC \p Size, \p Align
410  ///
411  /// G_DYN_STACKALLOC does a dynamic stack allocation and writes the address of
412  /// the allocated memory into \p Res.
413  /// \pre setBasicBlock or setMI must have been called.
414  /// \pre \p Res must be a generic virtual register with pointer type.
415  ///
416  /// \return a MachineInstrBuilder for the newly created instruction.
418  Align Alignment);
419 
420  /// Build and insert \p Res = G_FRAME_INDEX \p Idx
421  ///
422  /// G_FRAME_INDEX materializes the address of an alloca value or other
423  /// stack-based object.
424  ///
425  /// \pre setBasicBlock or setMI must have been called.
426  /// \pre \p Res must be a generic virtual register with pointer type.
427  ///
428  /// \return a MachineInstrBuilder for the newly created instruction.
429  MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx);
430 
431  /// Build and insert \p Res = G_GLOBAL_VALUE \p GV
432  ///
433  /// G_GLOBAL_VALUE materializes the address of the specified global
434  /// into \p Res.
435  ///
436  /// \pre setBasicBlock or setMI must have been called.
437  /// \pre \p Res must be a generic virtual register with pointer type
438  /// in the same address space as \p GV.
439  ///
440  /// \return a MachineInstrBuilder for the newly created instruction.
441  MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV);
442 
443  /// Build and insert \p Res = G_PTR_ADD \p Op0, \p Op1
444  ///
445  /// G_PTR_ADD adds \p Op1 addressible units to the pointer specified by \p Op0,
446  /// storing the resulting pointer in \p Res. Addressible units are typically
447  /// bytes but this can vary between targets.
448  ///
449  /// \pre setBasicBlock or setMI must have been called.
450  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
451  /// type.
452  /// \pre \p Op1 must be a generic virtual register with scalar type.
453  ///
454  /// \return a MachineInstrBuilder for the newly created instruction.
455  MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0,
456  const SrcOp &Op1);
457 
458  /// Materialize and insert \p Res = G_PTR_ADD \p Op0, (G_CONSTANT \p Value)
459  ///
460  /// G_PTR_ADD adds \p Value bytes to the pointer specified by \p Op0,
461  /// storing the resulting pointer in \p Res. If \p Value is zero then no
462  /// G_PTR_ADD or G_CONSTANT will be created and \pre Op0 will be assigned to
463  /// \p Res.
464  ///
465  /// \pre setBasicBlock or setMI must have been called.
466  /// \pre \p Op0 must be a generic virtual register with pointer type.
467  /// \pre \p ValueTy must be a scalar type.
468  /// \pre \p Res must be 0. This is to detect confusion between
469  /// materializePtrAdd() and buildPtrAdd().
470  /// \post \p Res will either be a new generic virtual register of the same
471  /// type as \p Op0 or \p Op0 itself.
472  ///
473  /// \return a MachineInstrBuilder for the newly created instruction.
475  const LLT ValueTy,
476  uint64_t Value);
477 
478  /// Build and insert \p Res = G_PTRMASK \p Op0, \p Op1
479  MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0,
480  const SrcOp &Op1) {
481  return buildInstr(TargetOpcode::G_PTRMASK, {Res}, {Op0, Op1});
482  }
483 
484  /// Build and insert \p Res = G_PTRMASK \p Op0, \p G_CONSTANT (1 << NumBits) - 1
485  ///
486  /// This clears the low bits of a pointer operand without destroying its
487  /// pointer properties. This has the effect of rounding the address *down* to
488  /// a specified alignment in bits.
489  ///
490  /// \pre setBasicBlock or setMI must have been called.
491  /// \pre \p Res and \p Op0 must be generic virtual registers with pointer
492  /// type.
493  /// \pre \p NumBits must be an integer representing the number of low bits to
494  /// be cleared in \p Op0.
495  ///
496  /// \return a MachineInstrBuilder for the newly created instruction.
497  MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0,
498  uint32_t NumBits);
499 
500  /// Build and insert
501  /// a, b, ..., x = G_UNMERGE_VALUES \p Op0
502  /// \p Res = G_BUILD_VECTOR a, b, ..., x, undef, ..., undef
503  ///
504  /// Pad \p Op0 with undef elements to match number of elements in \p Res.
505  ///
506  /// \pre setBasicBlock or setMI must have been called.
507  /// \pre \p Res and \p Op0 must be generic virtual registers with vector type,
508  /// same vector element type and Op0 must have fewer elements then Res.
509  ///
510  /// \return a MachineInstrBuilder for the newly created build vector instr.
512  const SrcOp &Op0);
513 
514  /// Build and insert
515  /// a, b, ..., x, y, z = G_UNMERGE_VALUES \p Op0
516  /// \p Res = G_BUILD_VECTOR a, b, ..., x
517  ///
518  /// Delete trailing elements in \p Op0 to match number of elements in \p Res.
519  ///
520  /// \pre setBasicBlock or setMI must have been called.
521  /// \pre \p Res and \p Op0 must be generic virtual registers with vector type,
522  /// same vector element type and Op0 must have more elements then Res.
523  ///
524  /// \return a MachineInstrBuilder for the newly created build vector instr.
526  const SrcOp &Op0);
527 
528  /// Build and insert \p Res, \p CarryOut = G_UADDO \p Op0, \p Op1
529  ///
530  /// G_UADDO sets \p Res to \p Op0 + \p Op1 (truncated to the bit width) and
531  /// sets \p CarryOut to 1 if the result overflowed in unsigned arithmetic.
532  ///
533  /// \pre setBasicBlock or setMI must have been called.
534  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers with the
535  /// same scalar type.
536  ////\pre \p CarryOut must be generic virtual register with scalar type
537  ///(typically s1)
538  ///
539  /// \return The newly created instruction.
540  MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut,
541  const SrcOp &Op0, const SrcOp &Op1) {
542  return buildInstr(TargetOpcode::G_UADDO, {Res, CarryOut}, {Op0, Op1});
543  }
544 
545  /// Build and insert \p Res, \p CarryOut = G_USUBO \p Op0, \p Op1
546  MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut,
547  const SrcOp &Op0, const SrcOp &Op1) {
548  return buildInstr(TargetOpcode::G_USUBO, {Res, CarryOut}, {Op0, Op1});
549  }
550 
551  /// Build and insert \p Res, \p CarryOut = G_SADDO \p Op0, \p Op1
552  MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut,
553  const SrcOp &Op0, const SrcOp &Op1) {
554  return buildInstr(TargetOpcode::G_SADDO, {Res, CarryOut}, {Op0, Op1});
555  }
556 
557  /// Build and insert \p Res, \p CarryOut = G_SUBO \p Op0, \p Op1
558  MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut,
559  const SrcOp &Op0, const SrcOp &Op1) {
560  return buildInstr(TargetOpcode::G_SSUBO, {Res, CarryOut}, {Op0, Op1});
561  }
562 
563  /// Build and insert \p Res, \p CarryOut = G_UADDE \p Op0,
564  /// \p Op1, \p CarryIn
565  ///
566  /// G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit
567  /// width) and sets \p CarryOut to 1 if the result overflowed in unsigned
568  /// arithmetic.
569  ///
570  /// \pre setBasicBlock or setMI must have been called.
571  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
572  /// with the same scalar type.
573  /// \pre \p CarryOut and \p CarryIn must be generic virtual
574  /// registers with the same scalar type (typically s1)
575  ///
576  /// \return The newly created instruction.
577  MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut,
578  const SrcOp &Op0, const SrcOp &Op1,
579  const SrcOp &CarryIn) {
580  return buildInstr(TargetOpcode::G_UADDE, {Res, CarryOut},
581  {Op0, Op1, CarryIn});
582  }
583 
584  /// Build and insert \p Res, \p CarryOut = G_USUBE \p Op0, \p Op1, \p CarryInp
585  MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut,
586  const SrcOp &Op0, const SrcOp &Op1,
587  const SrcOp &CarryIn) {
588  return buildInstr(TargetOpcode::G_USUBE, {Res, CarryOut},
589  {Op0, Op1, CarryIn});
590  }
591 
592  /// Build and insert \p Res, \p CarryOut = G_SADDE \p Op0, \p Op1, \p CarryInp
593  MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut,
594  const SrcOp &Op0, const SrcOp &Op1,
595  const SrcOp &CarryIn) {
596  return buildInstr(TargetOpcode::G_SADDE, {Res, CarryOut},
597  {Op0, Op1, CarryIn});
598  }
599 
600  /// Build and insert \p Res, \p CarryOut = G_SSUBE \p Op0, \p Op1, \p CarryInp
601  MachineInstrBuilder buildSSube(const DstOp &Res, const DstOp &CarryOut,
602  const SrcOp &Op0, const SrcOp &Op1,
603  const SrcOp &CarryIn) {
604  return buildInstr(TargetOpcode::G_SSUBE, {Res, CarryOut},
605  {Op0, Op1, CarryIn});
606  }
607 
608  /// Build and insert \p Res = G_ANYEXT \p Op0
609  ///
610  /// G_ANYEXT produces a register of the specified width, with bits 0 to
611  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified
612  /// (i.e. this is neither zero nor sign-extension). For a vector register,
613  /// each element is extended individually.
614  ///
615  /// \pre setBasicBlock or setMI must have been called.
616  /// \pre \p Res must be a generic virtual register with scalar or vector type.
617  /// \pre \p Op must be a generic virtual register with scalar or vector type.
618  /// \pre \p Op must be smaller than \p Res
619  ///
620  /// \return The newly created instruction.
621 
622  MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);
623 
624  /// Build and insert \p Res = G_SEXT \p Op
625  ///
626  /// G_SEXT produces a register of the specified width, with bits 0 to
627  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the
628  /// high bit of \p Op (i.e. 2s-complement sign extended).
629  ///
630  /// \pre setBasicBlock or setMI must have been called.
631  /// \pre \p Res must be a generic virtual register with scalar or vector type.
632  /// \pre \p Op must be a generic virtual register with scalar or vector type.
633  /// \pre \p Op must be smaller than \p Res
634  ///
635  /// \return The newly created instruction.
636  MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op);
637 
638  /// Build and insert \p Res = G_SEXT_INREG \p Op, ImmOp
639  MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp) {
640  return buildInstr(TargetOpcode::G_SEXT_INREG, {Res}, {Op, SrcOp(ImmOp)});
641  }
642 
643  /// Build and insert \p Res = G_FPEXT \p Op
645  Optional<unsigned> Flags = None) {
646  return buildInstr(TargetOpcode::G_FPEXT, {Res}, {Op}, Flags);
647  }
648 
649 
650  /// Build and insert a G_PTRTOINT instruction.
651  MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src) {
652  return buildInstr(TargetOpcode::G_PTRTOINT, {Dst}, {Src});
653  }
654 
655  /// Build and insert a G_INTTOPTR instruction.
656  MachineInstrBuilder buildIntToPtr(const DstOp &Dst, const SrcOp &Src) {
657  return buildInstr(TargetOpcode::G_INTTOPTR, {Dst}, {Src});
658  }
659 
660  /// Build and insert \p Dst = G_BITCAST \p Src
661  MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) {
662  return buildInstr(TargetOpcode::G_BITCAST, {Dst}, {Src});
663  }
664 
665  /// Build and insert \p Dst = G_ADDRSPACE_CAST \p Src
667  return buildInstr(TargetOpcode::G_ADDRSPACE_CAST, {Dst}, {Src});
668  }
669 
670  /// \return The opcode of the extension the target wants to use for boolean
671  /// values.
672  unsigned getBoolExtOp(bool IsVec, bool IsFP) const;
673 
674  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_SEXT \p Op, or \p Res
675  // = G_ZEXT \p Op depending on how the target wants to extend boolean values.
676  MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op,
677  bool IsFP);
678 
679  /// Build and insert \p Res = G_ZEXT \p Op
680  ///
681  /// G_ZEXT produces a register of the specified width, with bits 0 to
682  /// sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector
683  /// register, each element is extended individually.
684  ///
685  /// \pre setBasicBlock or setMI must have been called.
686  /// \pre \p Res must be a generic virtual register with scalar or vector type.
687  /// \pre \p Op must be a generic virtual register with scalar or vector type.
688  /// \pre \p Op must be smaller than \p Res
689  ///
690  /// \return The newly created instruction.
691  MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op);
692 
693  /// Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or
694  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
695  /// ///
696  /// \pre setBasicBlock or setMI must have been called.
697  /// \pre \p Res must be a generic virtual register with scalar or vector type.
698  /// \pre \p Op must be a generic virtual register with scalar or vector type.
699  ///
700  /// \return The newly created instruction.
701  MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op);
702 
703  /// Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or
704  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
705  /// ///
706  /// \pre setBasicBlock or setMI must have been called.
707  /// \pre \p Res must be a generic virtual register with scalar or vector type.
708  /// \pre \p Op must be a generic virtual register with scalar or vector type.
709  ///
710  /// \return The newly created instruction.
711  MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op);
712 
713  // Build and insert \p Res = G_ANYEXT \p Op, \p Res = G_TRUNC \p Op, or
714  /// \p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op.
715  /// ///
716  /// \pre setBasicBlock or setMI must have been called.
717  /// \pre \p Res must be a generic virtual register with scalar or vector type.
718  /// \pre \p Op must be a generic virtual register with scalar or vector type.
719  ///
720  /// \return The newly created instruction.
722 
723  /// Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p
724  /// Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and
725  /// \p Op.
726  /// ///
727  /// \pre setBasicBlock or setMI must have been called.
728  /// \pre \p Res must be a generic virtual register with scalar or vector type.
729  /// \pre \p Op must be a generic virtual register with scalar or vector type.
730  ///
731  /// \return The newly created instruction.
732  MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
733  const SrcOp &Op);
734 
735  /// Build and inserts \p Res = \p G_AND \p Op, \p LowBitsSet(ImmOp)
736  /// Since there is no G_ZEXT_INREG like G_SEXT_INREG, the instruction is
737  /// emulated using G_AND.
738  MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op,
739  int64_t ImmOp);
740 
741  /// Build and insert an appropriate cast between two registers of equal size.
742  MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src);
743 
744  /// Build and insert G_BR \p Dest
745  ///
746  /// G_BR is an unconditional branch to \p Dest.
747  ///
748  /// \pre setBasicBlock or setMI must have been called.
749  ///
750  /// \return a MachineInstrBuilder for the newly created instruction.
752 
753  /// Build and insert G_BRCOND \p Tst, \p Dest
754  ///
755  /// G_BRCOND is a conditional branch to \p Dest.
756  ///
757  /// \pre setBasicBlock or setMI must have been called.
758  /// \pre \p Tst must be a generic virtual register with scalar
759  /// type. At the beginning of legalization, this will be a single
760  /// bit (s1). Targets with interesting flags registers may change
761  /// this. For a wider type, whether the branch is taken must only
762  /// depend on bit 0 (for now).
763  ///
764  /// \return The newly created instruction.
766 
767  /// Build and insert G_BRINDIRECT \p Tgt
768  ///
769  /// G_BRINDIRECT is an indirect branch to \p Tgt.
770  ///
771  /// \pre setBasicBlock or setMI must have been called.
772  /// \pre \p Tgt must be a generic virtual register with pointer type.
773  ///
774  /// \return a MachineInstrBuilder for the newly created instruction.
776 
777  /// Build and insert G_BRJT \p TablePtr, \p JTI, \p IndexReg
778  ///
779  /// G_BRJT is a jump table branch using a table base pointer \p TablePtr,
780  /// jump table index \p JTI and index \p IndexReg
781  ///
782  /// \pre setBasicBlock or setMI must have been called.
783  /// \pre \p TablePtr must be a generic virtual register with pointer type.
784  /// \pre \p JTI must be be a jump table index.
785  /// \pre \p IndexReg must be a generic virtual register with pointer type.
786  ///
787  /// \return a MachineInstrBuilder for the newly created instruction.
788  MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI,
789  Register IndexReg);
790 
791  /// Build and insert \p Res = G_CONSTANT \p Val
792  ///
793  /// G_CONSTANT is an integer constant with the specified size and value. \p
794  /// Val will be extended or truncated to the size of \p Reg.
795  ///
796  /// \pre setBasicBlock or setMI must have been called.
797  /// \pre \p Res must be a generic virtual register with scalar or pointer
798  /// type.
799  ///
800  /// \return The newly created instruction.
801  virtual MachineInstrBuilder buildConstant(const DstOp &Res,
802  const ConstantInt &Val);
803 
804  /// Build and insert \p Res = G_CONSTANT \p Val
805  ///
806  /// G_CONSTANT is an integer constant with the specified size and value.
807  ///
808  /// \pre setBasicBlock or setMI must have been called.
809  /// \pre \p Res must be a generic virtual register with scalar type.
810  ///
811  /// \return The newly created instruction.
812  MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val);
813  MachineInstrBuilder buildConstant(const DstOp &Res, const APInt &Val);
814 
815  /// Build and insert \p Res = G_FCONSTANT \p Val
816  ///
817  /// G_FCONSTANT is a floating-point constant with the specified size and
818  /// value.
819  ///
820  /// \pre setBasicBlock or setMI must have been called.
821  /// \pre \p Res must be a generic virtual register with scalar type.
822  ///
823  /// \return The newly created instruction.
824  virtual MachineInstrBuilder buildFConstant(const DstOp &Res,
825  const ConstantFP &Val);
826 
827  MachineInstrBuilder buildFConstant(const DstOp &Res, double Val);
828  MachineInstrBuilder buildFConstant(const DstOp &Res, const APFloat &Val);
829 
830  /// Build and insert \p Res = COPY Op
831  ///
832  /// Register-to-register COPY sets \p Res to \p Op.
833  ///
834  /// \pre setBasicBlock or setMI must have been called.
835  ///
836  /// \return a MachineInstrBuilder for the newly created instruction.
837  MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);
838 
839  /// Build and insert \p Res = G_ASSERT_ZEXT Op, Size
840  ///
841  /// \return a MachineInstrBuilder for the newly created instruction.
842  MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op,
843  unsigned Size);
844 
845  /// Build and insert \p Res = G_ASSERT_SEXT Op, Size
846  ///
847  /// \return a MachineInstrBuilder for the newly created instruction.
848  MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op,
849  unsigned Size);
850 
851  /// Build and insert `Res = G_LOAD Addr, MMO`.
852  ///
853  /// Loads the value stored at \p Addr. Puts the result in \p Res.
854  ///
855  /// \pre setBasicBlock or setMI must have been called.
856  /// \pre \p Res must be a generic virtual register.
857  /// \pre \p Addr must be a generic virtual register with pointer type.
858  ///
859  /// \return a MachineInstrBuilder for the newly created instruction.
861  MachineMemOperand &MMO) {
862  return buildLoadInstr(TargetOpcode::G_LOAD, Res, Addr, MMO);
863  }
864 
865  /// Build and insert a G_LOAD instruction, while constructing the
866  /// MachineMemOperand.
868  buildLoad(const DstOp &Res, const SrcOp &Addr, MachinePointerInfo PtrInfo,
869  Align Alignment,
871  const AAMDNodes &AAInfo = AAMDNodes());
872 
873  /// Build and insert `Res = <opcode> Addr, MMO`.
874  ///
875  /// Loads the value stored at \p Addr. Puts the result in \p Res.
876  ///
877  /// \pre setBasicBlock or setMI must have been called.
878  /// \pre \p Res must be a generic virtual register.
879  /// \pre \p Addr must be a generic virtual register with pointer type.
880  ///
881  /// \return a MachineInstrBuilder for the newly created instruction.
882  MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res,
883  const SrcOp &Addr, MachineMemOperand &MMO);
884 
885  /// Helper to create a load from a constant offset given a base address. Load
886  /// the type of \p Dst from \p Offset from the given base address and memory
887  /// operand.
889  const SrcOp &BasePtr,
890  MachineMemOperand &BaseMMO,
891  int64_t Offset);
892 
893  /// Build and insert `G_STORE Val, Addr, MMO`.
894  ///
895  /// Stores the value \p Val to \p Addr.
896  ///
897  /// \pre setBasicBlock or setMI must have been called.
898  /// \pre \p Val must be a generic virtual register.
899  /// \pre \p Addr must be a generic virtual register with pointer type.
900  ///
901  /// \return a MachineInstrBuilder for the newly created instruction.
902  MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr,
903  MachineMemOperand &MMO);
904 
905  /// Build and insert a G_STORE instruction, while constructing the
906  /// MachineMemOperand.
908  buildStore(const SrcOp &Val, const SrcOp &Addr, MachinePointerInfo PtrInfo,
909  Align Alignment,
911  const AAMDNodes &AAInfo = AAMDNodes());
912 
913  /// Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.
914  ///
915  /// \pre setBasicBlock or setMI must have been called.
916  /// \pre \p Res and \p Src must be generic virtual registers.
917  ///
918  /// \return a MachineInstrBuilder for the newly created instruction.
919  MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index);
920 
921  /// Build and insert \p Res = IMPLICIT_DEF.
923 
924  /// Build and insert instructions to put \p Ops together at the specified p
925  /// Indices to form a larger register.
926  ///
927  /// If the types of the input registers are uniform and cover the entirity of
928  /// \p Res then a G_MERGE_VALUES will be produced. Otherwise an IMPLICIT_DEF
929  /// followed by a sequence of G_INSERT instructions.
930  ///
931  /// \pre setBasicBlock or setMI must have been called.
932  /// \pre The final element of the sequence must not extend past the end of the
933  /// destination register.
934  /// \pre The bits defined by each Op (derived from index and scalar size) must
935  /// not overlap.
936  /// \pre \p Indices must be in ascending order of bit position.
938  ArrayRef<uint64_t> Indices);
939 
940  /// Build and insert \p Res = G_MERGE_VALUES \p Op0, ...
941  ///
942  /// G_MERGE_VALUES combines the input elements contiguously into a larger
943  /// register.
944  ///
945  /// \pre setBasicBlock or setMI must have been called.
946  /// \pre The entire register \p Res (and no more) must be covered by the input
947  /// registers.
948  /// \pre The type of all \p Ops registers must be identical.
949  ///
950  /// \return a MachineInstrBuilder for the newly created instruction.
953  std::initializer_list<SrcOp> Ops);
954 
955  /// Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op
956  ///
957  /// G_UNMERGE_VALUES splits contiguous bits of the input into multiple
958  ///
959  /// \pre setBasicBlock or setMI must have been called.
960  /// \pre The entire register \p Res (and no more) must be covered by the input
961  /// registers.
962  /// \pre The type of all \p Res registers must be identical.
963  ///
964  /// \return a MachineInstrBuilder for the newly created instruction.
967 
968  /// Build and insert an unmerge of \p Res sized pieces to cover \p Op
970 
971  /// Build and insert \p Res = G_BUILD_VECTOR \p Op0, ...
972  ///
973  /// G_BUILD_VECTOR creates a vector value from multiple scalar registers.
974  /// \pre setBasicBlock or setMI must have been called.
975  /// \pre The entire register \p Res (and no more) must be covered by the
976  /// input scalar registers.
977  /// \pre The type of all \p Ops registers must be identical.
978  ///
979  /// \return a MachineInstrBuilder for the newly created instruction.
981  ArrayRef<Register> Ops);
982 
983  /// Build and insert \p Res = G_BUILD_VECTOR with \p Src replicated to fill
984  /// the number of elements
986  const SrcOp &Src);
987 
988  /// Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ...
989  ///
990  /// G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers
991  /// which have types larger than the destination vector element type, and
992  /// truncates the values to fit.
993  ///
994  /// If the operands given are already the same size as the vector elt type,
995  /// then this method will instead create a G_BUILD_VECTOR instruction.
996  ///
997  /// \pre setBasicBlock or setMI must have been called.
998  /// \pre The type of all \p Ops registers must be identical.
999  ///
1000  /// \return a MachineInstrBuilder for the newly created instruction.
1002  ArrayRef<Register> Ops);
1003 
1004  /// Build and insert a vector splat of a scalar \p Src using a
1005  /// G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idiom.
1006  ///
1007  /// \pre setBasicBlock or setMI must have been called.
1008  /// \pre \p Src must have the same type as the element type of \p Dst
1009  ///
1010  /// \return a MachineInstrBuilder for the newly created instruction.
1011  MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src);
1012 
1013  /// Build and insert \p Res = G_SHUFFLE_VECTOR \p Src1, \p Src2, \p Mask
1014  ///
1015  /// \pre setBasicBlock or setMI must have been called.
1016  ///
1017  /// \return a MachineInstrBuilder for the newly created instruction.
1018  MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1,
1019  const SrcOp &Src2, ArrayRef<int> Mask);
1020 
1021  /// Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ...
1022  ///
1023  /// G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more
1024  /// vectors.
1025  ///
1026  /// \pre setBasicBlock or setMI must have been called.
1027  /// \pre The entire register \p Res (and no more) must be covered by the input
1028  /// registers.
1029  /// \pre The type of all source operands must be identical.
1030  ///
1031  /// \return a MachineInstrBuilder for the newly created instruction.
1033  ArrayRef<Register> Ops);
1034 
1035  MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src,
1036  const SrcOp &Op, unsigned Index);
1037 
1038  /// Build and insert either a G_INTRINSIC (if \p HasSideEffects is false) or
1039  /// G_INTRINSIC_W_SIDE_EFFECTS instruction. Its first operand will be the
1040  /// result register definition unless \p Reg is NoReg (== 0). The second
1041  /// operand will be the intrinsic's ID.
1042  ///
1043  /// Callers are expected to add the required definitions and uses afterwards.
1044  ///
1045  /// \pre setBasicBlock or setMI must have been called.
1046  ///
1047  /// \return a MachineInstrBuilder for the newly created instruction.
1049  bool HasSideEffects);
1051  bool HasSideEffects);
1052 
1053  /// Build and insert \p Res = G_FPTRUNC \p Op
1054  ///
1055  /// G_FPTRUNC converts a floating-point value into one with a smaller type.
1056  ///
1057  /// \pre setBasicBlock or setMI must have been called.
1058  /// \pre \p Res must be a generic virtual register with scalar or vector type.
1059  /// \pre \p Op must be a generic virtual register with scalar or vector type.
1060  /// \pre \p Res must be smaller than \p Op
1061  ///
1062  /// \return The newly created instruction.
1063  MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op,
1064  Optional<unsigned> Flags = None);
1065 
1066  /// Build and insert \p Res = G_TRUNC \p Op
1067  ///
1068  /// G_TRUNC extracts the low bits of a type. For a vector type each element is
1069  /// truncated independently before being packed into the destination.
1070  ///
1071  /// \pre setBasicBlock or setMI must have been called.
1072  /// \pre \p Res must be a generic virtual register with scalar or vector type.
1073  /// \pre \p Op must be a generic virtual register with scalar or vector type.
1074  /// \pre \p Res must be smaller than \p Op
1075  ///
1076  /// \return The newly created instruction.
1077  MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op);
1078 
1079  /// Build and insert a \p Res = G_ICMP \p Pred, \p Op0, \p Op1
1080  ///
1081  /// \pre setBasicBlock or setMI must have been called.
1082 
1083  /// \pre \p Res must be a generic virtual register with scalar or
1084  /// vector type. Typically this starts as s1 or <N x s1>.
1085  /// \pre \p Op0 and Op1 must be generic virtual registers with the
1086  /// same number of elements as \p Res. If \p Res is a scalar,
1087  /// \p Op0 must be either a scalar or pointer.
1088  /// \pre \p Pred must be an integer predicate.
1089  ///
1090  /// \return a MachineInstrBuilder for the newly created instruction.
1092  const SrcOp &Op0, const SrcOp &Op1);
1093 
1094  /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1
1095  ///
1096  /// \pre setBasicBlock or setMI must have been called.
1097 
1098  /// \pre \p Res must be a generic virtual register with scalar or
1099  /// vector type. Typically this starts as s1 or <N x s1>.
1100  /// \pre \p Op0 and Op1 must be generic virtual registers with the
1101  /// same number of elements as \p Res (or scalar, if \p Res is
1102  /// scalar).
1103  /// \pre \p Pred must be a floating-point predicate.
1104  ///
1105  /// \return a MachineInstrBuilder for the newly created instruction.
1107  const SrcOp &Op0, const SrcOp &Op1,
1108  Optional<unsigned> Flags = None);
1109 
1110  /// Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1
1111  ///
1112  /// \pre setBasicBlock or setMI must have been called.
1113  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1114  /// with the same type.
1115  /// \pre \p Tst must be a generic virtual register with scalar, pointer or
1116  /// vector type. If vector then it must have the same number of
1117  /// elements as the other parameters.
1118  ///
1119  /// \return a MachineInstrBuilder for the newly created instruction.
1120  MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,
1121  const SrcOp &Op0, const SrcOp &Op1,
1122  Optional<unsigned> Flags = None);
1123 
1124  /// Build and insert \p Res = G_INSERT_VECTOR_ELT \p Val,
1125  /// \p Elt, \p Idx
1126  ///
1127  /// \pre setBasicBlock or setMI must have been called.
1128  /// \pre \p Res and \p Val must be a generic virtual register
1129  // with the same vector type.
1130  /// \pre \p Elt and \p Idx must be a generic virtual register
1131  /// with scalar type.
1132  ///
1133  /// \return The newly created instruction.
1135  const SrcOp &Val,
1136  const SrcOp &Elt,
1137  const SrcOp &Idx);
1138 
1139  /// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx
1140  ///
1141  /// \pre setBasicBlock or setMI must have been called.
1142  /// \pre \p Res must be a generic virtual register with scalar type.
1143  /// \pre \p Val must be a generic virtual register with vector type.
1144  /// \pre \p Idx must be a generic virtual register with scalar type.
1145  ///
1146  /// \return The newly created instruction.
1148  const SrcOp &Val,
1149  const SrcOp &Idx);
1150 
1151  /// Build and insert `OldValRes<def>, SuccessRes<def> =
1152  /// G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`.
1153  ///
1154  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
1155  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
1156  /// Addr in \p Res, along with an s1 indicating whether it was replaced.
1157  ///
1158  /// \pre setBasicBlock or setMI must have been called.
1159  /// \pre \p OldValRes must be a generic virtual register of scalar type.
1160  /// \pre \p SuccessRes must be a generic virtual register of scalar type. It
1161  /// will be assigned 0 on failure and 1 on success.
1162  /// \pre \p Addr must be a generic virtual register with pointer type.
1163  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
1164  /// registers of the same type.
1165  ///
1166  /// \return a MachineInstrBuilder for the newly created instruction.
1168  buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes,
1169  Register Addr, Register CmpVal, Register NewVal,
1170  MachineMemOperand &MMO);
1171 
1172  /// Build and insert `OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal,
1173  /// MMO`.
1174  ///
1175  /// Atomically replace the value at \p Addr with \p NewVal if it is currently
1176  /// \p CmpVal otherwise leaves it unchanged. Puts the original value from \p
1177  /// Addr in \p Res.
1178  ///
1179  /// \pre setBasicBlock or setMI must have been called.
1180  /// \pre \p OldValRes must be a generic virtual register of scalar type.
1181  /// \pre \p Addr must be a generic virtual register with pointer type.
1182  /// \pre \p OldValRes, \p CmpVal, and \p NewVal must be generic virtual
1183  /// registers of the same type.
1184  ///
1185  /// \return a MachineInstrBuilder for the newly created instruction.
1187  Register CmpVal, Register NewVal,
1188  MachineMemOperand &MMO);
1189 
1190  /// Build and insert `OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO`.
1191  ///
1192  /// Atomically read-modify-update the value at \p Addr with \p Val. Puts the
1193  /// original value from \p Addr in \p OldValRes. The modification is
1194  /// determined by the opcode.
1195  ///
1196  /// \pre setBasicBlock or setMI must have been called.
1197  /// \pre \p OldValRes must be a generic virtual register.
1198  /// \pre \p Addr must be a generic virtual register with pointer type.
1199  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1200  /// same type.
1201  ///
1202  /// \return a MachineInstrBuilder for the newly created instruction.
1203  MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes,
1204  const SrcOp &Addr, const SrcOp &Val,
1205  MachineMemOperand &MMO);
1206 
1207  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO`.
1208  ///
1209  /// Atomically replace the value at \p Addr with \p Val. Puts the original
1210  /// value from \p Addr in \p OldValRes.
1211  ///
1212  /// \pre setBasicBlock or setMI must have been called.
1213  /// \pre \p OldValRes must be a generic virtual register.
1214  /// \pre \p Addr must be a generic virtual register with pointer type.
1215  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1216  /// same type.
1217  ///
1218  /// \return a MachineInstrBuilder for the newly created instruction.
1220  Register Val, MachineMemOperand &MMO);
1221 
1222  /// Build and insert `OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO`.
1223  ///
1224  /// Atomically replace the value at \p Addr with the addition of \p Val and
1225  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1226  ///
1227  /// \pre setBasicBlock or setMI must have been called.
1228  /// \pre \p OldValRes must be a generic virtual register.
1229  /// \pre \p Addr must be a generic virtual register with pointer type.
1230  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1231  /// same type.
1232  ///
1233  /// \return a MachineInstrBuilder for the newly created instruction.
1235  Register Val, MachineMemOperand &MMO);
1236 
1237  /// Build and insert `OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO`.
1238  ///
1239  /// Atomically replace the value at \p Addr with the subtraction of \p Val and
1240  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1241  ///
1242  /// \pre setBasicBlock or setMI must have been called.
1243  /// \pre \p OldValRes must be a generic virtual register.
1244  /// \pre \p Addr must be a generic virtual register with pointer type.
1245  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1246  /// same type.
1247  ///
1248  /// \return a MachineInstrBuilder for the newly created instruction.
1250  Register Val, MachineMemOperand &MMO);
1251 
1252  /// Build and insert `OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO`.
1253  ///
1254  /// Atomically replace the value at \p Addr with the bitwise and of \p Val and
1255  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1256  ///
1257  /// \pre setBasicBlock or setMI must have been called.
1258  /// \pre \p OldValRes must be a generic virtual register.
1259  /// \pre \p Addr must be a generic virtual register with pointer type.
1260  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1261  /// same type.
1262  ///
1263  /// \return a MachineInstrBuilder for the newly created instruction.
1265  Register Val, MachineMemOperand &MMO);
1266 
1267  /// Build and insert `OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO`.
1268  ///
1269  /// Atomically replace the value at \p Addr with the bitwise nand of \p Val
1270  /// and the original value. Puts the original value from \p Addr in \p
1271  /// OldValRes.
1272  ///
1273  /// \pre setBasicBlock or setMI must have been called.
1274  /// \pre \p OldValRes must be a generic virtual register.
1275  /// \pre \p Addr must be a generic virtual register with pointer type.
1276  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1277  /// same type.
1278  ///
1279  /// \return a MachineInstrBuilder for the newly created instruction.
1281  Register Val, MachineMemOperand &MMO);
1282 
1283  /// Build and insert `OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO`.
1284  ///
1285  /// Atomically replace the value at \p Addr with the bitwise or of \p Val and
1286  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1287  ///
1288  /// \pre setBasicBlock or setMI must have been called.
1289  /// \pre \p OldValRes must be a generic virtual register.
1290  /// \pre \p Addr must be a generic virtual register with pointer type.
1291  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1292  /// same type.
1293  ///
1294  /// \return a MachineInstrBuilder for the newly created instruction.
1296  Register Val, MachineMemOperand &MMO);
1297 
1298  /// Build and insert `OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO`.
1299  ///
1300  /// Atomically replace the value at \p Addr with the bitwise xor of \p Val and
1301  /// the original value. Puts the original value from \p Addr in \p OldValRes.
1302  ///
1303  /// \pre setBasicBlock or setMI must have been called.
1304  /// \pre \p OldValRes must be a generic virtual register.
1305  /// \pre \p Addr must be a generic virtual register with pointer type.
1306  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1307  /// same type.
1308  ///
1309  /// \return a MachineInstrBuilder for the newly created instruction.
1311  Register Val, MachineMemOperand &MMO);
1312 
1313  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO`.
1314  ///
1315  /// Atomically replace the value at \p Addr with the signed maximum of \p
1316  /// Val and the original value. Puts the original value from \p Addr in \p
1317  /// OldValRes.
1318  ///
1319  /// \pre setBasicBlock or setMI must have been called.
1320  /// \pre \p OldValRes must be a generic virtual register.
1321  /// \pre \p Addr must be a generic virtual register with pointer type.
1322  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1323  /// same type.
1324  ///
1325  /// \return a MachineInstrBuilder for the newly created instruction.
1327  Register Val, MachineMemOperand &MMO);
1328 
1329  /// Build and insert `OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO`.
1330  ///
1331  /// Atomically replace the value at \p Addr with the signed minimum of \p
1332  /// Val and the original value. Puts the original value from \p Addr in \p
1333  /// OldValRes.
1334  ///
1335  /// \pre setBasicBlock or setMI must have been called.
1336  /// \pre \p OldValRes must be a generic virtual register.
1337  /// \pre \p Addr must be a generic virtual register with pointer type.
1338  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1339  /// same type.
1340  ///
1341  /// \return a MachineInstrBuilder for the newly created instruction.
1343  Register Val, MachineMemOperand &MMO);
1344 
1345  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO`.
1346  ///
1347  /// Atomically replace the value at \p Addr with the unsigned maximum of \p
1348  /// Val and the original value. Puts the original value from \p Addr in \p
1349  /// OldValRes.
1350  ///
1351  /// \pre setBasicBlock or setMI must have been called.
1352  /// \pre \p OldValRes must be a generic virtual register.
1353  /// \pre \p Addr must be a generic virtual register with pointer type.
1354  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1355  /// same type.
1356  ///
1357  /// \return a MachineInstrBuilder for the newly created instruction.
1359  Register Val, MachineMemOperand &MMO);
1360 
1361  /// Build and insert `OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO`.
1362  ///
1363  /// Atomically replace the value at \p Addr with the unsigned minimum of \p
1364  /// Val and the original value. Puts the original value from \p Addr in \p
1365  /// OldValRes.
1366  ///
1367  /// \pre setBasicBlock or setMI must have been called.
1368  /// \pre \p OldValRes must be a generic virtual register.
1369  /// \pre \p Addr must be a generic virtual register with pointer type.
1370  /// \pre \p OldValRes, and \p Val must be generic virtual registers of the
1371  /// same type.
1372  ///
1373  /// \return a MachineInstrBuilder for the newly created instruction.
1375  Register Val, MachineMemOperand &MMO);
1376 
1377  /// Build and insert `OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO`.
1379  const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1380  MachineMemOperand &MMO);
1381 
1382  /// Build and insert `OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO`.
1384  const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1385  MachineMemOperand &MMO);
1386 
1387  /// Build and insert `G_FENCE Ordering, Scope`.
1388  MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope);
1389 
1390  /// Build and insert \p Dst = G_FREEZE \p Src
1391  MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src) {
1392  return buildInstr(TargetOpcode::G_FREEZE, {Dst}, {Src});
1393  }
1394 
1395  /// Build and insert \p Res = G_BLOCK_ADDR \p BA
1396  ///
1397  /// G_BLOCK_ADDR computes the address of a basic block.
1398  ///
1399  /// \pre setBasicBlock or setMI must have been called.
1400  /// \pre \p Res must be a generic virtual register of a pointer type.
1401  ///
1402  /// \return The newly created instruction.
1404 
1405  /// Build and insert \p Res = G_ADD \p Op0, \p Op1
1406  ///
1407  /// G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1408  /// truncated to their width.
1409  ///
1410  /// \pre setBasicBlock or setMI must have been called.
1411  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1412  /// with the same (scalar or vector) type).
1413  ///
1414  /// \return a MachineInstrBuilder for the newly created instruction.
1415 
1416  MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,
1417  const SrcOp &Src1,
1418  Optional<unsigned> Flags = None) {
1419  return buildInstr(TargetOpcode::G_ADD, {Dst}, {Src0, Src1}, Flags);
1420  }
1421 
1422  /// Build and insert \p Res = G_SUB \p Op0, \p Op1
1423  ///
1424  /// G_SUB sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1425  /// truncated to their width.
1426  ///
1427  /// \pre setBasicBlock or setMI must have been called.
1428  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1429  /// with the same (scalar or vector) type).
1430  ///
1431  /// \return a MachineInstrBuilder for the newly created instruction.
1432 
1433  MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0,
1434  const SrcOp &Src1,
1435  Optional<unsigned> Flags = None) {
1436  return buildInstr(TargetOpcode::G_SUB, {Dst}, {Src0, Src1}, Flags);
1437  }
1438 
1439  /// Build and insert \p Res = G_MUL \p Op0, \p Op1
1440  ///
1441  /// G_MUL sets \p Res to the sum of integer parameters \p Op0 and \p Op1,
1442  /// truncated to their width.
1443  ///
1444  /// \pre setBasicBlock or setMI must have been called.
1445  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1446  /// with the same (scalar or vector) type).
1447  ///
1448  /// \return a MachineInstrBuilder for the newly created instruction.
1449  MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
1450  const SrcOp &Src1,
1451  Optional<unsigned> Flags = None) {
1452  return buildInstr(TargetOpcode::G_MUL, {Dst}, {Src0, Src1}, Flags);
1453  }
1454 
1455  MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0,
1456  const SrcOp &Src1,
1457  Optional<unsigned> Flags = None) {
1458  return buildInstr(TargetOpcode::G_UMULH, {Dst}, {Src0, Src1}, Flags);
1459  }
1460 
1461  MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0,
1462  const SrcOp &Src1,
1463  Optional<unsigned> Flags = None) {
1464  return buildInstr(TargetOpcode::G_SMULH, {Dst}, {Src0, Src1}, Flags);
1465  }
1466 
1467  /// Build and insert \p Res = G_UREM \p Op0, \p Op1
1468  MachineInstrBuilder buildURem(const DstOp &Dst, const SrcOp &Src0,
1469  const SrcOp &Src1,
1470  Optional<unsigned> Flags = None) {
1471  return buildInstr(TargetOpcode::G_UREM, {Dst}, {Src0, Src1}, Flags);
1472  }
1473 
1474  MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0,
1475  const SrcOp &Src1,
1476  Optional<unsigned> Flags = None) {
1477  return buildInstr(TargetOpcode::G_FMUL, {Dst}, {Src0, Src1}, Flags);
1478  }
1479 
1480  MachineInstrBuilder buildFMinNum(const DstOp &Dst, const SrcOp &Src0,
1481  const SrcOp &Src1,
1482  Optional<unsigned> Flags = None) {
1483  return buildInstr(TargetOpcode::G_FMINNUM, {Dst}, {Src0, Src1}, Flags);
1484  }
1485 
1486  MachineInstrBuilder buildFMaxNum(const DstOp &Dst, const SrcOp &Src0,
1487  const SrcOp &Src1,
1488  Optional<unsigned> Flags = None) {
1489  return buildInstr(TargetOpcode::G_FMAXNUM, {Dst}, {Src0, Src1}, Flags);
1490  }
1491 
1493  const SrcOp &Src1,
1494  Optional<unsigned> Flags = None) {
1495  return buildInstr(TargetOpcode::G_FMINNUM_IEEE, {Dst}, {Src0, Src1}, Flags);
1496  }
1497 
1499  const SrcOp &Src1,
1500  Optional<unsigned> Flags = None) {
1501  return buildInstr(TargetOpcode::G_FMAXNUM_IEEE, {Dst}, {Src0, Src1}, Flags);
1502  }
1503 
1504  MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0,
1505  const SrcOp &Src1,
1506  Optional<unsigned> Flags = None) {
1507  return buildInstr(TargetOpcode::G_SHL, {Dst}, {Src0, Src1}, Flags);
1508  }
1509 
1510  MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0,
1511  const SrcOp &Src1,
1512  Optional<unsigned> Flags = None) {
1513  return buildInstr(TargetOpcode::G_LSHR, {Dst}, {Src0, Src1}, Flags);
1514  }
1515 
1516  MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0,
1517  const SrcOp &Src1,
1518  Optional<unsigned> Flags = None) {
1519  return buildInstr(TargetOpcode::G_ASHR, {Dst}, {Src0, Src1}, Flags);
1520  }
1521 
1522  /// Build and insert \p Res = G_AND \p Op0, \p Op1
1523  ///
1524  /// G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p
1525  /// Op1.
1526  ///
1527  /// \pre setBasicBlock or setMI must have been called.
1528  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1529  /// with the same (scalar or vector) type).
1530  ///
1531  /// \return a MachineInstrBuilder for the newly created instruction.
1532 
1533  MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0,
1534  const SrcOp &Src1) {
1535  return buildInstr(TargetOpcode::G_AND, {Dst}, {Src0, Src1});
1536  }
1537 
1538  /// Build and insert \p Res = G_OR \p Op0, \p Op1
1539  ///
1540  /// G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p
1541  /// Op1.
1542  ///
1543  /// \pre setBasicBlock or setMI must have been called.
1544  /// \pre \p Res, \p Op0 and \p Op1 must be generic virtual registers
1545  /// with the same (scalar or vector) type).
1546  ///
1547  /// \return a MachineInstrBuilder for the newly created instruction.
1548  MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0,
1549  const SrcOp &Src1,
1550  Optional<unsigned> Flags = None) {
1551  return buildInstr(TargetOpcode::G_OR, {Dst}, {Src0, Src1}, Flags);
1552  }
1553 
1554  /// Build and insert \p Res = G_XOR \p Op0, \p Op1
1555  MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0,
1556  const SrcOp &Src1) {
1557  return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, Src1});
1558  }
1559 
1560  /// Build and insert a bitwise not,
1561  /// \p NegOne = G_CONSTANT -1
1562  /// \p Res = G_OR \p Op0, NegOne
1563  MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) {
1564  auto NegOne = buildConstant(Dst.getLLTTy(*getMRI()), -1);
1565  return buildInstr(TargetOpcode::G_XOR, {Dst}, {Src0, NegOne});
1566  }
1567 
1568  /// Build and insert integer negation
1569  /// \p Zero = G_CONSTANT 0
1570  /// \p Res = G_SUB Zero, \p Op0
1571  MachineInstrBuilder buildNeg(const DstOp &Dst, const SrcOp &Src0) {
1572  auto Zero = buildConstant(Dst.getLLTTy(*getMRI()), 0);
1573  return buildInstr(TargetOpcode::G_SUB, {Dst}, {Zero, Src0});
1574  }
1575 
1576  /// Build and insert \p Res = G_CTPOP \p Op0, \p Src0
1577  MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0) {
1578  return buildInstr(TargetOpcode::G_CTPOP, {Dst}, {Src0});
1579  }
1580 
1581  /// Build and insert \p Res = G_CTLZ \p Op0, \p Src0
1582  MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0) {
1583  return buildInstr(TargetOpcode::G_CTLZ, {Dst}, {Src0});
1584  }
1585 
1586  /// Build and insert \p Res = G_CTLZ_ZERO_UNDEF \p Op0, \p Src0
1588  return buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, {Dst}, {Src0});
1589  }
1590 
1591  /// Build and insert \p Res = G_CTTZ \p Op0, \p Src0
1592  MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0) {
1593  return buildInstr(TargetOpcode::G_CTTZ, {Dst}, {Src0});
1594  }
1595 
1596  /// Build and insert \p Res = G_CTTZ_ZERO_UNDEF \p Op0, \p Src0
1598  return buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, {Dst}, {Src0});
1599  }
1600 
1601  /// Build and insert \p Dst = G_BSWAP \p Src0
1602  MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0) {
1603  return buildInstr(TargetOpcode::G_BSWAP, {Dst}, {Src0});
1604  }
1605 
1606  /// Build and insert \p Res = G_FADD \p Op0, \p Op1
1607  MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0,
1608  const SrcOp &Src1,
1609  Optional<unsigned> Flags = None) {
1610  return buildInstr(TargetOpcode::G_FADD, {Dst}, {Src0, Src1}, Flags);
1611  }
1612 
1613  /// Build and insert \p Res = G_FSUB \p Op0, \p Op1
1614  MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0,
1615  const SrcOp &Src1,
1616  Optional<unsigned> Flags = None) {
1617  return buildInstr(TargetOpcode::G_FSUB, {Dst}, {Src0, Src1}, Flags);
1618  }
1619 
1620  /// Build and insert \p Res = G_FDIV \p Op0, \p Op1
1621  MachineInstrBuilder buildFDiv(const DstOp &Dst, const SrcOp &Src0,
1622  const SrcOp &Src1,
1623  Optional<unsigned> Flags = None) {
1624  return buildInstr(TargetOpcode::G_FDIV, {Dst}, {Src0, Src1}, Flags);
1625  }
1626 
1627  /// Build and insert \p Res = G_FMA \p Op0, \p Op1, \p Op2
1628  MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0,
1629  const SrcOp &Src1, const SrcOp &Src2,
1630  Optional<unsigned> Flags = None) {
1631  return buildInstr(TargetOpcode::G_FMA, {Dst}, {Src0, Src1, Src2}, Flags);
1632  }
1633 
1634  /// Build and insert \p Res = G_FMAD \p Op0, \p Op1, \p Op2
1635  MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0,
1636  const SrcOp &Src1, const SrcOp &Src2,
1637  Optional<unsigned> Flags = None) {
1638  return buildInstr(TargetOpcode::G_FMAD, {Dst}, {Src0, Src1, Src2}, Flags);
1639  }
1640 
1641  /// Build and insert \p Res = G_FNEG \p Op0
1642  MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0,
1643  Optional<unsigned> Flags = None) {
1644  return buildInstr(TargetOpcode::G_FNEG, {Dst}, {Src0}, Flags);
1645  }
1646 
1647  /// Build and insert \p Res = G_FABS \p Op0
1648  MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0,
1649  Optional<unsigned> Flags = None) {
1650  return buildInstr(TargetOpcode::G_FABS, {Dst}, {Src0}, Flags);
1651  }
1652 
1653  /// Build and insert \p Dst = G_FCANONICALIZE \p Src0
1655  Optional<unsigned> Flags = None) {
1656  return buildInstr(TargetOpcode::G_FCANONICALIZE, {Dst}, {Src0}, Flags);
1657  }
1658 
1659  /// Build and insert \p Dst = G_INTRINSIC_TRUNC \p Src0
1661  Optional<unsigned> Flags = None) {
1662  return buildInstr(TargetOpcode::G_INTRINSIC_TRUNC, {Dst}, {Src0}, Flags);
1663  }
1664 
1665  /// Build and insert \p Res = GFFLOOR \p Op0, \p Op1
1666  MachineInstrBuilder buildFFloor(const DstOp &Dst, const SrcOp &Src0,
1667  Optional<unsigned> Flags = None) {
1668  return buildInstr(TargetOpcode::G_FFLOOR, {Dst}, {Src0}, Flags);
1669  }
1670 
1671  /// Build and insert \p Dst = G_FLOG \p Src
1672  MachineInstrBuilder buildFLog(const DstOp &Dst, const SrcOp &Src,
1673  Optional<unsigned> Flags = None) {
1674  return buildInstr(TargetOpcode::G_FLOG, {Dst}, {Src}, Flags);
1675  }
1676 
1677  /// Build and insert \p Dst = G_FLOG2 \p Src
1678  MachineInstrBuilder buildFLog2(const DstOp &Dst, const SrcOp &Src,
1679  Optional<unsigned> Flags = None) {
1680  return buildInstr(TargetOpcode::G_FLOG2, {Dst}, {Src}, Flags);
1681  }
1682 
1683  /// Build and insert \p Dst = G_FEXP2 \p Src
1684  MachineInstrBuilder buildFExp2(const DstOp &Dst, const SrcOp &Src,
1685  Optional<unsigned> Flags = None) {
1686  return buildInstr(TargetOpcode::G_FEXP2, {Dst}, {Src}, Flags);
1687  }
1688 
1689  /// Build and insert \p Dst = G_FPOW \p Src0, \p Src1
1690  MachineInstrBuilder buildFPow(const DstOp &Dst, const SrcOp &Src0,
1691  const SrcOp &Src1,
1692  Optional<unsigned> Flags = None) {
1693  return buildInstr(TargetOpcode::G_FPOW, {Dst}, {Src0, Src1}, Flags);
1694  }
1695 
1696  /// Build and insert \p Res = G_FCOPYSIGN \p Op0, \p Op1
1698  const SrcOp &Src1) {
1699  return buildInstr(TargetOpcode::G_FCOPYSIGN, {Dst}, {Src0, Src1});
1700  }
1701 
1702  /// Build and insert \p Res = G_UITOFP \p Src0
1703  MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0) {
1704  return buildInstr(TargetOpcode::G_UITOFP, {Dst}, {Src0});
1705  }
1706 
1707  /// Build and insert \p Res = G_SITOFP \p Src0
1708  MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0) {
1709  return buildInstr(TargetOpcode::G_SITOFP, {Dst}, {Src0});
1710  }
1711 
1712  /// Build and insert \p Res = G_FPTOUI \p Src0
1713  MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0) {
1714  return buildInstr(TargetOpcode::G_FPTOUI, {Dst}, {Src0});
1715  }
1716 
1717  /// Build and insert \p Res = G_FPTOSI \p Src0
1718  MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0) {
1719  return buildInstr(TargetOpcode::G_FPTOSI, {Dst}, {Src0});
1720  }
1721 
1722  /// Build and insert \p Res = G_SMIN \p Op0, \p Op1
1723  MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0,
1724  const SrcOp &Src1) {
1725  return buildInstr(TargetOpcode::G_SMIN, {Dst}, {Src0, Src1});
1726  }
1727 
1728  /// Build and insert \p Res = G_SMAX \p Op0, \p Op1
1729  MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0,
1730  const SrcOp &Src1) {
1731  return buildInstr(TargetOpcode::G_SMAX, {Dst}, {Src0, Src1});
1732  }
1733 
1734  /// Build and insert \p Res = G_UMIN \p Op0, \p Op1
1735  MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0,
1736  const SrcOp &Src1) {
1737  return buildInstr(TargetOpcode::G_UMIN, {Dst}, {Src0, Src1});
1738  }
1739 
1740  /// Build and insert \p Res = G_UMAX \p Op0, \p Op1
1741  MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0,
1742  const SrcOp &Src1) {
1743  return buildInstr(TargetOpcode::G_UMAX, {Dst}, {Src0, Src1});
1744  }
1745 
1746  /// Build and insert \p Dst = G_ABS \p Src
1747  MachineInstrBuilder buildAbs(const DstOp &Dst, const SrcOp &Src) {
1748  return buildInstr(TargetOpcode::G_ABS, {Dst}, {Src});
1749  }
1750 
1751  /// Build and insert \p Res = G_JUMP_TABLE \p JTI
1752  ///
1753  /// G_JUMP_TABLE sets \p Res to the address of the jump table specified by
1754  /// the jump table index \p JTI.
1755  ///
1756  /// \return a MachineInstrBuilder for the newly created instruction.
1757  MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI);
1758 
1759  /// Build and insert \p Res = G_VECREDUCE_SEQ_FADD \p ScalarIn, \p VecIn
1760  ///
1761  /// \p ScalarIn is the scalar accumulator input to start the sequential
1762  /// reduction operation of \p VecIn.
1764  const SrcOp &ScalarIn,
1765  const SrcOp &VecIn) {
1766  return buildInstr(TargetOpcode::G_VECREDUCE_SEQ_FADD, {Dst},
1767  {ScalarIn, {VecIn}});
1768  }
1769 
1770  /// Build and insert \p Res = G_VECREDUCE_SEQ_FMUL \p ScalarIn, \p VecIn
1771  ///
1772  /// \p ScalarIn is the scalar accumulator input to start the sequential
1773  /// reduction operation of \p VecIn.
1775  const SrcOp &ScalarIn,
1776  const SrcOp &VecIn) {
1777  return buildInstr(TargetOpcode::G_VECREDUCE_SEQ_FMUL, {Dst},
1778  {ScalarIn, {VecIn}});
1779  }
1780 
1781  /// Build and insert \p Res = G_VECREDUCE_FADD \p Src
1782  ///
1783  /// \p ScalarIn is the scalar accumulator input to the reduction operation of
1784  /// \p VecIn.
1786  const SrcOp &ScalarIn,
1787  const SrcOp &VecIn) {
1788  return buildInstr(TargetOpcode::G_VECREDUCE_FADD, {Dst}, {ScalarIn, VecIn});
1789  }
1790 
1791  /// Build and insert \p Res = G_VECREDUCE_FMUL \p Src
1792  ///
1793  /// \p ScalarIn is the scalar accumulator input to the reduction operation of
1794  /// \p VecIn.
1796  const SrcOp &ScalarIn,
1797  const SrcOp &VecIn) {
1798  return buildInstr(TargetOpcode::G_VECREDUCE_FMUL, {Dst}, {ScalarIn, VecIn});
1799  }
1800 
1801  /// Build and insert \p Res = G_VECREDUCE_FMAX \p Src
1803  return buildInstr(TargetOpcode::G_VECREDUCE_FMAX, {Dst}, {Src});
1804  }
1805 
1806  /// Build and insert \p Res = G_VECREDUCE_FMIN \p Src
1808  return buildInstr(TargetOpcode::G_VECREDUCE_FMIN, {Dst}, {Src});
1809  }
1810  /// Build and insert \p Res = G_VECREDUCE_ADD \p Src
1812  return buildInstr(TargetOpcode::G_VECREDUCE_ADD, {Dst}, {Src});
1813  }
1814 
1815  /// Build and insert \p Res = G_VECREDUCE_MUL \p Src
1817  return buildInstr(TargetOpcode::G_VECREDUCE_MUL, {Dst}, {Src});
1818  }
1819 
1820  /// Build and insert \p Res = G_VECREDUCE_AND \p Src
1822  return buildInstr(TargetOpcode::G_VECREDUCE_AND, {Dst}, {Src});
1823  }
1824 
1825  /// Build and insert \p Res = G_VECREDUCE_OR \p Src
1827  return buildInstr(TargetOpcode::G_VECREDUCE_OR, {Dst}, {Src});
1828  }
1829 
1830  /// Build and insert \p Res = G_VECREDUCE_XOR \p Src
1832  return buildInstr(TargetOpcode::G_VECREDUCE_XOR, {Dst}, {Src});
1833  }
1834 
1835  /// Build and insert \p Res = G_VECREDUCE_SMAX \p Src
1837  return buildInstr(TargetOpcode::G_VECREDUCE_SMAX, {Dst}, {Src});
1838  }
1839 
1840  /// Build and insert \p Res = G_VECREDUCE_SMIN \p Src
1842  return buildInstr(TargetOpcode::G_VECREDUCE_SMIN, {Dst}, {Src});
1843  }
1844 
1845  /// Build and insert \p Res = G_VECREDUCE_UMAX \p Src
1847  return buildInstr(TargetOpcode::G_VECREDUCE_UMAX, {Dst}, {Src});
1848  }
1849 
1850  /// Build and insert \p Res = G_VECREDUCE_UMIN \p Src
1852  return buildInstr(TargetOpcode::G_VECREDUCE_UMIN, {Dst}, {Src});
1853  }
1854 
1855  /// Build and insert G_MEMCPY or G_MEMMOVE
1856  MachineInstrBuilder buildMemTransferInst(unsigned Opcode, const SrcOp &DstPtr,
1857  const SrcOp &SrcPtr,
1858  const SrcOp &Size,
1859  MachineMemOperand &DstMMO,
1860  MachineMemOperand &SrcMMO) {
1861  auto MIB = buildInstr(
1862  Opcode, {}, {DstPtr, SrcPtr, Size, SrcOp(INT64_C(0) /*isTailCall*/)});
1863  MIB.addMemOperand(&DstMMO);
1864  MIB.addMemOperand(&SrcMMO);
1865  return MIB;
1866  }
1867 
1868  MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr,
1869  const SrcOp &Size, MachineMemOperand &DstMMO,
1870  MachineMemOperand &SrcMMO) {
1871  return buildMemTransferInst(TargetOpcode::G_MEMCPY, DstPtr, SrcPtr, Size,
1872  DstMMO, SrcMMO);
1873  }
1874 
1875  /// Build and insert \p Dst = G_SBFX \p Src, \p LSB, \p Width.
1876  MachineInstrBuilder buildSbfx(const DstOp &Dst, const SrcOp &Src,
1877  const SrcOp &LSB, const SrcOp &Width) {
1878  return buildInstr(TargetOpcode::G_SBFX, {Dst}, {Src, LSB, Width});
1879  }
1880 
1881  /// Build and insert \p Dst = G_UBFX \p Src, \p LSB, \p Width.
1882  MachineInstrBuilder buildUbfx(const DstOp &Dst, const SrcOp &Src,
1883  const SrcOp &LSB, const SrcOp &Width) {
1884  return buildInstr(TargetOpcode::G_UBFX, {Dst}, {Src, LSB, Width});
1885  }
1886 
1887  /// Build and insert \p Dst = G_ROTR \p Src, \p Amt
1889  const SrcOp &Amt) {
1890  return buildInstr(TargetOpcode::G_ROTR, {Dst}, {Src, Amt});
1891  }
1892 
1893  /// Build and insert \p Dst = G_ROTL \p Src, \p Amt
1895  const SrcOp &Amt) {
1896  return buildInstr(TargetOpcode::G_ROTL, {Dst}, {Src, Amt});
1897  }
1898 
1899  /// Build and insert \p Dst = G_BITREVERSE \p Src
1901  return buildInstr(TargetOpcode::G_BITREVERSE, {Dst}, {Src});
1902  }
1903 
1904  virtual MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
1905  ArrayRef<SrcOp> SrcOps,
1906  Optional<unsigned> Flags = None);
1907 };
1908 
1909 } // End namespace llvm.
1910 #endif // LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::MachineIRBuilder::buildUSubo
MachineInstrBuilder buildUSubo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_USUBO Op0, Op1.
Definition: MachineIRBuilder.h:546
llvm::MachineIRBuilder::setMF
void setMF(MachineFunction &MF)
Definition: MachineIRBuilder.cpp:26
llvm::MachineIRBuilder::buildInsertVectorElement
MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
Definition: MachineIRBuilder.cpp:814
LowLevelType.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::MachineIRBuilder::buildGlobalValue
MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
Definition: MachineIRBuilder.cpp:146
Reg
unsigned Reg
Definition: MachineSink.cpp:1563
llvm::DstOp::DstType::Ty_LLT
@ Ty_LLT
llvm::MachineIRBuilder::buildOr
MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_OR Op0, Op1.
Definition: MachineIRBuilder.h:1548
llvm::MachineIRBuilder::buildFMul
MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1474
llvm::MachineIRBuilder::buildAtomicRMW
MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:877
llvm::MachineIRBuilder::setDebugLoc
void setDebugLoc(const DebugLoc &DL)
Set the debug location to DL for all the next build instructions.
Definition: MachineIRBuilder.h:355
llvm::MachineIRBuilder::buildIntToPtr
MachineInstrBuilder buildIntToPtr(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_INTTOPTR instruction.
Definition: MachineIRBuilder.h:656
llvm::MachineIRBuilder::buildICmp
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
Definition: MachineIRBuilder.cpp:788
llvm::MachineIRBuilder::buildSMax
MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMAX Op0, Op1.
Definition: MachineIRBuilder.h:1729
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:721
llvm::MachineIRBuilderState::II
MachineBasicBlock::iterator II
Definition: MachineIRBuilder.h:50
llvm::MachineIRBuilder::buildAShr
MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1516
llvm::MachineIRBuilder::buildFSub
MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_FSUB Op0, Op1.
Definition: MachineIRBuilder.h:1614
llvm::MachineIRBuilder::buildUSube
MachineInstrBuilder buildUSube(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_USUBE Op0, Op1, CarryInp.
Definition: MachineIRBuilder.h:585
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineIRBuilder::buildSMulH
MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1461
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::MachineIRBuilder::buildSbfx
MachineInstrBuilder buildSbfx(const DstOp &Dst, const SrcOp &Src, const SrcOp &LSB, const SrcOp &Width)
Build and insert Dst = G_SBFX Src, LSB, Width.
Definition: MachineIRBuilder.h:1876
llvm::MachineIRBuilder::getCSEInfo
GISelCSEInfo * getCSEInfo()
Definition: MachineIRBuilder.h:297
llvm::MachineIRBuilder::buildUMulH
MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1455
llvm::MachineIRBuilder::buildBSwap
MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0)
Build and insert Dst = G_BSWAP Src0.
Definition: MachineIRBuilder.h:1602
llvm::MachineIRBuilder::buildSplatVector
MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Src)
Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.
Definition: MachineIRBuilder.cpp:681
llvm::MachineIRBuilder::getMRI
MachineRegisterInfo * getMRI()
Getter for MRI.
Definition: MachineIRBuilder.h:280
llvm::MachineIRBuilder::buildZExtInReg
MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and inserts Res = G_AND Op, LowBitsSet(ImmOp) Since there is no G_ZEXT_INREG like G_SEXT_INREG,...
Definition: MachineIRBuilder.cpp:529
llvm::DstOp::RC
const TargetRegisterClass * RC
Definition: MachineIRBuilder.h:62
llvm::MachineIRBuilder::buildAtomicRMWOr
MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:931
llvm::MachineIRBuilder::buildFCanonicalize
MachineInstrBuilder buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
Build and insert Dst = G_FCANONICALIZE Src0.
Definition: MachineIRBuilder.h:1654
llvm::GISelCSEInfo
The CSE Analysis object.
Definition: CSEInfo.h:69
llvm::MachineIRBuilder::buildNeg
MachineInstrBuilder buildNeg(const DstOp &Dst, const SrcOp &Src0)
Build and insert integer negation Zero = G_CONSTANT 0 Res = G_SUB Zero, Op0.
Definition: MachineIRBuilder.h:1571
llvm::MachineIRBuilder::buildFAbs
MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
Build and insert Res = G_FABS Op0.
Definition: MachineIRBuilder.h:1648
llvm::MachineIRBuilder::MachineIRBuilder
MachineIRBuilder(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt)
Definition: MachineIRBuilder.h:236
llvm::MachineIRBuilder::buildZExtOrTrunc
MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
Definition: MachineIRBuilder.cpp:519
MachineBasicBlock.h
llvm::MachineIRBuilder::buildUMin
MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMIN Op0, Op1.
Definition: MachineIRBuilder.h:1735
llvm::AAMDNodes
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:651
llvm::MachineIRBuilder::buildAtomicRMWAdd
MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:908
llvm::MachineIRBuilder::buildAtomicCmpXchg
MachineInstrBuilder buildAtomicCmpXchg(Register OldValRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO.
Definition: MachineIRBuilder.cpp:853
llvm::MachineIRBuilder::buildDbgLabel
MachineInstrBuilder buildDbgLabel(const MDNode *Label)
Build and insert a DBG_LABEL instructions specifying that Label is given.
Definition: MachineIRBuilder.cpp:117
Module.h
llvm::MachineIRBuilder::buildFMAD
MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, Optional< unsigned > Flags=None)
Build and insert Res = G_FMAD Op0, Op1, Op2.
Definition: MachineIRBuilder.h:1635
llvm::SrcOp::Reg
Register Reg
Definition: MachineIRBuilder.h:122
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
llvm::MachineIRBuilder::MachineIRBuilder
MachineIRBuilder()=default
Some constructors for easy use.
llvm::MachineIRBuilder::getDL
const DebugLoc & getDL()
Getter for DebugLoc.
Definition: MachineIRBuilder.h:277
llvm::MachineIRBuilder::buildFPTrunc
MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op, Optional< unsigned > Flags=None)
Build and insert Res = G_FPTRUNC Op.
Definition: MachineIRBuilder.cpp:782
llvm::MachineIRBuilder::buildVecReduceAdd
MachineInstrBuilder buildVecReduceAdd(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_ADD Src.
Definition: MachineIRBuilder.h:1811
llvm::SrcOp::Imm
int64_t Imm
Definition: MachineIRBuilder.h:124
llvm::MachineIRBuilder::buildCTTZ
MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ Op0, Src0.
Definition: MachineIRBuilder.h:1592
llvm::Optional
Definition: APInt.h:33
T
#define T
Definition: Mips16ISelLowering.cpp:341
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:80
llvm::MachineIRBuilder::buildBuildVector
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
Definition: MachineIRBuilder.cpp:672
llvm::MachineIRBuilder::getMF
const MachineFunction & getMF() const
Definition: MachineIRBuilder.h:267
llvm::MachineIRBuilder::buildInstrNoInsert
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.cpp:40
llvm::MachineIRBuilder::setInstr
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
Definition: MachineIRBuilder.h:333
llvm::DstOp::DstOp
DstOp(const TargetRegisterClass *TRC)
Definition: MachineIRBuilder.h:71
llvm::MachineIRBuilder::buildExtOrTrunc
MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, const SrcOp &Op)
Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of...
Definition: MachineIRBuilder.cpp:490
llvm::MachineIRBuilderState::MBB
MachineBasicBlock * MBB
Definition: MachineIRBuilder.h:49
llvm::MachineIRBuilder::buildVecReduceFMin
MachineInstrBuilder buildVecReduceFMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_FMIN Src.
Definition: MachineIRBuilder.h:1807
llvm::MachineIRBuilder::buildPtrMask
MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTRMASK Op0, Op1.
Definition: MachineIRBuilder.h:479
llvm::MachineIRBuilder::buildXor
MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_XOR Op0, Op1.
Definition: MachineIRBuilder.h:1555
llvm::MachineIRBuilder::buildAtomicRMWFSub
MachineInstrBuilder buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FSUB Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:978
llvm::MachineIRBuilder::buildFence
MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope)
Build and insert G_FENCE Ordering, Scope.
Definition: MachineIRBuilder.cpp:985
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MachineIRBuilder::buildFCopysign
MachineInstrBuilder buildFCopysign(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_FCOPYSIGN Op0, Op1.
Definition: MachineIRBuilder.h:1697
llvm::SrcOp::SrcType::Ty_Predicate
@ Ty_Predicate
llvm::MachineIRBuilder::buildDynStackAlloc
MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size, Align Alignment)
Build and insert Res = G_DYN_STACKALLOC Size, Align.
Definition: MachineIRBuilder.cpp:126
llvm::MachineIRBuilder::getDebugLoc
const DebugLoc & getDebugLoc()
Get the current instruction's debug location.
Definition: MachineIRBuilder.h:358
llvm::MachineIRBuilder::getCSEInfo
const GISelCSEInfo * getCSEInfo() const
Definition: MachineIRBuilder.h:298
llvm::MachineIRBuilder::validateSelectOp
void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty, const LLT Op1Ty)
Definition: MachineIRBuilder.cpp:1019
llvm::MachineIRBuilderState
Class which stores all the state required in a MachineIRBuilder.
Definition: MachineIRBuilder.h:37
llvm::MachineIRBuilder::buildConstant
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
Definition: MachineIRBuilder.cpp:297
llvm::MachineIRBuilder::buildURem
MachineInstrBuilder buildURem(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_UREM Op0, Op1.
Definition: MachineIRBuilder.h:1468
llvm::MachineIRBuilder::validateBinaryOp
void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1)
Definition: MachineIRBuilder.cpp:170
MachineRegisterInfo.h
llvm::MachineIRBuilder::buildCTLZ_ZERO_UNDEF
MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ_ZERO_UNDEF Op0, Src0.
Definition: MachineIRBuilder.h:1587
llvm::DstOp::getRegClass
const TargetRegisterClass * getRegClass() const
Definition: MachineIRBuilder.h:104
CSEInfo.h
llvm::DstOp::DstOp
DstOp(const LLT T)
Definition: MachineIRBuilder.h:70
llvm::MachineIRBuilder::buildBitReverse
MachineInstrBuilder buildBitReverse(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITREVERSE Src.
Definition: MachineIRBuilder.h:1900
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:116
llvm::MachineIRBuilder::setCSEInfo
void setCSEInfo(GISelCSEInfo *Info)
Definition: MachineIRBuilder.h:315
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::MachineIRBuilder::getMRI
const MachineRegisterInfo * getMRI() const
Definition: MachineIRBuilder.h:281
llvm::MachineIRBuilder::buildAtomicCmpXchgWithSuccess
MachineInstrBuilder buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr,...
Definition: MachineIRBuilder.cpp:825
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::MachineIRBuilder::buildUnmerge
MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)
Build and insert Res0, ...
Definition: MachineIRBuilder.cpp:645
llvm::MachineIRBuilder::buildAtomicRMWMin
MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:951
llvm::MachineIRBuilder::buildZExt
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
Definition: MachineIRBuilder.cpp:466
llvm::MachineIRBuilder::buildExtractVectorElement
MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
Definition: MachineIRBuilder.cpp:820
llvm::MachineIRBuilder::buildLoad
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
Definition: MachineIRBuilder.h:860
llvm::MachineIRBuilder::MachineIRBuilder
MachineIRBuilder(const MachineIRBuilderState &BState)
Definition: MachineIRBuilder.h:254
Constants.h
llvm::MachineIRBuilder::buildShl
MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1504
llvm::MachineIRBuilder::setMBB
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
Definition: MachineIRBuilder.h:324
llvm::DstOp::LLTTy
LLT LLTTy
Definition: MachineIRBuilder.h:60
llvm::DstOp::addDefToMIB
void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const
Definition: MachineIRBuilder.h:73
llvm::MachineIRBuilder::buildSAdde
MachineInstrBuilder buildSAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_SADDE Op0, Op1, CarryInp.
Definition: MachineIRBuilder.h:593
llvm::DstOp::DstType::Ty_RC
@ Ty_RC
llvm::DstOp::getReg
Register getReg() const
Definition: MachineIRBuilder.h:99
llvm::MachineIRBuilder::buildFLog
MachineInstrBuilder buildFLog(const DstOp &Dst, const SrcOp &Src, Optional< unsigned > Flags=None)
Build and insert Dst = G_FLOG Src.
Definition: MachineIRBuilder.h:1672
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineIRBuilder::buildBoolExt
MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op, bool IsFP)
Definition: MachineIRBuilder.cpp:483
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
llvm::MachineIRBuilder::buildPtrToInt
MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_PTRTOINT instruction.
Definition: MachineIRBuilder.h:651
llvm::MachineIRBuilder::recordInsertion
void recordInsertion(MachineInstr *InsertedInstr) const
Definition: MachineIRBuilder.h:226
llvm::MachineIRBuilder::buildAnyExtOrTrunc
MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Res = COPY Op depending on the differing sizes of Res and Op.
Definition: MachineIRBuilder.cpp:524
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::MachineIRBuilder::buildFCmp
MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, Optional< unsigned > Flags=None)
Build and insert a Res = G_FCMP PredOp0, Op1.
Definition: MachineIRBuilder.cpp:795
llvm::MachineIRBuilder::buildFIDbgValue
MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in th...
Definition: MachineIRBuilder.cpp:77
llvm::MachineIRBuilder::buildCTLZ
MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTLZ Op0, Src0.
Definition: MachineIRBuilder.h:1582
TargetOpcodes.h
llvm::MachineIRBuilder::buildConcatVectors
MachineInstrBuilder buildConcatVectors(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_CONCAT_VECTORS Op0, ...
Definition: MachineIRBuilder.cpp:729
llvm::MachineIRBuilder::getDataLayout
const DataLayout & getDataLayout() const
Definition: MachineIRBuilder.h:272
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineIRBuilder::MachineIRBuilder
MachineIRBuilder(MachineFunction &MF)
Definition: MachineIRBuilder.h:234
llvm::DstOp::getDstOpKind
DstType getDstOpKind() const
Definition: MachineIRBuilder.h:113
llvm::MachineIRBuilder::buildAtomicRMWAnd
MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:920
llvm::MachineIRBuilder::getMF
MachineFunction & getMF()
Getter for the function we currently build.
Definition: MachineIRBuilder.h:262
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
llvm::MachineIRBuilder::buildFFloor
MachineInstrBuilder buildFFloor(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
Build and insert Res = GFFLOOR Op0, Op1.
Definition: MachineIRBuilder.h:1666
DebugLoc.h
llvm::MachineIRBuilder::buildAnd
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
Definition: MachineIRBuilder.h:1533
llvm::MachineIRBuilder::getMBB
MachineBasicBlock & getMBB()
Definition: MachineIRBuilder.h:292
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MachineIRBuilder::buildSMin
MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_SMIN Op0, Op1.
Definition: MachineIRBuilder.h:1723
llvm::DstOp::DstOp
DstOp(Register R)
Definition: MachineIRBuilder.h:68
llvm::MachineIRBuilder::buildVecReduceOr
MachineInstrBuilder buildVecReduceOr(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_OR Src.
Definition: MachineIRBuilder.h:1826
llvm::MachineIRBuilder::buildIndirectDbgValue
MachineInstrBuilder buildIndirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...
Definition: MachineIRBuilder.cpp:65
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MachineIRBuilder::buildBrCond
MachineInstrBuilder buildBrCond(const SrcOp &Tst, MachineBasicBlock &Dest)
Build and insert G_BRCOND Tst, Dest.
Definition: MachineIRBuilder.cpp:374
llvm::MachineIRBuilder::buildLoadInstr
MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = <opcode> Addr, MMO.
Definition: MachineIRBuilder.cpp:398
llvm::DstOp::DstOp
DstOp(unsigned R)
Definition: MachineIRBuilder.h:67
llvm::None
const NoneType None
Definition: None.h:23
llvm::MachineIRBuilder::buildAtomicRMWMax
MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:945
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineIRBuilder::buildBrIndirect
MachineInstrBuilder buildBrIndirect(Register Tgt)
Build and insert G_BRINDIRECT Tgt.
Definition: MachineIRBuilder.cpp:264
llvm::MachineIRBuilder::buildVecReduceFMul
MachineInstrBuilder buildVecReduceFMul(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_FMUL Src.
Definition: MachineIRBuilder.h:1795
llvm::MachineIRBuilder::validateUnaryOp
void validateUnaryOp(const LLT Res, const LLT Op0)
Definition: MachineIRBuilder.cpp:165
llvm::MachineIRBuilder::buildFNeg
MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
Build and insert Res = G_FNEG Op0.
Definition: MachineIRBuilder.h:1642
llvm::MachineIRBuilder::buildCTPOP
MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTPOP Op0, Src0.
Definition: MachineIRBuilder.h:1577
llvm::SrcOp::getImm
int64_t getImm() const
Definition: MachineIRBuilder.h:193
llvm::MachineIRBuilder::buildVecReduceXor
MachineInstrBuilder buildVecReduceXor(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_XOR Src.
Definition: MachineIRBuilder.h:1831
llvm::SrcOp::SrcOp
SrcOp(const MachineOperand &Op)
Definition: MachineIRBuilder.h:130
llvm::MachineIRBuilder::buildBr
MachineInstrBuilder buildBr(MachineBasicBlock &Dest)
Build and insert G_BR Dest.
Definition: MachineIRBuilder.cpp:260
llvm::MachineIRBuilder::buildMaskLowPtrBits
MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0, uint32_t NumBits)
Build and insert Res = G_PTRMASK Op0, G_CONSTANT (1 << NumBits) - 1.
Definition: MachineIRBuilder.cpp:208
llvm::APFloat
Definition: APFloat.h:701
llvm::MachineIRBuilder::buildAbs
MachineInstrBuilder buildAbs(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_ABS Src.
Definition: MachineIRBuilder.h:1747
llvm::MachineIRBuilder::buildFAdd
MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_FADD Op0, Op1.
Definition: MachineIRBuilder.h:1607
llvm::MachineIRBuilder::buildFMinNum
MachineInstrBuilder buildFMinNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1480
llvm::SrcOp::SrcOp
SrcOp(Register R)
Definition: MachineIRBuilder.h:129
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MachineIRBuilder::buildFConstant
virtual MachineInstrBuilder buildFConstant(const DstOp &Res, const ConstantFP &Val)
Build and insert Res = G_FCONSTANT Val.
Definition: MachineIRBuilder.cpp:326
llvm::MachineIRBuilder::buildUbfx
MachineInstrBuilder buildUbfx(const DstOp &Dst, const SrcOp &Src, const SrcOp &LSB, const SrcOp &Width)
Build and insert Dst = G_UBFX Src, LSB, Width.
Definition: MachineIRBuilder.h:1882
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::MachineIRBuilder::buildBrJT
MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI, Register IndexReg)
Build and insert G_BRJT TablePtr, JTI, IndexReg.
Definition: MachineIRBuilder.cpp:269
llvm::MachineIRBuilder::buildSExtOrTrunc
MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
Definition: MachineIRBuilder.cpp:514
llvm::MachineIRBuilder::setInsertPt
void setInsertPt(MachineBasicBlock &MBB, MachineBasicBlock::iterator II)
Set the insertion point before the specified position.
Definition: MachineIRBuilder.h:306
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:212
llvm::DstOp::Reg
Register Reg
Definition: MachineIRBuilder.h:61
Index
uint32_t Index
Definition: ELFObjHandler.cpp:83
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::MachineIRBuilder::buildAssertSExt
MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_SEXT Op, Size.
Definition: MachineIRBuilder.cpp:285
uint64_t
llvm::SrcOp::SrcType
SrcType
Definition: MachineIRBuilder.h:128
llvm::GlobalValue::getParent
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:578
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:79
llvm::MachineIRBuilder::buildAssertZExt
MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_ZEXT Op, Size.
Definition: MachineIRBuilder.cpp:291
llvm::MachineIRBuilder::buildUMax
MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_UMAX Op0, Op1.
Definition: MachineIRBuilder.h:1741
llvm::MachineIRBuilder::buildBitcast
MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITCAST Src.
Definition: MachineIRBuilder.h:661
llvm::MachineIRBuilder::buildMul
MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_MUL Op0, Op1.
Definition: MachineIRBuilder.h:1449
llvm::SrcOp::SrcType::Ty_Reg
@ Ty_Reg
llvm::MachineIRBuilder::getInsertPt
MachineBasicBlock::iterator getInsertPt()
Current insertion point for new instructions.
Definition: MachineIRBuilder.h:301
llvm::MachineIRBuilder::buildIntrinsicTrunc
MachineInstrBuilder buildIntrinsicTrunc(const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
Build and insert Dst = G_INTRINSIC_TRUNC Src0.
Definition: MachineIRBuilder.h:1660
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
llvm::MachineIRBuilder::setInstrAndDebugLoc
void setInstrAndDebugLoc(MachineInstr &MI)
Set the insertion point to before MI, and set the debug loc to MI's loc.
Definition: MachineIRBuilder.h:342
llvm::MachineIRBuilder::buildPtrAdd
MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTR_ADD Op0, Op1.
Definition: MachineIRBuilder.cpp:182
llvm::MachineIRBuilder::buildRotateLeft
MachineInstrBuilder buildRotateLeft(const DstOp &Dst, const SrcOp &Src, const SrcOp &Amt)
Build and insert Dst = G_ROTL Src, Amt.
Definition: MachineIRBuilder.h:1894
llvm::MachineIRBuilder::buildFPTOSI
MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOSI Src0.
Definition: MachineIRBuilder.h:1718
llvm::MachineIRBuilder::buildAtomicRMWNand
MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:926
llvm::MachineIRBuilder::buildSelect
MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1, Optional< unsigned > Flags=None)
Build and insert a Res = G_SELECT Tst, Op0, Op1.
Definition: MachineIRBuilder.cpp:804
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:131
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineIRBuilder::buildConstDbgValue
MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...
Definition: MachineIRBuilder.cpp:92
llvm::MachineIRBuilder::buildMemTransferInst
MachineInstrBuilder buildMemTransferInst(unsigned Opcode, const SrcOp &DstPtr, const SrcOp &SrcPtr, const SrcOp &Size, MachineMemOperand &DstMMO, MachineMemOperand &SrcMMO)
Build and insert G_MEMCPY or G_MEMMOVE.
Definition: MachineIRBuilder.h:1856
llvm::MachineIRBuilder::getMBB
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
Definition: MachineIRBuilder.h:287
llvm::MachineInstrBuilder::addMemOperand
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Definition: MachineInstrBuilder.h:202
llvm::MachineIRBuilder::MachineIRBuilder
MachineIRBuilder(MachineInstr &MI)
Definition: MachineIRBuilder.h:241
llvm::SrcOp::getSrcOpKind
SrcType getSrcOpKind() const
Definition: MachineIRBuilder.h:202
llvm::MachineIRBuilder::MachineIRBuilder
MachineIRBuilder(MachineInstr &MI, GISelChangeObserver &Observer)
Definition: MachineIRBuilder.h:247
llvm::MachineIRBuilder::buildFMaxNumIEEE
MachineInstrBuilder buildFMaxNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1498
llvm::MachineIRBuilder::buildUAddo
MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_UADDO Op0, Op1.
Definition: MachineIRBuilder.h:540
llvm::MachineInstrBuilder::addUse
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Definition: MachineInstrBuilder.h:123
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::MachineIRBuilder::buildAtomicRMWFAdd
MachineInstrBuilder buildAtomicRMWFAdd(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_FADD Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:970
llvm::MDNode
Metadata node.
Definition: Metadata.h:906
llvm::SrcOp::SrcOp
SrcOp(uint64_t V)
Definition: MachineIRBuilder.h:138
llvm::SrcOp::Pred
CmpInst::Predicate Pred
Definition: MachineIRBuilder.h:123
llvm::MachineIRBuilder::buildFMA
MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2, Optional< unsigned > Flags=None)
Build and insert Res = G_FMA Op0, Op1, Op2.
Definition: MachineIRBuilder.h:1628
llvm::GISelChangeObserver::createdInstr
virtual void createdInstr(MachineInstr &MI)=0
An instruction has been created and inserted into the function.
llvm::MachineIRBuilder::setChangeObserver
void setChangeObserver(GISelChangeObserver &Observer)
Definition: MachineIRBuilder.h:347
llvm::MachineIRBuilder::buildVecReduceFMax
MachineInstrBuilder buildVecReduceFMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_FMAX Src.
Definition: MachineIRBuilder.h:1802
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::MachineIRBuilder::buildVecReduceSMax
MachineInstrBuilder buildVecReduceSMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_SMAX Src.
Definition: MachineIRBuilder.h:1836
llvm::MachineIRBuilderState::Observer
GISelChangeObserver * Observer
Definition: MachineIRBuilder.h:53
llvm::MachineIRBuilder::buildInstr
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.h:367
llvm::BlockAddress
The address of a basic block.
Definition: Constants.h:848
llvm::SrcOp::addSrcToMIB
void addSrcToMIB(MachineInstrBuilder &MIB) const
Definition: MachineIRBuilder.h:141
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MachineIRBuilder::buildVecReduceFAdd
MachineInstrBuilder buildVecReduceFAdd(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_FADD Src.
Definition: MachineIRBuilder.h:1785
llvm::SrcOp::getReg
Register getReg() const
Definition: MachineIRBuilder.h:171
llvm::MachineIRBuilder::insertInstr
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Definition: MachineIRBuilder.cpp:45
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::MachineIRBuilder::buildCopy
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
Definition: MachineIRBuilder.cpp:280
llvm::MachineIRBuilder::buildFPTOUI
MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_FPTOUI Src0.
Definition: MachineIRBuilder.h:1713
llvm::MachineIRBuilder::buildFPExt
MachineInstrBuilder buildFPExt(const DstOp &Res, const SrcOp &Op, Optional< unsigned > Flags=None)
Build and insert Res = G_FPEXT Op.
Definition: MachineIRBuilder.h:644
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:870
uint32_t
llvm::SrcOp::SrcOp
SrcOp(const CmpInst::Predicate P)
Definition: MachineIRBuilder.h:132
llvm::MachineIRBuilder::buildSequence
void buildSequence(Register Res, ArrayRef< Register > Ops, ArrayRef< uint64_t > Indices)
Build and insert instructions to put Ops together at the specified p Indices to form a larger registe...
Definition: MachineIRBuilder.cpp:583
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachineIRBuilder::buildInsert
MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src, const SrcOp &Op, unsigned Index)
Definition: MachineIRBuilder.cpp:737
llvm::DstOp::DstOp
DstOp(const MachineOperand &Op)
Definition: MachineIRBuilder.h:69
llvm::MachineIRBuilder::buildFLog2
MachineInstrBuilder buildFLog2(const DstOp &Dst, const SrcOp &Src, Optional< unsigned > Flags=None)
Build and insert Dst = G_FLOG2 Src.
Definition: MachineIRBuilder.h:1678
llvm::MachineIRBuilderState::TII
const TargetInstrInfo * TII
Information used to access the description of the opcodes.
Definition: MachineIRBuilder.h:41
llvm::MachineIRBuilder::buildExtract
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert Res0, ...
Definition: MachineIRBuilder.cpp:558
llvm::MachineInstrBuilder::addPredicate
const MachineInstrBuilder & addPredicate(CmpInst::Predicate Pred) const
Definition: MachineInstrBuilder.h:257
llvm::MachineIRBuilder::buildVecReduceUMax
MachineInstrBuilder buildVecReduceUMax(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_UMAX Src.
Definition: MachineIRBuilder.h:1846
llvm::GISelChangeObserver
Abstract class that contains various methods for clients to notify about changes.
Definition: GISelChangeObserver.h:29
llvm::MachineIRBuilder::buildSExtInReg
MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)
Build and insert Res = G_SEXT_INREG Op, ImmOp.
Definition: MachineIRBuilder.h:639
llvm::MachineIRBuilder::buildNot
MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0)
Build and insert a bitwise not, NegOne = G_CONSTANT -1 Res = G_OR Op0, NegOne.
Definition: MachineIRBuilder.h:1563
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MachineIRBuilder::buildAnyExt
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
Definition: MachineIRBuilder.cpp:456
llvm::MachineIRBuilder::materializePtrAdd
Optional< MachineInstrBuilder > materializePtrAdd(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value)
Materialize and insert Res = G_PTR_ADD Op0, (G_CONSTANT Value)
Definition: MachineIRBuilder.cpp:193
llvm::MachineIRBuilder::buildJumpTable
MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI)
Build and insert Res = G_JUMP_TABLE JTI.
Definition: MachineIRBuilder.cpp:159
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::DstOp::DstType
DstType
Definition: MachineIRBuilder.h:66
llvm::MachineIRBuilder::buildFrameIndex
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
Definition: MachineIRBuilder.cpp:137
llvm::SrcOp::SrcMIB
MachineInstrBuilder SrcMIB
Definition: MachineIRBuilder.h:121
llvm::MachineIRBuilder::buildSSube
MachineInstrBuilder buildSSube(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_SSUBE Op0, Op1, CarryInp.
Definition: MachineIRBuilder.h:601
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachineIRBuilder::buildUAdde
MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
Build and insert Res, CarryOut = G_UADDE Op0, Op1, CarryIn.
Definition: MachineIRBuilder.h:577
llvm::MachineIRBuilder::buildUITOFP
MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_UITOFP Src0.
Definition: MachineIRBuilder.h:1703
llvm::MachineIRBuilder::buildVecReduceSeqFAdd
MachineInstrBuilder buildVecReduceSeqFAdd(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_SEQ_FADD ScalarIn, VecIn.
Definition: MachineIRBuilder.h:1763
llvm::MachineIRBuilder::buildVecReduceAnd
MachineInstrBuilder buildVecReduceAnd(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_AND Src.
Definition: MachineIRBuilder.h:1821
llvm::MachineIRBuilder::buildSAddo
MachineInstrBuilder buildSAddo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_SADDO Op0, Op1.
Definition: MachineIRBuilder.h:552
llvm::SrcOp::SrcType::Ty_Imm
@ Ty_Imm
llvm::MachineIRBuilder::buildFPow
MachineInstrBuilder buildFPow(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Dst = G_FPOW Src0, Src1.
Definition: MachineIRBuilder.h:1690
llvm::MachineIRBuilder::buildTrunc
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
Definition: MachineIRBuilder.cpp:777
llvm::MachineIRBuilder::buildMemCpy
MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr, const SrcOp &Size, MachineMemOperand &DstMMO, MachineMemOperand &SrcMMO)
Definition: MachineIRBuilder.h:1868
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:607
llvm::MachineIRBuilder::~MachineIRBuilder
virtual ~MachineIRBuilder()=default
llvm::MachineIRBuilder::buildVecReduceMul
MachineInstrBuilder buildVecReduceMul(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_MUL Src.
Definition: MachineIRBuilder.h:1816
llvm::MachineIRBuilderState::DL
DebugLoc DL
Debug location to be set to any instruction we create.
Definition: MachineIRBuilder.h:45
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:325
llvm::MachineIRBuilder::buildSITOFP
MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_SITOFP Src0.
Definition: MachineIRBuilder.h:1708
llvm::MachineIRBuilder::buildUndef
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
Definition: MachineIRBuilder.cpp:624
llvm::MachineIRBuilder::buildDirectDbgValue
MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...
Definition: MachineIRBuilder.cpp:52
llvm::MachineIRBuilder::buildVecReduceUMin
MachineInstrBuilder buildVecReduceUMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_UMIN Src.
Definition: MachineIRBuilder.h:1851
llvm::MachineIRBuilder::buildAtomicRMWUmin
MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:963
llvm::MachineIRBuilder::buildShuffleVector
MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1, const SrcOp &Src2, ArrayRef< int > Mask)
Build and insert Res = G_SHUFFLE_VECTOR Src1, Src2, Mask.
Definition: MachineIRBuilder.cpp:709
llvm::SrcOp::SrcOp
SrcOp(int64_t V)
Definition: MachineIRBuilder.h:139
llvm::MachineIRBuilder::buildAtomicRMWXor
MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:939
llvm::MachineIRBuilder::buildPadVectorWithUndefElements
MachineInstrBuilder buildPadVectorWithUndefElements(const DstOp &Res, const SrcOp &Op0)
Build and insert a, b, ..., x = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a, b, .....
Definition: MachineIRBuilder.cpp:219
llvm::MachineIRBuilder::getTII
const TargetInstrInfo & getTII()
Definition: MachineIRBuilder.h:256
llvm::MachineIRBuilder::buildRotateRight
MachineInstrBuilder buildRotateRight(const DstOp &Dst, const SrcOp &Src, const SrcOp &Amt)
Build and insert Dst = G_ROTR Src, Amt.
Definition: MachineIRBuilder.h:1888
llvm::MachineIRBuilderState::MF
MachineFunction * MF
MachineFunction under construction.
Definition: MachineIRBuilder.h:39
llvm::SrcOp::getPredicate
CmpInst::Predicate getPredicate() const
Definition: MachineIRBuilder.h:184
llvm::MachineIRBuilder::buildDeleteTrailingVectorElements
MachineInstrBuilder buildDeleteTrailingVectorElements(const DstOp &Res, const SrcOp &Op0)
Build and insert a, b, ..., x, y, z = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a,...
Definition: MachineIRBuilder.cpp:242
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:416
llvm::MachineIRBuilder::buildVecReduceSeqFMul
MachineInstrBuilder buildVecReduceSeqFMul(const DstOp &Dst, const SrcOp &ScalarIn, const SrcOp &VecIn)
Build and insert Res = G_VECREDUCE_SEQ_FMUL ScalarIn, VecIn.
Definition: MachineIRBuilder.h:1774
llvm::MachineIRBuilder::buildFMinNumIEEE
MachineInstrBuilder buildFMinNumIEEE(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1492
llvm::MachineIRBuilder::buildAddrSpaceCast
MachineInstrBuilder buildAddrSpaceCast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_ADDRSPACE_CAST Src.
Definition: MachineIRBuilder.h:666
llvm::MachineIRBuilder::buildBlockAddress
MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA)
Build and insert Res = G_BLOCK_ADDR BA.
Definition: MachineIRBuilder.cpp:992
llvm::MachineIRBuilder::validateTruncExt
void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend)
Definition: MachineIRBuilder.cpp:1000
llvm::DstOp::getLLTTy
LLT getLLTTy(const MachineRegisterInfo &MRI) const
Definition: MachineIRBuilder.h:87
llvm::MachineIRBuilder::buildAtomicRMWUmax
MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:957
llvm::MachineIRBuilder::validateShiftOp
void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1)
Definition: MachineIRBuilder.cpp:176
llvm::MachineIRBuilder::buildIntrinsic
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects)
Build and insert either a G_INTRINSIC (if HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS inst...
Definition: MachineIRBuilder.cpp:753
llvm::MachineIRBuilder::buildSSubo
MachineInstrBuilder buildSSubo(const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res, CarryOut = G_SUBO Op0, Op1.
Definition: MachineIRBuilder.h:558
MachineInstrBuilder.h
llvm::MachineIRBuilder::buildFExp2
MachineInstrBuilder buildFExp2(const DstOp &Dst, const SrcOp &Src, Optional< unsigned > Flags=None)
Build and insert Dst = G_FEXP2 Src.
Definition: MachineIRBuilder.h:1684
llvm::DstOp::DstType::Ty_Reg
@ Ty_Reg
llvm::MachineIRBuilder::buildSExt
MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op.
Definition: MachineIRBuilder.cpp:461
llvm::DstOp
Definition: MachineIRBuilder.h:58
llvm::MachineIRBuilder::buildFMaxNum
MachineInstrBuilder buildFMaxNum(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1486
llvm::MachineIRBuilder::buildSub
MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_SUB Op0, Op1.
Definition: MachineIRBuilder.h:1433
llvm::SrcOp::SrcOp
SrcOp(const MachineInstrBuilder &MIB)
Definition: MachineIRBuilder.h:131
llvm::MachineIRBuilder::buildLShr
MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1510
llvm::MachineIRBuilder::buildFDiv
MachineInstrBuilder buildFDiv(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_FDIV Op0, Op1.
Definition: MachineIRBuilder.h:1621
llvm::MachineIRBuilder::buildMerge
MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
Definition: MachineIRBuilder.cpp:628
llvm::SrcOp::getLLTTy
LLT getLLTTy(const MachineRegisterInfo &MRI) const
Definition: MachineIRBuilder.h:158
llvm::MachineIRBuilder::buildLoadFromOffset
MachineInstrBuilder buildLoadFromOffset(const DstOp &Dst, const SrcOp &BasePtr, MachineMemOperand &BaseMMO, int64_t Offset)
Helper to create a load from a constant offset given a base address.
Definition: MachineIRBuilder.cpp:412
llvm::MachineIRBuilder::buildAtomicRMWSub
MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:914
llvm::Module::getDataLayout
const DataLayout & getDataLayout() const
Get the data layout for the module's target platform.
Definition: Module.cpp:401
llvm::MachineIRBuilder::buildBuildVectorTrunc
MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR_TRUNC Op0, ...
Definition: MachineIRBuilder.cpp:688
llvm::MachineIRBuilder::getBoolExtOp
unsigned getBoolExtOp(bool IsVec, bool IsFP) const
Definition: MachineIRBuilder.cpp:471
llvm::MachineIRBuilder::buildFreeze
MachineInstrBuilder buildFreeze(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_FREEZE Src.
Definition: MachineIRBuilder.h:1391
llvm::MachineIRBuilder::getState
MachineIRBuilderState & getState()
Getter for the State.
Definition: MachineIRBuilder.h:284
llvm::MachineIRBuilder::buildCTTZ_ZERO_UNDEF
MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0)
Build and insert Res = G_CTTZ_ZERO_UNDEF Op0, Src0.
Definition: MachineIRBuilder.h:1597
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineIRBuilder::buildStore
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
Definition: MachineIRBuilder.cpp:429
llvm::MachineIRBuilder::buildAtomicRMWXchg
MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO.
Definition: MachineIRBuilder.cpp:902
llvm::MachineIRBuilder::buildAdd
MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_ADD Op0, Op1.
Definition: MachineIRBuilder.h:1416
llvm::MachineIRBuilder::stopObservingChanges
void stopObservingChanges()
Definition: MachineIRBuilder.h:351
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:133
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::MachineIRBuilderState::CSEInfo
GISelCSEInfo * CSEInfo
Definition: MachineIRBuilder.h:55
llvm::MachineIRBuilderState::MRI
MachineRegisterInfo * MRI
Information used to verify types are consistent and to create virtual registers.
Definition: MachineIRBuilder.h:43
llvm::SrcOp
Definition: MachineIRBuilder.h:119
llvm::SrcOp::SrcType::Ty_MIB
@ Ty_MIB
llvm::MachineIRBuilder::buildCast
MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src)
Build and insert an appropriate cast between two registers of equal size.
Definition: MachineIRBuilder.cpp:538
llvm::MachineIRBuilder::buildVecReduceSMin
MachineInstrBuilder buildVecReduceSMin(const DstOp &Dst, const SrcOp &Src)
Build and insert Res = G_VECREDUCE_SMIN Src.
Definition: MachineIRBuilder.h:1841
llvm::MachineIRBuilder::buildShuffleSplat
MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src)
Build and insert a vector splat of a scalar Src using a G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idio...
Definition: MachineIRBuilder.cpp:697
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::LLT
Definition: LowLevelTypeImpl.h:39