LLVM  10.0.0svn
Public Member Functions | Protected Member Functions | List of all members
llvm::MachineIRBuilder Class Reference

Helper class to build MachineInstr. More...

#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"

Inheritance diagram for llvm::MachineIRBuilder:
Inheritance graph
[legend]

Public Member Functions

 MachineIRBuilder ()=default
 Some constructors for easy use. More...
 
 MachineIRBuilder (MachineFunction &MF)
 
 MachineIRBuilder (MachineInstr &MI)
 
virtual ~MachineIRBuilder ()=default
 
 MachineIRBuilder (const MachineIRBuilderState &BState)
 
const TargetInstrInfogetTII ()
 
MachineFunctiongetMF ()
 Getter for the function we currently build. More...
 
const MachineFunctiongetMF () const
 
const DataLayoutgetDataLayout () const
 
const DebugLocgetDL ()
 Getter for DebugLoc. More...
 
MachineRegisterInfogetMRI ()
 Getter for MRI. More...
 
const MachineRegisterInfogetMRI () const
 
MachineIRBuilderStategetState ()
 Getter for the State. More...
 
const MachineBasicBlockgetMBB () const
 Getter for the basic block we currently build. More...
 
MachineBasicBlockgetMBB ()
 
GISelCSEInfogetCSEInfo ()
 
const GISelCSEInfogetCSEInfo () const
 
MachineBasicBlock::iterator getInsertPt ()
 Current insertion point for new instructions. More...
 
void setInsertPt (MachineBasicBlock &MBB, MachineBasicBlock::iterator II)
 Set the insertion point before the specified position. More...
 
void setCSEInfo (GISelCSEInfo *Info)
 
void setChangeObserver (GISelChangeObserver &Observer)
 
void stopObservingChanges ()
 
void setDebugLoc (const DebugLoc &DL)
 Set the debug location to DL for all the next build instructions. More...
 
DebugLoc getDebugLoc ()
 Get the current instruction's debug location. More...
 
MachineInstrBuilder buildInstr (unsigned Opcode)
 Build and insert <empty> = Opcode <empty>. More...
 
MachineInstrBuilder buildInstrNoInsert (unsigned Opcode)
 Build but don't insert <empty> = Opcode <empty>. More...
 
MachineInstrBuilder insertInstr (MachineInstrBuilder MIB)
 Insert an existing instruction at the insertion point. More...
 
MachineInstrBuilder buildDirectDbgValue (Register Reg, const MDNode *Variable, const MDNode *Expr)
 Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Reg (suitably modified by Expr). More...
 
MachineInstrBuilder buildIndirectDbgValue (Register Reg, const MDNode *Variable, const MDNode *Expr)
 Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in memory at Reg (suitably modified by Expr). More...
 
MachineInstrBuilder buildFIDbgValue (int FI, const MDNode *Variable, const MDNode *Expr)
 Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in the stack slot specified by FI (suitably modified by Expr). More...
 
MachineInstrBuilder buildConstDbgValue (const Constant &C, const MDNode *Variable, const MDNode *Expr)
 Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified by Expr). More...
 
MachineInstrBuilder buildDbgLabel (const MDNode *Label)
 Build and insert a DBG_LABEL instructions specifying that Label is given. More...
 
MachineInstrBuilder buildFrameIndex (const DstOp &Res, int Idx)
 Build and insert Res = G_FRAME_INDEX Idx. More...
 
MachineInstrBuilder buildGlobalValue (const DstOp &Res, const GlobalValue *GV)
 Build and insert Res = G_GLOBAL_VALUE GV. More...
 
MachineInstrBuilder buildGEP (const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
 Build and insert Res = G_GEP Op0, Op1. More...
 
Optional< MachineInstrBuildermaterializeGEP (Register &Res, Register Op0, const LLT &ValueTy, uint64_t Value)
 Materialize and insert Res = G_GEP Op0, (G_CONSTANT Value) More...
 
MachineInstrBuilder buildPtrMask (const DstOp &Res, const SrcOp &Op0, uint32_t NumBits)
 Build and insert Res = G_PTR_MASK Op0, NumBits. More...
 
MachineInstrBuilder buildUAddo (const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1)
 Build and insert Res, CarryOut = G_UADDO Op0, Op1. More...
 
MachineInstrBuilder buildUAdde (const DstOp &Res, const DstOp &CarryOut, const SrcOp &Op0, const SrcOp &Op1, const SrcOp &CarryIn)
 Build and insert Res, CarryOut = G_UADDE Op0, Op1, CarryIn. More...
 
MachineInstrBuilder buildAnyExt (const DstOp &Res, const SrcOp &Op)
 Build and insert Res = G_ANYEXT Op0. More...
 
MachineInstrBuilder buildSExt (const DstOp &Res, const SrcOp &Op)
 Build and insert Res = G_SEXT Op. More...
 
MachineInstrBuilder buildPtrToInt (const DstOp &Dst, const SrcOp &Src)
 Build and insert a G_PTRTOINT instruction. More...
 
MachineInstrBuilder buildBitcast (const DstOp &Dst, const SrcOp &Src)
 Build and insert Dst = G_BITCAST Src. More...
 
unsigned getBoolExtOp (bool IsVec, bool IsFP) const
 
MachineInstrBuilder buildBoolExt (const DstOp &Res, const SrcOp &Op, bool IsFP)
 
MachineInstrBuilder buildZExt (const DstOp &Res, const SrcOp &Op)
 Build and insert Res = G_ZEXT Op. More...
 
MachineInstrBuilder buildSExtOrTrunc (const DstOp &Res, const SrcOp &Op)
 Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of Res and Op. More...
 
MachineInstrBuilder buildZExtOrTrunc (const DstOp &Res, const SrcOp &Op)
 Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of Res and Op. More...
 
MachineInstrBuilder buildAnyExtOrTrunc (const DstOp &Res, const SrcOp &Op)
 Res = COPY Op depending on the differing sizes of Res and Op. More...
 
MachineInstrBuilder buildExtOrTrunc (unsigned ExtOpc, const DstOp &Res, const SrcOp &Op)
 Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of Res and Op. More...
 
MachineInstrBuilder buildCast (const DstOp &Dst, const SrcOp &Src)
 Build and insert an appropriate cast between two registers of equal size. More...
 
MachineInstrBuilder buildBr (MachineBasicBlock &Dest)
 Build and insert G_BR Dest. More...
 
MachineInstrBuilder buildBrCond (Register Tst, MachineBasicBlock &Dest)
 Build and insert G_BRCOND Tst, Dest. More...
 
MachineInstrBuilder buildBrIndirect (Register Tgt)
 Build and insert G_BRINDIRECT Tgt. More...
 
MachineInstrBuilder buildBrJT (Register TablePtr, unsigned JTI, Register IndexReg)
 Build and insert G_BRJT TablePtr, JTI, IndexReg. More...
 
virtual MachineInstrBuilder buildConstant (const DstOp &Res, const ConstantInt &Val)
 Build and insert Res = G_CONSTANT Val. More...
 
MachineInstrBuilder buildConstant (const DstOp &Res, int64_t Val)
 Build and insert Res = G_CONSTANT Val. More...
 
MachineInstrBuilder buildConstant (const DstOp &Res, const APInt &Val)
 
virtual MachineInstrBuilder buildFConstant (const DstOp &Res, const ConstantFP &Val)
 Build and insert Res = G_FCONSTANT Val. More...
 
MachineInstrBuilder buildFConstant (const DstOp &Res, double Val)
 
MachineInstrBuilder buildFConstant (const DstOp &Res, const APFloat &Val)
 
MachineInstrBuilder buildCopy (const DstOp &Res, const SrcOp &Op)
 Build and insert Res = COPY Op. More...
 
MachineInstrBuilder buildLoad (const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
 Build and insert Res = G_LOAD Addr, MMO. More...
 
MachineInstrBuilder buildLoadInstr (unsigned Opcode, const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
 Build and insert Res = <opcode> Addr, MMO. More...
 
MachineInstrBuilder buildStore (const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
 Build and insert G_STORE Val, Addr, MMO. More...
 
MachineInstrBuilder buildExtract (const DstOp &Res, const SrcOp &Src, uint64_t Index)
 Build and insert `Res0, ... More...
 
MachineInstrBuilder buildUndef (const DstOp &Res)
 Build and insert Res = IMPLICIT_DEF. More...
 
void buildSequence (Register Res, ArrayRef< Register > Ops, ArrayRef< uint64_t > Indices)
 Build and insert instructions to put Ops together at the specified p Indices to form a larger register. More...
 
MachineInstrBuilder buildMerge (const DstOp &Res, ArrayRef< Register > Ops)
 Build and insert Res = G_MERGE_VALUES Op0, ... More...
 
MachineInstrBuilder buildUnmerge (ArrayRef< LLT > Res, const SrcOp &Op)
 Build and insert Res0, ... More...
 
MachineInstrBuilder buildUnmerge (ArrayRef< Register > Res, const SrcOp &Op)
 
MachineInstrBuilder buildUnmerge (LLT Res, const SrcOp &Op)
 Build and insert an unmerge of Res sized pieces to cover Op. More...
 
MachineInstrBuilder buildBuildVector (const DstOp &Res, ArrayRef< Register > Ops)
 Build and insert Res = G_BUILD_VECTOR Op0, ... More...
 
MachineInstrBuilder buildSplatVector (const DstOp &Res, const SrcOp &Src)
 Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements. More...
 
MachineInstrBuilder buildBuildVectorTrunc (const DstOp &Res, ArrayRef< Register > Ops)
 Build and insert Res = G_BUILD_VECTOR_TRUNC Op0, ... More...
 
MachineInstrBuilder buildConcatVectors (const DstOp &Res, ArrayRef< Register > Ops)
 Build and insert Res = G_CONCAT_VECTORS Op0, ... More...
 
MachineInstrBuilder buildInsert (Register Res, Register Src, Register Op, unsigned Index)
 
MachineInstrBuilder buildIntrinsic (Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects)
 Build and insert either a G_INTRINSIC (if HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS instruction. More...
 
MachineInstrBuilder buildIntrinsic (Intrinsic::ID ID, ArrayRef< DstOp > Res, bool HasSideEffects)
 
MachineInstrBuilder buildFPTrunc (const DstOp &Res, const SrcOp &Op)
 Build and insert Res = G_FPTRUNC Op. More...
 
MachineInstrBuilder buildTrunc (const DstOp &Res, const SrcOp &Op)
 Build and insert Res = G_TRUNC Op. More...
 
MachineInstrBuilder buildICmp (CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
 Build and insert a Res = G_ICMP Pred, Op0, Op1. More...
 
MachineInstrBuilder buildFCmp (CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
 Build and insert a Res = G_FCMP PredOp0, Op1. More...
 
MachineInstrBuilder buildSelect (const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1)
 Build and insert a Res = G_SELECT Tst, Op0, Op1. More...
 
MachineInstrBuilder buildInsertVectorElement (const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)
 Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx. More...
 
MachineInstrBuilder buildExtractVectorElement (const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)
 Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx. More...
 
MachineInstrBuilder buildAtomicCmpXchgWithSuccess (Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
 Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO. More...
 
MachineInstrBuilder buildAtomicCmpXchg (Register OldValRes, Register Addr, Register CmpVal, Register NewVal, MachineMemOperand &MMO)
 Build and insert OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO. More...
 
MachineInstrBuilder buildAtomicRMW (unsigned Opcode, Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
 Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO. More...
 
MachineInstrBuilder buildAtomicRMWXchg (Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
 Build and insert OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO. More...
 
MachineInstrBuilder buildAtomicRMWAdd (Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
 Build and insert OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO. More...
 
MachineInstrBuilder buildAtomicRMWSub (Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
 Build and insert OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO. More...
 
MachineInstrBuilder buildAtomicRMWAnd (Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
 Build and insert OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO. More...
 
MachineInstrBuilder buildAtomicRMWNand (Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
 Build and insert OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO. More...
 
MachineInstrBuilder buildAtomicRMWOr (Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
 Build and insert OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO. More...
 
MachineInstrBuilder buildAtomicRMWXor (Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
 Build and insert OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO. More...
 
MachineInstrBuilder buildAtomicRMWMax (Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
 Build and insert OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO. More...
 
MachineInstrBuilder buildAtomicRMWMin (Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
 Build and insert OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO. More...
 
MachineInstrBuilder buildAtomicRMWUmax (Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
 Build and insert OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO. More...
 
MachineInstrBuilder buildAtomicRMWUmin (Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)
 Build and insert OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO. More...
 
MachineInstrBuilder buildFence (unsigned Ordering, unsigned Scope)
 Build and insert G_FENCE Ordering, Scope. More...
 
MachineInstrBuilder buildBlockAddress (Register Res, const BlockAddress *BA)
 Build and insert Res = G_BLOCK_ADDR BA. More...
 
MachineInstrBuilder buildAdd (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
 Build and insert Res = G_ADD Op0, Op1. More...
 
MachineInstrBuilder buildSub (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
 Build and insert Res = G_SUB Op0, Op1. More...
 
MachineInstrBuilder buildMul (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
 Build and insert Res = G_MUL Op0, Op1. More...
 
MachineInstrBuilder buildUMulH (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
 
MachineInstrBuilder buildSMulH (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
 
MachineInstrBuilder buildShl (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
 
MachineInstrBuilder buildLShr (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
 
MachineInstrBuilder buildAShr (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
 
MachineInstrBuilder buildAnd (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
 Build and insert Res = G_AND Op0, Op1. More...
 
MachineInstrBuilder buildOr (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
 Build and insert Res = G_OR Op0, Op1. More...
 
MachineInstrBuilder buildXor (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
 Build and insert Res = G_XOR Op0, Op1. More...
 
MachineInstrBuilder buildNot (const DstOp &Dst, const SrcOp &Src0)
 Build and insert a bitwise not, NegOne = G_CONSTANT -1 Res = G_OR Op0, NegOne. More...
 
MachineInstrBuilder buildCTPOP (const DstOp &Dst, const SrcOp &Src0)
 Build and insert Res = G_CTPOP Op0, Src0. More...
 
MachineInstrBuilder buildCTLZ (const DstOp &Dst, const SrcOp &Src0)
 Build and insert Res = G_CTLZ Op0, Src0. More...
 
MachineInstrBuilder buildCTLZ_ZERO_UNDEF (const DstOp &Dst, const SrcOp &Src0)
 Build and insert Res = G_CTLZ_ZERO_UNDEF Op0, Src0. More...
 
MachineInstrBuilder buildCTTZ (const DstOp &Dst, const SrcOp &Src0)
 Build and insert Res = G_CTTZ Op0, Src0. More...
 
MachineInstrBuilder buildCTTZ_ZERO_UNDEF (const DstOp &Dst, const SrcOp &Src0)
 Build and insert Res = G_CTTZ_ZERO_UNDEF Op0, Src0. More...
 
MachineInstrBuilder buildFAdd (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
 Build and insert Res = G_FADD Op0, Op1. More...
 
MachineInstrBuilder buildFSub (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
 Build and insert Res = G_FSUB Op0, Op1. More...
 
MachineInstrBuilder buildFMA (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, const SrcOp &Src2)
 Build and insert Res = G_FMA Op0, Op1, Op2. More...
 
MachineInstrBuilder buildFNeg (const DstOp &Dst, const SrcOp &Src0)
 Build and insert Res = G_FNEG Op0. More...
 
MachineInstrBuilder buildFAbs (const DstOp &Dst, const SrcOp &Src0)
 Build and insert Res = G_FABS Op0. More...
 
MachineInstrBuilder buildFCanonicalize (const DstOp &Dst, const SrcOp &Src0, Optional< unsigned > Flags=None)
 Build and insert Dst = G_FCANONICALIZE Src0. More...
 
MachineInstrBuilder buildFCopysign (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
 Build and insert Res = G_FCOPYSIGN Op0, Op1. More...
 
MachineInstrBuilder buildUITOFP (const DstOp &Dst, const SrcOp &Src0)
 Build and insert Res = G_UITOFP Src0. More...
 
MachineInstrBuilder buildSITOFP (const DstOp &Dst, const SrcOp &Src0)
 Build and insert Res = G_SITOFP Src0. More...
 
MachineInstrBuilder buildFPTOUI (const DstOp &Dst, const SrcOp &Src0)
 Build and insert Res = G_FPTOUI Src0. More...
 
MachineInstrBuilder buildFPTOSI (const DstOp &Dst, const SrcOp &Src0)
 Build and insert Res = G_FPTOSI Src0. More...
 
MachineInstrBuilder buildSMin (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
 Build and insert Res = G_SMIN Op0, Op1. More...
 
MachineInstrBuilder buildSMax (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
 Build and insert Res = G_SMAX Op0, Op1. More...
 
MachineInstrBuilder buildUMin (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
 Build and insert Res = G_UMIN Op0, Op1. More...
 
MachineInstrBuilder buildUMax (const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
 Build and insert Res = G_UMAX Op0, Op1. More...
 
MachineInstrBuilder buildJumpTable (const LLT PtrTy, unsigned JTI)
 Build and insert Res = G_JUMP_TABLE JTI. More...
 
virtual MachineInstrBuilder buildInstr (unsigned Opc, ArrayRef< DstOp > DstOps, ArrayRef< SrcOp > SrcOps, Optional< unsigned > Flags=None)
 
Setters for the insertion point.

Set the MachineFunction where to build instructions.

void setMF (MachineFunction &MF)
 
void setMBB (MachineBasicBlock &MBB)
 Set the insertion point to the end of MBB. More...
 
void setInstr (MachineInstr &MI)
 Set the insertion point to before MI. More...
 

Protected Member Functions

void validateTruncExt (const LLT &Dst, const LLT &Src, bool IsExtend)
 
void validateBinaryOp (const LLT &Res, const LLT &Op0, const LLT &Op1)
 
void validateShiftOp (const LLT &Res, const LLT &Op0, const LLT &Op1)
 
void validateSelectOp (const LLT &ResTy, const LLT &TstTy, const LLT &Op0Ty, const LLT &Op1Ty)
 
void recordInsertion (MachineInstr *MI) const
 

Detailed Description

Helper class to build MachineInstr.

It keeps internally the insertion point and debug location for all the new instructions we want to create. This information can be modify via the related setters.

Definition at line 199 of file MachineIRBuilder.h.

Constructor & Destructor Documentation

◆ MachineIRBuilder() [1/4]

llvm::MachineIRBuilder::MachineIRBuilder ( )
default

Some constructors for easy use.

◆ MachineIRBuilder() [2/4]

llvm::MachineIRBuilder::MachineIRBuilder ( MachineFunction MF)
inline

Definition at line 216 of file MachineIRBuilder.h.

◆ MachineIRBuilder() [3/4]

llvm::MachineIRBuilder::MachineIRBuilder ( MachineInstr MI)
inline

Definition at line 217 of file MachineIRBuilder.h.

◆ ~MachineIRBuilder()

virtual llvm::MachineIRBuilder::~MachineIRBuilder ( )
virtualdefault

◆ MachineIRBuilder() [4/4]

llvm::MachineIRBuilder::MachineIRBuilder ( const MachineIRBuilderState BState)
inline

Definition at line 223 of file MachineIRBuilder.h.

Member Function Documentation

◆ buildAdd()

MachineInstrBuilder llvm::MachineIRBuilder::buildAdd ( const DstOp Dst,
const SrcOp Src0,
const SrcOp Src1,
Optional< unsigned Flags = None 
)
inline

Build and insert Res = G_ADD Op0, Op1.

G_ADD sets Res to the sum of integer parameters Op0 and Op1, truncated to their width.

Precondition
setBasicBlock or setMI must have been called.
Res, Op0 and Op1 must be generic virtual registers with the same (scalar or vector) type).
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 1162 of file MachineIRBuilder.h.

Referenced by llvm::LegalizerHelper::lower(), llvm::LegalizerHelper::lowerSITOFP(), llvm::LegalizerHelper::lowerU64ToF32BitOps(), and llvm::LegalizerHelper::moreElementsVector().

◆ buildAnd()

MachineInstrBuilder llvm::MachineIRBuilder::buildAnd ( const DstOp Dst,
const SrcOp Src0,
const SrcOp Src1 
)
inline

Build and insert Res = G_AND Op0, Op1.

G_AND sets Res to the bitwise and of integer parameters Op0 and Op1.

Precondition
setBasicBlock or setMI must have been called.
Res, Op0 and Op1 must be generic virtual registers with the same (scalar or vector) type).
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 1242 of file MachineIRBuilder.h.

Referenced by llvm::AMDGPULegalizerInfo::legalizeFceil(), llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc(), llvm::AMDGPULegalizerInfo::loadInputValue(), llvm::LegalizerHelper::lowerFCopySign(), llvm::LegalizerHelper::lowerU64ToF32BitOps(), and llvm::LegalizationArtifactCombiner::tryCombineZExt().

◆ buildAnyExt()

MachineInstrBuilder MachineIRBuilder::buildAnyExt ( const DstOp Res,
const SrcOp Op 
)

Build and insert Res = G_ANYEXT Op0.

G_ANYEXT produces a register of the specified width, with bits 0 to sizeof(Ty) * 8 set to Op. The remaining bits are unspecified (i.e. this is neither zero nor sign-extension). For a vector register, each element is extended individually.

Precondition
setBasicBlock or setMI must have been called.
Res must be a generic virtual register with scalar or vector type.
Op must be a generic virtual register with scalar or vector type.
Op must be smaller than Res
Returns
The newly created instruction.

Definition at line 402 of file MachineIRBuilder.cpp.

References buildInstr().

Referenced by llvm::AArch64CallLowering::AArch64CallLowering(), llvm::CallLowering::ValueHandler::extendRegister(), llvm::LegalizerHelper::lower(), llvm::LegalizerHelper::narrowScalar(), substituteSimpleCopyRegs(), and llvm::X86CallLowering::X86CallLowering().

◆ buildAnyExtOrTrunc()

MachineInstrBuilder MachineIRBuilder::buildAnyExtOrTrunc ( const DstOp Res,
const SrcOp Op 
)

Res = COPY Op depending on the differing sizes of Res and Op.

///

Precondition
setBasicBlock or setMI must have been called.
Res must be a generic virtual register with scalar or vector type.
Op must be a generic virtual register with scalar or vector type.
Returns
The newly created instruction.

Definition at line 470 of file MachineIRBuilder.cpp.

References buildExtOrTrunc().

Referenced by llvm::LegalizerHelper::narrowScalar(), llvm::LegalizationArtifactCombiner::tryCombineAnyExt(), llvm::LegalizationArtifactCombiner::tryCombineSExt(), and llvm::LegalizationArtifactCombiner::tryCombineZExt().

◆ buildAShr()

MachineInstrBuilder llvm::MachineIRBuilder::buildAShr ( const DstOp Dst,
const SrcOp Src0,
const SrcOp Src1,
Optional< unsigned Flags = None 
)
inline

◆ buildAtomicCmpXchg()

MachineInstrBuilder MachineIRBuilder::buildAtomicCmpXchg ( Register  OldValRes,
Register  Addr,
Register  CmpVal,
Register  NewVal,
MachineMemOperand MMO 
)

Build and insert OldValRes<def> = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO.

Atomically replace the value at Addr with NewVal if it is currently CmpVal otherwise leaves it unchanged. Puts the original value from Addr in Res.

Precondition
setBasicBlock or setMI must have been called.
OldValRes must be a generic virtual register of scalar type.
Addr must be a generic virtual register with pointer type.
OldValRes, CmpVal, and NewVal must be generic virtual registers of the same type.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 753 of file MachineIRBuilder.cpp.

References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addUse(), assert(), buildInstr(), getMRI(), llvm::MachineRegisterInfo::getType(), llvm::LLT::isPointer(), llvm::LLT::isScalar(), and llvm::LLT::isValid().

Referenced by llvm::LegalizerHelper::lower().

◆ buildAtomicCmpXchgWithSuccess()

MachineInstrBuilder MachineIRBuilder::buildAtomicCmpXchgWithSuccess ( Register  OldValRes,
Register  SuccessRes,
Register  Addr,
Register  CmpVal,
Register  NewVal,
MachineMemOperand MMO 
)

Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO.

Atomically replace the value at Addr with NewVal if it is currently CmpVal otherwise leaves it unchanged. Puts the original value from Addr in Res, along with an s1 indicating whether it was replaced.

Precondition
setBasicBlock or setMI must have been called.
OldValRes must be a generic virtual register of scalar type.
SuccessRes must be a generic virtual register of scalar type. It will be assigned 0 on failure and 1 on success.
Addr must be a generic virtual register with pointer type.
OldValRes, CmpVal, and NewVal must be generic virtual registers of the same type.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 725 of file MachineIRBuilder.cpp.

References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addUse(), assert(), buildInstr(), getMRI(), llvm::MachineRegisterInfo::getType(), llvm::LLT::isPointer(), llvm::LLT::isScalar(), and llvm::LLT::isValid().

Referenced by getOffsetFromIndices().

◆ buildAtomicRMW()

MachineInstrBuilder MachineIRBuilder::buildAtomicRMW ( unsigned  Opcode,
Register  OldValRes,
Register  Addr,
Register  Val,
MachineMemOperand MMO 
)

Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.

Atomically read-modify-update the value at Addr with Val. Puts the original value from Addr in OldValRes. The modification is determined by the opcode.

Precondition
setBasicBlock or setMI must have been called.
OldValRes must be a generic virtual register.
Addr must be a generic virtual register with pointer type.
OldValRes, and Val must be generic virtual registers of the same type.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 777 of file MachineIRBuilder.cpp.

References llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addUse(), assert(), buildInstr(), getMRI(), llvm::MachineRegisterInfo::getType(), llvm::LLT::isPointer(), llvm::LLT::isScalar(), and llvm::LLT::isValid().

Referenced by buildAtomicRMWAdd(), buildAtomicRMWAnd(), buildAtomicRMWMax(), buildAtomicRMWMin(), buildAtomicRMWNand(), buildAtomicRMWOr(), buildAtomicRMWSub(), buildAtomicRMWUmax(), buildAtomicRMWUmin(), buildAtomicRMWXchg(), buildAtomicRMWXor(), and getOffsetFromIndices().

◆ buildAtomicRMWAdd()

MachineInstrBuilder MachineIRBuilder::buildAtomicRMWAdd ( Register  OldValRes,
Register  Addr,
Register  Val,
MachineMemOperand MMO 
)

Build and insert OldValRes<def> = G_ATOMICRMW_ADD Addr, Val, MMO.

Atomically replace the value at Addr with the addition of Val and the original value. Puts the original value from Addr in OldValRes.

Precondition
setBasicBlock or setMI must have been called.
OldValRes must be a generic virtual register.
Addr must be a generic virtual register with pointer type.
OldValRes, and Val must be generic virtual registers of the same type.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 806 of file MachineIRBuilder.cpp.

References buildAtomicRMW().

◆ buildAtomicRMWAnd()

MachineInstrBuilder MachineIRBuilder::buildAtomicRMWAnd ( Register  OldValRes,
Register  Addr,
Register  Val,
MachineMemOperand MMO 
)

Build and insert OldValRes<def> = G_ATOMICRMW_AND Addr, Val, MMO.

Atomically replace the value at Addr with the bitwise and of Val and the original value. Puts the original value from Addr in OldValRes.

Precondition
setBasicBlock or setMI must have been called.
OldValRes must be a generic virtual register.
Addr must be a generic virtual register with pointer type.
OldValRes, and Val must be generic virtual registers of the same type.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 818 of file MachineIRBuilder.cpp.

References buildAtomicRMW().

◆ buildAtomicRMWMax()

MachineInstrBuilder MachineIRBuilder::buildAtomicRMWMax ( Register  OldValRes,
Register  Addr,
Register  Val,
MachineMemOperand MMO 
)

Build and insert OldValRes<def> = G_ATOMICRMW_MAX Addr, Val, MMO.

Atomically replace the value at Addr with the signed maximum of Val and the original value. Puts the original value from Addr in OldValRes.

Precondition
setBasicBlock or setMI must have been called.
OldValRes must be a generic virtual register.
Addr must be a generic virtual register with pointer type.
OldValRes, and Val must be generic virtual registers of the same type.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 843 of file MachineIRBuilder.cpp.

References buildAtomicRMW().

◆ buildAtomicRMWMin()

MachineInstrBuilder MachineIRBuilder::buildAtomicRMWMin ( Register  OldValRes,
Register  Addr,
Register  Val,
MachineMemOperand MMO 
)

Build and insert OldValRes<def> = G_ATOMICRMW_MIN Addr, Val, MMO.

Atomically replace the value at Addr with the signed minimum of Val and the original value. Puts the original value from Addr in OldValRes.

Precondition
setBasicBlock or setMI must have been called.
OldValRes must be a generic virtual register.
Addr must be a generic virtual register with pointer type.
OldValRes, and Val must be generic virtual registers of the same type.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 849 of file MachineIRBuilder.cpp.

References buildAtomicRMW().

◆ buildAtomicRMWNand()

MachineInstrBuilder MachineIRBuilder::buildAtomicRMWNand ( Register  OldValRes,
Register  Addr,
Register  Val,
MachineMemOperand MMO 
)

Build and insert OldValRes<def> = G_ATOMICRMW_NAND Addr, Val, MMO.

Atomically replace the value at Addr with the bitwise nand of Val and the original value. Puts the original value from Addr in OldValRes.

Precondition
setBasicBlock or setMI must have been called.
OldValRes must be a generic virtual register.
Addr must be a generic virtual register with pointer type.
OldValRes, and Val must be generic virtual registers of the same type.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 824 of file MachineIRBuilder.cpp.

References buildAtomicRMW().

◆ buildAtomicRMWOr()

MachineInstrBuilder MachineIRBuilder::buildAtomicRMWOr ( Register  OldValRes,
Register  Addr,
Register  Val,
MachineMemOperand MMO 
)

Build and insert OldValRes<def> = G_ATOMICRMW_OR Addr, Val, MMO.

Atomically replace the value at Addr with the bitwise or of Val and the original value. Puts the original value from Addr in OldValRes.

Precondition
setBasicBlock or setMI must have been called.
OldValRes must be a generic virtual register.
Addr must be a generic virtual register with pointer type.
OldValRes, and Val must be generic virtual registers of the same type.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 829 of file MachineIRBuilder.cpp.

References buildAtomicRMW().

◆ buildAtomicRMWSub()

MachineInstrBuilder MachineIRBuilder::buildAtomicRMWSub ( Register  OldValRes,
Register  Addr,
Register  Val,
MachineMemOperand MMO 
)

Build and insert OldValRes<def> = G_ATOMICRMW_SUB Addr, Val, MMO.

Atomically replace the value at Addr with the subtraction of Val and the original value. Puts the original value from Addr in OldValRes.

Precondition
setBasicBlock or setMI must have been called.
OldValRes must be a generic virtual register.
Addr must be a generic virtual register with pointer type.
OldValRes, and Val must be generic virtual registers of the same type.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 812 of file MachineIRBuilder.cpp.

References buildAtomicRMW().

◆ buildAtomicRMWUmax()

MachineInstrBuilder MachineIRBuilder::buildAtomicRMWUmax ( Register  OldValRes,
Register  Addr,
Register  Val,
MachineMemOperand MMO 
)

Build and insert OldValRes<def> = G_ATOMICRMW_UMAX Addr, Val, MMO.

Atomically replace the value at Addr with the unsigned maximum of Val and the original value. Puts the original value from Addr in OldValRes.

Precondition
setBasicBlock or setMI must have been called.
OldValRes must be a generic virtual register.
Addr must be a generic virtual register with pointer type.
OldValRes, and Val must be generic virtual registers of the same type.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 855 of file MachineIRBuilder.cpp.

References buildAtomicRMW().

◆ buildAtomicRMWUmin()

MachineInstrBuilder MachineIRBuilder::buildAtomicRMWUmin ( Register  OldValRes,
Register  Addr,
Register  Val,
MachineMemOperand MMO 
)

Build and insert OldValRes<def> = G_ATOMICRMW_UMIN Addr, Val, MMO.

Atomically replace the value at Addr with the unsigned minimum of Val and the original value. Puts the original value from Addr in OldValRes.

Precondition
setBasicBlock or setMI must have been called.
OldValRes must be a generic virtual register.
Addr must be a generic virtual register with pointer type.
OldValRes, and Val must be generic virtual registers of the same type.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 861 of file MachineIRBuilder.cpp.

References buildAtomicRMW().

◆ buildAtomicRMWXchg()

MachineInstrBuilder MachineIRBuilder::buildAtomicRMWXchg ( Register  OldValRes,
Register  Addr,
Register  Val,
MachineMemOperand MMO 
)

Build and insert OldValRes<def> = G_ATOMICRMW_XCHG Addr, Val, MMO.

Atomically replace the value at Addr with Val. Puts the original value from Addr in OldValRes.

Precondition
setBasicBlock or setMI must have been called.
OldValRes must be a generic virtual register.
Addr must be a generic virtual register with pointer type.
OldValRes, and Val must be generic virtual registers of the same type.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 800 of file MachineIRBuilder.cpp.

References buildAtomicRMW().

◆ buildAtomicRMWXor()

MachineInstrBuilder MachineIRBuilder::buildAtomicRMWXor ( Register  OldValRes,
Register  Addr,
Register  Val,
MachineMemOperand MMO 
)

Build and insert OldValRes<def> = G_ATOMICRMW_XOR Addr, Val, MMO.

Atomically replace the value at Addr with the bitwise xor of Val and the original value. Puts the original value from Addr in OldValRes.

Precondition
setBasicBlock or setMI must have been called.
OldValRes must be a generic virtual register.
Addr must be a generic virtual register with pointer type.
OldValRes, and Val must be generic virtual registers of the same type.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 837 of file MachineIRBuilder.cpp.

References buildAtomicRMW().

◆ buildBitcast()

MachineInstrBuilder llvm::MachineIRBuilder::buildBitcast ( const DstOp Dst,
const SrcOp Src 
)
inline

Build and insert Dst = G_BITCAST Src.

Definition at line 493 of file MachineIRBuilder.h.

Referenced by llvm::AArch64LegalizerInfo::legalizeIntrinsic().

◆ buildBlockAddress()

MachineInstrBuilder MachineIRBuilder::buildBlockAddress ( Register  Res,
const BlockAddress BA 
)

Build and insert Res = G_BLOCK_ADDR BA.

G_BLOCK_ADDR computes the address of a basic block.

Precondition
setBasicBlock or setMI must have been called.
Res must be a generic virtual register of a pointer type.
Returns
The newly created instruction.

Definition at line 875 of file MachineIRBuilder.cpp.

References llvm::MachineInstrBuilder::addBlockAddress(), llvm::MachineInstrBuilder::addDef(), assert(), buildInstr(), getMRI(), getType(), and llvm::LegalityPredicates::isPointer().

◆ buildBoolExt()

MachineInstrBuilder MachineIRBuilder::buildBoolExt ( const DstOp Res,
const SrcOp Op,
bool  IsFP 
)

◆ buildBr()

MachineInstrBuilder MachineIRBuilder::buildBr ( MachineBasicBlock Dest)

Build and insert G_BR Dest.

G_BR is an unconditional branch to Dest.

Precondition
setBasicBlock or setMI must have been called.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 246 of file MachineIRBuilder.cpp.

References llvm::MachineInstrBuilder::addMBB(), and buildInstr().

Referenced by llvm::IRTranslator::getAnalysisUsage(), and getOffsetFromIndices().

◆ buildBrCond()

MachineInstrBuilder MachineIRBuilder::buildBrCond ( Register  Tst,
MachineBasicBlock Dest 
)

Build and insert G_BRCOND Tst, Dest.

G_BRCOND is a conditional branch to Dest.

Precondition
setBasicBlock or setMI must have been called.
Tst must be a generic virtual register with scalar type. At the beginning of legalization, this will be a single bit (s1). Targets with interesting flags registers may change this. For a wider type, whether the branch is taken must only depend on bit 0 (for now).
Returns
The newly created instruction.

Definition at line 346 of file MachineIRBuilder.cpp.

References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addUse(), assert(), buildInstr(), getMRI(), getType(), and llvm::LegalityPredicates::isScalar().

Referenced by llvm::IRTranslator::getAnalysisUsage().

◆ buildBrIndirect()

MachineInstrBuilder MachineIRBuilder::buildBrIndirect ( Register  Tgt)

Build and insert G_BRINDIRECT Tgt.

G_BRINDIRECT is an indirect branch to Tgt.

Precondition
setBasicBlock or setMI must have been called.
Tgt must be a generic virtual register with pointer type.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 250 of file MachineIRBuilder.cpp.

References llvm::MachineInstrBuilder::addUse(), assert(), buildInstr(), getMRI(), getType(), and llvm::LegalityPredicates::isPointer().

◆ buildBrJT()

MachineInstrBuilder MachineIRBuilder::buildBrJT ( Register  TablePtr,
unsigned  JTI,
Register  IndexReg 
)

Build and insert G_BRJT TablePtr, JTI, IndexReg.

G_BRJT is a jump table branch using a table base pointer TablePtr, jump table index JTI and index IndexReg

Precondition
setBasicBlock or setMI must have been called.
TablePtr must be a generic virtual register with pointer type.
JTI must be be a jump table index.
IndexReg must be a generic virtual register with pointer type.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 255 of file MachineIRBuilder.cpp.

References llvm::MachineInstrBuilder::addJumpTableIndex(), llvm::MachineInstrBuilder::addUse(), assert(), buildInstr(), getMRI(), getType(), and llvm::LegalityPredicates::isPointer().

Referenced by llvm::IRTranslator::getAnalysisUsage().

◆ buildBuildVector()

MachineInstrBuilder MachineIRBuilder::buildBuildVector ( const DstOp Res,
ArrayRef< Register Ops 
)

Build and insert Res = G_BUILD_VECTOR Op0, ...

G_BUILD_VECTOR creates a vector value from multiple scalar registers.

Precondition
setBasicBlock or setMI must have been called.
The entire register Res (and no more) must be covered by the input scalar registers.
The type of all Ops registers must be identical.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 604 of file MachineIRBuilder.cpp.

References llvm::ArrayRef< T >::begin(), buildInstr(), and llvm::ArrayRef< T >::end().

Referenced by llvm::LegalizerHelper::fewerElementsVectorBasic(), llvm::LegalizerHelper::fewerElementsVectorCasts(), llvm::LegalizerHelper::fewerElementsVectorCmp(), llvm::LegalizerHelper::fewerElementsVectorImplicitDef(), llvm::LegalizerHelper::fewerElementsVectorSelect(), getHalfSizedType(), llvm::LegalizerHelper::legalizeInstrStep(), llvm::AArch64CallLowering::lowerReturn(), llvm::LegalizerHelper::narrowScalar(), llvm::LegalizerHelper::narrowScalarExtract(), and llvm::LegalizerHelper::narrowScalarInsert().

◆ buildBuildVectorTrunc()

MachineInstrBuilder MachineIRBuilder::buildBuildVectorTrunc ( const DstOp Res,
ArrayRef< Register Ops 
)

Build and insert Res = G_BUILD_VECTOR_TRUNC Op0, ...

G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers which have types larger than the destination vector element type, and truncates the values to fit.

If the operands given are already the same size as the vector elt type, then this method will instead create a G_BUILD_VECTOR instruction.

Precondition
setBasicBlock or setMI must have been called.
The type of all Ops registers must be identical.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 620 of file MachineIRBuilder.cpp.

References llvm::ArrayRef< T >::begin(), buildInstr(), and llvm::ArrayRef< T >::end().

◆ buildCast()

MachineInstrBuilder MachineIRBuilder::buildCast ( const DstOp Dst,
const SrcOp Src 
)

Build and insert an appropriate cast between two registers of equal size.

Definition at line 475 of file MachineIRBuilder.cpp.

References assert(), buildCopy(), buildInstr(), llvm::DstOp::getLLTTy(), llvm::SrcOp::getLLTTy(), getMRI(), llvm::LLT::isPointer(), and llvm::LLT::isScalar().

Referenced by buildExtract(), buildInsert(), buildInstr(), and getOffsetFromIndices().

◆ buildConcatVectors()

MachineInstrBuilder MachineIRBuilder::buildConcatVectors ( const DstOp Res,
ArrayRef< Register Ops 
)

Build and insert Res = G_CONCAT_VECTORS Op0, ...

G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more vectors.

Precondition
setBasicBlock or setMI must have been called.
The entire register Res (and no more) must be covered by the input registers.
The type of all source operands must be identical.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 630 of file MachineIRBuilder.cpp.

References llvm::ArrayRef< T >::begin(), buildInstr(), and llvm::ArrayRef< T >::end().

Referenced by llvm::LegalizerHelper::fewerElementsVectorBasic(), llvm::LegalizerHelper::fewerElementsVectorCasts(), llvm::LegalizerHelper::fewerElementsVectorCmp(), llvm::LegalizerHelper::fewerElementsVectorImplicitDef(), llvm::LegalizerHelper::fewerElementsVectorSelect(), llvm::LegalizerHelper::legalizeInstrStep(), and llvm::LegalizerHelper::narrowScalar().

◆ buildConstant() [1/3]

MachineInstrBuilder MachineIRBuilder::buildConstant ( const DstOp Res,
const ConstantInt Val 
)
virtual

Build and insert Res = G_CONSTANT Val.

G_CONSTANT is an integer constant with the specified size and value. Val will be extended or truncated to the size of Reg.

Precondition
setBasicBlock or setMI must have been called.
Res must be a generic virtual register with scalar or pointer type.
Returns
The newly created instruction.

Reimplemented in llvm::CSEMIRBuilder.

Definition at line 271 of file MachineIRBuilder.cpp.

References llvm::MachineInstrBuilder::addCImm(), llvm::MachineInstrBuilder::addDef(), llvm::DstOp::addDefToMIB(), assert(), buildInstr(), buildSplatVector(), llvm::ConstantInt::getBitWidth(), llvm::DstOp::getLLTTy(), getMRI(), llvm::LLT::getScalarSizeInBits(), llvm::LLT::getScalarType(), and llvm::LLT::isVector().

Referenced by llvm::AArch64CallLowering::AArch64CallLowering(), llvm::CSEMIRBuilder::buildConstant(), buildConstant(), llvm::ConstantFoldingMIRBuilder::buildInstr(), extractF64Exponent(), llvm::IRTranslator::getAnalysisUsage(), getOffsetFromIndices(), getOtherVRegDef(), llvm::AMDGPULegalizerInfo::getSegmentAperture(), isSupportedType(), llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast(), llvm::ARMLegalizerInfo::legalizeCustom(), llvm::AMDGPULegalizerInfo::legalizeImplicitArgPtr(), llvm::AArch64LegalizerInfo::legalizeIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc(), llvm::AMDGPULegalizerInfo::legalizeITOFP(), llvm::AMDGPULegalizerInfo::loadInputValue(), llvm::LegalizerHelper::lower(), llvm::LegalizerHelper::lowerBitCount(), llvm::LegalizerHelper::lowerFCopySign(), llvm::AMDGPUCallLowering::lowerReturn(), llvm::LegalizerHelper::lowerSITOFP(), llvm::LegalizerHelper::lowerU64ToF32BitOps(), materializeGEP(), llvm::LegalizerHelper::narrowScalar(), llvm::LegalizerHelper::narrowScalarShift(), llvm::LegalizerHelper::narrowScalarShiftByConstant(), substituteSimpleCopyRegs(), llvm::LegalizationArtifactCombiner::tryCombineAnyExt(), llvm::LegalizationArtifactCombiner::tryCombineSExt(), llvm::LegalizationArtifactCombiner::tryCombineZExt(), llvm::LegalizationArtifactCombiner::tryFoldImplicitDef(), llvm::LegalizerHelper::widenScalar(), and llvm::X86CallLowering::X86CallLowering().

◆ buildConstant() [2/3]

MachineInstrBuilder MachineIRBuilder::buildConstant ( const DstOp Res,
int64_t  Val 
)

Build and insert Res = G_CONSTANT Val.

G_CONSTANT is an integer constant with the specified size and value.

Precondition
setBasicBlock or setMI must have been called.
Res must be a generic virtual register with scalar type.
Returns
The newly created instruction.

Definition at line 291 of file MachineIRBuilder.cpp.

References buildConstant(), llvm::IntegerType::get(), llvm::ConstantInt::get(), getFunction(), llvm::DstOp::getLLTTy(), getMF(), getMRI(), and llvm::LLT::getScalarSizeInBits().

◆ buildConstant() [3/3]

MachineInstrBuilder MachineIRBuilder::buildConstant ( const DstOp Res,
const APInt Val 
)

◆ buildConstDbgValue()

MachineInstrBuilder MachineIRBuilder::buildConstDbgValue ( const Constant C,
const MDNode Variable,
const MDNode Expr 
)

Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified by Expr).

Definition at line 130 of file MachineIRBuilder.cpp.

References assert(), buildInstr(), and getDL().

Referenced by getOffsetFromIndices().

◆ buildCopy()

MachineInstrBuilder MachineIRBuilder::buildCopy ( const DstOp Res,
const SrcOp Op 
)

◆ buildCTLZ()

MachineInstrBuilder llvm::MachineIRBuilder::buildCTLZ ( const DstOp Dst,
const SrcOp Src0 
)
inline

Build and insert Res = G_CTLZ Op0, Src0.

Definition at line 1282 of file MachineIRBuilder.h.

◆ buildCTLZ_ZERO_UNDEF()

MachineInstrBuilder llvm::MachineIRBuilder::buildCTLZ_ZERO_UNDEF ( const DstOp Dst,
const SrcOp Src0 
)
inline

Build and insert Res = G_CTLZ_ZERO_UNDEF Op0, Src0.

Definition at line 1287 of file MachineIRBuilder.h.

Referenced by llvm::LegalizerHelper::lowerU64ToF32BitOps().

◆ buildCTPOP()

MachineInstrBuilder llvm::MachineIRBuilder::buildCTPOP ( const DstOp Dst,
const SrcOp Src0 
)
inline

Build and insert Res = G_CTPOP Op0, Src0.

Definition at line 1277 of file MachineIRBuilder.h.

◆ buildCTTZ()

MachineInstrBuilder llvm::MachineIRBuilder::buildCTTZ ( const DstOp Dst,
const SrcOp Src0 
)
inline

Build and insert Res = G_CTTZ Op0, Src0.

Definition at line 1292 of file MachineIRBuilder.h.

◆ buildCTTZ_ZERO_UNDEF()

MachineInstrBuilder llvm::MachineIRBuilder::buildCTTZ_ZERO_UNDEF ( const DstOp Dst,
const SrcOp Src0 
)
inline

Build and insert Res = G_CTTZ_ZERO_UNDEF Op0, Src0.

Definition at line 1297 of file MachineIRBuilder.h.

◆ buildDbgLabel()

MachineInstrBuilder MachineIRBuilder::buildDbgLabel ( const MDNode Label)

Build and insert a DBG_LABEL instructions specifying that Label is given.

Convert "llvm.dbg.label Label" to "DBG_LABEL Label".

Definition at line 154 of file MachineIRBuilder.cpp.

References assert(), buildInstr(), and llvm::MachineIRBuilderState::DL.

Referenced by getOffsetFromIndices().

◆ buildDirectDbgValue()

MachineInstrBuilder MachineIRBuilder::buildDirectDbgValue ( Register  Reg,
const MDNode Variable,
const MDNode Expr 
)

Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Reg (suitably modified by Expr).

Definition at line 90 of file MachineIRBuilder.cpp.

References assert(), llvm::BuildMI(), getDL(), getMF(), getTII(), and insertInstr().

Referenced by getOffsetFromIndices().

◆ buildExtOrTrunc()

MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc ( unsigned  ExtOpc,
const DstOp Res,
const SrcOp Op 
)

Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of Res and Op.

///

Precondition
setBasicBlock or setMI must have been called.
Res must be a generic virtual register with scalar or vector type.
Op must be a generic virtual register with scalar or vector type.
Returns
The newly created instruction.

Definition at line 436 of file MachineIRBuilder.cpp.

References assert(), buildInstr(), llvm::DstOp::getLLTTy(), llvm::SrcOp::getLLTTy(), getMRI(), llvm::LLT::getSizeInBits(), llvm::LLT::isScalar(), and llvm::LLT::isVector().

Referenced by buildAnyExtOrTrunc(), buildSExtOrTrunc(), and buildZExtOrTrunc().

◆ buildExtract()

MachineInstrBuilder MachineIRBuilder::buildExtract ( const DstOp Res,
const SrcOp Src,
uint64_t  Index 
)

◆ buildExtractVectorElement()

MachineInstrBuilder MachineIRBuilder::buildExtractVectorElement ( const DstOp Res,
const SrcOp Val,
const SrcOp Idx 
)

Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.

Precondition
setBasicBlock or setMI must have been called.
Res must be a generic virtual register with scalar type.
Val must be a generic virtual register with vector type.
Idx must be a generic virtual register with scalar type.
Returns
The newly created instruction.

Definition at line 720 of file MachineIRBuilder.cpp.

References buildInstr().

Referenced by getOffsetFromIndices(), and getOtherVRegDef().

◆ buildFAbs()

MachineInstrBuilder llvm::MachineIRBuilder::buildFAbs ( const DstOp Dst,
const SrcOp Src0 
)
inline

Build and insert Res = G_FABS Op0.

Definition at line 1325 of file MachineIRBuilder.h.

Referenced by llvm::AMDGPULegalizerInfo::legalizeFrint().

◆ buildFAdd()

MachineInstrBuilder llvm::MachineIRBuilder::buildFAdd ( const DstOp Dst,
const SrcOp Src0,
const SrcOp Src1 
)
inline

◆ buildFCanonicalize()

MachineInstrBuilder llvm::MachineIRBuilder::buildFCanonicalize ( const DstOp Dst,
const SrcOp Src0,
Optional< unsigned Flags = None 
)
inline

Build and insert Dst = G_FCANONICALIZE Src0.

Definition at line 1330 of file MachineIRBuilder.h.

Referenced by llvm::LegalizerHelper::lowerFMinNumMaxNum().

◆ buildFCmp()

MachineInstrBuilder MachineIRBuilder::buildFCmp ( CmpInst::Predicate  Pred,
const DstOp Res,
const SrcOp Op0,
const SrcOp Op1 
)

Build and insert a Res = G_FCMP PredOp0, Op1.

Precondition
setBasicBlock or setMI must have been called.
Res must be a generic virtual register with scalar or vector type. Typically this starts as s1 or <N x="" s1>="">.
Op0 and Op1 must be generic virtual registers with the same number of elements as Res (or scalar, if Res is scalar).
Pred must be a floating-point predicate.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 697 of file MachineIRBuilder.cpp.

References buildInstr().

Referenced by llvm::LegalizerHelper::fewerElementsVectorCmp(), and llvm::AMDGPULegalizerInfo::legalizeFceil().

◆ buildFConstant() [1/3]

MachineInstrBuilder MachineIRBuilder::buildFConstant ( const DstOp Res,
const ConstantFP Val 
)
virtual

Build and insert Res = G_FCONSTANT Val.

G_FCONSTANT is a floating-point constant with the specified size and value.

Precondition
setBasicBlock or setMI must have been called.
Res must be a generic virtual register with scalar type.
Returns
The newly created instruction.

Reimplemented in llvm::CSEMIRBuilder.

Definition at line 299 of file MachineIRBuilder.cpp.

References llvm::MachineInstrBuilder::addDef(), llvm::DstOp::addDefToMIB(), llvm::MachineInstrBuilder::addFPImm(), assert(), buildInstr(), buildSplatVector(), llvm::DstOp::getLLTTy(), getMRI(), llvm::LLT::getScalarType(), llvm::APFloat::getSemantics(), llvm::LLT::getSizeInBits(), llvm::APFloatBase::getSizeInBits(), llvm::ConstantFP::getValueAPF(), llvm::LLT::isPointer(), and llvm::LLT::isVector().

Referenced by llvm::CSEMIRBuilder::buildFConstant(), buildFConstant(), llvm::AMDGPULegalizerInfo::legalizeFceil(), llvm::AMDGPULegalizerInfo::legalizeFrint(), and llvm::LegalizerHelper::lower().

◆ buildFConstant() [2/3]

MachineInstrBuilder MachineIRBuilder::buildFConstant ( const DstOp Res,
double  Val 
)

◆ buildFConstant() [3/3]

MachineInstrBuilder MachineIRBuilder::buildFConstant ( const DstOp Res,
const APFloat Val 
)

◆ buildFCopysign()

MachineInstrBuilder llvm::MachineIRBuilder::buildFCopysign ( const DstOp Dst,
const SrcOp Src0,
const SrcOp Src1 
)
inline

Build and insert Res = G_FCOPYSIGN Op0, Op1.

Definition at line 1336 of file MachineIRBuilder.h.

Referenced by llvm::AMDGPULegalizerInfo::legalizeFrint().

◆ buildFence()

MachineInstrBuilder MachineIRBuilder::buildFence ( unsigned  Ordering,
unsigned  Scope 
)

Build and insert G_FENCE Ordering, Scope.

Definition at line 868 of file MachineIRBuilder.cpp.

References llvm::MachineInstrBuilder::addImm(), and buildInstr().

Referenced by getOffsetFromIndices().

◆ buildFIDbgValue()

MachineInstrBuilder MachineIRBuilder::buildFIDbgValue ( int  FI,
const MDNode Variable,
const MDNode Expr 
)

Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in the stack slot specified by FI (suitably modified by Expr).

Definition at line 115 of file MachineIRBuilder.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMetadata(), assert(), buildInstr(), and getDL().

◆ buildFMA()

MachineInstrBuilder llvm::MachineIRBuilder::buildFMA ( const DstOp Dst,
const SrcOp Src0,
const SrcOp Src1,
const SrcOp Src2 
)
inline

Build and insert Res = G_FMA Op0, Op1, Op2.

Definition at line 1314 of file MachineIRBuilder.h.

◆ buildFNeg()

MachineInstrBuilder llvm::MachineIRBuilder::buildFNeg ( const DstOp Dst,
const SrcOp Src0 
)
inline

Build and insert Res = G_FNEG Op0.

Definition at line 1320 of file MachineIRBuilder.h.

Referenced by llvm::LegalizerHelper::lowerSITOFP().

◆ buildFPTOSI()

MachineInstrBuilder llvm::MachineIRBuilder::buildFPTOSI ( const DstOp Dst,
const SrcOp Src0 
)
inline

Build and insert Res = G_FPTOSI Src0.

Definition at line 1357 of file MachineIRBuilder.h.

◆ buildFPTOUI()

MachineInstrBuilder llvm::MachineIRBuilder::buildFPTOUI ( const DstOp Dst,
const SrcOp Src0 
)
inline

Build and insert Res = G_FPTOUI Src0.

Definition at line 1352 of file MachineIRBuilder.h.

◆ buildFPTrunc()

MachineInstrBuilder MachineIRBuilder::buildFPTrunc ( const DstOp Res,
const SrcOp Op 
)

Build and insert Res = G_FPTRUNC Op.

G_FPTRUNC converts a floating-point value into one with a smaller type.

Precondition
setBasicBlock or setMI must have been called.
Res must be a generic virtual register with scalar or vector type.
Op must be a generic virtual register with scalar or vector type.
Res must be smaller than Op
Returns
The newly created instruction.

Definition at line 685 of file MachineIRBuilder.cpp.

References buildInstr().

◆ buildFrameIndex()

MachineInstrBuilder MachineIRBuilder::buildFrameIndex ( const DstOp Res,
int  Idx 
)

Build and insert Res = G_FRAME_INDEX Idx.

G_FRAME_INDEX materializes the address of an alloca value or other stack-based object.

Precondition
setBasicBlock or setMI must have been called.
Res must be a generic virtual register with pointer type.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 163 of file MachineIRBuilder.cpp.

References llvm::DstOp::addDefToMIB(), assert(), buildInstr(), llvm::DstOp::getLLTTy(), getMRI(), and llvm::LLT::isPointer().

Referenced by llvm::AArch64CallLowering::AArch64CallLowering(), getOffsetFromIndices(), llvm::X86CallLowering::lowerReturn(), and llvm::ARMCallLowering::lowerReturn().

◆ buildFSub()

MachineInstrBuilder llvm::MachineIRBuilder::buildFSub ( const DstOp Dst,
const SrcOp Src0,
const SrcOp Src1 
)
inline

Build and insert Res = G_FSUB Op0, Op1.

Definition at line 1308 of file MachineIRBuilder.h.

Referenced by llvm::AMDGPULegalizerInfo::legalizeFrint().

◆ buildGEP()

MachineInstrBuilder MachineIRBuilder::buildGEP ( const DstOp Res,
const SrcOp Op0,
const SrcOp Op1 
)

Build and insert Res = G_GEP Op0, Op1.

G_GEP adds Op1 bytes to the pointer specified by Op0, storing the resulting pointer in Res.

Precondition
setBasicBlock or setMI must have been called.
Res and Op0 must be generic virtual registers with pointer type.
Op1 must be a generic virtual register with scalar type.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 203 of file MachineIRBuilder.cpp.

References llvm::DstOp::addDefToMIB(), llvm::SrcOp::addSrcToMIB(), assert(), buildInstr(), llvm::DstOp::getLLTTy(), llvm::SrcOp::getLLTTy(), getMRI(), llvm::LLT::isPointer(), and llvm::LLT::isScalar().

Referenced by llvm::AArch64CallLowering::AArch64CallLowering(), getOffsetFromIndices(), isSupportedType(), llvm::AMDGPULegalizerInfo::legalizeImplicitArgPtr(), llvm::AArch64LegalizerInfo::legalizeIntrinsic(), llvm::AMDGPUCallLowering::lowerReturn(), materializeGEP(), and llvm::X86CallLowering::X86CallLowering().

◆ buildGlobalValue()

MachineInstrBuilder MachineIRBuilder::buildGlobalValue ( const DstOp Res,
const GlobalValue GV 
)

Build and insert Res = G_GLOBAL_VALUE GV.

G_GLOBAL_VALUE materializes the address of the specified global into Res.

Precondition
setBasicBlock or setMI must have been called.
Res must be a generic virtual register with pointer type in the same address space as GV.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 172 of file MachineIRBuilder.cpp.

References llvm::DstOp::addDefToMIB(), assert(), buildInstr(), llvm::LLT::getAddressSpace(), llvm::PointerType::getAddressSpace(), llvm::DstOp::getLLTTy(), getMRI(), llvm::GlobalValue::getType(), and llvm::LLT::isPointer().

Referenced by llvm::MipsCallLowering::lowerCall().

◆ buildICmp()

MachineInstrBuilder MachineIRBuilder::buildICmp ( CmpInst::Predicate  Pred,
const DstOp Res,
const SrcOp Op0,
const SrcOp Op1 
)

Build and insert a Res = G_ICMP Pred, Op0, Op1.

Precondition
setBasicBlock or setMI must have been called.
Res must be a generic virtual register with scalar or vector type. Typically this starts as s1 or <N x="" s1>="">.
Op0 and Op1 must be generic virtual registers with the same number of elements as Res. If Res is a scalar, Op0 must be either a scalar or pointer.
Pred must be an integer predicate.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 690 of file MachineIRBuilder.cpp.

References buildInstr().

Referenced by llvm::LegalizerHelper::fewerElementsVectorCmp(), llvm::IRTranslator::getAnalysisUsage(), llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast(), llvm::ARMLegalizerInfo::legalizeCustom(), llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc(), llvm::LegalizerHelper::lower(), llvm::LegalizerHelper::lowerBitCount(), llvm::LegalizerHelper::lowerMinMax(), llvm::LegalizerHelper::lowerSITOFP(), llvm::LegalizerHelper::lowerU64ToF32BitOps(), llvm::LegalizerHelper::narrowScalar(), llvm::LegalizerHelper::narrowScalarShift(), and llvm::LegalizerHelper::widenScalar().

◆ buildIndirectDbgValue()

MachineInstrBuilder MachineIRBuilder::buildIndirectDbgValue ( Register  Reg,
const MDNode Variable,
const MDNode Expr 
)

Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in memory at Reg (suitably modified by Expr).

Definition at line 103 of file MachineIRBuilder.cpp.

References assert(), llvm::BuildMI(), getDL(), getMF(), getTII(), and insertInstr().

Referenced by getOffsetFromIndices().

◆ buildInsert()

MachineInstrBuilder MachineIRBuilder::buildInsert ( Register  Res,
Register  Src,
Register  Op,
unsigned  Index 
)

◆ buildInsertVectorElement()

MachineInstrBuilder MachineIRBuilder::buildInsertVectorElement ( const DstOp Res,
const SrcOp Val,
const SrcOp Elt,
const SrcOp Idx 
)

Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.

Precondition
setBasicBlock or setMI must have been called.
Res and Val must be a generic virtual register
Elt and Idx must be a generic virtual register with scalar type.
Returns
The newly created instruction.

Definition at line 714 of file MachineIRBuilder.cpp.

References buildInstr().

Referenced by getOffsetFromIndices().

◆ buildInstr() [1/2]

MachineInstrBuilder MachineIRBuilder::buildInstr ( unsigned  Opcode)

Build and insert <empty> = Opcode <empty>.

The insertion point is the one set by the last call of either setBasicBlock or setMI.

Precondition
setBasicBlock or setMI must have been called.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 74 of file MachineIRBuilder.cpp.

References buildInstrNoInsert(), and insertInstr().

Referenced by buildAnyExt(), buildAtomicCmpXchg(), buildAtomicCmpXchgWithSuccess(), buildAtomicRMW(), buildBlockAddress(), buildBoolExt(), buildBr(), buildBrCond(), buildBrIndirect(), buildBrJT(), buildBuildVector(), buildBuildVectorTrunc(), buildCast(), buildConcatVectors(), buildConstant(), buildConstDbgValue(), buildCopy(), buildDbgLabel(), buildExtOrTrunc(), buildExtract(), buildExtractVectorElement(), buildFCmp(), buildFConstant(), buildFence(), buildFIDbgValue(), buildFPTrunc(), buildFrameIndex(), buildGEP(), buildGlobalValue(), buildICmp(), buildInsert(), buildInsertVectorElement(), llvm::ConstantFoldingMIRBuilder::buildInstr(), llvm::CSEMIRBuilder::buildInstr(), buildInstr(), buildIntrinsic(), buildJumpTable(), buildLoadInstr(), buildMerge(), buildPtrMask(), buildSelect(), buildSExt(), buildSplatVector(), buildStore(), buildTrunc(), buildUAdde(), buildUAddo(), buildUndef(), buildUnmerge(), buildZExt(), changeFCMPPredToAArch64CC(), llvm::LegalizerHelper::fewerElementsVectorBasic(), llvm::LegalizerHelper::fewerElementsVectorCasts(), llvm::LegalizerHelper::fewerElementsVectorPhi(), llvm::IRTranslator::getAnalysisUsage(), getHalfSizedType(), getInsertVecEltOpInfo(), llvm::AMDGPURegisterBankInfo::getInstrAlternativeMappings(), getLaneCopyOpcode(), getOffsetFromIndices(), llvm::AMDGPULegalizerInfo::getSegmentAperture(), getStlxrOpcode(), llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast(), llvm::AMDGPULegalizerInfo::legalizeFceil(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), llvm::LegalizerHelper::lower(), llvm::LegalizerHelper::lowerBitCount(), llvm::X86CallLowering::lowerCall(), llvm::ARMCallLowering::lowerCall(), llvm::AArch64CallLowering::lowerCall(), llvm::MipsCallLowering::lowerCall(), llvm::LegalizerHelper::lowerFMinNumMaxNum(), llvm::AMDGPUCallLowering::lowerReturn(), llvm::AArch64CallLowering::lowerReturn(), llvm::LegalizerHelper::narrowScalar(), llvm::LegalizerHelper::narrowScalarBasic(), selectSubregisterCopy(), substituteSimpleCopyRegs(), llvm::LegalizationArtifactCombiner::tryCombineAnyExt(), llvm::LegalizationArtifactCombiner::tryCombineMerges(), llvm::LegalizationArtifactCombiner::tryCombineSExt(), llvm::LegalizationArtifactCombiner::tryFoldImplicitDef(), and llvm::LegalizerHelper::widenScalar().

◆ buildInstr() [2/2]

MachineInstrBuilder MachineIRBuilder::buildInstr ( unsigned  Opc,
ArrayRef< DstOp DstOps,
ArrayRef< SrcOp SrcOps,
Optional< unsigned Flags = None 
)
virtual

◆ buildInstrNoInsert()

MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert ( unsigned  Opcode)

◆ buildIntrinsic() [1/2]

MachineInstrBuilder MachineIRBuilder::buildIntrinsic ( Intrinsic::ID  ID,
ArrayRef< Register Res,
bool  HasSideEffects 
)

Build and insert either a G_INTRINSIC (if HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS instruction.

Its first operand will be the result register definition unless Reg is NoReg (== 0). The second operand will be the intrinsic's ID.

Callers are expected to add the required definitions and uses afterwards.

Precondition
setBasicBlock or setMI must have been called.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 656 of file MachineIRBuilder.cpp.

References buildInstr().

Referenced by extractF64Exponent(), getOffsetFromIndices(), and llvm::AMDGPULegalizerInfo::legalizeITOFP().

◆ buildIntrinsic() [2/2]

MachineInstrBuilder MachineIRBuilder::buildIntrinsic ( Intrinsic::ID  ID,
ArrayRef< DstOp Res,
bool  HasSideEffects 
)

Definition at line 668 of file MachineIRBuilder.cpp.

References buildInstr(), and getMRI().

◆ buildJumpTable()

MachineInstrBuilder MachineIRBuilder::buildJumpTable ( const LLT  PtrTy,
unsigned  JTI 
)

Build and insert Res = G_JUMP_TABLE JTI.

G_JUMP_TABLE sets Res to the address of the jump table specified by the jump table index JTI.

Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 185 of file MachineIRBuilder.cpp.

References buildInstr().

Referenced by llvm::IRTranslator::getAnalysisUsage().

◆ buildLoad()

MachineInstrBuilder MachineIRBuilder::buildLoad ( const DstOp Res,
const SrcOp Addr,
MachineMemOperand MMO 
)

Build and insert Res = G_LOAD Addr, MMO.

Loads the value stored at Addr. Puts the result in Res.

Precondition
setBasicBlock or setMI must have been called.
Res must be a generic virtual register.
Addr must be a generic virtual register with pointer type.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 353 of file MachineIRBuilder.cpp.

References buildLoadInstr().

Referenced by llvm::AArch64CallLowering::AArch64CallLowering(), llvm::AMDGPULegalizerInfo::getSegmentAperture(), llvm::MipsCallLowering::MipsHandler::handle(), isSwiftError(), llvm::AArch64LegalizerInfo::legalizeIntrinsic(), llvm::LegalizerHelper::lower(), llvm::X86CallLowering::lowerReturn(), llvm::ARMCallLowering::lowerReturn(), llvm::AMDGPUCallLowering::lowerReturn(), llvm::LegalizerHelper::narrowScalar(), and llvm::LegalizerHelper::reduceLoadStoreWidth().

◆ buildLoadInstr()

MachineInstrBuilder MachineIRBuilder::buildLoadInstr ( unsigned  Opcode,
const DstOp Res,
const SrcOp Addr,
MachineMemOperand MMO 
)

Build and insert Res = <opcode> Addr, MMO.

Loads the value stored at Addr. Puts the result in Res.

Precondition
setBasicBlock or setMI must have been called.
Res must be a generic virtual register.
Addr must be a generic virtual register with pointer type.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 359 of file MachineIRBuilder.cpp.

References llvm::DstOp::addDefToMIB(), llvm::SrcOp::addSrcToMIB(), assert(), buildInstr(), llvm::DstOp::getLLTTy(), llvm::SrcOp::getLLTTy(), getMRI(), llvm::LLT::isPointer(), and llvm::LLT::isValid().

Referenced by buildLoad().

◆ buildLShr()

MachineInstrBuilder llvm::MachineIRBuilder::buildLShr ( const DstOp Dst,
const SrcOp Src0,
const SrcOp Src1,
Optional< unsigned Flags = None 
)
inline

◆ buildMerge()

MachineInstrBuilder MachineIRBuilder::buildMerge ( const DstOp Res,
ArrayRef< Register Ops 
)

◆ buildMul()

MachineInstrBuilder llvm::MachineIRBuilder::buildMul ( const DstOp Dst,
const SrcOp Src0,
const SrcOp Src1,
Optional< unsigned Flags = None 
)
inline

Build and insert Res = G_MUL Op0, Op1.

G_MUL sets Res to the sum of integer parameters Op0 and Op1, truncated to their width.

Precondition
setBasicBlock or setMI must have been called.
Res, Op0 and Op1 must be generic virtual registers with the same (scalar or vector) type).
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 1195 of file MachineIRBuilder.h.

Referenced by getOffsetFromIndices(), llvm::LegalizerHelper::lower(), and llvm::LegalizerHelper::moreElementsVector().

◆ buildNot()

MachineInstrBuilder llvm::MachineIRBuilder::buildNot ( const DstOp Dst,
const SrcOp Src0 
)
inline

Build and insert a bitwise not, NegOne = G_CONSTANT -1 Res = G_OR Op0, NegOne.

Definition at line 1271 of file MachineIRBuilder.h.

References llvm::DstOp::getLLTTy().

Referenced by llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc().

◆ buildOr()

MachineInstrBuilder llvm::MachineIRBuilder::buildOr ( const DstOp Dst,
const SrcOp Src0,
const SrcOp Src1 
)
inline

Build and insert Res = G_OR Op0, Op1.

G_OR sets Res to the bitwise or of integer parameters Op0 and Op1.

Precondition
setBasicBlock or setMI must have been called.
Res, Op0 and Op1 must be generic virtual registers with the same (scalar or vector) type).
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 1257 of file MachineIRBuilder.h.

Referenced by llvm::ARMLegalizerInfo::legalizeCustom(), llvm::LegalizerHelper::lowerFCopySign(), llvm::LegalizerHelper::lowerU64ToF32BitOps(), llvm::LegalizerHelper::narrowScalar(), llvm::LegalizerHelper::narrowScalarShift(), llvm::LegalizerHelper::narrowScalarShiftByConstant(), and llvm::LegalizerHelper::widenScalar().

◆ buildPtrMask()

MachineInstrBuilder MachineIRBuilder::buildPtrMask ( const DstOp Res,
const SrcOp Op0,
uint32_t  NumBits 
)

Build and insert Res = G_PTR_MASK Op0, NumBits.

G_PTR_MASK clears the low bits of a pointer operand without destroying its pointer properties. This has the effect of rounding the address down to a specified alignment in bits.

Precondition
setBasicBlock or setMI must have been called.
Res and Op0 must be generic virtual registers with pointer type.
NumBits must be an integer representing the number of low bits to be cleared in Op0.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 233 of file MachineIRBuilder.cpp.

References llvm::DstOp::addDefToMIB(), llvm::SrcOp::addSrcToMIB(), assert(), buildInstr(), llvm::DstOp::getLLTTy(), llvm::SrcOp::getLLTTy(), getMRI(), and llvm::LLT::isPointer().

Referenced by getOffsetFromIndices(), and llvm::AArch64LegalizerInfo::legalizeIntrinsic().

◆ buildPtrToInt()

MachineInstrBuilder llvm::MachineIRBuilder::buildPtrToInt ( const DstOp Dst,
const SrcOp Src 
)
inline

Build and insert a G_PTRTOINT instruction.

Definition at line 488 of file MachineIRBuilder.h.

Referenced by llvm::LegalizerHelper::narrowScalar().

◆ buildSelect()

MachineInstrBuilder MachineIRBuilder::buildSelect ( const DstOp Res,
const SrcOp Tst,
const SrcOp Op0,
const SrcOp Op1 
)

Build and insert a Res = G_SELECT Tst, Op0, Op1.

Precondition
setBasicBlock or setMI must have been called.
Res, Op0 and Op1 must be generic virtual registers with the same type.
Tst must be a generic virtual register with scalar, pointer or vector type. If vector then it must have the same number of elements as the other parameters.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 705 of file MachineIRBuilder.cpp.

References buildInstr().

Referenced by llvm::LegalizerHelper::fewerElementsVectorSelect(), llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast(), llvm::AMDGPULegalizerInfo::legalizeFceil(), llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc(), llvm::LegalizerHelper::lower(), llvm::LegalizerHelper::lowerBitCount(), llvm::LegalizerHelper::lowerMinMax(), llvm::LegalizerHelper::lowerSITOFP(), llvm::LegalizerHelper::lowerU64ToF32BitOps(), llvm::LegalizerHelper::narrowScalar(), llvm::LegalizerHelper::narrowScalarSelect(), llvm::LegalizerHelper::narrowScalarShift(), and substituteSimpleCopyRegs().

◆ buildSequence()

void MachineIRBuilder::buildSequence ( Register  Res,
ArrayRef< Register Ops,
ArrayRef< uint64_t >  Indices 
)

Build and insert instructions to put Ops together at the specified p Indices to form a larger register.

If the types of the input registers are uniform and cover the entirity of Res then a G_MERGE_VALUES will be produced. Otherwise an IMPLICIT_DEF followed by a sequence of G_INSERT instructions.

Precondition
setBasicBlock or setMI must have been called.
The final element of the sequence must not extend past the end of the destination register.
The bits defined by each Op (derived from index and scalar size) must not overlap.
Indices must be in ascending order of bit position.

Definition at line 520 of file MachineIRBuilder.cpp.

References assert(), llvm::ArrayRef< T >::begin(), buildInsert(), buildMerge(), buildUndef(), llvm::MachineRegisterInfo::createGenericVirtualRegister(), llvm::ArrayRef< T >::empty(), llvm::ArrayRef< T >::end(), getMRI(), llvm::LLT::getSizeInBits(), getType(), llvm::MachineRegisterInfo::getType(), and llvm::ArrayRef< T >::size().

◆ buildSExt()

MachineInstrBuilder MachineIRBuilder::buildSExt ( const DstOp Res,
const SrcOp Op 
)

Build and insert Res = G_SEXT Op.

G_SEXT produces a register of the specified width, with bits 0 to sizeof(Ty) * 8 set to Op. The remaining bits are duplicated from the high bit of Op (i.e. 2s-complement sign extended).

Precondition
setBasicBlock or setMI must have been called.
Res must be a generic virtual register with scalar or vector type.
Op must be a generic virtual register with scalar or vector type.
Op must be smaller than Res
Returns
The newly created instruction.

Definition at line 407 of file MachineIRBuilder.cpp.

References buildInstr().

Referenced by llvm::CallLowering::ValueHandler::extendRegister(), llvm::LegalizerHelper::lower(), and llvm::LegalizerHelper::narrowScalar().

◆ buildSExtOrTrunc()

MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc ( const DstOp Res,
const SrcOp Op 
)

Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of Res and Op.

///

Precondition
setBasicBlock or setMI must have been called.
Res must be a generic virtual register with scalar or vector type.
Op must be a generic virtual register with scalar or vector type.
Returns
The newly created instruction.

Definition at line 460 of file MachineIRBuilder.cpp.

References buildExtOrTrunc().

Referenced by getOffsetFromIndices(), and substituteSimpleCopyRegs().

◆ buildShl()

MachineInstrBuilder llvm::MachineIRBuilder::buildShl ( const DstOp Dst,
const SrcOp Src0,
const SrcOp Src1,
Optional< unsigned Flags = None 
)
inline

◆ buildSITOFP()

MachineInstrBuilder llvm::MachineIRBuilder::buildSITOFP ( const DstOp Dst,
const SrcOp Src0 
)
inline

Build and insert Res = G_SITOFP Src0.

Definition at line 1347 of file MachineIRBuilder.h.

Referenced by llvm::AMDGPULegalizerInfo::legalizeITOFP().

◆ buildSMax()

MachineInstrBuilder llvm::MachineIRBuilder::buildSMax ( const DstOp Dst,
const SrcOp Src0,
const SrcOp Src1 
)
inline

Build and insert Res = G_SMAX Op0, Op1.

Definition at line 1368 of file MachineIRBuilder.h.

◆ buildSMin()

MachineInstrBuilder llvm::MachineIRBuilder::buildSMin ( const DstOp Dst,
const SrcOp Src0,
const SrcOp Src1 
)
inline

Build and insert Res = G_SMIN Op0, Op1.

Definition at line 1362 of file MachineIRBuilder.h.

◆ buildSMulH()

MachineInstrBuilder llvm::MachineIRBuilder::buildSMulH ( const DstOp Dst,
const SrcOp Src0,
const SrcOp Src1,
Optional< unsigned Flags = None 
)
inline

Definition at line 1207 of file MachineIRBuilder.h.

◆ buildSplatVector()

MachineInstrBuilder MachineIRBuilder::buildSplatVector ( const DstOp Res,
const SrcOp Src 
)

Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.

Definition at line 613 of file MachineIRBuilder.cpp.

References buildInstr(), llvm::DstOp::getLLTTy(), getMRI(), and llvm::LLT::getNumElements().

Referenced by llvm::CSEMIRBuilder::buildConstant(), buildConstant(), llvm::CSEMIRBuilder::buildFConstant(), and buildFConstant().

◆ buildStore()

MachineInstrBuilder MachineIRBuilder::buildStore ( const SrcOp Val,
const SrcOp Addr,
MachineMemOperand MMO 
)

Build and insert G_STORE Val, Addr, MMO.

Stores the value Val to Addr.

Precondition
setBasicBlock or setMI must have been called.
Val must be a generic virtual register.
Addr must be a generic virtual register with pointer type.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 373 of file MachineIRBuilder.cpp.

References llvm::SrcOp::addSrcToMIB(), assert(), buildInstr(), llvm::SrcOp::getLLTTy(), getMRI(), llvm::LLT::isPointer(), and llvm::LLT::isValid().

Referenced by llvm::AArch64CallLowering::AArch64CallLowering(), getOffsetFromIndices(), isSupportedType(), isSwiftError(), llvm::AArch64LegalizerInfo::legalizeIntrinsic(), llvm::LegalizerHelper::narrowScalar(), llvm::LegalizerHelper::reduceLoadStoreWidth(), and llvm::X86CallLowering::X86CallLowering().

◆ buildSub()

MachineInstrBuilder llvm::MachineIRBuilder::buildSub ( const DstOp Dst,
const SrcOp Src0,
const SrcOp Src1,
Optional< unsigned Flags = None 
)
inline

Build and insert Res = G_SUB Op0, Op1.

G_SUB sets Res to the sum of integer parameters Op0 and Op1, truncated to their width.

Precondition
setBasicBlock or setMI must have been called.
Res, Op0 and Op1 must be generic virtual registers with the same (scalar or vector) type).
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 1179 of file MachineIRBuilder.h.

Referenced by extractF64Exponent(), llvm::IRTranslator::getAnalysisUsage(), llvm::LegalizerHelper::lower(), llvm::LegalizerHelper::lowerU64ToF32BitOps(), and llvm::LegalizerHelper::narrowScalarShift().

◆ buildTrunc()

MachineInstrBuilder MachineIRBuilder::buildTrunc ( const DstOp Res,
const SrcOp Op 
)

Build and insert Res = G_TRUNC Op.

G_TRUNC extracts the low bits of a type. For a vector type each element is truncated independently before being packed into the destination.

Precondition
setBasicBlock or setMI must have been called.
Res must be a generic virtual register with scalar or vector type.
Op must be a generic virtual register with scalar or vector type.
Res must be smaller than Op
Returns
The newly created instruction.

Definition at line 680 of file MachineIRBuilder.cpp.

References buildInstr().

Referenced by llvm::AArch64CallLowering::AArch64CallLowering(), llvm::CombinerHelper::applyCombineExtendingLoads(), llvm::CallLowering::handleAssignments(), llvm::ARMLegalizerInfo::legalizeCustom(), llvm::LegalizerHelper::lowerFCopySign(), llvm::X86CallLowering::lowerReturn(), llvm::ARMCallLowering::lowerReturn(), llvm::LegalizerHelper::lowerU64ToF32BitOps(), llvm::LegalizerHelper::narrowScalar(), substituteSimpleCopyRegs(), and llvm::LegalizerHelper::widenScalar().

◆ buildUAdde()

MachineInstrBuilder MachineIRBuilder::buildUAdde ( const DstOp Res,
const DstOp CarryOut,
const SrcOp Op0,
const SrcOp Op1,
const SrcOp CarryIn 
)

Build and insert Res, CarryOut = G_UADDE Op0, Op1, CarryIn.

G_UADDE sets Res to Op0 + Op1 + CarryIn (truncated to the bit width) and sets CarryOut to 1 if the result overflowed in unsigned arithmetic.

Precondition
setBasicBlock or setMI must have been called.
Res, Op0 and Op1 must be generic virtual registers with the same scalar type.
CarryOut and CarryIn must be generic virtual registers with the same scalar type (typically s1)
Returns
The newly created instruction.

Definition at line 393 of file MachineIRBuilder.cpp.

References buildInstr().

Referenced by llvm::LegalizerHelper::narrowScalar().

◆ buildUAddo()

MachineInstrBuilder MachineIRBuilder::buildUAddo ( const DstOp Res,
const DstOp CarryOut,
const SrcOp Op0,
const SrcOp Op1 
)

Build and insert Res, CarryOut = G_UADDO Op0, Op1.

G_UADDO sets Res to Op0 + Op1 (truncated to the bit width) and sets CarryOut to 1 if the result overflowed in unsigned arithmetic.

Precondition
setBasicBlock or setMI must have been called.
Res, Op0 and Op1 must be generic virtual registers with the same scalar type.
CarryOut must be generic virtual register with scalar type (typically s1)
Returns
The newly created instruction.

Definition at line 386 of file MachineIRBuilder.cpp.

References buildInstr().

Referenced by llvm::LegalizerHelper::moreElementsVector().

◆ buildUITOFP()

MachineInstrBuilder llvm::MachineIRBuilder::buildUITOFP ( const DstOp Dst,
const SrcOp Src0 
)
inline

Build and insert Res = G_UITOFP Src0.

Definition at line 1342 of file MachineIRBuilder.h.

Referenced by llvm::AMDGPULegalizerInfo::legalizeITOFP(), and llvm::LegalizerHelper::lowerSITOFP().

◆ buildUMax()

MachineInstrBuilder llvm::MachineIRBuilder::buildUMax ( const DstOp Dst,
const SrcOp Src0,
const SrcOp Src1 
)
inline

Build and insert Res = G_UMAX Op0, Op1.

Definition at line 1380 of file MachineIRBuilder.h.

References llvm::None.

◆ buildUMin()

MachineInstrBuilder llvm::MachineIRBuilder::buildUMin ( const DstOp Dst,
const SrcOp Src0,
const SrcOp Src1 
)
inline

Build and insert Res = G_UMIN Op0, Op1.

Definition at line 1374 of file MachineIRBuilder.h.

◆ buildUMulH()

MachineInstrBuilder llvm::MachineIRBuilder::buildUMulH ( const DstOp Dst,
const SrcOp Src0,
const SrcOp Src1,
Optional< unsigned Flags = None 
)
inline

Definition at line 1201 of file MachineIRBuilder.h.

Referenced by llvm::LegalizerHelper::moreElementsVector().

◆ buildUndef()

MachineInstrBuilder MachineIRBuilder::buildUndef ( const DstOp Res)

◆ buildUnmerge() [1/3]

MachineInstrBuilder MachineIRBuilder::buildUnmerge ( ArrayRef< LLT Res,
const SrcOp Op 
)

Build and insert Res0, ...

= G_UNMERGE_VALUES Op

G_UNMERGE_VALUES splits contiguous bits of the input into multiple

Precondition
setBasicBlock or setMI must have been called.
The entire register Res (and no more) must be covered by the input registers.
The type of all Res registers must be identical.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 575 of file MachineIRBuilder.cpp.

References assert(), llvm::ArrayRef< T >::begin(), buildInstr(), and llvm::ArrayRef< T >::end().

Referenced by buildUnmerge(), getHalfSizedType(), llvm::CallLowering::handleAssignments(), isSupportedType(), llvm::LegalizerHelper::legalizeInstrStep(), llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc(), llvm::AMDGPULegalizerInfo::legalizeITOFP(), llvm::X86CallLowering::lowerCall(), llvm::X86CallLowering::lowerReturn(), llvm::LegalizerHelper::narrowScalar(), llvm::LegalizerHelper::narrowScalarShift(), llvm::LegalizerHelper::narrowScalarShiftByConstant(), and llvm::LegalizationArtifactCombiner::tryCombineMerges().

◆ buildUnmerge() [2/3]

MachineInstrBuilder MachineIRBuilder::buildUnmerge ( ArrayRef< Register Res,
const SrcOp Op 
)

◆ buildUnmerge() [3/3]

MachineInstrBuilder MachineIRBuilder::buildUnmerge ( LLT  Res,
const SrcOp Op 
)

Build and insert an unmerge of Res sized pieces to cover Op.

Definition at line 585 of file MachineIRBuilder.cpp.

References buildUnmerge(), llvm::SrcOp::getLLTTy(), getMRI(), llvm::LLT::getSizeInBits(), I, and llvm::SmallVectorTemplateBase< T >::push_back().

◆ buildXor()

MachineInstrBuilder llvm::MachineIRBuilder::buildXor ( const DstOp Dst,
const SrcOp Src0,
const SrcOp Src1 
)
inline

Build and insert Res = G_XOR Op0, Op1.

Definition at line 1263 of file MachineIRBuilder.h.

Referenced by llvm::LegalizerHelper::lowerSITOFP(), and llvm::LegalizerHelper::narrowScalar().

◆ buildZExt()

MachineInstrBuilder MachineIRBuilder::buildZExt ( const DstOp Res,
const SrcOp Op 
)

Build and insert Res = G_ZEXT Op.

G_ZEXT produces a register of the specified width, with bits 0 to sizeof(Ty) * 8 set to Op. The remaining bits are 0. For a vector register, each element is extended individually.

Precondition
setBasicBlock or setMI must have been called.
Res must be a generic virtual register with scalar or vector type.
Op must be a generic virtual register with scalar or vector type.
Op must be smaller than Res
Returns
The newly created instruction.

Definition at line 412 of file MachineIRBuilder.cpp.

References buildInstr().

Referenced by llvm::CallLowering::ValueHandler::extendRegister(), llvm::AArch64LegalizerInfo::legalizeIntrinsic(), llvm::LegalizerHelper::lower(), llvm::LegalizerHelper::lowerFCopySign(), llvm::AArch64CallLowering::lowerReturn(), llvm::LegalizerHelper::moreElementsVector(), llvm::LegalizerHelper::narrowScalar(), and llvm::LegalizerHelper::widenScalar().

◆ buildZExtOrTrunc()

MachineInstrBuilder MachineIRBuilder::buildZExtOrTrunc ( const DstOp Res,
const SrcOp Op 
)

Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of Res and Op.

///

Precondition
setBasicBlock or setMI must have been called.
Res must be a generic virtual register with scalar or vector type.
Op must be a generic virtual register with scalar or vector type.
Returns
The newly created instruction.

Definition at line 465 of file MachineIRBuilder.cpp.

References buildExtOrTrunc().

Referenced by llvm::IRTranslator::getAnalysisUsage(), getOffsetFromIndices(), substituteSimpleCopyRegs(), and llvm::LegalizerHelper::widenScalar().

◆ getBoolExtOp()

unsigned MachineIRBuilder::getBoolExtOp ( bool  IsVec,
bool  IsFP 
) const

◆ getCSEInfo() [1/2]

GISelCSEInfo* llvm::MachineIRBuilder::getCSEInfo ( )
inline

Definition at line 266 of file MachineIRBuilder.h.

References llvm::MachineIRBuilderState::CSEInfo.

Referenced by llvm::CSEMIRBuilder::buildInstr().

◆ getCSEInfo() [2/2]

const GISelCSEInfo* llvm::MachineIRBuilder::getCSEInfo ( ) const
inline

Definition at line 267 of file MachineIRBuilder.h.

References llvm::MachineIRBuilderState::CSEInfo.

◆ getDataLayout()

const DataLayout& llvm::MachineIRBuilder::getDataLayout ( ) const
inline

Definition at line 241 of file MachineIRBuilder.h.

Referenced by getLaneCopyOpcode(), and llvm::LegalizerHelper::narrowScalar().

◆ getDebugLoc()

DebugLoc llvm::MachineIRBuilder::getDebugLoc ( )
inline

Get the current instruction's debug location.

Definition at line 302 of file MachineIRBuilder.h.

References buildGEP(), C, llvm::MachineIRBuilderState::DL, and Reg.

Referenced by getOffsetFromIndices().

◆ getDL()

const DebugLoc& llvm::MachineIRBuilder::getDL ( )
inline

◆ getInsertPt()

MachineBasicBlock::iterator llvm::MachineIRBuilder::getInsertPt ( )
inline

◆ getMBB() [1/2]

const MachineBasicBlock& llvm::MachineIRBuilder::getMBB ( ) const
inline

◆ getMBB() [2/2]

MachineBasicBlock& llvm::MachineIRBuilder::getMBB ( )
inline

Definition at line 261 of file MachineIRBuilder.h.

◆ getMF() [1/2]

MachineFunction& llvm::MachineIRBuilder::getMF ( )
inline

Getter for the function we currently build.

Definition at line 231 of file MachineIRBuilder.h.

References assert(), and llvm::MachineIRBuilderState::MF.

Referenced by llvm::AArch64CallLowering::AArch64CallLowering(), buildConstant(), buildDirectDbgValue(), buildFConstant(), buildIndirectDbgValue(), buildInstrNoInsert(), llvm::createLibcall(), llvm::createMemLibcall(), llvm::RegBankSelect::getAnalysisUsage(), getBoolExtOp(), getInsertVecEltOpInfo(), getLaneCopyOpcode(), getOtherVRegDef(), llvm::AMDGPULegalizerInfo::getSegmentAperture(), llvm::CallLowering::handleAssignments(), isSupportedType(), llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast(), llvm::ARMLegalizerInfo::legalizeCustom(), llvm::AMDGPULegalizerInfo::legalizeImplicitArgPtr(), llvm::AArch64LegalizerInfo::legalizeIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeMinNumMaxNum(), llvm::AMDGPULegalizerInfo::legalizePreloadedArgIntrin(), llvm::LegalizerHelper::libcall(), llvm::AMDGPULegalizerInfo::loadInputValue(), llvm::LegalizerHelper::lower(), llvm::X86CallLowering::lowerCall(), llvm::ARMCallLowering::lowerCall(), llvm::AArch64CallLowering::lowerCall(), llvm::MipsCallLowering::lowerCall(), llvm::X86CallLowering::lowerFormalArguments(), llvm::ARMCallLowering::lowerFormalArguments(), llvm::AArch64CallLowering::lowerFormalArguments(), llvm::AMDGPUCallLowering::lowerFormalArguments(), llvm::MipsCallLowering::lowerFormalArguments(), llvm::AMDGPUCallLowering::lowerFormalArgumentsKernel(), llvm::X86CallLowering::lowerReturn(), llvm::ARMCallLowering::lowerReturn(), llvm::AMDGPUCallLowering::lowerReturn(), llvm::AArch64CallLowering::lowerReturn(), llvm::MipsCallLowering::lowerReturn(), llvm::CallLowering::packRegs(), llvm::LegalizerHelper::reduceLoadStoreWidth(), setInsertPt(), setMBB(), llvm::CallLowering::unpackRegs(), llvm::LegalizerHelper::widenScalar(), and llvm::X86CallLowering::X86CallLowering().

◆ getMF() [2/2]

const MachineFunction& llvm::MachineIRBuilder::getMF ( ) const
inline

Definition at line 236 of file MachineIRBuilder.h.

References assert(), and llvm::MachineIRBuilderState::MF.

◆ getMRI() [1/2]

MachineRegisterInfo* llvm::MachineIRBuilder::getMRI ( )
inline

◆ getMRI() [2/2]

const MachineRegisterInfo* llvm::MachineIRBuilder::getMRI ( ) const
inline

Definition at line 250 of file MachineIRBuilder.h.

References llvm::MachineIRBuilderState::MRI.

◆ getState()

MachineIRBuilderState& llvm::MachineIRBuilder::getState ( )
inline

Getter for the State.

Definition at line 253 of file MachineIRBuilder.h.

◆ getTII()

const TargetInstrInfo& llvm::MachineIRBuilder::getTII ( )
inline

◆ insertInstr()

MachineInstrBuilder MachineIRBuilder::insertInstr ( MachineInstrBuilder  MIB)

◆ materializeGEP()

Optional< MachineInstrBuilder > MachineIRBuilder::materializeGEP ( Register Res,
Register  Op0,
const LLT ValueTy,
uint64_t  Value 
)

Materialize and insert Res = G_GEP Op0, (G_CONSTANT Value)

G_GEP adds Value bytes to the pointer specified by Op0, storing the resulting pointer in Res. If Value is zero then no G_GEP or G_CONSTANT will be created and

Precondition
Op0 will be assigned to Res.
setBasicBlock or setMI must have been called.
Op0 must be a generic virtual register with pointer type.
ValueTy must be a scalar type.
Res must be 0. This is to detect confusion between materializeGEP() and buildGEP().
Postcondition
Res will either be a new generic virtual register of the same type as Op0 or Op0 itself.
Returns
a MachineInstrBuilder for the newly created instruction.

Definition at line 218 of file MachineIRBuilder.cpp.

References assert(), buildConstant(), buildGEP(), llvm::MachineRegisterInfo::createGenericVirtualRegister(), getMRI(), getType(), llvm::LLT::isScalar(), and llvm::None.

Referenced by llvm::AMDGPULegalizerInfo::getSegmentAperture(), isSwiftError(), and llvm::LegalizerHelper::reduceLoadStoreWidth().

◆ recordInsertion()

void MachineIRBuilder::recordInsertion ( MachineInstr MI) const
protected

◆ setChangeObserver()

void MachineIRBuilder::setChangeObserver ( GISelChangeObserver Observer)

◆ setCSEInfo()

void MachineIRBuilder::setCSEInfo ( GISelCSEInfo Info)

Definition at line 49 of file MachineIRBuilder.cpp.

References llvm::MachineIRBuilderState::CSEInfo, and Info.

◆ setDebugLoc()

void llvm::MachineIRBuilder::setDebugLoc ( const DebugLoc DL)
inline

Set the debug location to DL for all the next build instructions.

Definition at line 299 of file MachineIRBuilder.h.

References llvm::MachineIRBuilderState::DL.

Referenced by llvm::IRTranslator::getAnalysisUsage().

◆ setInsertPt()

void MachineIRBuilder::setInsertPt ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  II 
)

◆ setInstr()

void MachineIRBuilder::setInstr ( MachineInstr MI)

Set the insertion point to before MI.

Precondition
MI must be in getMF().

Definition at line 43 of file MachineIRBuilder.cpp.

References assert(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getParent(), llvm::MachineIRBuilderState::II, and setMBB().

Referenced by llvm::createMemLibcall(), llvm::LegalizerHelper::fewerElementsVector(), getHalfSizedType(), llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast(), llvm::MipsLegalizerInfo::legalizeCustom(), llvm::ARMLegalizerInfo::legalizeCustom(), llvm::AMDGPULegalizerInfo::legalizeExtractVectorElt(), llvm::AMDGPULegalizerInfo::legalizeFceil(), llvm::AMDGPULegalizerInfo::legalizeFrint(), llvm::AMDGPULegalizerInfo::legalizeImplicitArgPtr(), llvm::AMDGPULegalizerInfo::legalizeInsertVectorElt(), llvm::AArch64LegalizerInfo::legalizeIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc(), llvm::AMDGPULegalizerInfo::legalizeITOFP(), llvm::AMDGPULegalizerInfo::legalizePreloadedArgIntrin(), llvm::LegalizerHelper::libcall(), llvm::LegalizerHelper::lower(), llvm::X86CallLowering::lowerFormalArguments(), llvm::ARMCallLowering::lowerFormalArguments(), llvm::AArch64CallLowering::lowerFormalArguments(), llvm::LegalizerHelper::moreElementsVector(), llvm::LegalizerHelper::narrowScalar(), llvm::LegalizationArtifactCombiner::tryCombineAnyExt(), llvm::LegalizationArtifactCombiner::tryCombineExtract(), llvm::LegalizationArtifactCombiner::tryCombineMerges(), llvm::LegalizationArtifactCombiner::tryCombineSExt(), llvm::LegalizationArtifactCombiner::tryCombineZExt(), llvm::LegalizationArtifactCombiner::tryFoldImplicitDef(), and llvm::LegalizerHelper::widenScalar().

◆ setMBB()

void MachineIRBuilder::setMBB ( MachineBasicBlock MBB)

◆ setMF()

void MachineIRBuilder::setMF ( MachineFunction MF)

◆ stopObservingChanges()

void MachineIRBuilder::stopObservingChanges ( )

Definition at line 68 of file MachineIRBuilder.cpp.

References llvm::MachineIRBuilderState::Observer.

◆ validateBinaryOp()

void MachineIRBuilder::validateBinaryOp ( const LLT Res,
const LLT Op0,
const LLT Op1 
)
protected

Definition at line 191 of file MachineIRBuilder.cpp.

References assert(), llvm::LLT::isScalar(), and llvm::LLT::isVector().

Referenced by buildInstr().

◆ validateSelectOp()

void MachineIRBuilder::validateSelectOp ( const LLT ResTy,
const LLT TstTy,
const LLT Op0Ty,
const LLT Op1Ty 
)
protected

◆ validateShiftOp()

void MachineIRBuilder::validateShiftOp ( const LLT Res,
const LLT Op0,
const LLT Op1 
)
protected

Definition at line 197 of file MachineIRBuilder.cpp.

References assert(), llvm::LLT::isScalar(), and llvm::LLT::isVector().

Referenced by buildInstr().

◆ validateTruncExt()

void MachineIRBuilder::validateTruncExt ( const LLT Dst,
const LLT Src,
bool  IsExtend 
)
protected

The documentation for this class was generated from the following files: