LLVM  15.0.0git
M68kCallLowering.cpp
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1 //===-- M68kCallLowering.cpp - Call lowering --------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "M68kCallLowering.h"
16 #include "M68kISelLowering.h"
17 #include "M68kInstrInfo.h"
18 #include "M68kSubtarget.h"
19 #include "M68kTargetMachine.h"
25 
26 using namespace llvm;
27 
29  : CallLowering(&TLI) {}
30 
34  : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB),
35  DL(MIRBuilder.getMF().getDataLayout()),
36  STI(MIRBuilder.getMF().getSubtarget<M68kSubtarget>()) {}
37 
38  void assignValueToReg(Register ValVReg, Register PhysReg,
39  CCValAssign VA) override {
40  MIB.addUse(PhysReg, RegState::Implicit);
41  Register ExtReg = extendRegister(ValVReg, VA);
42  MIRBuilder.buildCopy(PhysReg, ExtReg);
43  }
44 
46  MachinePointerInfo &MPO, CCValAssign &VA) override {
47  MachineFunction &MF = MIRBuilder.getMF();
48  Register ExtReg = extendRegister(ValVReg, VA);
49 
50  auto *MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, MemTy,
51  inferAlignFromPtrInfo(MF, MPO));
52  MIRBuilder.buildStore(ExtReg, Addr, *MMO);
53  }
54 
55  Register getStackAddress(uint64_t Size, int64_t Offset,
56  MachinePointerInfo &MPO,
57  ISD::ArgFlagsTy Flags) override {
58  LLT p0 = LLT::pointer(0, DL.getPointerSizeInBits(0));
59  LLT SType = LLT::scalar(DL.getPointerSizeInBits(0));
60  Register StackReg = STI.getRegisterInfo()->getStackRegister();
61  auto SPReg = MIRBuilder.buildCopy(p0, StackReg).getReg(0);
62  auto OffsetReg = MIRBuilder.buildConstant(SType, Offset);
63  auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
64  MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
65  return AddrReg.getReg(0);
66  }
68  const DataLayout &DL;
70 };
72  const Value *Val, ArrayRef<Register> VRegs,
74  Register SwiftErrorVReg) const {
75 
76  auto MIB = MIRBuilder.buildInstrNoInsert(M68k::RTS);
77  bool Success = true;
78  MachineFunction &MF = MIRBuilder.getMF();
79  const Function &F = MF.getFunction();
81  const M68kTargetLowering &TLI = *getTLI<M68kTargetLowering>();
82  CCAssignFn *AssignFn =
83  TLI.getCCAssignFn(F.getCallingConv(), true, F.isVarArg());
84  auto &DL = F.getParent()->getDataLayout();
85  if (!VRegs.empty()) {
86  SmallVector<ArgInfo, 8> SplitArgs;
87  ArgInfo OrigArg{VRegs, Val->getType(), 0};
89  splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
90  OutgoingValueAssigner ArgAssigner(AssignFn);
91  M68kOutgoingArgHandler ArgHandler(MIRBuilder, MRI, MIB);
92  Success = determineAndHandleAssignments(ArgHandler, ArgAssigner, SplitArgs,
93  MIRBuilder, F.getCallingConv(),
94  F.isVarArg());
95  }
96  MIRBuilder.insertInstr(MIB);
97  return Success;
98 }
99 
101  const Function &F,
103  FunctionLoweringInfo &FLI) const {
104  MachineFunction &MF = MIRBuilder.getMF();
106  const auto &DL = F.getParent()->getDataLayout();
107  auto &TLI = *getTLI<M68kTargetLowering>();
108 
109  SmallVector<ArgInfo, 8> SplitArgs;
110  unsigned I = 0;
111  for (const auto &Arg : F.args()) {
112  ArgInfo OrigArg{VRegs[I], Arg.getType(), I};
114  splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
115  ++I;
116  }
117 
118  CCAssignFn *AssignFn =
119  TLI.getCCAssignFn(F.getCallingConv(), false, F.isVarArg());
120  IncomingValueAssigner ArgAssigner(AssignFn);
121  FormalArgHandler ArgHandler(MIRBuilder, MRI);
122  return determineAndHandleAssignments(ArgHandler, ArgAssigner, SplitArgs,
123  MIRBuilder, F.getCallingConv(),
124  F.isVarArg());
125 }
126 
127 void M68kIncomingValueHandler::assignValueToReg(Register ValVReg,
128  Register PhysReg,
129  CCValAssign VA) {
130  MIRBuilder.getMRI()->addLiveIn(PhysReg);
131  MIRBuilder.getMBB().addLiveIn(PhysReg);
132  IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
133 }
134 
135 void M68kIncomingValueHandler::assignValueToAddress(Register ValVReg,
136  Register Addr,
137  LLT MemTy,
138  MachinePointerInfo &MPO,
139  CCValAssign &VA) {
141  auto *MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, MemTy,
142  inferAlignFromPtrInfo(MF, MPO));
143  MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
144 }
145 
146 Register M68kIncomingValueHandler::getStackAddress(uint64_t Size,
147  int64_t Offset,
148  MachinePointerInfo &MPO,
149  ISD::ArgFlagsTy Flags) {
150  auto &MFI = MIRBuilder.getMF().getFrameInfo();
151  const bool IsImmutable = !Flags.isByVal();
152  int FI = MFI.CreateFixedObject(Size, Offset, IsImmutable);
154 
155  // Build Frame Index
158  MachineInstrBuilder AddrReg = MIRBuilder.buildFrameIndex(FramePtr, FI);
159  StackUsed = std::max(StackUsed, Size + Offset);
160  return AddrReg.getReg(0);
161 }
162 
163 void CallReturnHandler::assignValueToReg(Register ValVReg, Register PhysReg,
164  CCValAssign VA) {
165  MIB.addDef(PhysReg, RegState::Implicit);
166  MIRBuilder.buildCopy(ValVReg, PhysReg);
167 }
168 
170  CallLoweringInfo &Info) const {
171  MachineFunction &MF = MIRBuilder.getMF();
172  Function &F = MF.getFunction();
174  auto &DL = F.getParent()->getDataLayout();
175  const M68kTargetLowering &TLI = *getTLI<M68kTargetLowering>();
176  const M68kSubtarget &STI = MF.getSubtarget<M68kSubtarget>();
177  const TargetInstrInfo &TII = *STI.getInstrInfo();
178  const M68kRegisterInfo *TRI = STI.getRegisterInfo();
179 
180  SmallVector<ArgInfo, 8> OutArgs;
181  for (auto &OrigArg : Info.OrigArgs)
182  splitToValueTypes(OrigArg, OutArgs, DL, Info.CallConv);
183 
185  if (!Info.OrigRet.Ty->isVoidTy())
186  splitToValueTypes(Info.OrigRet, InArgs, DL, Info.CallConv);
187 
188  unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
189  auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown);
190 
191  unsigned Opc = TLI.getTargetMachine().isPositionIndependent() ? M68k::CALLq
192  : Info.Callee.isReg() ? M68k::CALLj
193  : M68k::CALLb;
194 
195  auto MIB = MIRBuilder.buildInstrNoInsert(Opc)
196  .add(Info.Callee)
197  .addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv));
198 
199  CCAssignFn *AssignFn = TLI.getCCAssignFn(Info.CallConv, false, Info.IsVarArg);
200  OutgoingValueAssigner Assigner(AssignFn);
201  M68kOutgoingArgHandler Handler(MIRBuilder, MRI, MIB);
202  if (!determineAndHandleAssignments(Handler, Assigner, OutArgs, MIRBuilder,
203  Info.CallConv, Info.IsVarArg))
204  return false;
205 
206  if (Info.Callee.isReg())
208  *STI.getRegBankInfo(), *MIB, MIB->getDesc(),
209  Info.Callee, 0);
210 
211  MIRBuilder.insertInstr(MIB);
212 
213  if (!Info.OrigRet.Ty->isVoidTy()) {
214  CCAssignFn *RetAssignFn =
215  TLI.getCCAssignFn(Info.CallConv, true, Info.IsVarArg);
216 
217  OutgoingValueAssigner Assigner(RetAssignFn, RetAssignFn);
218  CallReturnHandler Handler(MIRBuilder, MRI, MIB);
219  if (!determineAndHandleAssignments(Handler, Assigner, InArgs, MIRBuilder,
220  Info.CallConv, Info.IsVarArg))
221  return false;
222  }
223 
224  CallSeqStart.addImm(Assigner.StackOffset).addImm(0);
225 
226  unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
227  MIRBuilder.buildInstr(AdjStackUp).addImm(Assigner.StackOffset).addImm(0);
228 
229  return true;
230 }
231 
232 bool M68kCallLowering::enableBigEndian() const { return true; }
llvm::MachineRegisterInfo::addLiveIn
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Definition: MachineRegisterInfo.h:954
M68kOutgoingArgHandler::M68kOutgoingArgHandler
M68kOutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, MachineInstrBuilder MIB)
Definition: M68kCallLowering.cpp:32
llvm::M68kTargetLowering::getCCAssignFn
CCAssignFn * getCCAssignFn(CallingConv::ID CC, bool Return, bool IsVarArg) const
Definition: M68kISelLowering.cpp:3524
M68kOutgoingArgHandler::MIB
MachineInstrBuilder MIB
Definition: M68kCallLowering.cpp:67
M68kOutgoingArgHandler::STI
const M68kSubtarget & STI
Definition: M68kCallLowering.cpp:69
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
M68kOutgoingArgHandler
Definition: M68kCallLowering.cpp:31
M68kTargetMachine.h
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
CallLowering.h
M68kOutgoingArgHandler::getStackAddress
Register getStackAddress(uint64_t Size, int64_t Offset, MachinePointerInfo &MPO, ISD::ArgFlagsTy Flags) override
Materialize a VReg containing the address of the specified stack-based object.
Definition: M68kCallLowering.cpp:55
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::Function
Definition: Function.h:60
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::MachineIRBuilder::getMRI
MachineRegisterInfo * getMRI()
Getter for MRI.
Definition: MachineIRBuilder.h:287
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:454
llvm::M68kRegisterInfo
Definition: M68kRegisterInfo.h:30
llvm::M68kSubtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: M68kSubtarget.cpp:78
llvm::CallLowering::OutgoingValueHandler
Base class for ValueHandlers used for arguments passed to a function call, or for return values.
Definition: CallLowering.h:330
llvm::CallLowering::splitToValueTypes
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, SmallVectorImpl< uint64_t > *Offsets=nullptr) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
Definition: CallLowering.cpp:235
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::MachineIRBuilder::buildInstrNoInsert
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.cpp:38
MachineIRBuilder.h
llvm::M68kSubtarget::getRegisterInfo
const M68kRegisterInfo * getRegisterInfo() const override
Definition: M68kSubtarget.h:155
llvm::M68kCallLowering::lowerCall
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
Definition: M68kCallLowering.cpp:169
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:159
F
#define F(x, y, z)
Definition: MD5.cpp:55
M68kInstrInfo.h
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:186
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:116
llvm::M68kCallLowering::enableBigEndian
bool enableBigEndian() const override
For targets which want to use big-endian can enable it with enableBigEndian() hook.
Definition: M68kCallLowering.cpp:232
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
llvm::codeview::EncodedFramePtrReg::FramePtr
@ FramePtr
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:31
llvm::MachineIRBuilder::buildLoad
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
Definition: MachineIRBuilder.h:888
llvm::M68kSubtarget::getInstrInfo
const M68kInstrInfo * getInstrInfo() const override
Definition: M68kSubtarget.h:149
llvm::ISD::ArgFlagsTy::isByVal
bool isByVal() const
Definition: TargetCallingConv.h:85
llvm::CallLowering::ArgInfo
Definition: CallLowering.h:62
llvm::FormalArgHandler
Definition: M68kCallLowering.h:66
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
llvm::CallLowering::OutgoingValueAssigner
Definition: CallLowering.h:220
llvm::MachineIRBuilder::getMF
MachineFunction & getMF()
Getter for the function we currently build.
Definition: MachineIRBuilder.h:269
M68kISelLowering.h
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MachineInstrBuilder::getReg
Register getReg(unsigned Idx) const
Get the register for the operand index.
Definition: MachineInstrBuilder.h:94
llvm::TargetMachine::isPositionIndependent
bool isPositionIndependent() const
Definition: TargetMachine.cpp:41
llvm::M68kSubtarget
Definition: M68kSubtarget.h:45
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:175
llvm::LLT::pointer
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelTypeImpl.h:49
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::AttributeList::ReturnIndex
@ ReturnIndex
Definition: Attributes.h:428
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:219
TargetCallingConv.h
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:78
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:39
llvm::inferAlignFromPtrInfo
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:695
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:52
llvm::MachineIRBuilder::getMBB
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
Definition: MachineIRBuilder.h:294
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:672
llvm::M68kCallLowering::lowerFormalArguments
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register >> VRegs, FunctionLoweringInfo &FLI) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...
Definition: M68kCallLowering.cpp:100
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::MachineIRBuilder::buildInstr
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.h:374
llvm::MachineInstrBuilder::addRegMask
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Definition: MachineInstrBuilder.h:197
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MachineIRBuilder::insertInstr
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Definition: MachineIRBuilder.cpp:43
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
llvm::MachineIRBuilder::buildCopy
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
Definition: MachineIRBuilder.cpp:278
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:134
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:377
llvm::MachineIRBuilder::buildFrameIndex
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
Definition: MachineIRBuilder.cpp:135
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:347
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:622
M68kOutgoingArgHandler::DL
const DataLayout & DL
Definition: M68kCallLowering.cpp:68
CallingConvLower.h
llvm::M68kTargetLowering
Definition: M68kISelLowering.h:116
MachineFrameInfo.h
Success
#define Success
Definition: AArch64Disassembler.cpp:280
llvm::M68kCallLowering::lowerReturn
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI, Register SwiftErrorVReg) const override
This hook must be implemented to lower outgoing return values, described by Val, into the specified v...
Definition: M68kCallLowering.cpp:71
llvm::CallLowering::IncomingValueAssigner
Definition: CallLowering.h:214
llvm::CallLowering::CallLoweringInfo
Definition: CallLowering.h:102
llvm::CallLowering::ValueAssigner::StackOffset
uint64_t StackOffset
Stack offset for next argument.
Definition: CallLowering.h:201
llvm::CallLowering::ValueHandler::MIRBuilder
MachineIRBuilder & MIRBuilder
Definition: CallLowering.h:227
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:136
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1006
llvm::M68kCallLowering::M68kCallLowering
M68kCallLowering(const M68kTargetLowering &TLI)
Definition: M68kCallLowering.cpp:28
M68kSubtarget.h
llvm::constrainOperandRegClass
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:51
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:285
llvm::DataLayout::getPointerSizeInBits
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:412
llvm::CallReturnHandler
Definition: M68kCallLowering.h:71
M68kCallLowering.h
llvm::M68kIncomingValueHandler::StackUsed
uint64_t StackUsed
Definition: M68kCallLowering.h:52
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:42
llvm::CallLowering
Definition: CallLowering.h:44
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1019
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::AttributeList::FirstArgIndex
@ FirstArgIndex
Definition: Attributes.h:430
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:480
llvm::CallLowering::determineAndHandleAssignments
bool determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, bool IsVarArg, ArrayRef< Register > ThisReturnRegs=None) const
Invoke ValueAssigner::assignArg on each of the given Args and then use Handler to move them to the as...
Definition: CallLowering.cpp:532
M68kOutgoingArgHandler::assignValueToReg
void assignValueToReg(Register ValVReg, Register PhysReg, CCValAssign VA) override
The specified value has been assigned to a physical register, handle the appropriate COPY (either to ...
Definition: M68kCallLowering.cpp:38
M68kOutgoingArgHandler::assignValueToAddress
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy, MachinePointerInfo &MPO, CCValAssign &VA) override
The specified value has been assigned to a stack location.
Definition: M68kCallLowering.cpp:45
llvm::LLT
Definition: LowLevelTypeImpl.h:39
llvm::CallLowering::setArgFlags
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
Definition: CallLowering.cpp:177