LLVM 19.0.0git
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1//===-- M68kCallLowering.cpp - Call lowering --------------------*- C++ -*-===//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
9/// \file
10/// This file implements the lowering of LLVM calls to machine code calls for
11/// GlobalISel.
15#include "M68kCallLowering.h"
16#include "M68kISelLowering.h"
17#include "M68kInstrInfo.h"
18#include "M68kSubtarget.h"
19#include "M68kTargetMachine.h"
26using namespace llvm;
28namespace {
30struct M68kFormalArgHandler : public M68kIncomingValueHandler {
31 M68kFormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
32 : M68kIncomingValueHandler(MIRBuilder, MRI) {}
35struct CallReturnHandler : public M68kIncomingValueHandler {
36 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
38 : M68kIncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
41 void assignValueToReg(Register ValVReg, Register PhysReg,
42 const CCValAssign &VA) override;
47} // end anonymous namespace
50 : CallLowering(&TLI) {}
55 : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB),
56 DL(MIRBuilder.getMF().getDataLayout()),
57 STI(MIRBuilder.getMF().getSubtarget<M68kSubtarget>()) {}
59 void assignValueToReg(Register ValVReg, Register PhysReg,
60 const CCValAssign &VA) override {
61 MIB.addUse(PhysReg, RegState::Implicit);
62 Register ExtReg = extendRegister(ValVReg, VA);
63 MIRBuilder.buildCopy(PhysReg, ExtReg);
64 }
67 const MachinePointerInfo &MPO,
68 const CCValAssign &VA) override {
69 MachineFunction &MF = MIRBuilder.getMF();
70 Register ExtReg = extendRegister(ValVReg, VA);
72 auto *MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, MemTy,
73 inferAlignFromPtrInfo(MF, MPO));
74 MIRBuilder.buildStore(ExtReg, Addr, *MMO);
75 }
79 ISD::ArgFlagsTy Flags) override {
80 LLT p0 = LLT::pointer(0, DL.getPointerSizeInBits(0));
81 LLT SType = LLT::scalar(DL.getPointerSizeInBits(0));
82 Register StackReg = STI.getRegisterInfo()->getStackRegister();
83 auto SPReg = MIRBuilder.buildCopy(p0, StackReg).getReg(0);
84 auto OffsetReg = MIRBuilder.buildConstant(SType, Offset);
85 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
86 MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
87 return AddrReg.getReg(0);
88 }
90 const DataLayout &DL;
94 const Value *Val, ArrayRef<Register> VRegs,
96 Register SwiftErrorVReg) const {
98 auto MIB = MIRBuilder.buildInstrNoInsert(M68k::RTS);
99 bool Success = true;
100 MachineFunction &MF = MIRBuilder.getMF();
101 const Function &F = MF.getFunction();
103 const M68kTargetLowering &TLI = *getTLI<M68kTargetLowering>();
104 CCAssignFn *AssignFn =
105 TLI.getCCAssignFn(F.getCallingConv(), true, F.isVarArg());
106 auto &DL = F.getParent()->getDataLayout();
107 if (!VRegs.empty()) {
108 SmallVector<ArgInfo, 8> SplitArgs;
109 ArgInfo OrigArg{VRegs, Val->getType(), 0};
111 splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
112 OutgoingValueAssigner ArgAssigner(AssignFn);
113 M68kOutgoingArgHandler ArgHandler(MIRBuilder, MRI, MIB);
114 Success = determineAndHandleAssignments(ArgHandler, ArgAssigner, SplitArgs,
115 MIRBuilder, F.getCallingConv(),
116 F.isVarArg());
117 }
118 MIRBuilder.insertInstr(MIB);
119 return Success;
123 const Function &F,
125 FunctionLoweringInfo &FLI) const {
126 MachineFunction &MF = MIRBuilder.getMF();
128 const auto &DL = F.getParent()->getDataLayout();
129 auto &TLI = *getTLI<M68kTargetLowering>();
131 SmallVector<ArgInfo, 8> SplitArgs;
132 unsigned I = 0;
133 for (const auto &Arg : F.args()) {
134 ArgInfo OrigArg{VRegs[I], Arg.getType(), I};
136 splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
137 ++I;
138 }
140 CCAssignFn *AssignFn =
141 TLI.getCCAssignFn(F.getCallingConv(), false, F.isVarArg());
142 IncomingValueAssigner ArgAssigner(AssignFn);
143 M68kFormalArgHandler ArgHandler(MIRBuilder, MRI);
144 return determineAndHandleAssignments(ArgHandler, ArgAssigner, SplitArgs,
145 MIRBuilder, F.getCallingConv(),
146 F.isVarArg());
149void M68kIncomingValueHandler::assignValueToReg(Register ValVReg,
150 Register PhysReg,
151 const CCValAssign &VA) {
152 MIRBuilder.getMRI()->addLiveIn(PhysReg);
153 MIRBuilder.getMBB().addLiveIn(PhysReg);
154 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
157void M68kIncomingValueHandler::assignValueToAddress(
158 Register ValVReg, Register Addr, LLT MemTy, const MachinePointerInfo &MPO,
159 const CCValAssign &VA) {
161 auto *MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, MemTy,
162 inferAlignFromPtrInfo(MF, MPO));
163 MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
166Register M68kIncomingValueHandler::getStackAddress(uint64_t Size,
167 int64_t Offset,
169 ISD::ArgFlagsTy Flags) {
170 auto &MFI = MIRBuilder.getMF().getFrameInfo();
171 const bool IsImmutable = !Flags.isByVal();
172 int FI = MFI.CreateFixedObject(Size, Offset, IsImmutable);
175 // Build Frame Index
179 StackUsed = std::max(StackUsed, Size + Offset);
180 return AddrReg.getReg(0);
183void CallReturnHandler::assignValueToReg(Register ValVReg, Register PhysReg,
184 const CCValAssign &VA) {
185 MIB.addDef(PhysReg, RegState::Implicit);
186 MIRBuilder.buildCopy(ValVReg, PhysReg);
190 CallLoweringInfo &Info) const {
191 MachineFunction &MF = MIRBuilder.getMF();
192 Function &F = MF.getFunction();
194 auto &DL = F.getParent()->getDataLayout();
195 const M68kTargetLowering &TLI = *getTLI<M68kTargetLowering>();
196 const M68kSubtarget &STI = MF.getSubtarget<M68kSubtarget>();
197 const TargetInstrInfo &TII = *STI.getInstrInfo();
198 const M68kRegisterInfo *TRI = STI.getRegisterInfo();
201 for (auto &OrigArg : Info.OrigArgs)
202 splitToValueTypes(OrigArg, OutArgs, DL, Info.CallConv);
205 if (!Info.OrigRet.Ty->isVoidTy())
206 splitToValueTypes(Info.OrigRet, InArgs, DL, Info.CallConv);
208 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
209 auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown);
211 unsigned Opc = TLI.getTargetMachine().isPositionIndependent() ? M68k::CALLq
212 : Info.Callee.isReg() ? M68k::CALLj
213 : M68k::CALLb;
215 auto MIB = MIRBuilder.buildInstrNoInsert(Opc)
216 .add(Info.Callee)
217 .addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv));
219 CCAssignFn *AssignFn = TLI.getCCAssignFn(Info.CallConv, false, Info.IsVarArg);
220 OutgoingValueAssigner Assigner(AssignFn);
221 M68kOutgoingArgHandler Handler(MIRBuilder, MRI, MIB);
222 if (!determineAndHandleAssignments(Handler, Assigner, OutArgs, MIRBuilder,
223 Info.CallConv, Info.IsVarArg))
224 return false;
226 if (Info.Callee.isReg())
228 *STI.getRegBankInfo(), *MIB, MIB->getDesc(),
229 Info.Callee, 0);
231 MIRBuilder.insertInstr(MIB);
233 if (!Info.OrigRet.Ty->isVoidTy()) {
234 CCAssignFn *RetAssignFn =
235 TLI.getCCAssignFn(Info.CallConv, true, Info.IsVarArg);
237 OutgoingValueAssigner Assigner(RetAssignFn, RetAssignFn);
238 CallReturnHandler Handler(MIRBuilder, MRI, MIB);
239 if (!determineAndHandleAssignments(Handler, Assigner, InArgs, MIRBuilder,
240 Info.CallConv, Info.IsVarArg))
241 return false;
242 }
244 CallSeqStart.addImm(Assigner.StackSize).addImm(0);
246 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
247 MIRBuilder.buildInstr(AdjStackUp).addImm(Assigner.StackSize).addImm(0);
249 return true;
252bool M68kCallLowering::enableBigEndian() const { return true; }
unsigned const MachineRegisterInfo * MRI
#define Success
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
This file describes how to lower LLVM calls to machine code calls.
uint64_t Addr
uint64_t Size
const HexagonInstrInfo * TII
This file implements the lowering of LLVM calls to machine code calls for GlobalISel.
This file defines the interfaces that M68k uses to lower LLVM code into a selection DAG.
This file contains the M68k implementation of the TargetInstrInfo class.
This file declares the M68k specific subclass of TargetSubtargetInfo.
This file declares the M68k specific subclass of TargetMachine.
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
This file declares the MachineIRBuilder class.
unsigned const TargetRegisterInfo * TRI
static const unsigned FramePtr
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
CCValAssign - Represent assignment of one arg/retval to a location.
bool determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, bool IsVarArg, ArrayRef< Register > ThisReturnRegs=std::nullopt) const
Invoke ValueAssigner::assignArg on each of the given Args and then use Handler to move them to the as...
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, SmallVectorImpl< uint64_t > *Offsets=nullptr) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:410
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelType.h:42
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelType.h:57
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register > > VRegs, FunctionLoweringInfo &FLI) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...
M68kCallLowering(const M68kTargetLowering &TLI)
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI, Register SwiftErrorVReg) const override
This hook must be implemented to lower outgoing return values, described by Val, into the specified v...
bool enableBigEndian() const override
For targets which want to use big-endian can enable it with enableBigEndian() hook.
const RegisterBankInfo * getRegBankInfo() const override
const M68kInstrInfo * getInstrInfo() const override
const M68kRegisterInfo * getRegisterInfo() const override
CCAssignFn * getCCAssignFn(CallingConv::ID CC, bool Return, bool IsVarArg) const
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
Helper class to build MachineInstr.
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
MachineFunction & getMF()
Getter for the function we currently build.
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
Register getReg(unsigned Idx) const
Get the register for the operand index.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
TargetInstrInfo - Interface to description of machine instruction set.
const TargetMachine & getTargetMachine() const
bool isPositionIndependent() const
LLVM Value Representation.
Definition: Value.h:74
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
@ Implicit
Not emitted register (e.g. carry, or temporary result).
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:54
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:865
MachineInstrBuilder MIB
Register getStackAddress(uint64_t Size, int64_t Offset, MachinePointerInfo &MPO, ISD::ArgFlagsTy Flags) override
Materialize a VReg containing the address of the specified stack-based object.
M68kOutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, MachineInstrBuilder MIB)
const DataLayout & DL
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy, const MachinePointerInfo &MPO, const CCValAssign &VA) override
The specified value has been assigned to a stack location.
const M68kSubtarget & STI
void assignValueToReg(Register ValVReg, Register PhysReg, const CCValAssign &VA) override
The specified value has been assigned to a physical register, handle the appropriate COPY (either to ...
Base class for ValueHandlers used for arguments passed to a function call, or for return values.
Definition: CallLowering.h:339
uint64_t StackSize
The size of the currently allocated portion of the stack.
Definition: CallLowering.h:209
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.