LLVM  14.0.0git
RISCVFrameLowering.cpp
Go to the documentation of this file.
1 //===-- RISCVFrameLowering.cpp - RISCV Frame Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of TargetFrameLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVFrameLowering.h"
15 #include "RISCVSubtarget.h"
21 #include "llvm/IR/DiagnosticInfo.h"
22 #include "llvm/MC/MCDwarf.h"
23 
24 using namespace llvm;
25 
26 // For now we use x18, a.k.a s2, as pointer to shadow call stack.
27 // User should explicitly set -ffixed-x18 and not use x18 in their asm.
30  const DebugLoc &DL) {
31  if (!MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack))
32  return;
33 
34  const auto &STI = MF.getSubtarget<RISCVSubtarget>();
35  Register RAReg = STI.getRegisterInfo()->getRARegister();
36 
37  // Do not save RA to the SCS if it's not saved to the regular stack,
38  // i.e. RA is not at risk of being overwritten.
39  std::vector<CalleeSavedInfo> &CSI = MF.getFrameInfo().getCalleeSavedInfo();
40  if (std::none_of(CSI.begin(), CSI.end(),
41  [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
42  return;
43 
44  Register SCSPReg = RISCVABI::getSCSPReg();
45 
46  auto &Ctx = MF.getFunction().getContext();
47  if (!STI.isRegisterReservedByUser(SCSPReg)) {
49  MF.getFunction(), "x18 not reserved by user for Shadow Call Stack."});
50  return;
51  }
52 
53  const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
54  if (RVFI->useSaveRestoreLibCalls(MF)) {
55  Ctx.diagnose(DiagnosticInfoUnsupported{
56  MF.getFunction(),
57  "Shadow Call Stack cannot be combined with Save/Restore LibCalls."});
58  return;
59  }
60 
61  const RISCVInstrInfo *TII = STI.getInstrInfo();
62  bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
63  int64_t SlotSize = STI.getXLen() / 8;
64  // Store return address to shadow call stack
65  // s[w|d] ra, 0(s2)
66  // addi s2, s2, [4|8]
67  BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW))
68  .addReg(RAReg)
69  .addReg(SCSPReg)
70  .addImm(0)
72  BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI))
73  .addReg(SCSPReg, RegState::Define)
74  .addReg(SCSPReg)
75  .addImm(SlotSize)
77 }
78 
81  const DebugLoc &DL) {
82  if (!MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack))
83  return;
84 
85  const auto &STI = MF.getSubtarget<RISCVSubtarget>();
86  Register RAReg = STI.getRegisterInfo()->getRARegister();
87 
88  // See emitSCSPrologue() above.
89  std::vector<CalleeSavedInfo> &CSI = MF.getFrameInfo().getCalleeSavedInfo();
90  if (std::none_of(CSI.begin(), CSI.end(),
91  [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
92  return;
93 
94  Register SCSPReg = RISCVABI::getSCSPReg();
95 
96  auto &Ctx = MF.getFunction().getContext();
97  if (!STI.isRegisterReservedByUser(SCSPReg)) {
99  MF.getFunction(), "x18 not reserved by user for Shadow Call Stack."});
100  return;
101  }
102 
103  const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
104  if (RVFI->useSaveRestoreLibCalls(MF)) {
105  Ctx.diagnose(DiagnosticInfoUnsupported{
106  MF.getFunction(),
107  "Shadow Call Stack cannot be combined with Save/Restore LibCalls."});
108  return;
109  }
110 
111  const RISCVInstrInfo *TII = STI.getInstrInfo();
112  bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
113  int64_t SlotSize = STI.getXLen() / 8;
114  // Load return address from shadow call stack
115  // l[w|d] ra, -[4|8](s2)
116  // addi s2, s2, -[4|8]
117  BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::LD : RISCV::LW))
118  .addReg(RAReg, RegState::Define)
119  .addReg(SCSPReg)
120  .addImm(-SlotSize)
122  BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI))
123  .addReg(SCSPReg, RegState::Define)
124  .addReg(SCSPReg)
125  .addImm(-SlotSize)
127 }
128 
129 // Get the ID of the libcall used for spilling and restoring callee saved
130 // registers. The ID is representative of the number of registers saved or
131 // restored by the libcall, except it is zero-indexed - ID 0 corresponds to a
132 // single register.
133 static int getLibCallID(const MachineFunction &MF,
134  const std::vector<CalleeSavedInfo> &CSI) {
135  const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
136 
137  if (CSI.empty() || !RVFI->useSaveRestoreLibCalls(MF))
138  return -1;
139 
140  Register MaxReg = RISCV::NoRegister;
141  for (auto &CS : CSI)
142  // RISCVRegisterInfo::hasReservedSpillSlot assigns negative frame indexes to
143  // registers which can be saved by libcall.
144  if (CS.getFrameIdx() < 0)
145  MaxReg = std::max(MaxReg.id(), CS.getReg().id());
146 
147  if (MaxReg == RISCV::NoRegister)
148  return -1;
149 
150  switch (MaxReg) {
151  default:
152  llvm_unreachable("Something has gone wrong!");
153  case /*s11*/ RISCV::X27: return 12;
154  case /*s10*/ RISCV::X26: return 11;
155  case /*s9*/ RISCV::X25: return 10;
156  case /*s8*/ RISCV::X24: return 9;
157  case /*s7*/ RISCV::X23: return 8;
158  case /*s6*/ RISCV::X22: return 7;
159  case /*s5*/ RISCV::X21: return 6;
160  case /*s4*/ RISCV::X20: return 5;
161  case /*s3*/ RISCV::X19: return 4;
162  case /*s2*/ RISCV::X18: return 3;
163  case /*s1*/ RISCV::X9: return 2;
164  case /*s0*/ RISCV::X8: return 1;
165  case /*ra*/ RISCV::X1: return 0;
166  }
167 }
168 
169 // Get the name of the libcall used for spilling callee saved registers.
170 // If this function will not use save/restore libcalls, then return a nullptr.
171 static const char *
173  const std::vector<CalleeSavedInfo> &CSI) {
174  static const char *const SpillLibCalls[] = {
175  "__riscv_save_0",
176  "__riscv_save_1",
177  "__riscv_save_2",
178  "__riscv_save_3",
179  "__riscv_save_4",
180  "__riscv_save_5",
181  "__riscv_save_6",
182  "__riscv_save_7",
183  "__riscv_save_8",
184  "__riscv_save_9",
185  "__riscv_save_10",
186  "__riscv_save_11",
187  "__riscv_save_12"
188  };
189 
190  int LibCallID = getLibCallID(MF, CSI);
191  if (LibCallID == -1)
192  return nullptr;
193  return SpillLibCalls[LibCallID];
194 }
195 
196 // Get the name of the libcall used for restoring callee saved registers.
197 // If this function will not use save/restore libcalls, then return a nullptr.
198 static const char *
200  const std::vector<CalleeSavedInfo> &CSI) {
201  static const char *const RestoreLibCalls[] = {
202  "__riscv_restore_0",
203  "__riscv_restore_1",
204  "__riscv_restore_2",
205  "__riscv_restore_3",
206  "__riscv_restore_4",
207  "__riscv_restore_5",
208  "__riscv_restore_6",
209  "__riscv_restore_7",
210  "__riscv_restore_8",
211  "__riscv_restore_9",
212  "__riscv_restore_10",
213  "__riscv_restore_11",
214  "__riscv_restore_12"
215  };
216 
217  int LibCallID = getLibCallID(MF, CSI);
218  if (LibCallID == -1)
219  return nullptr;
220  return RestoreLibCalls[LibCallID];
221 }
222 
224  const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
225 
226  const MachineFrameInfo &MFI = MF.getFrameInfo();
227  return MF.getTarget().Options.DisableFramePointerElim(MF) ||
228  RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() ||
229  MFI.isFrameAddressTaken();
230 }
231 
233  const MachineFrameInfo &MFI = MF.getFrameInfo();
235 
236  return MFI.hasVarSizedObjects() && TRI->hasStackRealignment(MF);
237 }
238 
239 // Determines the size of the frame and maximum call frame size.
240 void RISCVFrameLowering::determineFrameLayout(MachineFunction &MF) const {
241  MachineFrameInfo &MFI = MF.getFrameInfo();
242 
243  // Get the number of bytes to allocate from the FrameInfo.
244  uint64_t FrameSize = MFI.getStackSize();
245 
246  // Get the alignment.
248 
249  // Make sure the frame is aligned.
250  FrameSize = alignTo(FrameSize, StackAlign);
251 
252  // Update frame info.
253  MFI.setStackSize(FrameSize);
254 }
255 
256 void RISCVFrameLowering::adjustReg(MachineBasicBlock &MBB,
258  const DebugLoc &DL, Register DestReg,
259  Register SrcReg, int64_t Val,
260  MachineInstr::MIFlag Flag) const {
262  const RISCVInstrInfo *TII = STI.getInstrInfo();
263 
264  if (DestReg == SrcReg && Val == 0)
265  return;
266 
267  if (isInt<12>(Val)) {
268  BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg)
269  .addReg(SrcReg)
270  .addImm(Val)
271  .setMIFlag(Flag);
272  } else {
273  unsigned Opc = RISCV::ADD;
274  bool isSub = Val < 0;
275  if (isSub) {
276  Val = -Val;
277  Opc = RISCV::SUB;
278  }
279 
280  Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
281  TII->movImm(MBB, MBBI, DL, ScratchReg, Val, Flag);
282  BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
283  .addReg(SrcReg)
284  .addReg(ScratchReg, RegState::Kill)
285  .setMIFlag(Flag);
286  }
287 }
288 
289 // Returns the register used to hold the frame pointer.
290 static Register getFPReg(const RISCVSubtarget &STI) { return RISCV::X8; }
291 
292 // Returns the register used to hold the stack pointer.
293 static Register getSPReg(const RISCVSubtarget &STI) { return RISCV::X2; }
294 
297  const std::vector<CalleeSavedInfo> &CSI) {
298  const MachineFrameInfo &MFI = MF.getFrameInfo();
299  SmallVector<CalleeSavedInfo, 8> NonLibcallCSI;
300 
301  for (auto &CS : CSI) {
302  int FI = CS.getFrameIdx();
303  if (FI >= 0 && MFI.getStackID(FI) == TargetStackID::Default)
304  NonLibcallCSI.push_back(CS);
305  }
306 
307  return NonLibcallCSI;
308 }
309 
310 void RISCVFrameLowering::adjustStackForRVV(MachineFunction &MF,
313  const DebugLoc &DL, int64_t Amount,
314  MachineInstr::MIFlag Flag) const {
315  assert(Amount != 0 && "Did not need to adjust stack pointer for RVV.");
316 
317  const RISCVInstrInfo *TII = STI.getInstrInfo();
318  Register SPReg = getSPReg(STI);
319  unsigned Opc = RISCV::ADD;
320  if (Amount < 0) {
321  Amount = -Amount;
322  Opc = RISCV::SUB;
323  }
324  // 1. Multiply the number of v-slots to the length of registers
325  Register FactorRegister =
326  TII->getVLENFactoredAmount(MF, MBB, MBBI, DL, Amount, Flag);
327  // 2. SP = SP - RVV stack size
328  BuildMI(MBB, MBBI, DL, TII->get(Opc), SPReg)
329  .addReg(SPReg)
330  .addReg(FactorRegister, RegState::Kill)
331  .setMIFlag(Flag);
332 }
333 
335  MachineBasicBlock &MBB) const {
336  MachineFrameInfo &MFI = MF.getFrameInfo();
337  auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
338  const RISCVRegisterInfo *RI = STI.getRegisterInfo();
339  const RISCVInstrInfo *TII = STI.getInstrInfo();
341 
342  Register FPReg = getFPReg(STI);
343  Register SPReg = getSPReg(STI);
344  Register BPReg = RISCVABI::getBPReg();
345 
346  // Debug location must be unknown since the first debug location is used
347  // to determine the end of the prologue.
348  DebugLoc DL;
349 
350  // All calls are tail calls in GHC calling conv, and functions have no
351  // prologue/epilogue.
353  return;
354 
355  // Emit prologue for shadow call stack.
356  emitSCSPrologue(MF, MBB, MBBI, DL);
357 
358  // Since spillCalleeSavedRegisters may have inserted a libcall, skip past
359  // any instructions marked as FrameSetup
360  while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup))
361  ++MBBI;
362 
363  // Determine the correct frame layout
364  determineFrameLayout(MF);
365 
366  // If libcalls are used to spill and restore callee-saved registers, the frame
367  // has two sections; the opaque section managed by the libcalls, and the
368  // section managed by MachineFrameInfo which can also hold callee saved
369  // registers in fixed stack slots, both of which have negative frame indices.
370  // This gets even more complicated when incoming arguments are passed via the
371  // stack, as these too have negative frame indices. An example is detailed
372  // below:
373  //
374  // | incoming arg | <- FI[-3]
375  // | libcallspill |
376  // | calleespill | <- FI[-2]
377  // | calleespill | <- FI[-1]
378  // | this_frame | <- FI[0]
379  //
380  // For negative frame indices, the offset from the frame pointer will differ
381  // depending on which of these groups the frame index applies to.
382  // The following calculates the correct offset knowing the number of callee
383  // saved registers spilt by the two methods.
384  if (int LibCallRegs = getLibCallID(MF, MFI.getCalleeSavedInfo()) + 1) {
385  // Calculate the size of the frame managed by the libcall. The libcalls are
386  // implemented such that the stack will always be 16 byte aligned.
387  unsigned LibCallFrameSize = alignTo((STI.getXLen() / 8) * LibCallRegs, 16);
388  RVFI->setLibCallStackSize(LibCallFrameSize);
389  }
390 
391  // FIXME (note copied from Lanai): This appears to be overallocating. Needs
392  // investigation. Get the number of bytes to allocate from the FrameInfo.
393  uint64_t StackSize = MFI.getStackSize() + RVFI->getRVVPadding();
394  uint64_t RealStackSize = StackSize + RVFI->getLibCallStackSize();
395  uint64_t RVVStackSize = RVFI->getRVVStackSize();
396 
397  // Early exit if there is no need to allocate on the stack
398  if (RealStackSize == 0 && !MFI.adjustsStack() && RVVStackSize == 0)
399  return;
400 
401  // If the stack pointer has been marked as reserved, then produce an error if
402  // the frame requires stack allocation
403  if (STI.isRegisterReservedByUser(SPReg))
405  MF.getFunction(), "Stack pointer required, but has been reserved."});
406 
407  uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
408  // Split the SP adjustment to reduce the offsets of callee saved spill.
409  if (FirstSPAdjustAmount) {
410  StackSize = FirstSPAdjustAmount;
411  RealStackSize = FirstSPAdjustAmount;
412  }
413 
414  // Allocate space on the stack if necessary.
415  adjustReg(MBB, MBBI, DL, SPReg, SPReg, -StackSize, MachineInstr::FrameSetup);
416 
417  // Emit ".cfi_def_cfa_offset RealStackSize"
418  unsigned CFIIndex = MF.addFrameInst(
419  MCCFIInstruction::cfiDefCfaOffset(nullptr, RealStackSize));
420  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
421  .addCFIIndex(CFIIndex)
423 
424  const auto &CSI = MFI.getCalleeSavedInfo();
425 
426  // The frame pointer is callee-saved, and code has been generated for us to
427  // save it to the stack. We need to skip over the storing of callee-saved
428  // registers as the frame pointer must be modified after it has been saved
429  // to the stack, not before.
430  // FIXME: assumes exactly one instruction is used to save each callee-saved
431  // register.
432  std::advance(MBBI, getNonLibcallCSI(MF, CSI).size());
433 
434  // Iterate over list of callee-saved registers and emit .cfi_offset
435  // directives.
436  for (const auto &Entry : CSI) {
437  int FrameIdx = Entry.getFrameIdx();
438  int64_t Offset;
439  // Offsets for objects with fixed locations (IE: those saved by libcall) are
440  // simply calculated from the frame index.
441  if (FrameIdx < 0)
442  Offset = FrameIdx * (int64_t) STI.getXLen() / 8;
443  else
444  Offset = MFI.getObjectOffset(Entry.getFrameIdx()) -
445  RVFI->getLibCallStackSize();
446  Register Reg = Entry.getReg();
447  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
448  nullptr, RI->getDwarfRegNum(Reg, true), Offset));
449  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
450  .addCFIIndex(CFIIndex)
452  }
453 
454  // Generate new FP.
455  if (hasFP(MF)) {
456  if (STI.isRegisterReservedByUser(FPReg))
458  MF.getFunction(), "Frame pointer required, but has been reserved."});
459 
460  adjustReg(MBB, MBBI, DL, FPReg, SPReg,
461  RealStackSize - RVFI->getVarArgsSaveSize(),
463 
464  // Emit ".cfi_def_cfa $fp, RVFI->getVarArgsSaveSize()"
465  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
466  nullptr, RI->getDwarfRegNum(FPReg, true), RVFI->getVarArgsSaveSize()));
467  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
468  .addCFIIndex(CFIIndex)
470  }
471 
472  // Emit the second SP adjustment after saving callee saved registers.
473  if (FirstSPAdjustAmount) {
474  uint64_t SecondSPAdjustAmount = MFI.getStackSize() - FirstSPAdjustAmount;
475  assert(SecondSPAdjustAmount > 0 &&
476  "SecondSPAdjustAmount should be greater than zero");
477  adjustReg(MBB, MBBI, DL, SPReg, SPReg, -SecondSPAdjustAmount,
479 
480  // If we are using a frame-pointer, and thus emitted ".cfi_def_cfa fp, 0",
481  // don't emit an sp-based .cfi_def_cfa_offset
482  if (!hasFP(MF)) {
483  // Emit ".cfi_def_cfa_offset StackSize"
484  unsigned CFIIndex = MF.addFrameInst(
486  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
487  .addCFIIndex(CFIIndex)
489  }
490  }
491 
492  if (RVVStackSize)
493  adjustStackForRVV(MF, MBB, MBBI, DL, -RVVStackSize,
495 
496  if (hasFP(MF)) {
497  // Realign Stack
498  const RISCVRegisterInfo *RI = STI.getRegisterInfo();
499  if (RI->hasStackRealignment(MF)) {
500  Align MaxAlignment = MFI.getMaxAlign();
501 
502  const RISCVInstrInfo *TII = STI.getInstrInfo();
503  if (isInt<12>(-(int)MaxAlignment.value())) {
504  BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg)
505  .addReg(SPReg)
506  .addImm(-(int)MaxAlignment.value())
508  } else {
509  unsigned ShiftAmount = Log2(MaxAlignment);
510  Register VR =
511  MF.getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
512  BuildMI(MBB, MBBI, DL, TII->get(RISCV::SRLI), VR)
513  .addReg(SPReg)
514  .addImm(ShiftAmount)
516  BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), SPReg)
517  .addReg(VR)
518  .addImm(ShiftAmount)
520  }
521  // FP will be used to restore the frame in the epilogue, so we need
522  // another base register BP to record SP after re-alignment. SP will
523  // track the current stack after allocating variable sized objects.
524  if (hasBP(MF)) {
525  // move BP, SP
526  BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), BPReg)
527  .addReg(SPReg)
528  .addImm(0)
530  }
531  }
532  }
533 }
534 
536  MachineBasicBlock &MBB) const {
537  const RISCVRegisterInfo *RI = STI.getRegisterInfo();
538  MachineFrameInfo &MFI = MF.getFrameInfo();
539  auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
540  Register FPReg = getFPReg(STI);
541  Register SPReg = getSPReg(STI);
542 
543  // All calls are tail calls in GHC calling conv, and functions have no
544  // prologue/epilogue.
546  return;
547 
548  // Get the insert location for the epilogue. If there were no terminators in
549  // the block, get the last instruction.
551  DebugLoc DL;
552  if (!MBB.empty()) {
554  if (MBBI == MBB.end())
556  DL = MBBI->getDebugLoc();
557 
558  // If this is not a terminator, the actual insert location should be after the
559  // last instruction.
560  if (!MBBI->isTerminator())
561  MBBI = std::next(MBBI);
562 
563  // If callee-saved registers are saved via libcall, place stack adjustment
564  // before this call.
565  while (MBBI != MBB.begin() &&
566  std::prev(MBBI)->getFlag(MachineInstr::FrameDestroy))
567  --MBBI;
568  }
569 
570  const auto &CSI = getNonLibcallCSI(MF, MFI.getCalleeSavedInfo());
571 
572  // Skip to before the restores of callee-saved registers
573  // FIXME: assumes exactly one instruction is used to restore each
574  // callee-saved register.
575  auto LastFrameDestroy = MBBI;
576  if (!CSI.empty())
577  LastFrameDestroy = std::prev(MBBI, CSI.size());
578 
579  uint64_t StackSize = MFI.getStackSize() + RVFI->getRVVPadding();
580  uint64_t RealStackSize = StackSize + RVFI->getLibCallStackSize();
581  uint64_t FPOffset = RealStackSize - RVFI->getVarArgsSaveSize();
582  uint64_t RVVStackSize = RVFI->getRVVStackSize();
583 
584  // Restore the stack pointer using the value of the frame pointer. Only
585  // necessary if the stack pointer was modified, meaning the stack size is
586  // unknown.
587  if (RI->hasStackRealignment(MF) || MFI.hasVarSizedObjects()) {
588  assert(hasFP(MF) && "frame pointer should not have been eliminated");
589  adjustReg(MBB, LastFrameDestroy, DL, SPReg, FPReg, -FPOffset,
591  } else {
592  if (RVVStackSize)
593  adjustStackForRVV(MF, MBB, LastFrameDestroy, DL, RVVStackSize,
595  }
596 
597  uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
598  if (FirstSPAdjustAmount) {
599  uint64_t SecondSPAdjustAmount = MFI.getStackSize() - FirstSPAdjustAmount;
600  assert(SecondSPAdjustAmount > 0 &&
601  "SecondSPAdjustAmount should be greater than zero");
602 
603  adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg, SecondSPAdjustAmount,
605  }
606 
607  if (FirstSPAdjustAmount)
608  StackSize = FirstSPAdjustAmount;
609 
610  // Deallocate stack
611  adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy);
612 
613  // Emit epilogue for shadow call stack.
614  emitSCSEpilogue(MF, MBB, MBBI, DL);
615 }
616 
619  Register &FrameReg) const {
620  const MachineFrameInfo &MFI = MF.getFrameInfo();
622  const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
623 
624  // Callee-saved registers should be referenced relative to the stack
625  // pointer (positive offset), otherwise use the frame pointer (negative
626  // offset).
627  const auto &CSI = getNonLibcallCSI(MF, MFI.getCalleeSavedInfo());
628  int MinCSFI = 0;
629  int MaxCSFI = -1;
631  auto StackID = MFI.getStackID(FI);
632 
633  assert((StackID == TargetStackID::Default ||
634  StackID == TargetStackID::ScalableVector) &&
635  "Unexpected stack ID for the frame object.");
636  if (StackID == TargetStackID::Default) {
637  Offset =
639  MFI.getOffsetAdjustment());
640  } else if (StackID == TargetStackID::ScalableVector) {
642  }
643 
644  uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
645 
646  if (CSI.size()) {
647  MinCSFI = CSI[0].getFrameIdx();
648  MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
649  }
650 
651  if (FI >= MinCSFI && FI <= MaxCSFI) {
652  FrameReg = RISCV::X2;
653 
654  if (FirstSPAdjustAmount)
655  Offset += StackOffset::getFixed(FirstSPAdjustAmount);
656  else
657  Offset +=
658  StackOffset::getFixed(MFI.getStackSize() + RVFI->getRVVPadding());
659  } else if (RI->hasStackRealignment(MF) && !MFI.isFixedObjectIndex(FI)) {
660  // If the stack was realigned, the frame pointer is set in order to allow
661  // SP to be restored, so we need another base register to record the stack
662  // after realignment.
663  if (hasBP(MF)) {
664  FrameReg = RISCVABI::getBPReg();
665  // |--------------------------| -- <-- FP
666  // | callee-saved registers | | <----.
667  // |--------------------------| -- |
668  // | realignment (the size of | | |
669  // | this area is not counted | | |
670  // | in MFI.getStackSize()) | | |
671  // |--------------------------| -- |
672  // | Padding after RVV | | |
673  // | (not counted in | | |
674  // | MFI.getStackSize() | | |
675  // |--------------------------| -- |-- MFI.getStackSize()
676  // | RVV objects | | |
677  // | (not counted in | | |
678  // | MFI.getStackSize() | | |
679  // |--------------------------| -- |
680  // | Padding before RVV | | |
681  // | (not counted in | | |
682  // | MFI.getStackSize() | | |
683  // |--------------------------| -- |
684  // | scalar local variables | | <----'
685  // |--------------------------| -- <-- BP
686  // | VarSize objects | |
687  // |--------------------------| -- <-- SP
688  } else {
689  FrameReg = RISCV::X2;
690  // |--------------------------| -- <-- FP
691  // | callee-saved registers | | <----.
692  // |--------------------------| -- |
693  // | realignment (the size of | | |
694  // | this area is not counted | | |
695  // | in MFI.getStackSize()) | | |
696  // |--------------------------| -- |
697  // | Padding after RVV | | |
698  // | (not counted in | | |
699  // | MFI.getStackSize() | | |
700  // |--------------------------| -- |-- MFI.getStackSize()
701  // | RVV objects | | |
702  // | (not counted in | | |
703  // | MFI.getStackSize() | | |
704  // |--------------------------| -- |
705  // | Padding before RVV | | |
706  // | (not counted in | | |
707  // | MFI.getStackSize() | | |
708  // |--------------------------| -- |
709  // | scalar local variables | | <----'
710  // |--------------------------| -- <-- SP
711  }
712  // The total amount of padding surrounding RVV objects is described by
713  // RVV->getRVVPadding() and it can be zero. It allows us to align the RVV
714  // objects to 8 bytes.
715  if (MFI.getStackID(FI) == TargetStackID::Default) {
717  if (FI < 0)
718  Offset += StackOffset::getFixed(RVFI->getLibCallStackSize());
719  } else if (MFI.getStackID(FI) == TargetStackID::ScalableVector) {
721  alignTo(MFI.getStackSize() - RVFI->getCalleeSavedStackSize(), 8),
722  RVFI->getRVVStackSize());
723  }
724  } else {
725  FrameReg = RI->getFrameRegister(MF);
726  if (hasFP(MF)) {
727  Offset += StackOffset::getFixed(RVFI->getVarArgsSaveSize());
728  if (FI >= 0)
729  Offset -= StackOffset::getFixed(RVFI->getLibCallStackSize());
730  // When using FP to access scalable vector objects, we need to minus
731  // the frame size.
732  //
733  // |--------------------------| -- <-- FP
734  // | callee-saved registers | |
735  // |--------------------------| | MFI.getStackSize()
736  // | scalar local variables | |
737  // |--------------------------| -- (Offset of RVV objects is from here.)
738  // | RVV objects |
739  // |--------------------------|
740  // | VarSize objects |
741  // |--------------------------| <-- SP
744  } else {
745  // When using SP to access frame objects, we need to add RVV stack size.
746  //
747  // |--------------------------| -- <-- FP
748  // | callee-saved registers | | <----.
749  // |--------------------------| -- |
750  // | Padding after RVV | | |
751  // | (not counted in | | |
752  // | MFI.getStackSize() | | |
753  // |--------------------------| -- |
754  // | RVV objects | | |-- MFI.getStackSize()
755  // | (not counted in | | |
756  // | MFI.getStackSize() | | |
757  // |--------------------------| -- |
758  // | Padding before RVV | | |
759  // | (not counted in | | |
760  // | MFI.getStackSize() | | |
761  // |--------------------------| -- |
762  // | scalar local variables | | <----'
763  // |--------------------------| -- <-- SP
764  //
765  // The total amount of padding surrounding RVV objects is described by
766  // RVV->getRVVPadding() and it can be zero. It allows us to align the RVV
767  // objects to 8 bytes.
768  if (MFI.getStackID(FI) == TargetStackID::Default) {
769  if (MFI.isFixedObjectIndex(FI)) {
770  Offset += StackOffset::get(MFI.getStackSize() + RVFI->getRVVPadding()
771  + RVFI->getLibCallStackSize(), RVFI->getRVVStackSize());
772  } else {
774  }
775  } else if (MFI.getStackID(FI) == TargetStackID::ScalableVector) {
777  alignTo(MFI.getStackSize() - RVFI->getCalleeSavedStackSize(), 8),
778  RVFI->getRVVStackSize());
779  }
780  }
781  }
782 
783  return Offset;
784 }
785 
787  BitVector &SavedRegs,
788  RegScavenger *RS) const {
790  // Unconditionally spill RA and FP only if the function uses a frame
791  // pointer.
792  if (hasFP(MF)) {
793  SavedRegs.set(RISCV::X1);
794  SavedRegs.set(RISCV::X8);
795  }
796  // Mark BP as used if function has dedicated base pointer.
797  if (hasBP(MF))
798  SavedRegs.set(RISCVABI::getBPReg());
799 
800  // If interrupt is enabled and there are calls in the handler,
801  // unconditionally save all Caller-saved registers and
802  // all FP registers, regardless whether they are used.
803  MachineFrameInfo &MFI = MF.getFrameInfo();
804 
805  if (MF.getFunction().hasFnAttribute("interrupt") && MFI.hasCalls()) {
806 
807  static const MCPhysReg CSRegs[] = { RISCV::X1, /* ra */
808  RISCV::X5, RISCV::X6, RISCV::X7, /* t0-t2 */
809  RISCV::X10, RISCV::X11, /* a0-a1, a2-a7 */
810  RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17,
811  RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, 0 /* t3-t6 */
812  };
813 
814  for (unsigned i = 0; CSRegs[i]; ++i)
815  SavedRegs.set(CSRegs[i]);
816 
817  if (MF.getSubtarget<RISCVSubtarget>().hasStdExtF()) {
818 
819  // If interrupt is enabled, this list contains all FP registers.
820  const MCPhysReg * Regs = MF.getRegInfo().getCalleeSavedRegs();
821 
822  for (unsigned i = 0; Regs[i]; ++i)
823  if (RISCV::FPR16RegClass.contains(Regs[i]) ||
824  RISCV::FPR32RegClass.contains(Regs[i]) ||
825  RISCV::FPR64RegClass.contains(Regs[i]))
826  SavedRegs.set(Regs[i]);
827  }
828  }
829 }
830 
831 int64_t
832 RISCVFrameLowering::assignRVVStackObjectOffsets(MachineFrameInfo &MFI) const {
833  int64_t Offset = 0;
834  // Create a buffer of RVV objects to allocate.
835  SmallVector<int, 8> ObjectsToAllocate;
836  for (int I = 0, E = MFI.getObjectIndexEnd(); I != E; ++I) {
837  unsigned StackID = MFI.getStackID(I);
838  if (StackID != TargetStackID::ScalableVector)
839  continue;
840  if (MFI.isDeadObjectIndex(I))
841  continue;
842 
843  ObjectsToAllocate.push_back(I);
844  }
845 
846  // Allocate all RVV locals and spills
847  for (int FI : ObjectsToAllocate) {
848  // ObjectSize in bytes.
849  int64_t ObjectSize = MFI.getObjectSize(FI);
850  // If the data type is the fractional vector type, reserve one vector
851  // register for it.
852  if (ObjectSize < 8)
853  ObjectSize = 8;
854  // Currently, all scalable vector types are aligned to 8 bytes.
855  Offset = alignTo(Offset + ObjectSize, 8);
856  MFI.setObjectOffset(FI, -Offset);
857  }
858 
859  return Offset;
860 }
861 
864  return false;
865  return any_of(MF, [&TII](const MachineBasicBlock &MBB) {
866  return any_of(MBB, [&TII](const MachineInstr &MI) {
867  return TII.isRVVSpill(MI, /*CheckFIs*/ true);
868  });
869  });
870 }
871 
873  MachineFunction &MF, RegScavenger *RS) const {
874  const RISCVRegisterInfo *RegInfo =
875  MF.getSubtarget<RISCVSubtarget>().getRegisterInfo();
876  MachineFrameInfo &MFI = MF.getFrameInfo();
877  const TargetRegisterClass *RC = &RISCV::GPRRegClass;
878  auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
879 
880  int64_t RVVStackSize = assignRVVStackObjectOffsets(MFI);
881  RVFI->setRVVStackSize(RVVStackSize);
882  const RISCVInstrInfo &TII = *MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
883 
884  // estimateStackSize has been observed to under-estimate the final stack
885  // size, so give ourselves wiggle-room by checking for stack size
886  // representable an 11-bit signed field rather than 12-bits.
887  // FIXME: It may be possible to craft a function with a small stack that
888  // still needs an emergency spill slot for branch relaxation. This case
889  // would currently be missed.
890  // RVV loads & stores have no capacity to hold the immediate address offsets
891  // so we must always reserve an emergency spill slot if the MachineFunction
892  // contains any RVV spills.
893  if (!isInt<11>(MFI.estimateStackSize(MF)) || hasRVVSpillWithFIs(MF, TII)) {
894  int RegScavFI = MFI.CreateStackObject(RegInfo->getSpillSize(*RC),
895  RegInfo->getSpillAlign(*RC), false);
896  RS->addScavengingFrameIndex(RegScavFI);
897  // For RVV, scalable stack offsets require up to two scratch registers to
898  // compute the final offset. Reserve an additional emergency spill slot.
899  if (RVVStackSize != 0) {
900  int RVVRegScavFI = MFI.CreateStackObject(
901  RegInfo->getSpillSize(*RC), RegInfo->getSpillAlign(*RC), false);
902  RS->addScavengingFrameIndex(RVVRegScavFI);
903  }
904  }
905 
906  if (MFI.getCalleeSavedInfo().empty() || RVFI->useSaveRestoreLibCalls(MF)) {
907  RVFI->setCalleeSavedStackSize(0);
908  return;
909  }
910 
911  unsigned Size = 0;
912  for (const auto &Info : MFI.getCalleeSavedInfo()) {
913  int FrameIdx = Info.getFrameIdx();
914  if (MFI.getStackID(FrameIdx) != TargetStackID::Default)
915  continue;
916 
917  Size += MFI.getObjectSize(FrameIdx);
918  }
919  RVFI->setCalleeSavedStackSize(Size);
920 
921  // Padding required to keep the RVV stack aligned to 8 bytes
922  // within the main stack. We only need this when not using FP.
923  if (RVVStackSize && !hasFP(MF) && Size % 8 != 0) {
924  // Because we add the padding to the size of the stack, adding
925  // getStackAlign() will keep it aligned.
926  RVFI->setRVVPadding(getStackAlign().value());
927  }
928 }
929 
930 static bool hasRVVFrameObject(const MachineFunction &MF) {
931  const MachineFrameInfo &MFI = MF.getFrameInfo();
932  for (int I = 0, E = MFI.getObjectIndexEnd(); I != E; ++I)
934  return true;
935  return false;
936 }
937 
938 // Not preserve stack space within prologue for outgoing variables when the
939 // function contains variable size objects or there are vector objects accessed
940 // by the frame pointer.
941 // Let eliminateCallFramePseudoInstr preserve stack space for it.
943  return !MF.getFrameInfo().hasVarSizedObjects() &&
944  !(hasFP(MF) && hasRVVFrameObject(MF));
945 }
946 
947 // Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions.
951  Register SPReg = RISCV::X2;
952  DebugLoc DL = MI->getDebugLoc();
953 
954  if (!hasReservedCallFrame(MF)) {
955  // If space has not been reserved for a call frame, ADJCALLSTACKDOWN and
956  // ADJCALLSTACKUP must be converted to instructions manipulating the stack
957  // pointer. This is necessary when there is a variable length stack
958  // allocation (e.g. alloca), which means it's not possible to allocate
959  // space for outgoing arguments from within the function prologue.
960  int64_t Amount = MI->getOperand(0).getImm();
961 
962  if (Amount != 0) {
963  // Ensure the stack remains aligned after adjustment.
964  Amount = alignSPAdjust(Amount);
965 
966  if (MI->getOpcode() == RISCV::ADJCALLSTACKDOWN)
967  Amount = -Amount;
968 
969  adjustReg(MBB, MI, DL, SPReg, SPReg, Amount, MachineInstr::NoFlags);
970  }
971  }
972 
973  return MBB.erase(MI);
974 }
975 
976 // We would like to split the SP adjustment to reduce prologue/epilogue
977 // as following instructions. In this way, the offset of the callee saved
978 // register could fit in a single store.
979 // add sp,sp,-2032
980 // sw ra,2028(sp)
981 // sw s0,2024(sp)
982 // sw s1,2020(sp)
983 // sw s3,2012(sp)
984 // sw s4,2008(sp)
985 // add sp,sp,-64
986 uint64_t
988  const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
989  const MachineFrameInfo &MFI = MF.getFrameInfo();
990  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
991  uint64_t StackSize = MFI.getStackSize();
992 
993  // Disable SplitSPAdjust if save-restore libcall used. The callee saved
994  // registers will be pushed by the save-restore libcalls, so we don't have to
995  // split the SP adjustment in this case.
996  if (RVFI->getLibCallStackSize())
997  return 0;
998 
999  // Return the FirstSPAdjustAmount if the StackSize can not fit in signed
1000  // 12-bit and there exists a callee saved register need to be pushed.
1001  if (!isInt<12>(StackSize) && (CSI.size() > 0)) {
1002  // FirstSPAdjustAmount is choosed as (2048 - StackAlign)
1003  // because 2048 will cause sp = sp + 2048 in epilogue split into
1004  // multi-instructions. The offset smaller than 2048 can fit in signle
1005  // load/store instruction and we have to stick with the stack alignment.
1006  // 2048 is 16-byte alignment. The stack alignment for RV32 and RV64 is 16,
1007  // for RV32E is 4. So (2048 - StackAlign) will satisfy the stack alignment.
1008  return 2048 - getStackAlign().value();
1009  }
1010  return 0;
1011 }
1012 
1015  ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
1016  if (CSI.empty())
1017  return true;
1018 
1019  MachineFunction *MF = MBB.getParent();
1020  const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
1021  DebugLoc DL;
1022  if (MI != MBB.end() && !MI->isDebugInstr())
1023  DL = MI->getDebugLoc();
1024 
1025  const char *SpillLibCall = getSpillLibCallName(*MF, CSI);
1026  if (SpillLibCall) {
1027  // Add spill libcall via non-callee-saved register t0.
1028  BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoCALLReg), RISCV::X5)
1029  .addExternalSymbol(SpillLibCall, RISCVII::MO_CALL)
1031 
1032  // Add registers spilled in libcall as liveins.
1033  for (auto &CS : CSI)
1034  MBB.addLiveIn(CS.getReg());
1035  }
1036 
1037  // Manually spill values not spilled by libcall.
1038  const auto &NonLibcallCSI = getNonLibcallCSI(*MF, CSI);
1039  for (auto &CS : NonLibcallCSI) {
1040  // Insert the spill to the stack frame.
1041  Register Reg = CS.getReg();
1043  TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI);
1044  }
1045 
1046  return true;
1047 }
1048 
1052  if (CSI.empty())
1053  return true;
1054 
1055  MachineFunction *MF = MBB.getParent();
1056  const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
1057  DebugLoc DL;
1058  if (MI != MBB.end() && !MI->isDebugInstr())
1059  DL = MI->getDebugLoc();
1060 
1061  // Manually restore values not restored by libcall. Insert in reverse order.
1062  // loadRegFromStackSlot can insert multiple instructions.
1063  const auto &NonLibcallCSI = getNonLibcallCSI(*MF, CSI);
1064  for (auto &CS : reverse(NonLibcallCSI)) {
1065  Register Reg = CS.getReg();
1067  TII.loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI);
1068  assert(MI != MBB.begin() && "loadRegFromStackSlot didn't insert any code!");
1069  }
1070 
1071  const char *RestoreLibCall = getRestoreLibCallName(*MF, CSI);
1072  if (RestoreLibCall) {
1073  // Add restore libcall via tail call.
1075  BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoTAIL))
1076  .addExternalSymbol(RestoreLibCall, RISCVII::MO_CALL)
1078 
1079  // Remove trailing returns, since the terminator is now a tail call to the
1080  // restore function.
1081  if (MI != MBB.end() && MI->getOpcode() == RISCV::PseudoRET) {
1082  NewMI->copyImplicitOps(*MF, *MI);
1083  MI->eraseFromParent();
1084  }
1085  }
1086 
1087  return true;
1088 }
1089 
1091  // Keep the conventional code flow when not optimizing.
1092  if (MF.getFunction().hasOptNone())
1093  return false;
1094 
1095  return true;
1096 }
1097 
1099  MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
1100  const MachineFunction *MF = MBB.getParent();
1101  const auto *RVFI = MF->getInfo<RISCVMachineFunctionInfo>();
1102 
1103  if (!RVFI->useSaveRestoreLibCalls(*MF))
1104  return true;
1105 
1106  // Inserting a call to a __riscv_save libcall requires the use of the register
1107  // t0 (X5) to hold the return address. Therefore if this register is already
1108  // used we can't insert the call.
1109 
1110  RegScavenger RS;
1111  RS.enterBasicBlock(*TmpMBB);
1112  return !RS.isRegUsed(RISCV::X5);
1113 }
1114 
1116  const MachineFunction *MF = MBB.getParent();
1117  MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
1118  const auto *RVFI = MF->getInfo<RISCVMachineFunctionInfo>();
1119 
1120  if (!RVFI->useSaveRestoreLibCalls(*MF))
1121  return true;
1122 
1123  // Using the __riscv_restore libcalls to restore CSRs requires a tail call.
1124  // This means if we still need to continue executing code within this function
1125  // the restore cannot take place in this basic block.
1126 
1127  if (MBB.succ_size() > 1)
1128  return false;
1129 
1130  MachineBasicBlock *SuccMBB =
1131  MBB.succ_empty() ? TmpMBB->getFallThrough() : *MBB.succ_begin();
1132 
1133  // Doing a tail call should be safe if there are no successors, because either
1134  // we have a returning block or the end of the block is unreachable, so the
1135  // restore will be eliminated regardless.
1136  if (!SuccMBB)
1137  return true;
1138 
1139  // The successor can only contain a return, since we would effectively be
1140  // replacing the successor with our own tail return at the end of our block.
1141  return SuccMBB->isReturnBlock() && SuccMBB->size() == 1;
1142 }
1143 
1145  switch (ID) {
1148  return true;
1152  return false;
1153  }
1154  llvm_unreachable("Invalid TargetStackID::Value");
1155 }
1156 
1159 }
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:240
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
i
i
Definition: README.txt:29
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:148
getSpillLibCallName
static const char * getSpillLibCallName(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
Definition: RISCVFrameLowering.cpp:172
llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:353
llvm::MachineBasicBlock::succ_size
unsigned succ_size() const
Definition: MachineBasicBlock.h:344
llvm::RISCVAttrs::StackAlign
StackAlign
Definition: RISCVAttributes.h:37
MCDwarf.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm::MachineFrameInfo::estimateStackSize
uint64_t estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
Definition: MachineFrameInfo.cpp:137
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::TargetStackID::WasmLocal
@ WasmLocal
Definition: TargetFrameLowering.h:31
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::none_of
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1561
llvm::RISCVFrameLowering::spillCalleeSavedRegisters
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
Definition: RISCVFrameLowering.cpp:1013
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::DiagnosticInfoUnsupported
Diagnostic information for unsupported feature in backend.
Definition: DiagnosticInfo.h:1004
llvm::Function::hasOptNone
bool hasOptNone() const
Do not optimize this function (-O0).
Definition: Function.h:665
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:343
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
llvm::Register::id
unsigned id() const
Definition: Register.h:111
llvm::MachineInstrBuilder::addCFIIndex
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
Definition: MachineInstrBuilder.h:247
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::RISCVRegisterInfo
Definition: RISCVRegisterInfo.h:23
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::RISCVSubtarget::isRegisterReservedByUser
bool isRegisterReservedByUser(Register i) const
Definition: RISCVSubtarget.h:134
llvm::MachineFrameInfo::getOffsetAdjustment
int getOffsetAdjustment() const
Return the correction for frame offsets.
Definition: MachineFrameInfo.h:562
llvm::MachineBasicBlock::isReturnBlock
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction.
Definition: MachineBasicBlock.h:805
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
getRestoreLibCallName
static const char * getRestoreLibCallName(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
Definition: RISCVFrameLowering.cpp:199
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:321
llvm::StackOffset::getFixed
ScalarTy getFixed() const
Definition: TypeSize.h:149
llvm::RISCVFrameLowering::hasReservedCallFrame
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
Definition: RISCVFrameLowering.cpp:942
llvm::MachineFrameInfo::setStackSize
void setStackSize(uint64_t Size)
Set the size of the stack.
Definition: MachineFrameInfo.h:556
llvm::reverse
auto reverse(ContainerTy &&C, std::enable_if_t< has_rbegin< ContainerTy >::value > *=nullptr)
Definition: STLExtras.h:329
llvm::RISCVFrameLowering::getFrameIndexReference
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
Definition: RISCVFrameLowering.cpp:618
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::MachineFrameInfo::getObjectIndexEnd
int getObjectIndexEnd() const
Return one past the maximum frame object index.
Definition: MachineFrameInfo.h:393
getFPReg
static Register getFPReg(const RISCVSubtarget &STI)
Definition: RISCVFrameLowering.cpp:290
llvm::RISCVABI::getBPReg
MCRegister getBPReg()
Definition: RISCVBaseInfo.cpp:81
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
llvm::RISCVFrameLowering::emitPrologue
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
Definition: RISCVFrameLowering.cpp:334
llvm::MCCFIInstruction::cfiDefCfaOffset
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:502
MachineRegisterInfo.h
llvm::MachineInstr::FrameDestroy
@ FrameDestroy
Definition: MachineInstr.h:84
llvm::RegScavenger::isRegUsed
bool isRegUsed(Register Reg, bool includeReserved=true) const
Return if a specific register is currently used.
Definition: RegisterScavenging.cpp:262
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1299
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:636
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::TargetFrameLowering::getOffsetOfLocalArea
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
Definition: TargetFrameLowering.h:140
llvm::MutableArrayRef
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:307
llvm::RISCVFrameLowering::STI
const RISCVSubtarget & STI
Definition: RISCVFrameLowering.h:74
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:724
llvm::TargetFrameLowering::getStackAlign
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:100
llvm::Log2
unsigned Log2(Align A)
Returns the log2 of the alignment.
Definition: Alignment.h:207
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::RISCVFrameLowering::canUseAsPrologue
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a prologue for the target.
Definition: RISCVFrameLowering.cpp:1098
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MachineInstr::FrameSetup
@ FrameSetup
Definition: MachineInstr.h:82
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:146
llvm::MachineFrameInfo::getStackID
uint8_t getStackID(int ObjectIdx) const
Definition: MachineFrameInfo.h:699
llvm::RISCVABI::getSCSPReg
MCRegister getSCSPReg()
Definition: RISCVBaseInfo.cpp:84
llvm::MachineFrameInfo::getStackSize
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
Definition: MachineFrameInfo.h:553
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:494
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:44
llvm::RISCVFrameLowering::getFirstSPAdjustAmount
uint64_t getFirstSPAdjustAmount(const MachineFunction &MF) const
Definition: RISCVFrameLowering.cpp:987
llvm::BitVector
Definition: BitVector.h:74
llvm::RISCVSubtarget::getInstrInfo
const RISCVInstrInfo * getInstrInfo() const override
Definition: RISCVSubtarget.h:94
llvm::StackOffset::getScalable
ScalarTy getScalable() const
Definition: TypeSize.h:150
llvm::MachineFrameInfo::isFixedObjectIndex
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Definition: MachineFrameInfo.h:656
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:184
llvm::RISCVFrameLowering::enableShrinkWrapping
bool enableShrinkWrapping(const MachineFunction &MF) const override
Returns true if the target will correctly handle shrink wrapping.
Definition: RISCVFrameLowering.cpp:1090
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineFrameInfo::isDeadObjectIndex
bool isDeadObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a dead object.
Definition: MachineFrameInfo.h:713
llvm::TargetOptions::DisableFramePointerElim
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
Definition: TargetOptionsImpl.cpp:24
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
llvm::MachineInstrBuilder::setMIFlag
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
Definition: MachineInstrBuilder.h:278
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:626
llvm::TargetFrameLowering::alignSPAdjust
int alignSPAdjust(int SPAdj) const
alignSPAdjust - This method aligns the stack adjustment to the correct alignment.
Definition: TargetFrameLowering.h:105
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
uint64_t
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:453
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:239
llvm::HexagonInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index.
Definition: HexagonInstrInfo.cpp:913
llvm::TargetRegisterInfo::getFrameRegister
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
llvm::MachineRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
Definition: MachineRegisterInfo.cpp:621
emitSCSPrologue
static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL)
Definition: RISCVFrameLowering.cpp:28
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::MachineFrameInfo::setObjectOffset
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
Definition: MachineFrameInfo.h:528
llvm::TargetStackID::ScalableVector
@ ScalableVector
Definition: TargetFrameLowering.h:30
llvm::RISCVMachineFunctionInfo
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
Definition: RISCVMachineFunctionInfo.h:24
llvm::MachineBasicBlock::getLastNonDebugInstr
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
Definition: MachineBasicBlock.cpp:267
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
llvm::MachineInstr::NoFlags
@ NoFlags
Definition: MachineInstr.h:81
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:120
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineBasicBlock::size
unsigned size() const
Definition: MachineBasicBlock.h:239
llvm::RISCVFrameLowering::eliminateCallFramePseudoInstr
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
Definition: RISCVFrameLowering.cpp:948
llvm::MachineBasicBlock::succ_begin
succ_iterator succ_begin()
Definition: MachineBasicBlock.h:332
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:642
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::RegScavenger::addScavengingFrameIndex
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
Definition: RegisterScavenging.h:123
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:488
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineInstr::MIFlag
MIFlag
Definition: MachineInstr.h:80
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1528
llvm::MachineBasicBlock::succ_empty
bool succ_empty() const
Definition: MachineBasicBlock.h:347
llvm::MachineFrameInfo::getCalleeSavedInfo
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
Definition: MachineFrameInfo.h:755
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:242
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::RISCVInstrInfo
Definition: RISCVInstrInfo.h:43
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1554
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Definition: MachineFrameInfo.cpp:51
llvm::HexagonInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index.
Definition: HexagonInstrInfo.cpp:958
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::RISCVSubtarget::getRegisterInfo
const RISCVRegisterInfo * getRegisterInfo() const override
Definition: RISCVSubtarget.h:95
llvm::TargetStackID::NoAlloc
@ NoAlloc
Definition: TargetFrameLowering.h:32
hasRVVFrameObject
static bool hasRVVFrameObject(const MachineFunction &MF)
Definition: RISCVFrameLowering.cpp:930
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::RISCVFrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Definition: RISCVFrameLowering.cpp:223
emitSCSEpilogue
static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL)
Definition: RISCVFrameLowering.cpp:79
llvm::RISCVFrameLowering::processFunctionBeforeFrameFinalized
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
Definition: RISCVFrameLowering.cpp:872
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MachineFrameInfo::getMaxAlign
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Definition: MachineFrameInfo.h:569
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:367
llvm::MachineFrameInfo::isFrameAddressTaken
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
Definition: MachineFrameInfo.h:368
llvm::RegScavenger::enterBasicBlock
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
Definition: RegisterScavenging.cpp:84
llvm::MachineFrameInfo::hasCalls
bool hasCalls() const
Return true if the current function has any function calls.
Definition: MachineFrameInfo.h:581
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::LLVMContext::diagnose
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
Definition: LLVMContext.cpp:228
llvm::RISCVFrameLowering::emitEpilogue
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
Definition: RISCVFrameLowering.cpp:535
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:592
llvm::CalleeSavedInfo
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
Definition: MachineFrameInfo.h:34
uint16_t
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:622
MachineFrameInfo.h
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::RISCVFrameLowering::restoreCalleeSavedRegisters
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
Definition: RISCVFrameLowering.cpp:1049
DiagnosticInfo.h
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::RISCVSubtarget::getXLen
unsigned getXLen() const
Definition: RISCVSubtarget.h:132
llvm::TargetStackID::Default
@ Default
Definition: TargetFrameLowering.h:28
llvm::TargetStackID::SGPRSpill
@ SGPRSpill
Definition: TargetFrameLowering.h:29
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
llvm::MachineBasicBlock::getFallThrough
MachineBasicBlock * getFallThrough()
Return the fallthrough block if the block can implicitly transfer control to the block after it by fa...
Definition: MachineBasicBlock.cpp:917
RISCVSubtarget.h
llvm::TargetRegisterInfo::hasStackRealignment
bool hasStackRealignment(const MachineFunction &MF) const
True if stack realignment is required and still possible.
Definition: TargetRegisterInfo.h:936
llvm::RISCVII::MO_CALL
@ MO_CALL
Definition: RISCVBaseInfo.h:148
llvm::MachineFunction::addFrameInst
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
Definition: MachineFunction.cpp:285
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
getLibCallID
static int getLibCallID(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
Definition: RISCVFrameLowering.cpp:133
llvm::RISCVFrameLowering::getStackIDForScalableVectors
TargetStackID::Value getStackIDForScalableVectors() const override
Returns the StackID that scalable vectors should be associated with.
Definition: RISCVFrameLowering.cpp:1157
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
MachineInstrBuilder.h
getSPReg
static Register getSPReg(const RISCVSubtarget &STI)
Definition: RISCVFrameLowering.cpp:293
RISCVFrameLowering.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
RISCVMachineFunctionInfo.h
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::RISCVFrameLowering::canUseAsEpilogue
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
Definition: RISCVFrameLowering.cpp:1115
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:240
llvm::MCCFIInstruction::createOffset
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:526
hasRVVSpillWithFIs
static bool hasRVVSpillWithFIs(MachineFunction &MF, const RISCVInstrInfo &TII)
Definition: RISCVFrameLowering.cpp:862
llvm::TargetFrameLowering::determineCalleeSaves
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Definition: TargetFrameLoweringImpl.cpp:78
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineFrameInfo::adjustsStack
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
Definition: MachineFrameInfo.h:577
llvm::RISCVFrameLowering::isSupportedStackID
bool isSupportedStackID(TargetStackID::Value ID) const override
Definition: RISCVFrameLowering.cpp:1144
llvm::TargetRegisterInfo::getMinimalPhysRegClass
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:211
RegisterScavenging.h
llvm::RISCVFrameLowering::hasBP
bool hasBP(const MachineFunction &MF) const
Definition: RISCVFrameLowering.cpp:232
llvm::RISCVFrameLowering::determineCalleeSaves
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Definition: RISCVFrameLowering.cpp:786
MachineFunction.h
llvm::MachineInstrBundleIterator
MachineBasicBlock iterator that automatically skips over MIs that are inside bundles (i....
Definition: MachineInstrBundleIterator.h:108
llvm::RISCVSubtarget::hasStdExtF
bool hasStdExtF() const
Definition: RISCVSubtarget.h:107
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
llvm::CallingConv::GHC
@ GHC
Definition: CallingConv.h:51
getNonLibcallCSI
static SmallVector< CalleeSavedInfo, 8 > getNonLibcallCSI(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
Definition: RISCVFrameLowering.cpp:296
llvm::RISCVSubtarget::hasStdExtV
bool hasStdExtV() const
Definition: RISCVSubtarget.h:122
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37
llvm::StackOffset::get
static StackOffset get(ScalarTy Fixed, ScalarTy Scalable)
Definition: TypeSize.h:145