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RISCVFrameLowering.cpp
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1 //===-- RISCVFrameLowering.cpp - RISCV Frame Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of TargetFrameLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVFrameLowering.h"
15 #include "RISCVSubtarget.h"
21 #include "llvm/IR/DiagnosticInfo.h"
22 #include "llvm/MC/MCDwarf.h"
23 
24 using namespace llvm;
25 
26 // For now we use x18, a.k.a s2, as pointer to shadow call stack.
27 // User should explicitly set -ffixed-x18 and not use x18 in their asm.
30  const DebugLoc &DL) {
31  if (!MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack))
32  return;
33 
34  const auto &STI = MF.getSubtarget<RISCVSubtarget>();
35  Register RAReg = STI.getRegisterInfo()->getRARegister();
36 
37  // Do not save RA to the SCS if it's not saved to the regular stack,
38  // i.e. RA is not at risk of being overwritten.
39  std::vector<CalleeSavedInfo> &CSI = MF.getFrameInfo().getCalleeSavedInfo();
40  if (std::none_of(CSI.begin(), CSI.end(),
41  [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
42  return;
43 
44  Register SCSPReg = RISCVABI::getSCSPReg();
45 
46  auto &Ctx = MF.getFunction().getContext();
47  if (!STI.isRegisterReservedByUser(SCSPReg)) {
49  MF.getFunction(), "x18 not reserved by user for Shadow Call Stack."});
50  return;
51  }
52 
53  const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
54  if (RVFI->useSaveRestoreLibCalls(MF)) {
55  Ctx.diagnose(DiagnosticInfoUnsupported{
56  MF.getFunction(),
57  "Shadow Call Stack cannot be combined with Save/Restore LibCalls."});
58  return;
59  }
60 
61  const RISCVInstrInfo *TII = STI.getInstrInfo();
62  bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
63  int64_t SlotSize = STI.getXLen() / 8;
64  // Store return address to shadow call stack
65  // s[w|d] ra, 0(s2)
66  // addi s2, s2, [4|8]
67  BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW))
68  .addReg(RAReg)
69  .addReg(SCSPReg)
70  .addImm(0)
72  BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI))
73  .addReg(SCSPReg, RegState::Define)
74  .addReg(SCSPReg)
75  .addImm(SlotSize)
77 }
78 
81  const DebugLoc &DL) {
82  if (!MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack))
83  return;
84 
85  const auto &STI = MF.getSubtarget<RISCVSubtarget>();
86  Register RAReg = STI.getRegisterInfo()->getRARegister();
87 
88  // See emitSCSPrologue() above.
89  std::vector<CalleeSavedInfo> &CSI = MF.getFrameInfo().getCalleeSavedInfo();
90  if (std::none_of(CSI.begin(), CSI.end(),
91  [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
92  return;
93 
94  Register SCSPReg = RISCVABI::getSCSPReg();
95 
96  auto &Ctx = MF.getFunction().getContext();
97  if (!STI.isRegisterReservedByUser(SCSPReg)) {
99  MF.getFunction(), "x18 not reserved by user for Shadow Call Stack."});
100  return;
101  }
102 
103  const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
104  if (RVFI->useSaveRestoreLibCalls(MF)) {
105  Ctx.diagnose(DiagnosticInfoUnsupported{
106  MF.getFunction(),
107  "Shadow Call Stack cannot be combined with Save/Restore LibCalls."});
108  return;
109  }
110 
111  const RISCVInstrInfo *TII = STI.getInstrInfo();
112  bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
113  int64_t SlotSize = STI.getXLen() / 8;
114  // Load return address from shadow call stack
115  // l[w|d] ra, -[4|8](s2)
116  // addi s2, s2, -[4|8]
117  BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::LD : RISCV::LW))
118  .addReg(RAReg, RegState::Define)
119  .addReg(SCSPReg)
120  .addImm(-SlotSize)
122  BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI))
123  .addReg(SCSPReg, RegState::Define)
124  .addReg(SCSPReg)
125  .addImm(-SlotSize)
127 }
128 
129 // Get the ID of the libcall used for spilling and restoring callee saved
130 // registers. The ID is representative of the number of registers saved or
131 // restored by the libcall, except it is zero-indexed - ID 0 corresponds to a
132 // single register.
133 static int getLibCallID(const MachineFunction &MF,
134  const std::vector<CalleeSavedInfo> &CSI) {
135  const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
136 
137  if (CSI.empty() || !RVFI->useSaveRestoreLibCalls(MF))
138  return -1;
139 
140  Register MaxReg = RISCV::NoRegister;
141  for (auto &CS : CSI)
142  // RISCVRegisterInfo::hasReservedSpillSlot assigns negative frame indexes to
143  // registers which can be saved by libcall.
144  if (CS.getFrameIdx() < 0)
145  MaxReg = std::max(MaxReg.id(), CS.getReg().id());
146 
147  if (MaxReg == RISCV::NoRegister)
148  return -1;
149 
150  switch (MaxReg) {
151  default:
152  llvm_unreachable("Something has gone wrong!");
153  case /*s11*/ RISCV::X27: return 12;
154  case /*s10*/ RISCV::X26: return 11;
155  case /*s9*/ RISCV::X25: return 10;
156  case /*s8*/ RISCV::X24: return 9;
157  case /*s7*/ RISCV::X23: return 8;
158  case /*s6*/ RISCV::X22: return 7;
159  case /*s5*/ RISCV::X21: return 6;
160  case /*s4*/ RISCV::X20: return 5;
161  case /*s3*/ RISCV::X19: return 4;
162  case /*s2*/ RISCV::X18: return 3;
163  case /*s1*/ RISCV::X9: return 2;
164  case /*s0*/ RISCV::X8: return 1;
165  case /*ra*/ RISCV::X1: return 0;
166  }
167 }
168 
169 // Get the name of the libcall used for spilling callee saved registers.
170 // If this function will not use save/restore libcalls, then return a nullptr.
171 static const char *
173  const std::vector<CalleeSavedInfo> &CSI) {
174  static const char *const SpillLibCalls[] = {
175  "__riscv_save_0",
176  "__riscv_save_1",
177  "__riscv_save_2",
178  "__riscv_save_3",
179  "__riscv_save_4",
180  "__riscv_save_5",
181  "__riscv_save_6",
182  "__riscv_save_7",
183  "__riscv_save_8",
184  "__riscv_save_9",
185  "__riscv_save_10",
186  "__riscv_save_11",
187  "__riscv_save_12"
188  };
189 
190  int LibCallID = getLibCallID(MF, CSI);
191  if (LibCallID == -1)
192  return nullptr;
193  return SpillLibCalls[LibCallID];
194 }
195 
196 // Get the name of the libcall used for restoring callee saved registers.
197 // If this function will not use save/restore libcalls, then return a nullptr.
198 static const char *
200  const std::vector<CalleeSavedInfo> &CSI) {
201  static const char *const RestoreLibCalls[] = {
202  "__riscv_restore_0",
203  "__riscv_restore_1",
204  "__riscv_restore_2",
205  "__riscv_restore_3",
206  "__riscv_restore_4",
207  "__riscv_restore_5",
208  "__riscv_restore_6",
209  "__riscv_restore_7",
210  "__riscv_restore_8",
211  "__riscv_restore_9",
212  "__riscv_restore_10",
213  "__riscv_restore_11",
214  "__riscv_restore_12"
215  };
216 
217  int LibCallID = getLibCallID(MF, CSI);
218  if (LibCallID == -1)
219  return nullptr;
220  return RestoreLibCalls[LibCallID];
221 }
222 
223 // Return true if the specified function should have a dedicated frame
224 // pointer register. This is true if frame pointer elimination is
225 // disabled, if it needs dynamic stack realignment, if the function has
226 // variable sized allocas, or if the frame address is taken.
228  const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
229 
230  const MachineFrameInfo &MFI = MF.getFrameInfo();
231  return MF.getTarget().Options.DisableFramePointerElim(MF) ||
232  RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() ||
233  MFI.isFrameAddressTaken();
234 }
235 
237  const MachineFrameInfo &MFI = MF.getFrameInfo();
239 
240  // If we do not reserve stack space for outgoing arguments in prologue,
241  // we will adjust the stack pointer before call instruction. After the
242  // adjustment, we can not use SP to access the stack objects for the
243  // arguments. Instead, use BP to access these stack objects.
244  return (MFI.hasVarSizedObjects() ||
246  MFI.getMaxCallFrameSize() != 0))) &&
248 }
249 
250 // Determines the size of the frame and maximum call frame size.
251 void RISCVFrameLowering::determineFrameLayout(MachineFunction &MF) const {
252  MachineFrameInfo &MFI = MF.getFrameInfo();
253 
254  // Get the number of bytes to allocate from the FrameInfo.
255  uint64_t FrameSize = MFI.getStackSize();
256 
257  // Get the alignment.
259 
260  // Make sure the frame is aligned.
261  FrameSize = alignTo(FrameSize, StackAlign);
262 
263  // Update frame info.
264  MFI.setStackSize(FrameSize);
265 }
266 
267 void RISCVFrameLowering::adjustReg(MachineBasicBlock &MBB,
269  const DebugLoc &DL, Register DestReg,
270  Register SrcReg, int64_t Val,
271  MachineInstr::MIFlag Flag) const {
273  const RISCVInstrInfo *TII = STI.getInstrInfo();
274 
275  if (DestReg == SrcReg && Val == 0)
276  return;
277 
278  if (isInt<12>(Val)) {
279  BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg)
280  .addReg(SrcReg)
281  .addImm(Val)
282  .setMIFlag(Flag);
283  } else {
284  unsigned Opc = RISCV::ADD;
285  bool IsSub = Val < 0;
286  if (IsSub) {
287  Val = -Val;
288  Opc = RISCV::SUB;
289  }
290 
291  Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
292  TII->movImm(MBB, MBBI, DL, ScratchReg, Val, Flag);
293  BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
294  .addReg(SrcReg)
295  .addReg(ScratchReg, RegState::Kill)
296  .setMIFlag(Flag);
297  }
298 }
299 
300 // Returns the register used to hold the frame pointer.
301 static Register getFPReg(const RISCVSubtarget &STI) { return RISCV::X8; }
302 
303 // Returns the register used to hold the stack pointer.
304 static Register getSPReg(const RISCVSubtarget &STI) { return RISCV::X2; }
305 
308  const std::vector<CalleeSavedInfo> &CSI) {
309  const MachineFrameInfo &MFI = MF.getFrameInfo();
310  SmallVector<CalleeSavedInfo, 8> NonLibcallCSI;
311 
312  for (auto &CS : CSI) {
313  int FI = CS.getFrameIdx();
314  if (FI >= 0 && MFI.getStackID(FI) == TargetStackID::Default)
315  NonLibcallCSI.push_back(CS);
316  }
317 
318  return NonLibcallCSI;
319 }
320 
321 void RISCVFrameLowering::adjustStackForRVV(MachineFunction &MF,
324  const DebugLoc &DL, int64_t Amount,
325  MachineInstr::MIFlag Flag) const {
326  assert(Amount != 0 && "Did not need to adjust stack pointer for RVV.");
327 
328  const RISCVInstrInfo *TII = STI.getInstrInfo();
329  Register SPReg = getSPReg(STI);
330  unsigned Opc = RISCV::ADD;
331  if (Amount < 0) {
332  Amount = -Amount;
333  Opc = RISCV::SUB;
334  }
335  // 1. Multiply the number of v-slots to the length of registers
336  Register FactorRegister =
337  TII->getVLENFactoredAmount(MF, MBB, MBBI, DL, Amount, Flag);
338  // 2. SP = SP - RVV stack size
339  BuildMI(MBB, MBBI, DL, TII->get(Opc), SPReg)
340  .addReg(SPReg)
341  .addReg(FactorRegister, RegState::Kill)
342  .setMIFlag(Flag);
343 }
344 
346  MachineBasicBlock &MBB) const {
347  MachineFrameInfo &MFI = MF.getFrameInfo();
348  auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
349  const RISCVRegisterInfo *RI = STI.getRegisterInfo();
350  const RISCVInstrInfo *TII = STI.getInstrInfo();
352 
353  Register FPReg = getFPReg(STI);
354  Register SPReg = getSPReg(STI);
355  Register BPReg = RISCVABI::getBPReg();
356 
357  // Debug location must be unknown since the first debug location is used
358  // to determine the end of the prologue.
359  DebugLoc DL;
360 
361  // All calls are tail calls in GHC calling conv, and functions have no
362  // prologue/epilogue.
364  return;
365 
366  // Emit prologue for shadow call stack.
367  emitSCSPrologue(MF, MBB, MBBI, DL);
368 
369  // Since spillCalleeSavedRegisters may have inserted a libcall, skip past
370  // any instructions marked as FrameSetup
371  while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup))
372  ++MBBI;
373 
374  // Determine the correct frame layout
375  determineFrameLayout(MF);
376 
377  // If libcalls are used to spill and restore callee-saved registers, the frame
378  // has two sections; the opaque section managed by the libcalls, and the
379  // section managed by MachineFrameInfo which can also hold callee saved
380  // registers in fixed stack slots, both of which have negative frame indices.
381  // This gets even more complicated when incoming arguments are passed via the
382  // stack, as these too have negative frame indices. An example is detailed
383  // below:
384  //
385  // | incoming arg | <- FI[-3]
386  // | libcallspill |
387  // | calleespill | <- FI[-2]
388  // | calleespill | <- FI[-1]
389  // | this_frame | <- FI[0]
390  //
391  // For negative frame indices, the offset from the frame pointer will differ
392  // depending on which of these groups the frame index applies to.
393  // The following calculates the correct offset knowing the number of callee
394  // saved registers spilt by the two methods.
395  if (int LibCallRegs = getLibCallID(MF, MFI.getCalleeSavedInfo()) + 1) {
396  // Calculate the size of the frame managed by the libcall. The libcalls are
397  // implemented such that the stack will always be 16 byte aligned.
398  unsigned LibCallFrameSize = alignTo((STI.getXLen() / 8) * LibCallRegs, 16);
399  RVFI->setLibCallStackSize(LibCallFrameSize);
400  }
401 
402  // FIXME (note copied from Lanai): This appears to be overallocating. Needs
403  // investigation. Get the number of bytes to allocate from the FrameInfo.
404  uint64_t StackSize = MFI.getStackSize() + RVFI->getRVVPadding();
405  uint64_t RealStackSize = StackSize + RVFI->getLibCallStackSize();
406  uint64_t RVVStackSize = RVFI->getRVVStackSize();
407 
408  // Early exit if there is no need to allocate on the stack
409  if (RealStackSize == 0 && !MFI.adjustsStack() && RVVStackSize == 0)
410  return;
411 
412  // If the stack pointer has been marked as reserved, then produce an error if
413  // the frame requires stack allocation
414  if (STI.isRegisterReservedByUser(SPReg))
416  MF.getFunction(), "Stack pointer required, but has been reserved."});
417 
418  uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
419  // Split the SP adjustment to reduce the offsets of callee saved spill.
420  if (FirstSPAdjustAmount) {
421  StackSize = FirstSPAdjustAmount;
422  RealStackSize = FirstSPAdjustAmount;
423  }
424 
425  // Allocate space on the stack if necessary.
426  adjustReg(MBB, MBBI, DL, SPReg, SPReg, -StackSize, MachineInstr::FrameSetup);
427 
428  // Emit ".cfi_def_cfa_offset RealStackSize"
429  unsigned CFIIndex = MF.addFrameInst(
430  MCCFIInstruction::cfiDefCfaOffset(nullptr, RealStackSize));
431  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
432  .addCFIIndex(CFIIndex)
434 
435  const auto &CSI = MFI.getCalleeSavedInfo();
436 
437  // The frame pointer is callee-saved, and code has been generated for us to
438  // save it to the stack. We need to skip over the storing of callee-saved
439  // registers as the frame pointer must be modified after it has been saved
440  // to the stack, not before.
441  // FIXME: assumes exactly one instruction is used to save each callee-saved
442  // register.
443  std::advance(MBBI, getNonLibcallCSI(MF, CSI).size());
444 
445  // Iterate over list of callee-saved registers and emit .cfi_offset
446  // directives.
447  for (const auto &Entry : CSI) {
448  int FrameIdx = Entry.getFrameIdx();
449  int64_t Offset;
450  // Offsets for objects with fixed locations (IE: those saved by libcall) are
451  // simply calculated from the frame index.
452  if (FrameIdx < 0)
453  Offset = FrameIdx * (int64_t) STI.getXLen() / 8;
454  else
455  Offset = MFI.getObjectOffset(Entry.getFrameIdx()) -
456  RVFI->getLibCallStackSize();
457  Register Reg = Entry.getReg();
458  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
459  nullptr, RI->getDwarfRegNum(Reg, true), Offset));
460  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
461  .addCFIIndex(CFIIndex)
463  }
464 
465  // Generate new FP.
466  if (hasFP(MF)) {
467  if (STI.isRegisterReservedByUser(FPReg))
469  MF.getFunction(), "Frame pointer required, but has been reserved."});
470 
471  adjustReg(MBB, MBBI, DL, FPReg, SPReg,
472  RealStackSize - RVFI->getVarArgsSaveSize(),
474 
475  // Emit ".cfi_def_cfa $fp, RVFI->getVarArgsSaveSize()"
476  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
477  nullptr, RI->getDwarfRegNum(FPReg, true), RVFI->getVarArgsSaveSize()));
478  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
479  .addCFIIndex(CFIIndex)
481  }
482 
483  // Emit the second SP adjustment after saving callee saved registers.
484  if (FirstSPAdjustAmount) {
485  uint64_t SecondSPAdjustAmount = MFI.getStackSize() - FirstSPAdjustAmount;
486  assert(SecondSPAdjustAmount > 0 &&
487  "SecondSPAdjustAmount should be greater than zero");
488  adjustReg(MBB, MBBI, DL, SPReg, SPReg, -SecondSPAdjustAmount,
490 
491  // If we are using a frame-pointer, and thus emitted ".cfi_def_cfa fp, 0",
492  // don't emit an sp-based .cfi_def_cfa_offset
493  if (!hasFP(MF)) {
494  // Emit ".cfi_def_cfa_offset StackSize"
495  unsigned CFIIndex = MF.addFrameInst(
497  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
498  .addCFIIndex(CFIIndex)
500  }
501  }
502 
503  if (RVVStackSize)
504  adjustStackForRVV(MF, MBB, MBBI, DL, -RVVStackSize,
506 
507  if (hasFP(MF)) {
508  // Realign Stack
509  const RISCVRegisterInfo *RI = STI.getRegisterInfo();
510  if (RI->hasStackRealignment(MF)) {
511  Align MaxAlignment = MFI.getMaxAlign();
512 
513  const RISCVInstrInfo *TII = STI.getInstrInfo();
514  if (isInt<12>(-(int)MaxAlignment.value())) {
515  BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg)
516  .addReg(SPReg)
517  .addImm(-(int)MaxAlignment.value())
519  } else {
520  unsigned ShiftAmount = Log2(MaxAlignment);
521  Register VR =
522  MF.getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
523  BuildMI(MBB, MBBI, DL, TII->get(RISCV::SRLI), VR)
524  .addReg(SPReg)
525  .addImm(ShiftAmount)
527  BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), SPReg)
528  .addReg(VR)
529  .addImm(ShiftAmount)
531  }
532  // FP will be used to restore the frame in the epilogue, so we need
533  // another base register BP to record SP after re-alignment. SP will
534  // track the current stack after allocating variable sized objects.
535  if (hasBP(MF)) {
536  // move BP, SP
537  BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), BPReg)
538  .addReg(SPReg)
539  .addImm(0)
541  }
542  }
543  }
544 }
545 
547  MachineBasicBlock &MBB) const {
548  const RISCVRegisterInfo *RI = STI.getRegisterInfo();
549  MachineFrameInfo &MFI = MF.getFrameInfo();
550  auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
551  Register FPReg = getFPReg(STI);
552  Register SPReg = getSPReg(STI);
553 
554  // All calls are tail calls in GHC calling conv, and functions have no
555  // prologue/epilogue.
557  return;
558 
559  // Get the insert location for the epilogue. If there were no terminators in
560  // the block, get the last instruction.
562  DebugLoc DL;
563  if (!MBB.empty()) {
565  if (MBBI != MBB.end())
566  DL = MBBI->getDebugLoc();
567 
569 
570  // If callee-saved registers are saved via libcall, place stack adjustment
571  // before this call.
572  while (MBBI != MBB.begin() &&
573  std::prev(MBBI)->getFlag(MachineInstr::FrameDestroy))
574  --MBBI;
575  }
576 
577  const auto &CSI = getNonLibcallCSI(MF, MFI.getCalleeSavedInfo());
578 
579  // Skip to before the restores of callee-saved registers
580  // FIXME: assumes exactly one instruction is used to restore each
581  // callee-saved register.
582  auto LastFrameDestroy = MBBI;
583  if (!CSI.empty())
584  LastFrameDestroy = std::prev(MBBI, CSI.size());
585 
586  uint64_t StackSize = MFI.getStackSize() + RVFI->getRVVPadding();
587  uint64_t RealStackSize = StackSize + RVFI->getLibCallStackSize();
588  uint64_t FPOffset = RealStackSize - RVFI->getVarArgsSaveSize();
589  uint64_t RVVStackSize = RVFI->getRVVStackSize();
590 
591  // Restore the stack pointer using the value of the frame pointer. Only
592  // necessary if the stack pointer was modified, meaning the stack size is
593  // unknown.
594  if (RI->hasStackRealignment(MF) || MFI.hasVarSizedObjects()) {
595  assert(hasFP(MF) && "frame pointer should not have been eliminated");
596  adjustReg(MBB, LastFrameDestroy, DL, SPReg, FPReg, -FPOffset,
598  } else {
599  if (RVVStackSize)
600  adjustStackForRVV(MF, MBB, LastFrameDestroy, DL, RVVStackSize,
602  }
603 
604  uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
605  if (FirstSPAdjustAmount) {
606  uint64_t SecondSPAdjustAmount = MFI.getStackSize() - FirstSPAdjustAmount;
607  assert(SecondSPAdjustAmount > 0 &&
608  "SecondSPAdjustAmount should be greater than zero");
609 
610  adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg, SecondSPAdjustAmount,
612  }
613 
614  if (FirstSPAdjustAmount)
615  StackSize = FirstSPAdjustAmount;
616 
617  // Deallocate stack
618  adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy);
619 
620  // Emit epilogue for shadow call stack.
621  emitSCSEpilogue(MF, MBB, MBBI, DL);
622 }
623 
626  Register &FrameReg) const {
627  const MachineFrameInfo &MFI = MF.getFrameInfo();
629  const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
630 
631  // Callee-saved registers should be referenced relative to the stack
632  // pointer (positive offset), otherwise use the frame pointer (negative
633  // offset).
634  const auto &CSI = getNonLibcallCSI(MF, MFI.getCalleeSavedInfo());
635  int MinCSFI = 0;
636  int MaxCSFI = -1;
637  StackOffset Offset;
638  auto StackID = MFI.getStackID(FI);
639 
640  assert((StackID == TargetStackID::Default ||
641  StackID == TargetStackID::ScalableVector) &&
642  "Unexpected stack ID for the frame object.");
643  if (StackID == TargetStackID::Default) {
644  Offset =
646  MFI.getOffsetAdjustment());
647  } else if (StackID == TargetStackID::ScalableVector) {
648  Offset = StackOffset::getScalable(MFI.getObjectOffset(FI));
649  }
650 
651  uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
652 
653  if (CSI.size()) {
654  MinCSFI = CSI[0].getFrameIdx();
655  MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
656  }
657 
658  if (FI >= MinCSFI && FI <= MaxCSFI) {
659  FrameReg = RISCV::X2;
660 
661  if (FirstSPAdjustAmount)
662  Offset += StackOffset::getFixed(FirstSPAdjustAmount);
663  else
664  Offset +=
665  StackOffset::getFixed(MFI.getStackSize() + RVFI->getRVVPadding());
666  } else if (RI->hasStackRealignment(MF) && !MFI.isFixedObjectIndex(FI)) {
667  // If the stack was realigned, the frame pointer is set in order to allow
668  // SP to be restored, so we need another base register to record the stack
669  // after realignment.
670  if (hasBP(MF)) {
671  FrameReg = RISCVABI::getBPReg();
672  // |--------------------------| -- <-- FP
673  // | callee-allocated save | | <----|
674  // | area for register varargs| | |
675  // |--------------------------| | |
676  // | callee-saved registers | | |
677  // |--------------------------| -- |
678  // | realignment (the size of | | |
679  // | this area is not counted | | |
680  // | in MFI.getStackSize()) | | |
681  // |--------------------------| -- |
682  // | Padding after RVV | | |
683  // | (not counted in | | |
684  // | MFI.getStackSize()) | | |
685  // |--------------------------| -- |-- MFI.getStackSize()
686  // | RVV objects | | |
687  // | (not counted in | | |
688  // | MFI.getStackSize()) | | |
689  // |--------------------------| -- |
690  // | Padding before RVV | | |
691  // | (not counted in | | |
692  // | MFI.getStackSize()) | | |
693  // |--------------------------| -- |
694  // | scalar local variables | | <----'
695  // |--------------------------| -- <-- BP
696  // | VarSize objects | |
697  // |--------------------------| -- <-- SP
698  } else {
699  FrameReg = RISCV::X2;
700  // |--------------------------| -- <-- FP
701  // | callee-allocated save | | <----|
702  // | area for register varargs| | |
703  // |--------------------------| | |
704  // | callee-saved registers | | |
705  // |--------------------------| -- |
706  // | realignment (the size of | | |
707  // | this area is not counted | | |
708  // | in MFI.getStackSize()) | | |
709  // |--------------------------| -- |
710  // | Padding after RVV | | |
711  // | (not counted in | | |
712  // | MFI.getStackSize()) | | |
713  // |--------------------------| -- |-- MFI.getStackSize()
714  // | RVV objects | | |
715  // | (not counted in | | |
716  // | MFI.getStackSize()) | | |
717  // |--------------------------| -- |
718  // | Padding before RVV | | |
719  // | (not counted in | | |
720  // | MFI.getStackSize()) | | |
721  // |--------------------------| -- |
722  // | scalar local variables | | <----'
723  // |--------------------------| -- <-- SP
724  }
725  // The total amount of padding surrounding RVV objects is described by
726  // RVV->getRVVPadding() and it can be zero. It allows us to align the RVV
727  // objects to 8 bytes.
728  if (MFI.getStackID(FI) == TargetStackID::Default) {
729  Offset += StackOffset::getFixed(MFI.getStackSize());
730  if (FI < 0)
731  Offset += StackOffset::getFixed(RVFI->getLibCallStackSize());
732  } else if (MFI.getStackID(FI) == TargetStackID::ScalableVector) {
733  Offset += StackOffset::get(
734  alignTo(MFI.getStackSize() - RVFI->getCalleeSavedStackSize(), 8),
735  RVFI->getRVVStackSize());
736  }
737  } else {
738  FrameReg = RI->getFrameRegister(MF);
739  if (hasFP(MF)) {
740  Offset += StackOffset::getFixed(RVFI->getVarArgsSaveSize());
741  if (FI >= 0)
742  Offset -= StackOffset::getFixed(RVFI->getLibCallStackSize());
743  // When using FP to access scalable vector objects, we need to minus
744  // the frame size.
745  //
746  // |--------------------------| -- <-- FP
747  // | callee-allocated save | |
748  // | area for register varargs| |
749  // |--------------------------| |
750  // | callee-saved registers | |
751  // |--------------------------| | MFI.getStackSize()
752  // | scalar local variables | |
753  // |--------------------------| -- (Offset of RVV objects is from here.)
754  // | RVV objects |
755  // |--------------------------|
756  // | VarSize objects |
757  // |--------------------------| <-- SP
759  Offset -= StackOffset::getFixed(MFI.getStackSize());
760  } else {
761  // When using SP to access frame objects, we need to add RVV stack size.
762  //
763  // |--------------------------| -- <-- FP
764  // | callee-allocated save | | <----|
765  // | area for register varargs| | |
766  // |--------------------------| | |
767  // | callee-saved registers | | |
768  // |--------------------------| -- |
769  // | Padding after RVV | | |
770  // | (not counted in | | |
771  // | MFI.getStackSize()) | | |
772  // |--------------------------| -- |
773  // | RVV objects | | |-- MFI.getStackSize()
774  // | (not counted in | | |
775  // | MFI.getStackSize()) | | |
776  // |--------------------------| -- |
777  // | Padding before RVV | | |
778  // | (not counted in | | |
779  // | MFI.getStackSize()) | | |
780  // |--------------------------| -- |
781  // | scalar local variables | | <----'
782  // |--------------------------| -- <-- SP
783  //
784  // The total amount of padding surrounding RVV objects is described by
785  // RVV->getRVVPadding() and it can be zero. It allows us to align the RVV
786  // objects to 8 bytes.
787  if (MFI.getStackID(FI) == TargetStackID::Default) {
788  if (MFI.isFixedObjectIndex(FI)) {
789  Offset +=
790  StackOffset::get(MFI.getStackSize() + RVFI->getRVVPadding() +
791  RVFI->getLibCallStackSize(),
792  RVFI->getRVVStackSize());
793  } else {
794  Offset += StackOffset::getFixed(MFI.getStackSize());
795  }
796  } else if (MFI.getStackID(FI) == TargetStackID::ScalableVector) {
797  int ScalarLocalVarSize = MFI.getStackSize() -
798  RVFI->getCalleeSavedStackSize() -
799  RVFI->getVarArgsSaveSize();
800  Offset += StackOffset::get(
801  alignTo(ScalarLocalVarSize, 8),
802  RVFI->getRVVStackSize());
803  }
804  }
805  }
806 
807  return Offset;
808 }
809 
811  BitVector &SavedRegs,
812  RegScavenger *RS) const {
814  // Unconditionally spill RA and FP only if the function uses a frame
815  // pointer.
816  if (hasFP(MF)) {
817  SavedRegs.set(RISCV::X1);
818  SavedRegs.set(RISCV::X8);
819  }
820  // Mark BP as used if function has dedicated base pointer.
821  if (hasBP(MF))
822  SavedRegs.set(RISCVABI::getBPReg());
823 
824  // If interrupt is enabled and there are calls in the handler,
825  // unconditionally save all Caller-saved registers and
826  // all FP registers, regardless whether they are used.
827  MachineFrameInfo &MFI = MF.getFrameInfo();
828 
829  if (MF.getFunction().hasFnAttribute("interrupt") && MFI.hasCalls()) {
830 
831  static const MCPhysReg CSRegs[] = { RISCV::X1, /* ra */
832  RISCV::X5, RISCV::X6, RISCV::X7, /* t0-t2 */
833  RISCV::X10, RISCV::X11, /* a0-a1, a2-a7 */
834  RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17,
835  RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, 0 /* t3-t6 */
836  };
837 
838  for (unsigned i = 0; CSRegs[i]; ++i)
839  SavedRegs.set(CSRegs[i]);
840 
841  if (MF.getSubtarget<RISCVSubtarget>().hasStdExtF()) {
842 
843  // If interrupt is enabled, this list contains all FP registers.
844  const MCPhysReg * Regs = MF.getRegInfo().getCalleeSavedRegs();
845 
846  for (unsigned i = 0; Regs[i]; ++i)
847  if (RISCV::FPR16RegClass.contains(Regs[i]) ||
848  RISCV::FPR32RegClass.contains(Regs[i]) ||
849  RISCV::FPR64RegClass.contains(Regs[i]))
850  SavedRegs.set(Regs[i]);
851  }
852  }
853 }
854 
855 int64_t
856 RISCVFrameLowering::assignRVVStackObjectOffsets(MachineFrameInfo &MFI) const {
857  // Create a buffer of RVV objects to allocate.
858  SmallVector<int, 8> ObjectsToAllocate;
859  for (int I = 0, E = MFI.getObjectIndexEnd(); I != E; ++I) {
860  unsigned StackID = MFI.getStackID(I);
861  if (StackID != TargetStackID::ScalableVector)
862  continue;
863  if (MFI.isDeadObjectIndex(I))
864  continue;
865 
866  ObjectsToAllocate.push_back(I);
867  }
868 
869  // Allocate all RVV locals and spills
870  int64_t Offset = 0;
871  for (int FI : ObjectsToAllocate) {
872  // ObjectSize in bytes.
873  int64_t ObjectSize = MFI.getObjectSize(FI);
874  // If the data type is the fractional vector type, reserve one vector
875  // register for it.
876  if (ObjectSize < 8)
877  ObjectSize = 8;
878  // Currently, all scalable vector types are aligned to 8 bytes.
879  Offset = alignTo(Offset + ObjectSize, 8);
880  MFI.setObjectOffset(FI, -Offset);
881  }
882 
883  return Offset;
884 }
885 
888  return false;
889  return any_of(MF, [&TII](const MachineBasicBlock &MBB) {
890  return any_of(MBB, [&TII](const MachineInstr &MI) {
891  return TII.isRVVSpill(MI, /*CheckFIs*/ true);
892  });
893  });
894 }
895 
897  MachineFunction &MF, RegScavenger *RS) const {
898  const RISCVRegisterInfo *RegInfo =
899  MF.getSubtarget<RISCVSubtarget>().getRegisterInfo();
900  MachineFrameInfo &MFI = MF.getFrameInfo();
901  const TargetRegisterClass *RC = &RISCV::GPRRegClass;
902  auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
903 
904  int64_t RVVStackSize = assignRVVStackObjectOffsets(MFI);
905  RVFI->setRVVStackSize(RVVStackSize);
906  const RISCVInstrInfo &TII = *MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
907 
908  // estimateStackSize has been observed to under-estimate the final stack
909  // size, so give ourselves wiggle-room by checking for stack size
910  // representable an 11-bit signed field rather than 12-bits.
911  // FIXME: It may be possible to craft a function with a small stack that
912  // still needs an emergency spill slot for branch relaxation. This case
913  // would currently be missed.
914  // RVV loads & stores have no capacity to hold the immediate address offsets
915  // so we must always reserve an emergency spill slot if the MachineFunction
916  // contains any RVV spills.
917  if (!isInt<11>(MFI.estimateStackSize(MF)) || hasRVVSpillWithFIs(MF, TII)) {
918  int RegScavFI = MFI.CreateStackObject(RegInfo->getSpillSize(*RC),
919  RegInfo->getSpillAlign(*RC), false);
920  RS->addScavengingFrameIndex(RegScavFI);
921  // For RVV, scalable stack offsets require up to two scratch registers to
922  // compute the final offset. Reserve an additional emergency spill slot.
923  if (RVVStackSize != 0) {
924  int RVVRegScavFI = MFI.CreateStackObject(
925  RegInfo->getSpillSize(*RC), RegInfo->getSpillAlign(*RC), false);
926  RS->addScavengingFrameIndex(RVVRegScavFI);
927  }
928  }
929 
930  if (MFI.getCalleeSavedInfo().empty() || RVFI->useSaveRestoreLibCalls(MF)) {
931  RVFI->setCalleeSavedStackSize(0);
932  return;
933  }
934 
935  unsigned Size = 0;
936  for (const auto &Info : MFI.getCalleeSavedInfo()) {
937  int FrameIdx = Info.getFrameIdx();
938  if (MFI.getStackID(FrameIdx) != TargetStackID::Default)
939  continue;
940 
941  Size += MFI.getObjectSize(FrameIdx);
942  }
943  RVFI->setCalleeSavedStackSize(Size);
944 
945  // Padding required to keep the RVV stack aligned to 8 bytes within the main
946  // stack. We only need this when using SP or BP to access stack objects.
948  if (RVVStackSize && (!hasFP(MF) || TRI->hasStackRealignment(MF)) &&
949  Size % 8 != 0) {
950  // Because we add the padding to the size of the stack, adding
951  // getStackAlign() will keep it aligned.
952  RVFI->setRVVPadding(getStackAlign().value());
953  }
954 }
955 
956 static bool hasRVVFrameObject(const MachineFunction &MF) {
957  // Originally, the function will scan all the stack objects to check whether
958  // if there is any scalable vector object on the stack or not. However, it
959  // causes errors in the register allocator. In issue 53016, it returns false
960  // before RA because there is no RVV stack objects. After RA, it returns true
961  // because there are spilling slots for RVV values during RA. It will not
962  // reserve BP during register allocation and generate BP access in the PEI
963  // pass due to the inconsistent behavior of the function.
964  //
965  // The function is changed to use hasVInstructions() as the return value. It
966  // is not precise, but it can make the register allocation correct.
967  //
968  // FIXME: Find a better way to make the decision or revisit the solution in
969  // D103622.
970  //
971  // Refer to https://github.com/llvm/llvm-project/issues/53016.
972  return MF.getSubtarget<RISCVSubtarget>().hasVInstructions();
973 }
974 
975 // Not preserve stack space within prologue for outgoing variables when the
976 // function contains variable size objects or there are vector objects accessed
977 // by the frame pointer.
978 // Let eliminateCallFramePseudoInstr preserve stack space for it.
980  return !MF.getFrameInfo().hasVarSizedObjects() &&
981  !(hasFP(MF) && hasRVVFrameObject(MF));
982 }
983 
984 // Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions.
988  Register SPReg = RISCV::X2;
989  DebugLoc DL = MI->getDebugLoc();
990 
991  if (!hasReservedCallFrame(MF)) {
992  // If space has not been reserved for a call frame, ADJCALLSTACKDOWN and
993  // ADJCALLSTACKUP must be converted to instructions manipulating the stack
994  // pointer. This is necessary when there is a variable length stack
995  // allocation (e.g. alloca), which means it's not possible to allocate
996  // space for outgoing arguments from within the function prologue.
997  int64_t Amount = MI->getOperand(0).getImm();
998 
999  if (Amount != 0) {
1000  // Ensure the stack remains aligned after adjustment.
1001  Amount = alignSPAdjust(Amount);
1002 
1003  if (MI->getOpcode() == RISCV::ADJCALLSTACKDOWN)
1004  Amount = -Amount;
1005 
1006  adjustReg(MBB, MI, DL, SPReg, SPReg, Amount, MachineInstr::NoFlags);
1007  }
1008  }
1009 
1010  return MBB.erase(MI);
1011 }
1012 
1013 // We would like to split the SP adjustment to reduce prologue/epilogue
1014 // as following instructions. In this way, the offset of the callee saved
1015 // register could fit in a single store.
1016 // add sp,sp,-2032
1017 // sw ra,2028(sp)
1018 // sw s0,2024(sp)
1019 // sw s1,2020(sp)
1020 // sw s3,2012(sp)
1021 // sw s4,2008(sp)
1022 // add sp,sp,-64
1023 uint64_t
1025  const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
1026  const MachineFrameInfo &MFI = MF.getFrameInfo();
1027  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
1028  uint64_t StackSize = MFI.getStackSize();
1029 
1030  // Disable SplitSPAdjust if save-restore libcall is used. The callee-saved
1031  // registers will be pushed by the save-restore libcalls, so we don't have to
1032  // split the SP adjustment in this case.
1033  if (RVFI->getLibCallStackSize())
1034  return 0;
1035 
1036  // Return the FirstSPAdjustAmount if the StackSize can not fit in a signed
1037  // 12-bit and there exists a callee-saved register needing to be pushed.
1038  if (!isInt<12>(StackSize) && (CSI.size() > 0)) {
1039  // FirstSPAdjustAmount is chosen as (2048 - StackAlign) because 2048 will
1040  // cause sp = sp + 2048 in the epilogue to be split into multiple
1041  // instructions. Offsets smaller than 2048 can fit in a single load/store
1042  // instruction, and we have to stick with the stack alignment. 2048 has
1043  // 16-byte alignment. The stack alignment for RV32 and RV64 is 16 and for
1044  // RV32E it is 4. So (2048 - StackAlign) will satisfy the stack alignment.
1045  return 2048 - getStackAlign().value();
1046  }
1047  return 0;
1048 }
1049 
1052  ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
1053  if (CSI.empty())
1054  return true;
1055 
1056  MachineFunction *MF = MBB.getParent();
1057  const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
1058  DebugLoc DL;
1059  if (MI != MBB.end() && !MI->isDebugInstr())
1060  DL = MI->getDebugLoc();
1061 
1062  const char *SpillLibCall = getSpillLibCallName(*MF, CSI);
1063  if (SpillLibCall) {
1064  // Add spill libcall via non-callee-saved register t0.
1065  BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoCALLReg), RISCV::X5)
1066  .addExternalSymbol(SpillLibCall, RISCVII::MO_CALL)
1068 
1069  // Add registers spilled in libcall as liveins.
1070  for (auto &CS : CSI)
1071  MBB.addLiveIn(CS.getReg());
1072  }
1073 
1074  // Manually spill values not spilled by libcall.
1075  const auto &NonLibcallCSI = getNonLibcallCSI(*MF, CSI);
1076  for (auto &CS : NonLibcallCSI) {
1077  // Insert the spill to the stack frame.
1078  Register Reg = CS.getReg();
1080  TII.storeRegToStackSlot(MBB, MI, Reg, !MBB.isLiveIn(Reg), CS.getFrameIdx(),
1081  RC, TRI);
1082  }
1083 
1084  return true;
1085 }
1086 
1090  if (CSI.empty())
1091  return true;
1092 
1093  MachineFunction *MF = MBB.getParent();
1094  const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
1095  DebugLoc DL;
1096  if (MI != MBB.end() && !MI->isDebugInstr())
1097  DL = MI->getDebugLoc();
1098 
1099  // Manually restore values not restored by libcall.
1100  // Keep the same order as in the prologue. There is no need to reverse the
1101  // order in the epilogue. In addition, the return address will be restored
1102  // first in the epilogue. It increases the opportunity to avoid the
1103  // load-to-use data hazard between loading RA and return by RA.
1104  // loadRegFromStackSlot can insert multiple instructions.
1105  const auto &NonLibcallCSI = getNonLibcallCSI(*MF, CSI);
1106  for (auto &CS : NonLibcallCSI) {
1107  Register Reg = CS.getReg();
1109  TII.loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI);
1110  assert(MI != MBB.begin() && "loadRegFromStackSlot didn't insert any code!");
1111  }
1112 
1113  const char *RestoreLibCall = getRestoreLibCallName(*MF, CSI);
1114  if (RestoreLibCall) {
1115  // Add restore libcall via tail call.
1117  BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoTAIL))
1118  .addExternalSymbol(RestoreLibCall, RISCVII::MO_CALL)
1120 
1121  // Remove trailing returns, since the terminator is now a tail call to the
1122  // restore function.
1123  if (MI != MBB.end() && MI->getOpcode() == RISCV::PseudoRET) {
1124  NewMI->copyImplicitOps(*MF, *MI);
1125  MI->eraseFromParent();
1126  }
1127  }
1128 
1129  return true;
1130 }
1131 
1133  MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
1134  const MachineFunction *MF = MBB.getParent();
1135  const auto *RVFI = MF->getInfo<RISCVMachineFunctionInfo>();
1136 
1137  if (!RVFI->useSaveRestoreLibCalls(*MF))
1138  return true;
1139 
1140  // Inserting a call to a __riscv_save libcall requires the use of the register
1141  // t0 (X5) to hold the return address. Therefore if this register is already
1142  // used we can't insert the call.
1143 
1144  RegScavenger RS;
1145  RS.enterBasicBlock(*TmpMBB);
1146  return !RS.isRegUsed(RISCV::X5);
1147 }
1148 
1150  const MachineFunction *MF = MBB.getParent();
1151  MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
1152  const auto *RVFI = MF->getInfo<RISCVMachineFunctionInfo>();
1153 
1154  if (!RVFI->useSaveRestoreLibCalls(*MF))
1155  return true;
1156 
1157  // Using the __riscv_restore libcalls to restore CSRs requires a tail call.
1158  // This means if we still need to continue executing code within this function
1159  // the restore cannot take place in this basic block.
1160 
1161  if (MBB.succ_size() > 1)
1162  return false;
1163 
1164  MachineBasicBlock *SuccMBB =
1165  MBB.succ_empty() ? TmpMBB->getFallThrough() : *MBB.succ_begin();
1166 
1167  // Doing a tail call should be safe if there are no successors, because either
1168  // we have a returning block or the end of the block is unreachable, so the
1169  // restore will be eliminated regardless.
1170  if (!SuccMBB)
1171  return true;
1172 
1173  // The successor can only contain a return, since we would effectively be
1174  // replacing the successor with our own tail return at the end of our block.
1175  return SuccMBB->isReturnBlock() && SuccMBB->size() == 1;
1176 }
1177 
1179  switch (ID) {
1182  return true;
1186  return false;
1187  }
1188  llvm_unreachable("Invalid TargetStackID::Value");
1189 }
1190 
1193 }
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:240
i
i
Definition: README.txt:29
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:148
getSpillLibCallName
static const char * getSpillLibCallName(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
Definition: RISCVFrameLowering.cpp:172
llvm::MachineFrameInfo::isMaxCallFrameSizeComputed
bool isMaxCallFrameSizeComputed() const
Definition: MachineFrameInfo.h:653
llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:354
llvm::MachineBasicBlock::succ_size
unsigned succ_size() const
Definition: MachineBasicBlock.h:353
llvm::RISCVAttrs::StackAlign
StackAlign
Definition: RISCVAttributes.h:37
MCDwarf.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm::MachineFrameInfo::estimateStackSize
uint64_t estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
Definition: MachineFrameInfo.cpp:137
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::TargetStackID::WasmLocal
@ WasmLocal
Definition: TargetFrameLowering.h:31
llvm::none_of
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1621
llvm::MachineBasicBlock::isLiveIn
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
Definition: MachineBasicBlock.cpp:576
llvm::RISCVFrameLowering::spillCalleeSavedRegisters
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
Definition: RISCVFrameLowering.cpp:1050
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:44
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::DiagnosticInfoUnsupported
Diagnostic information for unsupported feature in backend.
Definition: DiagnosticInfo.h:1009
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:344
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:93
llvm::Register::id
unsigned id() const
Definition: Register.h:111
llvm::MachineInstrBuilder::addCFIIndex
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
Definition: MachineInstrBuilder.h:247
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::RISCVRegisterInfo
Definition: RISCVRegisterInfo.h:23
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::RISCVSubtarget::isRegisterReservedByUser
bool isRegisterReservedByUser(Register i) const
Definition: RISCVSubtarget.h:211
llvm::RISCVSubtarget::hasVInstructions
bool hasVInstructions() const
Definition: RISCVSubtarget.h:217
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineFrameInfo::getOffsetAdjustment
int getOffsetAdjustment() const
Return the correction for frame offsets.
Definition: MachineFrameInfo.h:586
llvm::MachineBasicBlock::isReturnBlock
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction.
Definition: MachineBasicBlock.h:827
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:125
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
getRestoreLibCallName
static const char * getRestoreLibCallName(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
Definition: RISCVFrameLowering.cpp:199
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:319
llvm::StackOffset::getFixed
ScalarTy getFixed() const
Definition: TypeSize.h:149
llvm::RISCVFrameLowering::hasReservedCallFrame
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
Definition: RISCVFrameLowering.cpp:979
llvm::MachineFrameInfo::setStackSize
void setStackSize(uint64_t Size)
Set the size of the stack.
Definition: MachineFrameInfo.h:580
llvm::CallingConv::GHC
@ GHC
Definition: CallingConv.h:51
llvm::RISCVFrameLowering::getFrameIndexReference
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
Definition: RISCVFrameLowering.cpp:625
llvm::MachineFrameInfo::getObjectIndexEnd
int getObjectIndexEnd() const
Return one past the maximum frame object index.
Definition: MachineFrameInfo.h:409
getFPReg
static Register getFPReg(const RISCVSubtarget &STI)
Definition: RISCVFrameLowering.cpp:301
llvm::RISCVABI::getBPReg
MCRegister getBPReg()
Definition: RISCVBaseInfo.cpp:88
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1618
llvm::MachineFrameInfo::getMaxCallFrameSize
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
Definition: MachineFrameInfo.h:646
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:159
llvm::RISCVFrameLowering::emitPrologue
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
Definition: RISCVFrameLowering.cpp:345
llvm::MCCFIInstruction::cfiDefCfaOffset
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:540
MachineRegisterInfo.h
llvm::MachineInstr::FrameDestroy
@ FrameDestroy
Definition: MachineInstr.h:86
llvm::RegScavenger::isRegUsed
bool isRegUsed(Register Reg, bool includeReserved=true) const
Return if a specific register is currently used.
Definition: RegisterScavenging.cpp:260
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1295
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:650
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::TargetFrameLowering::getOffsetOfLocalArea
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
Definition: TargetFrameLowering.h:140
llvm::MutableArrayRef
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:306
llvm::RISCVFrameLowering::STI
const RISCVSubtarget & STI
Definition: RISCVFrameLowering.h:72
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:738
llvm::TargetFrameLowering::getStackAlign
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:100
llvm::Log2
unsigned Log2(Align A)
Returns the log2 of the alignment.
Definition: Alignment.h:207
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::RISCVFrameLowering::canUseAsPrologue
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a prologue for the target.
Definition: RISCVFrameLowering.cpp:1132
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
llvm::MachineInstr::FrameSetup
@ FrameSetup
Definition: MachineInstr.h:84
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::MachineFrameInfo::getStackID
uint8_t getStackID(int ObjectIdx) const
Definition: MachineFrameInfo.h:723
llvm::RISCVABI::getSCSPReg
MCRegister getSCSPReg()
Definition: RISCVBaseInfo.cpp:91
llvm::MachineFrameInfo::getStackSize
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
Definition: MachineFrameInfo.h:577
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:518
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::RISCVFrameLowering::getFirstSPAdjustAmount
uint64_t getFirstSPAdjustAmount(const MachineFunction &MF) const
Definition: RISCVFrameLowering.cpp:1024
llvm::BitVector
Definition: BitVector.h:75
llvm::RISCVSubtarget::getInstrInfo
const RISCVInstrInfo * getInstrInfo() const override
Definition: RISCVSubtarget.h:127
llvm::StackOffset::getScalable
ScalarTy getScalable() const
Definition: TypeSize.h:150
llvm::MachineFrameInfo::isFixedObjectIndex
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Definition: MachineFrameInfo.h:680
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:184
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MachineFrameInfo::isDeadObjectIndex
bool isDeadObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a dead object.
Definition: MachineFrameInfo.h:737
llvm::TargetOptions::DisableFramePointerElim
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
Definition: TargetOptionsImpl.cpp:23
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:640
llvm::MachineInstrBuilder::setMIFlag
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
Definition: MachineInstrBuilder.h:278
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:625
llvm::TargetFrameLowering::alignSPAdjust
int alignSPAdjust(int SPAdj) const
alignSPAdjust - This method aligns the stack adjustment to the correct alignment.
Definition: TargetFrameLowering.h:105
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:409
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:469
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:238
llvm::HexagonInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index.
Definition: HexagonInstrInfo.cpp:954
llvm::TargetRegisterInfo::getFrameRegister
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
llvm::MachineRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
Definition: MachineRegisterInfo.cpp:617
emitSCSPrologue
static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL)
Definition: RISCVFrameLowering.cpp:28
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::MachineFrameInfo::setObjectOffset
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
Definition: MachineFrameInfo.h:552
llvm::TargetStackID::ScalableVector
@ ScalableVector
Definition: TargetFrameLowering.h:30
llvm::RISCVMachineFunctionInfo
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
Definition: RISCVMachineFunctionInfo.h:47
llvm::MachineBasicBlock::getLastNonDebugInstr
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
Definition: MachineBasicBlock.cpp:263
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
llvm::MachineInstr::NoFlags
@ NoFlags
Definition: MachineInstr.h:83
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:118
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineBasicBlock::size
unsigned size() const
Definition: MachineBasicBlock.h:248
llvm::RISCVFrameLowering::eliminateCallFramePseudoInstr
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
Definition: RISCVFrameLowering.cpp:985
llvm::MachineBasicBlock::succ_begin
succ_iterator succ_begin()
Definition: MachineBasicBlock.h:341
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:656
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:234
llvm::RegScavenger::addScavengingFrameIndex
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
Definition: RegisterScavenging.h:143
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:526
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineInstr::MIFlag
MIFlag
Definition: MachineInstr.h:82
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1588
llvm::MachineBasicBlock::succ_empty
bool succ_empty() const
Definition: MachineBasicBlock.h:356
llvm::MachineFrameInfo::getCalleeSavedInfo
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
Definition: MachineFrameInfo.h:779
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:238
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::RISCVInstrInfo
Definition: RISCVInstrInfo.h:44
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1614
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Definition: MachineFrameInfo.cpp:51
llvm::HexagonInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index.
Definition: HexagonInstrInfo.cpp:999
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::RISCVSubtarget::getRegisterInfo
const RISCVRegisterInfo * getRegisterInfo() const override
Definition: RISCVSubtarget.h:128
llvm::TargetStackID::NoAlloc
@ NoAlloc
Definition: TargetFrameLowering.h:32
hasRVVFrameObject
static bool hasRVVFrameObject(const MachineFunction &MF)
Definition: RISCVFrameLowering.cpp:956
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::RISCVFrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Definition: RISCVFrameLowering.cpp:227
emitSCSEpilogue
static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL)
Definition: RISCVFrameLowering.cpp:79
llvm::RISCVFrameLowering::processFunctionBeforeFrameFinalized
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
Definition: RISCVFrameLowering.cpp:896
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MachineFrameInfo::getMaxAlign
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Definition: MachineFrameInfo.h:593
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:376
llvm::MachineFrameInfo::isFrameAddressTaken
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
Definition: MachineFrameInfo.h:370
llvm::RegScavenger::enterBasicBlock
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
Definition: RegisterScavenging.cpp:82
llvm::MachineFrameInfo::hasCalls
bool hasCalls() const
Return true if the current function has any function calls.
Definition: MachineFrameInfo.h:605
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::LLVMContext::diagnose
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
Definition: LLVMContext.cpp:243
llvm::RISCVFrameLowering::emitEpilogue
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
Definition: RISCVFrameLowering.cpp:546
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:606
llvm::CalleeSavedInfo
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
Definition: MachineFrameInfo.h:33
uint16_t
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:636
MachineFrameInfo.h
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::RISCVFrameLowering::restoreCalleeSavedRegisters
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
Definition: RISCVFrameLowering.cpp:1087
DiagnosticInfo.h
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::RISCVSubtarget::getXLen
unsigned getXLen() const
Definition: RISCVSubtarget.h:186
llvm::TargetStackID::Default
@ Default
Definition: TargetFrameLowering.h:28
llvm::TargetStackID::SGPRSpill
@ SGPRSpill
Definition: TargetFrameLowering.h:29
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
llvm::MachineBasicBlock::getFallThrough
MachineBasicBlock * getFallThrough()
Return the fallthrough block if the block can implicitly transfer control to the block after it by fa...
Definition: MachineBasicBlock.cpp:918
RISCVSubtarget.h
llvm::TargetRegisterInfo::hasStackRealignment
bool hasStackRealignment(const MachineFunction &MF) const
True if stack realignment is required and still possible.
Definition: TargetRegisterInfo.h:947
llvm::MachineFunction::addFrameInst
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
Definition: MachineFunction.cpp:312
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
getLibCallID
static int getLibCallID(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
Definition: RISCVFrameLowering.cpp:133
llvm::RISCVFrameLowering::getStackIDForScalableVectors
TargetStackID::Value getStackIDForScalableVectors() const override
Returns the StackID that scalable vectors should be associated with.
Definition: RISCVFrameLowering.cpp:1191
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:277
MachineInstrBuilder.h
getSPReg
static Register getSPReg(const RISCVSubtarget &STI)
Definition: RISCVFrameLowering.cpp:304
RISCVFrameLowering.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
RISCVMachineFunctionInfo.h
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::RISCVFrameLowering::canUseAsEpilogue
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
Definition: RISCVFrameLowering.cpp:1149
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:249
llvm::MCCFIInstruction::createOffset
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:564
hasRVVSpillWithFIs
static bool hasRVVSpillWithFIs(MachineFunction &MF, const RISCVInstrInfo &TII)
Definition: RISCVFrameLowering.cpp:886
llvm::TargetFrameLowering::determineCalleeSaves
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Definition: TargetFrameLoweringImpl.cpp:83
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineFrameInfo::adjustsStack
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
Definition: MachineFrameInfo.h:601
llvm::RISCVFrameLowering::isSupportedStackID
bool isSupportedStackID(TargetStackID::Value ID) const override
Definition: RISCVFrameLowering.cpp:1178
llvm::TargetRegisterInfo::getMinimalPhysRegClass
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:212
RegisterScavenging.h
llvm::RISCVFrameLowering::hasBP
bool hasBP(const MachineFunction &MF) const
Definition: RISCVFrameLowering.cpp:236
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
llvm::RISCVFrameLowering::determineCalleeSaves
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Definition: RISCVFrameLowering.cpp:810
MachineFunction.h
llvm::MachineInstrBundleIterator
MachineBasicBlock iterator that automatically skips over MIs that are inside bundles (i....
Definition: MachineInstrBundleIterator.h:108
llvm::RISCVSubtarget::hasStdExtF
bool hasStdExtF() const
Definition: RISCVSubtarget.h:147
llvm::RISCVII::MO_CALL
@ MO_CALL
Definition: RISCVBaseInfo.h:194
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:279
getNonLibcallCSI
static SmallVector< CalleeSavedInfo, 8 > getNonLibcallCSI(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
Definition: RISCVFrameLowering.cpp:307
llvm::StackOffset::get
static StackOffset get(ScalarTy Fixed, ScalarTy Scalable)
Definition: TypeSize.h:145