LLVM 17.0.0git
RISCVFrameLowering.cpp
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1//===-- RISCVFrameLowering.cpp - RISC-V Frame Information -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the RISC-V implementation of TargetFrameLowering class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVFrameLowering.h"
15#include "RISCVSubtarget.h"
23#include "llvm/MC/MCDwarf.h"
24#include "llvm/Support/LEB128.h"
25
26#include <algorithm>
27
28using namespace llvm;
29
30// For now we use x18, a.k.a s2, as pointer to shadow call stack.
31// User should explicitly set -ffixed-x18 and not use x18 in their asm.
34 const DebugLoc &DL) {
35 if (!MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack))
36 return;
37
38 const auto &STI = MF.getSubtarget<RISCVSubtarget>();
39 const llvm::RISCVRegisterInfo *TRI = STI.getRegisterInfo();
40 Register RAReg = TRI->getRARegister();
41
42 // Do not save RA to the SCS if it's not saved to the regular stack,
43 // i.e. RA is not at risk of being overwritten.
44 std::vector<CalleeSavedInfo> &CSI = MF.getFrameInfo().getCalleeSavedInfo();
45 if (llvm::none_of(
46 CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
47 return;
48
50
51 auto &Ctx = MF.getFunction().getContext();
52 if (!STI.isRegisterReservedByUser(SCSPReg)) {
54 MF.getFunction(), "x18 not reserved by user for Shadow Call Stack."});
55 return;
56 }
57
58 const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
59 if (RVFI->useSaveRestoreLibCalls(MF)) {
60 Ctx.diagnose(DiagnosticInfoUnsupported{
61 MF.getFunction(),
62 "Shadow Call Stack cannot be combined with Save/Restore LibCalls."});
63 return;
64 }
65
66 const RISCVInstrInfo *TII = STI.getInstrInfo();
67 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
68 int64_t SlotSize = STI.getXLen() / 8;
69 // Store return address to shadow call stack
70 // s[w|d] ra, 0(s2)
71 // addi s2, s2, [4|8]
72 BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW))
73 .addReg(RAReg)
74 .addReg(SCSPReg)
75 .addImm(0)
77 BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI))
78 .addReg(SCSPReg, RegState::Define)
79 .addReg(SCSPReg)
80 .addImm(SlotSize)
82
83 // Emit a CFI instruction that causes SlotSize to be subtracted from the value
84 // of the shadow stack pointer when unwinding past this frame.
85 char DwarfSCSReg = TRI->getDwarfRegNum(SCSPReg, /*IsEH*/ true);
86 assert(DwarfSCSReg < 32 && "SCS Register should be < 32 (X18).");
87
88 char Offset = static_cast<char>(-SlotSize) & 0x7f;
89 const char CFIInst[] = {
90 dwarf::DW_CFA_val_expression,
91 DwarfSCSReg, // register
92 2, // length
93 static_cast<char>(unsigned(dwarf::DW_OP_breg0 + DwarfSCSReg)),
94 Offset, // addend (sleb128)
95 };
96
97 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createEscape(
98 nullptr, StringRef(CFIInst, sizeof(CFIInst))));
99 BuildMI(MBB, MI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
100 .addCFIIndex(CFIIndex)
102}
103
106 const DebugLoc &DL) {
107 if (!MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack))
108 return;
109
110 const auto &STI = MF.getSubtarget<RISCVSubtarget>();
111 Register RAReg = STI.getRegisterInfo()->getRARegister();
112
113 // See emitSCSPrologue() above.
114 std::vector<CalleeSavedInfo> &CSI = MF.getFrameInfo().getCalleeSavedInfo();
115 if (llvm::none_of(
116 CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
117 return;
118
119 Register SCSPReg = RISCVABI::getSCSPReg();
120
121 auto &Ctx = MF.getFunction().getContext();
122 if (!STI.isRegisterReservedByUser(SCSPReg)) {
124 MF.getFunction(), "x18 not reserved by user for Shadow Call Stack."});
125 return;
126 }
127
128 const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
129 if (RVFI->useSaveRestoreLibCalls(MF)) {
130 Ctx.diagnose(DiagnosticInfoUnsupported{
131 MF.getFunction(),
132 "Shadow Call Stack cannot be combined with Save/Restore LibCalls."});
133 return;
134 }
135
136 const RISCVInstrInfo *TII = STI.getInstrInfo();
137 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
138 int64_t SlotSize = STI.getXLen() / 8;
139 // Load return address from shadow call stack
140 // l[w|d] ra, -[4|8](s2)
141 // addi s2, s2, -[4|8]
142 BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::LD : RISCV::LW))
143 .addReg(RAReg, RegState::Define)
144 .addReg(SCSPReg)
145 .addImm(-SlotSize)
147 BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI))
148 .addReg(SCSPReg, RegState::Define)
149 .addReg(SCSPReg)
150 .addImm(-SlotSize)
152 // Restore the SCS pointer
153 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
154 nullptr, STI.getRegisterInfo()->getDwarfRegNum(SCSPReg, /*IsEH*/ true)));
155 BuildMI(MBB, MI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
156 .addCFIIndex(CFIIndex)
158}
159
160// Get the ID of the libcall used for spilling and restoring callee saved
161// registers. The ID is representative of the number of registers saved or
162// restored by the libcall, except it is zero-indexed - ID 0 corresponds to a
163// single register.
164static int getLibCallID(const MachineFunction &MF,
165 const std::vector<CalleeSavedInfo> &CSI) {
166 const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
167
168 if (CSI.empty() || !RVFI->useSaveRestoreLibCalls(MF))
169 return -1;
170
171 Register MaxReg = RISCV::NoRegister;
172 for (auto &CS : CSI)
173 // RISCVRegisterInfo::hasReservedSpillSlot assigns negative frame indexes to
174 // registers which can be saved by libcall.
175 if (CS.getFrameIdx() < 0)
176 MaxReg = std::max(MaxReg.id(), CS.getReg().id());
177
178 if (MaxReg == RISCV::NoRegister)
179 return -1;
180
181 switch (MaxReg) {
182 default:
183 llvm_unreachable("Something has gone wrong!");
184 case /*s11*/ RISCV::X27: return 12;
185 case /*s10*/ RISCV::X26: return 11;
186 case /*s9*/ RISCV::X25: return 10;
187 case /*s8*/ RISCV::X24: return 9;
188 case /*s7*/ RISCV::X23: return 8;
189 case /*s6*/ RISCV::X22: return 7;
190 case /*s5*/ RISCV::X21: return 6;
191 case /*s4*/ RISCV::X20: return 5;
192 case /*s3*/ RISCV::X19: return 4;
193 case /*s2*/ RISCV::X18: return 3;
194 case /*s1*/ RISCV::X9: return 2;
195 case /*s0*/ RISCV::X8: return 1;
196 case /*ra*/ RISCV::X1: return 0;
197 }
198}
199
200// Get the name of the libcall used for spilling callee saved registers.
201// If this function will not use save/restore libcalls, then return a nullptr.
202static const char *
204 const std::vector<CalleeSavedInfo> &CSI) {
205 static const char *const SpillLibCalls[] = {
206 "__riscv_save_0",
207 "__riscv_save_1",
208 "__riscv_save_2",
209 "__riscv_save_3",
210 "__riscv_save_4",
211 "__riscv_save_5",
212 "__riscv_save_6",
213 "__riscv_save_7",
214 "__riscv_save_8",
215 "__riscv_save_9",
216 "__riscv_save_10",
217 "__riscv_save_11",
218 "__riscv_save_12"
219 };
220
221 int LibCallID = getLibCallID(MF, CSI);
222 if (LibCallID == -1)
223 return nullptr;
224 return SpillLibCalls[LibCallID];
225}
226
227// Get the name of the libcall used for restoring callee saved registers.
228// If this function will not use save/restore libcalls, then return a nullptr.
229static const char *
231 const std::vector<CalleeSavedInfo> &CSI) {
232 static const char *const RestoreLibCalls[] = {
233 "__riscv_restore_0",
234 "__riscv_restore_1",
235 "__riscv_restore_2",
236 "__riscv_restore_3",
237 "__riscv_restore_4",
238 "__riscv_restore_5",
239 "__riscv_restore_6",
240 "__riscv_restore_7",
241 "__riscv_restore_8",
242 "__riscv_restore_9",
243 "__riscv_restore_10",
244 "__riscv_restore_11",
245 "__riscv_restore_12"
246 };
247
248 int LibCallID = getLibCallID(MF, CSI);
249 if (LibCallID == -1)
250 return nullptr;
251 return RestoreLibCalls[LibCallID];
252}
253
254// Return true if the specified function should have a dedicated frame
255// pointer register. This is true if frame pointer elimination is
256// disabled, if it needs dynamic stack realignment, if the function has
257// variable sized allocas, or if the frame address is taken.
259 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
260
261 const MachineFrameInfo &MFI = MF.getFrameInfo();
262 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
263 RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() ||
265}
266
268 const MachineFrameInfo &MFI = MF.getFrameInfo();
270
271 // If we do not reserve stack space for outgoing arguments in prologue,
272 // we will adjust the stack pointer before call instruction. After the
273 // adjustment, we can not use SP to access the stack objects for the
274 // arguments. Instead, use BP to access these stack objects.
275 return (MFI.hasVarSizedObjects() ||
277 MFI.getMaxCallFrameSize() != 0))) &&
278 TRI->hasStackRealignment(MF);
279}
280
281// Determines the size of the frame and maximum call frame size.
282void RISCVFrameLowering::determineFrameLayout(MachineFunction &MF) const {
283 MachineFrameInfo &MFI = MF.getFrameInfo();
284 auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
285
286 // Get the number of bytes to allocate from the FrameInfo.
287 uint64_t FrameSize = MFI.getStackSize();
288
289 // Get the alignment.
290 Align StackAlign = getStackAlign();
291
292 // Make sure the frame is aligned.
293 FrameSize = alignTo(FrameSize, StackAlign);
294
295 // Update frame info.
296 MFI.setStackSize(FrameSize);
297
298 // When using SP or BP to access stack objects, we may require extra padding
299 // to ensure the bottom of the RVV stack is correctly aligned within the main
300 // stack. We calculate this as the amount required to align the scalar local
301 // variable section up to the RVV alignment.
303 if (RVFI->getRVVStackSize() && (!hasFP(MF) || TRI->hasStackRealignment(MF))) {
304 int ScalarLocalVarSize = FrameSize - RVFI->getCalleeSavedStackSize() -
305 RVFI->getVarArgsSaveSize();
306 if (auto RVVPadding =
307 offsetToAlignment(ScalarLocalVarSize, RVFI->getRVVStackAlign()))
308 RVFI->setRVVPadding(RVVPadding);
309 }
310}
311
312// Returns the stack size including RVV padding (when required), rounded back
313// up to the required stack alignment.
315 const MachineFunction &MF) const {
316 const MachineFrameInfo &MFI = MF.getFrameInfo();
317 auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
318 return alignTo(MFI.getStackSize() + RVFI->getRVVPadding(), getStackAlign());
319}
320
321// Returns the register used to hold the frame pointer.
322static Register getFPReg(const RISCVSubtarget &STI) { return RISCV::X8; }
323
324// Returns the register used to hold the stack pointer.
325static Register getSPReg(const RISCVSubtarget &STI) { return RISCV::X2; }
326
329 const std::vector<CalleeSavedInfo> &CSI) {
330 const MachineFrameInfo &MFI = MF.getFrameInfo();
332
333 for (auto &CS : CSI) {
334 int FI = CS.getFrameIdx();
335 if (FI >= 0 && MFI.getStackID(FI) == TargetStackID::Default)
336 NonLibcallCSI.push_back(CS);
337 }
338
339 return NonLibcallCSI;
340}
341
342void RISCVFrameLowering::adjustStackForRVV(MachineFunction &MF,
345 const DebugLoc &DL, int64_t Amount,
346 MachineInstr::MIFlag Flag) const {
347 assert(Amount != 0 && "Did not need to adjust stack pointer for RVV.");
348
349 const Register SPReg = getSPReg(STI);
350
351 // Optimize compile time offset case
354 // 1. Multiply the number of v-slots by the (constant) length of register
355 const int64_t VLENB = STI.getRealMinVLen() / 8;
356 assert(Amount % 8 == 0 &&
357 "Reserve the stack by the multiple of one vector size.");
358 const int64_t NumOfVReg = Amount / 8;
359 const int64_t FixedOffset = NumOfVReg * VLENB;
360 if (!isInt<32>(FixedOffset)) {
362 "Frame size outside of the signed 32-bit range not supported");
363 }
364 Offset = StackOffset::getFixed(FixedOffset);
365 }
366
368 // We must keep the stack pointer aligned through any intermediate
369 // updates.
370 RI.adjustReg(MBB, MBBI, DL, SPReg, SPReg, Offset,
371 Flag, getStackAlign());
372}
373
375 Register Reg,
376 uint64_t FixedOffset,
377 uint64_t ScalableOffset) {
378 assert(ScalableOffset != 0 && "Did not need to adjust CFA for RVV");
379 SmallString<64> Expr;
380 std::string CommentBuffer;
381 llvm::raw_string_ostream Comment(CommentBuffer);
382 // Build up the expression (Reg + FixedOffset + ScalableOffset * VLENB).
383 unsigned DwarfReg = TRI.getDwarfRegNum(Reg, true);
384 Expr.push_back((uint8_t)(dwarf::DW_OP_breg0 + DwarfReg));
385 Expr.push_back(0);
386 if (Reg == RISCV::X2)
387 Comment << "sp";
388 else
389 Comment << printReg(Reg, &TRI);
390
391 uint8_t buffer[16];
392 if (FixedOffset) {
393 Expr.push_back(dwarf::DW_OP_consts);
394 Expr.append(buffer, buffer + encodeSLEB128(FixedOffset, buffer));
395 Expr.push_back((uint8_t)dwarf::DW_OP_plus);
396 Comment << " + " << FixedOffset;
397 }
398
399 Expr.push_back((uint8_t)dwarf::DW_OP_consts);
400 Expr.append(buffer, buffer + encodeSLEB128(ScalableOffset, buffer));
401
402 unsigned DwarfVlenb = TRI.getDwarfRegNum(RISCV::VLENB, true);
403 Expr.push_back((uint8_t)dwarf::DW_OP_bregx);
404 Expr.append(buffer, buffer + encodeULEB128(DwarfVlenb, buffer));
405 Expr.push_back(0);
406
407 Expr.push_back((uint8_t)dwarf::DW_OP_mul);
408 Expr.push_back((uint8_t)dwarf::DW_OP_plus);
409
410 Comment << " + " << ScalableOffset << " * vlenb";
411
412 SmallString<64> DefCfaExpr;
413 DefCfaExpr.push_back(dwarf::DW_CFA_def_cfa_expression);
414 DefCfaExpr.append(buffer, buffer + encodeULEB128(Expr.size(), buffer));
415 DefCfaExpr.append(Expr.str());
416
417 return MCCFIInstruction::createEscape(nullptr, DefCfaExpr.str(),
418 Comment.str());
419}
420
422 MachineBasicBlock &MBB) const {
423 MachineFrameInfo &MFI = MF.getFrameInfo();
424 auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
428
429 Register FPReg = getFPReg(STI);
430 Register SPReg = getSPReg(STI);
432
433 // Debug location must be unknown since the first debug location is used
434 // to determine the end of the prologue.
435 DebugLoc DL;
436
437 // All calls are tail calls in GHC calling conv, and functions have no
438 // prologue/epilogue.
440 return;
441
442 // Emit prologue for shadow call stack.
443 emitSCSPrologue(MF, MBB, MBBI, DL);
444
445 // Since spillCalleeSavedRegisters may have inserted a libcall, skip past
446 // any instructions marked as FrameSetup
447 while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup))
448 ++MBBI;
449
450 // Determine the correct frame layout
451 determineFrameLayout(MF);
452
453 // If libcalls are used to spill and restore callee-saved registers, the frame
454 // has two sections; the opaque section managed by the libcalls, and the
455 // section managed by MachineFrameInfo which can also hold callee saved
456 // registers in fixed stack slots, both of which have negative frame indices.
457 // This gets even more complicated when incoming arguments are passed via the
458 // stack, as these too have negative frame indices. An example is detailed
459 // below:
460 //
461 // | incoming arg | <- FI[-3]
462 // | libcallspill |
463 // | calleespill | <- FI[-2]
464 // | calleespill | <- FI[-1]
465 // | this_frame | <- FI[0]
466 //
467 // For negative frame indices, the offset from the frame pointer will differ
468 // depending on which of these groups the frame index applies to.
469 // The following calculates the correct offset knowing the number of callee
470 // saved registers spilt by the two methods.
471 if (int LibCallRegs = getLibCallID(MF, MFI.getCalleeSavedInfo()) + 1) {
472 // Calculate the size of the frame managed by the libcall. The libcalls are
473 // implemented such that the stack will always be 16 byte aligned.
474 unsigned LibCallFrameSize = alignTo((STI.getXLen() / 8) * LibCallRegs, 16);
475 RVFI->setLibCallStackSize(LibCallFrameSize);
476 }
477
478 // FIXME (note copied from Lanai): This appears to be overallocating. Needs
479 // investigation. Get the number of bytes to allocate from the FrameInfo.
480 uint64_t StackSize = getStackSizeWithRVVPadding(MF);
481 uint64_t RealStackSize = StackSize + RVFI->getLibCallStackSize();
482 uint64_t RVVStackSize = RVFI->getRVVStackSize();
483
484 // Early exit if there is no need to allocate on the stack
485 if (RealStackSize == 0 && !MFI.adjustsStack() && RVVStackSize == 0)
486 return;
487
488 // If the stack pointer has been marked as reserved, then produce an error if
489 // the frame requires stack allocation
490 if (STI.isRegisterReservedByUser(SPReg))
492 MF.getFunction(), "Stack pointer required, but has been reserved."});
493
494 uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
495 // Split the SP adjustment to reduce the offsets of callee saved spill.
496 if (FirstSPAdjustAmount) {
497 StackSize = FirstSPAdjustAmount;
498 RealStackSize = FirstSPAdjustAmount;
499 }
500
501 // Allocate space on the stack if necessary.
502 RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackOffset::getFixed(-StackSize),
504
505 // Emit ".cfi_def_cfa_offset RealStackSize"
506 unsigned CFIIndex = MF.addFrameInst(
507 MCCFIInstruction::cfiDefCfaOffset(nullptr, RealStackSize));
508 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
509 .addCFIIndex(CFIIndex)
511
512 const auto &CSI = MFI.getCalleeSavedInfo();
513
514 // The frame pointer is callee-saved, and code has been generated for us to
515 // save it to the stack. We need to skip over the storing of callee-saved
516 // registers as the frame pointer must be modified after it has been saved
517 // to the stack, not before.
518 // FIXME: assumes exactly one instruction is used to save each callee-saved
519 // register.
520 std::advance(MBBI, getNonLibcallCSI(MF, CSI).size());
521
522 // Iterate over list of callee-saved registers and emit .cfi_offset
523 // directives.
524 for (const auto &Entry : CSI) {
525 int FrameIdx = Entry.getFrameIdx();
526 int64_t Offset;
527 // Offsets for objects with fixed locations (IE: those saved by libcall) are
528 // simply calculated from the frame index.
529 if (FrameIdx < 0)
530 Offset = FrameIdx * (int64_t) STI.getXLen() / 8;
531 else
532 Offset = MFI.getObjectOffset(Entry.getFrameIdx()) -
533 RVFI->getLibCallStackSize();
534 Register Reg = Entry.getReg();
535 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
536 nullptr, RI->getDwarfRegNum(Reg, true), Offset));
537 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
538 .addCFIIndex(CFIIndex)
540 }
541
542 // Generate new FP.
543 if (hasFP(MF)) {
544 if (STI.isRegisterReservedByUser(FPReg))
546 MF.getFunction(), "Frame pointer required, but has been reserved."});
547 // The frame pointer does need to be reserved from register allocation.
548 assert(MF.getRegInfo().isReserved(FPReg) && "FP not reserved");
549
550 RI->adjustReg(MBB, MBBI, DL, FPReg, SPReg,
551 StackOffset::getFixed(RealStackSize - RVFI->getVarArgsSaveSize()),
553
554 // Emit ".cfi_def_cfa $fp, RVFI->getVarArgsSaveSize()"
555 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
556 nullptr, RI->getDwarfRegNum(FPReg, true), RVFI->getVarArgsSaveSize()));
557 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
558 .addCFIIndex(CFIIndex)
560 }
561
562 // Emit the second SP adjustment after saving callee saved registers.
563 if (FirstSPAdjustAmount) {
564 uint64_t SecondSPAdjustAmount =
565 getStackSizeWithRVVPadding(MF) - FirstSPAdjustAmount;
566 assert(SecondSPAdjustAmount > 0 &&
567 "SecondSPAdjustAmount should be greater than zero");
568 RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg,
569 StackOffset::getFixed(-SecondSPAdjustAmount),
571
572 // If we are using a frame-pointer, and thus emitted ".cfi_def_cfa fp, 0",
573 // don't emit an sp-based .cfi_def_cfa_offset
574 if (!hasFP(MF)) {
575 // Emit ".cfi_def_cfa_offset StackSize"
576 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(
577 nullptr, getStackSizeWithRVVPadding(MF)));
578 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
579 .addCFIIndex(CFIIndex)
581 }
582 }
583
584 if (RVVStackSize) {
585 adjustStackForRVV(MF, MBB, MBBI, DL, -RVVStackSize,
587 if (!hasFP(MF)) {
588 // Emit .cfi_def_cfa_expression "sp + StackSize + RVVStackSize * vlenb".
589 unsigned CFIIndex = MF.addFrameInst(createDefCFAExpression(
590 *RI, SPReg, getStackSizeWithRVVPadding(MF), RVVStackSize / 8));
591 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
592 .addCFIIndex(CFIIndex)
594 }
595 }
596
597 if (hasFP(MF)) {
598 // Realign Stack
600 if (RI->hasStackRealignment(MF)) {
601 Align MaxAlignment = MFI.getMaxAlign();
602
604 if (isInt<12>(-(int)MaxAlignment.value())) {
605 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg)
606 .addReg(SPReg)
607 .addImm(-(int)MaxAlignment.value())
609 } else {
610 unsigned ShiftAmount = Log2(MaxAlignment);
611 Register VR =
612 MF.getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
613 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SRLI), VR)
614 .addReg(SPReg)
615 .addImm(ShiftAmount)
617 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), SPReg)
618 .addReg(VR)
619 .addImm(ShiftAmount)
621 }
622 // FP will be used to restore the frame in the epilogue, so we need
623 // another base register BP to record SP after re-alignment. SP will
624 // track the current stack after allocating variable sized objects.
625 if (hasBP(MF)) {
626 // move BP, SP
627 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), BPReg)
628 .addReg(SPReg)
629 .addImm(0)
631 }
632 }
633 }
634}
635
637 MachineBasicBlock &MBB) const {
639 MachineFrameInfo &MFI = MF.getFrameInfo();
640 auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
641 Register FPReg = getFPReg(STI);
642 Register SPReg = getSPReg(STI);
643
644 // All calls are tail calls in GHC calling conv, and functions have no
645 // prologue/epilogue.
647 return;
648
649 // Get the insert location for the epilogue. If there were no terminators in
650 // the block, get the last instruction.
652 DebugLoc DL;
653 if (!MBB.empty()) {
655 if (MBBI != MBB.end())
656 DL = MBBI->getDebugLoc();
657
659
660 // If callee-saved registers are saved via libcall, place stack adjustment
661 // before this call.
662 while (MBBI != MBB.begin() &&
663 std::prev(MBBI)->getFlag(MachineInstr::FrameDestroy))
664 --MBBI;
665 }
666
667 const auto &CSI = getNonLibcallCSI(MF, MFI.getCalleeSavedInfo());
668
669 // Skip to before the restores of callee-saved registers
670 // FIXME: assumes exactly one instruction is used to restore each
671 // callee-saved register.
672 auto LastFrameDestroy = MBBI;
673 if (!CSI.empty())
674 LastFrameDestroy = std::prev(MBBI, CSI.size());
675
676 uint64_t StackSize = getStackSizeWithRVVPadding(MF);
677 uint64_t RealStackSize = StackSize + RVFI->getLibCallStackSize();
678 uint64_t FPOffset = RealStackSize - RVFI->getVarArgsSaveSize();
679 uint64_t RVVStackSize = RVFI->getRVVStackSize();
680
681 // Restore the stack pointer using the value of the frame pointer. Only
682 // necessary if the stack pointer was modified, meaning the stack size is
683 // unknown.
684 //
685 // In order to make sure the stack point is right through the EH region,
686 // we also need to restore stack pointer from the frame pointer if we
687 // don't preserve stack space within prologue/epilogue for outgoing variables,
688 // normally it's just checking the variable sized object is present or not
689 // is enough, but we also don't preserve that at prologue/epilogue when
690 // have vector objects in stack.
691 if (RI->hasStackRealignment(MF) || MFI.hasVarSizedObjects() ||
693 assert(hasFP(MF) && "frame pointer should not have been eliminated");
694 RI->adjustReg(MBB, LastFrameDestroy, DL, SPReg, FPReg,
695 StackOffset::getFixed(-FPOffset),
697 } else {
698 if (RVVStackSize)
699 adjustStackForRVV(MF, MBB, LastFrameDestroy, DL, RVVStackSize,
701 }
702
703 uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
704 if (FirstSPAdjustAmount) {
705 uint64_t SecondSPAdjustAmount =
706 getStackSizeWithRVVPadding(MF) - FirstSPAdjustAmount;
707 assert(SecondSPAdjustAmount > 0 &&
708 "SecondSPAdjustAmount should be greater than zero");
709
710 RI->adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg,
711 StackOffset::getFixed(SecondSPAdjustAmount),
713 }
714
715 if (FirstSPAdjustAmount)
716 StackSize = FirstSPAdjustAmount;
717
718 // Deallocate stack
719 RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackOffset::getFixed(StackSize),
721
722 // Emit epilogue for shadow call stack.
723 emitSCSEpilogue(MF, MBB, MBBI, DL);
724}
725
728 Register &FrameReg) const {
729 const MachineFrameInfo &MFI = MF.getFrameInfo();
731 const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
732
733 // Callee-saved registers should be referenced relative to the stack
734 // pointer (positive offset), otherwise use the frame pointer (negative
735 // offset).
736 const auto &CSI = getNonLibcallCSI(MF, MFI.getCalleeSavedInfo());
737 int MinCSFI = 0;
738 int MaxCSFI = -1;
740 auto StackID = MFI.getStackID(FI);
741
742 assert((StackID == TargetStackID::Default ||
743 StackID == TargetStackID::ScalableVector) &&
744 "Unexpected stack ID for the frame object.");
745 if (StackID == TargetStackID::Default) {
746 Offset =
748 MFI.getOffsetAdjustment());
749 } else if (StackID == TargetStackID::ScalableVector) {
751 }
752
753 uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
754
755 if (CSI.size()) {
756 MinCSFI = CSI[0].getFrameIdx();
757 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
758 }
759
760 if (FI >= MinCSFI && FI <= MaxCSFI) {
761 FrameReg = RISCV::X2;
762
763 if (FirstSPAdjustAmount)
764 Offset += StackOffset::getFixed(FirstSPAdjustAmount);
765 else
767 return Offset;
768 }
769
770 if (RI->hasStackRealignment(MF) && !MFI.isFixedObjectIndex(FI)) {
771 // If the stack was realigned, the frame pointer is set in order to allow
772 // SP to be restored, so we need another base register to record the stack
773 // after realignment.
774 // |--------------------------| -- <-- FP
775 // | callee-allocated save | | <----|
776 // | area for register varargs| | |
777 // |--------------------------| | |
778 // | callee-saved registers | | |
779 // |--------------------------| -- |
780 // | realignment (the size of | | |
781 // | this area is not counted | | |
782 // | in MFI.getStackSize()) | | |
783 // |--------------------------| -- |-- MFI.getStackSize()
784 // | RVV alignment padding | | |
785 // | (not counted in | | |
786 // | MFI.getStackSize() but | | |
787 // | counted in | | |
788 // | RVFI.getRVVStackSize()) | | |
789 // |--------------------------| -- |
790 // | RVV objects | | |
791 // | (not counted in | | |
792 // | MFI.getStackSize()) | | |
793 // |--------------------------| -- |
794 // | padding before RVV | | |
795 // | (not counted in | | |
796 // | MFI.getStackSize() or in | | |
797 // | RVFI.getRVVStackSize()) | | |
798 // |--------------------------| -- |
799 // | scalar local variables | | <----'
800 // |--------------------------| -- <-- BP (if var sized objects present)
801 // | VarSize objects | |
802 // |--------------------------| -- <-- SP
803 if (hasBP(MF)) {
804 FrameReg = RISCVABI::getBPReg();
805 } else {
806 // VarSize objects must be empty in this case!
808 FrameReg = RISCV::X2;
809 }
810 } else {
811 FrameReg = RI->getFrameRegister(MF);
812 }
813
814 if (FrameReg == getFPReg(STI)) {
815 Offset += StackOffset::getFixed(RVFI->getVarArgsSaveSize());
816 if (FI >= 0)
817 Offset -= StackOffset::getFixed(RVFI->getLibCallStackSize());
818 // When using FP to access scalable vector objects, we need to minus
819 // the frame size.
820 //
821 // |--------------------------| -- <-- FP
822 // | callee-allocated save | |
823 // | area for register varargs| |
824 // |--------------------------| |
825 // | callee-saved registers | |
826 // |--------------------------| | MFI.getStackSize()
827 // | scalar local variables | |
828 // |--------------------------| -- (Offset of RVV objects is from here.)
829 // | RVV objects |
830 // |--------------------------|
831 // | VarSize objects |
832 // |--------------------------| <-- SP
834 assert(!RI->hasStackRealignment(MF) &&
835 "Can't index across variable sized realign");
836 // We don't expect any extra RVV alignment padding, as the stack size
837 // and RVV object sections should be correct aligned in their own
838 // right.
840 "Inconsistent stack layout");
842 }
843 return Offset;
844 }
845
846 // This case handles indexing off both SP and BP.
847 // If indexing off SP, there must not be any var sized objects
848 assert(FrameReg == RISCVABI::getBPReg() || !MFI.hasVarSizedObjects());
849
850 // When using SP to access frame objects, we need to add RVV stack size.
851 //
852 // |--------------------------| -- <-- FP
853 // | callee-allocated save | | <----|
854 // | area for register varargs| | |
855 // |--------------------------| | |
856 // | callee-saved registers | | |
857 // |--------------------------| -- |
858 // | RVV alignment padding | | |
859 // | (not counted in | | |
860 // | MFI.getStackSize() but | | |
861 // | counted in | | |
862 // | RVFI.getRVVStackSize()) | | |
863 // |--------------------------| -- |
864 // | RVV objects | | |-- MFI.getStackSize()
865 // | (not counted in | | |
866 // | MFI.getStackSize()) | | |
867 // |--------------------------| -- |
868 // | padding before RVV | | |
869 // | (not counted in | | |
870 // | MFI.getStackSize()) | | |
871 // |--------------------------| -- |
872 // | scalar local variables | | <----'
873 // |--------------------------| -- <-- BP (if var sized objects present)
874 // | VarSize objects | |
875 // |--------------------------| -- <-- SP
876 //
877 // The total amount of padding surrounding RVV objects is described by
878 // RVV->getRVVPadding() and it can be zero. It allows us to align the RVV
879 // objects to the required alignment.
880 if (MFI.getStackID(FI) == TargetStackID::Default) {
881 if (MFI.isFixedObjectIndex(FI)) {
882 assert(!RI->hasStackRealignment(MF) &&
883 "Can't index across variable sized realign");
885 RVFI->getLibCallStackSize(),
886 RVFI->getRVVStackSize());
887 } else {
889 }
890 } else if (MFI.getStackID(FI) == TargetStackID::ScalableVector) {
891 // Ensure the base of the RVV stack is correctly aligned: add on the
892 // alignment padding.
893 int ScalarLocalVarSize =
894 MFI.getStackSize() - RVFI->getCalleeSavedStackSize() -
895 RVFI->getVarArgsSaveSize() + RVFI->getRVVPadding();
896 Offset += StackOffset::get(ScalarLocalVarSize, RVFI->getRVVStackSize());
897 }
898 return Offset;
899}
900
902 BitVector &SavedRegs,
903 RegScavenger *RS) const {
905 // Unconditionally spill RA and FP only if the function uses a frame
906 // pointer.
907 if (hasFP(MF)) {
908 SavedRegs.set(RISCV::X1);
909 SavedRegs.set(RISCV::X8);
910 }
911 // Mark BP as used if function has dedicated base pointer.
912 if (hasBP(MF))
913 SavedRegs.set(RISCVABI::getBPReg());
914
915 // If interrupt is enabled and there are calls in the handler,
916 // unconditionally save all Caller-saved registers and
917 // all FP registers, regardless whether they are used.
918 MachineFrameInfo &MFI = MF.getFrameInfo();
919
920 if (MF.getFunction().hasFnAttribute("interrupt") && MFI.hasCalls()) {
921
922 static const MCPhysReg CSRegs[] = { RISCV::X1, /* ra */
923 RISCV::X5, RISCV::X6, RISCV::X7, /* t0-t2 */
924 RISCV::X10, RISCV::X11, /* a0-a1, a2-a7 */
925 RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17,
926 RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, 0 /* t3-t6 */
927 };
928
929 for (unsigned i = 0; CSRegs[i]; ++i)
930 SavedRegs.set(CSRegs[i]);
931
932 if (MF.getSubtarget<RISCVSubtarget>().hasStdExtF()) {
933
934 // If interrupt is enabled, this list contains all FP registers.
935 const MCPhysReg * Regs = MF.getRegInfo().getCalleeSavedRegs();
936
937 for (unsigned i = 0; Regs[i]; ++i)
938 if (RISCV::FPR16RegClass.contains(Regs[i]) ||
939 RISCV::FPR32RegClass.contains(Regs[i]) ||
940 RISCV::FPR64RegClass.contains(Regs[i]))
941 SavedRegs.set(Regs[i]);
942 }
943 }
944}
945
946std::pair<int64_t, Align>
947RISCVFrameLowering::assignRVVStackObjectOffsets(MachineFunction &MF) const {
948 MachineFrameInfo &MFI = MF.getFrameInfo();
949 // Create a buffer of RVV objects to allocate.
950 SmallVector<int, 8> ObjectsToAllocate;
951 for (int I = 0, E = MFI.getObjectIndexEnd(); I != E; ++I) {
952 unsigned StackID = MFI.getStackID(I);
953 if (StackID != TargetStackID::ScalableVector)
954 continue;
955 if (MFI.isDeadObjectIndex(I))
956 continue;
957
958 ObjectsToAllocate.push_back(I);
959 }
960
961 // The minimum alignment is 16 bytes.
962 Align RVVStackAlign(16);
963 const auto &ST = MF.getSubtarget<RISCVSubtarget>();
964
965 if (!ST.hasVInstructions()) {
966 assert(ObjectsToAllocate.empty() &&
967 "Can't allocate scalable-vector objects without V instructions");
968 return std::make_pair(0, RVVStackAlign);
969 }
970
971 // Allocate all RVV locals and spills
972 int64_t Offset = 0;
973 for (int FI : ObjectsToAllocate) {
974 // ObjectSize in bytes.
975 int64_t ObjectSize = MFI.getObjectSize(FI);
976 auto ObjectAlign = std::max(Align(8), MFI.getObjectAlign(FI));
977 // If the data type is the fractional vector type, reserve one vector
978 // register for it.
979 if (ObjectSize < 8)
980 ObjectSize = 8;
981 Offset = alignTo(Offset + ObjectSize, ObjectAlign);
982 MFI.setObjectOffset(FI, -Offset);
983 // Update the maximum alignment of the RVV stack section
984 RVVStackAlign = std::max(RVVStackAlign, ObjectAlign);
985 }
986
987 // Ensure the alignment of the RVV stack. Since we want the most-aligned
988 // object right at the bottom (i.e., any padding at the top of the frame),
989 // readjust all RVV objects down by the alignment padding.
990 uint64_t StackSize = Offset;
991 if (auto AlignmentPadding = offsetToAlignment(StackSize, RVVStackAlign)) {
992 StackSize += AlignmentPadding;
993 for (int FI : ObjectsToAllocate)
994 MFI.setObjectOffset(FI, MFI.getObjectOffset(FI) - AlignmentPadding);
995 }
996
997 return std::make_pair(StackSize, RVVStackAlign);
998}
999
1001 // For RVV spill, scalable stack offsets computing requires up to two scratch
1002 // registers
1003 static constexpr unsigned ScavSlotsNumRVVSpillScalableObject = 2;
1004
1005 // For RVV spill, non-scalable stack offsets computing requires up to one
1006 // scratch register.
1007 static constexpr unsigned ScavSlotsNumRVVSpillNonScalableObject = 1;
1008
1009 // ADDI instruction's destination register can be used for computing
1010 // offsets. So Scalable stack offsets require up to one scratch register.
1011 static constexpr unsigned ScavSlotsADDIScalableObject = 1;
1012
1013 static constexpr unsigned MaxScavSlotsNumKnown =
1014 std::max({ScavSlotsADDIScalableObject, ScavSlotsNumRVVSpillScalableObject,
1015 ScavSlotsNumRVVSpillNonScalableObject});
1016
1017 unsigned MaxScavSlotsNum = 0;
1019 return false;
1020 for (const MachineBasicBlock &MBB : MF)
1021 for (const MachineInstr &MI : MBB) {
1022 bool IsRVVSpill = RISCV::isRVVSpill(MI);
1023 for (auto &MO : MI.operands()) {
1024 if (!MO.isFI())
1025 continue;
1026 bool IsScalableVectorID = MF.getFrameInfo().getStackID(MO.getIndex()) ==
1028 if (IsRVVSpill) {
1029 MaxScavSlotsNum = std::max(
1030 MaxScavSlotsNum, IsScalableVectorID
1031 ? ScavSlotsNumRVVSpillScalableObject
1032 : ScavSlotsNumRVVSpillNonScalableObject);
1033 } else if (MI.getOpcode() == RISCV::ADDI && IsScalableVectorID) {
1034 MaxScavSlotsNum =
1035 std::max(MaxScavSlotsNum, ScavSlotsADDIScalableObject);
1036 }
1037 }
1038 if (MaxScavSlotsNum == MaxScavSlotsNumKnown)
1039 return MaxScavSlotsNumKnown;
1040 }
1041 return MaxScavSlotsNum;
1042}
1043
1044static bool hasRVVFrameObject(const MachineFunction &MF) {
1045 // Originally, the function will scan all the stack objects to check whether
1046 // if there is any scalable vector object on the stack or not. However, it
1047 // causes errors in the register allocator. In issue 53016, it returns false
1048 // before RA because there is no RVV stack objects. After RA, it returns true
1049 // because there are spilling slots for RVV values during RA. It will not
1050 // reserve BP during register allocation and generate BP access in the PEI
1051 // pass due to the inconsistent behavior of the function.
1052 //
1053 // The function is changed to use hasVInstructions() as the return value. It
1054 // is not precise, but it can make the register allocation correct.
1055 //
1056 // FIXME: Find a better way to make the decision or revisit the solution in
1057 // D103622.
1058 //
1059 // Refer to https://github.com/llvm/llvm-project/issues/53016.
1060 return MF.getSubtarget<RISCVSubtarget>().hasVInstructions();
1061}
1062
1064 const RISCVInstrInfo &TII) {
1065 unsigned FnSize = 0;
1066 for (auto &MBB : MF) {
1067 for (auto &MI : MBB) {
1068 // Far branches over 20-bit offset will be relaxed in branch relaxation
1069 // pass. In the worst case, conditional branches will be relaxed into
1070 // the following instruction sequence. Unconditional branches are
1071 // relaxed in the same way, with the exception that there is no first
1072 // branch instruction.
1073 //
1074 // foo
1075 // bne t5, t6, .rev_cond # `TII->getInstSizeInBytes(MI)` bytes
1076 // sd s11, 0(sp) # 4 bytes, or 2 bytes in RVC
1077 // jump .restore, s11 # 8 bytes
1078 // .rev_cond
1079 // bar
1080 // j .dest_bb # 4 bytes, or 2 bytes in RVC
1081 // .restore:
1082 // ld s11, 0(sp) # 4 bytes, or 2 bytes in RVC
1083 // .dest:
1084 // baz
1085 if (MI.isConditionalBranch())
1086 FnSize += TII.getInstSizeInBytes(MI);
1087 if (MI.isConditionalBranch() || MI.isUnconditionalBranch()) {
1088 if (MF.getSubtarget<RISCVSubtarget>().hasStdExtC())
1089 FnSize += 2 + 8 + 2 + 2;
1090 else
1091 FnSize += 4 + 8 + 4 + 4;
1092 continue;
1093 }
1094
1095 FnSize += TII.getInstSizeInBytes(MI);
1096 }
1097 }
1098 return FnSize;
1099}
1100
1102 MachineFunction &MF, RegScavenger *RS) const {
1103 const RISCVRegisterInfo *RegInfo =
1104 MF.getSubtarget<RISCVSubtarget>().getRegisterInfo();
1105 const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
1106 MachineFrameInfo &MFI = MF.getFrameInfo();
1107 const TargetRegisterClass *RC = &RISCV::GPRRegClass;
1108 auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
1109
1110 int64_t RVVStackSize;
1111 Align RVVStackAlign;
1112 std::tie(RVVStackSize, RVVStackAlign) = assignRVVStackObjectOffsets(MF);
1113
1114 RVFI->setRVVStackSize(RVVStackSize);
1115 RVFI->setRVVStackAlign(RVVStackAlign);
1116
1117 if (hasRVVFrameObject(MF)) {
1118 // Ensure the entire stack is aligned to at least the RVV requirement: some
1119 // scalable-vector object alignments are not considered by the
1120 // target-independent code.
1121 MFI.ensureMaxAlignment(RVVStackAlign);
1122 }
1123
1124 unsigned ScavSlotsNum = 0;
1125
1126 // estimateStackSize has been observed to under-estimate the final stack
1127 // size, so give ourselves wiggle-room by checking for stack size
1128 // representable an 11-bit signed field rather than 12-bits.
1129 if (!isInt<11>(MFI.estimateStackSize(MF)))
1130 ScavSlotsNum = 1;
1131
1132 // Far branches over 20-bit offset require a spill slot for scratch register.
1133 bool IsLargeFunction = !isInt<20>(estimateFunctionSizeInBytes(MF, *TII));
1134 if (IsLargeFunction)
1135 ScavSlotsNum = std::max(ScavSlotsNum, 1u);
1136
1137 // RVV loads & stores have no capacity to hold the immediate address offsets
1138 // so we must always reserve an emergency spill slot if the MachineFunction
1139 // contains any RVV spills.
1140 ScavSlotsNum = std::max(ScavSlotsNum, getScavSlotsNumForRVV(MF));
1141
1142 for (unsigned I = 0; I < ScavSlotsNum; I++) {
1143 int FI = MFI.CreateStackObject(RegInfo->getSpillSize(*RC),
1144 RegInfo->getSpillAlign(*RC), false);
1146
1147 if (IsLargeFunction && RVFI->getBranchRelaxationScratchFrameIndex() == -1)
1148 RVFI->setBranchRelaxationScratchFrameIndex(FI);
1149 }
1150
1151 if (MFI.getCalleeSavedInfo().empty() || RVFI->useSaveRestoreLibCalls(MF)) {
1152 RVFI->setCalleeSavedStackSize(0);
1153 return;
1154 }
1155
1156 unsigned Size = 0;
1157 for (const auto &Info : MFI.getCalleeSavedInfo()) {
1158 int FrameIdx = Info.getFrameIdx();
1159 if (MFI.getStackID(FrameIdx) != TargetStackID::Default)
1160 continue;
1161
1162 Size += MFI.getObjectSize(FrameIdx);
1163 }
1164 RVFI->setCalleeSavedStackSize(Size);
1165}
1166
1167// Not preserve stack space within prologue for outgoing variables when the
1168// function contains variable size objects or there are vector objects accessed
1169// by the frame pointer.
1170// Let eliminateCallFramePseudoInstr preserve stack space for it.
1172 return !MF.getFrameInfo().hasVarSizedObjects() &&
1173 !(hasFP(MF) && hasRVVFrameObject(MF));
1174}
1175
1176// Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions.
1180 Register SPReg = RISCV::X2;
1181 DebugLoc DL = MI->getDebugLoc();
1182
1183 if (!hasReservedCallFrame(MF)) {
1184 // If space has not been reserved for a call frame, ADJCALLSTACKDOWN and
1185 // ADJCALLSTACKUP must be converted to instructions manipulating the stack
1186 // pointer. This is necessary when there is a variable length stack
1187 // allocation (e.g. alloca), which means it's not possible to allocate
1188 // space for outgoing arguments from within the function prologue.
1189 int64_t Amount = MI->getOperand(0).getImm();
1190
1191 if (Amount != 0) {
1192 // Ensure the stack remains aligned after adjustment.
1193 Amount = alignSPAdjust(Amount);
1194
1195 if (MI->getOpcode() == RISCV::ADJCALLSTACKDOWN)
1196 Amount = -Amount;
1197
1198 const RISCVRegisterInfo &RI = *STI.getRegisterInfo();
1199 RI.adjustReg(MBB, MI, DL, SPReg, SPReg, StackOffset::getFixed(Amount),
1201 }
1202 }
1203
1204 return MBB.erase(MI);
1205}
1206
1207// We would like to split the SP adjustment to reduce prologue/epilogue
1208// as following instructions. In this way, the offset of the callee saved
1209// register could fit in a single store.
1210// add sp,sp,-2032
1211// sw ra,2028(sp)
1212// sw s0,2024(sp)
1213// sw s1,2020(sp)
1214// sw s3,2012(sp)
1215// sw s4,2008(sp)
1216// add sp,sp,-64
1219 const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
1220 const MachineFrameInfo &MFI = MF.getFrameInfo();
1221 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
1222 uint64_t StackSize = getStackSizeWithRVVPadding(MF);
1223
1224 // Disable SplitSPAdjust if save-restore libcall is used. The callee-saved
1225 // registers will be pushed by the save-restore libcalls, so we don't have to
1226 // split the SP adjustment in this case.
1227 if (RVFI->getLibCallStackSize())
1228 return 0;
1229
1230 // Return the FirstSPAdjustAmount if the StackSize can not fit in a signed
1231 // 12-bit and there exists a callee-saved register needing to be pushed.
1232 if (!isInt<12>(StackSize) && (CSI.size() > 0)) {
1233 // FirstSPAdjustAmount is chosen as (2048 - StackAlign) because 2048 will
1234 // cause sp = sp + 2048 in the epilogue to be split into multiple
1235 // instructions. Offsets smaller than 2048 can fit in a single load/store
1236 // instruction, and we have to stick with the stack alignment. 2048 has
1237 // 16-byte alignment. The stack alignment for RV32 and RV64 is 16 and for
1238 // RV32E it is 4. So (2048 - StackAlign) will satisfy the stack alignment.
1239 return 2048 - getStackAlign().value();
1240 }
1241 return 0;
1242}
1243
1247 if (CSI.empty())
1248 return true;
1249
1251 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
1252 DebugLoc DL;
1253 if (MI != MBB.end() && !MI->isDebugInstr())
1254 DL = MI->getDebugLoc();
1255
1256 const char *SpillLibCall = getSpillLibCallName(*MF, CSI);
1257 if (SpillLibCall) {
1258 // Add spill libcall via non-callee-saved register t0.
1259 BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoCALLReg), RISCV::X5)
1260 .addExternalSymbol(SpillLibCall, RISCVII::MO_CALL)
1262
1263 // Add registers spilled in libcall as liveins.
1264 for (auto &CS : CSI)
1265 MBB.addLiveIn(CS.getReg());
1266 }
1267
1268 // Manually spill values not spilled by libcall.
1269 const auto &NonLibcallCSI = getNonLibcallCSI(*MF, CSI);
1270 for (auto &CS : NonLibcallCSI) {
1271 // Insert the spill to the stack frame.
1272 Register Reg = CS.getReg();
1273 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1274 TII.storeRegToStackSlot(MBB, MI, Reg, !MBB.isLiveIn(Reg), CS.getFrameIdx(),
1275 RC, TRI, Register());
1276 }
1277
1278 return true;
1279}
1280
1284 if (CSI.empty())
1285 return true;
1286
1288 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
1289 DebugLoc DL;
1290 if (MI != MBB.end() && !MI->isDebugInstr())
1291 DL = MI->getDebugLoc();
1292
1293 // Manually restore values not restored by libcall.
1294 // Keep the same order as in the prologue. There is no need to reverse the
1295 // order in the epilogue. In addition, the return address will be restored
1296 // first in the epilogue. It increases the opportunity to avoid the
1297 // load-to-use data hazard between loading RA and return by RA.
1298 // loadRegFromStackSlot can insert multiple instructions.
1299 const auto &NonLibcallCSI = getNonLibcallCSI(*MF, CSI);
1300 for (auto &CS : NonLibcallCSI) {
1301 Register Reg = CS.getReg();
1302 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1303 TII.loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI,
1304 Register());
1305 assert(MI != MBB.begin() && "loadRegFromStackSlot didn't insert any code!");
1306 }
1307
1308 const char *RestoreLibCall = getRestoreLibCallName(*MF, CSI);
1309 if (RestoreLibCall) {
1310 // Add restore libcall via tail call.
1312 BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoTAIL))
1313 .addExternalSymbol(RestoreLibCall, RISCVII::MO_CALL)
1315
1316 // Remove trailing returns, since the terminator is now a tail call to the
1317 // restore function.
1318 if (MI != MBB.end() && MI->getOpcode() == RISCV::PseudoRET) {
1319 NewMI->copyImplicitOps(*MF, *MI);
1320 MI->eraseFromParent();
1321 }
1322 }
1323
1324 return true;
1325}
1326
1328 // Keep the conventional code flow when not optimizing.
1329 if (MF.getFunction().hasOptNone())
1330 return false;
1331
1332 return true;
1333}
1334
1336 MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
1337 const MachineFunction *MF = MBB.getParent();
1338 const auto *RVFI = MF->getInfo<RISCVMachineFunctionInfo>();
1339
1340 if (!RVFI->useSaveRestoreLibCalls(*MF))
1341 return true;
1342
1343 // Inserting a call to a __riscv_save libcall requires the use of the register
1344 // t0 (X5) to hold the return address. Therefore if this register is already
1345 // used we can't insert the call.
1346
1347 RegScavenger RS;
1348 RS.enterBasicBlock(*TmpMBB);
1349 return !RS.isRegUsed(RISCV::X5);
1350}
1351
1353 const MachineFunction *MF = MBB.getParent();
1354 MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
1355 const auto *RVFI = MF->getInfo<RISCVMachineFunctionInfo>();
1356
1357 if (!RVFI->useSaveRestoreLibCalls(*MF))
1358 return true;
1359
1360 // Using the __riscv_restore libcalls to restore CSRs requires a tail call.
1361 // This means if we still need to continue executing code within this function
1362 // the restore cannot take place in this basic block.
1363
1364 if (MBB.succ_size() > 1)
1365 return false;
1366
1367 MachineBasicBlock *SuccMBB =
1368 MBB.succ_empty() ? TmpMBB->getFallThrough() : *MBB.succ_begin();
1369
1370 // Doing a tail call should be safe if there are no successors, because either
1371 // we have a returning block or the end of the block is unreachable, so the
1372 // restore will be eliminated regardless.
1373 if (!SuccMBB)
1374 return true;
1375
1376 // The successor can only contain a return, since we would effectively be
1377 // replacing the successor with our own tail return at the end of our block.
1378 return SuccMBB->isReturnBlock() && SuccMBB->size() == 1;
1379}
1380
1382 switch (ID) {
1385 return true;
1389 return false;
1390 }
1391 llvm_unreachable("Invalid TargetStackID::Value");
1392}
1393
1396}
static MCCFIInstruction createDefCFAExpression(const TargetRegisterInfo &TRI, unsigned Reg, const StackOffset &Offset)
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
static Register getFPReg(const CSKYSubtarget &STI)
This file contains constants used for implementing Dwarf debug support.
uint64_t Size
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
static uint64_t estimateFunctionSizeInBytes(const LoongArchInstrInfo *TII, const MachineFunction &MF)
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
static const char * getRestoreLibCallName(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
static const char * getSpillLibCallName(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
static bool hasRVVFrameObject(const MachineFunction &MF)
static int getLibCallID(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
static Register getSPReg(const RISCVSubtarget &STI)
static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL)
static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL)
static SmallVector< CalleeSavedInfo, 8 > getNonLibcallCSI(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
static unsigned getScavSlotsNumForRVV(MachineFunction &MF)
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:467
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:158
BitVector & set()
Definition: BitVector.h:351
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
Register getReg() const
A debug info location.
Definition: DebugLoc.h:33
Diagnostic information for unsupported feature in backend.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:237
bool hasOptNone() const
Do not optimize this function (-O0).
Definition: Function.h:643
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:319
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:644
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Store the specified register of the given register class to the specified stack frame index.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Load the specified register of the given register class from the specified stack frame index.
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:547
static MCCFIInstruction createRestore(MCSymbol *L, unsigned Register)
.cfi_restore says that the rule for Register is now the same as it was at the beginning of the functi...
Definition: MCDwarf.h:604
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:533
static MCCFIInstruction createEscape(MCSymbol *L, StringRef Vals, StringRef Comment="")
.cfi_escape Allows the user to add arbitrary bytes to the unwind info.
Definition: MCDwarf.h:632
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:571
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
MachineBasicBlock * getFallThrough(bool JumpToFallThrough=false)
Return the fallthrough block if the block can implicitly transfer control to the block after it by fa...
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
unsigned succ_size() const
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
void ensureMaxAlignment(Align Alignment)
Make sure the function is at least Align bytes aligned.
bool hasCalls() const
Return true if the current function has any function calls.
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
uint64_t estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
int getOffsetAdjustment() const
Return the correction for frame offsets.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool isMaxCallFrameSizeComputed() const
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
int getObjectIndexEnd() const
Return one past the maximum frame object index.
uint8_t getStackID(int ObjectIdx) const
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
void setStackSize(uint64_t Size)
Set the size of the stack.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
bool isDeadObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a dead object.
unsigned addFrameInst(const MCCFIInstruction &Inst)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
Representation of each machine instruction.
Definition: MachineInstr.h:68
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:305
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
uint64_t getFirstSPAdjustAmount(const MachineFunction &MF) const
bool enableShrinkWrapping(const MachineFunction &MF) const override
Returns true if the target will correctly handle shrink wrapping.
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
bool hasBP(const MachineFunction &MF) const
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
const RISCVSubtarget & STI
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
bool isSupportedStackID(TargetStackID::Value ID) const override
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
TargetStackID::Value getStackIDForScalableVectors() const override
Returns the StackID that scalable vectors should be associated with.
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a prologue for the target.
uint64_t getStackSizeWithRVVPadding(const MachineFunction &MF) const
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
unsigned getRealMinVLen() const
unsigned getXLen() const
bool isRegisterReservedByUser(Register i) const
bool hasVInstructions() const
unsigned getRealMaxVLen() const
const RISCVRegisterInfo * getRegisterInfo() const override
const RISCVInstrInfo * getInstrInfo() const override
bool isRegUsed(Register Reg, bool includeReserved=true) const
Return if a specific register is currently used.
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
unsigned id() const
Definition: Register.h:111
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
void append(StringRef RHS)
Append from a StringRef.
Definition: SmallString.h:68
StringRef str() const
Explicit conversion to StringRef.
Definition: SmallString.h:261
bool empty() const
Definition: SmallVector.h:94
size_t size() const
Definition: SmallVector.h:91
void push_back(const T &Elt)
Definition: SmallVector.h:416
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
StackOffset holds a fixed and a scalable offset in bytes.
Definition: TypeSize.h:36
int64_t getFixed() const
Returns the fixed component of the stack.
Definition: TypeSize.h:52
int64_t getScalable() const
Returns the scalable component of the stack.
Definition: TypeSize.h:55
static StackOffset get(int64_t Fixed, int64_t Scalable)
Definition: TypeSize.h:47
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
int alignSPAdjust(int SPAdj) const
alignSPAdjust - This method aligns the stack adjustment to the correct alignment.
TargetInstrInfo - Interface to description of machine instruction set.
TargetOptions Options
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool hasStackRealignment(const MachineFunction &MF) const
True if stack realignment is required and still possible.
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:642
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ GHC
Used by the Glasgow Haskell Compiler (GHC).
Definition: CallingConv.h:50
MCRegister getBPReg()
MCRegister getSCSPReg()
bool isRVVSpill(const MachineInstr &MI)
@ Define
Register definition.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1777
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1833
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
uint64_t offsetToAlignment(uint64_t Value, Align Alignment)
Returns the offset to the next integer (mod 2**64) that is greater than or equal to Value and is a mu...
Definition: Alignment.h:197
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:155
unsigned encodeSLEB128(int64_t Value, raw_ostream &OS, unsigned PadTo=0)
Utility function to encode a SLEB128 value to an output stream.
Definition: LEB128.h:23
unsigned encodeULEB128(uint64_t Value, raw_ostream &OS, unsigned PadTo=0)
Utility function to encode a ULEB128 value to an output stream.
Definition: LEB128.h:80
unsigned Log2(Align A)
Returns the log2 of the alignment.
Definition: Alignment.h:208
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
void adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg, Register SrcReg, StackOffset Offset, MachineInstr::MIFlag Flag, MaybeAlign RequiredAlign) const