33class CFISaveRegisterEmitter {
39 : MF{MF}, MFI{MF.getFrameInfo()} {};
48 nullptr, RI.getDwarfRegNum(Reg,
true),
Offset));
55class CFIRestoreRegisterEmitter {
75template <
typename Emitter>
76void RISCVFrameLowering::emitCFIForCSI(
85 for (
const auto &CS : CSI)
117 { RISCV::X9, -3}, { RISCV::X18, -4},
118 { RISCV::X19, -5}, { RISCV::X20, -6},
119 { RISCV::X21, -7}, { RISCV::X22, -8},
120 { RISCV::X23, -9}, { RISCV::X24, -10},
121 { RISCV::X25, -11}, { RISCV::X26, -12},
131 STI.hasStdExtZicfiss();
132 bool HasSWShadowStack =
134 if (!HasHWShadowStack && !HasSWShadowStack)
148 if (HasHWShadowStack) {
155 bool IsRV64 = STI.is64Bit();
156 int64_t SlotSize = STI.getXLen() / 8;
173 char DwarfSCSReg =
TRI->getDwarfRegNum(SCSPReg,
true);
174 assert(DwarfSCSReg < 32 &&
"SCS Register should be < 32 (X3).");
176 char Offset =
static_cast<char>(-SlotSize) & 0x7f;
177 const char CFIInst[] = {
178 dwarf::DW_CFA_val_expression,
181 static_cast<char>(
unsigned(dwarf::DW_OP_breg0 + DwarfSCSReg)),
186 nullptr,
StringRef(CFIInst,
sizeof(CFIInst))));
197 STI.hasStdExtZicfiss();
198 bool HasSWShadowStack =
200 if (!HasHWShadowStack && !HasSWShadowStack)
212 if (HasHWShadowStack) {
219 bool IsRV64 = STI.is64Bit();
220 int64_t SlotSize = STI.getXLen() / 8;
236 nullptr, STI.getRegisterInfo()->getDwarfRegNum(SCSPReg,
true)));
247 const std::vector<CalleeSavedInfo> &CSI) {
250 if (CSI.empty() || !RVFI->useSaveRestoreLibCalls(MF))
253 Register MaxReg = RISCV::NoRegister;
258 MaxReg = std::max(MaxReg.
id(), CS.
getReg().
id());
260 if (MaxReg == RISCV::NoRegister)
267 case RISCV::X27:
return 12;
268 case RISCV::X26:
return 11;
269 case RISCV::X25:
return 10;
270 case RISCV::X24:
return 9;
271 case RISCV::X23:
return 8;
272 case RISCV::X22:
return 7;
273 case RISCV::X21:
return 6;
274 case RISCV::X20:
return 5;
275 case RISCV::X19:
return 4;
276 case RISCV::X18:
return 3;
277 case RISCV::X9:
return 2;
278 case FPReg:
return 1;
279 case RAReg:
return 0;
288 const std::vector<CalleeSavedInfo> &CSI) {
289 static const char *
const SpillLibCalls[] = {
308 return SpillLibCalls[LibCallID];
315 const std::vector<CalleeSavedInfo> &CSI) {
316 static const char *
const RestoreLibCalls[] = {
327 "__riscv_restore_10",
328 "__riscv_restore_11",
335 return RestoreLibCalls[LibCallID];
340static std::pair<unsigned, unsigned>
374 const std::vector<CalleeSavedInfo> &CSI) {
375 Register MaxPushPopReg = RISCV::NoRegister;
376 for (
auto &CS : CSI) {
380 MaxPushPopReg = std::max(MaxPushPopReg.
id(), CS.
getReg().
id());
382 assert(MaxPushPopReg != RISCV::X26 &&
"x26 requires x27 to also be pushed");
383 return MaxPushPopReg;
410 TRI->hasStackRealignment(MF);
414void RISCVFrameLowering::determineFrameLayout(
MachineFunction &MF)
const {
425 FrameSize =
alignTo(FrameSize, StackAlign);
435 if (RVFI->getRVVStackSize() && (!
hasFP(MF) ||
TRI->hasStackRealignment(MF))) {
436 int ScalarLocalVarSize = FrameSize - RVFI->getCalleeSavedStackSize() -
437 RVFI->getVarArgsSaveSize();
438 if (
auto RVVPadding =
440 RVFI->setRVVPadding(RVVPadding);
455 const std::vector<CalleeSavedInfo> &CSI) {
459 for (
auto &CS : CSI) {
465 return NonLibcallCSI;
470 const std::vector<CalleeSavedInfo> &CSI) {
474 for (
auto &CS : CSI) {
485 const std::vector<CalleeSavedInfo> &CSI) {
489 if (!RVFI->useSaveRestoreLibCalls(MF) && !RVFI->isPushable(MF))
490 return PushOrLibCallsCSI;
492 for (
const auto &CS : CSI) {
496 PushOrLibCallsCSI.push_back(CS);
499 return PushOrLibCallsCSI;
504 int FixedOffset,
int ScalableOffset,
506 unsigned DwarfVLenB =
TRI.getDwarfRegNum(RISCV::VLENB,
true);
512 Comment << (FixedOffset < 0 ?
" - " :
" + ") << std::abs(FixedOffset);
525 Comment << (ScalableOffset < 0 ?
" - " :
" + ") << std::abs(ScalableOffset)
533 assert(ScalableOffset != 0 &&
"Did not need to adjust CFA for RVV");
535 std::string CommentBuffer;
538 unsigned DwarfReg =
TRI.getDwarfRegNum(Reg,
true);
551 DefCfaExpr.
push_back(dwarf::DW_CFA_def_cfa_expression);
562 assert(ScalableOffset != 0 &&
"Did not need to adjust CFA for RVV");
564 std::string CommentBuffer;
574 unsigned DwarfReg =
TRI.getDwarfRegNum(Reg,
true);
575 DefCfaExpr.
push_back(dwarf::DW_CFA_expression);
588 uint64_t RealStackSize,
bool EmitCFI,
596 if (!NeedProbe ||
Offset <= ProbeSize) {
613 if (
Offset < ProbeSize * 5) {
616 while (CurrentOffset + ProbeSize <=
Offset) {
627 CurrentOffset += ProbeSize;
727 auto FirstFrameSetup =
MBBI;
735 determineFrameLayout(MF);
761 unsigned LibCallFrameSize =
763 RVFI->setLibCallStackSize(LibCallFrameSize);
771 emitCFIForCSI<CFISaveRegisterEmitter>(
MBB,
MBBI,
778 uint64_t StackSize = RealStackSize - RVFI->getReservedSpillsSize();
779 uint64_t RVVStackSize = RVFI->getRVVStackSize();
782 if (RealStackSize == 0 && !MFI.
adjustsStack() && RVVStackSize == 0)
789 MF.
getFunction(),
"Stack pointer required, but has been reserved."});
793 if (FirstSPAdjustAmount) {
794 StackSize = FirstSPAdjustAmount;
795 RealStackSize = FirstSPAdjustAmount;
798 if (RVFI->isPushable(MF) && FirstFrameSetup !=
MBB.
end() &&
799 FirstFrameSetup->getOpcode() == RISCV::CM_PUSH) {
806 FirstFrameSetup->getOperand(1).setImm(Spimm);
815 emitCFIForCSI<CFISaveRegisterEmitter>(
MBB,
MBBI,
826 NeedProbe, ProbeSize);
844 MF.
getFunction(),
"Frame pointer required, but has been reserved."});
854 nullptr, RI->getDwarfRegNum(
FPReg,
true), RVFI->getVarArgsSaveSize()));
861 if (FirstSPAdjustAmount) {
864 assert(SecondSPAdjustAmount > 0 &&
865 "SecondSPAdjustAmount should be greater than zero");
895 if (RI->hasStackRealignment(MF)) {
899 if (isInt<12>(-(
int)MaxAlignment.
value())) {
905 unsigned ShiftAmount =
Log2(MaxAlignment);
936 int64_t CFAOffset)
const {
989 uint64_t RealStackSize = FirstSPAdjustAmount ? FirstSPAdjustAmount
991 uint64_t StackSize = FirstSPAdjustAmount ? FirstSPAdjustAmount
993 RVFI->getReservedSpillsSize();
994 uint64_t FPOffset = RealStackSize - RVFI->getVarArgsSaveSize();
995 uint64_t RVVStackSize = RVFI->getRVVStackSize();
997 bool RestoreSPFromFP = RI->hasStackRealignment(MF) ||
1002 if (!RestoreSPFromFP)
1009 nullptr, RI->getDwarfRegNum(
SPReg,
true), RealStackSize));
1011 TII->get(TargetOpcode::CFI_INSTRUCTION))
1016 emitCalleeSavedRVVEpilogCFI(
MBB, LastFrameDestroy);
1019 if (FirstSPAdjustAmount) {
1022 assert(SecondSPAdjustAmount > 0 &&
1023 "SecondSPAdjustAmount should be greater than zero");
1027 if (!RestoreSPFromFP)
1036 TII->get(TargetOpcode::CFI_INSTRUCTION))
1052 if (RestoreSPFromFP) {
1053 assert(
hasFP(MF) &&
"frame pointer should not have been eliminated");
1061 nullptr, RI->getDwarfRegNum(
SPReg,
true), RealStackSize));
1062 BuildMI(
MBB, LastFrameDestroy,
DL,
TII->get(TargetOpcode::CFI_INSTRUCTION))
1072 deallocateStack(MF,
MBB,
MBBI,
DL, StackSize,
1073 RVFI->getLibCallStackSize());
1083 bool ApplyPop = RVFI->isPushable(MF) &&
MBBI !=
MBB.
end() &&
1084 MBBI->getOpcode() == RISCV::CM_POP;
1092 MBBI->getOperand(1).setImm(Spimm);
1096 deallocateStack(MF,
MBB,
MBBI,
DL, StackSize,
1097 RealStackSize - StackSize);
1100 if (NextI ==
MBB.
end() || NextI->getOpcode() != RISCV::PseudoRET) {
1103 emitCFIForCSI<CFIRestoreRegisterEmitter>(
1118 deallocateStack(MF,
MBB,
MBBI,
DL, StackSize, 0);
1142 "Unexpected stack ID for the frame object.");
1154 MinCSFI = CSI[0].getFrameIdx();
1155 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
1158 if (FI >= MinCSFI && FI <= MaxCSFI) {
1161 if (FirstSPAdjustAmount)
1212 if (FrameReg ==
FPReg) {
1231 "Can't index across variable sized realign");
1236 "Inconsistent stack layout");
1279 "Can't index across variable sized realign");
1281 RVFI->getRVVStackSize());
1289 RVFI->getCalleeSavedStackSize() -
1290 RVFI->getVarArgsSaveSize() + RVFI->getRVVPadding();
1312 if (RVFI->isPushable(MF) && SavedRegs.
test(RISCV::X26))
1313 SavedRegs.
set(RISCV::X27);
1316std::pair<int64_t, Align>
1317RISCVFrameLowering::assignRVVStackObjectOffsets(
MachineFunction &MF)
const {
1321 auto pushRVVObjects = [&](
int FIBegin,
int FIEnd) {
1322 for (
int I = FIBegin, E = FIEnd;
I != E; ++
I) {
1335 if (!RVVCSI.empty())
1336 pushRVVObjects(RVVCSI[0].getFrameIdx(),
1337 RVVCSI[RVVCSI.size() - 1].getFrameIdx() + 1);
1341 Align RVVStackAlign(16);
1344 if (!
ST.hasVInstructions()) {
1346 "Can't allocate scalable-vector objects without V instructions");
1347 return std::make_pair(0, RVVStackAlign);
1352 for (
int FI : ObjectsToAllocate) {
1364 RVVStackAlign = std::max(RVVStackAlign, ObjectAlign);
1377 if (
auto RVVStackAlignVScale = RVVStackAlign.value() / VScale) {
1378 if (
auto AlignmentPadding =
1380 StackSize += AlignmentPadding;
1381 for (
int FI : ObjectsToAllocate)
1386 return std::make_pair(StackSize, RVVStackAlign);
1392 static constexpr unsigned ScavSlotsNumRVVSpillScalableObject = 2;
1396 static constexpr unsigned ScavSlotsNumRVVSpillNonScalableObject = 1;
1400 static constexpr unsigned ScavSlotsADDIScalableObject = 1;
1402 static constexpr unsigned MaxScavSlotsNumKnown =
1403 std::max({ScavSlotsADDIScalableObject, ScavSlotsNumRVVSpillScalableObject,
1404 ScavSlotsNumRVVSpillNonScalableObject});
1406 unsigned MaxScavSlotsNum = 0;
1412 for (
auto &MO :
MI.operands()) {
1418 MaxScavSlotsNum = std::max(
1419 MaxScavSlotsNum, IsScalableVectorID
1420 ? ScavSlotsNumRVVSpillScalableObject
1421 : ScavSlotsNumRVVSpillNonScalableObject);
1422 }
else if (
MI.getOpcode() == RISCV::ADDI && IsScalableVectorID) {
1424 std::max(MaxScavSlotsNum, ScavSlotsADDIScalableObject);
1427 if (MaxScavSlotsNum == MaxScavSlotsNumKnown)
1428 return MaxScavSlotsNumKnown;
1430 return MaxScavSlotsNum;
1454 unsigned FnSize = 0;
1455 for (
auto &
MBB : MF) {
1456 for (
auto &
MI :
MBB) {
1474 if (
MI.isConditionalBranch())
1475 FnSize +=
TII.getInstSizeInBytes(
MI);
1476 if (
MI.isConditionalBranch() ||
MI.isUnconditionalBranch()) {
1478 FnSize += 2 + 8 + 2 + 2;
1480 FnSize += 4 + 8 + 4 + 4;
1484 FnSize +=
TII.getInstSizeInBytes(
MI);
1499 int64_t RVVStackSize;
1500 Align RVVStackAlign;
1501 std::tie(RVVStackSize, RVVStackAlign) = assignRVVStackObjectOffsets(MF);
1503 RVFI->setRVVStackSize(RVVStackSize);
1504 RVFI->setRVVStackAlign(RVVStackAlign);
1513 unsigned ScavSlotsNum = 0;
1523 if (IsLargeFunction)
1524 ScavSlotsNum = std::max(ScavSlotsNum, 1u);
1531 for (
unsigned I = 0;
I < ScavSlotsNum;
I++) {
1533 RegInfo->getSpillAlign(*RC),
false);
1536 if (IsLargeFunction && RVFI->getBranchRelaxationScratchFrameIndex() == -1)
1537 RVFI->setBranchRelaxationScratchFrameIndex(FI);
1540 unsigned Size = RVFI->getReservedSpillsSize();
1542 int FrameIdx =
Info.getFrameIdx();
1548 RVFI->setCalleeSavedStackSize(
Size);
1572 int64_t Amount =
MI->getOperand(0).getImm();
1578 if (
MI->getOpcode() == RISCV::ADJCALLSTACKDOWN)
1611 if (RVFI->getReservedSpillsSize())
1616 if (!isInt<12>(StackSize) && (CSI.size() > 0)) {
1646 auto CanCompress = [&](
uint64_t CompressLen) ->
bool {
1647 if (StackSize <= 2047 + CompressLen ||
1648 (StackSize > 2048 * 2 - StackAlign &&
1649 StackSize <= 2047 * 2 + CompressLen) ||
1650 StackSize > 2048 * 3 - StackAlign)
1658 const uint64_t ADDI16SPCompressLen = 496;
1659 if (
STI.
is64Bit() && CanCompress(ADDI16SPCompressLen))
1660 return ADDI16SPCompressLen;
1661 if (CanCompress(RVCompressLen))
1662 return RVCompressLen;
1664 return 2048 - StackAlign;
1671 std::vector<CalleeSavedInfo> &CSI,
unsigned &MinCSFrameIndex,
1672 unsigned &MaxCSFrameIndex)
const {
1679 if (RVFI->isPushable(MF)) {
1682 if (MaxReg != RISCV::NoRegister) {
1684 RVFI->setRVPushRegs(PushedRegNum);
1688 RVFI->setRVPushRlist(RegEnc);
1695 for (
auto &CS : CSI) {
1696 unsigned Reg = CS.
getReg();
1701 if (RVFI->useSaveRestoreLibCalls(MF) || RVFI->isPushable(MF)) {
1706 if (RVFI->isPushable(MF))
1707 Offset = -((FII->second + RVFI->getRVPushRegs() + 1) * (int64_t)
Size);
1725 if ((
unsigned)FrameIdx < MinCSFrameIndex)
1726 MinCSFrameIndex = FrameIdx;
1727 if ((
unsigned)FrameIdx > MaxCSFrameIndex)
1728 MaxCSFrameIndex = FrameIdx;
1735 if (RVFI->isPushable(MF)) {
1736 if (int64_t PushSize = RVFI->getRVPushStackSize())
1738 }
else if (
int LibCallRegs =
getLibCallID(MF, CSI) + 1) {
1739 int64_t LibCallFrameSize =
1757 DL =
MI->getDebugLoc();
1763 if (PushedRegNum > 0) {
1769 PushBuilder.
addImm((int64_t)RegEnc);
1772 for (
unsigned i = 0; i < PushedRegNum; i++)
1782 for (
auto &CS : CSI)
1790 auto storeRegsToStackSlots = [&](
decltype(UnmanagedCSI) CSInfo) {
1791 for (
auto &CS : CSInfo) {
1799 storeRegsToStackSlots(UnmanagedCSI);
1800 storeRegsToStackSlots(RVVCSI);
1806 return RISCV::VRRegClass.contains(BaseReg) ? 1
1807 : RISCV::VRM2RegClass.contains(BaseReg) ? 2
1808 : RISCV::VRM4RegClass.contains(BaseReg) ? 4
1817 if (BaseReg == RISCV::NoRegister)
1822void RISCVFrameLowering::emitCalleeSavedRVVPrologCFI(
1840 FixedSize -= ScalarLocalVarSize;
1843 for (
auto &CS : RVVCSI) {
1848 for (
unsigned i = 0; i < NumRegs; ++i) {
1858void RISCVFrameLowering::emitCalleeSavedRVVEpilogCFI(
1868 for (
auto &CS : RVVCSI) {
1871 for (
unsigned i = 0; i < NumRegs; ++i) {
1873 nullptr, RI->getDwarfRegNum(BaseReg + i,
true)));
1891 DL =
MI->getDebugLoc();
1902 auto loadRegFromStackSlot = [&](
decltype(UnmanagedCSI) CSInfo) {
1903 for (
auto &CS : CSInfo) {
1909 "loadRegFromStackSlot didn't insert any code!");
1912 loadRegFromStackSlot(RVVCSI);
1913 loadRegFromStackSlot(UnmanagedCSI);
1923 PopBuilder.
addImm(RegEnc);
1931 if (RestoreLibCall) {
1940 if (
MI !=
MBB.
end() &&
MI->getOpcode() == RISCV::PseudoRET) {
1941 NewMI->copyImplicitOps(*MF, *
MI);
1942 MI->eraseFromParent();
2027 bool IsRV64 = Subtarget.is64Bit();
2028 Align StackAlign = Subtarget.getFrameLowering()->getStackAlign();
2035 MF.
insert(MBBInsertPoint, LoopTestMBB);
2037 MF.
insert(MBBInsertPoint, ExitMBB);
2043 TII->movImm(
MBB,
MBBI,
DL, ScratchReg, ProbeSize, Flags);
2054 TII->get(IsRV64 ? RISCV::SD : RISCV::SW))
2079 return MI.getOpcode() == RISCV::PROBED_STACKALLOC;
2081 if (Where !=
MBB.
end()) {
2084 Where->eraseFromParent();
static MCCFIInstruction createDefCFAExpression(const TargetRegisterInfo &TRI, unsigned Reg, const StackOffset &Offset)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Analysis containing CSE Info
dxil DXContainer Global Emitter
This file contains constants used for implementing Dwarf debug support.
const HexagonInstrInfo * TII
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
static uint64_t estimateFunctionSizeInBytes(const LoongArchInstrInfo *TII, const MachineFunction &MF)
unsigned const TargetRegisterInfo * TRI
static constexpr Register SPReg
static constexpr Register FPReg
static MCRegister getRVVBaseRegister(const RISCVRegisterInfo &TRI, const Register &Reg)
static const char * getRestoreLibCallName(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
static const char * getSpillLibCallName(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
static void emitStackProbeInline(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL)
static bool hasRVVFrameObject(const MachineFunction &MF)
static std::pair< unsigned, unsigned > getPushPopEncodingAndNum(const Register MaxReg)
static const std::pair< MCPhysReg, int8_t > FixedCSRFIMap[]
static SmallVector< CalleeSavedInfo, 8 > getRVVCalleeSavedInfo(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
static void appendScalableVectorExpression(const TargetRegisterInfo &TRI, SmallVectorImpl< char > &Expr, int FixedOffset, int ScalableOffset, llvm::raw_string_ostream &Comment)
static unsigned getCalleeSavedRVVNumRegs(const Register &BaseReg)
static Align getABIStackAlignment(RISCVABI::ABI ABI)
static SmallVector< CalleeSavedInfo, 8 > getPushOrLibCallsSavedInfo(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
static int getLibCallID(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL)
static constexpr Register RAReg
static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL)
static SmallVector< CalleeSavedInfo, 8 > getUnmanagedCSI(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
static Register getMaxPushPopReg(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
static unsigned getScavSlotsNumForRVV(MachineFunction &MF)
static MCCFIInstruction createDefCFAOffset(const TargetRegisterInfo &TRI, Register Reg, uint64_t FixedOffset, uint64_t ScalableOffset)
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool empty() const
empty - Check if the array is empty.
bool test(unsigned Idx) const
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
Diagnostic information for unsupported feature in backend.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
bool hasOptNone() const
Do not optimize this function (-O0).
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Store the specified register of the given register class to the specified stack frame index.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Load the specified register of the given register class from the specified stack frame index.
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_def_cfa_register modifies a rule for computing CFA.
static MCCFIInstruction createRestore(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_restore says that the rule for Register is now the same as it was at the beginning of the functi...
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int64_t Offset, SMLoc Loc={})
.cfi_def_cfa_offset modifies a rule for computing CFA.
static MCCFIInstruction createEscape(MCSymbol *L, StringRef Vals, SMLoc Loc={}, StringRef Comment="")
.cfi_escape Allows the user to add arbitrary bytes to the unwind info.
Wrapper class representing physical registers. Should be passed by value.
MachineBasicBlock * getFallThrough(bool JumpToFallThrough=true)
Return the fallthrough block if the block can implicitly transfer control to the block after it by fa...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
succ_iterator succ_begin()
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
unsigned succ_size() const
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any debug instructions.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
bool isLiveIn(MCRegister Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
void ensureMaxAlignment(Align Alignment)
Make sure the function is at least Align bytes aligned.
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
uint64_t getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
int64_t getOffsetAdjustment() const
Return the correction for frame offsets.
uint64_t estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
void setStackID(int ObjectIdx, uint8_t ID)
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool isMaxCallFrameSizeComputed() const
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
int getObjectIndexEnd() const
Return one past the maximum frame object index.
int CreateFixedSpillStackObject(uint64_t Size, int64_t SPOffset, bool IsImmutable=false)
Create a spill slot at a fixed location on the stack.
uint8_t getStackID(int ObjectIdx) const
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
void setStackSize(uint64_t Size)
Set the size of the stack.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
bool isDeadObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a dead object.
unsigned addFrameInst(const MCCFIInstruction &Inst)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
void insert(iterator MBBI, MachineBasicBlock *MBB)
const TargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
uint64_t getFirstSPAdjustAmount(const MachineFunction &MF) const
bool enableShrinkWrapping(const MachineFunction &MF) const override
Returns true if the target will correctly handle shrink wrapping.
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
bool hasBP(const MachineFunction &MF) const
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI, unsigned &MinCSFrameIndex, unsigned &MaxCSFrameIndex) const override
assignCalleeSavedSpillSlots - Allows target to override spill slot assignment logic.
bool hasFPImpl(const MachineFunction &MF) const override
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
void allocateStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineFunction &MF, uint64_t Offset, uint64_t RealStackSize, bool EmitCFI, bool NeedProbe, uint64_t ProbeSize) const
const RISCVSubtarget & STI
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
bool isSupportedStackID(TargetStackID::Value ID) const override
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
TargetStackID::Value getStackIDForScalableVectors() const override
Returns the StackID that scalable vectors should be associated with.
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a prologue for the target.
RISCVFrameLowering(const RISCVSubtarget &STI)
uint64_t getStackSizeWithRVVPadding(const MachineFunction &MF) const
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
bool isPushable(const MachineFunction &MF) const
int getRVPushRlist() const
uint64_t getRVVPadding() const
unsigned getRVPushRegs() const
bool useSaveRestoreLibCalls(const MachineFunction &MF) const
unsigned getVarArgsSaveSize() const
unsigned getCalleeSavedStackSize() const
bool hasStdExtCOrZca() const
bool hasVInstructions() const
bool isRegisterReservedByUser(Register i) const override
const RISCVRegisterInfo * getRegisterInfo() const override
const RISCVInstrInfo * getInstrInfo() const override
bool hasInlineStackProbe(const MachineFunction &MF) const override
True if stack clash protection is enabled for this functions.
unsigned getStackProbeSize(const MachineFunction &MF, Align StackAlign) const
bool isRegUsed(Register Reg, bool includeReserved=true) const
Return if a specific register is currently used.
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
Wrapper class representing virtual and physical registers.
constexpr unsigned id() const
Represents a location in source code.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
void append(StringRef RHS)
Append from a StringRef.
StringRef str() const
Explicit conversion to StringRef.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StackOffset holds a fixed and a scalable offset in bytes.
int64_t getFixed() const
Returns the fixed component of the stack.
int64_t getScalable() const
Returns the scalable component of the stack.
static StackOffset get(int64_t Fixed, int64_t Scalable)
StringRef - Represent a constant reference to a string, i.e.
Information about stack frame layout on the target.
bool hasFP(const MachineFunction &MF) const
hasFP - Return true if the specified function should have a dedicated frame pointer register.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
int alignSPAdjust(int SPAdj) const
alignSPAdjust - This method aligns the stack adjustment to the correct alignment.
TargetInstrInfo - Interface to description of machine instruction set.
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
bool hasStackRealignment(const MachineFunction &MF) const
True if stack realignment is required and still possible.
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
self_iterator getIterator()
A raw_ostream that writes to an std::string.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ GHC
Used by the Glasgow Haskell Compiler (GHC).
static constexpr unsigned RVVBitsPerBlock
bool isRVVSpill(const MachineInstr &MI)
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Define
Register definition.
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
IterT next_nodbg(IterT It, IterT End, bool SkipPseudoOp=true)
Increment It, then continue incrementing it while it points to a debug instruction.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
constexpr T alignDown(U Value, V Align, W Skew=0)
Returns the largest unsigned integer less than or equal to Value and is Skew mod Align.
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
uint64_t offsetToAlignment(uint64_t Value, Align Alignment)
Returns the offset to the next integer (mod 2**64) that is greater than or equal to Value and is a mu...
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
unsigned encodeSLEB128(int64_t Value, raw_ostream &OS, unsigned PadTo=0)
Utility function to encode a SLEB128 value to an output stream.
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
unsigned encodeULEB128(uint64_t Value, raw_ostream &OS, unsigned PadTo=0)
Utility function to encode a ULEB128 value to an output stream.
unsigned Log2(Align A)
Returns the log2 of the alignment.
void fullyRecomputeLiveIns(ArrayRef< MachineBasicBlock * > MBBs)
Convenience function for recomputing live-in's for a set of MBBs until the computation converges.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.
static bool isRVVRegClass(const TargetRegisterClass *RC)
void adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg, Register SrcReg, StackOffset Offset, MachineInstr::MIFlag Flag, MaybeAlign RequiredAlign) const