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RISCVFrameLowering.cpp
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1 //===-- RISCVFrameLowering.cpp - RISCV Frame Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of TargetFrameLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVFrameLowering.h"
15 #include "RISCVSubtarget.h"
21 #include "llvm/IR/DiagnosticInfo.h"
22 #include "llvm/MC/MCDwarf.h"
23 
24 #include <algorithm>
25 
26 using namespace llvm;
27 
28 // For now we use x18, a.k.a s2, as pointer to shadow call stack.
29 // User should explicitly set -ffixed-x18 and not use x18 in their asm.
32  const DebugLoc &DL) {
33  if (!MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack))
34  return;
35 
36  const auto &STI = MF.getSubtarget<RISCVSubtarget>();
37  Register RAReg = STI.getRegisterInfo()->getRARegister();
38 
39  // Do not save RA to the SCS if it's not saved to the regular stack,
40  // i.e. RA is not at risk of being overwritten.
41  std::vector<CalleeSavedInfo> &CSI = MF.getFrameInfo().getCalleeSavedInfo();
42  if (llvm::none_of(
43  CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
44  return;
45 
46  Register SCSPReg = RISCVABI::getSCSPReg();
47 
48  auto &Ctx = MF.getFunction().getContext();
49  if (!STI.isRegisterReservedByUser(SCSPReg)) {
51  MF.getFunction(), "x18 not reserved by user for Shadow Call Stack."});
52  return;
53  }
54 
55  const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
56  if (RVFI->useSaveRestoreLibCalls(MF)) {
57  Ctx.diagnose(DiagnosticInfoUnsupported{
58  MF.getFunction(),
59  "Shadow Call Stack cannot be combined with Save/Restore LibCalls."});
60  return;
61  }
62 
63  const RISCVInstrInfo *TII = STI.getInstrInfo();
64  bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
65  int64_t SlotSize = STI.getXLen() / 8;
66  // Store return address to shadow call stack
67  // s[w|d] ra, 0(s2)
68  // addi s2, s2, [4|8]
69  BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW))
70  .addReg(RAReg)
71  .addReg(SCSPReg)
72  .addImm(0)
74  BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI))
75  .addReg(SCSPReg, RegState::Define)
76  .addReg(SCSPReg)
77  .addImm(SlotSize)
79 }
80 
83  const DebugLoc &DL) {
84  if (!MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack))
85  return;
86 
87  const auto &STI = MF.getSubtarget<RISCVSubtarget>();
88  Register RAReg = STI.getRegisterInfo()->getRARegister();
89 
90  // See emitSCSPrologue() above.
91  std::vector<CalleeSavedInfo> &CSI = MF.getFrameInfo().getCalleeSavedInfo();
92  if (llvm::none_of(
93  CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
94  return;
95 
96  Register SCSPReg = RISCVABI::getSCSPReg();
97 
98  auto &Ctx = MF.getFunction().getContext();
99  if (!STI.isRegisterReservedByUser(SCSPReg)) {
101  MF.getFunction(), "x18 not reserved by user for Shadow Call Stack."});
102  return;
103  }
104 
105  const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
106  if (RVFI->useSaveRestoreLibCalls(MF)) {
107  Ctx.diagnose(DiagnosticInfoUnsupported{
108  MF.getFunction(),
109  "Shadow Call Stack cannot be combined with Save/Restore LibCalls."});
110  return;
111  }
112 
113  const RISCVInstrInfo *TII = STI.getInstrInfo();
114  bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
115  int64_t SlotSize = STI.getXLen() / 8;
116  // Load return address from shadow call stack
117  // l[w|d] ra, -[4|8](s2)
118  // addi s2, s2, -[4|8]
119  BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::LD : RISCV::LW))
120  .addReg(RAReg, RegState::Define)
121  .addReg(SCSPReg)
122  .addImm(-SlotSize)
124  BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI))
125  .addReg(SCSPReg, RegState::Define)
126  .addReg(SCSPReg)
127  .addImm(-SlotSize)
129 }
130 
131 // Get the ID of the libcall used for spilling and restoring callee saved
132 // registers. The ID is representative of the number of registers saved or
133 // restored by the libcall, except it is zero-indexed - ID 0 corresponds to a
134 // single register.
135 static int getLibCallID(const MachineFunction &MF,
136  const std::vector<CalleeSavedInfo> &CSI) {
137  const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
138 
139  if (CSI.empty() || !RVFI->useSaveRestoreLibCalls(MF))
140  return -1;
141 
142  Register MaxReg = RISCV::NoRegister;
143  for (auto &CS : CSI)
144  // RISCVRegisterInfo::hasReservedSpillSlot assigns negative frame indexes to
145  // registers which can be saved by libcall.
146  if (CS.getFrameIdx() < 0)
147  MaxReg = std::max(MaxReg.id(), CS.getReg().id());
148 
149  if (MaxReg == RISCV::NoRegister)
150  return -1;
151 
152  switch (MaxReg) {
153  default:
154  llvm_unreachable("Something has gone wrong!");
155  case /*s11*/ RISCV::X27: return 12;
156  case /*s10*/ RISCV::X26: return 11;
157  case /*s9*/ RISCV::X25: return 10;
158  case /*s8*/ RISCV::X24: return 9;
159  case /*s7*/ RISCV::X23: return 8;
160  case /*s6*/ RISCV::X22: return 7;
161  case /*s5*/ RISCV::X21: return 6;
162  case /*s4*/ RISCV::X20: return 5;
163  case /*s3*/ RISCV::X19: return 4;
164  case /*s2*/ RISCV::X18: return 3;
165  case /*s1*/ RISCV::X9: return 2;
166  case /*s0*/ RISCV::X8: return 1;
167  case /*ra*/ RISCV::X1: return 0;
168  }
169 }
170 
171 // Get the name of the libcall used for spilling callee saved registers.
172 // If this function will not use save/restore libcalls, then return a nullptr.
173 static const char *
175  const std::vector<CalleeSavedInfo> &CSI) {
176  static const char *const SpillLibCalls[] = {
177  "__riscv_save_0",
178  "__riscv_save_1",
179  "__riscv_save_2",
180  "__riscv_save_3",
181  "__riscv_save_4",
182  "__riscv_save_5",
183  "__riscv_save_6",
184  "__riscv_save_7",
185  "__riscv_save_8",
186  "__riscv_save_9",
187  "__riscv_save_10",
188  "__riscv_save_11",
189  "__riscv_save_12"
190  };
191 
192  int LibCallID = getLibCallID(MF, CSI);
193  if (LibCallID == -1)
194  return nullptr;
195  return SpillLibCalls[LibCallID];
196 }
197 
198 // Get the name of the libcall used for restoring callee saved registers.
199 // If this function will not use save/restore libcalls, then return a nullptr.
200 static const char *
202  const std::vector<CalleeSavedInfo> &CSI) {
203  static const char *const RestoreLibCalls[] = {
204  "__riscv_restore_0",
205  "__riscv_restore_1",
206  "__riscv_restore_2",
207  "__riscv_restore_3",
208  "__riscv_restore_4",
209  "__riscv_restore_5",
210  "__riscv_restore_6",
211  "__riscv_restore_7",
212  "__riscv_restore_8",
213  "__riscv_restore_9",
214  "__riscv_restore_10",
215  "__riscv_restore_11",
216  "__riscv_restore_12"
217  };
218 
219  int LibCallID = getLibCallID(MF, CSI);
220  if (LibCallID == -1)
221  return nullptr;
222  return RestoreLibCalls[LibCallID];
223 }
224 
225 // Return true if the specified function should have a dedicated frame
226 // pointer register. This is true if frame pointer elimination is
227 // disabled, if it needs dynamic stack realignment, if the function has
228 // variable sized allocas, or if the frame address is taken.
230  const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
231 
232  const MachineFrameInfo &MFI = MF.getFrameInfo();
233  return MF.getTarget().Options.DisableFramePointerElim(MF) ||
234  RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() ||
235  MFI.isFrameAddressTaken();
236 }
237 
239  const MachineFrameInfo &MFI = MF.getFrameInfo();
241 
242  // If we do not reserve stack space for outgoing arguments in prologue,
243  // we will adjust the stack pointer before call instruction. After the
244  // adjustment, we can not use SP to access the stack objects for the
245  // arguments. Instead, use BP to access these stack objects.
246  return (MFI.hasVarSizedObjects() ||
248  MFI.getMaxCallFrameSize() != 0))) &&
250 }
251 
252 // Determines the size of the frame and maximum call frame size.
253 void RISCVFrameLowering::determineFrameLayout(MachineFunction &MF) const {
254  MachineFrameInfo &MFI = MF.getFrameInfo();
255  auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
256 
257  // Get the number of bytes to allocate from the FrameInfo.
258  uint64_t FrameSize = MFI.getStackSize();
259 
260  // Get the alignment.
262 
263  // Make sure the frame is aligned.
264  FrameSize = alignTo(FrameSize, StackAlign);
265 
266  // Update frame info.
267  MFI.setStackSize(FrameSize);
268 
269  // When using SP or BP to access stack objects, we may require extra padding
270  // to ensure the bottom of the RVV stack is correctly aligned within the main
271  // stack. We calculate this as the amount required to align the scalar local
272  // variable section up to the RVV alignment.
274  if (RVFI->getRVVStackSize() && (!hasFP(MF) || TRI->hasStackRealignment(MF))) {
275  int ScalarLocalVarSize = FrameSize - RVFI->getCalleeSavedStackSize() -
276  RVFI->getVarArgsSaveSize();
277  if (auto RVVPadding =
278  offsetToAlignment(ScalarLocalVarSize, RVFI->getRVVStackAlign()))
279  RVFI->setRVVPadding(RVVPadding);
280  }
281 }
282 
283 // Returns the stack size including RVV padding (when required), rounded back
284 // up to the required stack alignment.
286  const MachineFunction &MF) const {
287  const MachineFrameInfo &MFI = MF.getFrameInfo();
288  auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
289  return alignTo(MFI.getStackSize() + RVFI->getRVVPadding(), getStackAlign());
290 }
291 
292 void RISCVFrameLowering::adjustReg(MachineBasicBlock &MBB,
294  const DebugLoc &DL, Register DestReg,
295  Register SrcReg, int64_t Val,
296  MachineInstr::MIFlag Flag) const {
298  const RISCVInstrInfo *TII = STI.getInstrInfo();
299 
300  if (DestReg == SrcReg && Val == 0)
301  return;
302 
303  if (isInt<12>(Val)) {
304  BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg)
305  .addReg(SrcReg)
306  .addImm(Val)
307  .setMIFlag(Flag);
308  return;
309  }
310 
311  // Try to split the offset across two ADDIs. We need to keep the stack pointer
312  // aligned after each ADDI. We need to determine the maximum value we can put
313  // in each ADDI. In the negative direction, we can use -2048 which is always
314  // sufficiently aligned. In the positive direction, we need to find the
315  // largest 12-bit immediate that is aligned. Exclude -4096 since it can be
316  // created with LUI.
317  assert(getStackAlign().value() < 2048 && "Stack alignment too large");
318  int64_t MaxPosAdjStep = 2048 - getStackAlign().value();
319  if (Val > -4096 && Val <= (2 * MaxPosAdjStep)) {
320  int64_t FirstAdj = Val < 0 ? -2048 : MaxPosAdjStep;
321  Val -= FirstAdj;
322  BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg)
323  .addReg(SrcReg)
324  .addImm(FirstAdj)
325  .setMIFlag(Flag);
326  BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg)
327  .addReg(DestReg, RegState::Kill)
328  .addImm(Val)
329  .setMIFlag(Flag);
330  return;
331  }
332 
333  unsigned Opc = RISCV::ADD;
334  if (Val < 0) {
335  Val = -Val;
336  Opc = RISCV::SUB;
337  }
338 
339  Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
340  TII->movImm(MBB, MBBI, DL, ScratchReg, Val, Flag);
341  BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
342  .addReg(SrcReg)
343  .addReg(ScratchReg, RegState::Kill)
344  .setMIFlag(Flag);
345 }
346 
347 // Returns the register used to hold the frame pointer.
348 static Register getFPReg(const RISCVSubtarget &STI) { return RISCV::X8; }
349 
350 // Returns the register used to hold the stack pointer.
351 static Register getSPReg(const RISCVSubtarget &STI) { return RISCV::X2; }
352 
355  const std::vector<CalleeSavedInfo> &CSI) {
356  const MachineFrameInfo &MFI = MF.getFrameInfo();
357  SmallVector<CalleeSavedInfo, 8> NonLibcallCSI;
358 
359  for (auto &CS : CSI) {
360  int FI = CS.getFrameIdx();
361  if (FI >= 0 && MFI.getStackID(FI) == TargetStackID::Default)
362  NonLibcallCSI.push_back(CS);
363  }
364 
365  return NonLibcallCSI;
366 }
367 
368 void RISCVFrameLowering::adjustStackForRVV(MachineFunction &MF,
371  const DebugLoc &DL, int64_t Amount,
372  MachineInstr::MIFlag Flag) const {
373  assert(Amount != 0 && "Did not need to adjust stack pointer for RVV.");
374 
375  const RISCVInstrInfo *TII = STI.getInstrInfo();
376  const Register SPReg = getSPReg(STI);
377 
378  // Optimize compile time offset case
379  if (STI.getRealMinVLen() == STI.getRealMaxVLen()) {
380  // 1. Multiply the number of v-slots by the (constant) length of register
381  const int64_t VLENB = STI.getRealMinVLen() / 8;
382  assert(Amount % 8 == 0 &&
383  "Reserve the stack by the multiple of one vector size.");
384  const int64_t NumOfVReg = Amount / 8;
385  const int64_t Offset = NumOfVReg * VLENB;
386  if (!isInt<32>(Offset)) {
388  "Frame size outside of the signed 32-bit range not supported");
389  }
390  adjustReg(MBB, MBBI, DL, SPReg, SPReg, Offset, Flag);
391  return;
392  }
393 
394  unsigned Opc = RISCV::ADD;
395  if (Amount < 0) {
396  Amount = -Amount;
397  Opc = RISCV::SUB;
398  }
399  // 1. Multiply the number of v-slots to the length of registers
400  Register FactorRegister =
401  MF.getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
402  TII->getVLENFactoredAmount(MF, MBB, MBBI, DL, FactorRegister, Amount, Flag);
403  // 2. SP = SP - RVV stack size
404  BuildMI(MBB, MBBI, DL, TII->get(Opc), SPReg)
405  .addReg(SPReg)
406  .addReg(FactorRegister, RegState::Kill)
407  .setMIFlag(Flag);
408 }
409 
411  MachineBasicBlock &MBB) const {
412  MachineFrameInfo &MFI = MF.getFrameInfo();
413  auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
414  const RISCVRegisterInfo *RI = STI.getRegisterInfo();
415  const RISCVInstrInfo *TII = STI.getInstrInfo();
417 
418  Register FPReg = getFPReg(STI);
419  Register SPReg = getSPReg(STI);
420  Register BPReg = RISCVABI::getBPReg();
421 
422  // Debug location must be unknown since the first debug location is used
423  // to determine the end of the prologue.
424  DebugLoc DL;
425 
426  // All calls are tail calls in GHC calling conv, and functions have no
427  // prologue/epilogue.
429  return;
430 
431  // Emit prologue for shadow call stack.
432  emitSCSPrologue(MF, MBB, MBBI, DL);
433 
434  // Since spillCalleeSavedRegisters may have inserted a libcall, skip past
435  // any instructions marked as FrameSetup
436  while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup))
437  ++MBBI;
438 
439  // Determine the correct frame layout
440  determineFrameLayout(MF);
441 
442  // If libcalls are used to spill and restore callee-saved registers, the frame
443  // has two sections; the opaque section managed by the libcalls, and the
444  // section managed by MachineFrameInfo which can also hold callee saved
445  // registers in fixed stack slots, both of which have negative frame indices.
446  // This gets even more complicated when incoming arguments are passed via the
447  // stack, as these too have negative frame indices. An example is detailed
448  // below:
449  //
450  // | incoming arg | <- FI[-3]
451  // | libcallspill |
452  // | calleespill | <- FI[-2]
453  // | calleespill | <- FI[-1]
454  // | this_frame | <- FI[0]
455  //
456  // For negative frame indices, the offset from the frame pointer will differ
457  // depending on which of these groups the frame index applies to.
458  // The following calculates the correct offset knowing the number of callee
459  // saved registers spilt by the two methods.
460  if (int LibCallRegs = getLibCallID(MF, MFI.getCalleeSavedInfo()) + 1) {
461  // Calculate the size of the frame managed by the libcall. The libcalls are
462  // implemented such that the stack will always be 16 byte aligned.
463  unsigned LibCallFrameSize = alignTo((STI.getXLen() / 8) * LibCallRegs, 16);
464  RVFI->setLibCallStackSize(LibCallFrameSize);
465  }
466 
467  // FIXME (note copied from Lanai): This appears to be overallocating. Needs
468  // investigation. Get the number of bytes to allocate from the FrameInfo.
469  uint64_t StackSize = getStackSizeWithRVVPadding(MF);
470  uint64_t RealStackSize = StackSize + RVFI->getLibCallStackSize();
471  uint64_t RVVStackSize = RVFI->getRVVStackSize();
472 
473  // Early exit if there is no need to allocate on the stack
474  if (RealStackSize == 0 && !MFI.adjustsStack() && RVVStackSize == 0)
475  return;
476 
477  // If the stack pointer has been marked as reserved, then produce an error if
478  // the frame requires stack allocation
479  if (STI.isRegisterReservedByUser(SPReg))
481  MF.getFunction(), "Stack pointer required, but has been reserved."});
482 
483  uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
484  // Split the SP adjustment to reduce the offsets of callee saved spill.
485  if (FirstSPAdjustAmount) {
486  StackSize = FirstSPAdjustAmount;
487  RealStackSize = FirstSPAdjustAmount;
488  }
489 
490  // Allocate space on the stack if necessary.
491  adjustReg(MBB, MBBI, DL, SPReg, SPReg, -StackSize, MachineInstr::FrameSetup);
492 
493  // Emit ".cfi_def_cfa_offset RealStackSize"
494  unsigned CFIIndex = MF.addFrameInst(
495  MCCFIInstruction::cfiDefCfaOffset(nullptr, RealStackSize));
496  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
497  .addCFIIndex(CFIIndex)
499 
500  const auto &CSI = MFI.getCalleeSavedInfo();
501 
502  // The frame pointer is callee-saved, and code has been generated for us to
503  // save it to the stack. We need to skip over the storing of callee-saved
504  // registers as the frame pointer must be modified after it has been saved
505  // to the stack, not before.
506  // FIXME: assumes exactly one instruction is used to save each callee-saved
507  // register.
508  std::advance(MBBI, getNonLibcallCSI(MF, CSI).size());
509 
510  // Iterate over list of callee-saved registers and emit .cfi_offset
511  // directives.
512  for (const auto &Entry : CSI) {
513  int FrameIdx = Entry.getFrameIdx();
514  int64_t Offset;
515  // Offsets for objects with fixed locations (IE: those saved by libcall) are
516  // simply calculated from the frame index.
517  if (FrameIdx < 0)
518  Offset = FrameIdx * (int64_t) STI.getXLen() / 8;
519  else
520  Offset = MFI.getObjectOffset(Entry.getFrameIdx()) -
521  RVFI->getLibCallStackSize();
522  Register Reg = Entry.getReg();
523  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
524  nullptr, RI->getDwarfRegNum(Reg, true), Offset));
525  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
526  .addCFIIndex(CFIIndex)
528  }
529 
530  // Generate new FP.
531  if (hasFP(MF)) {
532  if (STI.isRegisterReservedByUser(FPReg))
534  MF.getFunction(), "Frame pointer required, but has been reserved."});
535  // The frame pointer does need to be reserved from register allocation.
536  assert(MF.getRegInfo().isReserved(FPReg) && "FP not reserved");
537 
538  adjustReg(MBB, MBBI, DL, FPReg, SPReg,
539  RealStackSize - RVFI->getVarArgsSaveSize(),
541 
542  // Emit ".cfi_def_cfa $fp, RVFI->getVarArgsSaveSize()"
543  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
544  nullptr, RI->getDwarfRegNum(FPReg, true), RVFI->getVarArgsSaveSize()));
545  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
546  .addCFIIndex(CFIIndex)
548  }
549 
550  // Emit the second SP adjustment after saving callee saved registers.
551  if (FirstSPAdjustAmount) {
552  uint64_t SecondSPAdjustAmount =
553  getStackSizeWithRVVPadding(MF) - FirstSPAdjustAmount;
554  assert(SecondSPAdjustAmount > 0 &&
555  "SecondSPAdjustAmount should be greater than zero");
556  adjustReg(MBB, MBBI, DL, SPReg, SPReg, -SecondSPAdjustAmount,
558 
559  // If we are using a frame-pointer, and thus emitted ".cfi_def_cfa fp, 0",
560  // don't emit an sp-based .cfi_def_cfa_offset
561  if (!hasFP(MF)) {
562  // Emit ".cfi_def_cfa_offset StackSize"
563  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(
564  nullptr, getStackSizeWithRVVPadding(MF)));
565  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
566  .addCFIIndex(CFIIndex)
568  }
569  }
570 
571  if (RVVStackSize)
572  adjustStackForRVV(MF, MBB, MBBI, DL, -RVVStackSize,
574 
575  if (hasFP(MF)) {
576  // Realign Stack
577  const RISCVRegisterInfo *RI = STI.getRegisterInfo();
578  if (RI->hasStackRealignment(MF)) {
579  Align MaxAlignment = MFI.getMaxAlign();
580 
581  const RISCVInstrInfo *TII = STI.getInstrInfo();
582  if (isInt<12>(-(int)MaxAlignment.value())) {
583  BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg)
584  .addReg(SPReg)
585  .addImm(-(int)MaxAlignment.value())
587  } else {
588  unsigned ShiftAmount = Log2(MaxAlignment);
589  Register VR =
590  MF.getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
591  BuildMI(MBB, MBBI, DL, TII->get(RISCV::SRLI), VR)
592  .addReg(SPReg)
593  .addImm(ShiftAmount)
595  BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), SPReg)
596  .addReg(VR)
597  .addImm(ShiftAmount)
599  }
600  // FP will be used to restore the frame in the epilogue, so we need
601  // another base register BP to record SP after re-alignment. SP will
602  // track the current stack after allocating variable sized objects.
603  if (hasBP(MF)) {
604  // move BP, SP
605  BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), BPReg)
606  .addReg(SPReg)
607  .addImm(0)
609  }
610  }
611  }
612 }
613 
615  MachineBasicBlock &MBB) const {
616  const RISCVRegisterInfo *RI = STI.getRegisterInfo();
617  MachineFrameInfo &MFI = MF.getFrameInfo();
618  auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
619  Register FPReg = getFPReg(STI);
620  Register SPReg = getSPReg(STI);
621 
622  // All calls are tail calls in GHC calling conv, and functions have no
623  // prologue/epilogue.
625  return;
626 
627  // Get the insert location for the epilogue. If there were no terminators in
628  // the block, get the last instruction.
630  DebugLoc DL;
631  if (!MBB.empty()) {
633  if (MBBI != MBB.end())
634  DL = MBBI->getDebugLoc();
635 
637 
638  // If callee-saved registers are saved via libcall, place stack adjustment
639  // before this call.
640  while (MBBI != MBB.begin() &&
641  std::prev(MBBI)->getFlag(MachineInstr::FrameDestroy))
642  --MBBI;
643  }
644 
645  const auto &CSI = getNonLibcallCSI(MF, MFI.getCalleeSavedInfo());
646 
647  // Skip to before the restores of callee-saved registers
648  // FIXME: assumes exactly one instruction is used to restore each
649  // callee-saved register.
650  auto LastFrameDestroy = MBBI;
651  if (!CSI.empty())
652  LastFrameDestroy = std::prev(MBBI, CSI.size());
653 
654  uint64_t StackSize = getStackSizeWithRVVPadding(MF);
655  uint64_t RealStackSize = StackSize + RVFI->getLibCallStackSize();
656  uint64_t FPOffset = RealStackSize - RVFI->getVarArgsSaveSize();
657  uint64_t RVVStackSize = RVFI->getRVVStackSize();
658 
659  // Restore the stack pointer using the value of the frame pointer. Only
660  // necessary if the stack pointer was modified, meaning the stack size is
661  // unknown.
662  //
663  // In order to make sure the stack point is right through the EH region,
664  // we also need to restore stack pointer from the frame pointer if we
665  // don't preserve stack space within prologue/epilogue for outgoing variables,
666  // normally it's just checking the variable sized object is present or not
667  // is enough, but we also don't preserve that at prologue/epilogue when
668  // have vector objects in stack.
669  if (RI->hasStackRealignment(MF) || MFI.hasVarSizedObjects() ||
670  !hasReservedCallFrame(MF)) {
671  assert(hasFP(MF) && "frame pointer should not have been eliminated");
672  adjustReg(MBB, LastFrameDestroy, DL, SPReg, FPReg, -FPOffset,
674  } else {
675  if (RVVStackSize)
676  adjustStackForRVV(MF, MBB, LastFrameDestroy, DL, RVVStackSize,
678  }
679 
680  uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
681  if (FirstSPAdjustAmount) {
682  uint64_t SecondSPAdjustAmount =
683  getStackSizeWithRVVPadding(MF) - FirstSPAdjustAmount;
684  assert(SecondSPAdjustAmount > 0 &&
685  "SecondSPAdjustAmount should be greater than zero");
686 
687  adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg, SecondSPAdjustAmount,
689  }
690 
691  if (FirstSPAdjustAmount)
692  StackSize = FirstSPAdjustAmount;
693 
694  // Deallocate stack
695  adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy);
696 
697  // Emit epilogue for shadow call stack.
698  emitSCSEpilogue(MF, MBB, MBBI, DL);
699 }
700 
703  Register &FrameReg) const {
704  const MachineFrameInfo &MFI = MF.getFrameInfo();
706  const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
707 
708  // Callee-saved registers should be referenced relative to the stack
709  // pointer (positive offset), otherwise use the frame pointer (negative
710  // offset).
711  const auto &CSI = getNonLibcallCSI(MF, MFI.getCalleeSavedInfo());
712  int MinCSFI = 0;
713  int MaxCSFI = -1;
714  StackOffset Offset;
715  auto StackID = MFI.getStackID(FI);
716 
717  assert((StackID == TargetStackID::Default ||
718  StackID == TargetStackID::ScalableVector) &&
719  "Unexpected stack ID for the frame object.");
720  if (StackID == TargetStackID::Default) {
721  Offset =
723  MFI.getOffsetAdjustment());
724  } else if (StackID == TargetStackID::ScalableVector) {
725  Offset = StackOffset::getScalable(MFI.getObjectOffset(FI));
726  }
727 
728  uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
729 
730  if (CSI.size()) {
731  MinCSFI = CSI[0].getFrameIdx();
732  MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
733  }
734 
735  if (FI >= MinCSFI && FI <= MaxCSFI) {
736  FrameReg = RISCV::X2;
737 
738  if (FirstSPAdjustAmount)
739  Offset += StackOffset::getFixed(FirstSPAdjustAmount);
740  else
742  return Offset;
743  }
744 
745  if (RI->hasStackRealignment(MF) && !MFI.isFixedObjectIndex(FI)) {
746  // If the stack was realigned, the frame pointer is set in order to allow
747  // SP to be restored, so we need another base register to record the stack
748  // after realignment.
749  // |--------------------------| -- <-- FP
750  // | callee-allocated save | | <----|
751  // | area for register varargs| | |
752  // |--------------------------| | |
753  // | callee-saved registers | | |
754  // |--------------------------| -- |
755  // | realignment (the size of | | |
756  // | this area is not counted | | |
757  // | in MFI.getStackSize()) | | |
758  // |--------------------------| -- |-- MFI.getStackSize()
759  // | RVV alignment padding | | |
760  // | (not counted in | | |
761  // | MFI.getStackSize() but | | |
762  // | counted in | | |
763  // | RVFI.getRVVStackSize()) | | |
764  // |--------------------------| -- |
765  // | RVV objects | | |
766  // | (not counted in | | |
767  // | MFI.getStackSize()) | | |
768  // |--------------------------| -- |
769  // | padding before RVV | | |
770  // | (not counted in | | |
771  // | MFI.getStackSize() or in | | |
772  // | RVFI.getRVVStackSize()) | | |
773  // |--------------------------| -- |
774  // | scalar local variables | | <----'
775  // |--------------------------| -- <-- BP (if var sized objects present)
776  // | VarSize objects | |
777  // |--------------------------| -- <-- SP
778  if (hasBP(MF)) {
779  FrameReg = RISCVABI::getBPReg();
780  } else {
781  // VarSize objects must be empty in this case!
782  assert(!MFI.hasVarSizedObjects());
783  FrameReg = RISCV::X2;
784  }
785  } else {
786  FrameReg = RI->getFrameRegister(MF);
787  }
788 
789  if (FrameReg == getFPReg(STI)) {
790  Offset += StackOffset::getFixed(RVFI->getVarArgsSaveSize());
791  if (FI >= 0)
792  Offset -= StackOffset::getFixed(RVFI->getLibCallStackSize());
793  // When using FP to access scalable vector objects, we need to minus
794  // the frame size.
795  //
796  // |--------------------------| -- <-- FP
797  // | callee-allocated save | |
798  // | area for register varargs| |
799  // |--------------------------| |
800  // | callee-saved registers | |
801  // |--------------------------| | MFI.getStackSize()
802  // | scalar local variables | |
803  // |--------------------------| -- (Offset of RVV objects is from here.)
804  // | RVV objects |
805  // |--------------------------|
806  // | VarSize objects |
807  // |--------------------------| <-- SP
808  if (MFI.getStackID(FI) == TargetStackID::ScalableVector) {
809  assert(!RI->hasStackRealignment(MF) &&
810  "Can't index across variable sized realign");
811  // We don't expect any extra RVV alignment padding, as the stack size
812  // and RVV object sections should be correct aligned in their own
813  // right.
815  "Inconsistent stack layout");
816  Offset -= StackOffset::getFixed(MFI.getStackSize());
817  }
818  return Offset;
819  }
820 
821  // This case handles indexing off both SP and BP.
822  // If indexing off SP, there must not be any var sized objects
823  assert(FrameReg == RISCVABI::getBPReg() || !MFI.hasVarSizedObjects());
824 
825  // When using SP to access frame objects, we need to add RVV stack size.
826  //
827  // |--------------------------| -- <-- FP
828  // | callee-allocated save | | <----|
829  // | area for register varargs| | |
830  // |--------------------------| | |
831  // | callee-saved registers | | |
832  // |--------------------------| -- |
833  // | RVV alignment padding | | |
834  // | (not counted in | | |
835  // | MFI.getStackSize() but | | |
836  // | counted in | | |
837  // | RVFI.getRVVStackSize()) | | |
838  // |--------------------------| -- |
839  // | RVV objects | | |-- MFI.getStackSize()
840  // | (not counted in | | |
841  // | MFI.getStackSize()) | | |
842  // |--------------------------| -- |
843  // | padding before RVV | | |
844  // | (not counted in | | |
845  // | MFI.getStackSize()) | | |
846  // |--------------------------| -- |
847  // | scalar local variables | | <----'
848  // |--------------------------| -- <-- BP (if var sized objects present)
849  // | VarSize objects | |
850  // |--------------------------| -- <-- SP
851  //
852  // The total amount of padding surrounding RVV objects is described by
853  // RVV->getRVVPadding() and it can be zero. It allows us to align the RVV
854  // objects to the required alignment.
855  if (MFI.getStackID(FI) == TargetStackID::Default) {
856  if (MFI.isFixedObjectIndex(FI)) {
857  assert(!RI->hasStackRealignment(MF) &&
858  "Can't index across variable sized realign");
860  RVFI->getLibCallStackSize(),
861  RVFI->getRVVStackSize());
862  } else {
863  Offset += StackOffset::getFixed(MFI.getStackSize());
864  }
865  } else if (MFI.getStackID(FI) == TargetStackID::ScalableVector) {
866  // Ensure the base of the RVV stack is correctly aligned: add on the
867  // alignment padding.
868  int ScalarLocalVarSize =
869  MFI.getStackSize() - RVFI->getCalleeSavedStackSize() -
870  RVFI->getVarArgsSaveSize() + RVFI->getRVVPadding();
871  Offset += StackOffset::get(ScalarLocalVarSize, RVFI->getRVVStackSize());
872  }
873  return Offset;
874 }
875 
877  BitVector &SavedRegs,
878  RegScavenger *RS) const {
880  // Unconditionally spill RA and FP only if the function uses a frame
881  // pointer.
882  if (hasFP(MF)) {
883  SavedRegs.set(RISCV::X1);
884  SavedRegs.set(RISCV::X8);
885  }
886  // Mark BP as used if function has dedicated base pointer.
887  if (hasBP(MF))
888  SavedRegs.set(RISCVABI::getBPReg());
889 
890  // If interrupt is enabled and there are calls in the handler,
891  // unconditionally save all Caller-saved registers and
892  // all FP registers, regardless whether they are used.
893  MachineFrameInfo &MFI = MF.getFrameInfo();
894 
895  if (MF.getFunction().hasFnAttribute("interrupt") && MFI.hasCalls()) {
896 
897  static const MCPhysReg CSRegs[] = { RISCV::X1, /* ra */
898  RISCV::X5, RISCV::X6, RISCV::X7, /* t0-t2 */
899  RISCV::X10, RISCV::X11, /* a0-a1, a2-a7 */
900  RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17,
901  RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, 0 /* t3-t6 */
902  };
903 
904  for (unsigned i = 0; CSRegs[i]; ++i)
905  SavedRegs.set(CSRegs[i]);
906 
907  if (MF.getSubtarget<RISCVSubtarget>().hasStdExtF()) {
908 
909  // If interrupt is enabled, this list contains all FP registers.
910  const MCPhysReg * Regs = MF.getRegInfo().getCalleeSavedRegs();
911 
912  for (unsigned i = 0; Regs[i]; ++i)
913  if (RISCV::FPR16RegClass.contains(Regs[i]) ||
914  RISCV::FPR32RegClass.contains(Regs[i]) ||
915  RISCV::FPR64RegClass.contains(Regs[i]))
916  SavedRegs.set(Regs[i]);
917  }
918  }
919 }
920 
921 std::pair<int64_t, Align>
922 RISCVFrameLowering::assignRVVStackObjectOffsets(MachineFunction &MF) const {
923  MachineFrameInfo &MFI = MF.getFrameInfo();
924  // Create a buffer of RVV objects to allocate.
925  SmallVector<int, 8> ObjectsToAllocate;
926  for (int I = 0, E = MFI.getObjectIndexEnd(); I != E; ++I) {
927  unsigned StackID = MFI.getStackID(I);
928  if (StackID != TargetStackID::ScalableVector)
929  continue;
930  if (MFI.isDeadObjectIndex(I))
931  continue;
932 
933  ObjectsToAllocate.push_back(I);
934  }
935 
936  // The minimum alignment is 16 bytes.
937  Align RVVStackAlign(16);
938  const auto &ST = MF.getSubtarget<RISCVSubtarget>();
939 
940  if (!ST.hasVInstructions()) {
941  assert(ObjectsToAllocate.empty() &&
942  "Can't allocate scalable-vector objects without V instructions");
943  return std::make_pair(0, RVVStackAlign);
944  }
945 
946  // Allocate all RVV locals and spills
947  int64_t Offset = 0;
948  for (int FI : ObjectsToAllocate) {
949  // ObjectSize in bytes.
950  int64_t ObjectSize = MFI.getObjectSize(FI);
951  auto ObjectAlign = std::max(Align(8), MFI.getObjectAlign(FI));
952  // If the data type is the fractional vector type, reserve one vector
953  // register for it.
954  if (ObjectSize < 8)
955  ObjectSize = 8;
956  Offset = alignTo(Offset + ObjectSize, ObjectAlign);
957  MFI.setObjectOffset(FI, -Offset);
958  // Update the maximum alignment of the RVV stack section
959  RVVStackAlign = std::max(RVVStackAlign, ObjectAlign);
960  }
961 
962  // Ensure the alignment of the RVV stack. Since we want the most-aligned
963  // object right at the bottom (i.e., any padding at the top of the frame),
964  // readjust all RVV objects down by the alignment padding.
965  uint64_t StackSize = Offset;
966  if (auto AlignmentPadding = offsetToAlignment(StackSize, RVVStackAlign)) {
967  StackSize += AlignmentPadding;
968  for (int FI : ObjectsToAllocate)
969  MFI.setObjectOffset(FI, MFI.getObjectOffset(FI) - AlignmentPadding);
970  }
971 
972  return std::make_pair(StackSize, RVVStackAlign);
973 }
974 
976  // For RVV spill, scalable stack offsets computing requires up to two scratch
977  // registers
978  static constexpr unsigned ScavSlotsNumRVVSpillScalableObject = 2;
979 
980  // For RVV spill, non-scalable stack offsets computing requires up to one
981  // scratch register.
982  static constexpr unsigned ScavSlotsNumRVVSpillNonScalableObject = 1;
983 
984  // ADDI instruction's destination register can be used for computing
985  // offsets. So Scalable stack offsets require up to one scratch register.
986  static constexpr unsigned ScavSlotsADDIScalableObject = 1;
987 
988  static constexpr unsigned MaxScavSlotsNumKnown =
989  std::max({ScavSlotsADDIScalableObject, ScavSlotsNumRVVSpillScalableObject,
990  ScavSlotsNumRVVSpillNonScalableObject});
991 
992  unsigned MaxScavSlotsNum = 0;
994  return false;
995  for (const MachineBasicBlock &MBB : MF)
996  for (const MachineInstr &MI : MBB) {
997  bool IsRVVSpill = RISCV::isRVVSpill(MI);
998  for (auto &MO : MI.operands()) {
999  if (!MO.isFI())
1000  continue;
1001  bool IsScalableVectorID = MF.getFrameInfo().getStackID(MO.getIndex()) ==
1003  if (IsRVVSpill) {
1004  MaxScavSlotsNum = std::max(
1005  MaxScavSlotsNum, IsScalableVectorID
1006  ? ScavSlotsNumRVVSpillScalableObject
1007  : ScavSlotsNumRVVSpillNonScalableObject);
1008  } else if (MI.getOpcode() == RISCV::ADDI && IsScalableVectorID) {
1009  MaxScavSlotsNum =
1010  std::max(MaxScavSlotsNum, ScavSlotsADDIScalableObject);
1011  }
1012  }
1013  if (MaxScavSlotsNum == MaxScavSlotsNumKnown)
1014  return MaxScavSlotsNumKnown;
1015  }
1016  return MaxScavSlotsNum;
1017 }
1018 
1019 static bool hasRVVFrameObject(const MachineFunction &MF) {
1020  // Originally, the function will scan all the stack objects to check whether
1021  // if there is any scalable vector object on the stack or not. However, it
1022  // causes errors in the register allocator. In issue 53016, it returns false
1023  // before RA because there is no RVV stack objects. After RA, it returns true
1024  // because there are spilling slots for RVV values during RA. It will not
1025  // reserve BP during register allocation and generate BP access in the PEI
1026  // pass due to the inconsistent behavior of the function.
1027  //
1028  // The function is changed to use hasVInstructions() as the return value. It
1029  // is not precise, but it can make the register allocation correct.
1030  //
1031  // FIXME: Find a better way to make the decision or revisit the solution in
1032  // D103622.
1033  //
1034  // Refer to https://github.com/llvm/llvm-project/issues/53016.
1035  return MF.getSubtarget<RISCVSubtarget>().hasVInstructions();
1036 }
1037 
1039  const RISCVInstrInfo &TII) {
1040  unsigned FnSize = 0;
1041  for (auto &MBB : MF) {
1042  for (auto &MI : MBB) {
1043  // Far branches over 20-bit offset will be relaxed in branch relaxation
1044  // pass. In the worst case, conditional branches will be relaxed into
1045  // the following instruction sequence. Unconditional branches are
1046  // relaxed in the same way, with the exception that there is no first
1047  // branch instruction.
1048  //
1049  // foo
1050  // bne t5, t6, .rev_cond # `TII->getInstSizeInBytes(MI)` bytes
1051  // sd s11, 0(sp) # 4 bytes, or 2 bytes in RVC
1052  // jump .restore, s11 # 8 bytes
1053  // .rev_cond
1054  // bar
1055  // j .dest_bb # 4 bytes, or 2 bytes in RVC
1056  // .restore:
1057  // ld s11, 0(sp) # 4 bytes, or 2 bytes in RVC
1058  // .dest:
1059  // baz
1060  if (MI.isConditionalBranch())
1061  FnSize += TII.getInstSizeInBytes(MI);
1062  if (MI.isConditionalBranch() || MI.isUnconditionalBranch()) {
1063  if (MF.getSubtarget<RISCVSubtarget>().hasStdExtC())
1064  FnSize += 2 + 8 + 2 + 2;
1065  else
1066  FnSize += 4 + 8 + 4 + 4;
1067  continue;
1068  }
1069 
1070  FnSize += TII.getInstSizeInBytes(MI);
1071  }
1072  }
1073  return FnSize;
1074 }
1075 
1077  MachineFunction &MF, RegScavenger *RS) const {
1078  const RISCVRegisterInfo *RegInfo =
1079  MF.getSubtarget<RISCVSubtarget>().getRegisterInfo();
1080  const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
1081  MachineFrameInfo &MFI = MF.getFrameInfo();
1082  const TargetRegisterClass *RC = &RISCV::GPRRegClass;
1083  auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
1084 
1085  int64_t RVVStackSize;
1086  Align RVVStackAlign;
1087  std::tie(RVVStackSize, RVVStackAlign) = assignRVVStackObjectOffsets(MF);
1088 
1089  RVFI->setRVVStackSize(RVVStackSize);
1090  RVFI->setRVVStackAlign(RVVStackAlign);
1091 
1092  if (hasRVVFrameObject(MF)) {
1093  // Ensure the entire stack is aligned to at least the RVV requirement: some
1094  // scalable-vector object alignments are not considered by the
1095  // target-independent code.
1096  MFI.ensureMaxAlignment(RVVStackAlign);
1097  }
1098 
1099  unsigned ScavSlotsNum = 0;
1100 
1101  // estimateStackSize has been observed to under-estimate the final stack
1102  // size, so give ourselves wiggle-room by checking for stack size
1103  // representable an 11-bit signed field rather than 12-bits.
1104  if (!isInt<11>(MFI.estimateStackSize(MF)))
1105  ScavSlotsNum = 1;
1106 
1107  // Far branches over 20-bit offset require a spill slot for scratch register.
1108  bool IsLargeFunction = !isInt<20>(estimateFunctionSizeInBytes(MF, *TII));
1109  if (IsLargeFunction)
1110  ScavSlotsNum = std::max(ScavSlotsNum, 1u);
1111 
1112  // RVV loads & stores have no capacity to hold the immediate address offsets
1113  // so we must always reserve an emergency spill slot if the MachineFunction
1114  // contains any RVV spills.
1115  ScavSlotsNum = std::max(ScavSlotsNum, getScavSlotsNumForRVV(MF));
1116 
1117  for (unsigned I = 0; I < ScavSlotsNum; I++) {
1118  int FI = MFI.CreateStackObject(RegInfo->getSpillSize(*RC),
1119  RegInfo->getSpillAlign(*RC), false);
1120  RS->addScavengingFrameIndex(FI);
1121 
1122  if (IsLargeFunction && RVFI->getBranchRelaxationScratchFrameIndex() == -1)
1123  RVFI->setBranchRelaxationScratchFrameIndex(FI);
1124  }
1125 
1126  if (MFI.getCalleeSavedInfo().empty() || RVFI->useSaveRestoreLibCalls(MF)) {
1127  RVFI->setCalleeSavedStackSize(0);
1128  return;
1129  }
1130 
1131  unsigned Size = 0;
1132  for (const auto &Info : MFI.getCalleeSavedInfo()) {
1133  int FrameIdx = Info.getFrameIdx();
1134  if (MFI.getStackID(FrameIdx) != TargetStackID::Default)
1135  continue;
1136 
1137  Size += MFI.getObjectSize(FrameIdx);
1138  }
1139  RVFI->setCalleeSavedStackSize(Size);
1140 }
1141 
1142 // Not preserve stack space within prologue for outgoing variables when the
1143 // function contains variable size objects or there are vector objects accessed
1144 // by the frame pointer.
1145 // Let eliminateCallFramePseudoInstr preserve stack space for it.
1147  return !MF.getFrameInfo().hasVarSizedObjects() &&
1148  !(hasFP(MF) && hasRVVFrameObject(MF));
1149 }
1150 
1151 // Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions.
1155  Register SPReg = RISCV::X2;
1156  DebugLoc DL = MI->getDebugLoc();
1157 
1158  if (!hasReservedCallFrame(MF)) {
1159  // If space has not been reserved for a call frame, ADJCALLSTACKDOWN and
1160  // ADJCALLSTACKUP must be converted to instructions manipulating the stack
1161  // pointer. This is necessary when there is a variable length stack
1162  // allocation (e.g. alloca), which means it's not possible to allocate
1163  // space for outgoing arguments from within the function prologue.
1164  int64_t Amount = MI->getOperand(0).getImm();
1165 
1166  if (Amount != 0) {
1167  // Ensure the stack remains aligned after adjustment.
1168  Amount = alignSPAdjust(Amount);
1169 
1170  if (MI->getOpcode() == RISCV::ADJCALLSTACKDOWN)
1171  Amount = -Amount;
1172 
1173  adjustReg(MBB, MI, DL, SPReg, SPReg, Amount, MachineInstr::NoFlags);
1174  }
1175  }
1176 
1177  return MBB.erase(MI);
1178 }
1179 
1180 // We would like to split the SP adjustment to reduce prologue/epilogue
1181 // as following instructions. In this way, the offset of the callee saved
1182 // register could fit in a single store.
1183 // add sp,sp,-2032
1184 // sw ra,2028(sp)
1185 // sw s0,2024(sp)
1186 // sw s1,2020(sp)
1187 // sw s3,2012(sp)
1188 // sw s4,2008(sp)
1189 // add sp,sp,-64
1190 uint64_t
1192  const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
1193  const MachineFrameInfo &MFI = MF.getFrameInfo();
1194  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
1195  uint64_t StackSize = getStackSizeWithRVVPadding(MF);
1196 
1197  // Disable SplitSPAdjust if save-restore libcall is used. The callee-saved
1198  // registers will be pushed by the save-restore libcalls, so we don't have to
1199  // split the SP adjustment in this case.
1200  if (RVFI->getLibCallStackSize())
1201  return 0;
1202 
1203  // Return the FirstSPAdjustAmount if the StackSize can not fit in a signed
1204  // 12-bit and there exists a callee-saved register needing to be pushed.
1205  if (!isInt<12>(StackSize) && (CSI.size() > 0)) {
1206  // FirstSPAdjustAmount is chosen as (2048 - StackAlign) because 2048 will
1207  // cause sp = sp + 2048 in the epilogue to be split into multiple
1208  // instructions. Offsets smaller than 2048 can fit in a single load/store
1209  // instruction, and we have to stick with the stack alignment. 2048 has
1210  // 16-byte alignment. The stack alignment for RV32 and RV64 is 16 and for
1211  // RV32E it is 4. So (2048 - StackAlign) will satisfy the stack alignment.
1212  return 2048 - getStackAlign().value();
1213  }
1214  return 0;
1215 }
1216 
1219  ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
1220  if (CSI.empty())
1221  return true;
1222 
1223  MachineFunction *MF = MBB.getParent();
1224  const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
1225  DebugLoc DL;
1226  if (MI != MBB.end() && !MI->isDebugInstr())
1227  DL = MI->getDebugLoc();
1228 
1229  const char *SpillLibCall = getSpillLibCallName(*MF, CSI);
1230  if (SpillLibCall) {
1231  // Add spill libcall via non-callee-saved register t0.
1232  BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoCALLReg), RISCV::X5)
1233  .addExternalSymbol(SpillLibCall, RISCVII::MO_CALL)
1235 
1236  // Add registers spilled in libcall as liveins.
1237  for (auto &CS : CSI)
1238  MBB.addLiveIn(CS.getReg());
1239  }
1240 
1241  // Manually spill values not spilled by libcall.
1242  const auto &NonLibcallCSI = getNonLibcallCSI(*MF, CSI);
1243  for (auto &CS : NonLibcallCSI) {
1244  // Insert the spill to the stack frame.
1245  Register Reg = CS.getReg();
1247  TII.storeRegToStackSlot(MBB, MI, Reg, !MBB.isLiveIn(Reg), CS.getFrameIdx(),
1248  RC, TRI);
1249  }
1250 
1251  return true;
1252 }
1253 
1257  if (CSI.empty())
1258  return true;
1259 
1260  MachineFunction *MF = MBB.getParent();
1261  const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
1262  DebugLoc DL;
1263  if (MI != MBB.end() && !MI->isDebugInstr())
1264  DL = MI->getDebugLoc();
1265 
1266  // Manually restore values not restored by libcall.
1267  // Keep the same order as in the prologue. There is no need to reverse the
1268  // order in the epilogue. In addition, the return address will be restored
1269  // first in the epilogue. It increases the opportunity to avoid the
1270  // load-to-use data hazard between loading RA and return by RA.
1271  // loadRegFromStackSlot can insert multiple instructions.
1272  const auto &NonLibcallCSI = getNonLibcallCSI(*MF, CSI);
1273  for (auto &CS : NonLibcallCSI) {
1274  Register Reg = CS.getReg();
1276  TII.loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI);
1277  assert(MI != MBB.begin() && "loadRegFromStackSlot didn't insert any code!");
1278  }
1279 
1280  const char *RestoreLibCall = getRestoreLibCallName(*MF, CSI);
1281  if (RestoreLibCall) {
1282  // Add restore libcall via tail call.
1284  BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoTAIL))
1285  .addExternalSymbol(RestoreLibCall, RISCVII::MO_CALL)
1287 
1288  // Remove trailing returns, since the terminator is now a tail call to the
1289  // restore function.
1290  if (MI != MBB.end() && MI->getOpcode() == RISCV::PseudoRET) {
1291  NewMI->copyImplicitOps(*MF, *MI);
1292  MI->eraseFromParent();
1293  }
1294  }
1295 
1296  return true;
1297 }
1298 
1300  // Keep the conventional code flow when not optimizing.
1301  if (MF.getFunction().hasOptNone())
1302  return false;
1303 
1304  return true;
1305 }
1306 
1308  MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
1309  const MachineFunction *MF = MBB.getParent();
1310  const auto *RVFI = MF->getInfo<RISCVMachineFunctionInfo>();
1311 
1312  if (!RVFI->useSaveRestoreLibCalls(*MF))
1313  return true;
1314 
1315  // Inserting a call to a __riscv_save libcall requires the use of the register
1316  // t0 (X5) to hold the return address. Therefore if this register is already
1317  // used we can't insert the call.
1318 
1319  RegScavenger RS;
1320  RS.enterBasicBlock(*TmpMBB);
1321  return !RS.isRegUsed(RISCV::X5);
1322 }
1323 
1325  const MachineFunction *MF = MBB.getParent();
1326  MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
1327  const auto *RVFI = MF->getInfo<RISCVMachineFunctionInfo>();
1328 
1329  if (!RVFI->useSaveRestoreLibCalls(*MF))
1330  return true;
1331 
1332  // Using the __riscv_restore libcalls to restore CSRs requires a tail call.
1333  // This means if we still need to continue executing code within this function
1334  // the restore cannot take place in this basic block.
1335 
1336  if (MBB.succ_size() > 1)
1337  return false;
1338 
1339  MachineBasicBlock *SuccMBB =
1340  MBB.succ_empty() ? TmpMBB->getFallThrough() : *MBB.succ_begin();
1341 
1342  // Doing a tail call should be safe if there are no successors, because either
1343  // we have a returning block or the end of the block is unreachable, so the
1344  // restore will be eliminated regardless.
1345  if (!SuccMBB)
1346  return true;
1347 
1348  // The successor can only contain a return, since we would effectively be
1349  // replacing the successor with our own tail return at the end of our block.
1350  return SuccMBB->isReturnBlock() && SuccMBB->size() == 1;
1351 }
1352 
1354  switch (ID) {
1357  return true;
1361  return false;
1362  }
1363  llvm_unreachable("Invalid TargetStackID::Value");
1364 }
1365 
1368 }
llvm::ISD::SUB
@ SUB
Definition: ISDOpcodes.h:240
i
i
Definition: README.txt:29
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:156
getSpillLibCallName
static const char * getSpillLibCallName(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
Definition: RISCVFrameLowering.cpp:174
llvm::MachineFrameInfo::isMaxCallFrameSizeComputed
bool isMaxCallFrameSizeComputed() const
Definition: MachineFrameInfo.h:661
llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:355
llvm::MachineBasicBlock::succ_size
unsigned succ_size() const
Definition: MachineBasicBlock.h:381
llvm::RISCVAttrs::StackAlign
StackAlign
Definition: RISCVAttributes.h:37
MCDwarf.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm::MachineFrameInfo::estimateStackSize
uint64_t estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
Definition: MachineFrameInfo.cpp:137
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::TargetStackID::WasmLocal
@ WasmLocal
Definition: TargetFrameLowering.h:31
llvm::none_of
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1723
llvm::MachineBasicBlock::isLiveIn
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
Definition: MachineBasicBlock.cpp:591
llvm::RISCVFrameLowering::spillCalleeSavedRegisters
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
Definition: RISCVFrameLowering.cpp:1217
llvm::CalleeSavedInfo::getReg
Register getReg() const
Definition: MachineFrameInfo.h:61
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:156
llvm::DiagnosticInfoUnsupported
Diagnostic information for unsupported feature in backend.
Definition: DiagnosticInfo.h:1008
llvm::Function::hasOptNone
bool hasOptNone() const
Do not optimize this function (-O0).
Definition: Function.h:639
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:344
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:95
llvm::Register::id
unsigned id() const
Definition: Register.h:111
llvm::MachineInstrBuilder::addCFIIndex
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
Definition: MachineInstrBuilder.h:247
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::RISCVRegisterInfo
Definition: RISCVRegisterInfo.h:23
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::RISCVSubtarget::isRegisterReservedByUser
bool isRegisterReservedByUser(Register i) const
Definition: RISCVSubtarget.h:235
llvm::RISCVSubtarget::hasVInstructions
bool hasVInstructions() const
Definition: RISCVSubtarget.h:243
llvm::RISCVSubtarget::getRealMaxVLen
unsigned getRealMaxVLen() const
Definition: RISCVSubtarget.h:230
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::RISCVII::MO_CALL
@ MO_CALL
Definition: RISCVBaseInfo.h:205
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:44
llvm::MachineFrameInfo::getOffsetAdjustment
int getOffsetAdjustment() const
Return the correction for frame offsets.
Definition: MachineFrameInfo.h:594
llvm::MachineBasicBlock::isReturnBlock
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction.
Definition: MachineBasicBlock.h:864
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:127
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
getRestoreLibCallName
static const char * getRestoreLibCallName(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
Definition: RISCVFrameLowering.cpp:201
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:321
llvm::StackOffset::getFixed
ScalarTy getFixed() const
Definition: TypeSize.h:149
llvm::RISCVFrameLowering::hasReservedCallFrame
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
Definition: RISCVFrameLowering.cpp:1146
llvm::MachineFrameInfo::setStackSize
void setStackSize(uint64_t Size)
Set the size of the stack.
Definition: MachineFrameInfo.h:588
llvm::RISCVFrameLowering::getFrameIndexReference
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
Definition: RISCVFrameLowering.cpp:702
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::MachineFrameInfo::getObjectIndexEnd
int getObjectIndexEnd() const
Return one past the maximum frame object index.
Definition: MachineFrameInfo.h:410
getFPReg
static Register getFPReg(const RISCVSubtarget &STI)
Definition: RISCVFrameLowering.cpp:348
llvm::RISCVABI::getBPReg
MCRegister getBPReg()
Definition: RISCVBaseInfo.cpp:88
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::MachineFrameInfo::getMaxCallFrameSize
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
Definition: MachineFrameInfo.h:654
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:159
llvm::RISCVFrameLowering::emitPrologue
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
Definition: RISCVFrameLowering.cpp:410
llvm::MCCFIInstruction::cfiDefCfaOffset
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:546
MachineRegisterInfo.h
llvm::MachineInstr::FrameDestroy
@ FrameDestroy
Definition: MachineInstr.h:86
llvm::RegScavenger::isRegUsed
bool isRegUsed(Register Reg, bool includeReserved=true) const
Return if a specific register is currently used.
Definition: RegisterScavenging.cpp:260
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1314
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:667
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::TargetFrameLowering::getOffsetOfLocalArea
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
Definition: TargetFrameLowering.h:140
llvm::MutableArrayRef
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:28
llvm::RISCVFrameLowering::STI
const RISCVSubtarget & STI
Definition: RISCVFrameLowering.h:77
estimateFunctionSizeInBytes
static unsigned estimateFunctionSizeInBytes(const MachineFunction &MF, const RISCVInstrInfo &TII)
Definition: RISCVFrameLowering.cpp:1038
llvm::MachineFrameInfo::ensureMaxAlignment
void ensureMaxAlignment(Align Alignment)
Make sure the function is at least Align bytes aligned.
Definition: MachineFrameInfo.cpp:31
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:755
llvm::TargetFrameLowering::getStackAlign
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:100
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:930
llvm::Log2
unsigned Log2(Align A)
Returns the log2 of the alignment.
Definition: Alignment.h:209
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::RISCVFrameLowering::canUseAsPrologue
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a prologue for the target.
Definition: RISCVFrameLowering.cpp:1307
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::MachineInstr::FrameSetup
@ FrameSetup
Definition: MachineInstr.h:84
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
llvm::MachineFrameInfo::getStackID
uint8_t getStackID(int ObjectIdx) const
Definition: MachineFrameInfo.h:731
llvm::RISCVABI::getSCSPReg
MCRegister getSCSPReg()
Definition: RISCVBaseInfo.cpp:91
llvm::MachineFrameInfo::getStackSize
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
Definition: MachineFrameInfo.h:585
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:526
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::RISCVFrameLowering::getFirstSPAdjustAmount
uint64_t getFirstSPAdjustAmount(const MachineFunction &MF) const
Definition: RISCVFrameLowering.cpp:1191
llvm::BitVector
Definition: BitVector.h:75
llvm::RISCVSubtarget::getInstrInfo
const RISCVInstrInfo * getInstrInfo() const override
Definition: RISCVSubtarget.h:140
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::StackOffset::getScalable
ScalarTy getScalable() const
Definition: TypeSize.h:150
llvm::MachineFrameInfo::isFixedObjectIndex
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Definition: MachineFrameInfo.h:688
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::RISCVSubtarget::getRealMinVLen
unsigned getRealMinVLen() const
Definition: RISCVSubtarget.h:226
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:184
getScavSlotsNumForRVV
static unsigned getScavSlotsNumForRVV(MachineFunction &MF)
Definition: RISCVFrameLowering.cpp:975
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::RISCVFrameLowering::enableShrinkWrapping
bool enableShrinkWrapping(const MachineFunction &MF) const override
Returns true if the target will correctly handle shrink wrapping.
Definition: RISCVFrameLowering.cpp:1299
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::RISCVSubtarget::hasStdExtC
bool hasStdExtC() const
Definition: RISCVSubtarget.h:162
llvm::MachineFrameInfo::isDeadObjectIndex
bool isDeadObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a dead object.
Definition: MachineFrameInfo.h:745
llvm::TargetOptions::DisableFramePointerElim
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
Definition: TargetOptionsImpl.cpp:23
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:657
llvm::MachineInstrBuilder::setMIFlag
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
Definition: MachineInstrBuilder.h:278
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:629
llvm::TargetFrameLowering::alignSPAdjust
int alignSPAdjust(int SPAdj) const
alignSPAdjust - This method aligns the stack adjustment to the correct alignment.
Definition: TargetFrameLowering.h:105
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:416
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:470
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:238
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::HexagonInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index.
Definition: HexagonInstrInfo.cpp:955
llvm::RISCVFrameLowering::getStackSizeWithRVVPadding
uint64_t getStackSizeWithRVVPadding(const MachineFunction &MF) const
Definition: RISCVFrameLowering.cpp:285
llvm::TargetRegisterInfo::getFrameRegister
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
llvm::MachineRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
Definition: MachineRegisterInfo.cpp:623
emitSCSPrologue
static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL)
Definition: RISCVFrameLowering.cpp:30
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:484
llvm::MachineFrameInfo::setObjectOffset
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
Definition: MachineFrameInfo.h:560
llvm::TargetStackID::ScalableVector
@ ScalableVector
Definition: TargetFrameLowering.h:30
llvm::RISCVMachineFunctionInfo
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
Definition: RISCVMachineFunctionInfo.h:47
llvm::MachineBasicBlock::getLastNonDebugInstr
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
Definition: MachineBasicBlock.cpp:264
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
llvm::MachineInstr::NoFlags
@ NoFlags
Definition: MachineInstr.h:83
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:118
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineBasicBlock::size
unsigned size() const
Definition: MachineBasicBlock.h:275
llvm::RISCVFrameLowering::eliminateCallFramePseudoInstr
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
Definition: RISCVFrameLowering.cpp:1152
llvm::MachineBasicBlock::succ_begin
succ_iterator succ_begin()
Definition: MachineBasicBlock.h:369
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:673
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:261
llvm::RegScavenger::addScavengingFrameIndex
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
Definition: RegisterScavenging.h:143
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:532
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineInstr::MIFlag
MIFlag
Definition: MachineInstr.h:82
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1690
llvm::MachineBasicBlock::succ_empty
bool succ_empty() const
Definition: MachineBasicBlock.h:384
llvm::MachineFrameInfo::getCalleeSavedInfo
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
Definition: MachineFrameInfo.h:787
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:239
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::RISCVInstrInfo
Definition: RISCVInstrInfo.h:44
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Definition: MachineFrameInfo.cpp:51
llvm::HexagonInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index.
Definition: HexagonInstrInfo.cpp:1000
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::RISCVSubtarget::getRegisterInfo
const RISCVRegisterInfo * getRegisterInfo() const override
Definition: RISCVSubtarget.h:141
llvm::TargetStackID::NoAlloc
@ NoAlloc
Definition: TargetFrameLowering.h:32
hasRVVFrameObject
static bool hasRVVFrameObject(const MachineFunction &MF)
Definition: RISCVFrameLowering.cpp:1019
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::RISCVFrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Definition: RISCVFrameLowering.cpp:229
emitSCSEpilogue
static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL)
Definition: RISCVFrameLowering.cpp:81
llvm::RISCVFrameLowering::processFunctionBeforeFrameFinalized
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
Definition: RISCVFrameLowering.cpp:1076
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MachineFrameInfo::getMaxAlign
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Definition: MachineFrameInfo.h:601
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineFunction::addFrameInst
unsigned addFrameInst(const MCCFIInstruction &Inst)
Definition: MachineFunction.cpp:310
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:404
llvm::MachineFrameInfo::isFrameAddressTaken
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
Definition: MachineFrameInfo.h:371
llvm::RegScavenger::enterBasicBlock
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
Definition: RegisterScavenging.cpp:82
llvm::MachineFrameInfo::hasCalls
bool hasCalls() const
Return true if the current function has any function calls.
Definition: MachineFrameInfo.h:613
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::LLVMContext::diagnose
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
Definition: LLVMContext.cpp:248
llvm::CallingConv::GHC
@ GHC
Used by the Glasgow Haskell Compiler (GHC).
Definition: CallingConv.h:50
llvm::RISCVFrameLowering::emitEpilogue
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
Definition: RISCVFrameLowering.cpp:614
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:623
llvm::CalleeSavedInfo
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
Definition: MachineFrameInfo.h:34
uint16_t
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:653
MachineFrameInfo.h
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::RISCVFrameLowering::restoreCalleeSavedRegisters
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
Definition: RISCVFrameLowering.cpp:1254
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
DiagnosticInfo.h
llvm::RISCV::isRVVSpill
bool isRVVSpill(const MachineInstr &MI)
Definition: RISCVInstrInfo.cpp:2398
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::RISCVSubtarget::getXLen
unsigned getXLen() const
Definition: RISCVSubtarget.h:212
llvm::TargetStackID::Default
@ Default
Definition: TargetFrameLowering.h:28
llvm::TargetStackID::SGPRSpill
@ SGPRSpill
Definition: TargetFrameLowering.h:29
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
llvm::MachineBasicBlock::getFallThrough
MachineBasicBlock * getFallThrough()
Return the fallthrough block if the block can implicitly transfer control to the block after it by fa...
Definition: MachineBasicBlock.cpp:937
RISCVSubtarget.h
llvm::TargetRegisterInfo::hasStackRealignment
bool hasStackRealignment(const MachineFunction &MF) const
True if stack realignment is required and still possible.
Definition: TargetRegisterInfo.h:968
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:106
getLibCallID
static int getLibCallID(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
Definition: RISCVFrameLowering.cpp:135
llvm::RISCVFrameLowering::getStackIDForScalableVectors
TargetStackID::Value getStackIDForScalableVectors() const override
Returns the StackID that scalable vectors should be associated with.
Definition: RISCVFrameLowering.cpp:1366
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:305
MachineInstrBuilder.h
getSPReg
static Register getSPReg(const RISCVSubtarget &STI)
Definition: RISCVFrameLowering.cpp:351
RISCVFrameLowering.h
RISCVMachineFunctionInfo.h
llvm::RISCVFrameLowering::canUseAsEpilogue
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
Definition: RISCVFrameLowering.cpp:1324
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:277
llvm::MCCFIInstruction::createOffset
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:570
llvm::TargetFrameLowering::determineCalleeSaves
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Definition: TargetFrameLoweringImpl.cpp:83
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineFrameInfo::adjustsStack
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
Definition: MachineFrameInfo.h:609
llvm::RISCVFrameLowering::isSupportedStackID
bool isSupportedStackID(TargetStackID::Value ID) const override
Definition: RISCVFrameLowering.cpp:1353
llvm::TargetRegisterInfo::getMinimalPhysRegClass
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:212
RegisterScavenging.h
llvm::RISCVFrameLowering::hasBP
bool hasBP(const MachineFunction &MF) const
Definition: RISCVFrameLowering.cpp:238
llvm::RISCVFrameLowering::determineCalleeSaves
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Definition: RISCVFrameLowering.cpp:876
MachineFunction.h
llvm::MachineInstrBundleIterator
MachineBasicBlock iterator that automatically skips over MIs that are inside bundles (i....
Definition: MachineInstrBundleIterator.h:108
llvm::RISCVSubtarget::hasStdExtF
bool hasStdExtF() const
Definition: RISCVSubtarget.h:160
llvm::offsetToAlignment
uint64_t offsetToAlignment(uint64_t Value, Align Alignment)
Returns the offset to the next integer (mod 2**64) that is greater than or equal to Value and is a mu...
Definition: Alignment.h:198
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:307
getNonLibcallCSI
static SmallVector< CalleeSavedInfo, 8 > getNonLibcallCSI(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
Definition: RISCVFrameLowering.cpp:354
llvm::StackOffset::get
static StackOffset get(ScalarTy Fixed, ScalarTy Scalable)
Definition: TypeSize.h:145