31 RISCV::X1, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19,
32 RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24,
33 RISCV::X25, RISCV::X26, RISCV::X27};
57 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
58 int64_t SlotSize = STI.getXLen() / 8;
75 char DwarfSCSReg =
TRI->getDwarfRegNum(SCSPReg,
true);
76 assert(DwarfSCSReg < 32 &&
"SCS Register should be < 32 (X3).");
78 char Offset =
static_cast<char>(-SlotSize) & 0x7f;
79 const char CFIInst[] = {
80 dwarf::DW_CFA_val_expression,
83 static_cast<char>(
unsigned(dwarf::DW_OP_breg0 + DwarfSCSReg)),
88 nullptr,
StringRef(CFIInst,
sizeof(CFIInst))));
101 Register RAReg = STI.getRegisterInfo()->getRARegister();
112 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
113 int64_t SlotSize = STI.getXLen() / 8;
129 nullptr, STI.getRegisterInfo()->getDwarfRegNum(SCSPReg,
true)));
140 const std::vector<CalleeSavedInfo> &CSI) {
143 if (CSI.empty() || !RVFI->useSaveRestoreLibCalls(MF))
146 Register MaxReg = RISCV::NoRegister;
150 if (CS.getFrameIdx() < 0)
151 MaxReg = std::max(MaxReg.
id(), CS.getReg().id());
153 if (MaxReg == RISCV::NoRegister)
159 case RISCV::X27:
return 12;
160 case RISCV::X26:
return 11;
161 case RISCV::X25:
return 10;
162 case RISCV::X24:
return 9;
163 case RISCV::X23:
return 8;
164 case RISCV::X22:
return 7;
165 case RISCV::X21:
return 6;
166 case RISCV::X20:
return 5;
167 case RISCV::X19:
return 4;
168 case RISCV::X18:
return 3;
169 case RISCV::X9:
return 2;
170 case RISCV::X8:
return 1;
171 case RISCV::X1:
return 0;
179 const std::vector<CalleeSavedInfo> &CSI) {
180 static const char *
const SpillLibCalls[] = {
199 return SpillLibCalls[LibCallID];
206 const std::vector<CalleeSavedInfo> &CSI) {
207 static const char *
const RestoreLibCalls[] = {
218 "__riscv_restore_10",
219 "__riscv_restore_11",
226 return RestoreLibCalls[LibCallID];
231static std::pair<unsigned, unsigned>
266 const std::vector<CalleeSavedInfo> &CSI) {
267 Register MaxPushPopReg = RISCV::NoRegister;
268 for (
auto &CS : CSI) {
271 if (CS.getFrameIdx() < 0)
272 MaxPushPopReg = std::max(MaxPushPopReg.
id(), CS.getReg().id());
275 if (MaxPushPopReg == RISCV::X26)
276 MaxPushPopReg = RISCV::X27;
277 return MaxPushPopReg;
304 TRI->hasStackRealignment(MF);
308void RISCVFrameLowering::determineFrameLayout(
MachineFunction &MF)
const {
319 FrameSize =
alignTo(FrameSize, StackAlign);
329 if (RVFI->getRVVStackSize() && (!
hasFP(MF) ||
TRI->hasStackRealignment(MF))) {
330 int ScalarLocalVarSize = FrameSize - RVFI->getCalleeSavedStackSize() -
331 RVFI->getVarArgsSaveSize();
332 if (
auto RVVPadding =
334 RVFI->setRVVPadding(RVVPadding);
355 const std::vector<CalleeSavedInfo> &CSI) {
359 for (
auto &CS : CSI) {
360 int FI = CS.getFrameIdx();
365 return NonLibcallCSI;
373 assert(Amount != 0 &&
"Did not need to adjust stack pointer for RVV.");
383 "Reserve the stack by the multiple of one vector size.");
384 const int64_t NumOfVReg = Amount / 8;
385 const int64_t FixedOffset = NumOfVReg * VLENB;
386 if (!isInt<32>(FixedOffset)) {
388 "Frame size outside of the signed 32-bit range not supported");
404 assert(ScalableOffset != 0 &&
"Did not need to adjust CFA for RVV");
406 std::string CommentBuffer;
409 unsigned DwarfReg =
TRI.getDwarfRegNum(Reg,
true);
410 Expr.
push_back((uint8_t)(dwarf::DW_OP_breg0 + DwarfReg));
412 if (Reg == RISCV::X2)
421 Expr.
push_back((uint8_t)dwarf::DW_OP_plus);
422 Comment <<
" + " << FixedOffset;
425 Expr.
push_back((uint8_t)dwarf::DW_OP_consts);
428 unsigned DwarfVlenb =
TRI.getDwarfRegNum(RISCV::VLENB,
true);
429 Expr.
push_back((uint8_t)dwarf::DW_OP_bregx);
433 Expr.
push_back((uint8_t)dwarf::DW_OP_mul);
434 Expr.
push_back((uint8_t)dwarf::DW_OP_plus);
436 Comment <<
" + " << ScalableOffset <<
" * vlenb";
439 DefCfaExpr.
push_back(dwarf::DW_CFA_def_cfa_expression);
471 auto FirstFrameSetup =
MBBI;
479 determineFrameLayout(MF);
503 RVFI->setLibCallStackSize(LibCallFrameSize);
509 uint64_t RealStackSize = StackSize + RVFI->getReservedSpillsSize();
510 uint64_t RVVStackSize = RVFI->getRVVStackSize();
513 if (RealStackSize == 0 && !MFI.
adjustsStack() && RVVStackSize == 0)
520 MF.
getFunction(),
"Stack pointer required, but has been reserved."});
524 if (FirstSPAdjustAmount) {
525 StackSize = FirstSPAdjustAmount;
526 RealStackSize = FirstSPAdjustAmount;
529 if (RVFI->isPushable(MF) && FirstFrameSetup->getOpcode() == RISCV::CM_PUSH) {
533 FirstFrameSetup->getOperand(1).setImm(Spimm);
537 if (StackSize != 0) {
539 RI->adjustReg(
MBB,
MBBI,
DL, SPReg, SPReg,
563 for (
const auto &Entry : CSI) {
564 int FrameIdx = Entry.getFrameIdx();
569 if (RVFI->isPushable(MF)) {
571 Offset = -(FrameIdx + RVFI->getRVPushRegs() + 1) *
581 nullptr, RI->getDwarfRegNum(Reg,
true),
Offset));
591 MF.
getFunction(),
"Frame pointer required, but has been reserved."});
595 RI->adjustReg(
MBB,
MBBI,
DL, FPReg, SPReg,
601 nullptr, RI->getDwarfRegNum(FPReg,
true), RVFI->getVarArgsSaveSize()));
608 if (FirstSPAdjustAmount) {
611 assert(SecondSPAdjustAmount > 0 &&
612 "SecondSPAdjustAmount should be greater than zero");
613 RI->adjustReg(
MBB,
MBBI,
DL, SPReg, SPReg,
630 adjustStackForRVV(MF,
MBB,
MBBI,
DL, -RVVStackSize,
645 if (RI->hasStackRealignment(MF)) {
649 if (isInt<12>(-(
int)MaxAlignment.
value())) {
655 unsigned ShiftAmount =
Log2(MaxAlignment);
717 auto LastFrameDestroy =
MBBI;
719 LastFrameDestroy = std::prev(
MBBI, CSI.
size());
722 uint64_t RealStackSize = StackSize + RVFI->getReservedSpillsSize();
723 uint64_t FPOffset = RealStackSize - RVFI->getVarArgsSaveSize();
724 uint64_t RVVStackSize = RVFI->getRVVStackSize();
738 assert(
hasFP(MF) &&
"frame pointer should not have been eliminated");
744 adjustStackForRVV(MF,
MBB, LastFrameDestroy,
DL, RVVStackSize,
749 if (FirstSPAdjustAmount) {
752 assert(SecondSPAdjustAmount > 0 &&
753 "SecondSPAdjustAmount should be greater than zero");
760 if (FirstSPAdjustAmount)
761 StackSize = FirstSPAdjustAmount;
763 if (RVFI->isPushable(MF) &&
MBBI !=
MBB.
end() &&
764 MBBI->getOpcode() == RISCV::CM_POP) {
768 MBBI->getOperand(1).setImm(Spimm);
773 if (StackSize != 0) {
800 "Unexpected stack ID for the frame object.");
812 MinCSFI = CSI[0].getFrameIdx();
813 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
816 if (FI >= MinCSFI && FI <= MaxCSFI) {
817 FrameReg = RISCV::X2;
819 if (FirstSPAdjustAmount)
864 FrameReg = RISCV::X2;
891 "Can't index across variable sized realign");
896 "Inconsistent stack layout");
939 "Can't index across variable sized realign");
941 RVFI->getReservedSpillsSize(),
942 RVFI->getRVVStackSize());
950 RVFI->getCalleeSavedStackSize() -
951 RVFI->getRVPushStackSize() -
952 RVFI->getVarArgsSaveSize() + RVFI->getRVVPadding();
965 SavedRegs.
set(RISCV::X1);
966 SavedRegs.
set(RISCV::X8);
979 static const MCPhysReg CSRegs[] = { RISCV::X1,
980 RISCV::X5, RISCV::X6, RISCV::X7,
981 RISCV::X10, RISCV::X11,
982 RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17,
983 RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, 0
986 for (
unsigned i = 0; CSRegs[i]; ++i)
987 SavedRegs.
set(CSRegs[i]);
994 for (
unsigned i = 0; Regs[i]; ++i)
995 if (RISCV::FPR16RegClass.
contains(Regs[i]) ||
996 RISCV::FPR32RegClass.
contains(Regs[i]) ||
997 RISCV::FPR64RegClass.
contains(Regs[i]))
998 SavedRegs.
set(Regs[i]);
1003std::pair<int64_t, Align>
1004RISCVFrameLowering::assignRVVStackObjectOffsets(
MachineFunction &MF)
const {
1019 Align RVVStackAlign(16);
1022 if (!ST.hasVInstructions()) {
1024 "Can't allocate scalable-vector objects without V instructions");
1025 return std::make_pair(0, RVVStackAlign);
1030 for (
int FI : ObjectsToAllocate) {
1041 RVVStackAlign = std::max(RVVStackAlign, ObjectAlign);
1049 StackSize += AlignmentPadding;
1050 for (
int FI : ObjectsToAllocate)
1054 return std::make_pair(StackSize, RVVStackAlign);
1060 static constexpr unsigned ScavSlotsNumRVVSpillScalableObject = 2;
1064 static constexpr unsigned ScavSlotsNumRVVSpillNonScalableObject = 1;
1068 static constexpr unsigned ScavSlotsADDIScalableObject = 1;
1070 static constexpr unsigned MaxScavSlotsNumKnown =
1071 std::max({ScavSlotsADDIScalableObject, ScavSlotsNumRVVSpillScalableObject,
1072 ScavSlotsNumRVVSpillNonScalableObject});
1074 unsigned MaxScavSlotsNum = 0;
1080 for (
auto &MO :
MI.operands()) {
1086 MaxScavSlotsNum = std::max(
1087 MaxScavSlotsNum, IsScalableVectorID
1088 ? ScavSlotsNumRVVSpillScalableObject
1089 : ScavSlotsNumRVVSpillNonScalableObject);
1090 }
else if (
MI.getOpcode() == RISCV::ADDI && IsScalableVectorID) {
1092 std::max(MaxScavSlotsNum, ScavSlotsADDIScalableObject);
1095 if (MaxScavSlotsNum == MaxScavSlotsNumKnown)
1096 return MaxScavSlotsNumKnown;
1098 return MaxScavSlotsNum;
1122 unsigned FnSize = 0;
1123 for (
auto &
MBB : MF) {
1124 for (
auto &
MI :
MBB) {
1142 if (
MI.isConditionalBranch())
1143 FnSize +=
TII.getInstSizeInBytes(
MI);
1144 if (
MI.isConditionalBranch() ||
MI.isUnconditionalBranch()) {
1146 FnSize += 2 + 8 + 2 + 2;
1148 FnSize += 4 + 8 + 4 + 4;
1152 FnSize +=
TII.getInstSizeInBytes(
MI);
1167 int64_t RVVStackSize;
1168 Align RVVStackAlign;
1169 std::tie(RVVStackSize, RVVStackAlign) = assignRVVStackObjectOffsets(MF);
1171 RVFI->setRVVStackSize(RVVStackSize);
1172 RVFI->setRVVStackAlign(RVVStackAlign);
1181 unsigned ScavSlotsNum = 0;
1191 if (IsLargeFunction)
1192 ScavSlotsNum = std::max(ScavSlotsNum, 1u);
1199 for (
unsigned I = 0;
I < ScavSlotsNum;
I++) {
1201 RegInfo->getSpillAlign(*RC),
false);
1204 if (IsLargeFunction && RVFI->getBranchRelaxationScratchFrameIndex() == -1)
1205 RVFI->setBranchRelaxationScratchFrameIndex(FI);
1209 RVFI->isPushable(MF)) {
1210 RVFI->setCalleeSavedStackSize(0);
1216 int FrameIdx =
Info.getFrameIdx();
1222 RVFI->setCalleeSavedStackSize(
Size);
1247 int64_t Amount =
MI->getOperand(0).getImm();
1253 if (
MI->getOpcode() == RISCV::ADJCALLSTACKDOWN)
1286 if (RVFI->getReservedSpillsSize())
1291 if (!isInt<12>(StackSize) && (CSI.size() > 0)) {
1321 auto CanCompress = [&](
uint64_t CompressLen) ->
bool {
1322 if (StackSize <= 2047 + CompressLen ||
1323 (StackSize > 2048 * 2 - StackAlign &&
1324 StackSize <= 2047 * 2 + CompressLen) ||
1325 StackSize > 2048 * 3 - StackAlign)
1333 const uint64_t ADDI16SPCompressLen = 496;
1334 if (
STI.
is64Bit() && CanCompress(ADDI16SPCompressLen))
1335 return ADDI16SPCompressLen;
1336 if (CanCompress(RVCompressLen))
1337 return RVCompressLen;
1339 return 2048 - StackAlign;
1354 DL =
MI->getDebugLoc();
1360 if (MaxReg != RISCV::NoRegister) {
1370 PushBuilder.
addImm((int64_t)RegEnc);
1373 for (
unsigned i = 0; i < PushedRegNum; i++)
1383 for (
auto &CS : CSI)
1389 for (
auto &CS : UnmanagedCSI) {
1410 DL =
MI->getDebugLoc();
1419 for (
auto &CS : UnmanagedCSI) {
1424 assert(
MI !=
MBB.
begin() &&
"loadRegFromStackSlot didn't insert any code!");
1435 PopBuilder.
addImm(RegEnc);
1443 if (RestoreLibCall) {
1452 if (
MI !=
MBB.
end() &&
MI->getOpcode() == RISCV::PseudoRET) {
1453 NewMI->copyImplicitOps(*MF, *
MI);
1454 MI->eraseFromParent();
1474 if (!RVFI->useSaveRestoreLibCalls(*MF))
1491 if (!RVFI->useSaveRestoreLibCalls(*MF))
static MCCFIInstruction createDefCFAExpression(const TargetRegisterInfo &TRI, unsigned Reg, const StackOffset &Offset)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
static Register getFPReg(const CSKYSubtarget &STI)
This file contains constants used for implementing Dwarf debug support.
const HexagonInstrInfo * TII
static uint64_t estimateFunctionSizeInBytes(const LoongArchInstrInfo *TII, const MachineFunction &MF)
unsigned const TargetRegisterInfo * TRI
static const char * getRestoreLibCallName(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
static const char * getSpillLibCallName(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
static bool hasRVVFrameObject(const MachineFunction &MF)
static const Register AllPopRegs[]
static std::pair< unsigned, unsigned > getPushPopEncodingAndNum(const Register MaxReg)
static int getLibCallID(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
static Register getSPReg(const RISCVSubtarget &STI)
static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL)
static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL)
static SmallVector< CalleeSavedInfo, 8 > getUnmanagedCSI(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
static Register getMaxPushPopReg(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
static unsigned getScavSlotsNumForRVV(MachineFunction &MF)
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool empty() const
empty - Check if the array is empty.
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
Diagnostic information for unsupported feature in backend.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
bool hasOptNone() const
Do not optimize this function (-O0).
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Store the specified register of the given register class to the specified stack frame index.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Load the specified register of the given register class from the specified stack frame index.
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset, SMLoc Loc={})
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int Offset, SMLoc Loc={})
.cfi_def_cfa_offset modifies a rule for computing CFA.
static MCCFIInstruction createRestore(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_restore says that the rule for Register is now the same as it was at the beginning of the functi...
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset, SMLoc Loc={})
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
static MCCFIInstruction createEscape(MCSymbol *L, StringRef Vals, SMLoc Loc={}, StringRef Comment="")
.cfi_escape Allows the user to add arbitrary bytes to the unwind info.
MachineBasicBlock * getFallThrough(bool JumpToFallThrough=true)
Return the fallthrough block if the block can implicitly transfer control to the block after it by fa...
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
succ_iterator succ_begin()
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
unsigned succ_size() const
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
void ensureMaxAlignment(Align Alignment)
Make sure the function is at least Align bytes aligned.
bool hasCalls() const
Return true if the current function has any function calls.
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
uint64_t estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
int getOffsetAdjustment() const
Return the correction for frame offsets.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool isMaxCallFrameSizeComputed() const
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
int getObjectIndexEnd() const
Return one past the maximum frame object index.
uint8_t getStackID(int ObjectIdx) const
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
void setStackSize(uint64_t Size)
Set the size of the stack.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
bool isDeadObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a dead object.
unsigned addFrameInst(const MCCFIInstruction &Inst)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
uint64_t getFirstSPAdjustAmount(const MachineFunction &MF) const
bool enableShrinkWrapping(const MachineFunction &MF) const override
Returns true if the target will correctly handle shrink wrapping.
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
bool hasBP(const MachineFunction &MF) const
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
const RISCVSubtarget & STI
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
bool isSupportedStackID(TargetStackID::Value ID) const override
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
TargetStackID::Value getStackIDForScalableVectors() const override
Returns the StackID that scalable vectors should be associated with.
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a prologue for the target.
uint64_t getStackSizeWithRVVPadding(const MachineFunction &MF) const
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
bool isPushable(const MachineFunction &MF) const
void setRVPushStackSize(unsigned Size)
int getRVPushRlist() const
unsigned getRVPushRegs() const
void setRVPushRlist(int Rlist)
void setRVPushRegs(unsigned Regs)
bool hasStdExtCOrZca() const
unsigned getRealMinVLen() const
bool isRegisterReservedByUser(Register i) const
bool hasVInstructions() const
unsigned getRealMaxVLen() const
const RISCVRegisterInfo * getRegisterInfo() const override
const RISCVInstrInfo * getInstrInfo() const override
bool isRegUsed(Register Reg, bool includeReserved=true) const
Return if a specific register is currently used.
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
Wrapper class representing virtual and physical registers.
constexpr unsigned id() const
Represents a location in source code.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
void append(StringRef RHS)
Append from a StringRef.
StringRef str() const
Explicit conversion to StringRef.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StackOffset holds a fixed and a scalable offset in bytes.
int64_t getFixed() const
Returns the fixed component of the stack.
int64_t getScalable() const
Returns the scalable component of the stack.
static StackOffset get(int64_t Fixed, int64_t Scalable)
StringRef - Represent a constant reference to a string, i.e.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
int alignSPAdjust(int SPAdj) const
alignSPAdjust - This method aligns the stack adjustment to the correct alignment.
TargetInstrInfo - Interface to description of machine instruction set.
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool hasStackRealignment(const MachineFunction &MF) const
True if stack realignment is required and still possible.
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
A raw_ostream that writes to an std::string.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ GHC
Used by the Glasgow Haskell Compiler (GHC).
bool isRVVSpill(const MachineInstr &MI)
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Define
Register definition.
This is an optimization pass for GlobalISel generic memory operations.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
uint64_t offsetToAlignment(uint64_t Value, Align Alignment)
Returns the offset to the next integer (mod 2**64) that is greater than or equal to Value and is a mu...
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
unsigned encodeSLEB128(int64_t Value, raw_ostream &OS, unsigned PadTo=0)
Utility function to encode a SLEB128 value to an output stream.
unsigned encodeULEB128(uint64_t Value, raw_ostream &OS, unsigned PadTo=0)
Utility function to encode a ULEB128 value to an output stream.
unsigned Log2(Align A)
Returns the log2 of the alignment.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.
void adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg, Register SrcReg, StackOffset Offset, MachineInstr::MIFlag Flag, MaybeAlign RequiredAlign) const