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RISCVBaseInfo.h
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1//===-- RISCVBaseInfo.h - Top level definitions for RISC-V MC ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone enum definitions for the RISC-V target
10// useful for the compiler back-end and the MC libraries.
11//
12//===----------------------------------------------------------------------===//
13#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15
17#include "llvm/ADT/APFloat.h"
18#include "llvm/ADT/APInt.h"
19#include "llvm/ADT/StringRef.h"
21#include "llvm/MC/MCInstrDesc.h"
24
25namespace llvm {
26
27// RISCVII - This namespace holds all of the target specific flags that
28// instruction info tracks. All definitions must match RISCVInstrFormats.td.
29namespace RISCVII {
30enum {
54
57
63
66
67 // Force a tail agnostic policy even this instruction has a tied destination.
70
71 // Is this a _TIED vector pseudo instruction. For these instructions we
72 // shouldn't skip the tied operand when converting to MC instructions.
75
76 // Does this instruction have a SEW operand. It will be the last explicit
77 // operand unless there is a vector policy operand. Used by RVV Pseudos.
80
81 // Does this instruction have a VL operand. It will be the second to last
82 // explicit operand unless there is a vector policy operand. Used by RVV
83 // Pseudos.
86
87 // Does this instruction have a vector policy operand. It will be the last
88 // explicit operand. Used by RVV Pseudos.
91
92 // Is this instruction a vector widening reduction instruction. Used by RVV
93 // Pseudos.
96
97 // Does this instruction care about mask policy. If it is not, the mask policy
98 // could be either agnostic or undisturbed. For example, unmasked, store, and
99 // reduction operations result would not be affected by mask policy, so
100 // compiler has free to select either one.
103
104 // Indicates that the result can be considered sign extended from bit 31. Some
105 // instructions with this flag aren't W instructions, but are either sign
106 // extended from a smaller size, always outputs a small integer, or put zeros
107 // in bits 63:31. Used by the SExtWRemoval pass.
110
113
116};
117
118enum VLMUL : uint8_t {
126 LMUL_F2
128
129enum {
133};
134
135// Helper functions to read TSFlags.
136/// \returns the format of the instruction.
137static inline unsigned getFormat(uint64_t TSFlags) {
139}
140/// \returns the LMUL for the instruction.
142 return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
143}
144/// \returns true if tail agnostic is enforced for the instruction.
147}
148/// \returns true if this a _TIED pseudo.
149static inline bool isTiedPseudo(uint64_t TSFlags) {
150 return TSFlags & IsTiedPseudoMask;
151}
152/// \returns true if there is a SEW operand for the instruction.
153static inline bool hasSEWOp(uint64_t TSFlags) {
154 return TSFlags & HasSEWOpMask;
155}
156/// \returns true if there is a VL operand for the instruction.
157static inline bool hasVLOp(uint64_t TSFlags) {
158 return TSFlags & HasVLOpMask;
159}
160/// \returns true if there is a vector policy operand for this instruction.
161static inline bool hasVecPolicyOp(uint64_t TSFlags) {
163}
164/// \returns true if it is a vector widening reduction instruction.
167}
168/// \returns true if mask policy is valid for the instruction.
169static inline bool usesMaskPolicy(uint64_t TSFlags) {
171}
172
173/// \returns true if there is a rounding mode operand for this instruction
174static inline bool hasRoundModeOp(uint64_t TSFlags) {
176}
177
178/// \returns true if this instruction uses vxrm
179static inline bool usesVXRM(uint64_t TSFlags) { return TSFlags & UsesVXRMMask; }
180
181static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
182 const uint64_t TSFlags = Desc.TSFlags;
183 // This method is only called if we expect to have a VL operand, and all
184 // instructions with VL also have SEW.
186 unsigned Offset = 2;
188 Offset = 3;
189 return Desc.getNumOperands() - Offset;
190}
191
192static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) {
193 const uint64_t TSFlags = Desc.TSFlags;
195 unsigned Offset = 1;
197 Offset = 2;
198 return Desc.getNumOperands() - Offset;
199}
200
201static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) {
202 assert(hasVecPolicyOp(Desc.TSFlags));
203 return Desc.getNumOperands() - 1;
204}
205
206/// \returns the index to the rounding mode immediate value if any, otherwise
207/// returns -1.
208static inline int getFRMOpNum(const MCInstrDesc &Desc) {
209 const uint64_t TSFlags = Desc.TSFlags;
211 return -1;
212
213 // The operand order
214 // --------------------------------------
215 // | n-1 (if any) | n-2 | n-3 | n-4 |
216 // | policy | sew | vl | frm |
217 // --------------------------------------
218 return getVLOpNum(Desc) - 1;
219}
220
221/// \returns the index to the rounding mode immediate value if any, otherwise
222/// returns -1.
223static inline int getVXRMOpNum(const MCInstrDesc &Desc) {
224 const uint64_t TSFlags = Desc.TSFlags;
226 return -1;
227 // The operand order
228 // --------------------------------------
229 // | n-1 (if any) | n-2 | n-3 | n-4 |
230 // | policy | sew | vl | vxrm |
231 // --------------------------------------
232 return getVLOpNum(Desc) - 1;
233}
234
235// Is the first def operand tied to the first use operand. This is true for
236// vector pseudo instructions that have a merge operand for tail/mask
237// undisturbed. It's also true for vector FMA instructions where one of the
238// operands is also the destination register.
239static inline bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc) {
240 return Desc.getNumDefs() < Desc.getNumOperands() &&
241 Desc.getOperandConstraint(Desc.getNumDefs(), MCOI::TIED_TO) == 0;
242}
243
244// RISC-V Specific Machine Operand Flags
245enum {
249 MO_LO = 3,
250 MO_HI = 4,
259
260 // Used to differentiate between target-specific "direct" flags and "bitmask"
261 // flags. A machine operand can only have one "direct" flag, but can have
262 // multiple "bitmask" flags.
265} // namespace RISCVII
266
267namespace RISCVOp {
268enum OperandType : unsigned {
305 // Operand is either a register or uimm5, this is used by V extension pseudo
306 // instructions to represent a value that be passed as AVL to either vsetvli
307 // or vsetivli.
309};
310} // namespace RISCVOp
311
312// Describes the predecessor/successor bits used in the FENCE instruction.
313namespace RISCVFenceField {
315 I = 8,
316 O = 4,
317 R = 2,
318 W = 1
320}
321
322// Describes the supported floating point rounding mode encodings.
323namespace RISCVFPRndMode {
325 RNE = 0,
326 RTZ = 1,
327 RDN = 2,
328 RUP = 3,
329 RMM = 4,
330 DYN = 7,
331 Invalid
333
335 switch (RndMode) {
336 default:
337 llvm_unreachable("Unknown floating point rounding mode");
339 return "rne";
341 return "rtz";
343 return "rdn";
345 return "rup";
347 return "rmm";
349 return "dyn";
350 }
351}
352
362}
363
364inline static bool isValidRoundingMode(unsigned Mode) {
365 switch (Mode) {
366 default:
367 return false;
374 return true;
375 }
376}
377} // namespace RISCVFPRndMode
378
379//===----------------------------------------------------------------------===//
380// Floating-point Immediates
381//
382
383namespace RISCVLoadFPImm {
384float getFPImm(unsigned Imm);
385
386/// getLoadFPImm - Return a 5-bit binary encoding of the floating-point
387/// immediate value. If the value cannot be represented as a 5-bit binary
388/// encoding, then return -1.
389int getLoadFPImm(APFloat FPImm);
390} // namespace RISCVLoadFPImm
391
392namespace RISCVSysReg {
393struct SysReg {
394 const char *Name;
395 const char *DeprecatedName;
396 unsigned Encoding;
397 // FIXME: add these additional fields when needed.
398 // Privilege Access: Read, Write, Read-Only.
399 // unsigned ReadWrite;
400 // Privilege Mode: User, System or Machine.
401 // unsigned Mode;
402 // Check field name.
403 // unsigned Extra;
404 // Register number without the privilege bits.
405 // unsigned Number;
408
409 bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
410 // Not in 32-bit mode.
411 if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
412 return false;
413 // No required feature associated with the system register.
415 return true;
416 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
417 }
418
419 bool haveVendorRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
420 // Not in 32-bit mode.
421 if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
422 return false;
423 // No required feature associated with the system register.
425 return false;
426 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
427 }
428};
429
430struct SiFiveReg : SysReg {};
431
432#define GET_SysRegsList_DECL
433#define GET_SiFiveRegsList_DECL
434#include "RISCVGenSearchableTables.inc"
435} // end namespace RISCVSysReg
436
437namespace RISCVInsnOpcode {
439 const char *Name;
440 unsigned Value;
441};
442
443#define GET_RISCVOpcodesList_DECL
444#include "RISCVGenSearchableTables.inc"
445} // end namespace RISCVInsnOpcode
446
447namespace RISCVABI {
448
449enum ABI {
460
461// Returns the target ABI, or else a StringError if the requested ABIName is
462// not supported for the given TT and FeatureBits combination.
463ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
464 StringRef ABIName);
465
466ABI getTargetABI(StringRef ABIName);
467
468// Returns the register used to hold the stack pointer after realignment.
470
471// Returns the register holding shadow call stack pointer.
473
474} // namespace RISCVABI
475
476namespace RISCVFeatures {
477
478// Validates if the given combination of features are valid for the target
479// triple. Exits with report_fatal_error if not.
480void validate(const Triple &TT, const FeatureBitset &FeatureBits);
481
483parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
484
485} // namespace RISCVFeatures
486
487namespace RISCVVType {
488// Is this a SEW value that can be encoded into the VTYPE format.
489inline static bool isValidSEW(unsigned SEW) {
490 return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024;
491}
492
493// Is this a LMUL value that can be encoded into the VTYPE format.
494inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
495 return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
496}
497
498unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
499 bool MaskAgnostic);
500
501inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
502 unsigned VLMUL = VType & 0x7;
503 return static_cast<RISCVII::VLMUL>(VLMUL);
504}
505
506// Decode VLMUL into 1,2,4,8 and fractional indicator.
507std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL);
508
509inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) {
510 assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL");
511 unsigned LmulLog2 = Log2_32(LMUL);
512 return static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
513}
514
515inline static unsigned decodeVSEW(unsigned VSEW) {
516 assert(VSEW < 8 && "Unexpected VSEW value");
517 return 1 << (VSEW + 3);
518}
519
520inline static unsigned encodeSEW(unsigned SEW) {
521 assert(isValidSEW(SEW) && "Unexpected SEW value");
522 return Log2_32(SEW) - 3;
523}
524
525inline static unsigned getSEW(unsigned VType) {
526 unsigned VSEW = (VType >> 3) & 0x7;
527 return decodeVSEW(VSEW);
528}
529
530inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
531
532inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
533
534void printVType(unsigned VType, raw_ostream &OS);
535
536unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
537
538} // namespace RISCVVType
539
540namespace RISCVRVC {
541bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
542bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
543} // namespace RISCVRVC
544
545namespace RISCVZC {
547 RA = 4,
558 // note - to include s10, s11 must also be included
561};
562
563inline unsigned encodeRlist(MCRegister EndReg, bool IsRV32E = false) {
564 assert((!IsRV32E || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E");
565 switch (EndReg) {
566 case RISCV::X1:
567 return RLISTENCODE::RA;
568 case RISCV::X8:
569 return RLISTENCODE::RA_S0;
570 case RISCV::X9:
572 case RISCV::X18:
574 case RISCV::X19:
576 case RISCV::X20:
578 case RISCV::X21:
580 case RISCV::X22:
582 case RISCV::X23:
584 case RISCV::X24:
586 case RISCV::X25:
588 case RISCV::X26:
590 case RISCV::X27:
592 default:
593 llvm_unreachable("Undefined input.");
594 }
595}
596
597inline static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64,
598 bool IsEABI) {
600 "{ra, s0-s10} is not supported, s11 must be included.");
601 if (IsEABI)
602 return 16;
603 if (!IsRV64) {
604 switch (RlistVal) {
605 case RLISTENCODE::RA:
609 return 16;
614 return 32;
618 return 48;
620 return 64;
621 }
622 } else {
623 switch (RlistVal) {
624 case RLISTENCODE::RA:
626 return 16;
629 return 32;
632 return 48;
635 return 64;
638 return 80;
640 return 96;
642 return 112;
643 }
644 }
645 llvm_unreachable("Unexpected RlistVal");
646}
647
648inline static bool getSpimm(unsigned RlistVal, unsigned &SpimmVal,
649 int64_t StackAdjustment, bool IsRV64, bool IsEABI) {
650 if (RlistVal == RLISTENCODE::INVALID_RLIST)
651 return false;
652 unsigned stackAdj = getStackAdjBase(RlistVal, IsRV64, IsEABI);
653 SpimmVal = (StackAdjustment - stackAdj) / 16;
654 if (SpimmVal > 3)
655 return false;
656 return true;
657}
658
659void printRlist(unsigned SlistEncode, raw_ostream &OS);
660void printSpimm(int64_t Spimm, raw_ostream &OS);
661} // namespace RISCVZC
662
663} // namespace llvm
664
665#endif
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
IRTranslator LLVM IR MI
bool TailAgnostic
bool MaskAgnostic
RISCVII::VLMUL VLMul
unsigned SEW
uint64_t TSFlags
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Tagged union holding either a T or a Error.
Definition: Error.h:468
Container class for subtarget features.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Generic base class for all target subtargets.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:78
ABI getTargetABI(StringRef ABIName)
ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits, StringRef ABIName)
MCRegister getBPReg()
MCRegister getSCSPReg()
static bool isValidRoundingMode(unsigned Mode)
static RoundingMode stringToRoundingMode(StringRef Str)
static StringRef roundingModeToString(RoundingMode RndMode)
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits)
static unsigned getVecPolicyOpNum(const MCInstrDesc &Desc)
static bool usesMaskPolicy(uint64_t TSFlags)
@ TAIL_UNDISTURBED_MASK_UNDISTURBED
static bool hasRoundModeOp(uint64_t TSFlags)
static bool isTiedPseudo(uint64_t TSFlags)
static unsigned getVLOpNum(const MCInstrDesc &Desc)
static bool doesForceTailAgnostic(uint64_t TSFlags)
static unsigned getFormat(uint64_t TSFlags)
static VLMUL getLMul(uint64_t TSFlags)
static bool hasVLOp(uint64_t TSFlags)
static int getFRMOpNum(const MCInstrDesc &Desc)
static int getVXRMOpNum(const MCInstrDesc &Desc)
static bool hasVecPolicyOp(uint64_t TSFlags)
static bool usesVXRM(uint64_t TSFlags)
@ IsRVVWideningReductionShift
Definition: RISCVBaseInfo.h:94
@ IsRVVWideningReductionMask
Definition: RISCVBaseInfo.h:95
static bool isRVVWideningReduction(uint64_t TSFlags)
static unsigned getSEWOpNum(const MCInstrDesc &Desc)
static bool hasSEWOp(uint64_t TSFlags)
static bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc)
int getLoadFPImm(APFloat FPImm)
getLoadFPImm - Return a 5-bit binary encoding of the floating-point immediate value.
float getFPImm(unsigned Imm)
@ OPERAND_UIMMLOG2XLEN_NONZERO
@ OPERAND_UIMM10_LSB00_NONZERO
@ OPERAND_SIMM10_LSB0000_NONZERO
bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
static bool isTailAgnostic(unsigned VType)
static RISCVII::VLMUL getVLMUL(unsigned VType)
static unsigned decodeVSEW(unsigned VSEW)
std::pair< unsigned, bool > decodeVLMUL(RISCVII::VLMUL VLMUL)
unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul)
static bool isValidLMUL(unsigned LMUL, bool Fractional)
static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional)
static bool isMaskAgnostic(unsigned VType)
static unsigned encodeSEW(unsigned SEW)
static bool isValidSEW(unsigned SEW)
void printVType(unsigned VType, raw_ostream &OS)
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic)
static unsigned getSEW(unsigned VType)
static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64, bool IsEABI)
unsigned encodeRlist(MCRegister EndReg, bool IsRV32E=false)
void printRlist(unsigned SlistEncode, raw_ostream &OS)
static bool getSpimm(unsigned RlistVal, unsigned &SpimmVal, int64_t StackAdjustment, bool IsRV64, bool IsEABI)
void printSpimm(int64_t Spimm, raw_ostream &OS)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:440
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:313
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:264
Description of the encoding of one expression Op.
FeatureBitset FeaturesRequired
bool haveVendorRequiredFeatures(const FeatureBitset &ActiveFeatures) const
bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const