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RISCVBaseInfo.h
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1//===-- RISCVBaseInfo.h - Top level definitions for RISC-V MC ---*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains small standalone enum definitions for the RISC-V target
10// useful for the compiler back-end and the MC libraries.
11//
12//===----------------------------------------------------------------------===//
13#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15
17#include "llvm/ADT/APFloat.h"
18#include "llvm/ADT/APInt.h"
19#include "llvm/ADT/StringRef.h"
21#include "llvm/MC/MCInstrDesc.h"
24
25namespace llvm {
26
27// RISCVII - This namespace holds all of the target specific flags that
28// instruction info tracks. All definitions must match RISCVInstrFormats.td.
29namespace RISCVII {
30enum {
54
57
63
66
67 // Do we need to add a dummy mask op when converting RVV Pseudo to MCInst.
70
71 // Force a tail agnostic policy even this instruction has a tied destination.
74
75 // Does this instruction have a merge operand that must be removed when
76 // converting to MCInst. It will be the first explicit use operand. Used by
77 // RVV Pseudos.
80
81 // Does this instruction have a SEW operand. It will be the last explicit
82 // operand unless there is a vector policy operand. Used by RVV Pseudos.
85
86 // Does this instruction have a VL operand. It will be the second to last
87 // explicit operand unless there is a vector policy operand. Used by RVV
88 // Pseudos.
91
92 // Does this instruction have a vector policy operand. It will be the last
93 // explicit operand. Used by RVV Pseudos.
96
97 // Is this instruction a vector widening reduction instruction. Used by RVV
98 // Pseudos.
101
102 // Does this instruction care about mask policy. If it is not, the mask policy
103 // could be either agnostic or undisturbed. For example, unmasked, store, and
104 // reduction operations result would not be affected by mask policy, so
105 // compiler has free to select either one.
108
109 // Indicates that the result can be considered sign extended from bit 31. Some
110 // instructions with this flag aren't W instructions, but are either sign
111 // extended from a smaller size, always outputs a small integer, or put zeros
112 // in bits 63:31. Used by the SExtWRemoval pass.
115};
116
117enum VLMUL : uint8_t {
125 LMUL_F2
127
128enum {
132};
133
134// Helper functions to read TSFlags.
135/// \returns the format of the instruction.
136static inline unsigned getFormat(uint64_t TSFlags) {
138}
139/// \returns the LMUL for the instruction.
141 return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
142}
143/// \returns true if there is a dummy mask operand for the instruction.
144static inline bool hasDummyMaskOp(uint64_t TSFlags) {
146}
147/// \returns true if tail agnostic is enforced for the instruction.
150}
151/// \returns true if there is a merge operand for the instruction.
152static inline bool hasMergeOp(uint64_t TSFlags) {
153 return TSFlags & HasMergeOpMask;
154}
155/// \returns true if there is a SEW operand for the instruction.
156static inline bool hasSEWOp(uint64_t TSFlags) {
157 return TSFlags & HasSEWOpMask;
158}
159/// \returns true if there is a VL operand for the instruction.
160static inline bool hasVLOp(uint64_t TSFlags) {
161 return TSFlags & HasVLOpMask;
162}
163/// \returns true if there is a vector policy operand for this instruction.
164static inline bool hasVecPolicyOp(uint64_t TSFlags) {
166}
167/// \returns true if it is a vector widening reduction instruction.
170}
171/// \returns true if mask policy is valid for the instruction.
172static inline bool usesMaskPolicy(uint64_t TSFlags) {
174}
175
176static inline unsigned getMergeOpNum(const MCInstrDesc &Desc) {
178 assert(!Desc.isVariadic());
179 return Desc.getNumDefs();
180}
181
182static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
183 const uint64_t TSFlags = Desc.TSFlags;
184 // This method is only called if we expect to have a VL operand, and all
185 // instructions with VL also have SEW.
187 unsigned Offset = 2;
189 Offset = 3;
190 return Desc.getNumOperands() - Offset;
191}
192
193static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) {
194 const uint64_t TSFlags = Desc.TSFlags;
196 unsigned Offset = 1;
198 Offset = 2;
199 return Desc.getNumOperands() - Offset;
200}
201
202static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) {
204 return Desc.getNumOperands() - 1;
205}
206
207// RISC-V Specific Machine Operand Flags
208enum {
212 MO_LO = 3,
213 MO_HI = 4,
222
223 // Used to differentiate between target-specific "direct" flags and "bitmask"
224 // flags. A machine operand can only have one "direct" flag, but can have
225 // multiple "bitmask" flags.
228} // namespace RISCVII
229
230namespace RISCVOp {
231enum OperandType : unsigned {
268 // Operand is either a register or uimm5, this is used by V extension pseudo
269 // instructions to represent a value that be passed as AVL to either vsetvli
270 // or vsetivli.
272};
273} // namespace RISCVOp
274
275// Describes the predecessor/successor bits used in the FENCE instruction.
276namespace RISCVFenceField {
278 I = 8,
279 O = 4,
280 R = 2,
281 W = 1
283}
284
285// Describes the supported floating point rounding mode encodings.
286namespace RISCVFPRndMode {
288 RNE = 0,
289 RTZ = 1,
290 RDN = 2,
291 RUP = 3,
292 RMM = 4,
293 DYN = 7,
294 Invalid
296
298 switch (RndMode) {
299 default:
300 llvm_unreachable("Unknown floating point rounding mode");
302 return "rne";
304 return "rtz";
306 return "rdn";
308 return "rup";
310 return "rmm";
312 return "dyn";
313 }
314}
315
325}
326
327inline static bool isValidRoundingMode(unsigned Mode) {
328 switch (Mode) {
329 default:
330 return false;
337 return true;
338 }
339}
340} // namespace RISCVFPRndMode
341
342//===----------------------------------------------------------------------===//
343// Floating-point Immediates
344//
345
346namespace RISCVLoadFPImm {
347float getFPImm(unsigned Imm);
348
349/// getLoadFPImm - Return a 5-bit binary encoding of the floating-point
350/// immediate value. If the value cannot be represented as a 5-bit binary
351/// encoding, then return -1.
352int getLoadFPImm(APFloat FPImm);
353} // namespace RISCVLoadFPImm
354
355namespace RISCVSysReg {
356struct SysReg {
357 const char *Name;
358 const char *AltName;
359 const char *DeprecatedName;
360 unsigned Encoding;
361 // FIXME: add these additional fields when needed.
362 // Privilege Access: Read, Write, Read-Only.
363 // unsigned ReadWrite;
364 // Privilege Mode: User, System or Machine.
365 // unsigned Mode;
366 // Check field name.
367 // unsigned Extra;
368 // Register number without the privilege bits.
369 // unsigned Number;
372
373 bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
374 // Not in 32-bit mode.
375 if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
376 return false;
377 // No required feature associated with the system register.
379 return true;
380 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
381 }
382};
383
384#define GET_SysRegsList_DECL
385#include "RISCVGenSearchableTables.inc"
386} // end namespace RISCVSysReg
387
388namespace RISCVInsnOpcode {
390 const char *Name;
391 unsigned Value;
392};
393
394#define GET_RISCVOpcodesList_DECL
395#include "RISCVGenSearchableTables.inc"
396} // end namespace RISCVInsnOpcode
397
398namespace RISCVABI {
399
400enum ABI {
411
412// Returns the target ABI, or else a StringError if the requested ABIName is
413// not supported for the given TT and FeatureBits combination.
414ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
415 StringRef ABIName);
416
417ABI getTargetABI(StringRef ABIName);
418
419// Returns the register used to hold the stack pointer after realignment.
421
422// Returns the register holding shadow call stack pointer.
424
425} // namespace RISCVABI
426
427namespace RISCVFeatures {
428
429// Validates if the given combination of features are valid for the target
430// triple. Exits with report_fatal_error if not.
431void validate(const Triple &TT, const FeatureBitset &FeatureBits);
432
434parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
435
436} // namespace RISCVFeatures
437
438namespace RISCVVType {
439// Is this a SEW value that can be encoded into the VTYPE format.
440inline static bool isValidSEW(unsigned SEW) {
441 return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024;
442}
443
444// Is this a LMUL value that can be encoded into the VTYPE format.
445inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
446 return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
447}
448
449unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
450 bool MaskAgnostic);
451
452inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
453 unsigned VLMUL = VType & 0x7;
454 return static_cast<RISCVII::VLMUL>(VLMUL);
455}
456
457// Decode VLMUL into 1,2,4,8 and fractional indicator.
458std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL);
459
460inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) {
461 assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL");
462 unsigned LmulLog2 = Log2_32(LMUL);
463 return static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
464}
465
466inline static unsigned decodeVSEW(unsigned VSEW) {
467 assert(VSEW < 8 && "Unexpected VSEW value");
468 return 1 << (VSEW + 3);
469}
470
471inline static unsigned encodeSEW(unsigned SEW) {
472 assert(isValidSEW(SEW) && "Unexpected SEW value");
473 return Log2_32(SEW) - 3;
474}
475
476inline static unsigned getSEW(unsigned VType) {
477 unsigned VSEW = (VType >> 3) & 0x7;
478 return decodeVSEW(VSEW);
479}
480
481inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
482
483inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
484
485void printVType(unsigned VType, raw_ostream &OS);
486
487unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
488
489} // namespace RISCVVType
490
491namespace RISCVRVC {
492bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
493bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
494} // namespace RISCVRVC
495
496namespace RISCVZC {
498 RA = 4,
509 // note - to include s10, s11 must also be included
512};
513
514inline unsigned encodeRlist(MCRegister EndReg, bool IsRV32E = false) {
515 assert((!IsRV32E || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E");
516 switch (EndReg) {
517 case RISCV::X1:
518 return RLISTENCODE::RA;
519 case RISCV::X8:
520 return RLISTENCODE::RA_S0;
521 case RISCV::X9:
523 case RISCV::X18:
525 case RISCV::X19:
527 case RISCV::X20:
529 case RISCV::X21:
531 case RISCV::X22:
533 case RISCV::X23:
535 case RISCV::X24:
537 case RISCV::X25:
539 case RISCV::X26:
541 case RISCV::X27:
543 default:
544 llvm_unreachable("Undefined input.");
545 }
546}
547
548inline static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64,
549 bool IsEABI) {
551 "{ra, s0-s10} is not supported, s11 must be included.");
552 if (IsEABI)
553 return 16;
554 if (!IsRV64) {
555 switch (RlistVal) {
556 case RLISTENCODE::RA:
560 return 16;
565 return 32;
569 return 48;
571 return 64;
572 }
573 } else {
574 switch (RlistVal) {
575 case RLISTENCODE::RA:
577 return 16;
580 return 32;
583 return 48;
586 return 64;
589 return 80;
591 return 96;
593 return 112;
594 }
595 }
596 llvm_unreachable("Unexpected RlistVal");
597}
598
599inline static bool getSpimm(unsigned RlistVal, unsigned &SpimmVal,
600 int64_t StackAdjustment, bool IsRV64, bool IsEABI) {
601 if (RlistVal == RLISTENCODE::INVALID_RLIST)
602 return false;
603 unsigned stackAdj = getStackAdjBase(RlistVal, IsRV64, IsEABI);
604 SpimmVal = (StackAdjustment - stackAdj) / 16;
605 if (SpimmVal > 3)
606 return false;
607 return true;
608}
609
610void printRlist(unsigned SlistEncode, raw_ostream &OS);
611void printSpimm(int64_t Spimm, raw_ostream &OS);
612} // namespace RISCVZC
613
614} // namespace llvm
615
616#endif
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
IRTranslator LLVM IR MI
RISCVII::VLMUL VLMul
unsigned SEW
bool MaskAgnostic
bool TailAgnostic
uint64_t TSFlags
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Tagged union holding either a T or a Error.
Definition: Error.h:470
Container class for subtarget features.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:237
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:248
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:261
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
Generic base class for all target subtargets.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:78
ABI getTargetABI(StringRef ABIName)
ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits, StringRef ABIName)
MCRegister getBPReg()
MCRegister getSCSPReg()
static bool isValidRoundingMode(unsigned Mode)
static RoundingMode stringToRoundingMode(StringRef Str)
static StringRef roundingModeToString(RoundingMode RndMode)
void validate(const Triple &TT, const FeatureBitset &FeatureBits)
llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits)
static unsigned getVecPolicyOpNum(const MCInstrDesc &Desc)
static bool usesMaskPolicy(uint64_t TSFlags)
static bool hasDummyMaskOp(uint64_t TSFlags)
static bool hasMergeOp(uint64_t TSFlags)
static unsigned getVLOpNum(const MCInstrDesc &Desc)
static bool doesForceTailAgnostic(uint64_t TSFlags)
static unsigned getFormat(uint64_t TSFlags)
static VLMUL getLMul(uint64_t TSFlags)
static bool hasVLOp(uint64_t TSFlags)
@ TAIL_UNDISTURBED_MASK_UNDISTURBED
@ IsRVVWideningReductionShift
Definition: RISCVBaseInfo.h:99
@ IsRVVWideningReductionMask
static bool hasVecPolicyOp(uint64_t TSFlags)
static unsigned getMergeOpNum(const MCInstrDesc &Desc)
static bool isRVVWideningReduction(uint64_t TSFlags)
static unsigned getSEWOpNum(const MCInstrDesc &Desc)
static bool hasSEWOp(uint64_t TSFlags)
int getLoadFPImm(APFloat FPImm)
getLoadFPImm - Return a 5-bit binary encoding of the floating-point immediate value.
float getFPImm(unsigned Imm)
@ OPERAND_UIMMLOG2XLEN_NONZERO
@ OPERAND_UIMM10_LSB00_NONZERO
@ OPERAND_SIMM10_LSB0000_NONZERO
bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
static bool isTailAgnostic(unsigned VType)
static RISCVII::VLMUL getVLMUL(unsigned VType)
static unsigned decodeVSEW(unsigned VSEW)
std::pair< unsigned, bool > decodeVLMUL(RISCVII::VLMUL VLMUL)
unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul)
static bool isValidLMUL(unsigned LMUL, bool Fractional)
static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional)
static bool isMaskAgnostic(unsigned VType)
static unsigned encodeSEW(unsigned SEW)
static bool isValidSEW(unsigned SEW)
void printVType(unsigned VType, raw_ostream &OS)
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic)
static unsigned getSEW(unsigned VType)
static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64, bool IsEABI)
unsigned encodeRlist(MCRegister EndReg, bool IsRV32E=false)
void printRlist(unsigned SlistEncode, raw_ostream &OS)
static bool getSpimm(unsigned RlistVal, unsigned &SpimmVal, int64_t StackAdjustment, bool IsRV64, bool IsEABI)
void printSpimm(int64_t Spimm, raw_ostream &OS)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:382
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:292
FeatureBitset FeaturesRequired
bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const