llvm::MCInst Class Reference

Instances of this class represent a single low-level machine instruction. More...

#include "llvm/MC/MCInst.h"

Public Types
using	iterator = SmallVectorImpl<MCOperand>::iterator
using	const_iterator = SmallVectorImpl<MCOperand>::const_iterator

Public Member Functions
	MCInst ()=default
void	setOpcode (unsigned Op)
unsigned	getOpcode () const
void	setFlags (unsigned F)
unsigned	getFlags () const
void	setLoc (SMLoc loc)
SMLoc	getLoc () const
const MCOperand &	getOperand (unsigned i) const
MCOperand &	getOperand (unsigned i)
unsigned	getNumOperands () const
ArrayRef< MCOperand >	getOperands () const
void	addOperand (const MCOperand Op)
void	setOperands (ArrayRef< MCOperand > Ops)
void	clear ()
void	erase (iterator I)
void	erase (iterator First, iterator Last)
size_t	size () const
iterator	begin ()
const_iterator	begin () const
iterator	end ()
const_iterator	end () const
iterator	insert (iterator I, const MCOperand &Op)
LLVM_ABI void	print (raw_ostream &OS, const MCContext *Ctx=nullptr) const
LLVM_ABI void	dump () const
LLVM_ABI void	dump_pretty (raw_ostream &OS, const MCInstPrinter *Printer=nullptr, StringRef Separator=" ", const MCContext *Ctx=nullptr) const
	Dump the MCInst as prettily as possible using the additional MC structures, if given.
LLVM_ABI void	dump_pretty (raw_ostream &OS, StringRef Name, StringRef Separator=" ", const MCContext *Ctx=nullptr) const

Detailed Description

Instances of this class represent a single low-level machine instruction.

Definition at line 188 of file MCInst.h.

Member Typedef Documentation

const_iterator

using llvm::MCInst::const_iterator = SmallVectorImpl<MCOperand>::const_iterator

Definition at line 221 of file MCInst.h.

iterator

using llvm::MCInst::iterator = SmallVectorImpl<MCOperand>::iterator

Definition at line 220 of file MCInst.h.

Constructor & Destructor Documentation

MCInst()

llvm::MCInst::MCInst ( )

default

Member Function Documentation

addOperand()

void llvm::MCInst::addOperand ( const MCOperand Op )

inline

Definition at line 215 of file MCInst.h.

Referenced by llvm::X86Operand::addAbsMemOperands(), llvm::HexagonMCInstrInfo::addConstExtender(), llvm::X86Operand::addDstIdxOperands(), llvm::X86Operand::addExpr(), XtensaOperand::addExpr(), llvm::X86Operand::addGR16orGR32orGR64Operands(), llvm::X86Operand::addGR32orGR64Operands(), llvm::X86Operand::addMaskPairOperands(), llvm::X86Operand::addMemOffsOperands(), llvm::X86Operand::addMemOperands(), addNegOperand(), addOperand(), addOps(), addOpsFromMDNode(), addOptionalImmOperand(), llvm::X86Operand::addRegOperands(), XtensaOperand::addRegOperands(), llvm::X86Operand::addSrcIdxOperands(), llvm::addStringImm(), llvm::X86Operand::addTILEPairOperands(), convertSSEToAVX(), llvm::HexagonMCShuffler::copyTo(), Decode2RImmInstruction(), Decode2RUSInstruction(), Decode3RImmInstruction(), DecodeACC64DSPRegisterClass(), DecodeAddiur2Simm7(), DecodeAddrMode2IdxInstruction(), DecodeAddrMode3Instruction(), DecodeAddrMode5FP16Operand(), DecodeAddrMode5Operand(), DecodeAddrMode6Operand(), DecodeAddrModeImm12Operand(), DecodeAddSubERegInstruction(), DecodeAddSubImmShift(), DecodeAdrInstruction(), DecodeAFGR64RegisterClass(), DecodeANDI16Imm(), DecodeArmMOVTWInstruction(), DecodeARRegisterClass(), DecodeASRRegsRegisterClass(), decodeB4constOperand(), decodeB4constuOperand(), DecodeBankedReg(), DecodeBFAfterTargetOperand(), DecodeBFLabelOperand(), DecodeBitfieldMaskOperand(), DecodeBitpOperand(), DecodeBranchImmInstruction(), decodeBranchOperand(), DecodeBranchTarget(), DecodeBranchTarget10MM(), DecodeBranchTarget1SImm16(), DecodeBranchTarget21(), DecodeBranchTarget21MM(), DecodeBranchTarget26(), DecodeBranchTarget26MM(), DecodeBranchTarget7MM(), DecodeBranchTargetMM(), DecodeBRRegisterClass(), DecodeCacheeOp_CacheOpR6(), DecodeCacheOp(), DecodeCacheOpMM(), decodeCallOperand(), decodeCallTarget(), DecodeCARRYRegisterClass(), DecodeCCOutOperand(), DecodeCCOutOperand(), DecodeCCRCRegisterClass(), DecodeCCRRegisterClass(), DecodeCCRU6Instruction(), DecodeCFRRegisterClass(), DecodeCLRMGPRRegisterClass(), decodeCLUIImmOperand(), decodeCondBrTarget(), DecodeCOP0RegisterClass(), DecodeCOP2RegisterClass(), DecodeCopMemInstruction(), DecodeCoprocessor(), DecodeCoprocPairRegisterClass(), DecodeCoprocRegsRegisterClass(), DecodeCPSInstruction(), decodeCRBitMOperand(), DecodeCtrRegs64RegisterClass(), DecodeCtrRegsRegisterClass(), DecodeDFPRegsRegisterClass(), decodeDirectBrTarget(), decodeDispRIHashOperand(), decodeDispRIX16Operand(), decodeDispRIXOperand(), decodeDispSPE2Operand(), decodeDispSPE4Operand(), decodeDispSPE8Operand(), DecodeDPairRegisterClass(), DecodeDPairSpacedRegisterClass(), DecodeDPRRegisterClass(), DecodeDREGSRegisterClass(), decodeEntry_Imm12OpValue(), DecodeF128RegisterClass(), DecodeF32RegisterClass(), DecodeFCCRegisterClass(), DecodeFCCRegsRegisterClass(), DecodeFCSRRegisterClass(), DecodeFGR32RegisterClass(), DecodeFGR64RegisterClass(), DecodeFGRCCRegisterClass(), DecodeFixedPointScaleImm32(), DecodeFixedPointScaleImm64(), DecodeFMem(), DecodeFMem2(), DecodeFMem3(), DecodeFMemCop2MMR6(), DecodeFMemCop2R6(), DecodeFMemMMR2(), DecodeFMOVLaneInstruction(), DecodeForVMRSandVMSR(), DecodeFPR128RegisterClass(), DecodeFPR16RegisterClass(), DecodeFPR32CRegisterClass(), DecodeFPR32RegisterClass(), DecodeFPR32RegisterClass(), DecodeFPR32RegisterClass(), DecodeFPR64CRegisterClass(), DecodeFPR64RegisterClass(), DecodeFPR64RegisterClass(), DecodeFPR64RegisterClass(), DecodeFPRegsRegisterClass(), DecodeFPRRegisterClass(), decodeFRMArg(), DecodeFromCyclicRange(), DecodeGPR32RegisterClass(), DecodeGPR32RegisterClass(), DecodeGPR32RegisterClass(), DecodeGPR64RegisterClass(), DecodeGPR64x8ClassRegisterClass(), DecodeGPR8RegisterClass(), DecodeGPRCRegisterClass(), DecodeGPRF16RegisterClass(), DecodeGPRF32RegisterClass(), DecodeGPRMM16MovePRegisterClass(), DecodeGPRMM16RegisterClass(), DecodeGPRMM16ZeroRegisterClass(), DecodeGPRPairCRegisterClass(), DecodeGPRPairnospRegisterClass(), DecodeGPRPairRegisterClass(), DecodeGPRPairRegisterClass(), DecodeGPRPairRegisterClass(), DecodeGPRRegisterClass(), DecodeGPRRegisterClass(), DecodeGPRRegisterClass(), DecodeGPRRegisterClass(), DecodeGPRRegisterClass(), DecodeGPRRegisterClass(), DecodeGPRSeqPairsClassRegisterClass(), DecodeGPRSPRegisterClass(), DecodeGPRspRegisterClass(), DecodeGPRwithAPSR_NZCVnospRegisterClass(), DecodeGPRwithAPSRRegisterClass(), DecodeGPRwithZRRegisterClass(), DecodeGPRX1RegisterClass(), DecodeGPRX1X5RegisterClass(), DecodeGPRX5RegisterClass(), DecodeGRRegsRegisterClass(), DecodeGuestRegs64RegisterClass(), DecodeGuestRegsRegisterClass(), DecodeHI32DSPRegisterClass(), DecodeHINTInstruction(), DecodeHWRegsRegisterClass(), DecodeI32RegisterClass(), DecodeI64RegisterClass(), decodeImm12Operand(), decodeImm1_16Operand(), decodeImm1n_15Operand(), DecodeImm32(), decodeImm32n_95Operand(), decodeImm64n_4nOperand(), decodeImm7_22Operand(), decodeImm8_sh8Operand(), decodeImm8n_7Operand(), decodeImm8Operand(), DecodeImm8OptLsl(), decodeImmFourOperand(), decodeImmShiftOpValue(), decodeImmThreeOperand(), decodeImmZeroOperand(), decodeImmZibiOperand(), DecodeInsSize(), DecodeInstSyncBarrierOption(), DecodeIntPairRegisterClass(), DecodeIntRegsRegisterClass(), DecodeIT(), DecodeIWREGSRegisterClass(), decodeJMPIXImmOperand(), decodeJumpOperand(), DecodeJumpTarget(), DecodeJumpTargetMM(), DecodeJumpTargetXMM(), DecodeL2RUSInstruction(), decodeL32ROperand(), DecodeLASX256RegisterClass(), DecodeLazyLoadStoreMul(), DecodeLD8loRegisterClass(), DecodeLD8RegisterClass(), DecodeLdLImmInstruction(), DecodeLdRLImmInstruction(), decodeLenOperand(), DecodeLi16Imm(), DecodeLO32DSPRegisterClass(), DecodeLoadByte15(), decodeLoadStore(), DecodeLogicalImmInstruction(), DecodeLOLoop(), DecodeLongShiftOperand(), decodeLoopOperand(), decodeLRW16Imm8(), DecodeLSX128RegisterClass(), DecodeMatrixTileListRegisterClass(), DecodeMem(), decodeMem16Operand(), decodeMem32nOperand(), decodeMem32Operand(), decodeMem8Operand(), DecodeMemBarrierOption(), DecodeMemEVA(), DecodeMemExtend(), DecodeMemMMGPImm7Lsl2(), DecodeMemMMImm12(), DecodeMemMMImm16(), DecodeMemMMImm4(), DecodeMemMMImm9(), DecodeMemMMReglistImm4Lsl2(), DecodeMemMMSPImm5Lsl2(), DecodeMemMultipleWritebackInstruction(), decodeMemoryOpValue(), decodeMemri(), DecodeMEMrs9(), DecodemGPRRegisterClass(), DecodeMISCRegisterClass(), DecodeModImmInstruction(), DecodeModImmTiedInstruction(), DecodeModRegsRegisterClass(), DecodeMoveHRegInstruction(), DecodeMoveImmInstruction(), DecodeMovePRegPair(), DecodeMPR128RegisterClass(), DecodeMPR16RegisterClass(), DecodeMPR32RegisterClass(), DecodeMPR64RegisterClass(), DecodeMPR8RegisterClass(), DecodeMPRRegisterClass(), DecodeMQPRRegisterClass(), DecodeMQQPRRegisterClass(), DecodeMQQQQPRRegisterClass(), DecodeMR01RegisterClass(), DecodeMR23RegisterClass(), DecodeMRRegisterClass(), DecodeMRSSystemRegister(), DecodeMSA128BRegisterClass(), DecodeMSA128DRegisterClass(), DecodeMSA128HRegisterClass(), DecodeMSA128Mem(), DecodeMSA128WRegisterClass(), DecodeMSACtrlRegisterClass(), DecodeMSRMask(), DecodeMSRSystemRegister(), DecodeMveAddrModeQ(), DecodeMVEModImmInstruction(), DecodeMVEOverlappingLongShift(), DecodeMVEPairVectorIndexOperand(), DecodeMVEVADCInstruction(), DecodeMVEVCMP(), DecodeMveVCTP(), DecodeMVEVPNOT(), DecodeNegImmOperand(), DecodeNEONComplexLane64Instruction(), decodeOImmOperand(), DecodePairLdStInstruction(), decodePCDBLOperand(), DecodePCRelLabel16(), DecodePCRelLabel19(), DecodePCRelLabel9(), DecodePOOL16BEncodedField(), DecodePostIdxReg(), DecodePowerTwoOperand(), DecodePPR2Mul2RegisterClass(), DecodePredicateOperand(), decodePredicateOperand(), DecodePredNoALOperand(), DecodePrefeOpMM(), DecodePRFMRegInstruction(), DecodePRRegsRegisterClass(), DecodeQFPRegsRegisterClass(), DecodeQPRRegisterClass(), DecodeRegisterClass(), DecodeRegisterClass(), decodeRegisterClass(), decodeRegisterClass(), DecodeRegListOperand(), DecodeRegListOperand16(), DecodeRegSeqOperand(), DecodeRegSeqOperandD1(), DecodeRegSeqOperandD2(), DecodeRegSeqOperandF1(), DecodeRegSeqOperandF2(), decodeRelCondBrTarget13(), decodeRelCondBrTarget7(), DecodeRestrictedFPPredicateOperand(), DecodeRestrictedIPredicateOperand(), DecodeRestrictedSPredicateOperand(), DecodeRestrictedUPredicateOperand(), DecoderForMRRC2AndMCRR2(), decodeRiMemoryValue(), DecodeRRegsRegisterClass(), decodeRrMemoryValue(), decodeRTZArg(), DecodeRUSInstruction(), DecodeSCRRegisterClass(), DecodeSETPANInstruction(), DecodesFPR128RegisterClass(), DecodesFPR32RegisterClass(), DecodesFPR64_VRegisterClass(), DecodesFPR64RegisterClass(), DecodesGPRRegisterClass(), decodeShiftImm(), DecodeShiftRight16Imm(), DecodeShiftRight32Imm(), DecodeShiftRight64Imm(), DecodeShiftRight8Imm(), decodeShimm1_31Operand(), DecodeSignedLdStInstruction(), DecodeSignedOperand(), DecodeSImm(), DecodeSimm18Lsl3(), DecodeSimm19Lsl2(), DecodeSimm23Lsl2(), DecodeSimm9SP(), decodeSImmOperand(), decodeSImmOperand(), decodeSImmOperand(), decodeSImmOperand(), decodeSImmOperand(), decodeSImmOperandAndLslN(), DecodeSImmWithOffsetAndScale(), DecodeSimpleRegisterClass(), DecodeSMESpillFillInstruction(), DecodeSOPwithRS12(), DecodeSOPwithRU6(), DecodeSORegImmOperand(), DecodeSORegMemOperand(), DecodeSORegRegOperand(), DecodeSpecial3LlSc(), decodeSplsValue(), DecodeSPRegisterClass(), DecodeSPRegisterClass(), DecodeSPRRegisterClass(), DecodeSR07RegisterClass(), DecodeSRCRegisterClass(), DecodeSRRegisterClass(), DecodeStLImmInstruction(), DecodeSVCROp(), DecodeSVEIncDecImm(), DecodeSVELogicalImmInstruction(), DecodeSymbolicOperandOff(), DecodeSyncI(), DecodeSyncI_MM(), DecodeSynciR6(), DecodeSyspXzrInstruction(), DecodeSysRegs64RegisterClass(), DecodeSysRegsRegisterClass(), DecodeSystemPStateImm0_15Instruction(), DecodeSystemPStateImm0_1Instruction(), DecodeT2AddrModeImm0_1020s4(), DecodeT2AddrModeImm12(), DecodeT2AddrModeSOReg(), DecodeT2AddSubSPImm(), DecodeT2Adr(), DecodeT2BInstruction(), DecodeT2BROperand(), DecodeT2CPSInstruction(), DecodeT2HintSpaceInstruction(), DecodeT2Imm7(), DecodeT2Imm7S4(), DecodeT2Imm8(), DecodeT2Imm8S4(), DecodeT2LoadLabel(), DecodeT2MOVTWInstruction(), DecodeT2ShifterImmOperand(), DecodeT2SOImm(), DecodetcGPRRegisterClass(), DecodeTestAndBranch(), DecodetGPREvenRegisterClass(), DecodetGPROddRegisterClass(), DecodeThreeAddrSRegInstruction(), DecodeThumbAddrModeIS(), DecodeThumbAddrModePC(), DecodeThumbAddrModeSP(), DecodeThumbAddSpecialReg(), DecodeThumbAddSPImm(), DecodeThumbAddSPReg(), DecodeThumbBCCTargetOperand(), DecodeThumbBLTargetOperand(), DecodeThumbBLXOffset(), DecodeThumbBROperand(), DecodeThumbCmpBROperand(), DecodeThumbCPS(), DecodeTRM2RegisterClass(), DecodeTRM4RegisterClass(), DecodeTRRegisterClass(), DecodeTSBInstruction(), decodeUimm4Operand(), decodeUimm5Operand(), decodeUImmLog2XLenOperand(), decodeUImmOperand(), decodeUImmOperand(), decodeUImmOperand(), decodeUImmOperand(), decodeUImmOperand(), decodeUImmOperandGE(), decodeUImmPlus1Operand(), decodeUImmPlus1OperandGE(), decodeUImmSlistOperand(), DecodeUImmWithOffsetAndScale(), DecodeUnconditionalBranch(), DecodeUnsignedLdStInstruction(), DecodeURRegisterClass(), DecodeV64RegisterClass(), DecodeVCVTD(), DecodeVCVTImmOperand(), DecodeVCVTQ(), DecodeVecShiftLImm(), DecodeVecShiftRImm(), DecodeVLD1DupInstruction(), DecodeVLD1LN(), DecodeVLD2DupInstruction(), DecodeVLD2LN(), DecodeVLD3DupInstruction(), DecodeVLD3LN(), DecodeVLD4DupInstruction(), DecodeVLD4LN(), DecodeVLDInstruction(), DecodeVM512RegisterClass(), decodeVMaskReg(), DecodeVMOVModImmInstruction(), DecodeVMRegisterClass(), DecodeVMV0RegisterClass(), DecodeVPTMaskOperand(), DecodeVRM2RegisterClass(), DecodeVRM4RegisterClass(), DecodeVRM8RegisterClass(), DecodeVRRegisterClass(), DecodeVSCCLRM(), DecodeVSHLMaxInstruction(), decodeVSRpEvenOperands(), DecodeVST1LN(), DecodeVST2LN(), DecodeVST3LN(), DecodeVST4LN(), DecodeVSTInstruction(), DecodeVSTRVLDR_SYSREG(), decodeZcmpRlist(), DecodeZeroImm(), DecodeZK(), DecodeZPR2Mul2RegisterClass(), DecodeZPR4Mul4RegisterClass(), DecodeZPRMul2_MinMax(), DecodeZREGRegisterClass(), DecodeZTRRegisterClass(), llvm::HexagonMCInstrInfo::deriveDuplex(), llvm::HexagonMCInstrInfo::deriveExtender(), EmitBinary(), emitBinary(), emitBSIC(), llvm::MipsTargetELFStreamer::emitDirectiveCpLoad(), llvm::MipsTargetELFStreamer::emitDirectiveCpreturn(), llvm::MipsTargetStreamer::emitII(), llvm::ARMAsmPrinter::emitInstruction(), llvm::HexagonAsmPrinter::emitInstruction(), emitLEASLrri(), emitLEASLzzi(), emitLEAzii(), emitLEAzzi(), llvm::MipsTargetStreamer::emitR(), EmitRDPC(), llvm::MipsTargetStreamer::emitRRIII(), llvm::MipsTargetStreamer::emitRRRX(), llvm::MipsTargetStreamer::emitRRX(), llvm::MipsTargetStreamer::emitRX(), EmitSETHI(), emitSIC(), llvm::HexagonAsmPrinter::EmitSled(), getCompoundInsn(), llvm::ARMInstrInfo::getNop(), llvm::HexagonLowerToMC(), llvm::HexagonAsmPrinter::HexagonProcessInstruction(), llvm::BTFDebug::InstLower(), llvm::AArch64MCInstLower::Lower(), llvm::ARCMCInstLower::Lower(), llvm::BPFMCInstLower::Lower(), llvm::CSKYMCInstLower::Lower(), llvm::LanaiMCInstLower::Lower(), llvm::M68kMCInstLower::Lower(), llvm::MipsMCInstLower::Lower(), llvm::MSP430MCInstLower::Lower(), llvm::XCoreMCInstLower::Lower(), llvm::AMDGPUMCInstLower::lower(), llvm::SPIRVMCInstLower::lower(), llvm::SystemZMCInstLower::lower(), llvm::WebAssemblyMCInstLower::lower(), lowerAlignmentHint(), llvm::LowerARMMachineInstrToMCInst(), llvm::AVRMCInstLower::lowerInstruction(), llvm::lowerLoongArchMachineInstrToMCInst(), llvm::LowerPPCMachineInstrToMCInst(), lowerRISCVVMachineInstrToMCInst(), llvm::AMDGPUMCInstLower::lowerT16D16Helper(), llvm::AMDGPUMCInstLower::lowerT16FmaMixFP16(), llvm::XtensaAsmPrinter::lowerToMCInst(), llvm::LowerVEMachineInstrToMCInst(), makeCombineInst(), llvm::HexagonMCInstrInfo::padEndloop(), llvm::ARMInstPrinter::printInst(), llvm::ARMAsmBackend::relaxInstruction(), llvm::CSKYAsmBackend::relaxInstruction(), llvm::RISCVAsmBackend::relaxInstruction(), translateDstIndex(), translateFPRegister(), translateImmediate(), translateMaskRegister(), translateOperand(), translateRegister(), translateRMMemory(), translateSrcIndex(), and llvm::AMDGPUSymbolizer::tryAddingSymbolicOperand().

begin() [1/2]

iterator llvm::MCInst::begin ( )

inline

Definition at line 227 of file MCInst.h.

Referenced by addOptionalImmOperand(), lookForCompound(), llvm::WebAssemblyMCInstLower::lower(), llvm::Hexagon::PacketIterator::operator++(), llvm::HexagonMCInstrInfo::replaceDuplex(), and llvm::MCFragment::setInst().

begin() [2/2]

const_iterator llvm::MCInst::begin ( ) const

inline

Definition at line 228 of file MCInst.h.

clear()

void llvm::MCInst::clear ( )

inline

Definition at line 223 of file MCInst.h.

Referenced by llvm::HexagonMCShuffler::copyTo(), DecodeL5RInstructionFail(), llvm::MipsTargetELFStreamer::emitDirectiveCpLoad(), llvm::HexagonAsmPrinter::HexagonProcessInstruction(), and translateInstruction().

dump()

LLVM_DUMP_METHOD void MCInst::dump

(

)

const

Definition at line 112 of file MCInst.cpp.

References llvm::dbgs(), LLVM_DUMP_METHOD, and print().

Referenced by llvm::CSKYAsmBackend::relaxInstruction(), and llvm::HexagonMCShuffler::reshuffleTo().

dump_pretty() [1/2]

void MCInst::dump_pretty	(	raw_ostream &	OS,
		const MCInstPrinter *	Printer = nullptr,
		StringRef	Separator = " ",
		const MCContext *	Ctx = nullptr ) const

Dump the MCInst as prettily as possible using the additional MC structures, if given.

Operators are separated by the Separator string.

Definition at line 90 of file MCInst.cpp.

References dump_pretty(), getOpcode(), and Printer.

Referenced by llvm::MCFragment::dump(), and dump_pretty().

dump_pretty() [2/2]

void MCInst::dump_pretty	(	raw_ostream &	OS,
		StringRef	Name,
		StringRef	Separator = " ",
		const MCContext *	Ctx = nullptr ) const

Definition at line 96 of file MCInst.cpp.

References getNumOperands(), getOpcode(), getOperand(), and llvm::MCOperand::print().

end() [1/2]

iterator llvm::MCInst::end ( )

inline

Definition at line 229 of file MCInst.h.

Referenced by DecodeRegListOperand(), lookForCompound(), and llvm::Hexagon::PacketIterator::operator++().

end() [2/2]

const_iterator llvm::MCInst::end ( ) const

inline

Definition at line 230 of file MCInst.h.

erase() [1/2]

void llvm::MCInst::erase ( iterator First, iterator Last )

inline

Definition at line 225 of file MCInst.h.

References llvm::First, and llvm::Last.

erase() [2/2]

void llvm::MCInst::erase ( iterator I )

inline

Definition at line 224 of file MCInst.h.

References I.

Referenced by lookForCompound(), removeRegisterOperands(), and llvm::HexagonMCInstrInfo::replaceDuplex().

getFlags()

unsigned llvm::MCInst::getFlags ( ) const

inline

Definition at line 205 of file MCInst.h.

Referenced by llvm::mca::hashMCInst(), and llvm::MCFragment::setInst().

getLoc()

SMLoc llvm::MCInst::getLoc ( ) const

inline

Definition at line 208 of file MCInst.h.

Referenced by llvm::HexagonMCInstrInfo::addConstExtender(), llvm::HexagonMCInstrInfo::deriveSubInst(), llvm::HexagonShuffler::restrictNoSlot1Store(), and llvm::HexagonShuffler::restrictSlot1AOK().

getNumOperands()

unsigned llvm::MCInst::getNumOperands ( ) const

inline

Definition at line 212 of file MCInst.h.

Referenced by checkLowRegisterList(), llvm::AMDGPUDisassembler::decodeLiteral64Constant(), DecodeT2Adr(), dump_pretty(), llvm::MCStreamer::emitInstruction(), llvm::MipsELFStreamer::emitInstruction(), llvm::HexagonMCELFStreamer::EmitSymbol(), llvm::AMDGPU::AMDGPUMCInstrAnalysis::evaluateBranch(), llvm::X86_MC::X86MCInstrAnalysis::evaluateBranch(), llvm::HexagonMCInstrInfo::getDuplexPossibilties(), llvm::mca::hashMCInst(), llvm::HexagonMCInstrInfo::isOrderedDuplexPair(), llvm::isPartOfGOTToPCRelPair(), listContainsReg(), llvm::M68kMCInstLower::Lower(), llvm::AMDGPUMCInstLower::lower(), LowerLargeShift(), lowerRISCVVMachineInstrToMCInst(), print(), removeRegisterOperands(), ScaleVectorOffset(), llvm::MCFragment::setInst(), llvm::DWARFCFIAnalysis::update(), and llvm::mca::verifyOperands().

getOpcode()

unsigned llvm::MCInst::getOpcode ( ) const

inline

Definition at line 202 of file MCInst.h.

Referenced by checkWriteLane(), llvm::X86_MC::X86MCInstrAnalysis::clearsSuperRegisters(), llvm::TargetSchedModel::computeInstrLatency(), convertSSEToAVX(), llvm::mca::InstrBuilder::createInstruction(), llvm::mca::RISCVInstrumentManager::createInstruments(), cvtVOP3DstOpSelOnly(), DecodeAddrMode2IdxInstruction(), DecodeAddrMode3Instruction(), DecodeAddSubERegInstruction(), DecodeArmMOVTWInstruction(), DecodeAuthLoadInstruction(), DecodeBranchImmInstruction(), decodeBranchOperand(), DecodeCopMemInstruction(), DecodeExclusiveLdStInstruction(), DecodeForVMRSandVMSR(), llvm::AMDGPUDisassembler::decodeLiteral64Constant(), DecodeLogicalImmInstruction(), DecodeLOLoop(), DecodeMem(), DecodeMemEVA(), DecodeMemMMImm12(), DecodeMemMMImm4(), DecodeMemMMImm9(), DecodeMemMMReglistImm4Lsl2(), DecodeMemMultipleWritebackInstruction(), DecodeModImmInstruction(), DecodeMoveImmInstruction(), DecodeMSA128Mem(), DecodeMSRMask(), DecodeMVEModImmInstruction(), DecodeMVEOverlappingLongShift(), DecodePairLdStInstruction(), DecodePCRelLabel19(), DecodePredicateOperand(), DecodePRFMRegInstruction(), DecodeRegListOperand(), DecodeRegListOperand16(), DecoderForMRRC2AndMCRR2(), DecodeSignedLdStInstruction(), DecodeSpecial3LlSc(), DecodeSRRegisterClass(), DecodeSVELogicalImmInstruction(), DecodeT2AddrModeImm12(), DecodeT2AddrModeImm8(), DecodeT2AddrModeSOReg(), DecodeT2LdStPre(), DecodeT2LoadImm12(), DecodeT2LoadImm8(), DecodeT2LoadLabel(), DecodeT2LoadShift(), DecodeT2LoadT(), DecodeT2MOVTWInstruction(), DecodeTBLInstruction(), DecodeThreeAddrSRegInstruction(), DecodeThumbAddSpecialReg(), DecodeThumbAddSPReg(), DecodeTSBInstruction(), DecodeUnsignedLdStInstruction(), DecodeURRegisterClass(), DecodeVCVTImmOperand(), DecodeVLD1DupInstruction(), DecodeVLD2DupInstruction(), DecodeVLDInstruction(), DecodeVMOVModImmInstruction(), llvm::AMDGPUDisassembler::decodeVOPDDstYOp(), DecodeVSCCLRM(), DecodeVSTInstruction(), DecodeVSTRVLDR_SYSREG(), llvm::HexagonMCInstrInfo::deriveSubInst(), dump_pretty(), dump_pretty(), llvm::AsmPrinter::emitFunctionBody(), llvm::HexagonMCELFStreamer::emitInstruction(), llvm::MCObjectStreamer::emitInstruction(), llvm::MipsMCCodeEmitter::encodeInstruction(), llvm::AMDGPU::AMDGPUMCInstrAnalysis::evaluateBranch(), llvm::X86_MC::X86MCInstrAnalysis::evaluateBranch(), llvm::X86_MC::X86MCInstrAnalysis::evaluateMemoryOperandAddress(), getCompoundOp(), llvm::HexagonMCInstrInfo::getDesc(), llvm::HexagonMCInstrInfo::getDuplexCandidateGroup(), llvm::HexagonMCInstrInfo::getDuplexPossibilties(), llvm::X86_MC::X86MCInstrAnalysis::getMemoryOperandRelocationOffset(), llvm::HexagonMCInstrInfo::getName(), llvm::MCSchedModel::getReciprocalThroughput(), getRegisterForMxtrDSP(), llvm::mca::InstrumentManager::getSchedClassID(), llvm::mca::RISCVInstrumentManager::getSchedClassID(), llvm::HexagonMCInstrInfo::getType(), llvm::mca::hashMCInst(), hasShortDelaySlot(), llvm::HexagonMCInstrInfo::hasTmpDst(), llvm::HexagonLowerToMC(), llvm::HexagonAsmPrinter::HexagonProcessInstruction(), instIsBreakpoint(), IsAGPROperand(), llvm::MCInstrAnalysis::isBarrier(), llvm::MCInstrAnalysis::isBranch(), llvm::HexagonMCInstrInfo::isBundle(), llvm::MCInstrAnalysis::isCall(), llvm::MCInstrAnalysis::isConditionalBranch(), llvm::HexagonMCInstrInfo::isConstExtended(), isFirstMacroFusibleInst(), llvm::HexagonMCInstrInfo::isImmext(), llvm::MCInstrAnalysis::isIndirectBranch(), isOrderedCompoundPair(), llvm::HexagonMCInstrInfo::isOrderedDuplexPair(), llvm::isPartOfGOTToPCRelPair(), llvm::MCInstrAnalysis::isReturn(), llvm::HexagonMCInstrInfo::isSolo(), llvm::HexagonMCInstrInfo::isSubInstruction(), llvm::MCInstrAnalysis::isTerminator(), llvm::MCInstrAnalysis::isUnconditionalBranch(), lookForCompound(), llvm::AArch64MCInstLower::Lower(), LowerLargeShift(), lowerRISCVVMachineInstrToMCInst(), llvm::MCInstrAnalysis::mayAffectControlFlow(), PermitsD32(), llvm::mca::AMDGPUInstrPostProcess::postProcessInstruction(), print(), llvm::ARMAsmBackend::relaxInstruction(), llvm::CSKYAsmBackend::relaxInstruction(), llvm::RISCVAsmBackend::relaxInstruction(), removeRegisterOperands(), llvm::HexagonMCInstrInfo::requiresSlot(), ScaleVectorOffset(), llvm::MCFragment::setInst(), llvm::HexagonMCInstrInfo::subInstWouldBeExtended(), translateInstruction(), llvm::WebAssemblyAsmTypeCheck::typeCheck(), llvm::DWARFCFIAnalysis::update(), and llvm::AMDGPU::AMDGPUMCInstrAnalysis::updateState().

getOperand() [1/2]

MCOperand & llvm::MCInst::getOperand ( unsigned i )

inline

Definition at line 211 of file MCInst.h.

getOperand() [2/2]

const MCOperand & llvm::MCInst::getOperand ( unsigned i ) const

inline

Definition at line 210 of file MCInst.h.

Referenced by llvm::HexagonMCInstrInfo::addConstExtender(), addOps(), llvm::adjustPqBits(), checkLowRegisterList(), checkWriteLane(), llvm::X86_MC::X86MCInstrAnalysis::clearsSuperRegisters(), convertSSEToAVX(), llvm::mca::InstrBuilder::createInstruction(), llvm::mca::RISCVInstrumentManager::createInstruments(), cvtVOP3DstOpSelOnly(), DecodeBFAfterTargetOperand(), DecodeInsSize(), DecodeMoveImmInstruction(), DecodeRegListOperand(), llvm::AMDGPUDisassembler::decodeVOPDDstYOp(), llvm::HexagonMCInstrInfo::deriveSubInst(), dump_pretty(), llvm::MCStreamer::emitInstruction(), llvm::MipsELFStreamer::emitInstruction(), llvm::HexagonMCELFStreamer::EmitSymbol(), llvm::AMDGPU::AMDGPUMCInstrAnalysis::evaluateBranch(), llvm::X86_MC::X86MCInstrAnalysis::evaluateBranch(), evaluateMemOpAddrForAddrMode3(), evaluateMemOpAddrForAddrMode5(), evaluateMemOpAddrForAddrMode5FP16(), evaluateMemOpAddrForAddrMode_i12(), evaluateMemOpAddrForAddrModeT2_i8s4(), evaluateMemOpAddrForAddrModeT2_pc(), llvm::X86_MC::X86MCInstrAnalysis::evaluateMemoryOperandAddress(), llvm::HexagonMCInstrInfo::extenderForIndex(), getCompoundOp(), llvm::HexagonMCInstrInfo::getDuplexCandidateGroup(), llvm::HexagonMCInstrInfo::getDuplexPossibilties(), llvm::HexagonMCInstrInfo::getExtendableOperand(), llvm::X86_MC::X86MCInstrAnalysis::getMemoryOperandRelocationOffset(), llvm::HexagonMCInstrInfo::getNewValueOperand(), llvm::HexagonMCInstrInfo::getNewValueOperand2(), getRegisterForMxtrC0(), getRegisterForMxtrDSP(), getRegisterForMxtrFP(), llvm::mca::hashMCInst(), hasShortDelaySlot(), llvm::HexagonAsmPrinter::HexagonProcessInstruction(), llvm::HexagonMCInstrInfo::instruction(), IsAGPROperand(), llvm::HexagonMCInstrInfo::isBundle(), llvm::HexagonMCInstrInfo::isInnerLoop(), llvm::HexagonMCInstrInfo::isMemReorderDisabled(), isOrderedCompoundPair(), llvm::HexagonMCInstrInfo::isOrderedDuplexPair(), llvm::HexagonMCInstrInfo::isOuterLoop(), llvm::isPartOfGOTToPCRelPair(), llvm::HexagonMCInstrInfo::isPredRegister(), listContainsReg(), LowerLargeShift(), llvm::HexagonMCInstrInfo::minConstant(), needsExpandMemInst(), llvm::HexagonMCInstrInfo::predicateInfo(), print(), llvm::CSKYAsmBackend::relaxInstruction(), llvm::RISCVAsmBackend::relaxInstruction(), removeRegisterOperands(), llvm::HexagonMCInstrInfo::replaceDuplex(), ScaleVectorOffset(), llvm::HexagonMCInstrInfo::setInnerLoop(), llvm::HexagonMCInstrInfo::setMemReorderDisabled(), llvm::HexagonMCInstrInfo::setOuterLoop(), llvm::HexagonMCInstrInfo::subInstWouldBeExtended(), llvm::WebAssemblyAsmTypeCheck::typeCheck(), llvm::DWARFCFIAnalysis::update(), llvm::AMDGPU::AMDGPUMCInstrAnalysis::updateState(), and llvm::mca::verifyOperands().

getOperands()

ArrayRef< MCOperand > llvm::MCInst::getOperands ( ) const

inline

Definition at line 214 of file MCInst.h.

Referenced by llvm::MCObjectStreamer::emitInstruction(), and llvm::RISCVAsmBackend::relaxInstruction().

insert()

iterator llvm::MCInst::insert ( iterator I, const MCOperand & Op )

inline

Definition at line 232 of file MCInst.h.

References I.

Referenced by addOptionalImmOperand(), and llvm::WebAssemblyMCInstLower::lower().

print()

void MCInst::print	(	raw_ostream &	OS,
		const MCContext *	Ctx = nullptr ) const

Definition at line 81 of file MCInst.cpp.

References getNumOperands(), getOpcode(), getOperand(), and llvm::MCOperand::print().

Referenced by dump().

setFlags()

void llvm::MCInst::setFlags ( unsigned F )

inline

Definition at line 204 of file MCInst.h.

References F.

Referenced by llvm::MCFragment::getInst(), and llvm::SPIRVMCInstLower::lower().

setLoc()

void llvm::MCInst::setLoc ( SMLoc loc )

inline

Definition at line 207 of file MCInst.h.

Referenced by llvm::HexagonMCInstrInfo::addConstExtender(), llvm::HexagonMCShuffler::copyTo(), llvm::MipsTargetStreamer::emitII(), llvm::MipsTargetStreamer::emitR(), llvm::MipsTargetStreamer::emitRRIII(), llvm::MipsTargetStreamer::emitRRRX(), llvm::MipsTargetStreamer::emitRRX(), and llvm::MipsTargetStreamer::emitRX().

setOpcode()

void llvm::MCInst::setOpcode ( unsigned Op )

inline

Definition at line 201 of file MCInst.h.

Referenced by convertSSEToAVX(), Decode2OpInstructionFail(), DecodeBranchImmInstruction(), DecodeCPSInstruction(), DecodeL2OpInstructionFail(), DecodeL5RInstructionFail(), decodeLoadStore(), DecodeLOLoop(), DecodeMemMultipleWritebackInstruction(), DecodeMVEOverlappingLongShift(), DecodeSETPANInstruction(), DecodeT2AddSubSPImm(), DecodeT2Adr(), DecodeT2CPSInstruction(), DecodeT2HintSpaceInstruction(), DecodeT2LdStPre(), DecodeT2LoadImm12(), DecodeT2LoadImm8(), DecodeT2LoadLabel(), DecodeT2LoadShift(), DecodeT2LoadT(), DecodeThumb2BCCInstruction(), DecodeVCVTD(), DecodeVCVTQ(), llvm::HexagonMCInstrInfo::deriveDuplex(), llvm::HexagonMCInstrInfo::deriveExtender(), llvm::X86AsmPrinter::emitBasicBlockEnd(), EmitBinary(), emitBinary(), emitBSIC(), llvm::MipsTargetELFStreamer::emitDirectiveCpLoad(), llvm::MipsTargetELFStreamer::emitDirectiveCpreturn(), llvm::MipsTargetStreamer::emitII(), llvm::ARMAsmPrinter::emitInstruction(), llvm::HexagonAsmPrinter::emitInstruction(), emitLEASLrri(), emitLEASLzzi(), emitLEAzii(), emitLEAzzi(), llvm::MipsTargetStreamer::emitR(), EmitRDPC(), llvm::MipsTargetStreamer::emitRRIII(), llvm::MipsTargetStreamer::emitRRRX(), llvm::MipsTargetStreamer::emitRRX(), llvm::MipsTargetStreamer::emitRX(), EmitSETHI(), emitSIC(), llvm::HexagonAsmPrinter::EmitSled(), llvm::MipsMCCodeEmitter::encodeInstruction(), getCompoundInsn(), llvm::MCFragment::getInst(), getMIMnemonic(), llvm::ARMInstrInfo::getNop(), llvm::PPCInstrInfo::getNop(), llvm::X86InstrInfo::getNop(), llvm::HexagonLowerToMC(), llvm::HexagonAsmPrinter::HexagonProcessInstruction(), llvm::BTFDebug::InstLower(), llvm::AArch64MCInstLower::Lower(), llvm::ARCMCInstLower::Lower(), llvm::BPFMCInstLower::Lower(), llvm::CSKYMCInstLower::Lower(), llvm::LanaiMCInstLower::Lower(), llvm::M68kMCInstLower::Lower(), llvm::MipsMCInstLower::Lower(), llvm::MSP430MCInstLower::Lower(), llvm::XCoreMCInstLower::Lower(), llvm::AMDGPUMCInstLower::lower(), llvm::SPIRVMCInstLower::lower(), llvm::SystemZMCInstLower::lower(), llvm::WebAssemblyMCInstLower::lower(), lowerAlignmentHint(), llvm::LowerARMMachineInstrToMCInst(), llvm::AVRMCInstLower::lowerInstruction(), LowerLargeShift(), llvm::lowerLoongArchMachineInstrToMCInst(), llvm::LowerPPCMachineInstrToMCInst(), lowerRISCVVMachineInstrToMCInst(), llvm::AMDGPUMCInstLower::lowerT16D16Helper(), llvm::AMDGPUMCInstLower::lowerT16FmaMixFP16(), llvm::XtensaAsmPrinter::lowerToMCInst(), llvm::LowerVEMachineInstrToMCInst(), makeCombineInst(), llvm::HexagonMCInstrInfo::padEndloop(), llvm::ARMInstPrinter::printInst(), llvm::ARMAsmBackend::relaxInstruction(), llvm::CSKYAsmBackend::relaxInstruction(), llvm::RISCVAsmBackend::relaxInstruction(), removeRegisterOperands(), and translateInstruction().

setOperands()

void llvm::MCInst::setOperands ( ArrayRef< MCOperand > Ops )

inline

Definition at line 216 of file MCInst.h.

References AbstractManglingParser< Derived, Alloc >::Ops.

Referenced by llvm::MCFragment::getInst().

size()

size_t llvm::MCInst::size ( ) const

inline

Definition at line 226 of file MCInst.h.

Referenced by llvm::HexagonMCInstrInfo::bundleSize(), llvm::HexagonMCInstrInfo::isBundle(), llvm::HexagonMCInstrInfo::minConstant(), llvm::HexagonMCInstrInfo::replaceDuplex(), and llvm::HexagonMCInstrInfo::tryCompound().

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The documentation for this class was generated from the following files:

• include/llvm/MC/MCInst.h
• lib/MC/MCInst.cpp