LLVM  14.0.0git
RISCVAsmBackend.cpp
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1 //===-- RISCVAsmBackend.cpp - RISCV Assembler Backend ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "RISCVAsmBackend.h"
10 #include "RISCVMCExpr.h"
11 #include "llvm/ADT/APInt.h"
12 #include "llvm/MC/MCAsmInfo.h"
13 #include "llvm/MC/MCAsmLayout.h"
14 #include "llvm/MC/MCAssembler.h"
15 #include "llvm/MC/MCContext.h"
16 #include "llvm/MC/MCDirectives.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCObjectWriter.h"
20 #include "llvm/MC/MCSymbol.h"
21 #include "llvm/MC/MCValue.h"
22 #include "llvm/Support/Endian.h"
25 #include "llvm/Support/LEB128.h"
27 
28 using namespace llvm;
29 
31  if (STI.getTargetTriple().isOSBinFormatELF()) {
32  unsigned Type;
34 #define ELF_RELOC(X, Y) .Case(#X, Y)
35 #include "llvm/BinaryFormat/ELFRelocs/RISCV.def"
36 #undef ELF_RELOC
37  .Case("BFD_RELOC_NONE", ELF::R_RISCV_NONE)
38  .Case("BFD_RELOC_32", ELF::R_RISCV_32)
39  .Case("BFD_RELOC_64", ELF::R_RISCV_64)
40  .Default(-1u);
41  if (Type != -1u)
42  return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
43  }
44  return None;
45 }
46 
47 const MCFixupKindInfo &
49  const static MCFixupKindInfo Infos[] = {
50  // This table *must* be in the order that the fixup_* kinds are defined in
51  // RISCVFixupKinds.h.
52  //
53  // name offset bits flags
54  {"fixup_riscv_hi20", 12, 20, 0},
55  {"fixup_riscv_lo12_i", 20, 12, 0},
56  {"fixup_riscv_lo12_s", 0, 32, 0},
57  {"fixup_riscv_pcrel_hi20", 12, 20,
59  {"fixup_riscv_pcrel_lo12_i", 20, 12,
61  {"fixup_riscv_pcrel_lo12_s", 0, 32,
63  {"fixup_riscv_got_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
64  {"fixup_riscv_tprel_hi20", 12, 20, 0},
65  {"fixup_riscv_tprel_lo12_i", 20, 12, 0},
66  {"fixup_riscv_tprel_lo12_s", 0, 32, 0},
67  {"fixup_riscv_tprel_add", 0, 0, 0},
68  {"fixup_riscv_tls_got_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
69  {"fixup_riscv_tls_gd_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
70  {"fixup_riscv_jal", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
71  {"fixup_riscv_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
72  {"fixup_riscv_rvc_jump", 2, 11, MCFixupKindInfo::FKF_IsPCRel},
73  {"fixup_riscv_rvc_branch", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
74  {"fixup_riscv_call", 0, 64, MCFixupKindInfo::FKF_IsPCRel},
75  {"fixup_riscv_call_plt", 0, 64, MCFixupKindInfo::FKF_IsPCRel},
76  {"fixup_riscv_relax", 0, 0, 0},
77  {"fixup_riscv_align", 0, 0, 0},
78 
79  {"fixup_riscv_set_8", 0, 8, 0},
80  {"fixup_riscv_add_8", 0, 8, 0},
81  {"fixup_riscv_sub_8", 0, 8, 0},
82 
83  {"fixup_riscv_set_16", 0, 16, 0},
84  {"fixup_riscv_add_16", 0, 16, 0},
85  {"fixup_riscv_sub_16", 0, 16, 0},
86 
87  {"fixup_riscv_set_32", 0, 32, 0},
88  {"fixup_riscv_add_32", 0, 32, 0},
89  {"fixup_riscv_sub_32", 0, 32, 0},
90 
91  {"fixup_riscv_add_64", 0, 64, 0},
92  {"fixup_riscv_sub_64", 0, 64, 0},
93 
94  {"fixup_riscv_set_6b", 2, 6, 0},
95  {"fixup_riscv_sub_6b", 2, 6, 0},
96  };
97  static_assert((array_lengthof(Infos)) == RISCV::NumTargetFixupKinds,
98  "Not all fixup kinds added to Infos array");
99 
100  // Fixup kinds from .reloc directive are like R_RISCV_NONE. They
101  // do not require any extra processing.
104 
107 
109  "Invalid kind!");
110  return Infos[Kind - FirstTargetFixupKind];
111 }
112 
113 // If linker relaxation is enabled, or the relax option had previously been
114 // enabled, always emit relocations even if the fixup can be resolved. This is
115 // necessary for correctness as offsets may change during relaxation.
117  const MCFixup &Fixup,
118  const MCValue &Target) {
119  if (Fixup.getKind() >= FirstLiteralRelocationKind)
120  return true;
121  switch (Fixup.getTargetKind()) {
122  default:
123  break;
124  case FK_Data_1:
125  case FK_Data_2:
126  case FK_Data_4:
127  case FK_Data_8:
128  if (Target.isAbsolute())
129  return false;
130  break;
134  return true;
135  }
136 
137  return STI.getFeatureBits()[RISCV::FeatureRelax] || ForceRelocs;
138 }
139 
141  bool Resolved,
142  uint64_t Value,
143  const MCRelaxableFragment *DF,
144  const MCAsmLayout &Layout,
145  const bool WasForced) const {
146  // Return true if the symbol is actually unresolved.
147  // Resolved could be always false when shouldForceRelocation return true.
148  // We use !WasForced to indicate that the symbol is unresolved and not forced
149  // by shouldForceRelocation.
150  if (!Resolved && !WasForced)
151  return true;
152 
153  int64_t Offset = int64_t(Value);
154  switch (Fixup.getTargetKind()) {
155  default:
156  return false;
158  // For compressed branch instructions the immediate must be
159  // in the range [-256, 254].
160  return Offset > 254 || Offset < -256;
162  // For compressed jump instructions the immediate must be
163  // in the range [-2048, 2046].
164  return Offset > 2046 || Offset < -2048;
165  }
166 }
167 
169  const MCSubtargetInfo &STI) const {
170  // TODO: replace this with call to auto generated uncompressinstr() function.
171  MCInst Res;
172  switch (Inst.getOpcode()) {
173  default:
174  llvm_unreachable("Opcode not expected!");
175  case RISCV::C_BEQZ:
176  // c.beqz $rs1, $imm -> beq $rs1, X0, $imm.
177  Res.setOpcode(RISCV::BEQ);
178  Res.addOperand(Inst.getOperand(0));
179  Res.addOperand(MCOperand::createReg(RISCV::X0));
180  Res.addOperand(Inst.getOperand(1));
181  break;
182  case RISCV::C_BNEZ:
183  // c.bnez $rs1, $imm -> bne $rs1, X0, $imm.
184  Res.setOpcode(RISCV::BNE);
185  Res.addOperand(Inst.getOperand(0));
186  Res.addOperand(MCOperand::createReg(RISCV::X0));
187  Res.addOperand(Inst.getOperand(1));
188  break;
189  case RISCV::C_J:
190  // c.j $imm -> jal X0, $imm.
191  Res.setOpcode(RISCV::JAL);
192  Res.addOperand(MCOperand::createReg(RISCV::X0));
193  Res.addOperand(Inst.getOperand(0));
194  break;
195  case RISCV::C_JAL:
196  // c.jal $imm -> jal X1, $imm.
197  Res.setOpcode(RISCV::JAL);
198  Res.addOperand(MCOperand::createReg(RISCV::X1));
199  Res.addOperand(Inst.getOperand(0));
200  break;
201  }
202  Inst = std::move(Res);
203 }
204 
206  MCAsmLayout &Layout,
207  bool &WasRelaxed) const {
208  MCContext &C = Layout.getAssembler().getContext();
209 
210  int64_t LineDelta = DF.getLineDelta();
211  const MCExpr &AddrDelta = DF.getAddrDelta();
212  SmallVectorImpl<char> &Data = DF.getContents();
213  SmallVectorImpl<MCFixup> &Fixups = DF.getFixups();
214  size_t OldSize = Data.size();
215 
216  int64_t Value;
217  bool IsAbsolute = AddrDelta.evaluateKnownAbsolute(Value, Layout);
218  assert(IsAbsolute && "CFA with invalid expression");
219  (void)IsAbsolute;
220 
221  Data.clear();
222  Fixups.clear();
224 
225  // INT64_MAX is a signal that this is actually a DW_LNE_end_sequence.
226  if (LineDelta != INT64_MAX) {
227  OS << uint8_t(dwarf::DW_LNS_advance_line);
228  encodeSLEB128(LineDelta, OS);
229  }
230 
231  unsigned Offset;
232  std::pair<unsigned, unsigned> Fixup;
233 
234  // According to the DWARF specification, the `DW_LNS_fixed_advance_pc` opcode
235  // takes a single unsigned half (unencoded) operand. The maximum encodable
236  // value is therefore 65535. Set a conservative upper bound for relaxation.
237  if (Value > 60000) {
238  unsigned PtrSize = C.getAsmInfo()->getCodePointerSize();
239 
240  OS << uint8_t(dwarf::DW_LNS_extended_op);
241  encodeULEB128(PtrSize + 1, OS);
242 
243  OS << uint8_t(dwarf::DW_LNE_set_address);
244  Offset = OS.tell();
245  Fixup = PtrSize == 4 ? std::make_pair(RISCV::fixup_riscv_add_32,
247  : std::make_pair(RISCV::fixup_riscv_add_64,
249  OS.write_zeros(PtrSize);
250  } else {
251  OS << uint8_t(dwarf::DW_LNS_fixed_advance_pc);
252  Offset = OS.tell();
254  support::endian::write<uint16_t>(OS, 0, support::little);
255  }
256 
257  const MCBinaryExpr &MBE = cast<MCBinaryExpr>(AddrDelta);
258  Fixups.push_back(MCFixup::create(
259  Offset, MBE.getLHS(), static_cast<MCFixupKind>(std::get<0>(Fixup))));
260  Fixups.push_back(MCFixup::create(
261  Offset, MBE.getRHS(), static_cast<MCFixupKind>(std::get<1>(Fixup))));
262 
263  if (LineDelta == INT64_MAX) {
264  OS << uint8_t(dwarf::DW_LNS_extended_op);
265  OS << uint8_t(1);
266  OS << uint8_t(dwarf::DW_LNE_end_sequence);
267  } else {
268  OS << uint8_t(dwarf::DW_LNS_copy);
269  }
270 
271  WasRelaxed = OldSize != Data.size();
272  return true;
273 }
274 
276  MCAsmLayout &Layout,
277  bool &WasRelaxed) const {
278 
279  const MCExpr &AddrDelta = DF.getAddrDelta();
280  SmallVectorImpl<char> &Data = DF.getContents();
281  SmallVectorImpl<MCFixup> &Fixups = DF.getFixups();
282  size_t OldSize = Data.size();
283 
284  int64_t Value;
285  bool IsAbsolute = AddrDelta.evaluateKnownAbsolute(Value, Layout);
286  assert(IsAbsolute && "CFA with invalid expression");
287  (void)IsAbsolute;
288 
289  Data.clear();
290  Fixups.clear();
292 
293  assert(
295  1 &&
296  "expected 1-byte alignment");
297  if (Value == 0) {
298  WasRelaxed = OldSize != Data.size();
299  return true;
300  }
301 
302  auto AddFixups = [&Fixups, &AddrDelta](unsigned Offset,
303  std::pair<unsigned, unsigned> Fixup) {
304  const MCBinaryExpr &MBE = cast<MCBinaryExpr>(AddrDelta);
305  Fixups.push_back(MCFixup::create(
306  Offset, MBE.getLHS(), static_cast<MCFixupKind>(std::get<0>(Fixup))));
307  Fixups.push_back(MCFixup::create(
308  Offset, MBE.getRHS(), static_cast<MCFixupKind>(std::get<1>(Fixup))));
309  };
310 
311  if (isUIntN(6, Value)) {
312  OS << uint8_t(dwarf::DW_CFA_advance_loc);
314  } else if (isUInt<8>(Value)) {
315  OS << uint8_t(dwarf::DW_CFA_advance_loc1);
316  support::endian::write<uint8_t>(OS, 0, support::little);
318  } else if (isUInt<16>(Value)) {
319  OS << uint8_t(dwarf::DW_CFA_advance_loc2);
320  support::endian::write<uint16_t>(OS, 0, support::little);
322  } else if (isUInt<32>(Value)) {
323  OS << uint8_t(dwarf::DW_CFA_advance_loc4);
324  support::endian::write<uint32_t>(OS, 0, support::little);
326  } else {
327  llvm_unreachable("unsupported CFA encoding");
328  }
329 
330  WasRelaxed = OldSize != Data.size();
331  return true;
332 }
333 
334 // Given a compressed control flow instruction this function returns
335 // the expanded instruction.
336 unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const {
337  switch (Op) {
338  default:
339  return Op;
340  case RISCV::C_BEQZ:
341  return RISCV::BEQ;
342  case RISCV::C_BNEZ:
343  return RISCV::BNE;
344  case RISCV::C_J:
345  case RISCV::C_JAL: // fall through.
346  return RISCV::JAL;
347  }
348 }
349 
351  const MCSubtargetInfo &STI) const {
352  return getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode();
353 }
354 
356  const MCSubtargetInfo *STI) const {
357  bool HasStdExtC = STI->getFeatureBits()[RISCV::FeatureStdExtC];
358  unsigned MinNopLen = HasStdExtC ? 2 : 4;
359 
360  if ((Count % MinNopLen) != 0)
361  return false;
362 
363  // The canonical nop on RISC-V is addi x0, x0, 0.
364  for (; Count >= 4; Count -= 4)
365  OS.write("\x13\0\0\0", 4);
366 
367  // The canonical nop on RVC is c.nop.
368  if (Count && HasStdExtC)
369  OS.write("\x01\0", 2);
370 
371  return true;
372 }
373 
375  MCContext &Ctx) {
376  switch (Fixup.getTargetKind()) {
377  default:
378  llvm_unreachable("Unknown fixup kind!");
382  llvm_unreachable("Relocation should be unconditionally forced\n");
394  case FK_Data_1:
395  case FK_Data_2:
396  case FK_Data_4:
397  case FK_Data_8:
398  case FK_Data_6b:
399  return Value;
401  return Value & 0x03;
405  return Value & 0xfff;
409  return (((Value >> 5) & 0x7f) << 25) | ((Value & 0x1f) << 7);
413  // Add 1 if bit 11 is 1, to compensate for low 12 bits being negative.
414  return ((Value + 0x800) >> 12) & 0xfffff;
415  case RISCV::fixup_riscv_jal: {
416  if (!isInt<21>(Value))
417  Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
418  if (Value & 0x1)
419  Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned");
420  // Need to produce imm[19|10:1|11|19:12] from the 21-bit Value.
421  unsigned Sbit = (Value >> 20) & 0x1;
422  unsigned Hi8 = (Value >> 12) & 0xff;
423  unsigned Mid1 = (Value >> 11) & 0x1;
424  unsigned Lo10 = (Value >> 1) & 0x3ff;
425  // Inst{31} = Sbit;
426  // Inst{30-21} = Lo10;
427  // Inst{20} = Mid1;
428  // Inst{19-12} = Hi8;
429  Value = (Sbit << 19) | (Lo10 << 9) | (Mid1 << 8) | Hi8;
430  return Value;
431  }
433  if (!isInt<13>(Value))
434  Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
435  if (Value & 0x1)
436  Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned");
437  // Need to extract imm[12], imm[10:5], imm[4:1], imm[11] from the 13-bit
438  // Value.
439  unsigned Sbit = (Value >> 12) & 0x1;
440  unsigned Hi1 = (Value >> 11) & 0x1;
441  unsigned Mid6 = (Value >> 5) & 0x3f;
442  unsigned Lo4 = (Value >> 1) & 0xf;
443  // Inst{31} = Sbit;
444  // Inst{30-25} = Mid6;
445  // Inst{11-8} = Lo4;
446  // Inst{7} = Hi1;
447  Value = (Sbit << 31) | (Mid6 << 25) | (Lo4 << 8) | (Hi1 << 7);
448  return Value;
449  }
452  // Jalr will add UpperImm with the sign-extended 12-bit LowerImm,
453  // we need to add 0x800ULL before extract upper bits to reflect the
454  // effect of the sign extension.
455  uint64_t UpperImm = (Value + 0x800ULL) & 0xfffff000ULL;
456  uint64_t LowerImm = Value & 0xfffULL;
457  return UpperImm | ((LowerImm << 20) << 32);
458  }
460  // Need to produce offset[11|4|9:8|10|6|7|3:1|5] from the 11-bit Value.
461  unsigned Bit11 = (Value >> 11) & 0x1;
462  unsigned Bit4 = (Value >> 4) & 0x1;
463  unsigned Bit9_8 = (Value >> 8) & 0x3;
464  unsigned Bit10 = (Value >> 10) & 0x1;
465  unsigned Bit6 = (Value >> 6) & 0x1;
466  unsigned Bit7 = (Value >> 7) & 0x1;
467  unsigned Bit3_1 = (Value >> 1) & 0x7;
468  unsigned Bit5 = (Value >> 5) & 0x1;
469  Value = (Bit11 << 10) | (Bit4 << 9) | (Bit9_8 << 7) | (Bit10 << 6) |
470  (Bit6 << 5) | (Bit7 << 4) | (Bit3_1 << 1) | Bit5;
471  return Value;
472  }
474  // Need to produce offset[8|4:3], [reg 3 bit], offset[7:6|2:1|5]
475  unsigned Bit8 = (Value >> 8) & 0x1;
476  unsigned Bit7_6 = (Value >> 6) & 0x3;
477  unsigned Bit5 = (Value >> 5) & 0x1;
478  unsigned Bit4_3 = (Value >> 3) & 0x3;
479  unsigned Bit2_1 = (Value >> 1) & 0x3;
480  Value = (Bit8 << 12) | (Bit4_3 << 10) | (Bit7_6 << 5) | (Bit2_1 << 3) |
481  (Bit5 << 2);
482  return Value;
483  }
484 
485  }
486 }
487 
489  const MCAssembler &Asm, const MCAsmLayout &Layout, const MCFixup &Fixup,
490  const MCFragment *DF, const MCValue &Target, uint64_t &Value,
491  bool &WasForced) {
492  const MCFixup *AUIPCFixup;
493  const MCFragment *AUIPCDF;
494  MCValue AUIPCTarget;
495  switch (Fixup.getTargetKind()) {
496  default:
497  llvm_unreachable("Unexpected fixup kind!");
499  AUIPCFixup = &Fixup;
500  AUIPCDF = DF;
501  AUIPCTarget = Target;
502  break;
505  AUIPCFixup = cast<RISCVMCExpr>(Fixup.getValue())->getPCRelHiFixup(&AUIPCDF);
506  if (!AUIPCFixup) {
507  Asm.getContext().reportError(Fixup.getLoc(),
508  "could not find corresponding %pcrel_hi");
509  return true;
510  }
511 
512  // MCAssembler::evaluateFixup will emit an error for this case when it sees
513  // the %pcrel_hi, so don't duplicate it when also seeing the %pcrel_lo.
514  const MCExpr *AUIPCExpr = AUIPCFixup->getValue();
515  if (!AUIPCExpr->evaluateAsRelocatable(AUIPCTarget, &Layout, AUIPCFixup))
516  return true;
517  break;
518  }
519  }
520 
521  if (!AUIPCTarget.getSymA() || AUIPCTarget.getSymB())
522  return false;
523 
524  const MCSymbolRefExpr *A = AUIPCTarget.getSymA();
525  const MCSymbol &SA = A->getSymbol();
526  if (A->getKind() != MCSymbolRefExpr::VK_None || SA.isUndefined())
527  return false;
528 
529  auto *Writer = Asm.getWriterPtr();
530  if (!Writer)
531  return false;
532 
533  bool IsResolved = Writer->isSymbolRefDifferenceFullyResolvedImpl(
534  Asm, SA, *AUIPCDF, false, true);
535  if (!IsResolved)
536  return false;
537 
538  Value = Layout.getSymbolOffset(SA) + AUIPCTarget.getConstant();
539  Value -= Layout.getFragmentOffset(AUIPCDF) + AUIPCFixup->getOffset();
540 
541  if (shouldForceRelocation(Asm, *AUIPCFixup, AUIPCTarget)) {
542  WasForced = true;
543  return false;
544  }
545 
546  return true;
547 }
548 
550  const MCValue &Target,
552  bool IsResolved,
553  const MCSubtargetInfo *STI) const {
554  MCFixupKind Kind = Fixup.getKind();
556  return;
557  MCContext &Ctx = Asm.getContext();
559  if (!Value)
560  return; // Doesn't change encoding.
561  // Apply any target-specific value adjustments.
563 
564  // Shift the value into position.
565  Value <<= Info.TargetOffset;
566 
567  unsigned Offset = Fixup.getOffset();
568  unsigned NumBytes = alignTo(Info.TargetSize + Info.TargetOffset, 8) / 8;
569 
570  assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
571 
572  // For each byte of the fragment that the fixup touches, mask in the
573  // bits from the fixup value.
574  for (unsigned i = 0; i != NumBytes; ++i) {
575  Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
576  }
577 }
578 
579 // Linker relaxation may change code size. We have to insert Nops
580 // for .align directive when linker relaxation enabled. So then Linker
581 // could satisfy alignment by removing Nops.
582 // The function return the total Nops Size we need to insert.
584  const MCAlignFragment &AF, unsigned &Size) {
585  // Calculate Nops Size only when linker relaxation enabled.
586  if (!STI.getFeatureBits()[RISCV::FeatureRelax])
587  return false;
588 
589  bool HasStdExtC = STI.getFeatureBits()[RISCV::FeatureStdExtC];
590  unsigned MinNopLen = HasStdExtC ? 2 : 4;
591 
592  if (AF.getAlignment() <= MinNopLen) {
593  return false;
594  } else {
595  Size = AF.getAlignment() - MinNopLen;
596  return true;
597  }
598 }
599 
600 // We need to insert R_RISCV_ALIGN relocation type to indicate the
601 // position of Nops and the total bytes of the Nops have been inserted
602 // when linker relaxation enabled.
603 // The function insert fixup_riscv_align fixup which eventually will
604 // transfer to R_RISCV_ALIGN relocation type.
606  const MCAsmLayout &Layout,
607  MCAlignFragment &AF) {
608  // Insert the fixup only when linker relaxation enabled.
609  if (!STI.getFeatureBits()[RISCV::FeatureRelax])
610  return false;
611 
612  // Calculate total Nops we need to insert. If there are none to insert
613  // then simply return.
614  unsigned Count;
615  if (!shouldInsertExtraNopBytesForCodeAlign(AF, Count) || (Count == 0))
616  return false;
617 
618  MCContext &Ctx = Asm.getContext();
619  const MCExpr *Dummy = MCConstantExpr::create(0, Ctx);
620  // Create fixup_riscv_align fixup.
621  MCFixup Fixup =
623 
624  uint64_t FixedValue = 0;
625  MCValue NopBytes = MCValue::get(Count);
626 
627  Asm.getWriter().recordRelocation(Asm, Layout, &AF, Fixup, NopBytes,
628  FixedValue);
629 
630  return true;
631 }
632 
633 std::unique_ptr<MCObjectTargetWriter>
635  return createRISCVELFObjectWriter(OSABI, Is64Bit);
636 }
637 
639  const MCSubtargetInfo &STI,
640  const MCRegisterInfo &MRI,
641  const MCTargetOptions &Options) {
642  const Triple &TT = STI.getTargetTriple();
643  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
644  return new RISCVAsmBackend(STI, OSABI, TT.isArch64Bit(), Options);
645 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:67
i
i
Definition: README.txt:29
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:148
llvm::RISCV::fixup_riscv_pcrel_lo12_i
@ fixup_riscv_pcrel_lo12_i
Definition: RISCVFixupKinds.h:28
llvm::raw_ostream::tell
uint64_t tell() const
tell - Return the current offset with the file.
Definition: raw_ostream.h:135
llvm::RISCV::fixup_riscv_call_plt
@ fixup_riscv_call_plt
Definition: RISCVFixupKinds.h:64
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::MCRelaxableFragment
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:271
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
llvm::MCAsmBackend::getFixupKindInfo
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
Definition: MCAsmBackend.cpp:74
llvm::MCDwarfCallFrameFragment
Definition: MCFragment.h:481
llvm::raw_ostream::write_zeros
raw_ostream & write_zeros(unsigned NumZeros)
write_zeros - Insert 'NumZeros' nulls.
Definition: raw_ostream.cpp:502
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::StringSwitch::Default
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
llvm::MCAsmInfo::getMinInstAlignment
unsigned getMinInstAlignment() const
Definition: MCAsmInfo.h:631
MCDirectives.h
llvm::MCConstantExpr::create
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::FirstTargetFixupKind
@ FirstTargetFixupKind
Definition: MCFixup.h:45
llvm::RISCV::fixup_riscv_tls_gd_hi20
@ fixup_riscv_tls_gd_hi20
Definition: RISCVFixupKinds.h:50
llvm::MCFixup::create
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:87
ErrorHandling.h
llvm::MCSymbol::isUndefined
bool isUndefined(bool SetUsed=true) const
isUndefined - Check if this symbol undefined (i.e., implicitly defined).
Definition: MCSymbol.h:252
llvm::RISCV::fixup_riscv_lo12_s
@ fixup_riscv_lo12_s
Definition: RISCVFixupKinds.h:24
llvm::RISCV::fixup_riscv_call
@ fixup_riscv_call
Definition: RISCVFixupKinds.h:61
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
MCAssembler.h
APInt.h
llvm::RISCVAsmBackend::getFixupKind
Optional< MCFixupKind > getFixupKind(StringRef Name) const override
Map a relocation name used in .reloc to a fixup kind.
Definition: RISCVAsmBackend.cpp:30
llvm::RISCVAsmBackend::getRelaxedOpcode
unsigned getRelaxedOpcode(unsigned Op) const
Definition: RISCVAsmBackend.cpp:336
llvm::RISCV::fixup_riscv_sub_64
@ fixup_riscv_sub_64
Definition: RISCVFixupKinds.h:100
llvm::RISCVAsmBackend::fixupNeedsRelaxationAdvanced
bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout, const bool WasForced) const override
Target specific predicate for whether a given fixup requires the associated instruction to be relaxed...
Definition: RISCVAsmBackend.cpp:140
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::AMDGPU::Exp::Target
Target
Definition: SIDefines.h:739
llvm::Optional
Definition: APInt.h:33
RISCVMCExpr.h
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::RISCV::fixup_riscv_add_32
@ fixup_riscv_add_32
Definition: RISCVFixupKinds.h:91
llvm::MCBinaryExpr
Binary assembler expressions.
Definition: MCExpr.h:480
llvm::Data
@ Data
Definition: SIMachineScheduler.h:55
llvm::RISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign
bool shouldInsertExtraNopBytesForCodeAlign(const MCAlignFragment &AF, unsigned &Size) override
Hook to check if extra nop bytes must be inserted for alignment directive.
Definition: RISCVAsmBackend.cpp:583
llvm::RISCV::fixup_riscv_pcrel_lo12_s
@ fixup_riscv_pcrel_lo12_s
Definition: RISCVFixupKinds.h:31
llvm::MCExpr::evaluateAsRelocatable
bool evaluateAsRelocatable(MCValue &Res, const MCAsmLayout *Layout, const MCFixup *Fixup) const
Try to evaluate the expression to a relocatable value, i.e.
Definition: MCExpr.cpp:747
llvm::MCInst::setOpcode
void setOpcode(unsigned Op)
Definition: MCInst.h:197
llvm::FirstLiteralRelocationKind
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
Definition: MCFixup.h:50
llvm::MCFragment
Definition: MCFragment.h:31
llvm::RISCVAsmBackend::createObjectTargetWriter
std::unique_ptr< MCObjectTargetWriter > createObjectTargetWriter() const override
Definition: RISCVAsmBackend.cpp:634
x3
In x86 we generate this spiffy xmm0 xmm0 ret in x86 we generate this which could be xmm1 movss xmm1 xmm0 ret In sse4 we could use insertps to make both better Here s another testcase that could use x3
Definition: README-SSE.txt:547
llvm::MCFixup::getValue
const MCExpr * getValue() const
Definition: MCFixup.h:105
llvm::FK_Data_4
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
llvm::createRISCVAsmBackend
MCAsmBackend * createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: RISCVAsmBackend.cpp:638
llvm::Triple::isOSBinFormatELF
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:632
llvm::MCAsmBackend
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:36
llvm::FK_Data_6b
@ FK_Data_6b
A six-bits fixup.
Definition: MCFixup.h:27
llvm::MutableArrayRef
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:307
llvm::SMLoc
Represents a location in source code.
Definition: SMLoc.h:23
llvm::RISCV::fixup_riscv_jal
@ fixup_riscv_jal
Definition: RISCVFixupKinds.h:52
llvm::RISCV::fixup_riscv_hi20
@ fixup_riscv_hi20
Definition: RISCVFixupKinds.h:20
llvm::MCAlignFragment
Definition: MCFragment.h:295
llvm::encodeSLEB128
unsigned encodeSLEB128(int64_t Value, raw_ostream &OS, unsigned PadTo=0)
Utility function to encode a SLEB128 value to an output stream.
Definition: LEB128.h:23
llvm::RISCV::fixup_riscv_rvc_jump
@ fixup_riscv_rvc_jump
Definition: RISCVFixupKinds.h:56
llvm::support::little
@ little
Definition: Endian.h:27
llvm::RISCV::fixup_riscv_tls_got_hi20
@ fixup_riscv_tls_got_hi20
Definition: RISCVFixupKinds.h:47
llvm::MCAssembler::getContext
MCContext & getContext() const
Definition: MCAssembler.h:292
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition: MCSubtargetInfo.h:107
MCContext.h
MCSymbol.h
llvm::RISCV::fixup_riscv_lo12_i
@ fixup_riscv_lo12_i
Definition: RISCVFixupKinds.h:22
llvm::MCBinaryExpr::getRHS
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
Definition: MCExpr.h:630
llvm::isUIntN
bool isUIntN(unsigned N, uint64_t x)
Checks if an unsigned integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:455
llvm::AArch64::Fixups
Fixups
Definition: AArch64FixupKinds.h:17
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
llvm::RISCVAsmBackend::getNumFixupKinds
unsigned getNumFixupKinds() const override
Get the number of target specific fixup kinds.
Definition: RISCVAsmBackend.h:82
llvm::RISCV::fixup_riscv_got_hi20
@ fixup_riscv_got_hi20
Definition: RISCVFixupKinds.h:34
llvm::raw_ostream::write
raw_ostream & write(unsigned char C)
Definition: raw_ostream.cpp:220
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::MCValue::getConstant
int64_t getConstant() const
Definition: MCValue.h:44
INT64_MAX
#define INT64_MAX
Definition: DataTypes.h:71
llvm::MCExpr::evaluateKnownAbsolute
bool evaluateKnownAbsolute(int64_t &Res, const MCAsmLayout &Layout) const
Definition: MCExpr.cpp:559
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MCValue::getSymA
const MCSymbolRefExpr * getSymA() const
Definition: MCValue.h:45
llvm::array_lengthof
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1394
llvm::None
const NoneType None
Definition: None.h:23
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
DF
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
llvm::RISCVAsmBackend::relaxDwarfCFA
bool relaxDwarfCFA(MCDwarfCallFrameFragment &DF, MCAsmLayout &Layout, bool &WasRelaxed) const override
Definition: RISCVAsmBackend.cpp:275
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::MCDwarfLineAddrFragment
Definition: MCFragment.h:457
RISCVAsmBackend.h
llvm::RISCVAsmBackend::mayNeedRelaxation
bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const override
Check whether the given instruction may need relaxation.
Definition: RISCVAsmBackend.cpp:350
llvm::RISCV::fixup_riscv_sub_8
@ fixup_riscv_sub_8
Definition: RISCVFixupKinds.h:78
llvm::RISCV::fixup_riscv_branch
@ fixup_riscv_branch
Definition: RISCVFixupKinds.h:54
llvm::MCAssembler
Definition: MCAssembler.h:60
llvm::isUInt< 16 >
constexpr bool isUInt< 16 >(uint64_t x)
Definition: MathExtras.h:408
llvm::RISCVAsmBackend::relaxDwarfLineAddr
bool relaxDwarfLineAddr(MCDwarfLineAddrFragment &DF, MCAsmLayout &Layout, bool &WasRelaxed) const override
Definition: RISCVAsmBackend.cpp:205
uint64_t
llvm::MCContext::getAsmInfo
const MCAsmInfo * getAsmInfo() const
Definition: MCContext.h:423
MCELFObjectWriter.h
llvm::MCValue::get
static MCValue get(const MCSymbolRefExpr *SymA, const MCSymbolRefExpr *SymB=nullptr, int64_t Val=0, uint32_t RefKind=0)
Definition: MCValue.h:60
LEB128.h
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::RISCV::fixup_riscv_align
@ fixup_riscv_align
Definition: RISCVFixupKinds.h:70
llvm::MCFixupKindInfo::FKF_IsPCRel
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
Definition: MCFixupKindInfo.h:19
llvm::RISCV::fixup_riscv_tprel_lo12_s
@ fixup_riscv_tprel_lo12_s
Definition: RISCVFixupKinds.h:41
adjustFixupValue
static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, MCContext &Ctx)
Definition: RISCVAsmBackend.cpp:374
llvm::isUInt< 32 >
constexpr bool isUInt< 32 >(uint64_t x)
Definition: MathExtras.h:411
llvm::createRISCVELFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createRISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit)
Definition: RISCVELFObjectWriter.cpp:173
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::RISCV::fixup_riscv_tprel_lo12_i
@ fixup_riscv_tprel_lo12_i
Definition: RISCVFixupKinds.h:38
llvm::RISCV::fixup_riscv_add_8
@ fixup_riscv_add_8
Definition: RISCVFixupKinds.h:75
llvm::isUInt< 8 >
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:405
llvm::MCFixupKindInfo
Target independent information on a fixup kind.
Definition: MCFixupKindInfo.h:15
llvm::MCContext::reportError
void reportError(SMLoc L, const Twine &Msg)
Definition: MCContext.cpp:963
llvm::RISCVAsmBackend::getFixupKindInfo
const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const override
Get information on a fixup kind.
Definition: RISCVAsmBackend.cpp:48
llvm::RISCVAsmBackend::shouldInsertFixupForCodeAlign
bool shouldInsertFixupForCodeAlign(MCAssembler &Asm, const MCAsmLayout &Layout, MCAlignFragment &AF) override
Hook which indicates if the target requires a fixup to be generated when handling an align directive ...
Definition: RISCVAsmBackend.cpp:605
llvm::FK_Data_1
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
llvm::MCTargetOptions
Definition: MCTargetOptions.h:36
llvm::MCSymbolRefExpr
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192
llvm::MCFixupKindInfo::FKF_IsTarget
@ FKF_IsTarget
Should this fixup be evaluated in a target dependent manner?
Definition: MCFixupKindInfo.h:25
llvm::FK_NONE
@ FK_NONE
A no-op fixup.
Definition: MCFixup.h:22
llvm::MCELFObjectTargetWriter::getOSABI
uint8_t getOSABI() const
Definition: MCELFObjectWriter.h:101
llvm::NVPTXISD::Dummy
@ Dummy
Definition: NVPTXISelLowering.h:60
MCAsmInfo.h
Fixup
PowerPC TLS Dynamic Call Fixup
Definition: PPCTLSDynamicCall.cpp:235
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
llvm::RISCV::fixup_riscv_pcrel_hi20
@ fixup_riscv_pcrel_hi20
Definition: RISCVFixupKinds.h:26
llvm::RISCV::fixup_riscv_sub_16
@ fixup_riscv_sub_16
Definition: RISCVFixupKinds.h:86
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MCAsmLayout::getFragmentOffset
uint64_t getFragmentOffset(const MCFragment *F) const
Get the offset of the given fragment inside its containing section.
Definition: MCFragment.cpp:96
MCAsmLayout.h
llvm::RISCV::fixup_riscv_set_8
@ fixup_riscv_set_8
Definition: RISCVFixupKinds.h:72
MCObjectWriter.h
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
EndianStream.h
llvm::RISCV::fixup_riscv_sub_32
@ fixup_riscv_sub_32
Definition: RISCVFixupKinds.h:94
llvm::RISCV::NumTargetFixupKinds
@ NumTargetFixupKinds
Definition: RISCVFixupKinds.h:110
llvm::MCAsmLayout
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
llvm::RISCVAsmBackend::applyFixup
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const override
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
Definition: RISCVAsmBackend.cpp:549
llvm::RISCVAsmBackend::evaluateTargetFixup
bool evaluateTargetFixup(const MCAssembler &Asm, const MCAsmLayout &Layout, const MCFixup &Fixup, const MCFragment *DF, const MCValue &Target, uint64_t &Value, bool &WasForced) override
Definition: RISCVAsmBackend.cpp:488
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:321
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::MCAsmLayout::getSymbolOffset
bool getSymbolOffset(const MCSymbol &S, uint64_t &Val) const
Get the offset of the given symbol, as computed in the current layout.
Definition: MCFragment.cpp:148
llvm::RISCV::fixup_riscv_add_64
@ fixup_riscv_add_64
Definition: RISCVFixupKinds.h:97
llvm::RISCV::fixup_riscv_add_16
@ fixup_riscv_add_16
Definition: RISCVFixupKinds.h:83
llvm::MCAlignFragment::getAlignment
unsigned getAlignment() const
Definition: MCFragment.h:323
llvm::RISCVAsmBackend::writeNopData
bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override
Write an (optimal) nop sequence of Count bytes to the given output.
Definition: RISCVAsmBackend.cpp:355
MCValue.h
llvm::RISCV::fixup_riscv_sub_6b
@ fixup_riscv_sub_6b
Definition: RISCVFixupKinds.h:106
llvm::RISCV::fixup_riscv_set_16
@ fixup_riscv_set_16
Definition: RISCVFixupKinds.h:80
llvm::MCFixupKind
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
llvm::FK_Data_8
@ FK_Data_8
A eight-byte fixup.
Definition: MCFixup.h:26
llvm::RISCV::fixup_riscv_set_32
@ fixup_riscv_set_32
Definition: RISCVFixupKinds.h:88
llvm::RISCV::fixup_riscv_rvc_branch
@ fixup_riscv_rvc_branch
Definition: RISCVFixupKinds.h:58
llvm::RISCVAsmBackend::shouldForceRelocation
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target) override
Hook to check if a relocation is needed for some target specific reason.
Definition: RISCVAsmBackend.cpp:116
llvm::RISCVAsmBackend::relaxInstruction
void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const override
Relax the instruction in the given fragment to the next wider instruction.
Definition: RISCVAsmBackend.cpp:168
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
llvm::raw_svector_ostream
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:658
llvm::encodeULEB128
unsigned encodeULEB128(uint64_t Value, raw_ostream &OS, unsigned PadTo=0)
Utility function to encode a ULEB128 value to an output stream.
Definition: LEB128.h:80
llvm::SmallVectorImpl< char >
llvm::RISCVAsmBackend
Definition: RISCVAsmBackend.h:24
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
llvm::HexStyle::Asm
@ Asm
0ffh
Definition: MCInstPrinter.h:34
llvm::MCAsmLayout::getAssembler
MCAssembler & getAssembler() const
Get the assembler object this is a layout for.
Definition: MCAsmLayout.h:50
llvm::MCValue
This represents an "assembler immediate".
Definition: MCValue.h:37
llvm::MCSymbolRefExpr::VK_None
@ VK_None
Definition: MCExpr.h:195
raw_ostream.h
llvm::FK_Data_2
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
Endian.h
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::RISCV::fixup_riscv_tprel_hi20
@ fixup_riscv_tprel_hi20
Definition: RISCVFixupKinds.h:36
llvm::MCFixup
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::MCValue::getSymB
const MCSymbolRefExpr * getSymB() const
Definition: MCValue.h:46
llvm::RISCV::fixup_riscv_set_6b
@ fixup_riscv_set_6b
Definition: RISCVFixupKinds.h:103
llvm::MCBinaryExpr::getLHS
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
Definition: MCExpr.h:627
llvm::MCFixup::getOffset
uint32_t getOffset() const
Definition: MCFixup.h:102