LLVM 17.0.0git
RISCVAsmBackend.cpp
Go to the documentation of this file.
1//===-- RISCVAsmBackend.cpp - RISCV Assembler Backend ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "RISCVAsmBackend.h"
10#include "RISCVMCExpr.h"
11#include "llvm/ADT/APInt.h"
12#include "llvm/MC/MCAsmInfo.h"
13#include "llvm/MC/MCAsmLayout.h"
14#include "llvm/MC/MCAssembler.h"
15#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCSymbol.h"
21#include "llvm/MC/MCValue.h"
22#include "llvm/Support/Endian.h"
25#include "llvm/Support/LEB128.h"
27
28using namespace llvm;
29
30std::optional<MCFixupKind> RISCVAsmBackend::getFixupKind(StringRef Name) const {
32 unsigned Type;
34#define ELF_RELOC(X, Y) .Case(#X, Y)
35#include "llvm/BinaryFormat/ELFRelocs/RISCV.def"
36#undef ELF_RELOC
37 .Case("BFD_RELOC_NONE", ELF::R_RISCV_NONE)
38 .Case("BFD_RELOC_32", ELF::R_RISCV_32)
39 .Case("BFD_RELOC_64", ELF::R_RISCV_64)
40 .Default(-1u);
41 if (Type != -1u)
42 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
43 }
44 return std::nullopt;
45}
46
47const MCFixupKindInfo &
49 const static MCFixupKindInfo Infos[] = {
50 // This table *must* be in the order that the fixup_* kinds are defined in
51 // RISCVFixupKinds.h.
52 //
53 // name offset bits flags
54 {"fixup_riscv_hi20", 12, 20, 0},
55 {"fixup_riscv_lo12_i", 20, 12, 0},
56 {"fixup_riscv_12_i", 20, 12, 0},
57 {"fixup_riscv_lo12_s", 0, 32, 0},
58 {"fixup_riscv_pcrel_hi20", 12, 20,
60 {"fixup_riscv_pcrel_lo12_i", 20, 12,
62 {"fixup_riscv_pcrel_lo12_s", 0, 32,
64 {"fixup_riscv_got_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
65 {"fixup_riscv_tprel_hi20", 12, 20, 0},
66 {"fixup_riscv_tprel_lo12_i", 20, 12, 0},
67 {"fixup_riscv_tprel_lo12_s", 0, 32, 0},
68 {"fixup_riscv_tprel_add", 0, 0, 0},
69 {"fixup_riscv_tls_got_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
70 {"fixup_riscv_tls_gd_hi20", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
71 {"fixup_riscv_jal", 12, 20, MCFixupKindInfo::FKF_IsPCRel},
72 {"fixup_riscv_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
73 {"fixup_riscv_rvc_jump", 2, 11, MCFixupKindInfo::FKF_IsPCRel},
74 {"fixup_riscv_rvc_branch", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
75 {"fixup_riscv_call", 0, 64, MCFixupKindInfo::FKF_IsPCRel},
76 {"fixup_riscv_call_plt", 0, 64, MCFixupKindInfo::FKF_IsPCRel},
77 {"fixup_riscv_relax", 0, 0, 0},
78 {"fixup_riscv_align", 0, 0, 0},
79
80 {"fixup_riscv_set_8", 0, 8, 0},
81 {"fixup_riscv_add_8", 0, 8, 0},
82 {"fixup_riscv_sub_8", 0, 8, 0},
83
84 {"fixup_riscv_set_16", 0, 16, 0},
85 {"fixup_riscv_add_16", 0, 16, 0},
86 {"fixup_riscv_sub_16", 0, 16, 0},
87
88 {"fixup_riscv_set_32", 0, 32, 0},
89 {"fixup_riscv_add_32", 0, 32, 0},
90 {"fixup_riscv_sub_32", 0, 32, 0},
91
92 {"fixup_riscv_add_64", 0, 64, 0},
93 {"fixup_riscv_sub_64", 0, 64, 0},
94
95 {"fixup_riscv_set_6b", 2, 6, 0},
96 {"fixup_riscv_sub_6b", 2, 6, 0},
97 };
98 static_assert((std::size(Infos)) == RISCV::NumTargetFixupKinds,
99 "Not all fixup kinds added to Infos array");
100
101 // Fixup kinds from .reloc directive are like R_RISCV_NONE. They
102 // do not require any extra processing.
103 if (Kind >= FirstLiteralRelocationKind)
105
106 if (Kind < FirstTargetFixupKind)
108
109 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
110 "Invalid kind!");
111 return Infos[Kind - FirstTargetFixupKind];
112}
113
114// If linker relaxation is enabled, or the relax option had previously been
115// enabled, always emit relocations even if the fixup can be resolved. This is
116// necessary for correctness as offsets may change during relaxation.
118 const MCFixup &Fixup,
119 const MCValue &Target) {
120 if (Fixup.getKind() >= FirstLiteralRelocationKind)
121 return true;
122 switch (Fixup.getTargetKind()) {
123 default:
124 break;
125 case FK_Data_1:
126 case FK_Data_2:
127 case FK_Data_4:
128 case FK_Data_8:
129 if (Target.isAbsolute())
130 return false;
131 break;
135 return true;
136 }
137
138 return STI.hasFeature(RISCV::FeatureRelax) || ForceRelocs;
139}
140
142 bool Resolved,
144 const MCRelaxableFragment *DF,
145 const MCAsmLayout &Layout,
146 const bool WasForced) const {
147 int64_t Offset = int64_t(Value);
148 unsigned Kind = Fixup.getTargetKind();
149
150 // We only do conditional branch relaxation when the symbol is resolved.
151 // For conditional branch, the immediate must be in the range
152 // [-4096, 4094].
153 if (Kind == RISCV::fixup_riscv_branch)
154 return Resolved && !isInt<13>(Offset);
155
156 // Return true if the symbol is actually unresolved.
157 // Resolved could be always false when shouldForceRelocation return true.
158 // We use !WasForced to indicate that the symbol is unresolved and not forced
159 // by shouldForceRelocation.
160 if (!Resolved && !WasForced)
161 return true;
162
163 switch (Kind) {
164 default:
165 return false;
167 // For compressed branch instructions the immediate must be
168 // in the range [-256, 254].
169 return Offset > 254 || Offset < -256;
171 // For compressed jump instructions the immediate must be
172 // in the range [-2048, 2046].
173 return Offset > 2046 || Offset < -2048;
174 }
175}
176
178 const MCSubtargetInfo &STI) const {
179 MCInst Res;
180 switch (Inst.getOpcode()) {
181 default:
182 llvm_unreachable("Opcode not expected!");
183 case RISCV::C_BEQZ:
184 case RISCV::C_BNEZ:
185 case RISCV::C_J:
186 case RISCV::C_JAL: {
187 bool Success = RISCVRVC::uncompress(Res, Inst, STI);
188 assert(Success && "Can't uncompress instruction");
189 (void)Success;
190 break;
191 }
192 case RISCV::BEQ:
193 case RISCV::BNE:
194 case RISCV::BLT:
195 case RISCV::BGE:
196 case RISCV::BLTU:
197 case RISCV::BGEU:
199 Res.addOperand(Inst.getOperand(0));
200 Res.addOperand(Inst.getOperand(1));
201 Res.addOperand(Inst.getOperand(2));
202 break;
203 }
204 Inst = std::move(Res);
205}
206
208 MCAsmLayout &Layout,
209 bool &WasRelaxed) const {
210 MCContext &C = Layout.getAssembler().getContext();
211
212 int64_t LineDelta = DF.getLineDelta();
213 const MCExpr &AddrDelta = DF.getAddrDelta();
214 SmallVectorImpl<char> &Data = DF.getContents();
215 SmallVectorImpl<MCFixup> &Fixups = DF.getFixups();
216 size_t OldSize = Data.size();
217
218 int64_t Value;
219 bool IsAbsolute = AddrDelta.evaluateKnownAbsolute(Value, Layout);
220 assert(IsAbsolute && "CFA with invalid expression");
221 (void)IsAbsolute;
222
223 Data.clear();
224 Fixups.clear();
226
227 // INT64_MAX is a signal that this is actually a DW_LNE_end_sequence.
228 if (LineDelta != INT64_MAX) {
229 OS << uint8_t(dwarf::DW_LNS_advance_line);
230 encodeSLEB128(LineDelta, OS);
231 }
232
233 unsigned Offset;
234 std::pair<MCFixupKind, MCFixupKind> Fixup;
235
236 // According to the DWARF specification, the `DW_LNS_fixed_advance_pc` opcode
237 // takes a single unsigned half (unencoded) operand. The maximum encodable
238 // value is therefore 65535. Set a conservative upper bound for relaxation.
239 if (Value > 60000) {
240 unsigned PtrSize = C.getAsmInfo()->getCodePointerSize();
241
242 OS << uint8_t(dwarf::DW_LNS_extended_op);
243 encodeULEB128(PtrSize + 1, OS);
244
245 OS << uint8_t(dwarf::DW_LNE_set_address);
246 Offset = OS.tell();
247 assert((PtrSize == 4 || PtrSize == 8) && "Unexpected pointer size");
249 OS.write_zeros(PtrSize);
250 } else {
251 OS << uint8_t(dwarf::DW_LNS_fixed_advance_pc);
252 Offset = OS.tell();
254 support::endian::write<uint16_t>(OS, 0, support::little);
255 }
256
257 const MCBinaryExpr &MBE = cast<MCBinaryExpr>(AddrDelta);
258 Fixups.push_back(MCFixup::create(Offset, MBE.getLHS(), std::get<0>(Fixup)));
259 Fixups.push_back(MCFixup::create(Offset, MBE.getRHS(), std::get<1>(Fixup)));
260
261 if (LineDelta == INT64_MAX) {
262 OS << uint8_t(dwarf::DW_LNS_extended_op);
263 OS << uint8_t(1);
264 OS << uint8_t(dwarf::DW_LNE_end_sequence);
265 } else {
266 OS << uint8_t(dwarf::DW_LNS_copy);
267 }
268
269 WasRelaxed = OldSize != Data.size();
270 return true;
271}
272
274 MCAsmLayout &Layout,
275 bool &WasRelaxed) const {
276
277 const MCExpr &AddrDelta = DF.getAddrDelta();
278 SmallVectorImpl<char> &Data = DF.getContents();
279 SmallVectorImpl<MCFixup> &Fixups = DF.getFixups();
280 size_t OldSize = Data.size();
281
282 int64_t Value;
283 bool IsAbsolute = AddrDelta.evaluateKnownAbsolute(Value, Layout);
284 assert(IsAbsolute && "CFA with invalid expression");
285 (void)IsAbsolute;
286
287 Data.clear();
288 Fixups.clear();
290
291 assert(
293 1 &&
294 "expected 1-byte alignment");
295 if (Value == 0) {
296 WasRelaxed = OldSize != Data.size();
297 return true;
298 }
299
300 auto AddFixups = [&Fixups, &AddrDelta](unsigned Offset,
301 std::pair<unsigned, unsigned> Fixup) {
302 const MCBinaryExpr &MBE = cast<MCBinaryExpr>(AddrDelta);
303 Fixups.push_back(MCFixup::create(
304 Offset, MBE.getLHS(), static_cast<MCFixupKind>(std::get<0>(Fixup))));
305 Fixups.push_back(MCFixup::create(
306 Offset, MBE.getRHS(), static_cast<MCFixupKind>(std::get<1>(Fixup))));
307 };
308
309 if (isUIntN(6, Value)) {
310 OS << uint8_t(dwarf::DW_CFA_advance_loc);
312 } else if (isUInt<8>(Value)) {
313 OS << uint8_t(dwarf::DW_CFA_advance_loc1);
314 support::endian::write<uint8_t>(OS, 0, support::little);
316 } else if (isUInt<16>(Value)) {
317 OS << uint8_t(dwarf::DW_CFA_advance_loc2);
318 support::endian::write<uint16_t>(OS, 0, support::little);
320 } else if (isUInt<32>(Value)) {
321 OS << uint8_t(dwarf::DW_CFA_advance_loc4);
322 support::endian::write<uint32_t>(OS, 0, support::little);
324 } else {
325 llvm_unreachable("unsupported CFA encoding");
326 }
327
328 WasRelaxed = OldSize != Data.size();
329 return true;
330}
331
332// Given a compressed control flow instruction this function returns
333// the expanded instruction.
334unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const {
335 switch (Op) {
336 default:
337 return Op;
338 case RISCV::C_BEQZ:
339 return RISCV::BEQ;
340 case RISCV::C_BNEZ:
341 return RISCV::BNE;
342 case RISCV::C_J:
343 case RISCV::C_JAL: // fall through.
344 return RISCV::JAL;
345 case RISCV::BEQ:
346 return RISCV::PseudoLongBEQ;
347 case RISCV::BNE:
348 return RISCV::PseudoLongBNE;
349 case RISCV::BLT:
350 return RISCV::PseudoLongBLT;
351 case RISCV::BGE:
352 return RISCV::PseudoLongBGE;
353 case RISCV::BLTU:
354 return RISCV::PseudoLongBLTU;
355 case RISCV::BGEU:
356 return RISCV::PseudoLongBGEU;
357 }
358}
359
361 const MCSubtargetInfo &STI) const {
362 return getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode();
363}
364
366 const MCSubtargetInfo *STI) const {
367 // We mostly follow binutils' convention here: align to even boundary with a
368 // 0-fill padding. We emit up to 1 2-byte nop, though we use c.nop if RVC is
369 // enabled or 0-fill otherwise. The remainder is now padded with 4-byte nops.
370
371 // Instructions always are at even addresses. We must be in a data area or
372 // be unaligned due to some other reason.
373 if (Count % 2) {
374 OS.write("\0", 1);
375 Count -= 1;
376 }
377
378 bool UseCompressedNop = STI->hasFeature(RISCV::FeatureStdExtC) ||
379 STI->hasFeature(RISCV::FeatureStdExtZca);
380 // The canonical nop on RVC is c.nop.
381 if (Count % 4 == 2) {
382 OS.write(UseCompressedNop ? "\x01\0" : "\0\0", 2);
383 Count -= 2;
384 }
385
386 // The canonical nop on RISC-V is addi x0, x0, 0.
387 for (; Count >= 4; Count -= 4)
388 OS.write("\x13\0\0\0", 4);
389
390 return true;
391}
392
394 MCContext &Ctx) {
395 switch (Fixup.getTargetKind()) {
396 default:
397 llvm_unreachable("Unknown fixup kind!");
401 llvm_unreachable("Relocation should be unconditionally forced\n");
413 case FK_Data_1:
414 case FK_Data_2:
415 case FK_Data_4:
416 case FK_Data_8:
417 case FK_Data_6b:
418 return Value;
420 return Value & 0x03;
424 return Value & 0xfff;
426 if (!isInt<12>(Value)) {
427 Ctx.reportError(Fixup.getLoc(),
428 "operand must be a constant 12-bit integer");
429 }
430 return Value & 0xfff;
434 return (((Value >> 5) & 0x7f) << 25) | ((Value & 0x1f) << 7);
438 // Add 1 if bit 11 is 1, to compensate for low 12 bits being negative.
439 return ((Value + 0x800) >> 12) & 0xfffff;
441 if (!isInt<21>(Value))
442 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
443 if (Value & 0x1)
444 Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned");
445 // Need to produce imm[19|10:1|11|19:12] from the 21-bit Value.
446 unsigned Sbit = (Value >> 20) & 0x1;
447 unsigned Hi8 = (Value >> 12) & 0xff;
448 unsigned Mid1 = (Value >> 11) & 0x1;
449 unsigned Lo10 = (Value >> 1) & 0x3ff;
450 // Inst{31} = Sbit;
451 // Inst{30-21} = Lo10;
452 // Inst{20} = Mid1;
453 // Inst{19-12} = Hi8;
454 Value = (Sbit << 19) | (Lo10 << 9) | (Mid1 << 8) | Hi8;
455 return Value;
456 }
458 if (!isInt<13>(Value))
459 Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
460 if (Value & 0x1)
461 Ctx.reportError(Fixup.getLoc(), "fixup value must be 2-byte aligned");
462 // Need to extract imm[12], imm[10:5], imm[4:1], imm[11] from the 13-bit
463 // Value.
464 unsigned Sbit = (Value >> 12) & 0x1;
465 unsigned Hi1 = (Value >> 11) & 0x1;
466 unsigned Mid6 = (Value >> 5) & 0x3f;
467 unsigned Lo4 = (Value >> 1) & 0xf;
468 // Inst{31} = Sbit;
469 // Inst{30-25} = Mid6;
470 // Inst{11-8} = Lo4;
471 // Inst{7} = Hi1;
472 Value = (Sbit << 31) | (Mid6 << 25) | (Lo4 << 8) | (Hi1 << 7);
473 return Value;
474 }
477 // Jalr will add UpperImm with the sign-extended 12-bit LowerImm,
478 // we need to add 0x800ULL before extract upper bits to reflect the
479 // effect of the sign extension.
480 uint64_t UpperImm = (Value + 0x800ULL) & 0xfffff000ULL;
481 uint64_t LowerImm = Value & 0xfffULL;
482 return UpperImm | ((LowerImm << 20) << 32);
483 }
485 // Need to produce offset[11|4|9:8|10|6|7|3:1|5] from the 11-bit Value.
486 unsigned Bit11 = (Value >> 11) & 0x1;
487 unsigned Bit4 = (Value >> 4) & 0x1;
488 unsigned Bit9_8 = (Value >> 8) & 0x3;
489 unsigned Bit10 = (Value >> 10) & 0x1;
490 unsigned Bit6 = (Value >> 6) & 0x1;
491 unsigned Bit7 = (Value >> 7) & 0x1;
492 unsigned Bit3_1 = (Value >> 1) & 0x7;
493 unsigned Bit5 = (Value >> 5) & 0x1;
494 Value = (Bit11 << 10) | (Bit4 << 9) | (Bit9_8 << 7) | (Bit10 << 6) |
495 (Bit6 << 5) | (Bit7 << 4) | (Bit3_1 << 1) | Bit5;
496 return Value;
497 }
499 // Need to produce offset[8|4:3], [reg 3 bit], offset[7:6|2:1|5]
500 unsigned Bit8 = (Value >> 8) & 0x1;
501 unsigned Bit7_6 = (Value >> 6) & 0x3;
502 unsigned Bit5 = (Value >> 5) & 0x1;
503 unsigned Bit4_3 = (Value >> 3) & 0x3;
504 unsigned Bit2_1 = (Value >> 1) & 0x3;
505 Value = (Bit8 << 12) | (Bit4_3 << 10) | (Bit7_6 << 5) | (Bit2_1 << 3) |
506 (Bit5 << 2);
507 return Value;
508 }
509
510 }
511}
512
514 const MCAssembler &Asm, const MCAsmLayout &Layout, const MCFixup &Fixup,
515 const MCFragment *DF, const MCValue &Target, uint64_t &Value,
516 bool &WasForced) {
517 const MCFixup *AUIPCFixup;
518 const MCFragment *AUIPCDF;
519 MCValue AUIPCTarget;
520 switch (Fixup.getTargetKind()) {
521 default:
522 llvm_unreachable("Unexpected fixup kind!");
524 AUIPCFixup = &Fixup;
525 AUIPCDF = DF;
526 AUIPCTarget = Target;
527 break;
530 AUIPCFixup = cast<RISCVMCExpr>(Fixup.getValue())->getPCRelHiFixup(&AUIPCDF);
531 if (!AUIPCFixup) {
532 Asm.getContext().reportError(Fixup.getLoc(),
533 "could not find corresponding %pcrel_hi");
534 return true;
535 }
536
537 // MCAssembler::evaluateFixup will emit an error for this case when it sees
538 // the %pcrel_hi, so don't duplicate it when also seeing the %pcrel_lo.
539 const MCExpr *AUIPCExpr = AUIPCFixup->getValue();
540 if (!AUIPCExpr->evaluateAsRelocatable(AUIPCTarget, &Layout, AUIPCFixup))
541 return true;
542 break;
543 }
544 }
545
546 if (!AUIPCTarget.getSymA() || AUIPCTarget.getSymB())
547 return false;
548
549 const MCSymbolRefExpr *A = AUIPCTarget.getSymA();
550 const MCSymbol &SA = A->getSymbol();
551 if (A->getKind() != MCSymbolRefExpr::VK_None || SA.isUndefined())
552 return false;
553
554 auto *Writer = Asm.getWriterPtr();
555 if (!Writer)
556 return false;
557
558 bool IsResolved = Writer->isSymbolRefDifferenceFullyResolvedImpl(
559 Asm, SA, *AUIPCDF, false, true);
560 if (!IsResolved)
561 return false;
562
563 Value = Layout.getSymbolOffset(SA) + AUIPCTarget.getConstant();
564 Value -= Layout.getFragmentOffset(AUIPCDF) + AUIPCFixup->getOffset();
565
566 if (shouldForceRelocation(Asm, *AUIPCFixup, AUIPCTarget)) {
567 WasForced = true;
568 return false;
569 }
570
571 return true;
572}
573
575 const MCValue &Target,
577 bool IsResolved,
578 const MCSubtargetInfo *STI) const {
579 MCFixupKind Kind = Fixup.getKind();
580 if (Kind >= FirstLiteralRelocationKind)
581 return;
582 MCContext &Ctx = Asm.getContext();
584 if (!Value)
585 return; // Doesn't change encoding.
586 // Apply any target-specific value adjustments.
588
589 // Shift the value into position.
590 Value <<= Info.TargetOffset;
591
592 unsigned Offset = Fixup.getOffset();
593 unsigned NumBytes = alignTo(Info.TargetSize + Info.TargetOffset, 8) / 8;
594
595 assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
596
597 // For each byte of the fragment that the fixup touches, mask in the
598 // bits from the fixup value.
599 for (unsigned i = 0; i != NumBytes; ++i) {
600 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
601 }
602}
603
604// Linker relaxation may change code size. We have to insert Nops
605// for .align directive when linker relaxation enabled. So then Linker
606// could satisfy alignment by removing Nops.
607// The function return the total Nops Size we need to insert.
609 const MCAlignFragment &AF, unsigned &Size) {
610 // Calculate Nops Size only when linker relaxation enabled.
611 const MCSubtargetInfo *STI = AF.getSubtargetInfo();
612 if (!STI->hasFeature(RISCV::FeatureRelax))
613 return false;
614
615 bool UseCompressedNop = STI->hasFeature(RISCV::FeatureStdExtC) ||
616 STI->hasFeature(RISCV::FeatureStdExtZca);
617 unsigned MinNopLen = UseCompressedNop ? 2 : 4;
618
619 if (AF.getAlignment() <= MinNopLen) {
620 return false;
621 } else {
622 Size = AF.getAlignment().value() - MinNopLen;
623 return true;
624 }
625}
626
627// We need to insert R_RISCV_ALIGN relocation type to indicate the
628// position of Nops and the total bytes of the Nops have been inserted
629// when linker relaxation enabled.
630// The function insert fixup_riscv_align fixup which eventually will
631// transfer to R_RISCV_ALIGN relocation type.
633 const MCAsmLayout &Layout,
634 MCAlignFragment &AF) {
635 // Insert the fixup only when linker relaxation enabled.
636 const MCSubtargetInfo *STI = AF.getSubtargetInfo();
637 if (!STI->hasFeature(RISCV::FeatureRelax))
638 return false;
639
640 // Calculate total Nops we need to insert. If there are none to insert
641 // then simply return.
642 unsigned Count;
643 if (!shouldInsertExtraNopBytesForCodeAlign(AF, Count) || (Count == 0))
644 return false;
645
646 MCContext &Ctx = Asm.getContext();
647 const MCExpr *Dummy = MCConstantExpr::create(0, Ctx);
648 // Create fixup_riscv_align fixup.
649 MCFixup Fixup =
651
652 uint64_t FixedValue = 0;
653 MCValue NopBytes = MCValue::get(Count);
654
655 Asm.getWriter().recordRelocation(Asm, Layout, &AF, Fixup, NopBytes,
656 FixedValue);
657
658 return true;
659}
660
661std::unique_ptr<MCObjectTargetWriter>
663 return createRISCVELFObjectWriter(OSABI, Is64Bit);
664}
665
667 const MCSubtargetInfo &STI,
668 const MCRegisterInfo &MRI,
669 const MCTargetOptions &Options) {
670 const Triple &TT = STI.getTargetTriple();
671 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
672 return new RISCVAsmBackend(STI, OSABI, TT.isArch64Bit(), Options);
673}
unsigned const MachineRegisterInfo * MRI
static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target, uint64_t Value, MCContext &Ctx, const Triple &TheTriple, bool IsResolved)
#define Success
This file implements a class to represent arbitrary precision integral constant values and operations...
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
std::string Name
uint64_t Size
static LVOptions Options
Definition: LVOptions.cpp:25
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
Align getAlignment() const
Definition: MCFragment.h:322
const MCSubtargetInfo * getSubtargetInfo() const
Definition: MCFragment.h:336
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:41
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
unsigned getMinInstAlignment() const
Definition: MCAsmInfo.h:645
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
bool getSymbolOffset(const MCSymbol &S, uint64_t &Val) const
Get the offset of the given symbol, as computed in the current layout.
Definition: MCFragment.cpp:152
uint64_t getFragmentOffset(const MCFragment *F) const
Get the offset of the given fragment inside its containing section.
Definition: MCFragment.cpp:96
MCAssembler & getAssembler() const
Get the assembler object this is a layout for.
Definition: MCAsmLayout.h:50
MCContext & getContext() const
Definition: MCAssembler.h:321
Binary assembler expressions.
Definition: MCExpr.h:481
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
Definition: MCExpr.h:628
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
Definition: MCExpr.h:631
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
Context object for machine code objects.
Definition: MCContext.h:76
const MCAsmInfo * getAsmInfo() const
Definition: MCContext.h:446
void reportError(SMLoc L, const Twine &Msg)
Definition: MCContext.cpp:1049
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
bool evaluateKnownAbsolute(int64_t &Res, const MCAsmLayout &Layout) const
Definition: MCExpr.cpp:561
bool evaluateAsRelocatable(MCValue &Res, const MCAsmLayout *Layout, const MCFixup *Fixup) const
Try to evaluate the expression to a relocatable value, i.e.
Definition: MCExpr.cpp:749
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
const MCExpr * getValue() const
Definition: MCFixup.h:105
uint32_t getOffset() const
Definition: MCFixup.h:102
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:87
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
unsigned getOpcode() const
Definition: MCInst.h:198
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
void setOpcode(unsigned Op)
Definition: MCInst.h:197
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:270
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
bool isUndefined(bool SetUsed=true) const
isUndefined - Check if this symbol undefined (i.e., implicitly defined).
Definition: MCSymbol.h:257
This represents an "assembler immediate".
Definition: MCValue.h:36
int64_t getConstant() const
Definition: MCValue.h:43
static MCValue get(const MCSymbolRefExpr *SymA, const MCSymbolRefExpr *SymB=nullptr, int64_t Val=0, uint32_t RefKind=0)
Definition: MCValue.h:59
const MCSymbolRefExpr * getSymB() const
Definition: MCValue.h:45
const MCSymbolRefExpr * getSymA() const
Definition: MCValue.h:44
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:305
std::unique_ptr< MCObjectTargetWriter > createObjectTargetWriter() const override
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const override
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const override
Relax the instruction in the given fragment to the next wider instruction.
bool shouldInsertFixupForCodeAlign(MCAssembler &Asm, const MCAsmLayout &Layout, MCAlignFragment &AF) override
Hook which indicates if the target requires a fixup to be generated when handling an align directive ...
bool relaxDwarfLineAddr(MCDwarfLineAddrFragment &DF, MCAsmLayout &Layout, bool &WasRelaxed) const override
bool relaxDwarfCFA(MCDwarfCallFrameFragment &DF, MCAsmLayout &Layout, bool &WasRelaxed) const override
const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const override
Get information on a fixup kind.
bool shouldInsertExtraNopBytesForCodeAlign(const MCAlignFragment &AF, unsigned &Size) override
Hook to check if extra nop bytes must be inserted for alignment directive.
bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const override
Check whether the given instruction may need relaxation.
bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override
Write an (optimal) nop sequence of Count bytes to the given output.
unsigned getRelaxedOpcode(unsigned Op) const
bool evaluateTargetFixup(const MCAssembler &Asm, const MCAsmLayout &Layout, const MCFixup &Fixup, const MCFragment *DF, const MCValue &Target, uint64_t &Value, bool &WasForced) override
bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout, const bool WasForced) const override
Target specific predicate for whether a given fixup requires the associated instruction to be relaxed...
unsigned getNumFixupKinds() const override
Get the number of target specific fixup kinds.
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target) override
Hook to check if a relocation is needed for some target specific reason.
std::optional< MCFixupKind > getFixupKind(StringRef Name) const override
Map a relocation name used in .reloc to a fixup kind.
Represents a location in source code.
Definition: SMLoc.h:23
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:675
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
raw_ostream & write_zeros(unsigned NumZeros)
write_zeros - Insert 'NumZeros' nulls.
uint64_t tell() const
tell - Return the current offset with the file.
Definition: raw_ostream.h:134
raw_ostream & write(unsigned char C)
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:672
#define INT64_MAX
Definition: DataTypes.h:71
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
static std::pair< MCFixupKind, MCFixupKind > getRelocPairForSize(unsigned Size)
@ fixup_riscv_tprel_lo12_s
@ fixup_riscv_tls_got_hi20
@ fixup_riscv_pcrel_lo12_i
@ fixup_riscv_pcrel_lo12_s
@ fixup_riscv_tprel_lo12_i
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
std::unique_ptr< MCObjectTargetWriter > createRISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit)
@ Offset
Definition: DWP.cpp:440
bool isUIntN(unsigned N, uint64_t x)
Checks if an unsigned integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:256
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
@ FirstTargetFixupKind
Definition: MCFixup.h:45
@ FK_Data_6b
A six-bits fixup.
Definition: MCFixup.h:27
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
Definition: MCFixup.h:50
@ FK_Data_8
A eight-byte fixup.
Definition: MCFixup.h:26
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
@ FK_NONE
A no-op fixup.
Definition: MCFixup.h:22
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
MCAsmBackend * createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:155
unsigned encodeSLEB128(int64_t Value, raw_ostream &OS, unsigned PadTo=0)
Utility function to encode a SLEB128 value to an output stream.
Definition: LEB128.h:23
unsigned encodeULEB128(uint64_t Value, raw_ostream &OS, unsigned PadTo=0)
Utility function to encode a ULEB128 value to an output stream.
Definition: LEB128.h:80
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
Target independent information on a fixup kind.
@ FKF_IsTarget
Should this fixup be evaluated in a target dependent manner?
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...