llvm::RISCV Namespace Reference

Namespaces
namespace	RISCVExtensionBitmaskTable

Classes
struct	CPUInfo
struct	CPUModel
struct	RISCVMaskedPseudoInfo
struct	VLEPseudo
struct	VLSEGPseudo
struct	VLX_VSXPseudo
struct	VLXSEGPseudo
struct	VSEPseudo
struct	VSSEGPseudo
struct	VSXSEGPseudo

Enumerations
enum	PartialMappingIdx {   PMI_GPRB32 = 0 , PMI_GPRB64 = 1 , PMI_FPRB16 = 2 , PMI_FPRB32 = 3 ,   PMI_FPRB64 = 4 , PMI_VRB64 = 5 , PMI_VRB128 = 6 , PMI_VRB256 = 7 ,   PMI_VRB512 = 8 }
enum	ValueMappingIdx {   InvalidIdx = 0 , GPRB32Idx = 1 , GPRB64Idx = 4 , FPRB16Idx = 7 ,   FPRB32Idx = 10 , FPRB64Idx = 13 , VRB64Idx = 16 , VRB128Idx = 19 ,   VRB256Idx = 22 , VRB512Idx = 25 }
enum	Fixups {   fixup_riscv_hi20 = FirstTargetFixupKind , fixup_riscv_lo12_i , fixup_riscv_12_i , fixup_riscv_lo12_s ,   fixup_riscv_pcrel_hi20 , fixup_riscv_pcrel_lo12_i , fixup_riscv_pcrel_lo12_s , fixup_riscv_got_hi20 ,   fixup_riscv_tprel_hi20 , fixup_riscv_tprel_lo12_i , fixup_riscv_tprel_lo12_s , fixup_riscv_tprel_add ,   fixup_riscv_tls_got_hi20 , fixup_riscv_tls_gd_hi20 , fixup_riscv_jal , fixup_riscv_branch ,   fixup_riscv_rvc_jump , fixup_riscv_rvc_branch , fixup_riscv_call , fixup_riscv_call_plt ,   fixup_riscv_relax , fixup_riscv_align , fixup_riscv_tlsdesc_hi20 , fixup_riscv_tlsdesc_load_lo12 ,   fixup_riscv_tlsdesc_add_lo12 , fixup_riscv_tlsdesc_call , fixup_riscv_invalid , NumTargetFixupKinds = fixup_riscv_invalid - FirstTargetFixupKind }
enum	CPUKind : unsigned

Functions
void	getFeaturesForCPU (StringRef CPU, SmallVectorImpl< std::string > &EnabledFeatures, bool NeedPlus=false)
bool	parseCPU (StringRef CPU, bool IsRV64)
bool	parseTuneCPU (StringRef CPU, bool IsRV64)
StringRef	getMArchFromMcpu (StringRef CPU)
void	fillValidCPUArchList (SmallVectorImpl< StringRef > &Values, bool IsRV64)
void	fillValidTuneCPUArchList (SmallVectorImpl< StringRef > &Values, bool IsRV64)
bool	hasFastScalarUnalignedAccess (StringRef CPU)
bool	hasFastVectorUnalignedAccess (StringRef CPU)
bool	hasValidCPUModel (StringRef CPU)
CPUModel	getCPUModel (StringRef CPU)
static std::pair< MCFixupKind, MCFixupKind >	getRelocPairForSize (unsigned Size)
ArrayRef< MCPhysReg >	getArgGPRs (const RISCVABI::ABI ABI)
bool	isSEXT_W (const MachineInstr &MI)
bool	isZEXT_W (const MachineInstr &MI)
bool	isZEXT_B (const MachineInstr &MI)
bool	isRVVSpill (const MachineInstr &MI)
std::optional< std::pair< unsigned, unsigned > >	isRVVSpillForZvlsseg (unsigned Opcode)
bool	isFaultFirstLoad (const MachineInstr &MI)
int16_t	getNamedOperandIdx (uint16_t Opcode, uint16_t NamedIndex)
bool	hasEqualFRM (const MachineInstr &MI1, const MachineInstr &MI2)
std::optional< unsigned >	getVectorLowDemandedScalarBits (uint16_t Opcode, unsigned Log2SEW)
unsigned	getRVVMCOpcode (unsigned RVVPseudoOpcode)
unsigned	getDestLog2EEW (const MCInstrDesc &Desc, unsigned Log2SEW)
bool	isVLKnownLE (const MachineOperand &LHS, const MachineOperand &RHS)
	Given two VL operands, do we know that LHS <= RHS?
static const CPUInfo *	getCPUInfoByName (StringRef CPU)

Variables
static constexpr unsigned	RVVBitsPerBlock = 64
const RegisterBankInfo::PartialMapping	PartMappings []
const RegisterBankInfo::ValueMapping	ValueMappings []
static constexpr int64_t	VLMaxSentinel = -1LL
static constexpr unsigned	FPMASK_Negative_Infinity = 0x001
static constexpr unsigned	FPMASK_Negative_Normal = 0x002
static constexpr unsigned	FPMASK_Negative_Subnormal = 0x004
static constexpr unsigned	FPMASK_Negative_Zero = 0x008
static constexpr unsigned	FPMASK_Positive_Zero = 0x010
static constexpr unsigned	FPMASK_Positive_Subnormal = 0x020
static constexpr unsigned	FPMASK_Positive_Normal = 0x040
static constexpr unsigned	FPMASK_Positive_Infinity = 0x080
static constexpr unsigned	FPMASK_Signaling_NaN = 0x100
static constexpr unsigned	FPMASK_Quiet_NaN = 0x200
constexpr CPUInfo	RISCVCPUInfo []

Enumeration Type Documentation

CPUKind

enum llvm::RISCV::CPUKind : unsigned

Definition at line 22 of file RISCVTargetParser.cpp.

Fixups

enum llvm::RISCV::Fixups

Enumerator
fixup_riscv_hi20
fixup_riscv_lo12_i
fixup_riscv_12_i
fixup_riscv_lo12_s
fixup_riscv_pcrel_hi20
fixup_riscv_pcrel_lo12_i
fixup_riscv_pcrel_lo12_s
fixup_riscv_got_hi20
fixup_riscv_tprel_hi20
fixup_riscv_tprel_lo12_i
fixup_riscv_tprel_lo12_s
fixup_riscv_tprel_add
fixup_riscv_tls_got_hi20
fixup_riscv_tls_gd_hi20
fixup_riscv_jal
fixup_riscv_branch
fixup_riscv_rvc_jump
fixup_riscv_rvc_branch
fixup_riscv_call
fixup_riscv_call_plt
fixup_riscv_relax
fixup_riscv_align
fixup_riscv_tlsdesc_hi20
fixup_riscv_tlsdesc_load_lo12
fixup_riscv_tlsdesc_add_lo12
fixup_riscv_tlsdesc_call
fixup_riscv_invalid
NumTargetFixupKinds

Definition at line 19 of file RISCVFixupKinds.h.

PartialMappingIdx

enum llvm::RISCV::PartialMappingIdx

Enumerator
PMI_GPRB32
PMI_GPRB64
PMI_FPRB16
PMI_FPRB32
PMI_FPRB64
PMI_VRB64
PMI_VRB128
PMI_VRB256
PMI_VRB512

Definition at line 42 of file RISCVRegisterBankInfo.cpp.

ValueMappingIdx

enum llvm::RISCV::ValueMappingIdx

Enumerator
InvalidIdx
GPRB32Idx
GPRB64Idx
FPRB16Idx
FPRB32Idx
FPRB64Idx
VRB64Idx
VRB128Idx
VRB256Idx
VRB512Idx

Definition at line 95 of file RISCVRegisterBankInfo.cpp.

Function Documentation

fillValidCPUArchList()

void llvm::RISCV::fillValidCPUArchList	(	SmallVectorImpl< StringRef > &	Values,
		bool	IsRV64
	)

Definition at line 101 of file RISCVTargetParser.cpp.

References llvm::CallingConv::C, llvm::SmallVectorImpl< T >::emplace_back(), and RISCVCPUInfo.

fillValidTuneCPUArchList()

void llvm::RISCV::fillValidTuneCPUArchList	(	SmallVectorImpl< StringRef > &	Values,
		bool	IsRV64
	)

Definition at line 108 of file RISCVTargetParser.cpp.

References llvm::CallingConv::C, llvm::SmallVectorImpl< T >::emplace_back(), and RISCVCPUInfo.

getArgGPRs()

ArrayRef< MCPhysReg > llvm::RISCV::getArgGPRs

(

const RISCVABI::ABI

ABI

)

Definition at line 126 of file RISCVCallingConv.cpp.

References llvm::RISCVABI::ABI_ILP32E, and llvm::RISCVABI::ABI_LP64E.

Referenced by llvm::CC_RISCV(), CC_RISCVAssign2XLen(), and llvm::RISCVTargetLowering::LowerFormalArguments().

getCPUInfoByName()

static const CPUInfo * llvm::RISCV::getCPUInfoByName ( StringRef  CPU )

static

Definition at line 43 of file RISCVTargetParser.cpp.

References llvm::CallingConv::C, and RISCVCPUInfo.

Referenced by getCPUModel(), getMArchFromMcpu(), hasFastScalarUnalignedAccess(), hasFastVectorUnalignedAccess(), and parseCPU().

getCPUModel()

CPUModel llvm::RISCV::getCPUModel

(

StringRef

CPU

)

Definition at line 65 of file RISCVTargetParser.cpp.

References getCPUInfoByName(), and Info.

Referenced by hasValidCPUModel().

getDestLog2EEW()

unsigned llvm::RISCV::getDestLog2EEW	(	const MCInstrDesc &	Desc,
		unsigned	Log2SEW
	)

Definition at line 4226 of file RISCVInstrInfo.cpp.

References assert(), llvm::RISCVII::DestEEWMask, llvm::RISCVII::DestEEWShift, and Scaled.

Referenced by INITIALIZE_PASS().

getFeaturesForCPU()

void llvm::RISCV::getFeaturesForCPU	(	StringRef	CPU,
		SmallVectorImpl< std::string > &	EnabledFeatures,
		bool	NeedPlus = false
	)

Definition at line 118 of file RISCVTargetParser.cpp.

References llvm::SmallVectorImpl< T >::clear(), llvm::errorToBool(), F, getMArchFromMcpu(), llvm::RISCVISAInfo::parseArchString(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

getMArchFromMcpu()

StringRef llvm::RISCV::getMArchFromMcpu

(

StringRef

CPU

)

Definition at line 94 of file RISCVTargetParser.cpp.

References getCPUInfoByName(), and Info.

Referenced by getFeaturesForCPU().

getNamedOperandIdx()

int16_t llvm::RISCV::getNamedOperandIdx	(	uint16_t	Opcode,
		uint16_t	NamedIndex
	)

Referenced by llvm::RISCVTargetLowering::AdjustInstrPostInstrSelection(), llvm::RISCVInstrInfo::finalizeInsInstrs(), hasEqualFRM(), and llvm::RISCVInstrInfo::hasReassociableSibling().

getRelocPairForSize()

static std::pair< MCFixupKind, MCFixupKind > llvm::RISCV::getRelocPairForSize ( unsigned  Size )

inlinestatic

Definition at line 87 of file RISCVFixupKinds.h.

References llvm::FirstLiteralRelocationKind, llvm_unreachable, and Size.

Referenced by llvm::RISCVAsmBackend::relaxDwarfLineAddr().

getRVVMCOpcode()

unsigned llvm::RISCV::getRVVMCOpcode

(

unsigned

RVVPseudoOpcode

)

Definition at line 4218 of file RISCVInstrInfo.cpp.

References llvm::RVV.

Referenced by llvm::RISCVInstrInfo::copyPhysRegVector(), llvm::RISCVInstrInfo::foldMemoryOperandImpl(), llvm::RISCVInstrInfo::getReassociateOperandIndices(), hasGPROut(), INITIALIZE_PASS(), llvm::RISCVInstrInfo::isReallyTriviallyReMaterializable(), llvm::isVectorMaskProducer(), IsVMerge(), and vectorPseudoHasAllNBitUsers().

getVectorLowDemandedScalarBits()

std::optional< unsigned > llvm::RISCV::getVectorLowDemandedScalarBits	(	uint16_t	Opcode,
		unsigned	Log2SEW
	)

Definition at line 4107 of file RISCVInstrInfo.cpp.

Referenced by vectorPseudoHasAllNBitUsers().

hasEqualFRM()

bool llvm::RISCV::hasEqualFRM	(	const MachineInstr &	MI1,
		const MachineInstr &	MI2
	)

Definition at line 4094 of file RISCVInstrInfo.cpp.

References llvm::MachineOperand::getImm(), getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), and llvm::MachineInstr::getOperand().

Referenced by canCombineFPFusedMultiply(), and llvm::RISCVInstrInfo::hasReassociableSibling().

hasFastScalarUnalignedAccess()

bool llvm::RISCV::hasFastScalarUnalignedAccess

(

StringRef

CPU

)

Definition at line 50 of file RISCVTargetParser.cpp.

References getCPUInfoByName(), and Info.

hasFastVectorUnalignedAccess()

bool llvm::RISCV::hasFastVectorUnalignedAccess

(

StringRef

CPU

)

Definition at line 55 of file RISCVTargetParser.cpp.

References getCPUInfoByName(), and Info.

hasValidCPUModel()

bool llvm::RISCV::hasValidCPUModel

(

StringRef

CPU

)

Definition at line 60 of file RISCVTargetParser.cpp.

References getCPUModel().

isFaultFirstLoad()

bool llvm::RISCV::isFaultFirstLoad

(

const MachineInstr &

MI

)

Definition at line 4089 of file RISCVInstrInfo.cpp.

References MI.

Referenced by lowerRISCVVMachineInstrToMCInst().

isRVVSpill()

bool llvm::RISCV::isRVVSpill

(

const MachineInstr &

MI

)

Definition at line 4038 of file RISCVInstrInfo.cpp.

References isRVVSpillForZvlsseg(), isRVVWholeLoadStore(), and MI.

Referenced by llvm::RISCVRegisterInfo::eliminateFrameIndex(), and getScavSlotsNumForRVV().

isRVVSpillForZvlsseg()

std::optional< std::pair< unsigned, unsigned > > llvm::RISCV::isRVVSpillForZvlsseg

(

unsigned

Opcode

)

Definition at line 4049 of file RISCVInstrInfo.cpp.

Referenced by isRVVSpill(), llvm::RISCVRegisterInfo::lowerVRELOAD(), and llvm::RISCVRegisterInfo::lowerVSPILL().

isSEXT_W()

bool llvm::RISCV::isSEXT_W

(

const MachineInstr &

MI

)

Definition at line 3993 of file RISCVInstrInfo.cpp.

References MI.

Referenced by llvm::RISCVInstrInfo::foldMemoryOperandImpl().

isVLKnownLE()

bool llvm::RISCV::isVLKnownLE	(	const MachineOperand &	LHS,
		const MachineOperand &	RHS
	)

Given two VL operands, do we know that LHS <= RHS?

Definition at line 4239 of file RISCVInstrInfo.cpp.

References LHS, RHS, and VLMaxSentinel.

isZEXT_B()

bool llvm::RISCV::isZEXT_B

(

const MachineInstr &

MI

)

Definition at line 4005 of file RISCVInstrInfo.cpp.

References MI.

Referenced by llvm::RISCVInstrInfo::foldMemoryOperandImpl().

isZEXT_W()

bool llvm::RISCV::isZEXT_W

(

const MachineInstr &

MI

)

Definition at line 3999 of file RISCVInstrInfo.cpp.

References MI.

Referenced by llvm::RISCVInstrInfo::foldMemoryOperandImpl().

parseCPU()

bool llvm::RISCV::parseCPU	(	StringRef	CPU,
		bool	IsRV64
	)

Definition at line 72 of file RISCVTargetParser.cpp.

References getCPUInfoByName(), and Info.

Referenced by parseTuneCPU().

parseTuneCPU()

bool llvm::RISCV::parseTuneCPU	(	StringRef	CPU,
		bool	IsRV64
	)

Definition at line 80 of file RISCVTargetParser.cpp.

References ENUM, parseCPU(), and TUNE_PROC.

Variable Documentation

FPMASK_Negative_Infinity

constexpr unsigned llvm::RISCV::FPMASK_Negative_Infinity = 0x001

staticconstexpr

Definition at line 361 of file RISCVInstrInfo.h.

FPMASK_Negative_Normal

constexpr unsigned llvm::RISCV::FPMASK_Negative_Normal = 0x002

staticconstexpr

Definition at line 362 of file RISCVInstrInfo.h.

FPMASK_Negative_Subnormal

constexpr unsigned llvm::RISCV::FPMASK_Negative_Subnormal = 0x004

staticconstexpr

Definition at line 363 of file RISCVInstrInfo.h.

FPMASK_Negative_Zero

constexpr unsigned llvm::RISCV::FPMASK_Negative_Zero = 0x008

staticconstexpr

Definition at line 364 of file RISCVInstrInfo.h.

FPMASK_Positive_Infinity

constexpr unsigned llvm::RISCV::FPMASK_Positive_Infinity = 0x080

staticconstexpr

Definition at line 368 of file RISCVInstrInfo.h.

FPMASK_Positive_Normal

constexpr unsigned llvm::RISCV::FPMASK_Positive_Normal = 0x040

staticconstexpr

Definition at line 367 of file RISCVInstrInfo.h.

FPMASK_Positive_Subnormal

constexpr unsigned llvm::RISCV::FPMASK_Positive_Subnormal = 0x020

staticconstexpr

Definition at line 366 of file RISCVInstrInfo.h.

FPMASK_Positive_Zero

constexpr unsigned llvm::RISCV::FPMASK_Positive_Zero = 0x010

staticconstexpr

Definition at line 365 of file RISCVInstrInfo.h.

FPMASK_Quiet_NaN

constexpr unsigned llvm::RISCV::FPMASK_Quiet_NaN = 0x200

staticconstexpr

Definition at line 370 of file RISCVInstrInfo.h.

FPMASK_Signaling_NaN

constexpr unsigned llvm::RISCV::FPMASK_Signaling_NaN = 0x100

staticconstexpr

Definition at line 369 of file RISCVInstrInfo.h.

PartMappings

const RegisterBankInfo::PartialMapping llvm::RISCV::PartMappings[]

Initial value:

= {
    
    {0, 32, GPRBRegBank},
    {0, 64, GPRBRegBank},
    {0, 16, FPRBRegBank},
    {0, 32, FPRBRegBank},
    {0, 64, FPRBRegBank},
    {0, 64, VRBRegBank},
    {0, 128, VRBRegBank},
    {0, 256, VRBRegBank},
    {0, 512, VRBRegBank},
    
}

Definition at line 28 of file RISCVRegisterBankInfo.cpp.

RISCVCPUInfo

constexpr CPUInfo llvm::RISCV::RISCVCPUInfo[]

constexpr

Initial value:

= {
#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN,                   FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID)                  
                                                                         
                                                                               
                                                                               
                                                                               
                                                                               
                                                                               
                                                                               
    
 
}

Definition at line 30 of file RISCVTargetParser.cpp.

Referenced by fillValidCPUArchList(), fillValidTuneCPUArchList(), and getCPUInfoByName().

RVVBitsPerBlock

constexpr unsigned llvm::RISCV::RVVBitsPerBlock = 64

staticconstexpr

Definition at line 51 of file RISCVTargetParser.h.

Referenced by llvm::RISCVRegisterInfo::adjustReg(), computeKnownBitsFromOperator(), llvm::RISCVTargetLowering::computeVLMAX(), llvm::RISCVSubtarget::expandVScale(), getContainerForFixedLengthVector(), getLMUL1Ty(), getLMUL1VT(), llvm::RISCVTTIImpl::getMaxVScale(), llvm::RISCVTargetLowering::getOptimalMemOpType(), llvm::RISCVTargetLowering::getRegClassIDForVecVT(), llvm::RISCVTTIImpl::getRegisterBitWidth(), llvm::RISCVTTIImpl::getRegUsageForType(), llvm::RISCVTargetMachine::getSubtargetImpl(), llvm::RISCVTTIImpl::getVScaleForTuning(), isValidEGW(), llvm::RISCVTargetLowering::isVScaleKnownToBeAPowerOfTwo(), lowerGetVectorLength(), llvm::RISCVTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::selectVLXSEG(), llvm::RISCVDAGToDAGISel::selectVSXSEG(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), and llvm::RISCVSubtarget::useRVVForFixedLengthVectors().

ValueMappings

const RegisterBankInfo::ValueMapping llvm::RISCV::ValueMappings[]

Definition at line 54 of file RISCVRegisterBankInfo.cpp.

Referenced by getFPValueMapping(), llvm::RISCVRegisterBankInfo::getInstrMapping(), and getVRBValueMapping().

VLMaxSentinel

constexpr int64_t llvm::RISCV::VLMaxSentinel = -1LL

staticconstexpr

Definition at line 355 of file RISCVInstrInfo.h.

Referenced by isVLKnownLE(), and llvm::RISCVDAGToDAGISel::selectVLOp().