Classes
struct	CPUInfo

struct	RISCVMaskedPseudoInfo

struct	VLEPseudo

struct	VLSEGPseudo

struct	VLX_VSXPseudo

struct	VLXSEGPseudo

struct	VSEPseudo

struct	VSSEGPseudo

struct	VSXSEGPseudo

Enumerations
enum	CPUKind : unsigned

enum	Fixups { fixup_riscv_hi20 = FirstTargetFixupKind , fixup_riscv_lo12_i , fixup_riscv_lo12_s , fixup_riscv_pcrel_hi20 , fixup_riscv_pcrel_lo12_i , fixup_riscv_pcrel_lo12_s , fixup_riscv_got_hi20 , fixup_riscv_tprel_hi20 , fixup_riscv_tprel_lo12_i , fixup_riscv_tprel_lo12_s , fixup_riscv_tprel_add , fixup_riscv_tls_got_hi20 , fixup_riscv_tls_gd_hi20 , fixup_riscv_jal , fixup_riscv_branch , fixup_riscv_rvc_jump , fixup_riscv_rvc_branch , fixup_riscv_call , fixup_riscv_call_plt , fixup_riscv_relax , fixup_riscv_align , fixup_riscv_set_8 , fixup_riscv_add_8 , fixup_riscv_sub_8 , fixup_riscv_set_16 , fixup_riscv_add_16 , fixup_riscv_sub_16 , fixup_riscv_set_32 , fixup_riscv_add_32 , fixup_riscv_sub_32 , fixup_riscv_add_64 , fixup_riscv_sub_64 , fixup_riscv_set_6b , fixup_riscv_sub_6b , fixup_riscv_invalid , NumTargetFixupKinds = fixup_riscv_invalid - FirstTargetFixupKind }

Functions
bool	checkCPUKind (CPUKind Kind, bool IsRV64)

bool	checkTuneCPUKind (CPUKind Kind, bool IsRV64)

CPUKind	parseCPUKind (StringRef CPU)

CPUKind	parseTuneCPUKind (StringRef CPU, bool IsRV64)

StringRef	getMArchFromMcpu (StringRef CPU)

void	fillValidCPUArchList (SmallVectorImpl< StringRef > &Values, bool IsRV64)

void	fillValidTuneCPUArchList (SmallVectorImpl< StringRef > &Values, bool IsRV64)

bool	getCPUFeaturesExceptStdExt (CPUKind Kind, std::vector< StringRef > &Features)

bool	isX18ReservedByDefault (const Triple &TT)

static std::pair< MCFixupKind, MCFixupKind >	getRelocPairForSize (unsigned Size)

bool	isSEXT_W (const MachineInstr &MI)

bool	isZEXT_W (const MachineInstr &MI)

bool	isZEXT_B (const MachineInstr &MI)

bool	isRVVSpill (const MachineInstr &MI)

std::optional< std::pair< unsigned, unsigned > >	isRVVSpillForZvlsseg (unsigned Opcode)

bool	isFaultFirstLoad (const MachineInstr &MI)

int16_t	getNamedOperandIdx (uint16_t Opcode, uint16_t NamedIndex)

bool	hasEqualFRM (const MachineInstr &MI1, const MachineInstr &MI2)

Variables
static constexpr unsigned	RVVBitsPerBlock = 64

static constexpr int64_t	VLMaxSentinel = -1LL

constexpr CPUInfo	RISCVCPUInfo []

Enumeration Type Documentation

◆ CPUKind

enum llvm::RISCV::CPUKind : unsigned

Definition at line 29 of file RISCVTargetParser.h.

◆ Fixups

enum llvm::RISCV::Fixups

Enumerator
fixup_riscv_hi20
fixup_riscv_lo12_i
fixup_riscv_lo12_s
fixup_riscv_pcrel_hi20
fixup_riscv_pcrel_lo12_i
fixup_riscv_pcrel_lo12_s
fixup_riscv_got_hi20
fixup_riscv_tprel_hi20
fixup_riscv_tprel_lo12_i
fixup_riscv_tprel_lo12_s
fixup_riscv_tprel_add
fixup_riscv_tls_got_hi20
fixup_riscv_tls_gd_hi20
fixup_riscv_jal
fixup_riscv_branch
fixup_riscv_rvc_jump
fixup_riscv_rvc_branch
fixup_riscv_call
fixup_riscv_call_plt
fixup_riscv_relax
fixup_riscv_align
fixup_riscv_set_8
fixup_riscv_add_8
fixup_riscv_sub_8
fixup_riscv_set_16
fixup_riscv_add_16
fixup_riscv_sub_16
fixup_riscv_set_32
fixup_riscv_add_32
fixup_riscv_sub_32
fixup_riscv_add_64
fixup_riscv_sub_64
fixup_riscv_set_6b
fixup_riscv_sub_6b
fixup_riscv_invalid
NumTargetFixupKinds

Definition at line 18 of file RISCVFixupKinds.h.

Function Documentation

◆ checkCPUKind()

bool llvm::RISCV::checkCPUKind	(	CPUKind	Kind,
		bool	IsRV64
	)

Definition at line 36 of file RISCVTargetParser.cpp.

References is64Bit(), and RISCVCPUInfo.

◆ checkTuneCPUKind()

bool llvm::RISCV::checkTuneCPUKind	(	CPUKind	Kind,
		bool	IsRV64
	)

Definition at line 42 of file RISCVTargetParser.cpp.

References is64Bit(), and RISCVCPUInfo.

◆ fillValidCPUArchList()

void llvm::RISCV::fillValidCPUArchList	(	SmallVectorImpl< StringRef > &	Values,
		bool	IsRV64
	)

Definition at line 72 of file RISCVTargetParser.cpp.

References llvm::CallingConv::C, llvm::SmallVectorImpl< T >::emplace_back(), and RISCVCPUInfo.

◆ fillValidTuneCPUArchList()

void llvm::RISCV::fillValidTuneCPUArchList	(	SmallVectorImpl< StringRef > &	Values,
		bool	IsRV64
	)

Definition at line 79 of file RISCVTargetParser.cpp.

References llvm::CallingConv::C, llvm::SmallVectorImpl< T >::emplace_back(), and RISCVCPUInfo.

◆ getCPUFeaturesExceptStdExt()

bool llvm::RISCV::getCPUFeaturesExceptStdExt	(	CPUKind	Kind,
		std::vector< StringRef > &	Features
	)

Definition at line 89 of file RISCVTargetParser.cpp.

References Info, and RISCVCPUInfo.

◆ getMArchFromMcpu()

StringRef llvm::RISCV::getMArchFromMcpu ( StringRef CPU )

Definition at line 67 of file RISCVTargetParser.cpp.

References parseCPUKind(), and RISCVCPUInfo.

◆ getNamedOperandIdx()

int16_t llvm::RISCV::getNamedOperandIdx	(	uint16_t	Opcode,
		uint16_t	NamedIndex
	)

Referenced by llvm::RISCVTargetLowering::AdjustInstrPostInstrSelection(), llvm::RISCVInstrInfo::finalizeInsInstrs(), hasEqualFRM(), and llvm::RISCVInstrInfo::hasReassociableSibling().

◆ getRelocPairForSize()

static std::pair< MCFixupKind, MCFixupKind > llvm::RISCV::getRelocPairForSize ( unsigned Size )

inlinestatic

Definition at line 114 of file RISCVFixupKinds.h.

References fixup_riscv_add_16, fixup_riscv_add_32, fixup_riscv_add_64, fixup_riscv_add_8, fixup_riscv_sub_16, fixup_riscv_sub_32, fixup_riscv_sub_64, fixup_riscv_sub_8, llvm_unreachable, and Size.

Referenced by RISCVELFStreamer::emitValueImpl(), and llvm::RISCVAsmBackend::relaxDwarfLineAddr().

◆ hasEqualFRM()

bool llvm::RISCV::hasEqualFRM	(	const MachineInstr &	MI1,
		const MachineInstr &	MI2
	)

Definition at line 2719 of file RISCVInstrInfo.cpp.

References llvm::MachineOperand::getImm(), getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), and llvm::MachineInstr::getOperand().

Referenced by canCombineFPFusedMultiply(), and llvm::RISCVInstrInfo::hasReassociableSibling().

◆ isFaultFirstLoad()

bool llvm::RISCV::isFaultFirstLoad ( const MachineInstr & MI )

Definition at line 2714 of file RISCVInstrInfo.cpp.

References MI.

Referenced by lowerRISCVVMachineInstrToMCInst().

◆ isRVVSpill()

bool llvm::RISCV::isRVVSpill ( const MachineInstr & MI )

Definition at line 2663 of file RISCVInstrInfo.cpp.

References isRVVSpillForZvlsseg(), isRVVWholeLoadStore(), and MI.

Referenced by llvm::RISCVRegisterInfo::eliminateFrameIndex(), and getScavSlotsNumForRVV().

◆ isRVVSpillForZvlsseg()

std::optional< std::pair< unsigned, unsigned > > llvm::RISCV::isRVVSpillForZvlsseg ( unsigned Opcode )

Definition at line 2674 of file RISCVInstrInfo.cpp.

Referenced by isRVVSpill(), llvm::RISCVRegisterInfo::lowerVRELOAD(), and llvm::RISCVRegisterInfo::lowerVSPILL().

◆ isSEXT_W()

bool llvm::RISCV::isSEXT_W ( const MachineInstr & MI )

Definition at line 2618 of file RISCVInstrInfo.cpp.

References MI.

Referenced by llvm::RISCVInstrInfo::foldMemoryOperandImpl().

◆ isX18ReservedByDefault()

bool llvm::RISCV::isX18ReservedByDefault ( const Triple & TT )

Definition at line 104 of file RISCVTargetParser.cpp.

Referenced by llvm::RISCVSubtarget::RISCVSubtarget().

◆ isZEXT_B()

bool llvm::RISCV::isZEXT_B ( const MachineInstr & MI )

Definition at line 2630 of file RISCVInstrInfo.cpp.

References MI.

Referenced by llvm::RISCVInstrInfo::foldMemoryOperandImpl().

◆ isZEXT_W()

bool llvm::RISCV::isZEXT_W ( const MachineInstr & MI )

Definition at line 2624 of file RISCVInstrInfo.cpp.

References MI.

Referenced by llvm::RISCVInstrInfo::foldMemoryOperandImpl().

◆ parseCPUKind()

CPUKind llvm::RISCV::parseCPUKind ( StringRef CPU )

Definition at line 52 of file RISCVTargetParser.cpp.

References llvm::StringSwitch< T, R >::Default().

Referenced by getMArchFromMcpu().

◆ parseTuneCPUKind()

CPUKind llvm::RISCV::parseTuneCPUKind	(	StringRef	CPU,
		bool	IsRV64
	)

Definition at line 59 of file RISCVTargetParser.cpp.

References llvm::StringSwitch< T, R >::Default().

Variable Documentation

◆ RISCVCPUInfo

constexpr CPUInfo llvm::RISCV::RISCVCPUInfo[]

constexpr

Initial value:

= {
#define PROC(ENUM, NAME, DEFAULT_MARCH)                              
                                   
 
}

Definition at line 30 of file RISCVTargetParser.cpp.

Referenced by checkCPUKind(), checkTuneCPUKind(), fillValidCPUArchList(), fillValidTuneCPUArchList(), getCPUFeaturesExceptStdExt(), and getMArchFromMcpu().

◆ RVVBitsPerBlock

constexpr unsigned llvm::RISCV::RVVBitsPerBlock = 64

staticconstexpr

Definition at line 27 of file RISCVTargetParser.h.

Referenced by llvm::RISCVTargetLowering::computeVLMAX(), getContainerForFixedLengthVector(), getLMUL1VT(), llvm::RISCVTTIImpl::getMaxVScale(), llvm::RISCVTTIImpl::getRegisterBitWidth(), llvm::RISCVTTIImpl::getRegUsageForType(), llvm::RISCVTargetMachine::getSubtargetImpl(), llvm::RISCVTTIImpl::getVScaleForTuning(), llvm::RISCVTargetLowering::isVScaleKnownToBeAPowerOfTwo(), llvm::RISCVTargetLowering::LowerOperation(), and llvm::RISCVTargetLowering::RISCVTargetLowering().

◆ VLMaxSentinel

constexpr int64_t llvm::RISCV::VLMaxSentinel = -1LL

staticconstexpr

Definition at line 258 of file RISCVInstrInfo.h.

Referenced by if(), and llvm::RISCVDAGToDAGISel::selectVLOp().

Classes

Enumerations

Functions

Variables

Enumeration Type Documentation

◆ CPUKind

◆ Fixups

Function Documentation

◆ checkCPUKind()

◆ checkTuneCPUKind()

◆ fillValidCPUArchList()

◆ fillValidTuneCPUArchList()

◆ getCPUFeaturesExceptStdExt()

◆ getMArchFromMcpu()

◆ getNamedOperandIdx()

◆ getRelocPairForSize()

◆ hasEqualFRM()

◆ isFaultFirstLoad()

◆ isRVVSpill()

◆ isRVVSpillForZvlsseg()

◆ isSEXT_W()

◆ isX18ReservedByDefault()

◆ isZEXT_B()

◆ isZEXT_W()

◆ parseCPUKind()

◆ parseTuneCPUKind()

Variable Documentation

◆ RISCVCPUInfo

◆ RVVBitsPerBlock

◆ VLMaxSentinel