LLVM 19.0.0git
Classes | Enumerations | Functions | Variables
llvm::RISCV Namespace Reference

Classes

struct  CPUInfo
 
struct  RISCVMaskedPseudoInfo
 
struct  VLEPseudo
 
struct  VLSEGPseudo
 
struct  VLX_VSXPseudo
 
struct  VLXSEGPseudo
 
struct  VSEPseudo
 
struct  VSSEGPseudo
 
struct  VSXSEGPseudo
 

Enumerations

enum  PartialMappingIdx {
  PMI_GPRB32 = 0 , PMI_GPRB64 = 1 , PMI_FPRB32 = 2 , PMI_FPRB64 = 3 ,
  PMI_VRB64 = 4 , PMI_VRB128 = 5 , PMI_VRB256 = 6 , PMI_VRB512 = 7
}
 
enum  ValueMappingIdx {
  InvalidIdx = 0 , GPRB32Idx = 1 , GPRB64Idx = 4 , FPRB32Idx = 7 ,
  FPRB64Idx = 10 , VRB64Idx = 13 , VRB128Idx = 16 , VRB256Idx = 19 ,
  VRB512Idx = 22
}
 
enum  Fixups {
  fixup_riscv_hi20 = FirstTargetFixupKind , fixup_riscv_lo12_i , fixup_riscv_12_i , fixup_riscv_lo12_s ,
  fixup_riscv_pcrel_hi20 , fixup_riscv_pcrel_lo12_i , fixup_riscv_pcrel_lo12_s , fixup_riscv_got_hi20 ,
  fixup_riscv_tprel_hi20 , fixup_riscv_tprel_lo12_i , fixup_riscv_tprel_lo12_s , fixup_riscv_tprel_add ,
  fixup_riscv_tls_got_hi20 , fixup_riscv_tls_gd_hi20 , fixup_riscv_jal , fixup_riscv_branch ,
  fixup_riscv_rvc_jump , fixup_riscv_rvc_branch , fixup_riscv_call , fixup_riscv_call_plt ,
  fixup_riscv_relax , fixup_riscv_align , fixup_riscv_tlsdesc_hi20 , fixup_riscv_tlsdesc_load_lo12 ,
  fixup_riscv_tlsdesc_add_lo12 , fixup_riscv_tlsdesc_call , fixup_riscv_invalid , NumTargetFixupKinds = fixup_riscv_invalid - FirstTargetFixupKind
}
 
enum  CPUKind : unsigned
 

Functions

void getFeaturesForCPU (StringRef CPU, SmallVectorImpl< std::string > &EnabledFeatures, bool NeedPlus=false)
 
bool parseCPU (StringRef CPU, bool IsRV64)
 
bool parseTuneCPU (StringRef CPU, bool IsRV64)
 
StringRef getMArchFromMcpu (StringRef CPU)
 
void fillValidCPUArchList (SmallVectorImpl< StringRef > &Values, bool IsRV64)
 
void fillValidTuneCPUArchList (SmallVectorImpl< StringRef > &Values, bool IsRV64)
 
bool hasFastUnalignedAccess (StringRef CPU)
 
static std::pair< MCFixupKind, MCFixupKind > getRelocPairForSize (unsigned Size)
 
bool isSEXT_W (const MachineInstr &MI)
 
bool isZEXT_W (const MachineInstr &MI)
 
bool isZEXT_B (const MachineInstr &MI)
 
bool isRVVSpill (const MachineInstr &MI)
 
std::optional< std::pair< unsigned, unsigned > > isRVVSpillForZvlsseg (unsigned Opcode)
 
bool isFaultFirstLoad (const MachineInstr &MI)
 
int16_t getNamedOperandIdx (uint16_t Opcode, uint16_t NamedIndex)
 
bool hasEqualFRM (const MachineInstr &MI1, const MachineInstr &MI2)
 
std::optional< unsigned > getVectorLowDemandedScalarBits (uint16_t Opcode, unsigned Log2SEW)
 
unsigned getRVVMCOpcode (unsigned RVVPseudoOpcode)
 
bool CC_RISCV (const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, RVVArgDispatcher &RVVDispatcher)
 
bool CC_RISCV_FastCC (const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, RVVArgDispatcher &RVVDispatcher)
 
bool CC_RISCV_GHC (unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
 
ArrayRef< MCPhysReg > getArgGPRs (const RISCVABI::ABI ABI)
 
static const CPUInfo * getCPUInfoByName (StringRef CPU)
 

Variables

static constexpr unsigned RVVBitsPerBlock = 64
 
const RegisterBankInfo::PartialMapping PartMappings []
 
const RegisterBankInfo::ValueMapping ValueMappings []
 
static constexpr int64_t VLMaxSentinel = -1LL
 
static constexpr unsigned FPMASK_Negative_Infinity = 0x001
 
static constexpr unsigned FPMASK_Negative_Normal = 0x002
 
static constexpr unsigned FPMASK_Negative_Subnormal = 0x004
 
static constexpr unsigned FPMASK_Negative_Zero = 0x008
 
static constexpr unsigned FPMASK_Positive_Zero = 0x010
 
static constexpr unsigned FPMASK_Positive_Subnormal = 0x020
 
static constexpr unsigned FPMASK_Positive_Normal = 0x040
 
static constexpr unsigned FPMASK_Positive_Infinity = 0x080
 
static constexpr unsigned FPMASK_Signaling_NaN = 0x100
 
static constexpr unsigned FPMASK_Quiet_NaN = 0x200
 
constexpr CPUInfo RISCVCPUInfo []
 

Enumeration Type Documentation

◆ CPUKind

enum llvm::RISCV::CPUKind : unsigned

Definition at line 23 of file RISCVTargetParser.cpp.

◆ Fixups

enum llvm::RISCV::Fixups
Enumerator
fixup_riscv_hi20 
fixup_riscv_lo12_i 
fixup_riscv_12_i 
fixup_riscv_lo12_s 
fixup_riscv_pcrel_hi20 
fixup_riscv_pcrel_lo12_i 
fixup_riscv_pcrel_lo12_s 
fixup_riscv_got_hi20 
fixup_riscv_tprel_hi20 
fixup_riscv_tprel_lo12_i 
fixup_riscv_tprel_lo12_s 
fixup_riscv_tprel_add 
fixup_riscv_tls_got_hi20 
fixup_riscv_tls_gd_hi20 
fixup_riscv_jal 
fixup_riscv_branch 
fixup_riscv_rvc_jump 
fixup_riscv_rvc_branch 
fixup_riscv_call 
fixup_riscv_call_plt 
fixup_riscv_relax 
fixup_riscv_align 
fixup_riscv_tlsdesc_hi20 
fixup_riscv_tlsdesc_load_lo12 
fixup_riscv_tlsdesc_add_lo12 
fixup_riscv_tlsdesc_call 
fixup_riscv_invalid 
NumTargetFixupKinds 

Definition at line 19 of file RISCVFixupKinds.h.

◆ PartialMappingIdx

enum llvm::RISCV::PartialMappingIdx
Enumerator
PMI_GPRB32 
PMI_GPRB64 
PMI_FPRB32 
PMI_FPRB64 
PMI_VRB64 
PMI_VRB128 
PMI_VRB256 
PMI_VRB512 

Definition at line 41 of file RISCVRegisterBankInfo.cpp.

◆ ValueMappingIdx

enum llvm::RISCV::ValueMappingIdx
Enumerator
InvalidIdx 
GPRB32Idx 
GPRB64Idx 
FPRB32Idx 
FPRB64Idx 
VRB64Idx 
VRB128Idx 
VRB256Idx 
VRB512Idx 

Definition at line 89 of file RISCVRegisterBankInfo.cpp.

Function Documentation

◆ CC_RISCV()

bool llvm::RISCV::CC_RISCV ( const DataLayout &  DL,
RISCVABI::ABI  ABI,
unsigned  ValNo,
MVT  ValVT,
MVT  LocVT,
CCValAssign::LocInfo  LocInfo,
ISD::ArgFlagsTy  ArgFlags,
CCState &  State,
bool  IsFixed,
bool  IsRet,
Type *  OrigTy,
const RISCVTargetLowering &  TLI,
RVVArgDispatcher &  RVVDispatcher 
)

Definition at line 18287 of file RISCVISelLowering.cpp.

References llvm::RISCVABI::ABI_ILP32, llvm::RISCVABI::ABI_ILP32D, llvm::RISCVABI::ABI_ILP32E, llvm::RISCVABI::ABI_ILP32F, llvm::RISCVABI::ABI_LP64, llvm::RISCVABI::ABI_LP64D, llvm::RISCVABI::ABI_LP64E, llvm::RISCVABI::ABI_LP64F, llvm::CCState::addLoc(), llvm::CCState::AllocateReg(), llvm::CCState::AllocateStack(), ArgFPR16s, ArgFPR32s, ArgFPR64s, ArgGPRs, assert(), llvm::CCValAssign::BCvt, CC_RISCVAssign2XLen(), llvm::SmallVectorImpl< T >::clear(), DL, llvm::SmallVectorBase< Size_T >::empty(), llvm::CCValAssign::Full, getArgGPRs(), llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), llvm::CCValAssign::getCustomMem(), llvm::CCValAssign::getCustomReg(), llvm::CCState::getFirstUnallocated(), llvm::CCValAssign::getMem(), llvm::RVVArgDispatcher::getNextPhysReg(), llvm::ISD::ArgFlagsTy::getNonZeroOrigAlign(), llvm::CCValAssign::getPending(), llvm::CCState::getPendingArgFlags(), llvm::CCState::getPendingLocs(), llvm::CCValAssign::getReg(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getStoreSize(), llvm::RISCVTargetLowering::getSubtarget(), llvm::RISCVSubtarget::hasVInstructions(), llvm::CCValAssign::Indirect, llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::ISD::ArgFlagsTy::isNest(), llvm::MVT::isScalableVector(), llvm::MVT::isScalarInteger(), llvm::ISD::ArgFlagsTy::isSplit(), llvm::ISD::ArgFlagsTy::isSplitEnd(), llvm::MVT::isVector(), llvm_unreachable, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorBase< Size_T >::size(), and llvm::MaybeAlign::valueOrOne().

Referenced by llvm::RISCVTargetLowering::CanLowerReturn(), llvm::RISCVCallLowering::lowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::RISCVCallLowering::lowerFormalArguments(), llvm::RISCVTargetLowering::LowerFormalArguments(), and llvm::RISCVTargetLowering::LowerReturn().

◆ CC_RISCV_FastCC()

bool llvm::RISCV::CC_RISCV_FastCC ( const DataLayout &  DL,
RISCVABI::ABI  ABI,
unsigned  ValNo,
MVT  ValVT,
MVT  LocVT,
CCValAssign::LocInfo  LocInfo,
ISD::ArgFlagsTy  ArgFlags,
CCState &  State,
bool  IsFixed,
bool  IsRet,
Type *  OrigTy,
const RISCVTargetLowering &  TLI,
RVVArgDispatcher &  RVVDispatcher 
)

Definition at line 18774 of file RISCVISelLowering.cpp.

References llvm::CCState::addLoc(), llvm::CCState::AllocateReg(), llvm::CCState::AllocateStack(), llvm::RISCVTargetLowering::getContainerForFixedLengthVector(), getFastCCArgGPRs(), llvm::CCValAssign::getMem(), llvm::RVVArgDispatcher::getNextPhysReg(), llvm::CCValAssign::getReg(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getStoreSize(), llvm::RISCVTargetLowering::getSubtarget(), llvm::RISCVSubtarget::getXLenVT(), llvm::CCValAssign::Indirect, llvm::RISCVSubtarget::is64Bit(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isVector(), and llvm::MaybeAlign::valueOrOne().

Referenced by llvm::RISCVCallLowering::lowerCall(), llvm::RISCVTargetLowering::LowerCall(), llvm::RISCVCallLowering::lowerFormalArguments(), and llvm::RISCVTargetLowering::LowerFormalArguments().

◆ CC_RISCV_GHC()

bool llvm::RISCV::CC_RISCV_GHC ( unsigned  ValNo,
MVT  ValVT,
MVT  LocVT,
CCValAssign::LocInfo  LocInfo,
ISD::ArgFlagsTy  ArgFlags,
CCState &  State 
)

Definition at line 18891 of file RISCVISelLowering.cpp.

References llvm::CCState::addLoc(), llvm::CCState::AllocateReg(), llvm::CCState::getMachineFunction(), llvm::CCValAssign::getReg(), llvm::MachineFunction::getSubtarget(), llvm::RISCVSubtarget::is64Bit(), llvm::ISD::ArgFlagsTy::isNest(), and llvm::report_fatal_error().

Referenced by llvm::RISCVTargetLowering::LowerCall(), and llvm::RISCVTargetLowering::LowerFormalArguments().

◆ fillValidCPUArchList()

void llvm::RISCV::fillValidCPUArchList ( SmallVectorImpl< StringRef > &  Values,
bool  IsRV64 
)

Definition at line 83 of file RISCVTargetParser.cpp.

References llvm::CallingConv::C, llvm::SmallVectorImpl< T >::emplace_back(), and RISCVCPUInfo.

◆ fillValidTuneCPUArchList()

void llvm::RISCV::fillValidTuneCPUArchList ( SmallVectorImpl< StringRef > &  Values,
bool  IsRV64 
)

Definition at line 90 of file RISCVTargetParser.cpp.

References llvm::CallingConv::C, llvm::SmallVectorImpl< T >::emplace_back(), and RISCVCPUInfo.

◆ getArgGPRs()

ArrayRef< MCPhysReg > llvm::RISCV::getArgGPRs ( const RISCVABI::ABI  ABI)

Definition at line 18205 of file RISCVISelLowering.cpp.

References llvm::RISCVABI::ABI_ILP32E, and llvm::RISCVABI::ABI_LP64E.

Referenced by CC_RISCV(), CC_RISCVAssign2XLen(), and llvm::RISCVTargetLowering::LowerFormalArguments().

◆ getCPUInfoByName()

static const CPUInfo * llvm::RISCV::getCPUInfoByName ( StringRef  CPU)
static

Definition at line 42 of file RISCVTargetParser.cpp.

References llvm::CallingConv::C, and RISCVCPUInfo.

Referenced by getMArchFromMcpu(), hasFastUnalignedAccess(), and parseCPU().

◆ getFeaturesForCPU()

void llvm::RISCV::getFeaturesForCPU ( StringRef  CPU,
SmallVectorImpl< std::string > &  EnabledFeatures,
bool  NeedPlus = false 
)

Definition at line 100 of file RISCVTargetParser.cpp.

References llvm::SmallVectorImpl< T >::clear(), llvm::errorToBool(), F, getMArchFromMcpu(), llvm::RISCVISAInfo::parseArchString(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ getMArchFromMcpu()

StringRef llvm::RISCV::getMArchFromMcpu ( StringRef  CPU)

Definition at line 76 of file RISCVTargetParser.cpp.

References getCPUInfoByName(), and Info.

Referenced by getFeaturesForCPU().

◆ getNamedOperandIdx()

int16_t llvm::RISCV::getNamedOperandIdx ( uint16_t  Opcode,
uint16_t  NamedIndex 
)

Referenced by llvm::RISCVTargetLowering::AdjustInstrPostInstrSelection(), llvm::RISCVInstrInfo::finalizeInsInstrs(), hasEqualFRM(), and llvm::RISCVInstrInfo::hasReassociableSibling().

◆ getRelocPairForSize()

static std::pair< MCFixupKind, MCFixupKind > llvm::RISCV::getRelocPairForSize ( unsigned  Size)
inlinestatic

Definition at line 87 of file RISCVFixupKinds.h.

References llvm::FirstLiteralRelocationKind, llvm_unreachable, and Size.

Referenced by llvm::RISCVAsmBackend::relaxDwarfLineAddr().

◆ getRVVMCOpcode()

unsigned llvm::RISCV::getRVVMCOpcode ( unsigned  RVVPseudoOpcode)

Definition at line 3677 of file RISCVInstrInfo.cpp.

References llvm::RISCVVPseudosTable::PseudoInfo::BaseInstr.

Referenced by llvm::RISCVInstrInfo::copyPhysRegVector(), INITIALIZE_PASS(), IsVMerge(), IsVMv(), and vectorPseudoHasAllNBitUsers().

◆ getVectorLowDemandedScalarBits()

std::optional< unsigned > llvm::RISCV::getVectorLowDemandedScalarBits ( uint16_t  Opcode,
unsigned  Log2SEW 
)

Definition at line 3566 of file RISCVInstrInfo.cpp.

Referenced by vectorPseudoHasAllNBitUsers().

◆ hasEqualFRM()

bool llvm::RISCV::hasEqualFRM ( const MachineInstr &  MI1,
const MachineInstr &  MI2 
)

Definition at line 3553 of file RISCVInstrInfo.cpp.

References llvm::MachineOperand::getImm(), getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), and llvm::MachineInstr::getOperand().

Referenced by canCombineFPFusedMultiply(), and llvm::RISCVInstrInfo::hasReassociableSibling().

◆ hasFastUnalignedAccess()

bool llvm::RISCV::hasFastUnalignedAccess ( StringRef  CPU)

Definition at line 49 of file RISCVTargetParser.cpp.

References getCPUInfoByName(), and Info.

◆ isFaultFirstLoad()

bool llvm::RISCV::isFaultFirstLoad ( const MachineInstr &  MI)

Definition at line 3548 of file RISCVInstrInfo.cpp.

References MI.

Referenced by lowerRISCVVMachineInstrToMCInst().

◆ isRVVSpill()

bool llvm::RISCV::isRVVSpill ( const MachineInstr &  MI)

Definition at line 3497 of file RISCVInstrInfo.cpp.

References isRVVSpillForZvlsseg(), isRVVWholeLoadStore(), and MI.

Referenced by llvm::RISCVRegisterInfo::eliminateFrameIndex(), and getScavSlotsNumForRVV().

◆ isRVVSpillForZvlsseg()

std::optional< std::pair< unsigned, unsigned > > llvm::RISCV::isRVVSpillForZvlsseg ( unsigned  Opcode)

Definition at line 3508 of file RISCVInstrInfo.cpp.

Referenced by isRVVSpill(), llvm::RISCVRegisterInfo::lowerVRELOAD(), and llvm::RISCVRegisterInfo::lowerVSPILL().

◆ isSEXT_W()

bool llvm::RISCV::isSEXT_W ( const MachineInstr &  MI)

Definition at line 3452 of file RISCVInstrInfo.cpp.

References MI.

Referenced by llvm::RISCVInstrInfo::foldMemoryOperandImpl().

◆ isZEXT_B()

bool llvm::RISCV::isZEXT_B ( const MachineInstr &  MI)

Definition at line 3464 of file RISCVInstrInfo.cpp.

References MI.

Referenced by llvm::RISCVInstrInfo::foldMemoryOperandImpl().

◆ isZEXT_W()

bool llvm::RISCV::isZEXT_W ( const MachineInstr &  MI)

Definition at line 3458 of file RISCVInstrInfo.cpp.

References MI.

Referenced by llvm::RISCVInstrInfo::foldMemoryOperandImpl().

◆ parseCPU()

bool llvm::RISCV::parseCPU ( StringRef  CPU,
bool  IsRV64 
)

Definition at line 54 of file RISCVTargetParser.cpp.

References getCPUInfoByName(), and Info.

Referenced by parseTuneCPU().

◆ parseTuneCPU()

bool llvm::RISCV::parseTuneCPU ( StringRef  CPU,
bool  IsRV64 
)

Definition at line 62 of file RISCVTargetParser.cpp.

References ENUM, parseCPU(), and TUNE_PROC.

Variable Documentation

◆ FPMASK_Negative_Infinity

constexpr unsigned llvm::RISCV::FPMASK_Negative_Infinity = 0x001
staticconstexpr

Definition at line 338 of file RISCVInstrInfo.h.

◆ FPMASK_Negative_Normal

constexpr unsigned llvm::RISCV::FPMASK_Negative_Normal = 0x002
staticconstexpr

Definition at line 339 of file RISCVInstrInfo.h.

◆ FPMASK_Negative_Subnormal

constexpr unsigned llvm::RISCV::FPMASK_Negative_Subnormal = 0x004
staticconstexpr

Definition at line 340 of file RISCVInstrInfo.h.

◆ FPMASK_Negative_Zero

constexpr unsigned llvm::RISCV::FPMASK_Negative_Zero = 0x008
staticconstexpr

Definition at line 341 of file RISCVInstrInfo.h.

◆ FPMASK_Positive_Infinity

constexpr unsigned llvm::RISCV::FPMASK_Positive_Infinity = 0x080
staticconstexpr

Definition at line 345 of file RISCVInstrInfo.h.

◆ FPMASK_Positive_Normal

constexpr unsigned llvm::RISCV::FPMASK_Positive_Normal = 0x040
staticconstexpr

Definition at line 344 of file RISCVInstrInfo.h.

◆ FPMASK_Positive_Subnormal

constexpr unsigned llvm::RISCV::FPMASK_Positive_Subnormal = 0x020
staticconstexpr

Definition at line 343 of file RISCVInstrInfo.h.

◆ FPMASK_Positive_Zero

constexpr unsigned llvm::RISCV::FPMASK_Positive_Zero = 0x010
staticconstexpr

Definition at line 342 of file RISCVInstrInfo.h.

◆ FPMASK_Quiet_NaN

constexpr unsigned llvm::RISCV::FPMASK_Quiet_NaN = 0x200
staticconstexpr

Definition at line 347 of file RISCVInstrInfo.h.

◆ FPMASK_Signaling_NaN

constexpr unsigned llvm::RISCV::FPMASK_Signaling_NaN = 0x100
staticconstexpr

Definition at line 346 of file RISCVInstrInfo.h.

◆ PartMappings

const RegisterBankInfo::PartialMapping llvm::RISCV::PartMappings[]
Initial value:
= {
{0, 32, GPRBRegBank},
{0, 64, GPRBRegBank},
{0, 32, FPRBRegBank},
{0, 64, FPRBRegBank},
{0, 64, VRBRegBank},
{0, 128, VRBRegBank},
{0, 256, VRBRegBank},
{0, 512, VRBRegBank},
}

Definition at line 28 of file RISCVRegisterBankInfo.cpp.

◆ RISCVCPUInfo

constexpr CPUInfo llvm::RISCV::RISCVCPUInfo[]
constexpr
Initial value:
= {
#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_UNALIGN)
}

Definition at line 36 of file RISCVTargetParser.cpp.

Referenced by fillValidCPUArchList(), fillValidTuneCPUArchList(), and getCPUInfoByName().

◆ RVVBitsPerBlock

constexpr unsigned llvm::RISCV::RVVBitsPerBlock = 64
staticconstexpr

Definition at line 28 of file RISCVTargetParser.h.

Referenced by computeKnownBitsFromOperator(), llvm::RISCVTargetLowering::computeVLMAX(), getContainerForFixedLengthVector(), getLMUL1VT(), llvm::RISCVTTIImpl::getMaxVScale(), llvm::RISCVTTIImpl::getRegisterBitWidth(), llvm::RISCVTTIImpl::getRegUsageForType(), llvm::RISCVTargetMachine::getSubtargetImpl(), llvm::RISCVTTIImpl::getVScaleForTuning(), isValidEGW(), llvm::RISCVTargetLowering::isVScaleKnownToBeAPowerOfTwo(), lowerGetVectorLength(), llvm::RISCVTargetLowering::LowerOperation(), and llvm::RISCVTargetLowering::RISCVTargetLowering().

◆ ValueMappings

const RegisterBankInfo::ValueMapping llvm::RISCV::ValueMappings[]

Definition at line 52 of file RISCVRegisterBankInfo.cpp.

Referenced by getFPValueMapping(), llvm::RISCVRegisterBankInfo::getInstrMapping(), and getVRBValueMapping().

◆ VLMaxSentinel

constexpr int64_t llvm::RISCV::VLMaxSentinel = -1LL
staticconstexpr

Definition at line 335 of file RISCVInstrInfo.h.

Referenced by computeInfoForInstr(), and llvm::RISCVDAGToDAGISel::selectVLOp().

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