Classes
struct	CPUInfo

struct	RISCVMaskedPseudoInfo

struct	VLEPseudo

struct	VLSEGPseudo

struct	VLX_VSXPseudo

struct	VLXSEGPseudo

struct	VSEPseudo

struct	VSSEGPseudo

struct	VSXSEGPseudo

Enumerations
enum	CPUKind : unsigned

enum	FeatureKind : unsigned { FK_INVALID = 0, FK_NONE = 1, FK_64BIT = 1 << 2 }

enum	Fixups { fixup_riscv_hi20 = FirstTargetFixupKind, fixup_riscv_lo12_i, fixup_riscv_lo12_s, fixup_riscv_pcrel_hi20, fixup_riscv_pcrel_lo12_i, fixup_riscv_pcrel_lo12_s, fixup_riscv_got_hi20, fixup_riscv_tprel_hi20, fixup_riscv_tprel_lo12_i, fixup_riscv_tprel_lo12_s, fixup_riscv_tprel_add, fixup_riscv_tls_got_hi20, fixup_riscv_tls_gd_hi20, fixup_riscv_jal, fixup_riscv_branch, fixup_riscv_rvc_jump, fixup_riscv_rvc_branch, fixup_riscv_call, fixup_riscv_call_plt, fixup_riscv_relax, fixup_riscv_align, fixup_riscv_set_8, fixup_riscv_add_8, fixup_riscv_sub_8, fixup_riscv_set_16, fixup_riscv_add_16, fixup_riscv_sub_16, fixup_riscv_set_32, fixup_riscv_add_32, fixup_riscv_sub_32, fixup_riscv_add_64, fixup_riscv_sub_64, fixup_riscv_set_6b, fixup_riscv_sub_6b, fixup_riscv_invalid, NumTargetFixupKinds = fixup_riscv_invalid - FirstTargetFixupKind }

Functions
bool	checkCPUKind (CPUKind Kind, bool IsRV64)

bool	checkTuneCPUKind (CPUKind Kind, bool IsRV64)

CPUKind	parseCPUKind (StringRef CPU)

CPUKind	parseTuneCPUKind (StringRef CPU, bool IsRV64)

StringRef	getMArchFromMcpu (StringRef CPU)

void	fillValidCPUArchList (SmallVectorImpl< StringRef > &Values, bool IsRV64)
	Provide a list of valid CPU names. More...

void	fillValidTuneCPUArchList (SmallVectorImpl< StringRef > &Values, bool IsRV64)

bool	getCPUFeaturesExceptStdExt (CPUKind Kind, std::vector< StringRef > &Features)

bool	isSEXT_W (const MachineInstr &MI)

bool	isZEXT_W (const MachineInstr &MI)

bool	isZEXT_B (const MachineInstr &MI)

bool	isRVVSpill (const MachineInstr &MI)

Optional< std::pair< unsigned, unsigned > >	isRVVSpillForZvlsseg (unsigned Opcode)

bool	isFaultFirstLoad (const MachineInstr &MI)

int16_t	getNamedOperandIdx (uint16_t Opcode, uint16_t NamedIndex)

bool	hasEqualFRM (const MachineInstr &MI1, const MachineInstr &MI2)

Variables
static constexpr unsigned	RVVBitsPerBlock = 64

constexpr CPUInfo	RISCVCPUInfo []

static constexpr int64_t	VLMaxSentinel = -1LL

Enumeration Type Documentation

◆ CPUKind

enum llvm::RISCV::CPUKind : unsigned

Definition at line 163 of file TargetParser.h.

◆ FeatureKind

enum llvm::RISCV::FeatureKind : unsigned

Enumerator
FK_INVALID
FK_NONE
FK_64BIT

Definition at line 169 of file TargetParser.h.

◆ Fixups

enum llvm::RISCV::Fixups

Enumerator
fixup_riscv_hi20
fixup_riscv_lo12_i
fixup_riscv_lo12_s
fixup_riscv_pcrel_hi20
fixup_riscv_pcrel_lo12_i
fixup_riscv_pcrel_lo12_s
fixup_riscv_got_hi20
fixup_riscv_tprel_hi20
fixup_riscv_tprel_lo12_i
fixup_riscv_tprel_lo12_s
fixup_riscv_tprel_add
fixup_riscv_tls_got_hi20
fixup_riscv_tls_gd_hi20
fixup_riscv_jal
fixup_riscv_branch
fixup_riscv_rvc_jump
fixup_riscv_rvc_branch
fixup_riscv_call
fixup_riscv_call_plt
fixup_riscv_relax
fixup_riscv_align
fixup_riscv_set_8
fixup_riscv_add_8
fixup_riscv_sub_8
fixup_riscv_set_16
fixup_riscv_add_16
fixup_riscv_sub_16
fixup_riscv_set_32
fixup_riscv_add_32
fixup_riscv_sub_32
fixup_riscv_add_64
fixup_riscv_sub_64
fixup_riscv_set_6b
fixup_riscv_sub_6b
fixup_riscv_invalid
NumTargetFixupKinds

Definition at line 17 of file RISCVFixupKinds.h.

Function Documentation

◆ checkCPUKind()

bool llvm::RISCV::checkCPUKind	(	CPUKind	Kind,
		bool	IsRV64
	)

Definition at line 272 of file TargetParser.cpp.

References is64Bit(), and RISCVCPUInfo.

◆ checkTuneCPUKind()

bool llvm::RISCV::checkTuneCPUKind	(	CPUKind	Kind,
		bool	IsRV64
	)

Definition at line 278 of file TargetParser.cpp.

References is64Bit(), and RISCVCPUInfo.

◆ fillValidCPUArchList()

void llvm::RISCV::fillValidCPUArchList	(	SmallVectorImpl< StringRef > &	Values,
		bool	IsRV64
	)

Provide a list of valid CPU names.

If Only64Bit is true, the list will only contain 64-bit capable CPUs.

Definition at line 306 of file TargetParser.cpp.

References llvm::SmallVectorImpl< T >::emplace_back(), P, Processors, and RISCVCPUInfo.

◆ fillValidTuneCPUArchList()

void llvm::RISCV::fillValidTuneCPUArchList	(	SmallVectorImpl< StringRef > &	Values,
		bool	IsRV64
	)

Definition at line 313 of file TargetParser.cpp.

References llvm::SmallVectorImpl< T >::emplace_back(), and RISCVCPUInfo.

◆ getCPUFeaturesExceptStdExt()

bool llvm::RISCV::getCPUFeaturesExceptStdExt	(	CPUKind	Kind,
		std::vector< StringRef > &	Features
	)

Definition at line 323 of file TargetParser.cpp.

References llvm::LoongArch::FK_64BIT, llvm::LoongArch::FK_INVALID, and RISCVCPUInfo.

◆ getMArchFromMcpu()

StringRef llvm::RISCV::getMArchFromMcpu ( StringRef CPU )

Definition at line 301 of file TargetParser.cpp.

References parseCPUKind(), and RISCVCPUInfo.

◆ getNamedOperandIdx()

int16_t llvm::RISCV::getNamedOperandIdx	(	uint16_t	Opcode,
		uint16_t	NamedIndex
	)

Referenced by llvm::RISCVInstrInfo::finalizeInsInstrs(), and hasEqualFRM().

◆ hasEqualFRM()

bool llvm::RISCV::hasEqualFRM	(	const MachineInstr &	MI1,
		const MachineInstr &	MI2
	)

Definition at line 2454 of file RISCVInstrInfo.cpp.

References llvm::MachineOperand::getImm(), getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), and llvm::MachineInstr::getOperand().

Referenced by canCombineFPFusedMultiply(), and canReassociate().

◆ isFaultFirstLoad()

bool llvm::RISCV::isFaultFirstLoad ( const MachineInstr & MI )

Definition at line 2449 of file RISCVInstrInfo.cpp.

References MI.

Referenced by lowerRISCVVMachineInstrToMCInst().

◆ isRVVSpill()

bool llvm::RISCV::isRVVSpill ( const MachineInstr & MI )

Definition at line 2398 of file RISCVInstrInfo.cpp.

References isRVVSpillForZvlsseg(), isRVVWholeLoadStore(), and MI.

Referenced by llvm::RISCVRegisterInfo::eliminateFrameIndex(), and getScavSlotsNumForRVV().

◆ isRVVSpillForZvlsseg()

Optional< std::pair< unsigned, unsigned > > llvm::RISCV::isRVVSpillForZvlsseg ( unsigned Opcode )

Definition at line 2409 of file RISCVInstrInfo.cpp.

References llvm::None.

Referenced by llvm::RISCVRegisterInfo::eliminateFrameIndex(), and isRVVSpill().

◆ isSEXT_W()

bool llvm::RISCV::isSEXT_W ( const MachineInstr & MI )

Definition at line 2353 of file RISCVInstrInfo.cpp.

References MI.

Referenced by llvm::RISCVInstrInfo::foldMemoryOperandImpl().

◆ isZEXT_B()

bool llvm::RISCV::isZEXT_B ( const MachineInstr & MI )

Definition at line 2365 of file RISCVInstrInfo.cpp.

References MI.

Referenced by llvm::RISCVInstrInfo::foldMemoryOperandImpl().

◆ isZEXT_W()

bool llvm::RISCV::isZEXT_W ( const MachineInstr & MI )

Definition at line 2359 of file RISCVInstrInfo.cpp.

References MI.

Referenced by llvm::RISCVInstrInfo::foldMemoryOperandImpl().

◆ parseCPUKind()

CPUKind llvm::RISCV::parseCPUKind ( StringRef CPU )

Definition at line 286 of file TargetParser.cpp.

References llvm::StringSwitch< T, R >::Default().

Referenced by getMArchFromMcpu().

◆ parseTuneCPUKind()

CPUKind llvm::RISCV::parseTuneCPUKind	(	StringRef	CPU,
		bool	IsRV64
	)

Definition at line 293 of file TargetParser.cpp.

References llvm::StringSwitch< T, R >::Default().

Variable Documentation

◆ RISCVCPUInfo

constexpr CPUInfo llvm::RISCV::RISCVCPUInfo[]

constexpr

Initial value:

= {
#define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH)                              
 
 
}

Definition at line 266 of file TargetParser.cpp.

Referenced by checkCPUKind(), checkTuneCPUKind(), fillValidCPUArchList(), fillValidTuneCPUArchList(), getCPUFeaturesExceptStdExt(), and getMArchFromMcpu().

◆ RVVBitsPerBlock

constexpr unsigned llvm::RISCV::RVVBitsPerBlock = 64

staticconstexpr

Definition at line 161 of file TargetParser.h.

Referenced by llvm::RISCVTargetLowering::computeVLMAX(), getContainerForFixedLengthVector(), getLMUL1VT(), llvm::RISCVTTIImpl::getMaxVScale(), llvm::RISCVTTIImpl::getRegisterBitWidth(), llvm::RISCVTTIImpl::getRegUsageForType(), llvm::RISCVTTIImpl::getVScaleForTuning(), llvm::RISCVTargetLowering::isVScaleKnownToBeAPowerOfTwo(), llvm::RISCVTargetLowering::LowerOperation(), and llvm::RISCVTargetLowering::RISCVTargetLowering().

◆ VLMaxSentinel

constexpr int64_t llvm::RISCV::VLMaxSentinel = -1LL

staticconstexpr

Definition at line 232 of file RISCVInstrInfo.h.

Referenced by if(), and llvm::RISCVDAGToDAGISel::selectVLOp().

Classes

Enumerations

Functions

Variables

Enumeration Type Documentation

◆ CPUKind

◆ FeatureKind

◆ Fixups

Function Documentation

◆ checkCPUKind()

◆ checkTuneCPUKind()

◆ fillValidCPUArchList()

◆ fillValidTuneCPUArchList()

◆ getCPUFeaturesExceptStdExt()

◆ getMArchFromMcpu()

◆ getNamedOperandIdx()

◆ hasEqualFRM()

◆ isFaultFirstLoad()

◆ isRVVSpill()

◆ isRVVSpillForZvlsseg()

◆ isSEXT_W()

◆ isZEXT_B()

◆ isZEXT_W()

◆ parseCPUKind()

◆ parseTuneCPUKind()

Variable Documentation

◆ RISCVCPUInfo

◆ RVVBitsPerBlock

◆ VLMaxSentinel