LLVM
15.0.0git
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Classes | |
struct | CPUInfo |
struct | RISCVMaskedPseudoInfo |
struct | VLEPseudo |
struct | VLSEGPseudo |
struct | VLX_VSXPseudo |
struct | VLXSEGPseudo |
struct | VSEPseudo |
struct | VSSEGPseudo |
struct | VSXSEGPseudo |
Enumerations | |
enum | CPUKind : unsigned |
enum | FeatureKind : unsigned { FK_INVALID = 0, FK_NONE = 1, FK_64BIT = 1 << 2 } |
enum | Fixups { fixup_riscv_hi20 = FirstTargetFixupKind, fixup_riscv_lo12_i, fixup_riscv_lo12_s, fixup_riscv_pcrel_hi20, fixup_riscv_pcrel_lo12_i, fixup_riscv_pcrel_lo12_s, fixup_riscv_got_hi20, fixup_riscv_tprel_hi20, fixup_riscv_tprel_lo12_i, fixup_riscv_tprel_lo12_s, fixup_riscv_tprel_add, fixup_riscv_tls_got_hi20, fixup_riscv_tls_gd_hi20, fixup_riscv_jal, fixup_riscv_branch, fixup_riscv_rvc_jump, fixup_riscv_rvc_branch, fixup_riscv_call, fixup_riscv_call_plt, fixup_riscv_relax, fixup_riscv_align, fixup_riscv_set_8, fixup_riscv_add_8, fixup_riscv_sub_8, fixup_riscv_set_16, fixup_riscv_add_16, fixup_riscv_sub_16, fixup_riscv_set_32, fixup_riscv_add_32, fixup_riscv_sub_32, fixup_riscv_add_64, fixup_riscv_sub_64, fixup_riscv_set_6b, fixup_riscv_sub_6b, fixup_riscv_invalid, NumTargetFixupKinds = fixup_riscv_invalid - FirstTargetFixupKind } |
Functions | |
bool | checkCPUKind (CPUKind Kind, bool IsRV64) |
bool | checkTuneCPUKind (CPUKind Kind, bool IsRV64) |
CPUKind | parseCPUKind (StringRef CPU) |
CPUKind | parseTuneCPUKind (StringRef CPU, bool IsRV64) |
StringRef | getMArchFromMcpu (StringRef CPU) |
void | fillValidCPUArchList (SmallVectorImpl< StringRef > &Values, bool IsRV64) |
Provide a list of valid CPU names. More... | |
void | fillValidTuneCPUArchList (SmallVectorImpl< StringRef > &Values, bool IsRV64) |
bool | getCPUFeaturesExceptStdExt (CPUKind Kind, std::vector< StringRef > &Features) |
StringRef | resolveTuneCPUAlias (StringRef TuneCPU, bool IsRV64) |
int16_t | getNamedOperandIdx (uint16_t Opcode, uint16_t NamedIndex) |
Variables | |
constexpr CPUInfo | RISCVCPUInfo [] |
static constexpr int64_t | VLMaxSentinel = -1LL |
static constexpr unsigned | RVVBitsPerBlock = 64 |
enum llvm::RISCV::CPUKind : unsigned |
Definition at line 160 of file TargetParser.h.
enum llvm::RISCV::FeatureKind : unsigned |
Enumerator | |
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FK_INVALID | |
FK_NONE | |
FK_64BIT |
Definition at line 165 of file TargetParser.h.
enum llvm::RISCV::Fixups |
Definition at line 18 of file RISCVFixupKinds.h.
bool llvm::RISCV::checkCPUKind | ( | CPUKind | Kind, |
bool | IsRV64 | ||
) |
Definition at line 272 of file TargetParser.cpp.
References is64Bit(), and RISCVCPUInfo.
bool llvm::RISCV::checkTuneCPUKind | ( | CPUKind | Kind, |
bool | IsRV64 | ||
) |
Definition at line 278 of file TargetParser.cpp.
References is64Bit(), and RISCVCPUInfo.
void llvm::RISCV::fillValidCPUArchList | ( | SmallVectorImpl< StringRef > & | Values, |
bool | IsRV64 | ||
) |
Provide a list of valid CPU names.
If Only64Bit
is true, the list will only contain 64-bit capable CPUs.
Definition at line 312 of file TargetParser.cpp.
References llvm::SmallVectorImpl< T >::emplace_back(), P, Processors, and RISCVCPUInfo.
void llvm::RISCV::fillValidTuneCPUArchList | ( | SmallVectorImpl< StringRef > & | Values, |
bool | IsRV64 | ||
) |
Definition at line 319 of file TargetParser.cpp.
References llvm::SmallVectorImpl< T >::emplace_back(), and RISCVCPUInfo.
Definition at line 329 of file TargetParser.cpp.
References FK_64BIT, FK_INVALID, and RISCVCPUInfo.
Definition at line 307 of file TargetParser.cpp.
References parseCPUKind(), and RISCVCPUInfo.
Definition at line 284 of file TargetParser.cpp.
References llvm::StringSwitch< T, R >::Default().
Referenced by getMArchFromMcpu().
Definition at line 298 of file TargetParser.cpp.
References llvm::StringSwitch< T, R >::Default(), and resolveTuneCPUAlias().
Definition at line 291 of file TargetParser.cpp.
References llvm::StringSwitch< T, R >::Default().
Referenced by parseTuneCPUKind().
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constexpr |
Definition at line 266 of file TargetParser.cpp.
Referenced by checkCPUKind(), checkTuneCPUKind(), fillValidCPUArchList(), fillValidTuneCPUArchList(), getCPUFeaturesExceptStdExt(), and getMArchFromMcpu().
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staticconstexpr |
Definition at line 322 of file RISCVISelLowering.h.
Referenced by llvm::RISCVTargetLowering::computeVLMAX(), getContainerForFixedLengthVector(), getLMUL1VT(), llvm::RISCVTTIImpl::getMaxVScale(), llvm::RISCVTTIImpl::getRegisterBitWidth(), llvm::RISCVTTIImpl::getRegUsageForType(), and llvm::RISCVTargetLowering::LowerOperation().
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staticconstexpr |
Definition at line 198 of file RISCVInstrInfo.h.
Referenced by computeInfoForInstr(), and llvm::RISCVDAGToDAGISel::selectVLOp().