LLVM 17.0.0git
RISCVISelLowering.h
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1//===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that RISCV uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
15#define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
16
17#include "RISCV.h"
22#include <optional>
23
24namespace llvm {
25class RISCVSubtarget;
26struct RISCVRegisterInfo;
27namespace RISCVISD {
28enum NodeType : unsigned {
35 /// Select with condition operator - This selects between a true value and
36 /// a false value (ops #3 and #4) based on the boolean result of comparing
37 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
38 /// condition code in op #2, a XLenVT constant from the ISD::CondCode enum.
39 /// The lhs and rhs are XLenVT integers. The true and false values can be
40 /// integer or floating point.
46
47 // Add the Lo 12 bits from an address. Selected to ADDI.
49 // Get the Hi 20 bits from an address. Selected to LUI.
51
52 // Represents an AUIPC+ADDI pair. Selected to PseudoLLA.
54
55 // Selected as PseudoAddTPRel. Used to emit a TP-relative relocation.
57
58 // Load address.
60
61 // Multiply high for signedxunsigned.
63 // RV64I shifts, directly matching the semantics of the named RISC-V
64 // instructions.
68 // 32-bit operations from RV64M that can't be simply matched with a pattern
69 // at instruction selection time. These have undefined behavior for division
70 // by 0 or overflow (divw) like their target independent counterparts.
74 // RV64IB rotates, directly matching the semantics of the named RISC-V
75 // instructions.
78 // RV64IZbb bit counting instructions directly matching the semantics of the
79 // named RISC-V instructions.
82
83 // RV64IZbb absolute value for i32. Expanded to (max (negw X), X) during isel.
85
86 // FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as
87 // XLEN is the only legal integer width.
88 //
89 // FMV_H_X matches the semantics of the FMV.H.X.
90 // FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result.
91 // FMV_X_SIGNEXTH is similar to FMV.X.H and has a sign-extended result.
92 // FMV_W_X_RV64 matches the semantics of the FMV.W.X.
93 // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result.
94 //
95 // This is a more convenient semantic for producing dagcombines that remove
96 // unnecessary GPR->FPR->GPR moves.
102 // FP to XLen int conversions. Corresponds to fcvt.l(u).s/d/h on RV64 and
103 // fcvt.w(u).s/d/h on RV32. Unlike FP_TO_S/UINT these saturate out of
104 // range inputs. These are used for FP_TO_S/UINT_SAT lowering. Rounding mode
105 // is passed as a TargetConstant operand using the RISCVFPRndMode enum.
108 // FP to 32 bit int conversions for RV64. These are used to keep track of the
109 // result being sign extended to 64 bit. These saturate out of range inputs.
110 // Used for FP_TO_S/UINT and FP_TO_S/UINT_SAT lowering. Rounding mode
111 // is passed as a TargetConstant operand using the RISCVFPRndMode enum.
114
115 // Rounds an FP value to its corresponding integer in the same FP format.
116 // First operand is the value to round, the second operand is the largest
117 // integer that can be represented exactly in the FP format. This will be
118 // expanded into multiple instructions and basic blocks with a custom
119 // inserter.
121
122 // READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target
123 // (returns (Lo, Hi)). It takes a chain operand.
125 // brev8, orc.b, zip, and unzip from Zbb and Zbkb. All operands are i32 or
126 // XLenVT.
131 // Vector Extension
132 // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand
133 // for the VL value to be used for the operation. The first operand is
134 // passthru operand.
136 // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand
137 // for the VL value to be used for the operation. The first operand is
138 // passthru operand.
140 // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign
141 // extended from the vector element size.
143 // VMV_S_X_VL matches the semantics of vmv.s.x. It carries a VL operand.
145 // VFMV_S_F_VL matches the semantics of vfmv.s.f. It carries a VL operand.
147 // Splats an 64-bit value that has been split into two i32 parts. This is
148 // expanded late to two scalar stores and a stride 0 vector load.
149 // The first operand is passthru operand.
151 // Read VLENB CSR
153 // Truncates a RVV integer vector by one power-of-two. Carries both an extra
154 // mask and VL operand.
156 // Matches the semantics of vslideup/vslidedown. The first operand is the
157 // pass-thru operand, the second is the source vector, the third is the
158 // XLenVT index (either constant or non-constant), the fourth is the mask
159 // and the fifth the VL.
162 // Matches the semantics of vslide1up/slide1down. The first operand is
163 // passthru operand, the second is source vector, third is the XLenVT scalar
164 // value. The fourth and fifth operands are the mask and VL operands.
167 // Matches the semantics of the vid.v instruction, with a mask and VL
168 // operand.
170 // Matches the semantics of the vfcnvt.rod function (Convert double-width
171 // float to single-width float, rounding towards odd). Takes a double-width
172 // float vector and produces a single-width float vector. Also has a mask and
173 // VL operand.
175 // These nodes match the semantics of the corresponding RVV vector reduction
176 // instructions. They produce a vector result which is the reduction
177 // performed over the second vector operand plus the first element of the
178 // third vector operand. The first operand is the pass-thru operand. The
179 // second operand is an unconstrained vector type, and the result, first, and
180 // third operand's types are expected to be the corresponding full-width
181 // LMUL=1 type for the second operand:
182 // nxv8i8 = vecreduce_add nxv8i8, nxv32i8, nxv8i8
183 // nxv2i32 = vecreduce_add nxv2i32, nxv8i32, nxv2i32
184 // The different in types does introduce extra vsetvli instructions but
185 // similarly it reduces the number of registers consumed per reduction.
186 // Also has a mask and VL operand.
199
200 // Vector binary ops with a merge as a third operand, a mask as a fourth
201 // operand, and VL as a fifth operand.
219
224
233
234 // Vector unary ops with a mask as a second operand and VL as a third operand.
238 FCOPYSIGN_VL, // Has a merge operand
244 VFCVT_RM_X_F_VL, // Has a rounding mode operand.
245 VFCVT_RM_XU_F_VL, // Has a rounding mode operand.
248 VFCVT_RM_F_X_VL, // Has a rounding mode operand.
249 VFCVT_RM_F_XU_VL, // Has a rounding mode operand.
252
253 // Vector FMA ops with a mask as a fourth operand and VL as a fifth operand.
258
259 // Widening instructions with a merge value a third operand, a mask as a
260 // fourth operand, and VL as a fifth operand.
272
274
275 // Vector compare producing a mask. Fourth operand is input mask. Fifth
276 // operand is VL.
278
279 // Vector select with an additional VL operand. This operation is unmasked.
281 // Vector select with operand #2 (the value when the condition is false) tied
282 // to the destination and an additional VL operand. This operation is
283 // unmasked.
285
286 // Mask binary operators.
290
291 // Set mask vector to all zeros or ones.
294
295 // Matches the semantics of vrgather.vx and vrgather.vv with extra operands
296 // for passthru and VL. Operands are (src, index, mask, passthru, vl).
300
301 // Vector sign/zero extend with additional mask & VL operands.
304
305 // vcpop.m with additional mask and VL operands.
307
308 // vfirst.m with additional mask and VL operands.
310
311 // Reads value of CSR.
312 // The first operand is a chain pointer. The second specifies address of the
313 // required CSR. Two results are produced, the read value and the new chain
314 // pointer.
316 // Write value to CSR.
317 // The first operand is a chain pointer, the second specifies address of the
318 // required CSR and the third is the value to write. The result is the new
319 // chain pointer.
321 // Read and write value of CSR.
322 // The first operand is a chain pointer, the second specifies address of the
323 // required CSR and the third is the value to write. Two results are produced,
324 // the value read before the modification and the new chain pointer.
326
327 // FP to 32 bit int conversions for RV64. These are used to keep track of the
328 // result being sign extended to 64 bit. These saturate out of range inputs.
331
332 // WARNING: Do not add anything in the end unless you want the node to
333 // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
334 // opcodes will be thought as target memory ops!
335
336 // Load address.
339};
340} // namespace RISCVISD
341
343 const RISCVSubtarget &Subtarget;
344
345public:
346 explicit RISCVTargetLowering(const TargetMachine &TM,
347 const RISCVSubtarget &STI);
348
349 const RISCVSubtarget &getSubtarget() const { return Subtarget; }
350
351 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
352 MachineFunction &MF,
353 unsigned Intrinsic) const override;
354 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
355 unsigned AS,
356 Instruction *I = nullptr) const override;
357 bool isLegalICmpImmediate(int64_t Imm) const override;
358 bool isLegalAddImmediate(int64_t Imm) const override;
359 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
360 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
361 bool isZExtFree(SDValue Val, EVT VT2) const override;
362 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
363 bool signExtendConstant(const ConstantInt *CI) const override;
364 bool isCheapToSpeculateCttz(Type *Ty) const override;
365 bool isCheapToSpeculateCtlz(Type *Ty) const override;
366 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
367 bool hasAndNotCompare(SDValue Y) const override;
368 bool hasBitTest(SDValue X, SDValue Y) const override;
371 unsigned OldShiftOpcode, unsigned NewShiftOpcode,
372 SelectionDAG &DAG) const override;
373 /// Return true if the (vector) instruction I will be lowered to an instruction
374 /// with a scalar splat operand for the given Operand number.
375 bool canSplatOperand(Instruction *I, int Operand) const;
376 /// Return true if a vector instruction will lower to a target instruction
377 /// able to splat the given operand.
378 bool canSplatOperand(unsigned Opcode, int Operand) const;
380 SmallVectorImpl<Use *> &Ops) const override;
381 bool shouldScalarizeBinop(SDValue VecOp) const override;
382 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
383 bool isFPImmLegal(const APFloat &Imm, EVT VT,
384 bool ForCodeSize) const override;
385 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
386 unsigned Index) const override;
387
388 bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
389
390 bool preferScalarizeSplat(unsigned Opc) const override;
391
392 bool softPromoteHalfType() const override { return true; }
393
394 /// Return the register type for a given MVT, ensuring vectors are treated
395 /// as a series of gpr sized integers.
397 EVT VT) const override;
398
399 /// Return the number of registers for a given MVT, ensuring vectors are
400 /// treated as a series of gpr sized integers.
403 EVT VT) const override;
404
405 bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode,
406 EVT VT) const override;
407
408 /// Return true if the given shuffle mask can be codegen'd directly, or if it
409 /// should be stack expanded.
410 bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
411
412 bool hasBitPreservingFPLogic(EVT VT) const override;
413 bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override {
414 // If the pair to store is a mixture of float and int values, we will
415 // save two bitwise instructions and one float-to-int instruction and
416 // increase one store instruction. There is potentially a more
417 // significant benefit because it avoids the float->int domain switch
418 // for input value. So It is more likely a win.
419 if ((LTy.isFloatingPoint() && HTy.isInteger()) ||
420 (LTy.isInteger() && HTy.isFloatingPoint()))
421 return true;
422 // If the pair only contains int values, we will save two bitwise
423 // instructions and increase one store instruction (costing one more
424 // store buffer). Since the benefit is more blurred we leave such a pair
425 // out until we get testcase to prove it is a win.
426 return false;
427 }
428 bool
430 unsigned DefinedValues) const override;
431
432 // Provide custom lowering hooks for some operations.
433 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
435 SelectionDAG &DAG) const override;
436
437 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
438
440 const APInt &DemandedElts,
441 TargetLoweringOpt &TLO) const override;
442
444 KnownBits &Known,
445 const APInt &DemandedElts,
446 const SelectionDAG &DAG,
447 unsigned Depth) const override;
449 const APInt &DemandedElts,
450 const SelectionDAG &DAG,
451 unsigned Depth) const override;
452
453 const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const override;
454
455 // This method returns the name of a target specific DAG node.
456 const char *getTargetNodeName(unsigned Opcode) const override;
457
458 ConstraintType getConstraintType(StringRef Constraint) const override;
459
460 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
461
462 std::pair<unsigned, const TargetRegisterClass *>
464 StringRef Constraint, MVT VT) const override;
465
466 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
467 std::vector<SDValue> &Ops,
468 SelectionDAG &DAG) const override;
469
472 MachineBasicBlock *BB) const override;
473
475 SDNode *Node) const override;
476
478 EVT VT) const override;
479
480 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
481 return VT.isScalarInteger();
482 }
483 bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
484
485 bool shouldInsertFencesForAtomic(const Instruction *I) const override {
486 return isa<LoadInst>(I) || isa<StoreInst>(I);
487 }
489 AtomicOrdering Ord) const override;
491 AtomicOrdering Ord) const override;
492
494 EVT VT) const override;
495
497 return ISD::SIGN_EXTEND;
498 }
499
501 return ISD::SIGN_EXTEND;
502 }
503
506 unsigned ExpansionFactor) const override {
510 ExpansionFactor);
511 }
512
514 CombineLevel Level) const override;
515
516 /// If a physical register, this returns the register that receives the
517 /// exception address on entry to an EH pad.
519 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
520
521 /// If a physical register, this returns the register that receives the
522 /// exception typeid on entry to a landing pad.
524 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
525
526 bool shouldExtendTypeInLibCall(EVT Type) const override;
527 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
528
529 /// Returns the register with the specified architectural or ABI name. This
530 /// method is necessary to lower the llvm.read_register.* and
531 /// llvm.write_register.* intrinsics. Allocatable registers must be reserved
532 /// with the clang -ffixed-xX flag for access to be allowed.
533 Register getRegisterByName(const char *RegName, LLT VT,
534 const MachineFunction &MF) const override;
535
536 // Lower incoming arguments, copy physregs into vregs
538 bool IsVarArg,
540 const SDLoc &DL, SelectionDAG &DAG,
541 SmallVectorImpl<SDValue> &InVals) const override;
543 bool IsVarArg,
545 LLVMContext &Context) const override;
546 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
548 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
549 SelectionDAG &DAG) const override;
551 SmallVectorImpl<SDValue> &InVals) const override;
552
554 Type *Ty) const override;
555 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
556 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
557 bool shouldConsiderGEPOffsetSplit() const override { return true; }
558
559 bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
560 SDValue C) const override;
561
563 SDValue ConstNode) const override;
564
566 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
568 Value *AlignedAddr, Value *Incr,
569 Value *Mask, Value *ShiftAmt,
570 AtomicOrdering Ord) const override;
575 Value *AlignedAddr, Value *CmpVal,
576 Value *NewVal, Value *Mask,
577 AtomicOrdering Ord) const override;
578
579 /// Returns true if the target allows unaligned memory accesses of the
580 /// specified type.
582 EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
584 unsigned *Fast = nullptr) const override;
585
587 SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
588 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
589 const override;
590
592 SelectionDAG & DAG, const SDLoc &DL, const SDValue *Parts,
593 unsigned NumParts, MVT PartVT, EVT ValueVT,
594 std::optional<CallingConv::ID> CC) const override;
595
596 static RISCVII::VLMUL getLMUL(MVT VT);
597 inline static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize,
598 unsigned MinSize) {
599 // Original equation:
600 // VLMAX = (VectorBits / EltSize) * LMUL
601 // where LMUL = MinSize / RISCV::RVVBitsPerBlock
602 // The following equations have been reordered to prevent loss of precision
603 // when calculating fractional LMUL.
604 return ((VectorBits / EltSize) * MinSize) / RISCV::RVVBitsPerBlock;
605 };
606 static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul);
607 static unsigned getSubregIndexByMVT(MVT VT, unsigned Index);
608 static unsigned getRegClassIDForVecVT(MVT VT);
609 static std::pair<unsigned, unsigned>
611 unsigned InsertExtractIdx,
612 const RISCVRegisterInfo *TRI);
614
615 bool shouldRemoveExtendFromGSIndex(EVT IndexVT, EVT DataVT) const override;
616
617 bool isLegalElementTypeForRVV(Type *ScalarTy) const;
618
619 bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
620
621 unsigned getJumpTableEncoding() const override;
622
624 const MachineBasicBlock *MBB,
625 unsigned uid,
626 MCContext &Ctx) const override;
627
628 bool isVScaleKnownToBeAPowerOfTwo() const override;
629
631 uint64_t ElemSize) const override {
632 // Scaled addressing not supported on indexed load/stores
633 return Scale == 1;
634 }
635
636 /// If the target has a standard location for the stack protector cookie,
637 /// returns the address of that location. Otherwise, returns nullptr.
638 Value *getIRStackGuard(IRBuilderBase &IRB) const override;
639
640private:
641 /// RISCVCCAssignFn - This target-specific function extends the default
642 /// CCValAssign with additional information used to lower RISC-V calling
643 /// conventions.
644 typedef bool RISCVCCAssignFn(const DataLayout &DL, RISCVABI::ABI,
645 unsigned ValNo, MVT ValVT, MVT LocVT,
646 CCValAssign::LocInfo LocInfo,
647 ISD::ArgFlagsTy ArgFlags, CCState &State,
648 bool IsFixed, bool IsRet, Type *OrigTy,
649 const RISCVTargetLowering &TLI,
650 std::optional<unsigned> FirstMaskArgument);
651
652 void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
653 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
654 RISCVCCAssignFn Fn) const;
655 void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
657 bool IsRet, CallLoweringInfo *CLI,
658 RISCVCCAssignFn Fn) const;
659
660 template <class NodeTy>
661 SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const;
662 SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
663 bool UseGOT) const;
664 SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
665
666 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
667 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
668 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
669 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
670 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
671 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
672 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
673 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
674 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
675 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
676 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
677 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
678 SDValue lowerSPLAT_VECTOR_PARTS(SDValue Op, SelectionDAG &DAG) const;
679 SDValue lowerVectorMaskSplat(SDValue Op, SelectionDAG &DAG) const;
680 SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
681 int64_t ExtTrueVal) const;
682 SDValue lowerVectorMaskTruncLike(SDValue Op, SelectionDAG &DAG) const;
683 SDValue lowerVectorTruncLike(SDValue Op, SelectionDAG &DAG) const;
684 SDValue lowerVectorFPExtendOrRoundLike(SDValue Op, SelectionDAG &DAG) const;
685 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
686 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
687 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
688 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
689 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
690 SDValue lowerVPREDUCE(SDValue Op, SelectionDAG &DAG) const;
691 SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
692 SDValue lowerVectorMaskVecReduction(SDValue Op, SelectionDAG &DAG,
693 bool IsVP) const;
694 SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
695 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
696 SDValue lowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
697 SDValue lowerSTEP_VECTOR(SDValue Op, SelectionDAG &DAG) const;
698 SDValue lowerVECTOR_REVERSE(SDValue Op, SelectionDAG &DAG) const;
699 SDValue lowerVECTOR_SPLICE(SDValue Op, SelectionDAG &DAG) const;
700 SDValue lowerABS(SDValue Op, SelectionDAG &DAG) const;
701 SDValue lowerMaskedLoad(SDValue Op, SelectionDAG &DAG) const;
702 SDValue lowerMaskedStore(SDValue Op, SelectionDAG &DAG) const;
703 SDValue lowerFixedLengthVectorFCOPYSIGNToRVV(SDValue Op,
704 SelectionDAG &DAG) const;
705 SDValue lowerMaskedGather(SDValue Op, SelectionDAG &DAG) const;
706 SDValue lowerMaskedScatter(SDValue Op, SelectionDAG &DAG) const;
707 SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const;
708 SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const;
709 SDValue lowerFixedLengthVectorSetccToRVV(SDValue Op, SelectionDAG &DAG) const;
710 SDValue lowerFixedLengthVectorLogicOpToRVV(SDValue Op, SelectionDAG &DAG,
711 unsigned MaskOpc,
712 unsigned VecOpc) const;
713 SDValue lowerFixedLengthVectorShiftToRVV(SDValue Op, SelectionDAG &DAG) const;
714 SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op,
715 SelectionDAG &DAG) const;
716 SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG, unsigned NewOpc,
717 bool HasMergeOp = false, bool HasMask = true) const;
718 SDValue lowerVPOp(SDValue Op, SelectionDAG &DAG, unsigned RISCVISDOpc,
719 bool HasMergeOp = false) const;
720 SDValue lowerLogicVPOp(SDValue Op, SelectionDAG &DAG, unsigned MaskOpc,
721 unsigned VecOpc) const;
722 SDValue lowerVPExtMaskOp(SDValue Op, SelectionDAG &DAG) const;
723 SDValue lowerVPSetCCMaskOp(SDValue Op, SelectionDAG &DAG) const;
724 SDValue lowerVPFPIntConvOp(SDValue Op, SelectionDAG &DAG,
725 unsigned RISCVISDOpc) const;
726 SDValue lowerVPStridedLoad(SDValue Op, SelectionDAG &DAG) const;
727 SDValue lowerVPStridedStore(SDValue Op, SelectionDAG &DAG) const;
728 SDValue lowerFixedLengthVectorExtendToRVV(SDValue Op, SelectionDAG &DAG,
729 unsigned ExtendOpc) const;
730 SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
731 SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
732
733 SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
734 SDValue lowerCTLZ_CTTZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) const;
735
736 SDValue expandUnalignedRVVLoad(SDValue Op, SelectionDAG &DAG) const;
737 SDValue expandUnalignedRVVStore(SDValue Op, SelectionDAG &DAG) const;
738
739 bool isEligibleForTailCallOptimization(
740 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
741 const SmallVector<CCValAssign, 16> &ArgLocs) const;
742
743 /// Generate error diagnostics if any register used by CC has been marked
744 /// reserved.
745 void validateCCReservedRegs(
746 const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs,
747 MachineFunction &MF) const;
748
749 bool useRVVForFixedLengthVectorVT(MVT VT) const;
750
751 MVT getVPExplicitVectorLengthTy() const override;
752
753 /// RVV code generation for fixed length vectors does not lower all
754 /// BUILD_VECTORs. This makes BUILD_VECTOR legalisation a source of stores to
755 /// merge. However, merging them creates a BUILD_VECTOR that is just as
756 /// illegal as the original, thus leading to an infinite legalisation loop.
757 /// NOTE: Once BUILD_VECTOR can be custom lowered for all legal vector types,
758 /// this override can be removed.
759 bool mergeStoresAfterLegalization(EVT VT) const override;
760
761 /// Disable normalizing
762 /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
763 /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y))
764 /// RISCV doesn't have flags so it's better to perform the and/or in a GPR.
765 bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override {
766 return false;
767 };
768
769 /// For available scheduling models FDIV + two independent FMULs are much
770 /// faster than two FDIVs.
771 unsigned combineRepeatedFPDivisors() const override;
772};
773namespace RISCVVIntrinsicsTable {
774
776 unsigned IntrinsicID;
778 uint8_t VLOperand;
779 bool hasScalarOperand() const {
780 // 0xF is not valid. See NoScalarOperand in IntrinsicsRISCV.td.
781 return ScalarOperand != 0xF;
782 }
783 bool hasVLOperand() const {
784 // 0x1F is not valid. See NoVLOperand in IntrinsicsRISCV.td.
785 return VLOperand != 0x1F;
786 }
787};
788
789using namespace RISCV;
790
791#define GET_RISCVVIntrinsicsTable_DECL
792#include "RISCVGenSearchableTables.inc"
793
794} // end namespace RISCVVIntrinsicsTable
795
796} // end namespace llvm
797
798#endif
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
IRTranslator LLVM IR MI
#define RegName(no)
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
This file describes how to lower LLVM code to machine code.
Class for arbitrary precision integers.
Definition: APInt.h:75
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:513
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:718
CCState - This class holds information needed while lowering arguments and return values.
This class represents a function call, abstracting a target machine's calling convention.
This is the shared class of boolean and integer constants.
Definition: Constants.h:78
This is an important base class in LLVM.
Definition: Constant.h:41
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:114
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:641
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:94
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
This class is used to represent ISD::LOAD nodes.
Context object for machine code objects.
Definition: MCContext.h:76
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Machine Value Type.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
Definition: MachineInstr.h:68
Flags
Flags values. These may be or'd together.
static std::pair< unsigned, unsigned > decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT, unsigned InsertExtractIdx, const RISCVRegisterInfo *TRI)
static unsigned getSubregIndexByMVT(MVT VT, unsigned Index)
Value * getIRStackGuard(IRBuilderBase &IRB) const override
If the target has a standard location for the stack protector cookie, returns the address of that loc...
bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override
Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) satur...
bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const override
Check if sinking I's operands to I's basic block is profitable, because the operands can be folded in...
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT) const override
Return true if pulling a binary operation into a select with an identity constant is profitable.
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Value * emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override
Perform a masked atomicrmw using a target-specific intrinsic.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override
Returns true if the target allows unaligned memory accesses of the specified type.
const Constant * getTargetConstantFromLoad(LoadSDNode *LD) const override
This method returns the constant pool value that will be loaded by LD.
const RISCVSubtarget & getSubtarget() const
TargetLowering::ShiftLegalizationStrategy preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const override
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
bool canSplatOperand(Instruction *I, int Operand) const
Return true if the (vector) instruction I will be lowered to an instruction with a scalar splat opera...
bool shouldExtendTypeInLibCall(EVT Type) const override
Returns true if arguments should be extended in lib calls.
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Return true if it is beneficial to convert a load of a constant to just the constant itself.
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
bool hasAndNotCompare(SDValue Y) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
bool shouldScalarizeBinop(SDValue VecOp) const override
Try to convert an extract element of a vector binary operation into an extract element followed by a ...
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to move this shift by a constant amount through its operand,...
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize, unsigned MinSize)
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const override
Perform a masked cmpxchg using a target-specific intrinsic.
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
bool convertSelectOfConstantsToMath(EVT VT) const override
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
bool isMulAddWithConstProfitable(SDValue AddNode, SDValue ConstNode) const override
Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x,...
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
MVT getContainerForFixedLengthVector(MVT VT) const
static unsigned getRegClassIDForVecVT(MVT VT)
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
TargetLowering::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
bool isLegalElementTypeForRVV(Type *ScalarTy) const
bool signExtendConstant(const ConstantInt *CI) const override
Return true if this constant should be sign extended when promoting to a larger type.
bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const override
Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>>...
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Returns the register with the specified architectural or ABI name.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul)
bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override
Return true if result of the specified node is used by a return node only.
bool softPromoteHalfType() const override
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
TargetLowering::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override
Returns true if arguments should be sign-extended in lib calls.
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
ISD::NodeType getExtendForAtomicCmpSwapArg() const override
Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_...
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
bool isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override
Return true if the given shuffle mask can be codegen'd directly, or if it should be stack expanded.
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
bool isLegalScaleForGatherScatter(uint64_t Scale, uint64_t ElemSize) const override
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
bool isVScaleKnownToBeAPowerOfTwo() const override
Return true only if vscale must be a power of two.
static RISCVII::VLMUL getLMUL(MVT VT)
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, std::optional< CallingConv::ID > CC) const override
Target-specific splitting of values into parts that fit a register storing a legal type.
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
bool shouldConsiderGEPOffsetSplit() const override
bool preferScalarizeSplat(unsigned Opc) const override
bool isIntDivCheap(EVT VT, AttributeList Attr) const override
Return true if integer divide is usually cheaper than a sequence of several shifts,...
bool shouldRemoveExtendFromGSIndex(EVT IndexVT, EVT DataVT) const override
bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
SDValue joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, std::optional< CallingConv::ID > CC) const override
Target-specific combining of register parts into its original value.
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:465
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
ShiftLegalizationStrategy
Return the preferred strategy to legalize tihs SHIFT instruction, with ExpansionFactor being the recu...
virtual ShiftLegalizationStrategy preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1311
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:760
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1323
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
Definition: ISDOpcodes.h:1317
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #3 and #4) ...
static constexpr unsigned RVVBitsPerBlock
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
AtomicOrdering
Atomic ordering for LLVM's memory model.
CombineLevel
Definition: DAGCombine.h:15
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:139
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:149
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:144
This structure contains all information that is necessary for lowering calls.