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RISCVISelLowering.h
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1//===-- RISCVISelLowering.h - RISC-V DAG Lowering Interface -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that RISC-V uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
15#define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
16
17#include "RISCV.h"
22#include <optional>
23
24namespace llvm {
25class InstructionCost;
26class RISCVSubtarget;
27struct RISCVRegisterInfo;
28namespace RISCVISD {
29enum NodeType : unsigned {
35 /// Select with condition operator - This selects between a true value and
36 /// a false value (ops #3 and #4) based on the boolean result of comparing
37 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
38 /// condition code in op #2, a XLenVT constant from the ISD::CondCode enum.
39 /// The lhs and rhs are XLenVT integers. The true and false values can be
40 /// integer or floating point.
46
47 // Add the Lo 12 bits from an address. Selected to ADDI.
49 // Get the Hi 20 bits from an address. Selected to LUI.
51
52 // Represents an AUIPC+ADDI pair. Selected to PseudoLLA.
54
55 // Selected as PseudoAddTPRel. Used to emit a TP-relative relocation.
57
58 // Multiply high for signedxunsigned.
60 // RV64I shifts, directly matching the semantics of the named RISC-V
61 // instructions.
65 // 32-bit operations from RV64M that can't be simply matched with a pattern
66 // at instruction selection time. These have undefined behavior for division
67 // by 0 or overflow (divw) like their target independent counterparts.
71 // RV64IB rotates, directly matching the semantics of the named RISC-V
72 // instructions.
75 // RV64IZbb bit counting instructions directly matching the semantics of the
76 // named RISC-V instructions.
79
80 // RV64IZbb absolute value for i32. Expanded to (max (negw X), X) during isel.
82
83 // FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as
84 // XLEN is the only legal integer width.
85 //
86 // FMV_H_X matches the semantics of the FMV.H.X.
87 // FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result.
88 // FMV_X_SIGNEXTH is similar to FMV.X.H and has a sign-extended result.
89 // FMV_W_X_RV64 matches the semantics of the FMV.W.X.
90 // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result.
91 //
92 // This is a more convenient semantic for producing dagcombines that remove
93 // unnecessary GPR->FPR->GPR moves.
99 // FP to XLen int conversions. Corresponds to fcvt.l(u).s/d/h on RV64 and
100 // fcvt.w(u).s/d/h on RV32. Unlike FP_TO_S/UINT these saturate out of
101 // range inputs. These are used for FP_TO_S/UINT_SAT lowering. Rounding mode
102 // is passed as a TargetConstant operand using the RISCVFPRndMode enum.
105 // FP to 32 bit int conversions for RV64. These are used to keep track of the
106 // result being sign extended to 64 bit. These saturate out of range inputs.
107 // Used for FP_TO_S/UINT and FP_TO_S/UINT_SAT lowering. Rounding mode
108 // is passed as a TargetConstant operand using the RISCVFPRndMode enum.
111
114
115 // Rounds an FP value to its corresponding integer in the same FP format.
116 // First operand is the value to round, the second operand is the largest
117 // integer that can be represented exactly in the FP format. This will be
118 // expanded into multiple instructions and basic blocks with a custom
119 // inserter.
121
123
124 // Floating point fmax and fmin matching the RISC-V instruction semantics.
126
127 // READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target
128 // (returns (Lo, Hi)). It takes a chain operand.
130 // brev8, orc.b, zip, and unzip from Zbb and Zbkb. All operands are i32 or
131 // XLenVT.
136
137 // Scalar cryptography
142
143 // Vector Extension
145 // VMV_V_V_VL matches the semantics of vmv.v.v but includes an extra operand
146 // for the VL value to be used for the operation. The first operand is
147 // passthru operand.
149 // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand
150 // for the VL value to be used for the operation. The first operand is
151 // passthru operand.
153 // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand
154 // for the VL value to be used for the operation. The first operand is
155 // passthru operand.
157 // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign
158 // extended from the vector element size.
160 // VMV_S_X_VL matches the semantics of vmv.s.x. It carries a VL operand.
162 // VFMV_S_F_VL matches the semantics of vfmv.s.f. It carries a VL operand.
164 // Splats an 64-bit value that has been split into two i32 parts. This is
165 // expanded late to two scalar stores and a stride 0 vector load.
166 // The first operand is passthru operand.
168 // Truncates a RVV integer vector by one power-of-two. Carries both an extra
169 // mask and VL operand.
171 // Matches the semantics of vslideup/vslidedown. The first operand is the
172 // pass-thru operand, the second is the source vector, the third is the XLenVT
173 // index (either constant or non-constant), the fourth is the mask, the fifth
174 // is the VL and the sixth is the policy.
177 // Matches the semantics of vslide1up/slide1down. The first operand is
178 // passthru operand, the second is source vector, third is the XLenVT scalar
179 // value. The fourth and fifth operands are the mask and VL operands.
182 // Matches the semantics of vfslide1up/vfslide1down. The first operand is
183 // passthru operand, the second is source vector, third is a scalar value
184 // whose type matches the element type of the vectors. The fourth and fifth
185 // operands are the mask and VL operands.
188 // Matches the semantics of the vid.v instruction, with a mask and VL
189 // operand.
191 // Matches the semantics of the vfcnvt.rod function (Convert double-width
192 // float to single-width float, rounding towards odd). Takes a double-width
193 // float vector and produces a single-width float vector. Also has a mask and
194 // VL operand.
196 // These nodes match the semantics of the corresponding RVV vector reduction
197 // instructions. They produce a vector result which is the reduction
198 // performed over the second vector operand plus the first element of the
199 // third vector operand. The first operand is the pass-thru operand. The
200 // second operand is an unconstrained vector type, and the result, first, and
201 // third operand's types are expected to be the corresponding full-width
202 // LMUL=1 type for the second operand:
203 // nxv8i8 = vecreduce_add nxv8i8, nxv32i8, nxv8i8
204 // nxv2i32 = vecreduce_add nxv2i32, nxv8i32, nxv2i32
205 // The different in types does introduce extra vsetvli instructions but
206 // similarly it reduces the number of registers consumed per reduction.
207 // Also has a mask and VL operand.
220
221 // Vector binary ops with a merge as a third operand, a mask as a fourth
222 // operand, and VL as a fifth operand.
242
248
253
262
263 // Vector unary ops with a mask as a second operand and VL as a third operand.
268 FCOPYSIGN_VL, // Has a merge operand
274 VFCVT_RM_X_F_VL, // Has a rounding mode operand.
275 VFCVT_RM_XU_F_VL, // Has a rounding mode operand.
278 VFCVT_RM_F_X_VL, // Has a rounding mode operand.
279 VFCVT_RM_F_XU_VL, // Has a rounding mode operand.
282
283 // Vector FMA ops with a mask as a fourth operand and VL as a fifth operand.
288
289 // Vector widening FMA ops with a mask as a fourth operand and VL as a fifth
290 // operand.
295
296 // Widening instructions with a merge value a third operand, a mask as a
297 // fourth operand, and VL as a fifth operand.
310
316
317 // Widening ternary operations with a mask as the fourth operand and VL as the
318 // fifth operand.
322
323 // Narrowing logical shift right.
324 // Operands are (source, shift, passthru, mask, vl)
326
327 // Vector compare producing a mask. Fourth operand is input mask. Fifth
328 // operand is VL.
330
331 // Vector select with an additional VL operand. This operation is unmasked.
333 // Vector select with operand #2 (the value when the condition is false) tied
334 // to the destination and an additional VL operand. This operation is
335 // unmasked.
337
338 // Mask binary operators.
342
343 // Set mask vector to all zeros or ones.
346
347 // Matches the semantics of vrgather.vx and vrgather.vv with extra operands
348 // for passthru and VL. Operands are (src, index, mask, passthru, vl).
352
353 // Vector sign/zero extend with additional mask & VL operands.
356
357 // vcpop.m with additional mask and VL operands.
359
360 // vfirst.m with additional mask and VL operands.
362
364
365 // Read VLENB CSR
367 // Reads value of CSR.
368 // The first operand is a chain pointer. The second specifies address of the
369 // required CSR. Two results are produced, the read value and the new chain
370 // pointer.
372 // Write value to CSR.
373 // The first operand is a chain pointer, the second specifies address of the
374 // required CSR and the third is the value to write. The result is the new
375 // chain pointer.
377 // Read and write value of CSR.
378 // The first operand is a chain pointer, the second specifies address of the
379 // required CSR and the third is the value to write. Two results are produced,
380 // the value read before the modification and the new chain pointer.
382
383 // Branchless select operations, matching the semantics of the instructions
384 // defined in Zicond or XVentanaCondOps.
385 CZERO_EQZ, // vt.maskc for XVentanaCondOps.
386 CZERO_NEZ, // vt.maskcn for XVentanaCondOps.
387
388 // FP to 32 bit int conversions for RV64. These are used to keep track of the
389 // result being sign extended to 64 bit. These saturate out of range inputs.
413
414 // WARNING: Do not add anything in the end unless you want the node to
415 // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
416 // opcodes will be thought as target memory ops!
417
423};
424} // namespace RISCVISD
425
427 const RISCVSubtarget &Subtarget;
428
429public:
430 explicit RISCVTargetLowering(const TargetMachine &TM,
431 const RISCVSubtarget &STI);
432
433 const RISCVSubtarget &getSubtarget() const { return Subtarget; }
434
435 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
436 MachineFunction &MF,
437 unsigned Intrinsic) const override;
438 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
439 unsigned AS,
440 Instruction *I = nullptr) const override;
441 bool isLegalICmpImmediate(int64_t Imm) const override;
442 bool isLegalAddImmediate(int64_t Imm) const override;
443 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
444 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
445 bool isZExtFree(SDValue Val, EVT VT2) const override;
446 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
447 bool signExtendConstant(const ConstantInt *CI) const override;
448 bool isCheapToSpeculateCttz(Type *Ty) const override;
449 bool isCheapToSpeculateCtlz(Type *Ty) const override;
450 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
451 bool hasAndNotCompare(SDValue Y) const override;
452 bool hasBitTest(SDValue X, SDValue Y) const override;
455 unsigned OldShiftOpcode, unsigned NewShiftOpcode,
456 SelectionDAG &DAG) const override;
457 /// Return true if the (vector) instruction I will be lowered to an instruction
458 /// with a scalar splat operand for the given Operand number.
459 bool canSplatOperand(Instruction *I, int Operand) const;
460 /// Return true if a vector instruction will lower to a target instruction
461 /// able to splat the given operand.
462 bool canSplatOperand(unsigned Opcode, int Operand) const;
464 SmallVectorImpl<Use *> &Ops) const override;
465 bool shouldScalarizeBinop(SDValue VecOp) const override;
466 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
467 std::pair<int, bool> getLegalZfaFPImm(const APFloat &Imm, EVT VT) const;
468 bool isFPImmLegal(const APFloat &Imm, EVT VT,
469 bool ForCodeSize) const override;
470 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
471 unsigned Index) const override;
472
473 bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
474
475 bool preferScalarizeSplat(SDNode *N) const override;
476
477 bool softPromoteHalfType() const override { return true; }
478
479 /// Return the register type for a given MVT, ensuring vectors are treated
480 /// as a series of gpr sized integers.
482 EVT VT) const override;
483
484 /// Return the number of registers for a given MVT, ensuring vectors are
485 /// treated as a series of gpr sized integers.
488 EVT VT) const override;
489
492 EVT &IntermediateVT,
493 unsigned &NumIntermediates,
494 MVT &RegisterVT) const override;
495
496 bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode,
497 EVT VT) const override;
498
499 /// Return true if the given shuffle mask can be codegen'd directly, or if it
500 /// should be stack expanded.
501 bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
502
503 bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override {
504 // If the pair to store is a mixture of float and int values, we will
505 // save two bitwise instructions and one float-to-int instruction and
506 // increase one store instruction. There is potentially a more
507 // significant benefit because it avoids the float->int domain switch
508 // for input value. So It is more likely a win.
509 if ((LTy.isFloatingPoint() && HTy.isInteger()) ||
510 (LTy.isInteger() && HTy.isFloatingPoint()))
511 return true;
512 // If the pair only contains int values, we will save two bitwise
513 // instructions and increase one store instruction (costing one more
514 // store buffer). Since the benefit is more blurred we leave such a pair
515 // out until we get testcase to prove it is a win.
516 return false;
517 }
518
519 bool
521 unsigned DefinedValues) const override;
522
523 /// Return the cost of LMUL for linear operations.
525
529
530 // Provide custom lowering hooks for some operations.
531 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
533 SelectionDAG &DAG) const override;
534
535 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
536
538 const APInt &DemandedElts,
539 TargetLoweringOpt &TLO) const override;
540
542 KnownBits &Known,
543 const APInt &DemandedElts,
544 const SelectionDAG &DAG,
545 unsigned Depth) const override;
547 const APInt &DemandedElts,
548 const SelectionDAG &DAG,
549 unsigned Depth) const override;
550
551 const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const override;
552
553 // This method returns the name of a target specific DAG node.
554 const char *getTargetNodeName(unsigned Opcode) const override;
555
557 getTargetMMOFlags(const Instruction &I) const override;
558
560 getTargetMMOFlags(const MemSDNode &Node) const override;
561
562 bool
564 const MemSDNode &NodeY) const override;
565
566 ConstraintType getConstraintType(StringRef Constraint) const override;
567
569 getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
570
571 std::pair<unsigned, const TargetRegisterClass *>
573 StringRef Constraint, MVT VT) const override;
574
576 std::vector<SDValue> &Ops,
577 SelectionDAG &DAG) const override;
578
581 MachineBasicBlock *BB) const override;
582
584 SDNode *Node) const override;
585
587 EVT VT) const override;
588
589 bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
590 bool MathUsed) const override {
591 if (VT == MVT::i8 || VT == MVT::i16)
592 return false;
593
594 return TargetLowering::shouldFormOverflowOp(Opcode, VT, MathUsed);
595 }
596
597 bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem,
598 unsigned AddrSpace) const override {
599 // If we can replace 4 or more scalar stores, there will be a reduction
600 // in instructions even after we add a vector constant load.
601 return NumElem >= 4;
602 }
603
604 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
605 return VT.isScalarInteger();
606 }
607 bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
608
609 bool isCtpopFast(EVT VT) const override;
610
611 unsigned getCustomCtpopCost(EVT VT, ISD::CondCode Cond) const override;
612
613 bool preferZeroCompareBranch() const override { return true; }
614
615 bool shouldInsertFencesForAtomic(const Instruction *I) const override {
616 return isa<LoadInst>(I) || isa<StoreInst>(I);
617 }
619 AtomicOrdering Ord) const override;
621 AtomicOrdering Ord) const override;
622
624 EVT VT) const override;
625
627 return ISD::SIGN_EXTEND;
628 }
629
631 return ISD::SIGN_EXTEND;
632 }
633
635 unsigned KeptBits) const override;
636
639 unsigned ExpansionFactor) const override {
643 ExpansionFactor);
644 }
645
647 CombineLevel Level) const override;
648
649 /// If a physical register, this returns the register that receives the
650 /// exception address on entry to an EH pad.
652 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
653
654 /// If a physical register, this returns the register that receives the
655 /// exception typeid on entry to a landing pad.
657 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
658
659 bool shouldExtendTypeInLibCall(EVT Type) const override;
660 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
661
662 /// Returns the register with the specified architectural or ABI name. This
663 /// method is necessary to lower the llvm.read_register.* and
664 /// llvm.write_register.* intrinsics. Allocatable registers must be reserved
665 /// with the clang -ffixed-xX flag for access to be allowed.
666 Register getRegisterByName(const char *RegName, LLT VT,
667 const MachineFunction &MF) const override;
668
669 // Lower incoming arguments, copy physregs into vregs
671 bool IsVarArg,
673 const SDLoc &DL, SelectionDAG &DAG,
674 SmallVectorImpl<SDValue> &InVals) const override;
676 bool IsVarArg,
678 LLVMContext &Context) const override;
679 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
681 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
682 SelectionDAG &DAG) const override;
684 SmallVectorImpl<SDValue> &InVals) const override;
685
687 Type *Ty) const override;
688 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
689 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
690 bool shouldConsiderGEPOffsetSplit() const override { return true; }
691
692 bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
693 SDValue C) const override;
694
696 SDValue ConstNode) const override;
697
699 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
701 Value *AlignedAddr, Value *Incr,
702 Value *Mask, Value *ShiftAmt,
703 AtomicOrdering Ord) const override;
708 Value *AlignedAddr, Value *CmpVal,
709 Value *NewVal, Value *Mask,
710 AtomicOrdering Ord) const override;
711
712 /// Returns true if the target allows unaligned memory accesses of the
713 /// specified type.
715 EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
717 unsigned *Fast = nullptr) const override;
718
720 const AttributeList &FuncAttributes) const override;
721
723 SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
724 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
725 const override;
726
728 SelectionDAG & DAG, const SDLoc &DL, const SDValue *Parts,
729 unsigned NumParts, MVT PartVT, EVT ValueVT,
730 std::optional<CallingConv::ID> CC) const override;
731
732 // Return the value of VLMax for the given vector type (i.e. SEW and LMUL)
733 SDValue computeVLMax(MVT VecVT, const SDLoc &DL, SelectionDAG &DAG) const;
734
735 static RISCVII::VLMUL getLMUL(MVT VT);
736 inline static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize,
737 unsigned MinSize) {
738 // Original equation:
739 // VLMAX = (VectorBits / EltSize) * LMUL
740 // where LMUL = MinSize / RISCV::RVVBitsPerBlock
741 // The following equations have been reordered to prevent loss of precision
742 // when calculating fractional LMUL.
743 return ((VectorBits / EltSize) * MinSize) / RISCV::RVVBitsPerBlock;
744 };
745 static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul);
746 static unsigned getSubregIndexByMVT(MVT VT, unsigned Index);
747 static unsigned getRegClassIDForVecVT(MVT VT);
748 static std::pair<unsigned, unsigned>
750 unsigned InsertExtractIdx,
751 const RISCVRegisterInfo *TRI);
753
754 bool shouldRemoveExtendFromGSIndex(SDValue Extend, EVT DataVT) const override;
755
756 bool isLegalElementTypeForRVV(EVT ScalarTy) const;
757
758 bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
759
760 unsigned getJumpTableEncoding() const override;
761
763 const MachineBasicBlock *MBB,
764 unsigned uid,
765 MCContext &Ctx) const override;
766
767 bool isVScaleKnownToBeAPowerOfTwo() const override;
768
770 ISD::MemIndexedMode &AM, bool &IsInc,
771 SelectionDAG &DAG) const;
774 SelectionDAG &DAG) const override;
777 SelectionDAG &DAG) const override;
778
780 uint64_t ElemSize) const override {
781 // Scaled addressing not supported on indexed load/stores
782 return Scale == 1;
783 }
784
785 /// If the target has a standard location for the stack protector cookie,
786 /// returns the address of that location. Otherwise, returns nullptr.
787 Value *getIRStackGuard(IRBuilderBase &IRB) const override;
788
789 /// Returns whether or not generating a interleaved load/store intrinsic for
790 /// this type will be legal.
791 bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor,
792 Align Alignment, unsigned AddrSpace,
793 const DataLayout &) const;
794
795 /// Return true if a stride load store of the given result type and
796 /// alignment is legal.
797 bool isLegalStridedLoadStore(EVT DataType, Align Alignment) const;
798
799 unsigned getMaxSupportedInterleaveFactor() const override { return 8; }
800
801 bool fallBackToDAGISel(const Instruction &Inst) const override;
802
805 ArrayRef<unsigned> Indices,
806 unsigned Factor) const override;
807
809 unsigned Factor) const override;
810
812 LoadInst *LI) const override;
813
815 StoreInst *SI) const override;
816
817 bool supportKCFIBundles() const override { return true; }
818
821 const TargetInstrInfo *TII) const override;
822
823 /// RISCVCCAssignFn - This target-specific function extends the default
824 /// CCValAssign with additional information used to lower RISC-V calling
825 /// conventions.
827 unsigned ValNo, MVT ValVT, MVT LocVT,
828 CCValAssign::LocInfo LocInfo,
829 ISD::ArgFlagsTy ArgFlags, CCState &State,
830 bool IsFixed, bool IsRet, Type *OrigTy,
831 const RISCVTargetLowering &TLI,
832 std::optional<unsigned> FirstMaskArgument);
833
834private:
835 void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
836 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
837 RISCVCCAssignFn Fn) const;
838 void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
840 bool IsRet, CallLoweringInfo *CLI,
841 RISCVCCAssignFn Fn) const;
842
843 template <class NodeTy>
844 SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true,
845 bool IsExternWeak = false) const;
846 SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
847 bool UseGOT) const;
848 SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
849
850 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
851 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
852 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
853 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
854 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
855 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
856 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
857 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
858 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
859 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
860 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
861 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
862 SDValue lowerSPLAT_VECTOR_PARTS(SDValue Op, SelectionDAG &DAG) const;
863 SDValue lowerVectorMaskSplat(SDValue Op, SelectionDAG &DAG) const;
864 SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
865 int64_t ExtTrueVal) const;
866 SDValue lowerVectorMaskTruncLike(SDValue Op, SelectionDAG &DAG) const;
867 SDValue lowerVectorTruncLike(SDValue Op, SelectionDAG &DAG) const;
868 SDValue lowerVectorFPExtendOrRoundLike(SDValue Op, SelectionDAG &DAG) const;
869 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
870 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
871 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
872 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
873 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
874 SDValue lowerVPREDUCE(SDValue Op, SelectionDAG &DAG) const;
875 SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
876 SDValue lowerVectorMaskVecReduction(SDValue Op, SelectionDAG &DAG,
877 bool IsVP) const;
878 SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
879 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
880 SDValue lowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
881 SDValue lowerVECTOR_DEINTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
882 SDValue lowerVECTOR_INTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
883 SDValue lowerSTEP_VECTOR(SDValue Op, SelectionDAG &DAG) const;
884 SDValue lowerVECTOR_REVERSE(SDValue Op, SelectionDAG &DAG) const;
885 SDValue lowerVECTOR_SPLICE(SDValue Op, SelectionDAG &DAG) const;
886 SDValue lowerABS(SDValue Op, SelectionDAG &DAG) const;
887 SDValue lowerMaskedLoad(SDValue Op, SelectionDAG &DAG) const;
888 SDValue lowerMaskedStore(SDValue Op, SelectionDAG &DAG) const;
889 SDValue lowerFixedLengthVectorFCOPYSIGNToRVV(SDValue Op,
890 SelectionDAG &DAG) const;
891 SDValue lowerMaskedGather(SDValue Op, SelectionDAG &DAG) const;
892 SDValue lowerMaskedScatter(SDValue Op, SelectionDAG &DAG) const;
893 SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const;
894 SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const;
895 SDValue lowerFixedLengthVectorSetccToRVV(SDValue Op, SelectionDAG &DAG) const;
896 SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op,
897 SelectionDAG &DAG) const;
898 SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG) const;
899 SDValue LowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG) const;
900 SDValue lowerVPOp(SDValue Op, SelectionDAG &DAG) const;
901 SDValue lowerLogicVPOp(SDValue Op, SelectionDAG &DAG) const;
902 SDValue lowerVPExtMaskOp(SDValue Op, SelectionDAG &DAG) const;
903 SDValue lowerVPSetCCMaskOp(SDValue Op, SelectionDAG &DAG) const;
904 SDValue lowerVPReverseExperimental(SDValue Op, SelectionDAG &DAG) const;
905 SDValue lowerVPFPIntConvOp(SDValue Op, SelectionDAG &DAG) const;
906 SDValue lowerVPStridedLoad(SDValue Op, SelectionDAG &DAG) const;
907 SDValue lowerVPStridedStore(SDValue Op, SelectionDAG &DAG) const;
908 SDValue lowerFixedLengthVectorExtendToRVV(SDValue Op, SelectionDAG &DAG,
909 unsigned ExtendOpc) const;
910 SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
911 SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
912
913 SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
914 SDValue lowerCTLZ_CTTZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) const;
915
916 SDValue lowerStrictFPExtendOrRoundLike(SDValue Op, SelectionDAG &DAG) const;
917
918 SDValue lowerVectorStrictFSetcc(SDValue Op, SelectionDAG &DAG) const;
919
920 SDValue expandUnalignedRVVLoad(SDValue Op, SelectionDAG &DAG) const;
921 SDValue expandUnalignedRVVStore(SDValue Op, SelectionDAG &DAG) const;
922
923 bool isEligibleForTailCallOptimization(
924 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
925 const SmallVector<CCValAssign, 16> &ArgLocs) const;
926
927 /// Generate error diagnostics if any register used by CC has been marked
928 /// reserved.
929 void validateCCReservedRegs(
930 const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs,
931 MachineFunction &MF) const;
932
933 bool useRVVForFixedLengthVectorVT(MVT VT) const;
934
935 MVT getVPExplicitVectorLengthTy() const override;
936
937 bool shouldExpandGetVectorLength(EVT TripCountVT, unsigned VF,
938 bool IsScalable) const override;
939
940 /// RVV code generation for fixed length vectors does not lower all
941 /// BUILD_VECTORs. This makes BUILD_VECTOR legalisation a source of stores to
942 /// merge. However, merging them creates a BUILD_VECTOR that is just as
943 /// illegal as the original, thus leading to an infinite legalisation loop.
944 /// NOTE: Once BUILD_VECTOR can be custom lowered for all legal vector types,
945 /// this override can be removed.
946 bool mergeStoresAfterLegalization(EVT VT) const override;
947
948 /// Disable normalizing
949 /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
950 /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y))
951 /// RISC-V doesn't have flags so it's better to perform the and/or in a GPR.
952 bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override {
953 return false;
954 };
955
956 /// For available scheduling models FDIV + two independent FMULs are much
957 /// faster than two FDIVs.
958 unsigned combineRepeatedFPDivisors() const override;
959
960 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
961 SmallVectorImpl<SDNode *> &Created) const override;
962
963 bool shouldFoldSelectWithSingleBitTest(EVT VT,
964 const APInt &AndMask) const override;
965
966 unsigned getMinimumJumpTableEntries() const override;
967};
968
969namespace RISCV {
970
971bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
972 MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo,
973 ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed,
974 bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI,
975 std::optional<unsigned> FirstMaskArgument);
976
977bool CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
978 MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo,
979 ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed,
980 bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI,
981 std::optional<unsigned> FirstMaskArgument);
982
983bool CC_RISCV_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
984 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
985 CCState &State);
986} // end namespace RISCV
987
988namespace RISCVVIntrinsicsTable {
989
991 unsigned IntrinsicID;
993 uint8_t VLOperand;
994 bool hasScalarOperand() const {
995 // 0xF is not valid. See NoScalarOperand in IntrinsicsRISCV.td.
996 return ScalarOperand != 0xF;
997 }
998 bool hasVLOperand() const {
999 // 0x1F is not valid. See NoVLOperand in IntrinsicsRISCV.td.
1000 return VLOperand != 0x1F;
1001 }
1002};
1003
1004using namespace RISCV;
1005
1006#define GET_RISCVVIntrinsicsTable_DECL
1007#include "RISCVGenSearchableTables.inc"
1008#undef GET_RISCVVIntrinsicsTable_DECL
1009
1010} // end namespace RISCVVIntrinsicsTable
1011
1012} // end namespace llvm
1013
1014#endif
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Function Alias Analysis Results
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
#define RegName(no)
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
const SmallVectorImpl< MachineOperand > & Cond
This file describes how to lower LLVM code to machine code.
static constexpr uint32_t Opcode
Definition: aarch32.h:200
Class for arbitrary precision integers.
Definition: APInt.h:76
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:513
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:718
CCState - This class holds information needed while lowering arguments and return values.
This class represents a function call, abstracting a target machine's calling convention.
This is the shared class of boolean and integer constants.
Definition: Constants.h:78
This is an important base class in LLVM.
Definition: Constant.h:41
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:674
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:94
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:47
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
An instruction for reading from memory.
Definition: Instructions.h:177
This class is used to represent ISD::LOAD nodes.
Context object for machine code objects.
Definition: MCContext.h:76
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Machine Value Type.
Instructions::iterator instr_iterator
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
Definition: MachineInstr.h:68
Flags
Flags values. These may be or'd together.
This is an abstract virtual class for memory operations.
static std::pair< unsigned, unsigned > decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT, unsigned InsertExtractIdx, const RISCVRegisterInfo *TRI)
bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, bool &IsInc, SelectionDAG &DAG) const
InstructionCost getVRGatherVVCost(MVT VT) const
Return the cost of a vrgather.vv instruction for the type VT.
static unsigned getSubregIndexByMVT(MVT VT, unsigned Index)
Value * getIRStackGuard(IRBuilderBase &IRB) const override
If the target has a standard location for the stack protector cookie, returns the address of that loc...
bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override
Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) satur...
bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem, unsigned AddrSpace) const override
Return true if it is expected to be cheaper to do a store of vector constant with the given size and ...
bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const override
Check if sinking I's operands to I's basic block is profitable, because the operands can be folded in...
InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const override
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT) const override
Return true if pulling a binary operation into a select with an identity constant is profitable.
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
std::pair< int, bool > getLegalZfaFPImm(const APFloat &Imm, EVT VT) const
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
bool preferZeroCompareBranch() const override
Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.
bool shouldRemoveExtendFromGSIndex(SDValue Extend, EVT DataVT) const override
Value * emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override
Perform a masked atomicrmw using a target-specific intrinsic.
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override
Returns true if the target allows unaligned memory accesses of the specified type.
const Constant * getTargetConstantFromLoad(LoadSDNode *LD) const override
This method returns the constant pool value that will be loaded by LD.
const RISCVSubtarget & getSubtarget() const
TargetLowering::ShiftLegalizationStrategy preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const override
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
bool lowerInterleaveIntrinsicToStore(IntrinsicInst *II, StoreInst *SI) const override
Lower an interleave intrinsic to a target specific store intrinsic.
bool preferScalarizeSplat(SDNode *N) const override
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
bool canSplatOperand(Instruction *I, int Operand) const
Return true if the (vector) instruction I will be lowered to an instruction with a scalar splat opera...
bool shouldExtendTypeInLibCall(EVT Type) const override
Returns true if arguments should be extended in lib calls.
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override
InstructionCost getVRGatherVICost(MVT VT) const
Return the cost of a vrgather.vi (or vx) instruction for the type VT.
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Return true if it is beneficial to convert a load of a constant to just the constant itself.
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
bool hasAndNotCompare(SDValue Y) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
bool shouldScalarizeBinop(SDValue VecOp) const override
Try to convert an extract element of a vector binary operation into an extract element followed by a ...
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to move this shift by a constant amount through its operand,...
bool areTwoSDNodeTargetMMOFlagsMergeable(const MemSDNode &NodeX, const MemSDNode &NodeY) const override
Return true if it is valid to merge the TargetMMOFlags in two SDNodes.
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize, unsigned MinSize)
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const override
Perform a masked cmpxchg using a target-specific intrinsic.
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
bool convertSelectOfConstantsToMath(EVT VT) const override
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
InstructionCost getLMULCost(MVT VT) const
Return the cost of LMUL for linear operations.
bool supportKCFIBundles() const override
Return true if the target supports kcfi operand bundles.
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
bool isMulAddWithConstProfitable(SDValue AddNode, SDValue ConstNode) const override
Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x,...
bool fallBackToDAGISel(const Instruction &Inst) const override
InstructionCost getVSlideCost(MVT VT) const
Return the cost of a vslidedown.vi/vx or vslideup.vi/vx instruction for the type VT.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower an interleaved load into a vlsegN intrinsic.
bool isCtpopFast(EVT VT) const override
Return true if ctpop instruction is fast.
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
MVT getContainerForFixedLengthVector(MVT VT) const
static unsigned getRegClassIDForVecVT(MVT VT)
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
TargetLowering::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const override
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
SDValue computeVLMax(MVT VecVT, const SDLoc &DL, SelectionDAG &DAG) const
bool signExtendConstant(const ConstantInt *CI) const override
Return true if this constant should be sign extended when promoting to a larger type.
bool shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const override
Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be trun...
bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const override
Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>>...
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Returns the register with the specified architectural or ABI name.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul)
bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override
Return true if result of the specified node is used by a return node only.
bool softPromoteHalfType() const override
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
bool RISCVCCAssignFn(const DataLayout &DL, RISCVABI::ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, std::optional< unsigned > FirstMaskArgument)
RISCVCCAssignFn - This target-specific function extends the default CCValAssign with additional infor...
TargetLowering::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override
Returns true if arguments should be sign-extended in lib calls.
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
ISD::NodeType getExtendForAtomicCmpSwapArg() const override
Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_...
unsigned getCustomCtpopCost(EVT VT, ISD::CondCode Cond) const override
Return the maximum number of "x & (x - 1)" operations that can be done instead of deferring to a cust...
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
bool isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override
Return true if the given shuffle mask can be codegen'd directly, or if it should be stack expanded.
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override
Lower an interleaved store into a vssegN intrinsic.
bool isLegalScaleForGatherScatter(uint64_t Scale, uint64_t ElemSize) const override
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
bool isLegalElementTypeForRVV(EVT ScalarTy) const
bool isVScaleKnownToBeAPowerOfTwo() const override
Return true only if vscale must be a power of two.
bool lowerDeinterleaveIntrinsicToLoad(IntrinsicInst *II, LoadInst *LI) const override
Lower a deinterleave intrinsic to a target specific load intrinsic.
static RISCVII::VLMUL getLMUL(MVT VT)
void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, std::optional< CallingConv::ID > CC) const override
Target-specific splitting of values into parts that fit a register storing a legal type.
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
bool shouldConsiderGEPOffsetSplit() const override
MachineInstr * EmitKCFICheck(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator &MBBI, const TargetInstrInfo *TII) const override
bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor, Align Alignment, unsigned AddrSpace, const DataLayout &) const
Returns whether or not generating a interleaved load/store intrinsic for this type will be legal.
bool isIntDivCheap(EVT VT, AttributeList Attr) const override
Return true if integer divide is usually cheaper than a sequence of several shifts,...
bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Try to convert math with an overflow comparison into the corresponding DAG node operation.
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's...
SDValue joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, std::optional< CallingConv::ID > CC) const override
Target-specific combining of register parts into its original value.
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
bool isLegalStridedLoadStore(EVT DataType, Align Alignment) const
Return true if a stride load store of the given result type and alignment is legal.
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:469
This instruction constructs a fixed permutation of two input vectors.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
An instruction for storing to memory.
Definition: Instructions.h:301
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetInstrInfo - Interface to description of machine instruction set.
virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const
Try to convert math with an overflow comparison into the corresponding DAG node operation.
ShiftLegalizationStrategy
Return the preferred strategy to legalize tihs SHIFT instruction, with ExpansionFactor being the recu...
virtual ShiftLegalizationStrategy preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
Base class of all SIMD vector types.
Definition: DerivedTypes.h:403
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1383
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:774
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1395
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1455
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
Definition: ISDOpcodes.h:1389
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1506
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #3 and #4) ...
bool CC_RISCV_GHC(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static constexpr unsigned RVVBitsPerBlock
bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, std::optional< unsigned > FirstMaskArgument)
bool CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, std::optional< unsigned > FirstMaskArgument)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:440
AtomicOrdering
Atomic ordering for LLVM's memory model.
CombineLevel
Definition: DAGCombine.h:15
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:139
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:149
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:144
This structure contains all information that is necessary for lowering calls.