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RISCVISelLowering.h
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1//===-- RISCVISelLowering.h - RISC-V DAG Lowering Interface -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that RISC-V uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
15#define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
16
17#include "RISCV.h"
22#include <optional>
23
24namespace llvm {
25class RISCVSubtarget;
26struct RISCVRegisterInfo;
27namespace RISCVISD {
28enum NodeType : unsigned {
34 /// Select with condition operator - This selects between a true value and
35 /// a false value (ops #3 and #4) based on the boolean result of comparing
36 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
37 /// condition code in op #2, a XLenVT constant from the ISD::CondCode enum.
38 /// The lhs and rhs are XLenVT integers. The true and false values can be
39 /// integer or floating point.
45
46 // Add the Lo 12 bits from an address. Selected to ADDI.
48 // Get the Hi 20 bits from an address. Selected to LUI.
50
51 // Represents an AUIPC+ADDI pair. Selected to PseudoLLA.
53
54 // Selected as PseudoAddTPRel. Used to emit a TP-relative relocation.
56
57 // Load address.
59
60 // Multiply high for signedxunsigned.
62 // RV64I shifts, directly matching the semantics of the named RISC-V
63 // instructions.
67 // 32-bit operations from RV64M that can't be simply matched with a pattern
68 // at instruction selection time. These have undefined behavior for division
69 // by 0 or overflow (divw) like their target independent counterparts.
73 // RV64IB rotates, directly matching the semantics of the named RISC-V
74 // instructions.
77 // RV64IZbb bit counting instructions directly matching the semantics of the
78 // named RISC-V instructions.
81
82 // RV64IZbb absolute value for i32. Expanded to (max (negw X), X) during isel.
84
85 // FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as
86 // XLEN is the only legal integer width.
87 //
88 // FMV_H_X matches the semantics of the FMV.H.X.
89 // FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result.
90 // FMV_X_SIGNEXTH is similar to FMV.X.H and has a sign-extended result.
91 // FMV_W_X_RV64 matches the semantics of the FMV.W.X.
92 // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result.
93 //
94 // This is a more convenient semantic for producing dagcombines that remove
95 // unnecessary GPR->FPR->GPR moves.
101 // FP to XLen int conversions. Corresponds to fcvt.l(u).s/d/h on RV64 and
102 // fcvt.w(u).s/d/h on RV32. Unlike FP_TO_S/UINT these saturate out of
103 // range inputs. These are used for FP_TO_S/UINT_SAT lowering. Rounding mode
104 // is passed as a TargetConstant operand using the RISCVFPRndMode enum.
107 // FP to 32 bit int conversions for RV64. These are used to keep track of the
108 // result being sign extended to 64 bit. These saturate out of range inputs.
109 // Used for FP_TO_S/UINT and FP_TO_S/UINT_SAT lowering. Rounding mode
110 // is passed as a TargetConstant operand using the RISCVFPRndMode enum.
113
114 // Rounds an FP value to its corresponding integer in the same FP format.
115 // First operand is the value to round, the second operand is the largest
116 // integer that can be represented exactly in the FP format. This will be
117 // expanded into multiple instructions and basic blocks with a custom
118 // inserter.
120
122 // READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target
123 // (returns (Lo, Hi)). It takes a chain operand.
125 // brev8, orc.b, zip, and unzip from Zbb and Zbkb. All operands are i32 or
126 // XLenVT.
131 // Vector Extension
132 // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand
133 // for the VL value to be used for the operation. The first operand is
134 // passthru operand.
136 // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand
137 // for the VL value to be used for the operation. The first operand is
138 // passthru operand.
140 // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign
141 // extended from the vector element size.
143 // VMV_S_X_VL matches the semantics of vmv.s.x. It carries a VL operand.
145 // VFMV_S_F_VL matches the semantics of vfmv.s.f. It carries a VL operand.
147 // Splats an 64-bit value that has been split into two i32 parts. This is
148 // expanded late to two scalar stores and a stride 0 vector load.
149 // The first operand is passthru operand.
151 // Read VLENB CSR
153 // Truncates a RVV integer vector by one power-of-two. Carries both an extra
154 // mask and VL operand.
156 // Matches the semantics of vslideup/vslidedown. The first operand is the
157 // pass-thru operand, the second is the source vector, the third is the
158 // XLenVT index (either constant or non-constant), the fourth is the mask
159 // and the fifth the VL.
162 // Matches the semantics of vslide1up/slide1down. The first operand is
163 // passthru operand, the second is source vector, third is the XLenVT scalar
164 // value. The fourth and fifth operands are the mask and VL operands.
167 // Matches the semantics of vfslide1up/vfslide1down. The first operand is
168 // passthru operand, the second is source vector, third is a scalar value
169 // whose type matches the element type of the vectors. The fourth and fifth
170 // operands are the mask and VL operands.
173 // Matches the semantics of the vid.v instruction, with a mask and VL
174 // operand.
176 // Matches the semantics of the vfcnvt.rod function (Convert double-width
177 // float to single-width float, rounding towards odd). Takes a double-width
178 // float vector and produces a single-width float vector. Also has a mask and
179 // VL operand.
181 // These nodes match the semantics of the corresponding RVV vector reduction
182 // instructions. They produce a vector result which is the reduction
183 // performed over the second vector operand plus the first element of the
184 // third vector operand. The first operand is the pass-thru operand. The
185 // second operand is an unconstrained vector type, and the result, first, and
186 // third operand's types are expected to be the corresponding full-width
187 // LMUL=1 type for the second operand:
188 // nxv8i8 = vecreduce_add nxv8i8, nxv32i8, nxv8i8
189 // nxv2i32 = vecreduce_add nxv2i32, nxv8i32, nxv2i32
190 // The different in types does introduce extra vsetvli instructions but
191 // similarly it reduces the number of registers consumed per reduction.
192 // Also has a mask and VL operand.
205
206 // Vector binary ops with a merge as a third operand, a mask as a fourth
207 // operand, and VL as a fifth operand.
225
230
239
240 // Vector unary ops with a mask as a second operand and VL as a third operand.
245 FCOPYSIGN_VL, // Has a merge operand
251 VFCVT_RM_X_F_VL, // Has a rounding mode operand.
252 VFCVT_RM_XU_F_VL, // Has a rounding mode operand.
255 VFCVT_RM_F_X_VL, // Has a rounding mode operand.
256 VFCVT_RM_F_XU_VL, // Has a rounding mode operand.
259
260 // Vector FMA ops with a mask as a fourth operand and VL as a fifth operand.
265
266 // Vector widening FMA ops with a mask as a fourth operand and VL as a fifth
267 // operand.
272
273 // Widening instructions with a merge value a third operand, a mask as a
274 // fourth operand, and VL as a fifth operand.
286
292
293 // Narrowing logical shift right.
294 // Operands are (source, shift, passthru, mask, vl)
296
297 // Vector compare producing a mask. Fourth operand is input mask. Fifth
298 // operand is VL.
300
301 // Vector select with an additional VL operand. This operation is unmasked.
303 // Vector select with operand #2 (the value when the condition is false) tied
304 // to the destination and an additional VL operand. This operation is
305 // unmasked.
307
308 // Mask binary operators.
312
313 // Set mask vector to all zeros or ones.
316
317 // Matches the semantics of vrgather.vx and vrgather.vv with extra operands
318 // for passthru and VL. Operands are (src, index, mask, passthru, vl).
322
323 // Vector sign/zero extend with additional mask & VL operands.
326
327 // vcpop.m with additional mask and VL operands.
329
330 // vfirst.m with additional mask and VL operands.
332
333 // Reads value of CSR.
334 // The first operand is a chain pointer. The second specifies address of the
335 // required CSR. Two results are produced, the read value and the new chain
336 // pointer.
338 // Write value to CSR.
339 // The first operand is a chain pointer, the second specifies address of the
340 // required CSR and the third is the value to write. The result is the new
341 // chain pointer.
343 // Read and write value of CSR.
344 // The first operand is a chain pointer, the second specifies address of the
345 // required CSR and the third is the value to write. Two results are produced,
346 // the value read before the modification and the new chain pointer.
348
349 // FP to 32 bit int conversions for RV64. These are used to keep track of the
350 // result being sign extended to 64 bit. These saturate out of range inputs.
373
374 // WARNING: Do not add anything in the end unless you want the node to
375 // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
376 // opcodes will be thought as target memory ops!
377
378 // Represents an AUIPC+L[WD] pair. Selected to PseudoLGA.
380 // Load initial exec thread-local address.
382
388};
389} // namespace RISCVISD
390
392 const RISCVSubtarget &Subtarget;
393
394public:
395 explicit RISCVTargetLowering(const TargetMachine &TM,
396 const RISCVSubtarget &STI);
397
398 const RISCVSubtarget &getSubtarget() const { return Subtarget; }
399
400 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
401 MachineFunction &MF,
402 unsigned Intrinsic) const override;
403 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
404 unsigned AS,
405 Instruction *I = nullptr) const override;
406 bool isLegalICmpImmediate(int64_t Imm) const override;
407 bool isLegalAddImmediate(int64_t Imm) const override;
408 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
409 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
410 bool isZExtFree(SDValue Val, EVT VT2) const override;
411 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
412 bool signExtendConstant(const ConstantInt *CI) const override;
413 bool isCheapToSpeculateCttz(Type *Ty) const override;
414 bool isCheapToSpeculateCtlz(Type *Ty) const override;
415 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
416 bool hasAndNotCompare(SDValue Y) const override;
417 bool hasBitTest(SDValue X, SDValue Y) const override;
420 unsigned OldShiftOpcode, unsigned NewShiftOpcode,
421 SelectionDAG &DAG) const override;
422 /// Return true if the (vector) instruction I will be lowered to an instruction
423 /// with a scalar splat operand for the given Operand number.
424 bool canSplatOperand(Instruction *I, int Operand) const;
425 /// Return true if a vector instruction will lower to a target instruction
426 /// able to splat the given operand.
427 bool canSplatOperand(unsigned Opcode, int Operand) const;
429 SmallVectorImpl<Use *> &Ops) const override;
430 bool shouldScalarizeBinop(SDValue VecOp) const override;
431 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
432 int getLegalZfaFPImm(const APFloat &Imm, EVT VT) const;
433 bool isFPImmLegal(const APFloat &Imm, EVT VT,
434 bool ForCodeSize) const override;
435 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
436 unsigned Index) const override;
437
438 bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
439
440 bool preferScalarizeSplat(SDNode *N) const override;
441
442 bool softPromoteHalfType() const override { return true; }
443
444 /// Return the register type for a given MVT, ensuring vectors are treated
445 /// as a series of gpr sized integers.
447 EVT VT) const override;
448
449 /// Return the number of registers for a given MVT, ensuring vectors are
450 /// treated as a series of gpr sized integers.
453 EVT VT) const override;
454
455 bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode,
456 EVT VT) const override;
457
458 /// Return true if the given shuffle mask can be codegen'd directly, or if it
459 /// should be stack expanded.
460 bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
461
462 bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override {
463 // If the pair to store is a mixture of float and int values, we will
464 // save two bitwise instructions and one float-to-int instruction and
465 // increase one store instruction. There is potentially a more
466 // significant benefit because it avoids the float->int domain switch
467 // for input value. So It is more likely a win.
468 if ((LTy.isFloatingPoint() && HTy.isInteger()) ||
469 (LTy.isInteger() && HTy.isFloatingPoint()))
470 return true;
471 // If the pair only contains int values, we will save two bitwise
472 // instructions and increase one store instruction (costing one more
473 // store buffer). Since the benefit is more blurred we leave such a pair
474 // out until we get testcase to prove it is a win.
475 return false;
476 }
477
478 bool
480 unsigned DefinedValues) const override;
481
482 // Provide custom lowering hooks for some operations.
483 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
485 SelectionDAG &DAG) const override;
486
487 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
488
490 const APInt &DemandedElts,
491 TargetLoweringOpt &TLO) const override;
492
494 KnownBits &Known,
495 const APInt &DemandedElts,
496 const SelectionDAG &DAG,
497 unsigned Depth) const override;
499 const APInt &DemandedElts,
500 const SelectionDAG &DAG,
501 unsigned Depth) const override;
502
503 const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const override;
504
505 // This method returns the name of a target specific DAG node.
506 const char *getTargetNodeName(unsigned Opcode) const override;
507
509 getTargetMMOFlags(const Instruction &I) const override;
510
512 getTargetMMOFlags(const MemSDNode &Node) const override;
513
514 bool
516 const MemSDNode &NodeY) const override;
517
518 ConstraintType getConstraintType(StringRef Constraint) const override;
519
520 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
521
522 std::pair<unsigned, const TargetRegisterClass *>
524 StringRef Constraint, MVT VT) const override;
525
526 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
527 std::vector<SDValue> &Ops,
528 SelectionDAG &DAG) const override;
529
532 MachineBasicBlock *BB) const override;
533
535 SDNode *Node) const override;
536
538 EVT VT) const override;
539
540 bool shouldFormOverflowOp(unsigned Opcode, EVT VT,
541 bool MathUsed) const override {
542 if (VT == MVT::i8 || VT == MVT::i16)
543 return false;
544
545 return TargetLowering::shouldFormOverflowOp(Opcode, VT, MathUsed);
546 }
547
548 bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem,
549 unsigned AddrSpace) const override {
550 // If we can replace 4 or more scalar stores, there will be a reduction
551 // in instructions even after we add a vector constant load.
552 return NumElem >= 4;
553 }
554
555 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
556 return VT.isScalarInteger();
557 }
558 bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
559
560 bool preferZeroCompareBranch() const override { return true; }
561
562 bool shouldInsertFencesForAtomic(const Instruction *I) const override {
563 return isa<LoadInst>(I) || isa<StoreInst>(I);
564 }
566 AtomicOrdering Ord) const override;
568 AtomicOrdering Ord) const override;
569
571 EVT VT) const override;
572
574 return ISD::SIGN_EXTEND;
575 }
576
578 return ISD::SIGN_EXTEND;
579 }
580
582 unsigned KeptBits) const override;
583
586 unsigned ExpansionFactor) const override {
590 ExpansionFactor);
591 }
592
594 CombineLevel Level) const override;
595
596 /// If a physical register, this returns the register that receives the
597 /// exception address on entry to an EH pad.
599 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
600
601 /// If a physical register, this returns the register that receives the
602 /// exception typeid on entry to a landing pad.
604 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
605
606 bool shouldExtendTypeInLibCall(EVT Type) const override;
607 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
608
609 /// Returns the register with the specified architectural or ABI name. This
610 /// method is necessary to lower the llvm.read_register.* and
611 /// llvm.write_register.* intrinsics. Allocatable registers must be reserved
612 /// with the clang -ffixed-xX flag for access to be allowed.
613 Register getRegisterByName(const char *RegName, LLT VT,
614 const MachineFunction &MF) const override;
615
616 // Lower incoming arguments, copy physregs into vregs
618 bool IsVarArg,
620 const SDLoc &DL, SelectionDAG &DAG,
621 SmallVectorImpl<SDValue> &InVals) const override;
623 bool IsVarArg,
625 LLVMContext &Context) const override;
626 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
628 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
629 SelectionDAG &DAG) const override;
631 SmallVectorImpl<SDValue> &InVals) const override;
632
634 Type *Ty) const override;
635 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
636 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
637 bool shouldConsiderGEPOffsetSplit() const override { return true; }
638
639 bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
640 SDValue C) const override;
641
643 SDValue ConstNode) const override;
644
646 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
648 Value *AlignedAddr, Value *Incr,
649 Value *Mask, Value *ShiftAmt,
650 AtomicOrdering Ord) const override;
655 Value *AlignedAddr, Value *CmpVal,
656 Value *NewVal, Value *Mask,
657 AtomicOrdering Ord) const override;
658
659 /// Returns true if the target allows unaligned memory accesses of the
660 /// specified type.
662 EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
664 unsigned *Fast = nullptr) const override;
665
667 SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
668 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
669 const override;
670
672 SelectionDAG & DAG, const SDLoc &DL, const SDValue *Parts,
673 unsigned NumParts, MVT PartVT, EVT ValueVT,
674 std::optional<CallingConv::ID> CC) const override;
675
676 // Return the value of VLMax for the given vector type (i.e. SEW and LMUL)
677 SDValue computeVLMax(MVT VecVT, const SDLoc &DL, SelectionDAG &DAG) const;
678
679 static RISCVII::VLMUL getLMUL(MVT VT);
680 inline static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize,
681 unsigned MinSize) {
682 // Original equation:
683 // VLMAX = (VectorBits / EltSize) * LMUL
684 // where LMUL = MinSize / RISCV::RVVBitsPerBlock
685 // The following equations have been reordered to prevent loss of precision
686 // when calculating fractional LMUL.
687 return ((VectorBits / EltSize) * MinSize) / RISCV::RVVBitsPerBlock;
688 };
689 static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul);
690 static unsigned getSubregIndexByMVT(MVT VT, unsigned Index);
691 static unsigned getRegClassIDForVecVT(MVT VT);
692 static std::pair<unsigned, unsigned>
694 unsigned InsertExtractIdx,
695 const RISCVRegisterInfo *TRI);
697
698 bool shouldRemoveExtendFromGSIndex(EVT IndexVT, EVT DataVT) const override;
699
700 bool isLegalElementTypeForRVV(EVT ScalarTy) const;
701
702 bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
703
704 unsigned getJumpTableEncoding() const override;
705
707 const MachineBasicBlock *MBB,
708 unsigned uid,
709 MCContext &Ctx) const override;
710
711 bool isVScaleKnownToBeAPowerOfTwo() const override;
712
714 ISD::MemIndexedMode &AM, bool &IsInc,
715 SelectionDAG &DAG) const;
718 SelectionDAG &DAG) const override;
721 SelectionDAG &DAG) const override;
722
724 uint64_t ElemSize) const override {
725 // Scaled addressing not supported on indexed load/stores
726 return Scale == 1;
727 }
728
729 /// If the target has a standard location for the stack protector cookie,
730 /// returns the address of that location. Otherwise, returns nullptr.
731 Value *getIRStackGuard(IRBuilderBase &IRB) const override;
732
733 /// Returns whether or not generating a fixed length interleaved load/store
734 /// intrinsic for this type will be legal.
735 bool isLegalInterleavedAccessType(FixedVectorType *, unsigned Factor,
736 const DataLayout &) const;
737
738 /// Return true if a stride load store of the given result type and
739 /// alignment is legal.
740 bool isLegalStridedLoadStore(EVT DataType, Align Alignment) const;
741
742 unsigned getMaxSupportedInterleaveFactor() const override { return 8; }
743
746 ArrayRef<unsigned> Indices,
747 unsigned Factor) const override;
748
750 unsigned Factor) const override;
751
752 /// RISCVCCAssignFn - This target-specific function extends the default
753 /// CCValAssign with additional information used to lower RISC-V calling
754 /// conventions.
756 unsigned ValNo, MVT ValVT, MVT LocVT,
757 CCValAssign::LocInfo LocInfo,
758 ISD::ArgFlagsTy ArgFlags, CCState &State,
759 bool IsFixed, bool IsRet, Type *OrigTy,
760 const RISCVTargetLowering &TLI,
761 std::optional<unsigned> FirstMaskArgument);
762
763private:
764 void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
765 const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
766 RISCVCCAssignFn Fn) const;
767 void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
769 bool IsRet, CallLoweringInfo *CLI,
770 RISCVCCAssignFn Fn) const;
771
772 template <class NodeTy>
773 SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true,
774 bool IsExternWeak = false) const;
775 SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
776 bool UseGOT) const;
777 SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
778
779 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
780 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
781 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
782 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
783 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
784 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
785 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
786 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
787 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
788 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
789 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
790 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
791 SDValue lowerSPLAT_VECTOR_PARTS(SDValue Op, SelectionDAG &DAG) const;
792 SDValue lowerVectorMaskSplat(SDValue Op, SelectionDAG &DAG) const;
793 SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
794 int64_t ExtTrueVal) const;
795 SDValue lowerVectorMaskTruncLike(SDValue Op, SelectionDAG &DAG) const;
796 SDValue lowerVectorTruncLike(SDValue Op, SelectionDAG &DAG) const;
797 SDValue lowerVectorFPExtendOrRoundLike(SDValue Op, SelectionDAG &DAG) const;
798 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
799 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
800 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
801 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
802 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
803 SDValue lowerVPREDUCE(SDValue Op, SelectionDAG &DAG) const;
804 SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
805 SDValue lowerVectorMaskVecReduction(SDValue Op, SelectionDAG &DAG,
806 bool IsVP) const;
807 SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
808 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
809 SDValue lowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
810 SDValue lowerVECTOR_DEINTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
811 SDValue lowerVECTOR_INTERLEAVE(SDValue Op, SelectionDAG &DAG) const;
812 SDValue lowerSTEP_VECTOR(SDValue Op, SelectionDAG &DAG) const;
813 SDValue lowerVECTOR_REVERSE(SDValue Op, SelectionDAG &DAG) const;
814 SDValue lowerVECTOR_SPLICE(SDValue Op, SelectionDAG &DAG) const;
815 SDValue lowerABS(SDValue Op, SelectionDAG &DAG) const;
816 SDValue lowerMaskedLoad(SDValue Op, SelectionDAG &DAG) const;
817 SDValue lowerMaskedStore(SDValue Op, SelectionDAG &DAG) const;
818 SDValue lowerFixedLengthVectorFCOPYSIGNToRVV(SDValue Op,
819 SelectionDAG &DAG) const;
820 SDValue lowerMaskedGather(SDValue Op, SelectionDAG &DAG) const;
821 SDValue lowerMaskedScatter(SDValue Op, SelectionDAG &DAG) const;
822 SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const;
823 SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const;
824 SDValue lowerFixedLengthVectorSetccToRVV(SDValue Op, SelectionDAG &DAG) const;
825 SDValue lowerFixedLengthVectorLogicOpToRVV(SDValue Op, SelectionDAG &DAG,
826 unsigned MaskOpc,
827 unsigned VecOpc) const;
828 SDValue lowerFixedLengthVectorShiftToRVV(SDValue Op, SelectionDAG &DAG) const;
829 SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op,
830 SelectionDAG &DAG) const;
831 SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG, unsigned NewOpc,
832 bool HasMergeOp = false, bool HasMask = true) const;
833 SDValue LowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG) const;
834 SDValue lowerVPOp(SDValue Op, SelectionDAG &DAG, unsigned RISCVISDOpc,
835 bool HasMergeOp = false) const;
836 SDValue lowerLogicVPOp(SDValue Op, SelectionDAG &DAG, unsigned MaskOpc,
837 unsigned VecOpc) const;
838 SDValue lowerVPExtMaskOp(SDValue Op, SelectionDAG &DAG) const;
839 SDValue lowerVPSetCCMaskOp(SDValue Op, SelectionDAG &DAG) const;
840 SDValue lowerVPFPIntConvOp(SDValue Op, SelectionDAG &DAG,
841 unsigned RISCVISDOpc) const;
842 SDValue lowerVPStridedLoad(SDValue Op, SelectionDAG &DAG) const;
843 SDValue lowerVPStridedStore(SDValue Op, SelectionDAG &DAG) const;
844 SDValue lowerFixedLengthVectorExtendToRVV(SDValue Op, SelectionDAG &DAG,
845 unsigned ExtendOpc) const;
846 SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
847 SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
848
849 SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
850 SDValue lowerCTLZ_CTTZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) const;
851
852 SDValue lowerStrictFPExtendOrRoundLike(SDValue Op, SelectionDAG &DAG) const;
853
854 SDValue lowerVectorStrictFSetcc(SDValue Op, SelectionDAG &DAG) const;
855
856 SDValue expandUnalignedRVVLoad(SDValue Op, SelectionDAG &DAG) const;
857 SDValue expandUnalignedRVVStore(SDValue Op, SelectionDAG &DAG) const;
858
859 bool isEligibleForTailCallOptimization(
860 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
861 const SmallVector<CCValAssign, 16> &ArgLocs) const;
862
863 /// Generate error diagnostics if any register used by CC has been marked
864 /// reserved.
865 void validateCCReservedRegs(
866 const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs,
867 MachineFunction &MF) const;
868
869 bool useRVVForFixedLengthVectorVT(MVT VT) const;
870
871 MVT getVPExplicitVectorLengthTy() const override;
872
873 bool shouldExpandGetVectorLength(EVT TripCountVT, unsigned VF,
874 bool IsScalable) const override;
875
876 /// RVV code generation for fixed length vectors does not lower all
877 /// BUILD_VECTORs. This makes BUILD_VECTOR legalisation a source of stores to
878 /// merge. However, merging them creates a BUILD_VECTOR that is just as
879 /// illegal as the original, thus leading to an infinite legalisation loop.
880 /// NOTE: Once BUILD_VECTOR can be custom lowered for all legal vector types,
881 /// this override can be removed.
882 bool mergeStoresAfterLegalization(EVT VT) const override;
883
884 /// Disable normalizing
885 /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
886 /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y))
887 /// RISC-V doesn't have flags so it's better to perform the and/or in a GPR.
888 bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override {
889 return false;
890 };
891
892 /// For available scheduling models FDIV + two independent FMULs are much
893 /// faster than two FDIVs.
894 unsigned combineRepeatedFPDivisors() const override;
895};
896
897namespace RISCV {
898
899bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
900 MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo,
901 ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed,
902 bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI,
903 std::optional<unsigned> FirstMaskArgument);
904
905bool CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
906 MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo,
907 ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed,
908 bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI,
909 std::optional<unsigned> FirstMaskArgument);
910
911bool CC_RISCV_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
912 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
913 CCState &State);
914} // end namespace RISCV
915
916namespace RISCVVIntrinsicsTable {
917
919 unsigned IntrinsicID;
921 uint8_t VLOperand;
922 bool hasScalarOperand() const {
923 // 0xF is not valid. See NoScalarOperand in IntrinsicsRISCV.td.
924 return ScalarOperand != 0xF;
925 }
926 bool hasVLOperand() const {
927 // 0x1F is not valid. See NoVLOperand in IntrinsicsRISCV.td.
928 return VLOperand != 0x1F;
929 }
930};
931
932using namespace RISCV;
933
934#define GET_RISCVVIntrinsicsTable_DECL
935#include "RISCVGenSearchableTables.inc"
936#undef GET_RISCVVIntrinsicsTable_DECL
937
938} // end namespace RISCVVIntrinsicsTable
939
940} // end namespace llvm
941
942#endif
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
IRTranslator LLVM IR MI
#define RegName(no)
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
This file describes how to lower LLVM code to machine code.
@ Flags
Definition: TextStubV5.cpp:93
@ ABI
Definition: TextStubV5.cpp:100
Class for arbitrary precision integers.
Definition: APInt.h:75
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:513
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:718
CCState - This class holds information needed while lowering arguments and return values.
This class represents a function call, abstracting a target machine's calling convention.
This is the shared class of boolean and integer constants.
Definition: Constants.h:78
This is an important base class in LLVM.
Definition: Constant.h:41
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
Class to represent fixed width SIMD vectors.
Definition: DerivedTypes.h:536
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:642
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:94
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
An instruction for reading from memory.
Definition: Instructions.h:177
This class is used to represent ISD::LOAD nodes.
Context object for machine code objects.
Definition: MCContext.h:76
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Machine Value Type.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
Definition: MachineInstr.h:68
Flags
Flags values. These may be or'd together.
This is an abstract virtual class for memory operations.
static std::pair< unsigned, unsigned > decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT, unsigned InsertExtractIdx, const RISCVRegisterInfo *TRI)
bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, bool &IsInc, SelectionDAG &DAG) const
static unsigned getSubregIndexByMVT(MVT VT, unsigned Index)
Value * getIRStackGuard(IRBuilderBase &IRB) const override
If the target has a standard location for the stack protector cookie, returns the address of that loc...
bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override
Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) satur...
bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem, unsigned AddrSpace) const override
Return true if it is expected to be cheaper to do a store of vector constant with the given size and ...
bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const override
Check if sinking I's operands to I's basic block is profitable, because the operands can be folded in...
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT) const override
Return true if pulling a binary operation into a select with an identity constant is profitable.
bool isLegalInterleavedAccessType(FixedVectorType *, unsigned Factor, const DataLayout &) const
Returns whether or not generating a fixed length interleaved load/store intrinsic for this type will ...
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
bool preferZeroCompareBranch() const override
Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.
Value * emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override
Perform a masked atomicrmw using a target-specific intrinsic.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override
Returns true if the target allows unaligned memory accesses of the specified type.
const Constant * getTargetConstantFromLoad(LoadSDNode *LD) const override
This method returns the constant pool value that will be loaded by LD.
const RISCVSubtarget & getSubtarget() const
TargetLowering::ShiftLegalizationStrategy preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const override
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
bool preferScalarizeSplat(SDNode *N) const override
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
bool canSplatOperand(Instruction *I, int Operand) const
Return true if the (vector) instruction I will be lowered to an instruction with a scalar splat opera...
bool shouldExtendTypeInLibCall(EVT Type) const override
Returns true if arguments should be extended in lib calls.
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Return true if it is beneficial to convert a load of a constant to just the constant itself.
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
bool hasAndNotCompare(SDValue Y) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
bool shouldScalarizeBinop(SDValue VecOp) const override
Try to convert an extract element of a vector binary operation into an extract element followed by a ...
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to move this shift by a constant amount through its operand,...
bool areTwoSDNodeTargetMMOFlagsMergeable(const MemSDNode &NodeX, const MemSDNode &NodeY) const override
Return true if it is valid to merge the TargetMMOFlags in two SDNodes.
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize, unsigned MinSize)
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const override
Perform a masked cmpxchg using a target-specific intrinsic.
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
bool convertSelectOfConstantsToMath(EVT VT) const override
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
bool isMulAddWithConstProfitable(SDValue AddNode, SDValue ConstNode) const override
Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x,...
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
bool lowerInterleavedLoad(LoadInst *LI, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const override
Lower an interleaved load into a vlsegN intrinsic.
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
MVT getContainerForFixedLengthVector(MVT VT) const
static unsigned getRegClassIDForVecVT(MVT VT)
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
TargetLowering::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const override
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
SDValue computeVLMax(MVT VecVT, const SDLoc &DL, SelectionDAG &DAG) const
bool signExtendConstant(const ConstantInt *CI) const override
Return true if this constant should be sign extended when promoting to a larger type.
bool shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const override
Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be trun...
bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const override
Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>>...
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Returns the register with the specified architectural or ABI name.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul)
bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override
Return true if result of the specified node is used by a return node only.
bool softPromoteHalfType() const override
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
bool RISCVCCAssignFn(const DataLayout &DL, RISCVABI::ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, std::optional< unsigned > FirstMaskArgument)
RISCVCCAssignFn - This target-specific function extends the default CCValAssign with additional infor...
TargetLowering::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override
Returns true if arguments should be sign-extended in lib calls.
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
ISD::NodeType getExtendForAtomicCmpSwapArg() const override
Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_...
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
bool isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override
Return true if the given shuffle mask can be codegen'd directly, or if it should be stack expanded.
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const override
Lower an interleaved store into a vssegN intrinsic.
bool isLegalScaleForGatherScatter(uint64_t Scale, uint64_t ElemSize) const override
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
bool isLegalElementTypeForRVV(EVT ScalarTy) const
bool isVScaleKnownToBeAPowerOfTwo() const override
Return true only if vscale must be a power of two.
static RISCVII::VLMUL getLMUL(MVT VT)
int getLegalZfaFPImm(const APFloat &Imm, EVT VT) const
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, std::optional< CallingConv::ID > CC) const override
Target-specific splitting of values into parts that fit a register storing a legal type.
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
bool shouldConsiderGEPOffsetSplit() const override
bool isIntDivCheap(EVT VT, AttributeList Attr) const override
Return true if integer divide is usually cheaper than a sequence of several shifts,...
bool shouldRemoveExtendFromGSIndex(EVT IndexVT, EVT DataVT) const override
bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override
Try to convert math with an overflow comparison into the corresponding DAG node operation.
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's...
SDValue joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, std::optional< CallingConv::ID > CC) const override
Target-specific combining of register parts into its original value.
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
bool isLegalStridedLoadStore(EVT DataType, Align Alignment) const
Return true if a stride load store of the given result type and alignment is legal.
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:469
This instruction constructs a fixed permutation of two input vectors.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
An instruction for storing to memory.
Definition: Instructions.h:301
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const
Try to convert math with an overflow comparison into the corresponding DAG node operation.
ShiftLegalizationStrategy
Return the preferred strategy to legalize tihs SHIFT instruction, with ExpansionFactor being the recu...
virtual ShiftLegalizationStrategy preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1351
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:774
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1363
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1423
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
Definition: ISDOpcodes.h:1357
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #3 and #4) ...
bool CC_RISCV_GHC(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static constexpr unsigned RVVBitsPerBlock
bool CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, std::optional< unsigned > FirstMaskArgument)
bool CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsFixed, bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI, std::optional< unsigned > FirstMaskArgument)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:440
AtomicOrdering
Atomic ordering for LLVM's memory model.
CombineLevel
Definition: DAGCombine.h:15
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:139
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:149
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:144
This structure contains all information that is necessary for lowering calls.