LLVM  13.0.0git
RISCVISelLowering.h
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1 //===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that RISCV uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
15 #define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
16 
17 #include "RISCV.h"
20 
21 namespace llvm {
22 class RISCVSubtarget;
23 struct RISCVRegisterInfo;
24 namespace RISCVISD {
25 enum NodeType : unsigned {
32  /// Select with condition operator - This selects between a true value and
33  /// a false value (ops #3 and #4) based on the boolean result of comparing
34  /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
35  /// condition code in op #2, a XLenVT constant from the ISD::CondCode enum.
36  /// The lhs and rhs are XLenVT integers. The true and false values can be
37  /// integer or floating point.
42  // RV64I shifts, directly matching the semantics of the named RISC-V
43  // instructions.
47  // 32-bit operations from RV64M that can't be simply matched with a pattern
48  // at instruction selection time. These have undefined behavior for division
49  // by 0 or overflow (divw) like their target independent counterparts.
53  // RV64IB rotates, directly matching the semantics of the named RISC-V
54  // instructions.
57  // RV64IB/RV32IB funnel shifts, with the semantics of the named RISC-V
58  // instructions, but the same operand order as fshl/fshr intrinsics.
59  FSR,
60  FSL,
61  // RV64IB funnel shifts, with the semantics of the named RISC-V instructions,
62  // but the same operand order as fshl/fshr intrinsics.
65  // FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as
66  // XLEN is the only legal integer width.
67  //
68  // FMV_H_X matches the semantics of the FMV.H.X.
69  // FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result.
70  // FMV_W_X_RV64 matches the semantics of the FMV.W.X.
71  // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result.
72  //
73  // This is a more convenient semantic for producing dagcombines that remove
74  // unnecessary GPR->FPR->GPR moves.
79  // READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target
80  // (returns (Lo, Hi)). It takes a chain operand.
82  // Generalized Reverse and Generalized Or-Combine - directly matching the
83  // semantics of the named RISC-V instructions. Lowered as custom nodes as
84  // TableGen chokes when faced with commutative permutations in deeply-nested
85  // DAGs. Each node takes an input operand and a TargetConstant immediate
86  // shift amount, and outputs a bit-manipulated version of input. All operands
87  // are of type XLenVT.
93  // Vector Extension
94  // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand
95  // for the VL value to be used for the operation.
97  // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand
98  // for the VL value to be used for the operation.
100  // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign
101  // extended from the vector element size.
103  // VMV_S_XF_VL matches the semantics of vmv.s.x/vmv.s.f, depending on the
104  // types of its operands. It carries a VL operand.
106  // Splats an i64 scalar to a vector type (with element type i64) where the
107  // scalar is a sign-extended i32.
109  // Read VLENB CSR
111  // Truncates a RVV integer vector by one power-of-two. Carries both an extra
112  // mask and VL operand.
114  // Unit-stride fault-only-first load
117  // Matches the semantics of vslideup/vslidedown. The first operand is the
118  // pass-thru operand, the second is the source vector, the third is the
119  // XLenVT index (either constant or non-constant), the fourth is the mask
120  // and the fifth the VL.
123  // Matches the semantics of the vid.v instruction, with a mask and VL
124  // operand.
126  // Matches the semantics of the vfcnvt.rod function (Convert double-width
127  // float to single-width float, rounding towards odd). Takes a double-width
128  // float vector and produces a single-width float vector. Also has a mask and
129  // VL operand.
131  // These nodes match the semantics of the corresponding RVV vector reduction
132  // instructions. They produce a vector result which is the reduction
133  // performed over the first vector operand plus the first element of the
134  // second vector operand. The first operand is an unconstrained vector type,
135  // and the result and second operand's types are expected to be the
136  // corresponding full-width LMUL=1 type for the first operand:
137  // nxv8i8 = vecreduce_add nxv32i8, nxv8i8
138  // nxv2i32 = vecreduce_add nxv8i32, nxv2i32
139  // The different in types does introduce extra vsetvli instructions but
140  // similarly it reduces the number of registers consumed per reduction.
151 
152  // Vector binary and unary ops with a mask as a third operand, and VL as a
153  // fourth operand.
154  // FIXME: Can we replace these with ISD::VP_*?
188 
189  // Vector compare producing a mask. Fourth operand is input mask. Fifth
190  // operand is VL.
192 
193  // Vector select with an additional VL operand. This operation is unmasked.
195 
196  // Mask binary operators.
200 
201  // Set mask vector to all zeros or ones.
204 
205  // Matches the semantics of vrgather.vx with an extra operand for VL.
207 
208  // Vector sign/zero extend with additional mask & VL operands.
211 
212  // Memory opcodes start here.
215 
216  // WARNING: Do not add anything in the end unless you want the node to
217  // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
218  // opcodes will be thought as target memory ops!
219 };
220 } // namespace RISCVISD
221 
223  const RISCVSubtarget &Subtarget;
224 
225 public:
226  explicit RISCVTargetLowering(const TargetMachine &TM,
227  const RISCVSubtarget &STI);
228 
229  const RISCVSubtarget &getSubtarget() const { return Subtarget; }
230 
231  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
232  MachineFunction &MF,
233  unsigned Intrinsic) const override;
234  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
235  unsigned AS,
236  Instruction *I = nullptr) const override;
237  bool isLegalICmpImmediate(int64_t Imm) const override;
238  bool isLegalAddImmediate(int64_t Imm) const override;
239  bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
240  bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
241  bool isZExtFree(SDValue Val, EVT VT2) const override;
242  bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
243  bool isCheapToSpeculateCttz() const override;
244  bool isCheapToSpeculateCtlz() const override;
245  bool isFPImmLegal(const APFloat &Imm, EVT VT,
246  bool ForCodeSize) const override;
247 
248  bool hasBitPreservingFPLogic(EVT VT) const override;
249  bool
251  unsigned DefinedValues) const override;
252 
253  // Provide custom lowering hooks for some operations.
254  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
256  SelectionDAG &DAG) const override;
257 
258  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
259 
261  const APInt &DemandedElts,
262  TargetLoweringOpt &TLO) const override;
263 
265  KnownBits &Known,
266  const APInt &DemandedElts,
267  const SelectionDAG &DAG,
268  unsigned Depth) const override;
270  const APInt &DemandedElts,
271  const SelectionDAG &DAG,
272  unsigned Depth) const override;
273 
274  // This method returns the name of a target specific DAG node.
275  const char *getTargetNodeName(unsigned Opcode) const override;
276 
277  ConstraintType getConstraintType(StringRef Constraint) const override;
278 
279  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
280 
281  std::pair<unsigned, const TargetRegisterClass *>
283  StringRef Constraint, MVT VT) const override;
284 
285  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
286  std::vector<SDValue> &Ops,
287  SelectionDAG &DAG) const override;
288 
291  MachineBasicBlock *BB) const override;
292 
294  EVT VT) const override;
295 
296  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
297  return VT.isScalarInteger();
298  }
299  bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
300 
301  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
302  return isa<LoadInst>(I) || isa<StoreInst>(I);
303  }
305  AtomicOrdering Ord) const override;
307  AtomicOrdering Ord) const override;
308 
310  EVT VT) const override;
311 
313  return ISD::SIGN_EXTEND;
314  }
315 
317  return ISD::SIGN_EXTEND;
318  }
319 
320  bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override {
322  return false;
323  return true;
324  }
326  CombineLevel Level) const override;
327 
328  /// If a physical register, this returns the register that receives the
329  /// exception address on entry to an EH pad.
330  Register
331  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
332 
333  /// If a physical register, this returns the register that receives the
334  /// exception typeid on entry to a landing pad.
335  Register
336  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
337 
338  bool shouldExtendTypeInLibCall(EVT Type) const override;
339  bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
340 
341  /// Returns the register with the specified architectural or ABI name. This
342  /// method is necessary to lower the llvm.read_register.* and
343  /// llvm.write_register.* intrinsics. Allocatable registers must be reserved
344  /// with the clang -ffixed-xX flag for access to be allowed.
345  Register getRegisterByName(const char *RegName, LLT VT,
346  const MachineFunction &MF) const override;
347 
348  // Lower incoming arguments, copy physregs into vregs
350  bool IsVarArg,
352  const SDLoc &DL, SelectionDAG &DAG,
353  SmallVectorImpl<SDValue> &InVals) const override;
355  bool IsVarArg,
357  LLVMContext &Context) const override;
358  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
360  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
361  SelectionDAG &DAG) const override;
363  SmallVectorImpl<SDValue> &InVals) const override;
364 
366  Type *Ty) const override {
367  return true;
368  }
369  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
370  bool shouldConsiderGEPOffsetSplit() const override { return true; }
371 
373  SDValue C) const override;
374 
376  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
378  Value *AlignedAddr, Value *Incr,
379  Value *Mask, Value *ShiftAmt,
380  AtomicOrdering Ord) const override;
384  AtomicCmpXchgInst *CI,
385  Value *AlignedAddr, Value *CmpVal,
386  Value *NewVal, Value *Mask,
387  AtomicOrdering Ord) const override;
388 
389  /// Returns true if the target allows unaligned memory accesses of the
390  /// specified type.
392  EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
394  bool *Fast = nullptr) const override;
395 
396  static RISCVVLMUL getLMUL(MVT VT);
397  static unsigned getRegClassIDForLMUL(RISCVVLMUL LMul);
398  static unsigned getSubregIndexByMVT(MVT VT, unsigned Index);
399  static unsigned getRegClassIDForVecVT(MVT VT);
400  static std::pair<unsigned, unsigned>
402  unsigned InsertExtractIdx,
403  const RISCVRegisterInfo *TRI);
405  const RISCVSubtarget &Subtarget);
406 
407 private:
408  void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
410  bool IsRet) const;
411  void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
413  bool IsRet, CallLoweringInfo *CLI) const;
414 
415  template <class NodeTy>
416  SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const;
417 
418  SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
419  bool UseGOT) const;
420  SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
421 
422  SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
423  SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
424  SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
425  SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
426  SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
427  SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
428  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
429  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
430  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
431  SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
432  SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
433  SDValue lowerSPLATVECTOR(SDValue Op, SelectionDAG &DAG) const;
434  SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
435  int64_t ExtTrueVal) const;
436  SDValue lowerVectorMaskTrunc(SDValue Op, SelectionDAG &DAG) const;
437  SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
438  SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
439  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
440  SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
441  SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
442  SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
443  SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
444  SDValue lowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
445  SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const;
446  SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const;
447  SDValue lowerFixedLengthVectorSetccToRVV(SDValue Op, SelectionDAG &DAG) const;
448  SDValue lowerFixedLengthVectorLogicOpToRVV(SDValue Op, SelectionDAG &DAG,
449  unsigned MaskOpc,
450  unsigned VecOpc) const;
451  SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op,
452  SelectionDAG &DAG) const;
453  SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG, unsigned NewOpc,
454  bool HasMask = true) const;
455  SDValue lowerFixedLengthVectorExtendToRVV(SDValue Op, SelectionDAG &DAG,
456  unsigned ExtendOpc) const;
457 
458  bool isEligibleForTailCallOptimization(
459  CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
460  const SmallVector<CCValAssign, 16> &ArgLocs) const;
461 
462  /// Generate error diagnostics if any register used by CC has been marked
463  /// reserved.
464  void validateCCReservedRegs(
465  const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs,
466  MachineFunction &MF) const;
467 
468  bool useRVVForFixedLengthVectorVT(MVT VT) const;
469 };
470 
471 namespace RISCV {
472 // We use 64 bits as the known part in the scalable vector types.
473 static constexpr unsigned RVVBitsPerBlock = 64;
474 } // namespace RISCV
475 
476 namespace RISCVVIntrinsicsTable {
477 
479  unsigned IntrinsicID;
481 };
482 
483 using namespace RISCV;
484 
485 #define GET_RISCVVIntrinsicsTable_DECL
486 #include "RISCVGenSearchableTables.inc"
487 
488 } // end namespace RISCVVIntrinsicsTable
489 
490 } // end namespace llvm
491 
492 #endif
llvm::RISCVTargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: RISCVISelLowering.cpp:6180
llvm::RISCVISD::SUB_VL
@ SUB_VL
Definition: RISCVISelLowering.h:164
llvm::RISCVISD::READ_CYCLE_WIDE
@ READ_CYCLE_WIDE
Definition: RISCVISelLowering.h:81
llvm::RISCVISD::AND_VL
@ AND_VL
Definition: RISCVISelLowering.h:156
llvm::RISCVISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: RISCVISelLowering.h:26
llvm::RISCVISD::VECREDUCE_UMIN
@ VECREDUCE_UMIN
Definition: RISCVISelLowering.h:144
llvm::RISCVISD::SMAX_VL
@ SMAX_VL
Definition: RISCVISelLowering.h:177
llvm::RISCVISD::SINT_TO_FP_VL
@ SINT_TO_FP_VL
Definition: RISCVISelLowering.h:184
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm
This class represents lattice values for constants.
Definition: AllocatorList.h:23
llvm::RISCVISD::SLLW
@ SLLW
Definition: RISCVISelLowering.h:44
llvm::RISCVTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: RISCVISelLowering.cpp:4408
llvm::RISCVTargetLowering::isSExtCheaperThanZExt
bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
Definition: RISCVISelLowering.cpp:769
llvm::EVT::isScalarInteger
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:144
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1078
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:111
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4103
llvm::RISCVTargetLowering::shouldConvertConstantLoadToIntImm
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Return true if it is beneficial to convert a load of a constant to just the constant itself.
Definition: RISCVISelLowering.h:365
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:191
llvm::RISCVTargetLowering::emitLeadingFence
Instruction * emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
Definition: RISCVISelLowering.cpp:6002
llvm::RISCVTargetLowering::RISCVTargetLowering
RISCVTargetLowering(const TargetMachine &TM, const RISCVSubtarget &STI)
Definition: RISCVISelLowering.cpp:45
llvm::RISCVISD::FMV_H_X
@ FMV_H_X
Definition: RISCVISelLowering.h:75
llvm::RISCVRegisterInfo
Definition: RISCVRegisterInfo.h:23
llvm::RISCVISD::DIVUW
@ DIVUW
Definition: RISCVISelLowering.h:51
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::RISCVISD::VRGATHER_VX_VL
@ VRGATHER_VX_VL
Definition: RISCVISelLowering.h:206
llvm::RISCVTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: RISCVISelLowering.cpp:5830
llvm::RISCVISD::VECREDUCE_ADD
@ VECREDUCE_ADD
Definition: RISCVISelLowering.h:141
llvm::RISCVISD::VMAND_VL
@ VMAND_VL
Definition: RISCVISelLowering.h:197
llvm::RISCVISD::SDIV_VL
@ SDIV_VL
Definition: RISCVISelLowering.h:159
llvm::RISCVTargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: RISCVISelLowering.cpp:3969
llvm::RISCVISD::MULHU_VL
@ MULHU_VL
Definition: RISCVISelLowering.h:181
llvm::RISCVISD::GREVI
@ GREVI
Definition: RISCVISelLowering.h:88
llvm::IRBuilder<>
llvm::RISCVISD::VZEXT_VL
@ VZEXT_VL
Definition: RISCVISelLowering.h:210
llvm::RISCVTargetLowering::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
Definition: RISCVISelLowering.cpp:673
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::RISCVTargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const override
Returns true if the target allows unaligned memory accesses of the specified type.
Definition: RISCVISelLowering.cpp:6288
llvm::RISCVISD::VECREDUCE_SMAX
@ VECREDUCE_SMAX
Definition: RISCVISelLowering.h:143
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:34
llvm::RISCVISD::MUL_VL
@ MUL_VL
Definition: RISCVISelLowering.h:157
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::RISCVTargetLowering::getExtendForAtomicCmpSwapArg
ISD::NodeType getExtendForAtomicCmpSwapArg() const override
Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_...
Definition: RISCVISelLowering.h:316
llvm::RISCVISD::SHL_VL
@ SHL_VL
Definition: RISCVISelLowering.h:160
llvm::RISCVISD::ADD_VL
@ ADD_VL
Definition: RISCVISelLowering.h:155
llvm::RISCVISD::VMV_S_XF_VL
@ VMV_S_XF_VL
Definition: RISCVISelLowering.h:105
llvm::RISCVISD::VECREDUCE_OR
@ VECREDUCE_OR
Definition: RISCVISelLowering.h:147
llvm::RISCVISD::VMXOR_VL
@ VMXOR_VL
Definition: RISCVISelLowering.h:199
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:847
llvm::RISCVTargetLowering::shouldExpandAtomicRMWInIR
TargetLowering::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition: RISCVISelLowering.cpp:6021
llvm::RISCVTargetLowering::getRegClassIDForVecVT
static unsigned getRegClassIDForVecVT(MVT VT)
Definition: RISCVISelLowering.cpp:904
llvm::RISCVTargetLowering::LowerFormalArguments
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition: RISCVISelLowering.cpp:5052
llvm::RISCVISD::VSE_VL
@ VSE_VL
Definition: RISCVISelLowering.h:214
SelectionDAG.h
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1541
llvm::RISCVTargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: RISCVISelLowering.cpp:777
llvm::RISCVTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: RISCVISelLowering.cpp:5695
llvm::RISCVISD::GORCIW
@ GORCIW
Definition: RISCVISelLowering.h:91
llvm::RISCVISD::VID_VL
@ VID_VL
Definition: RISCVISelLowering.h:125
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::RISCVTargetLowering::targetShrinkDemandedConstant
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
Definition: RISCVISelLowering.cpp:3904
llvm::RISCVISD::VSEXT_VL
@ VSEXT_VL
Definition: RISCVISelLowering.h:209
TargetLowering.h
llvm::RISCVISD::FMV_X_ANYEXTH
@ FMV_X_ANYEXTH
Definition: RISCVISelLowering.h:76
llvm::RISCVTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: RISCVISelLowering.cpp:3637
llvm::RISCVISD::SMIN_VL
@ SMIN_VL
Definition: RISCVISelLowering.h:176
llvm::RISCVTargetLowering::shouldSignExtendTypeInLibCall
bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override
Returns true if arguments should be sign-extended in lib calls.
Definition: RISCVISelLowering.cpp:6200
llvm::RISCVISD::VLE_VL
@ VLE_VL
Definition: RISCVISelLowering.h:213
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:223
llvm::RISCVTargetLowering::hasBitPreservingFPLogic
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Definition: RISCVISelLowering.cpp:794
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::IntrinsicID
unsigned IntrinsicID
Definition: RISCVISelLowering.h:479
llvm::RISCVISD::SPLAT_VECTOR_I64
@ SPLAT_VECTOR_I64
Definition: RISCVISelLowering.h:108
llvm::RISCVTargetLowering::isCheapToSpeculateCttz
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
Definition: RISCVISelLowering.cpp:773
llvm::RISCVISD::CALL
@ CALL
Definition: RISCVISelLowering.h:31
llvm::RISCVISD::VECREDUCE_FADD
@ VECREDUCE_FADD
Definition: RISCVISelLowering.h:149
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::ExtendedOperand
uint8_t ExtendedOperand
Definition: RISCVISelLowering.h:480
llvm::RISCVISD::VECREDUCE_XOR
@ VECREDUCE_XOR
Definition: RISCVISelLowering.h:148
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3143
llvm::RISCVISD::VMCLR_VL
@ VMCLR_VL
Definition: RISCVISelLowering.h:202
llvm::RISCVTargetLowering::getSubregIndexByMVT
static unsigned getSubregIndexByMVT(MVT VT, unsigned Index)
Definition: RISCVISelLowering.cpp:883
llvm::RISCVISD::FADD_VL
@ FADD_VL
Definition: RISCVISelLowering.h:168
llvm::RISCVISD::VLEFF
@ VLEFF
Definition: RISCVISelLowering.h:115
llvm::RISCVISD::FSL
@ FSL
Definition: RISCVISelLowering.h:60
llvm::RISCVISD::MULHS_VL
@ MULHS_VL
Definition: RISCVISelLowering.h:180
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::RISCVTargetLowering::LowerCall
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Definition: RISCVISelLowering.cpp:5277
llvm::Instruction
Definition: Instruction.h:45
llvm::RISCVTargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: RISCVISelLowering.cpp:6185
llvm::RISCVISD::VECREDUCE_UMAX
@ VECREDUCE_UMAX
Definition: RISCVISelLowering.h:142
llvm::RISCVISD::VECREDUCE_AND
@ VECREDUCE_AND
Definition: RISCVISelLowering.h:146
llvm::RISCVTargetLowering::convertSelectOfConstantsToMath
bool convertSelectOfConstantsToMath(EVT VT) const override
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
Definition: RISCVISelLowering.h:299
llvm::RISCVISD::FMV_W_X_RV64
@ FMV_W_X_RV64
Definition: RISCVISelLowering.h:77
llvm::RISCVISD::FSLW
@ FSLW
Definition: RISCVISelLowering.h:64
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:26
llvm::RISCVISD::VSELECT_VL
@ VSELECT_VL
Definition: RISCVISelLowering.h:194
llvm::RISCVISD::UMIN_VL
@ UMIN_VL
Definition: RISCVISelLowering.h:178
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::RISCVTargetLowering::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
Definition: RISCVISelLowering.cpp:731
llvm::RISCVISD::SRL_VL
@ SRL_VL
Definition: RISCVISelLowering.h:163
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::RISCVTargetLowering::decomposeMulByConstant
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
Definition: RISCVISelLowering.cpp:6207
llvm::RISCVISD::DIVW
@ DIVW
Definition: RISCVISelLowering.h:50
llvm::RISCVTargetLowering::getRegClassIDForLMUL
static unsigned getRegClassIDForLMUL(RISCVVLMUL LMul)
Definition: RISCVISelLowering.cpp:865
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::RISCVTargetLowering::shouldExpandShift
bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
Definition: RISCVISelLowering.h:320
llvm::RISCVISD::VFNCVT_ROD_VL
@ VFNCVT_ROD_VL
Definition: RISCVISelLowering.h:130
llvm::RISCVISD::FABS_VL
@ FABS_VL
Definition: RISCVISelLowering.h:173
llvm::RISCVISD::FNEG_VL
@ FNEG_VL
Definition: RISCVISelLowering.h:172
llvm::RISCVISD::SplitF64
@ SplitF64
Definition: RISCVISelLowering.h:40
llvm::RISCVISD::FP_TO_UINT_VL
@ FP_TO_UINT_VL
Definition: RISCVISelLowering.h:183
llvm::RISCVISD::SREM_VL
@ SREM_VL
Definition: RISCVISelLowering.h:161
llvm::RISCV::RVVBitsPerBlock
static constexpr unsigned RVVBitsPerBlock
Definition: RISCVISelLowering.h:473
llvm::RISCVISD::UINT_TO_FP_VL
@ UINT_TO_FP_VL
Definition: RISCVISelLowering.h:185
llvm::RISCVISD::GREVIW
@ GREVIW
Definition: RISCVISelLowering.h:89
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::RISCVISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #3 and #4) ...
Definition: RISCVISelLowering.h:38
llvm::APFloat
Definition: APFloat.h:701
llvm::RISCVTargetLowering::convertSetCCLogicToBitwiseLogic
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Definition: RISCVISelLowering.h:296
llvm::RISCVISD::FMV_X_ANYEXTW_RV64
@ FMV_X_ANYEXTW_RV64
Definition: RISCVISelLowering.h:78
llvm::RISCVTargetLowering::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: RISCVISelLowering.cpp:727
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::RISCVISD::SETCC_VL
@ SETCC_VL
Definition: RISCVISelLowering.h:191
Index
uint32_t Index
Definition: ELFObjHandler.cpp:84
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:63
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::RISCVISD::VSLIDEDOWN_VL
@ VSLIDEDOWN_VL
Definition: RISCVISelLowering.h:122
llvm::DemandedBits
Definition: DemandedBits.h:40
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::RISCVISD::MRET_FLAG
@ MRET_FLAG
Definition: RISCVISelLowering.h:30
llvm::RISCVISD::XOR_VL
@ XOR_VL
Definition: RISCVISelLowering.h:167
llvm::RISCVISD::ROLW
@ ROLW
Definition: RISCVISelLowering.h:55
llvm::RISCVTargetLowering::isTruncateFree
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
Definition: RISCVISelLowering.cpp:738
llvm::RISCVTargetLowering::shouldConsiderGEPOffsetSplit
bool shouldConsiderGEPOffsetSplit() const override
Definition: RISCVISelLowering.h:370
llvm::RISCVTargetLowering::getInlineAsmMemConstraint
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Definition: RISCVISelLowering.cpp:5950
llvm::RISCVTargetLowering::ComputeNumSignBitsForTargetNode
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
Definition: RISCVISelLowering.cpp:4014
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:3694
llvm::RISCVTargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: RISCVISelLowering.cpp:701
llvm::RISCVTargetLowering::isZExtFree
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
Definition: RISCVISelLowering.cpp:755
llvm::RISCVISD::OR_VL
@ OR_VL
Definition: RISCVISelLowering.h:158
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::RISCVTargetLowering::getLMUL
static RISCVVLMUL getLMUL(MVT VT)
Definition: RISCVISelLowering.cpp:839
llvm::RISCVTargetLowering::isDesirableToCommuteWithShift
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to move this shift by a constant amount though its operand,...
Definition: RISCVISelLowering.cpp:3858
llvm::RISCVTargetLowering::getContainerForFixedLengthVector
static MVT getContainerForFixedLengthVector(SelectionDAG &DAG, MVT VT, const RISCVSubtarget &Subtarget)
Definition: RISCVISelLowering.cpp:947
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:30
llvm::RISCVISD::SRAW
@ SRAW
Definition: RISCVISelLowering.h:45
llvm::RISCVTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Definition: RISCVISelLowering.cpp:3031
llvm::RISCVISD::READ_VLENB
@ READ_VLENB
Definition: RISCVISelLowering.h:110
llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Definition: RISCVISelLowering.cpp:6159
llvm::RISCVISD::VMOR_VL
@ VMOR_VL
Definition: RISCVISelLowering.h:198
RISCV.h
llvm::RISCVISD::FSRW
@ FSRW
Definition: RISCVISelLowering.h:63
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:643
llvm::RISCVISD::BuildPairF64
@ BuildPairF64
Definition: RISCVISelLowering.h:39
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:70
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::RISCVTargetLowering::getSubtarget
const RISCVSubtarget & getSubtarget() const
Definition: RISCVISelLowering.h:229
llvm::RISCVISD::FSUB_VL
@ FSUB_VL
Definition: RISCVISelLowering.h:169
llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs
static std::pair< unsigned, unsigned > decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT, unsigned InsertExtractIdx, const RISCVRegisterInfo *TRI)
Definition: RISCVISelLowering.cpp:916
llvm::RISCVISD::REMUW
@ REMUW
Definition: RISCVISelLowering.h:52
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::RISCVISD::VMV_V_X_VL
@ VMV_V_X_VL
Definition: RISCVISelLowering.h:96
llvm::RISCVTargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
Definition: RISCVISelLowering.cpp:5811
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::RISCVISD::FP_EXTEND_VL
@ FP_EXTEND_VL
Definition: RISCVISelLowering.h:187
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1201
llvm::RISCVISD::SHFLI
@ SHFLI
Definition: RISCVISelLowering.h:92
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:702
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::RISCVISD::FMUL_VL
@ FMUL_VL
Definition: RISCVISelLowering.h:170
llvm::RISCVISD::RORW
@ RORW
Definition: RISCVISelLowering.h:56
llvm::RISCVISD::VECREDUCE_SMIN
@ VECREDUCE_SMIN
Definition: RISCVISelLowering.h:145
llvm::RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic
Value * emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override
Perform a masked atomicrmw using a target-specific intrinsic.
Definition: RISCVISelLowering.cpp:6085
llvm::RISCVTargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
Definition: RISCVISelLowering.cpp:781
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1687
llvm::KnownBits
Definition: KnownBits.h:23
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:521
llvm::RISCVISD::VMSET_VL
@ VMSET_VL
Definition: RISCVISelLowering.h:203
llvm::RISCVISD::SRLW
@ SRLW
Definition: RISCVISelLowering.h:46
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:246
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:302
llvm::RISCVTargetLowering::CanLowerReturn
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition: RISCVISelLowering.cpp:5554
llvm::RISCVISD::RET_FLAG
@ RET_FLAG
Definition: RISCVISelLowering.h:27
llvm::RISCVISD::VECREDUCE_SEQ_FADD
@ VECREDUCE_SEQ_FADD
Definition: RISCVISelLowering.h:150
llvm::RISCVISD::FP_ROUND_VL
@ FP_ROUND_VL
Definition: RISCVISelLowering.h:186
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
llvm::RISCVTargetLowering
Definition: RISCVISelLowering.h:222
llvm::RISCVISD::GORCI
@ GORCI
Definition: RISCVISelLowering.h:90
llvm::RISCVTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: RISCVISelLowering.cpp:1135
llvm::RISCVISD::VMV_X_S
@ VMV_X_S
Definition: RISCVISelLowering.h:102
llvm::RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic
Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const override
Perform a masked cmpxchg using a target-specific intrinsic.
Definition: RISCVISelLowering.cpp:6137
llvm::RISCVTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: RISCVISelLowering.cpp:5964
llvm::RISCVISD::FSR
@ FSR
Definition: RISCVISelLowering.h:59
llvm::RISCVISD::VFMV_V_F_VL
@ VFMV_V_F_VL
Definition: RISCVISelLowering.h:99
llvm::RISCVTargetLowering::shouldInsertFencesForAtomic
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
Definition: RISCVISelLowering.h:301
llvm::RISCVISD::FP_TO_SINT_VL
@ FP_TO_SINT_VL
Definition: RISCVISelLowering.h:182
llvm::RISCVTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Returns the register with the specified architectural or ABI name.
Definition: RISCVISelLowering.cpp:6308
llvm::RISCVISD::UREM_VL
@ UREM_VL
Definition: RISCVISelLowering.h:166
llvm::RISCVISD::TAIL
@ TAIL
Definition: RISCVISelLowering.h:41
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo
Definition: RISCVISelLowering.h:478
llvm::CombineLevel
CombineLevel
Definition: DAGCombine.h:15
llvm::RISCVISD::VLEFF_MASK
@ VLEFF_MASK
Definition: RISCVISelLowering.h:116
llvm::RISCVISD::NodeType
NodeType
Definition: RISCVISelLowering.h:25
llvm::RISCVTargetLowering::shouldExpandBuildVectorWithShuffles
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
Definition: RISCVISelLowering.cpp:1035
llvm::RISCVISD::UMAX_VL
@ UMAX_VL
Definition: RISCVISelLowering.h:179
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1213
N
#define N
llvm::RISCVTargetLowering::emitTrailingFence
Instruction * emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Definition: RISCVISelLowering.cpp:6012
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:157
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::RISCVTargetLowering::shouldExtendTypeInLibCall
bool shouldExtendTypeInLibCall(EVT Type) const override
Returns true if arguments should be extended in lib calls.
Definition: RISCVISelLowering.cpp:6190
RegName
#define RegName(no)
llvm::Function::hasMinSize
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:682
llvm::RISCVVLMUL
RISCVVLMUL
Definition: RISCVBaseInfo.h:270
llvm::RISCVISD::SRET_FLAG
@ SRET_FLAG
Definition: RISCVISelLowering.h:29
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1450
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:444
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::RISCVTargetLowering::LowerReturn
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition: RISCVISelLowering.cpp:5577
llvm::RISCVTargetLowering::getExtendForAtomicOps
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
Definition: RISCVISelLowering.h:312
llvm::RISCVISD::FDIV_VL
@ FDIV_VL
Definition: RISCVISelLowering.h:171
llvm::RISCVTargetLowering::mayBeEmittedAsTailCall
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
Definition: RISCVISelLowering.cpp:5691
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:682
llvm::RISCVTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
Definition: RISCVISelLowering.cpp:662
llvm::RISCVISD::TRUNCATE_VECTOR_VL
@ TRUNCATE_VECTOR_VL
Definition: RISCVISelLowering.h:113
llvm::RISCVISD::FMA_VL
@ FMA_VL
Definition: RISCVISelLowering.h:175
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:132
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::AtomicCmpXchgInst
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:522
llvm::RISCVISD::URET_FLAG
@ URET_FLAG
Definition: RISCVISelLowering.h:28
llvm::RISCVISD::VSLIDEUP_VL
@ VSLIDEUP_VL
Definition: RISCVISelLowering.h:121
llvm::RISCVISD::FSQRT_VL
@ FSQRT_VL
Definition: RISCVISelLowering.h:174
llvm::RISCVISD::UDIV_VL
@ UDIV_VL
Definition: RISCVISelLowering.h:165
llvm::RISCVISD::SRA_VL
@ SRA_VL
Definition: RISCVISelLowering.h:162
llvm::RISCVTargetLowering::shouldExpandAtomicCmpXchgInIR
TargetLowering::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Definition: RISCVISelLowering.cpp:6129
llvm::LLT
Definition: LowLevelTypeImpl.h:40