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RISCVISelLowering.h
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1 //===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that RISCV uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
15 #define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
16 
17 #include "RISCV.h"
21 
22 namespace llvm {
23 class RISCVSubtarget;
24 struct RISCVRegisterInfo;
25 namespace RISCVISD {
26 enum NodeType : unsigned {
33  /// Select with condition operator - This selects between a true value and
34  /// a false value (ops #3 and #4) based on the boolean result of comparing
35  /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
36  /// condition code in op #2, a XLenVT constant from the ISD::CondCode enum.
37  /// The lhs and rhs are XLenVT integers. The true and false values can be
38  /// integer or floating point.
44 
45  // Add the Lo 12 bits from an address. Selected to ADDI.
47  // Get the Hi 20 bits from an address. Selected to LUI.
48  HI,
49 
50  // Represents an AUIPC+ADDI pair. Selected to PseudoLLA.
51  LLA,
52 
53  // Selected as PseudoAddTPRel. Used to emit a TP-relative relocation.
55 
56  // Load address.
58 
59  // Multiply high for signedxunsigned.
61  // RV64I shifts, directly matching the semantics of the named RISC-V
62  // instructions.
66  // 32-bit operations from RV64M that can't be simply matched with a pattern
67  // at instruction selection time. These have undefined behavior for division
68  // by 0 or overflow (divw) like their target independent counterparts.
72  // RV64IB rotates, directly matching the semantics of the named RISC-V
73  // instructions.
76  // RV64IZbb bit counting instructions directly matching the semantics of the
77  // named RISC-V instructions.
80  // FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as
81  // XLEN is the only legal integer width.
82  //
83  // FMV_H_X matches the semantics of the FMV.H.X.
84  // FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result.
85  // FMV_X_SIGNEXTH is similar to FMV.X.H and has a sign-extended result.
86  // FMV_W_X_RV64 matches the semantics of the FMV.W.X.
87  // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result.
88  //
89  // This is a more convenient semantic for producing dagcombines that remove
90  // unnecessary GPR->FPR->GPR moves.
96  // FP to XLen int conversions. Corresponds to fcvt.l(u).s/d/h on RV64 and
97  // fcvt.w(u).s/d/h on RV32. Unlike FP_TO_S/UINT these saturate out of
98  // range inputs. These are used for FP_TO_S/UINT_SAT lowering. Rounding mode
99  // is passed as a TargetConstant operand using the RISCVFPRndMode enum.
102  // FP to 32 bit int conversions for RV64. These are used to keep track of the
103  // result being sign extended to 64 bit. These saturate out of range inputs.
104  // Used for FP_TO_S/UINT and FP_TO_S/UINT_SAT lowering. Rounding mode
105  // is passed as a TargetConstant operand using the RISCVFPRndMode enum.
108  // READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target
109  // (returns (Lo, Hi)). It takes a chain operand.
111  // brev8, orc.b, zip, and unzip from Zbb and Zbkb. All operands are i32 or
112  // XLenVT.
117  // Vector Extension
118  // VMV_V_X_VL matches the semantics of vmv.v.x but includes an extra operand
119  // for the VL value to be used for the operation. The first operand is
120  // passthru operand.
122  // VFMV_V_F_VL matches the semantics of vfmv.v.f but includes an extra operand
123  // for the VL value to be used for the operation. The first operand is
124  // passthru operand.
126  // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign
127  // extended from the vector element size.
129  // VMV_S_X_VL matches the semantics of vmv.s.x. It carries a VL operand.
131  // VFMV_S_F_VL matches the semantics of vfmv.s.f. It carries a VL operand.
133  // Splats an 64-bit value that has been split into two i32 parts. This is
134  // expanded late to two scalar stores and a stride 0 vector load.
135  // The first operand is passthru operand.
137  // Read VLENB CSR
139  // Truncates a RVV integer vector by one power-of-two. Carries both an extra
140  // mask and VL operand.
142  // Matches the semantics of vslideup/vslidedown. The first operand is the
143  // pass-thru operand, the second is the source vector, the third is the
144  // XLenVT index (either constant or non-constant), the fourth is the mask
145  // and the fifth the VL.
148  // Matches the semantics of vslide1up/slide1down. The first operand is
149  // passthru operand, the second is source vector, third is the XLenVT scalar
150  // value. The fourth and fifth operands are the mask and VL operands.
153  // Matches the semantics of the vid.v instruction, with a mask and VL
154  // operand.
156  // Matches the semantics of the vfcnvt.rod function (Convert double-width
157  // float to single-width float, rounding towards odd). Takes a double-width
158  // float vector and produces a single-width float vector. Also has a mask and
159  // VL operand.
161  // These nodes match the semantics of the corresponding RVV vector reduction
162  // instructions. They produce a vector result which is the reduction
163  // performed over the second vector operand plus the first element of the
164  // third vector operand. The first operand is the pass-thru operand. The
165  // second operand is an unconstrained vector type, and the result, first, and
166  // third operand's types are expected to be the corresponding full-width
167  // LMUL=1 type for the second operand:
168  // nxv8i8 = vecreduce_add nxv8i8, nxv32i8, nxv8i8
169  // nxv2i32 = vecreduce_add nxv2i32, nxv8i32, nxv2i32
170  // The different in types does introduce extra vsetvli instructions but
171  // similarly it reduces the number of registers consumed per reduction.
172  // Also has a mask and VL operand.
185 
186  // Vector binary ops with a merge as a third operand, a mask as a fourth
187  // operand, and VL as a fifth operand.
205 
210 
219 
220  // Vector unary ops with a mask as a second operand and VL as a third operand.
224  FCOPYSIGN_VL, // Has a merge operand
227  VFCVT_X_F_VL, // Has a rounding mode operand.
232 
233  // Vector FMA ops with a mask as a fourth operand and VL as a fifth operand.
238 
239  // Widening instructions with a merge value a third operand, a mask as a
240  // fourth operand, and VL as a fifth operand.
252 
254 
255  // Vector compare producing a mask. Fourth operand is input mask. Fifth
256  // operand is VL.
258 
259  // Vector select with an additional VL operand. This operation is unmasked.
261  // Vector select with operand #2 (the value when the condition is false) tied
262  // to the destination and an additional VL operand. This operation is
263  // unmasked.
265 
266  // Mask binary operators.
270 
271  // Set mask vector to all zeros or ones.
274 
275  // Matches the semantics of vrgather.vx and vrgather.vv with extra operands
276  // for passthru and VL. Operands are (src, index, mask, passthru, vl).
280 
281  // Vector sign/zero extend with additional mask & VL operands.
284 
285  // vcpop.m with additional mask and VL operands.
287 
288  // Reads value of CSR.
289  // The first operand is a chain pointer. The second specifies address of the
290  // required CSR. Two results are produced, the read value and the new chain
291  // pointer.
293  // Write value to CSR.
294  // The first operand is a chain pointer, the second specifies address of the
295  // required CSR and the third is the value to write. The result is the new
296  // chain pointer.
298  // Read and write value of CSR.
299  // The first operand is a chain pointer, the second specifies address of the
300  // required CSR and the third is the value to write. Two results are produced,
301  // the value read before the modification and the new chain pointer.
303 
304  // FP to 32 bit int conversions for RV64. These are used to keep track of the
305  // result being sign extended to 64 bit. These saturate out of range inputs.
308 
309  // WARNING: Do not add anything in the end unless you want the node to
310  // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all
311  // opcodes will be thought as target memory ops!
312 
313  // Load address.
316 };
317 } // namespace RISCVISD
318 
319 namespace RISCV {
320 // We use 64 bits as the known part in the scalable vector types.
321 static constexpr unsigned RVVBitsPerBlock = 64;
322 } // namespace RISCV
323 
325  const RISCVSubtarget &Subtarget;
326 
327 public:
328  explicit RISCVTargetLowering(const TargetMachine &TM,
329  const RISCVSubtarget &STI);
330 
331  const RISCVSubtarget &getSubtarget() const { return Subtarget; }
332 
333  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
334  MachineFunction &MF,
335  unsigned Intrinsic) const override;
336  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
337  unsigned AS,
338  Instruction *I = nullptr) const override;
339  bool isLegalICmpImmediate(int64_t Imm) const override;
340  bool isLegalAddImmediate(int64_t Imm) const override;
341  bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
342  bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
343  bool isZExtFree(SDValue Val, EVT VT2) const override;
344  bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
345  bool signExtendConstant(const ConstantInt *CI) const override;
346  bool isCheapToSpeculateCttz(Type *Ty) const override;
347  bool isCheapToSpeculateCtlz(Type *Ty) const override;
348  bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
349  bool hasAndNotCompare(SDValue Y) const override;
350  bool hasBitTest(SDValue X, SDValue Y) const override;
353  unsigned OldShiftOpcode, unsigned NewShiftOpcode,
354  SelectionDAG &DAG) const override;
356  SmallVectorImpl<Use *> &Ops) const override;
357  bool shouldScalarizeBinop(SDValue VecOp) const override;
358  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
359  bool isFPImmLegal(const APFloat &Imm, EVT VT,
360  bool ForCodeSize) const override;
361  bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
362  unsigned Index) const override;
363 
364  bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
365 
366  bool softPromoteHalfType() const override { return true; }
367 
368  /// Return the register type for a given MVT, ensuring vectors are treated
369  /// as a series of gpr sized integers.
371  EVT VT) const override;
372 
373  /// Return the number of registers for a given MVT, ensuring vectors are
374  /// treated as a series of gpr sized integers.
377  EVT VT) const override;
378 
379  /// Return true if the given shuffle mask can be codegen'd directly, or if it
380  /// should be stack expanded.
381  bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
382 
383  bool hasBitPreservingFPLogic(EVT VT) const override;
384  bool
386  unsigned DefinedValues) const override;
387 
388  // Provide custom lowering hooks for some operations.
389  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
391  SelectionDAG &DAG) const override;
392 
393  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
394 
396  const APInt &DemandedElts,
397  TargetLoweringOpt &TLO) const override;
398 
400  KnownBits &Known,
401  const APInt &DemandedElts,
402  const SelectionDAG &DAG,
403  unsigned Depth) const override;
405  const APInt &DemandedElts,
406  const SelectionDAG &DAG,
407  unsigned Depth) const override;
408 
409  const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const override;
410 
411  // This method returns the name of a target specific DAG node.
412  const char *getTargetNodeName(unsigned Opcode) const override;
413 
414  ConstraintType getConstraintType(StringRef Constraint) const override;
415 
416  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
417 
418  std::pair<unsigned, const TargetRegisterClass *>
420  StringRef Constraint, MVT VT) const override;
421 
422  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
423  std::vector<SDValue> &Ops,
424  SelectionDAG &DAG) const override;
425 
428  MachineBasicBlock *BB) const override;
429 
431  SDNode *Node) const override;
432 
434  EVT VT) const override;
435 
436  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
437  return VT.isScalarInteger();
438  }
439  bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
440 
441  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
442  return isa<LoadInst>(I) || isa<StoreInst>(I);
443  }
445  AtomicOrdering Ord) const override;
447  AtomicOrdering Ord) const override;
448 
450  EVT VT) const override;
451 
453  return ISD::SIGN_EXTEND;
454  }
455 
457  return ISD::SIGN_EXTEND;
458  }
459 
460  bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override {
462  return false;
463  return true;
464  }
466  CombineLevel Level) const override;
467 
468  /// If a physical register, this returns the register that receives the
469  /// exception address on entry to an EH pad.
470  Register
471  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
472 
473  /// If a physical register, this returns the register that receives the
474  /// exception typeid on entry to a landing pad.
475  Register
476  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
477 
478  bool shouldExtendTypeInLibCall(EVT Type) const override;
479  bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
480 
481  /// Returns the register with the specified architectural or ABI name. This
482  /// method is necessary to lower the llvm.read_register.* and
483  /// llvm.write_register.* intrinsics. Allocatable registers must be reserved
484  /// with the clang -ffixed-xX flag for access to be allowed.
485  Register getRegisterByName(const char *RegName, LLT VT,
486  const MachineFunction &MF) const override;
487 
488  // Lower incoming arguments, copy physregs into vregs
490  bool IsVarArg,
492  const SDLoc &DL, SelectionDAG &DAG,
493  SmallVectorImpl<SDValue> &InVals) const override;
495  bool IsVarArg,
497  LLVMContext &Context) const override;
498  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
500  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
501  SelectionDAG &DAG) const override;
503  SmallVectorImpl<SDValue> &InVals) const override;
504 
506  Type *Ty) const override;
507  bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
508  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
509  bool shouldConsiderGEPOffsetSplit() const override { return true; }
510 
512  SDValue C) const override;
513 
515  SDValue ConstNode) const override;
516 
518  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
520  Value *AlignedAddr, Value *Incr,
521  Value *Mask, Value *ShiftAmt,
522  AtomicOrdering Ord) const override;
526  AtomicCmpXchgInst *CI,
527  Value *AlignedAddr, Value *CmpVal,
528  Value *NewVal, Value *Mask,
529  AtomicOrdering Ord) const override;
530 
531  /// Returns true if the target allows unaligned memory accesses of the
532  /// specified type.
534  EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),
536  bool *Fast = nullptr) const override;
537 
539  SDValue Val, SDValue *Parts,
540  unsigned NumParts, MVT PartVT,
541  Optional<CallingConv::ID> CC) const override;
542 
543  SDValue
545  const SDValue *Parts, unsigned NumParts,
546  MVT PartVT, EVT ValueVT,
547  Optional<CallingConv::ID> CC) const override;
548 
549  static RISCVII::VLMUL getLMUL(MVT VT);
550  inline static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize,
551  unsigned MinSize) {
552  // Original equation:
553  // VLMAX = (VectorBits / EltSize) * LMUL
554  // where LMUL = MinSize / RISCV::RVVBitsPerBlock
555  // The following equations have been reordered to prevent loss of precision
556  // when calculating fractional LMUL.
557  return ((VectorBits / EltSize) * MinSize) / RISCV::RVVBitsPerBlock;
558  };
559  static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul);
560  static unsigned getSubregIndexByMVT(MVT VT, unsigned Index);
561  static unsigned getRegClassIDForVecVT(MVT VT);
562  static std::pair<unsigned, unsigned>
564  unsigned InsertExtractIdx,
565  const RISCVRegisterInfo *TRI);
567 
568  bool shouldRemoveExtendFromGSIndex(EVT IndexVT, EVT DataVT) const override;
569 
570  bool isLegalElementTypeForRVV(Type *ScalarTy) const;
571 
572  bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
573 
574  unsigned getJumpTableEncoding() const override;
575 
577  const MachineBasicBlock *MBB,
578  unsigned uid,
579  MCContext &Ctx) const override;
580 
581  bool isVScaleKnownToBeAPowerOfTwo() const override;
582 
584  uint64_t ElemSize) const override {
585  // Scaled addressing not supported on indexed load/stores
586  return Scale == 1;
587  }
588 
589 private:
590  /// RISCVCCAssignFn - This target-specific function extends the default
591  /// CCValAssign with additional information used to lower RISC-V calling
592  /// conventions.
593  typedef bool RISCVCCAssignFn(const DataLayout &DL, RISCVABI::ABI,
594  unsigned ValNo, MVT ValVT, MVT LocVT,
595  CCValAssign::LocInfo LocInfo,
596  ISD::ArgFlagsTy ArgFlags, CCState &State,
597  bool IsFixed, bool IsRet, Type *OrigTy,
598  const RISCVTargetLowering &TLI,
599  Optional<unsigned> FirstMaskArgument);
600 
601  void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
602  const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
603  RISCVCCAssignFn Fn) const;
604  void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
606  bool IsRet, CallLoweringInfo *CLI,
607  RISCVCCAssignFn Fn) const;
608 
609  template <class NodeTy>
610  SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const;
611  SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
612  bool UseGOT) const;
613  SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
614 
615  SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
616  SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
617  SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
618  SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
619  SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
620  SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
621  SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
622  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
623  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
624  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
625  SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
626  SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
627  SDValue lowerSPLAT_VECTOR_PARTS(SDValue Op, SelectionDAG &DAG) const;
628  SDValue lowerVectorMaskSplat(SDValue Op, SelectionDAG &DAG) const;
629  SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
630  int64_t ExtTrueVal) const;
631  SDValue lowerVectorMaskTruncLike(SDValue Op, SelectionDAG &DAG) const;
632  SDValue lowerVectorTruncLike(SDValue Op, SelectionDAG &DAG) const;
633  SDValue lowerVectorFPExtendOrRoundLike(SDValue Op, SelectionDAG &DAG) const;
634  SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
635  SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
636  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
637  SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
638  SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
639  SDValue lowerVPREDUCE(SDValue Op, SelectionDAG &DAG) const;
640  SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
641  SDValue lowerVectorMaskVecReduction(SDValue Op, SelectionDAG &DAG,
642  bool IsVP) const;
643  SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
644  SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
645  SDValue lowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
646  SDValue lowerSTEP_VECTOR(SDValue Op, SelectionDAG &DAG) const;
647  SDValue lowerVECTOR_REVERSE(SDValue Op, SelectionDAG &DAG) const;
648  SDValue lowerVECTOR_SPLICE(SDValue Op, SelectionDAG &DAG) const;
649  SDValue lowerABS(SDValue Op, SelectionDAG &DAG) const;
650  SDValue lowerMaskedLoad(SDValue Op, SelectionDAG &DAG) const;
651  SDValue lowerMaskedStore(SDValue Op, SelectionDAG &DAG) const;
652  SDValue lowerFixedLengthVectorFCOPYSIGNToRVV(SDValue Op,
653  SelectionDAG &DAG) const;
654  SDValue lowerMaskedGather(SDValue Op, SelectionDAG &DAG) const;
655  SDValue lowerMaskedScatter(SDValue Op, SelectionDAG &DAG) const;
656  SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const;
657  SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const;
658  SDValue lowerFixedLengthVectorSetccToRVV(SDValue Op, SelectionDAG &DAG) const;
659  SDValue lowerFixedLengthVectorLogicOpToRVV(SDValue Op, SelectionDAG &DAG,
660  unsigned MaskOpc,
661  unsigned VecOpc) const;
662  SDValue lowerFixedLengthVectorShiftToRVV(SDValue Op, SelectionDAG &DAG) const;
663  SDValue lowerFixedLengthVectorSelectToRVV(SDValue Op,
664  SelectionDAG &DAG) const;
665  SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG, unsigned NewOpc,
666  bool HasMergeOp = false, bool HasMask = true) const;
667  SDValue lowerVPOp(SDValue Op, SelectionDAG &DAG, unsigned RISCVISDOpc,
668  bool HasMergeOp = false) const;
669  SDValue lowerLogicVPOp(SDValue Op, SelectionDAG &DAG, unsigned MaskOpc,
670  unsigned VecOpc) const;
671  SDValue lowerVPExtMaskOp(SDValue Op, SelectionDAG &DAG) const;
672  SDValue lowerVPSetCCMaskOp(SDValue Op, SelectionDAG &DAG) const;
673  SDValue lowerVPFPIntConvOp(SDValue Op, SelectionDAG &DAG,
674  unsigned RISCVISDOpc) const;
675  SDValue lowerVPStridedLoad(SDValue Op, SelectionDAG &DAG) const;
676  SDValue lowerVPStridedStore(SDValue Op, SelectionDAG &DAG) const;
677  SDValue lowerFixedLengthVectorExtendToRVV(SDValue Op, SelectionDAG &DAG,
678  unsigned ExtendOpc) const;
679  SDValue lowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
680  SDValue lowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
681 
682  SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
683 
684  SDValue expandUnalignedRVVLoad(SDValue Op, SelectionDAG &DAG) const;
685  SDValue expandUnalignedRVVStore(SDValue Op, SelectionDAG &DAG) const;
686 
687  bool isEligibleForTailCallOptimization(
688  CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
689  const SmallVector<CCValAssign, 16> &ArgLocs) const;
690 
691  /// Generate error diagnostics if any register used by CC has been marked
692  /// reserved.
693  void validateCCReservedRegs(
694  const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs,
695  MachineFunction &MF) const;
696 
697  bool useRVVForFixedLengthVectorVT(MVT VT) const;
698 
699  MVT getVPExplicitVectorLengthTy() const override;
700 
701  /// RVV code generation for fixed length vectors does not lower all
702  /// BUILD_VECTORs. This makes BUILD_VECTOR legalisation a source of stores to
703  /// merge. However, merging them creates a BUILD_VECTOR that is just as
704  /// illegal as the original, thus leading to an infinite legalisation loop.
705  /// NOTE: Once BUILD_VECTOR can be custom lowered for all legal vector types,
706  /// this override can be removed.
707  bool mergeStoresAfterLegalization(EVT VT) const override;
708 
709  /// Disable normalizing
710  /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
711  /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y))
712  /// RISCV doesn't have flags so it's better to perform the and/or in a GPR.
713  bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override {
714  return false;
715  };
716 };
717 namespace RISCVVIntrinsicsTable {
718 
720  unsigned IntrinsicID;
721  uint8_t ScalarOperand;
722  uint8_t VLOperand;
723  bool hasScalarOperand() const {
724  // 0xF is not valid. See NoScalarOperand in IntrinsicsRISCV.td.
725  return ScalarOperand != 0xF;
726  }
727  bool hasVLOperand() const {
728  // 0x1F is not valid. See NoVLOperand in IntrinsicsRISCV.td.
729  return VLOperand != 0x1F;
730  }
731 };
732 
733 using namespace RISCV;
734 
735 #define GET_RISCVVIntrinsicsTable_DECL
736 #include "RISCVGenSearchableTables.inc"
737 
738 } // end namespace RISCVVIntrinsicsTable
739 
740 } // end namespace llvm
741 
742 #endif
llvm::RISCVTargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: RISCVISelLowering.cpp:12350
llvm::RISCVISD::SUB_VL
@ SUB_VL
Definition: RISCVISelLowering.h:197
llvm::RISCVISD::READ_CYCLE_WIDE
@ READ_CYCLE_WIDE
Definition: RISCVISelLowering.h:110
llvm::RISCVISD::AND_VL
@ AND_VL
Definition: RISCVISelLowering.h:189
llvm::RISCVISD::VFMV_S_F_VL
@ VFMV_S_F_VL
Definition: RISCVISelLowering.h:132
llvm::RISCVISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: RISCVISelLowering.h:27
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1581
llvm::RISCVISD::VFMSUB_VL
@ VFMSUB_VL
Definition: RISCVISelLowering.h:236
llvm::RISCVISD::VECREDUCE_FMAX_VL
@ VECREDUCE_FMAX_VL
Definition: RISCVISelLowering.h:184
llvm::RISCVISD::VWSUBU_W_VL
@ VWSUBU_W_VL
Definition: RISCVISelLowering.h:251
llvm::RISCVISD::SMAX_VL
@ SMAX_VL
Definition: RISCVISelLowering.h:202
llvm::RISCVISD::LLA
@ LLA
Definition: RISCVISelLowering.h:51
llvm::RISCVISD::SINT_TO_FP_VL
@ SINT_TO_FP_VL
Definition: RISCVISelLowering.h:228
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::RISCVISD::SLLW
@ SLLW
Definition: RISCVISelLowering.h:63
llvm::RISCVTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: RISCVISelLowering.cpp:10213
llvm::RISCVTargetLowering::isSExtCheaperThanZExt
bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
Definition: RISCVISelLowering.cpp:1142
llvm::EVT::isScalarInteger
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:149
llvm::RISCVISD::SWAP_CSR
@ SWAP_CSR
Definition: RISCVISelLowering.h:302
llvm::RISCVISD::VWADD_W_VL
@ VWADD_W_VL
Definition: RISCVISelLowering.h:248
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1103
llvm::RISCVISD::FMAXNUM_VL
@ FMAXNUM_VL
Definition: RISCVISelLowering.h:218
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::RISCVTargetLowering::signExtendConstant
bool signExtendConstant(const ConstantInt *CI) const override
Return true if this constant should be sign extended when promoting to a larger type.
Definition: RISCVISelLowering.cpp:1146
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4495
llvm::RISCVTargetLowering::hasBitTest
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
Definition: RISCVISelLowering.cpp:1185
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:189
llvm::RISCVISD::VWSUB_VL
@ VWSUB_VL
Definition: RISCVISelLowering.h:246
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::RISCVISD::FMINNUM_VL
@ FMINNUM_VL
Definition: RISCVISelLowering.h:217
llvm::RISCVTargetLowering::RISCVTargetLowering
RISCVTargetLowering(const TargetMachine &TM, const RISCVSubtarget &STI)
Definition: RISCVISelLowering.cpp:48
llvm::RISCVISD::FMV_H_X
@ FMV_H_X
Definition: RISCVISelLowering.h:91
llvm::RISCVTargetLowering::isVScaleKnownToBeAPowerOfTwo
bool isVScaleKnownToBeAPowerOfTwo() const override
Return true only if vscale must be a power of two.
Definition: RISCVISelLowering.cpp:12317
llvm::ARM_MB::LD
@ LD
Definition: ARMBaseInfo.h:72
llvm::RISCVRegisterInfo
Definition: RISCVRegisterInfo.h:23
llvm::RISCVTargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd
bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const override
Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>>...
Definition: RISCVISelLowering.cpp:1226
llvm::RISCVISD::DIVUW
@ DIVUW
Definition: RISCVISelLowering.h:70
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1181
llvm::RISCVISD::LA_TLS_IE
@ LA_TLS_IE
Definition: RISCVISelLowering.h:315
llvm::RISCVISD::VRGATHER_VX_VL
@ VRGATHER_VX_VL
Definition: RISCVISelLowering.h:277
llvm::RISCVISD::VECREDUCE_UMIN_VL
@ VECREDUCE_UMIN_VL
Definition: RISCVISelLowering.h:176
llvm::RISCVTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: RISCVISelLowering.cpp:11852
llvm::RISCVISD::VFCVT_RTZ_XU_F_VL
@ VFCVT_RTZ_XU_F_VL
Definition: RISCVISelLowering.h:226
llvm::RISCVISD::VMAND_VL
@ VMAND_VL
Definition: RISCVISelLowering.h:267
llvm::RISCVISD::SDIV_VL
@ SDIV_VL
Definition: RISCVISelLowering.h:192
llvm::RISCVTargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
Definition: RISCVISelLowering.cpp:9537
llvm::RISCVISD::MULHU_VL
@ MULHU_VL
Definition: RISCVISelLowering.h:212
llvm::RISCVISD::VZEXT_VL
@ VZEXT_VL
Definition: RISCVISelLowering.h:283
llvm::RISCVTargetLowering::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
Definition: RISCVISelLowering.cpp:1000
llvm::RISCVISD::VNSRL_VL
@ VNSRL_VL
Definition: RISCVISelLowering.h:253
llvm::RISCVISD::VFCVT_RTZ_X_F_VL
@ VFCVT_RTZ_X_F_VL
Definition: RISCVISelLowering.h:225
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:462
llvm::RISCVTargetLowering::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const override
Returns true if the target allows unaligned memory accesses of the specified type.
Definition: RISCVISelLowering.cpp:12439
llvm::RISCVISD::STRICT_FCVT_W_RV64
@ STRICT_FCVT_W_RV64
Definition: RISCVISelLowering.h:306
llvm::LoadSDNode
This class is used to represent ISD::LOAD nodes.
Definition: SelectionDAGNodes.h:2342
llvm::RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic
Value * emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override
Perform a masked atomicrmw using a target-specific intrinsic.
Definition: RISCVISelLowering.cpp:12199
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::RISCVISD::VECREDUCE_FMIN_VL
@ VECREDUCE_FMIN_VL
Definition: RISCVISelLowering.h:183
llvm::RISCVISD::MUL_VL
@ MUL_VL
Definition: RISCVISelLowering.h:190
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::AttributeList
Definition: Attributes.h:425
llvm::RISCVTargetLowering::getExtendForAtomicCmpSwapArg
ISD::NodeType getExtendForAtomicCmpSwapArg() const override
Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_...
Definition: RISCVISelLowering.h:456
llvm::RISCVISD::SHL_VL
@ SHL_VL
Definition: RISCVISelLowering.h:193
llvm::RISCVISD::ADD_VL
@ ADD_VL
Definition: RISCVISelLowering.h:188
llvm::Optional< CallingConv::ID >
llvm::RISCVTargetLowering::isIntDivCheap
bool isIntDivCheap(EVT VT, AttributeList Attr) const override
Return true if integer divide is usually cheaper than a sequence of several shifts,...
Definition: RISCVISelLowering.cpp:12558
llvm::RISCVISD::VMXOR_VL
@ VMXOR_VL
Definition: RISCVISelLowering.h:269
llvm::RISCVTargetLowering::emitLeadingFence
Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
Definition: RISCVISelLowering.cpp:12112
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:830
llvm::RISCVTargetLowering::emitTrailingFence
Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Definition: RISCVISelLowering.cpp:12122
llvm::RISCVTargetLowering::shouldExpandAtomicRMWInIR
TargetLowering::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition: RISCVISelLowering.cpp:12131
llvm::RISCVISD::VECREDUCE_OR_VL
@ VECREDUCE_OR_VL
Definition: RISCVISelLowering.h:179
llvm::RISCVTargetLowering::getRegClassIDForVecVT
static unsigned getRegClassIDForVecVT(MVT VT)
Definition: RISCVISelLowering.cpp:1580
llvm::RISCVTargetLowering::splitValueIntoRegisterParts
bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, Optional< CallingConv::ID > CC) const override
Target-specific splitting of values into parts that fit a register storing a legal type.
Definition: RISCVISelLowering.cpp:12459
llvm::RISCVTargetLowering::LowerFormalArguments
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition: RISCVISelLowering.cpp:10963
SelectionDAG.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::RISCVISD::VFMADD_VL
@ VFMADD_VL
Definition: RISCVISelLowering.h:234
llvm::RISCVTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: RISCVISelLowering.cpp:11668
llvm::RISCVISD::VID_VL
@ VID_VL
Definition: RISCVISelLowering.h:155
llvm::RISCVTargetLowering::computeVLMAX
static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize, unsigned MinSize)
Definition: RISCVISelLowering.h:550
llvm::RISCVISD::ZIP
@ ZIP
Definition: RISCVISelLowering.h:115
llvm::RISCVTargetLowering::isUsedByReturnOnly
bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override
Return true if result of the specified node is used by a return node only.
Definition: RISCVISelLowering.cpp:11632
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::RISCVTargetLowering::targetShrinkDemandedConstant
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override
Definition: RISCVISelLowering.cpp:9432
llvm::RISCVISD::VWMUL_VL
@ VWMUL_VL
Definition: RISCVISelLowering.h:241
llvm::RISCVISD::VSEXT_VL
@ VSEXT_VL
Definition: RISCVISelLowering.h:282
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TargetLowering.h
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::RISCVISD::FMV_X_ANYEXTH
@ FMV_X_ANYEXTH
Definition: RISCVISelLowering.h:92
llvm::RISCVTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: RISCVISelLowering.cpp:8844
llvm::RISCVTargetLowering::isLegalElementTypeForRVV
bool isLegalElementTypeForRVV(Type *ScalarTy) const
Definition: RISCVISelLowering.cpp:1629
llvm::RISCVISD::SMIN_VL
@ SMIN_VL
Definition: RISCVISelLowering.h:201
llvm::RISCVTargetLowering::shouldSignExtendTypeInLibCall
bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override
Returns true if arguments should be sign-extended in lib calls.
Definition: RISCVISelLowering.cpp:12370
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::RISCVTargetLowering::hasBitPreservingFPLogic
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Definition: RISCVISelLowering.cpp:1423
llvm::RISCVISD::VCPOP_VL
@ VCPOP_VL
Definition: RISCVISelLowering.h:286
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::IntrinsicID
unsigned IntrinsicID
Definition: RISCVISelLowering.h:720
llvm::RISCVISD::CALL
@ CALL
Definition: RISCVISelLowering.h:32
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3446
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::RISCVISD::VMCLR_VL
@ VMCLR_VL
Definition: RISCVISelLowering.h:272
llvm::RISCVTargetLowering::getSubregIndexByMVT
static unsigned getSubregIndexByMVT(MVT VT, unsigned Index)
Definition: RISCVISelLowering.cpp:1557
llvm::RISCVISD::VWSUBU_VL
@ VWSUBU_VL
Definition: RISCVISelLowering.h:247
llvm::RISCVISD::FADD_VL
@ FADD_VL
Definition: RISCVISelLowering.h:213
llvm::RISCVISD::MULHS_VL
@ MULHS_VL
Definition: RISCVISelLowering.h:211
llvm::RISCVTargetLowering::joinRegisterPartsIntoValue
SDValue joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, Optional< CallingConv::ID > CC) const override
Target-specific combining of register parts into its original value.
Definition: RISCVISelLowering.cpp:12513
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::RISCVTargetLowering::LowerCall
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Definition: RISCVISelLowering.cpp:11198
llvm::RISCVTargetLowering::isCheapToSpeculateCttz
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
Definition: RISCVISelLowering.cpp:1150
llvm::Instruction
Definition: Instruction.h:42
llvm::RISCVTargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: RISCVISelLowering.cpp:12355
llvm::RISCVISD::HI
@ HI
Definition: RISCVISelLowering.h:48
llvm::RISCVTargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: RISCVISelLowering.cpp:1369
llvm::RISCVTargetLowering::convertSelectOfConstantsToMath
bool convertSelectOfConstantsToMath(EVT VT) const override
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...
Definition: RISCVISelLowering.h:439
llvm::RISCVISD::FMV_W_X_RV64
@ FMV_W_X_RV64
Definition: RISCVISelLowering.h:94
llvm::RISCVISD::LA_TLS_GD
@ LA_TLS_GD
Definition: RISCVISelLowering.h:57
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::RISCVISD::VSELECT_VL
@ VSELECT_VL
Definition: RISCVISelLowering.h:260
llvm::RISCVISD::UMIN_VL
@ UMIN_VL
Definition: RISCVISelLowering.h:203
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::RISCVISD::VFNMADD_VL
@ VFNMADD_VL
Definition: RISCVISelLowering.h:235
llvm::RISCVISD::VFNMSUB_VL
@ VFNMSUB_VL
Definition: RISCVISelLowering.h:237
llvm::RISCVTargetLowering::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
Definition: RISCVISelLowering.cpp:1099
llvm::RISCVISD::SRL_VL
@ SRL_VL
Definition: RISCVISelLowering.h:196
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::RISCVTargetLowering::decomposeMulByConstant
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
Definition: RISCVISelLowering.cpp:12377
llvm::RISCVISD::DIVW
@ DIVW
Definition: RISCVISelLowering.h:69
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::hasVLOperand
bool hasVLOperand() const
Definition: RISCVISelLowering.h:727
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::RISCVTargetLowering::shouldExpandShift
bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
Definition: RISCVISelLowering.h:460
llvm::RISCVTargetLowering::shouldRemoveExtendFromGSIndex
bool shouldRemoveExtendFromGSIndex(EVT IndexVT, EVT DataVT) const override
Definition: RISCVISelLowering.cpp:12277
llvm::RISCVISD::CLZW
@ CLZW
Definition: RISCVISelLowering.h:78
llvm::RISCVTargetLowering::isMulAddWithConstProfitable
bool isMulAddWithConstProfitable(SDValue AddNode, SDValue ConstNode) const override
Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x,...
Definition: RISCVISelLowering.cpp:12416
llvm::RISCVISD::VFNCVT_ROD_VL
@ VFNCVT_ROD_VL
Definition: RISCVISelLowering.h:160
llvm::RISCVISD::FABS_VL
@ FABS_VL
Definition: RISCVISelLowering.h:222
llvm::RISCVTargetLowering::isMaskAndCmp0FoldingBeneficial
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
Definition: RISCVISelLowering.cpp:1158
llvm::RISCVISD::FNEG_VL
@ FNEG_VL
Definition: RISCVISelLowering.h:221
llvm::RISCVISD::SplitF64
@ SplitF64
Definition: RISCVISelLowering.h:42
llvm::RISCVISD::SREM_VL
@ SREM_VL
Definition: RISCVISelLowering.h:194
llvm::RISCV::RVVBitsPerBlock
static constexpr unsigned RVVBitsPerBlock
Definition: RISCVISelLowering.h:321
llvm::RISCVISD::UINT_TO_FP_VL
@ UINT_TO_FP_VL
Definition: RISCVISelLowering.h:229
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::RISCVISD::SELECT_CC
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #3 and #4) ...
Definition: RISCVISelLowering.h:39
llvm::APFloat
Definition: APFloat.h:701
llvm::CCValAssign::LocInfo
LocInfo
Definition: CallingConvLower.h:33
llvm::RISCVTargetLowering::convertSetCCLogicToBitwiseLogic
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
Definition: RISCVISelLowering.h:436
llvm::RISCVISD::VMV_S_X_VL
@ VMV_S_X_VL
Definition: RISCVISelLowering.h:130
llvm::RISCVISD::FMV_X_ANYEXTW_RV64
@ FMV_X_ANYEXTW_RV64
Definition: RISCVISelLowering.h:95
llvm::RISCVTargetLowering::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: RISCVISelLowering.cpp:1095
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::RISCVTargetLowering::isExtractSubvectorCheap
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
Definition: RISCVISelLowering.cpp:1391
llvm::RISCVISD::VECREDUCE_XOR_VL
@ VECREDUCE_XOR_VL
Definition: RISCVISelLowering.h:180
llvm::RISCVISD::VFCVT_X_F_VL
@ VFCVT_X_F_VL
Definition: RISCVISelLowering.h:227
llvm::RISCVISD::VWSUB_W_VL
@ VWSUB_W_VL
Definition: RISCVISelLowering.h:250
llvm::RISCVTargetLowering::hasAndNotCompare
bool hasAndNotCompare(SDValue Y) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) !...
Definition: RISCVISelLowering.cpp:1174
llvm::RISCVISD::UNZIP
@ UNZIP
Definition: RISCVISelLowering.h:116
llvm::RISCVISD::SETCC_VL
@ SETCC_VL
Definition: RISCVISelLowering.h:257
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::ISD::FIRST_TARGET_STRICTFP_OPCODE
static const int FIRST_TARGET_STRICTFP_OPCODE
FIRST_TARGET_STRICTFP_OPCODE - Target-specific pre-isel operations which cannot raise FP exceptions s...
Definition: ISDOpcodes.h:1313
llvm::RISCVISD::MULHSU
@ MULHSU
Definition: RISCVISelLowering.h:60
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::RISCVISD::VSLIDEDOWN_VL
@ VSLIDEDOWN_VL
Definition: RISCVISelLowering.h:147
llvm::DemandedBits
Definition: DemandedBits.h:40
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::RISCVISD::MRET_FLAG
@ MRET_FLAG
Definition: RISCVISelLowering.h:31
llvm::RISCVISD::XOR_VL
@ XOR_VL
Definition: RISCVISelLowering.h:200
llvm::RISCVTargetLowering::AdjustInstrPostInstrSelection
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
Definition: RISCVISelLowering.cpp:10258
llvm::SystemZISD::XC
@ XC
Definition: SystemZISelLowering.h:123
llvm::RISCVISD::ROLW
@ ROLW
Definition: RISCVISelLowering.h:74
llvm::RISCVTargetLowering::isTruncateFree
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
Definition: RISCVISelLowering.cpp:1108
llvm::RISCVTargetLowering::shouldConsiderGEPOffsetSplit
bool shouldConsiderGEPOffsetSplit() const override
Definition: RISCVISelLowering.h:509
llvm::RISCVISD::VECREDUCE_SMAX_VL
@ VECREDUCE_SMAX_VL
Definition: RISCVISelLowering.h:175
llvm::RISCVTargetLowering::getInlineAsmMemConstraint
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override
Definition: RISCVISelLowering.cpp:12051
llvm::RISCVTargetLowering::ComputeNumSignBitsForTargetNode
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
This method can be implemented by targets that want to expose additional information about sign bits ...
Definition: RISCVISelLowering.cpp:9646
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::RISCVISD::ADD_LO
@ ADD_LO
Definition: RISCVISelLowering.h:46
llvm::RISCVISD::WRITE_CSR
@ WRITE_CSR
Definition: RISCVISelLowering.h:297
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:4079
llvm::RISCVTargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: RISCVISelLowering.cpp:1065
llvm::RISCVTargetLowering::isZExtFree
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
Definition: RISCVISelLowering.cpp:1127
llvm::RISCVISD::OR_VL
@ OR_VL
Definition: RISCVISelLowering.h:191
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::RISCVISD::VECREDUCE_SEQ_FADD_VL
@ VECREDUCE_SEQ_FADD_VL
Definition: RISCVISelLowering.h:182
llvm::RISCVISD::BREV8
@ BREV8
Definition: RISCVISelLowering.h:113
llvm::RISCVISD::SADDSAT_VL
@ SADDSAT_VL
Definition: RISCVISelLowering.h:206
llvm::RISCVTargetLowering::isDesirableToCommuteWithShift
bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override
Return true if it is profitable to move this shift by a constant amount through its operand,...
Definition: RISCVISelLowering.cpp:9380
llvm::RISCVISD::VECREDUCE_SMIN_VL
@ VECREDUCE_SMIN_VL
Definition: RISCVISelLowering.h:177
llvm::RISCVISD::VSLIDE1UP_VL
@ VSLIDE1UP_VL
Definition: RISCVISelLowering.h:151
llvm::RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic
Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const override
Perform a masked cmpxchg using a target-specific intrinsic.
Definition: RISCVISelLowering.cpp:12255
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::RISCVTargetLowering::softPromoteHalfType
bool softPromoteHalfType() const override
Definition: RISCVISelLowering.h:366
llvm::RISCVISD::SRAW
@ SRAW
Definition: RISCVISelLowering.h:64
llvm::RISCVTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Definition: RISCVISelLowering.cpp:7170
llvm::RISCVISD::READ_VLENB
@ READ_VLENB
Definition: RISCVISelLowering.h:138
llvm::RISCVISD::ORC_B
@ ORC_B
Definition: RISCVISelLowering.h:114
llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Definition: RISCVISelLowering.cpp:12329
llvm::RISCVISD::VMOR_VL
@ VMOR_VL
Definition: RISCVISelLowering.h:268
RISCV.h
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:651
llvm::RISCVISD::BuildPairF64
@ BuildPairF64
Definition: RISCVISelLowering.h:41
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::RISCVTargetLowering::getSubtarget
const RISCVSubtarget & getSubtarget() const
Definition: RISCVISelLowering.h:331
llvm::SystemZ::VectorBits
const unsigned VectorBits
Definition: SystemZ.h:154
llvm::RISCVISD::FSUB_VL
@ FSUB_VL
Definition: RISCVISelLowering.h:214
llvm::RISCVISD::USUBSAT_VL
@ USUBSAT_VL
Definition: RISCVISelLowering.h:209
llvm::RISCVISD::FCVT_XU
@ FCVT_XU
Definition: RISCVISelLowering.h:101
llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs
static std::pair< unsigned, unsigned > decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT, unsigned InsertExtractIdx, const RISCVRegisterInfo *TRI)
Definition: RISCVISelLowering.cpp:1592
llvm::RISCVISD::REMUW
@ REMUW
Definition: RISCVISelLowering.h:71
llvm::ArrayRef< int >
llvm::RISCVISD::VECREDUCE_AND_VL
@ VECREDUCE_AND_VL
Definition: RISCVISelLowering.h:178
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::RISCVISD::STRICT_FCVT_WU_RV64
@ STRICT_FCVT_WU_RV64
Definition: RISCVISelLowering.h:307
llvm::RISCVTargetLowering::isLegalScaleForGatherScatter
bool isLegalScaleForGatherScatter(uint64_t Scale, uint64_t ElemSize) const override
Definition: RISCVISelLowering.h:583
llvm::RISCVISD::VMV_V_X_VL
@ VMV_V_X_VL
Definition: RISCVISelLowering.h:121
llvm::RISCVTargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
Definition: RISCVISelLowering.cpp:11828
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::ScalarOperand
uint8_t ScalarOperand
Definition: RISCVISelLowering.h:721
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
llvm::IRBuilderBase
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:93
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::RISCVISD::FP_EXTEND_VL
@ FP_EXTEND_VL
Definition: RISCVISelLowering.h:231
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::RISCVTargetLowering::LowerCustomJumpTableEntry
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override
Definition: RISCVISelLowering.cpp:12309
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::RISCVISD::FCVT_X
@ FCVT_X
Definition: RISCVISelLowering.h:100
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1307
llvm::RISCVISD::VWADD_VL
@ VWADD_VL
Definition: RISCVISelLowering.h:244
llvm::RISCVISD::VWADDU_VL
@ VWADDU_VL
Definition: RISCVISelLowering.h:245
Node
Definition: ItaniumDemangle.h:155
llvm::RISCVISD::FCVT_WU_RV64
@ FCVT_WU_RV64
Definition: RISCVISelLowering.h:107
llvm::RISCVTargetLowering::shouldConvertConstantLoadToIntImm
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Return true if it is beneficial to convert a load of a constant to just the constant itself.
Definition: RISCVISelLowering.cpp:1194
llvm::RISCVISD::BR_CC
@ BR_CC
Definition: RISCVISelLowering.h:40
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:715
llvm::RISCVISD::LA
@ LA
Definition: RISCVISelLowering.h:314
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::RISCVISD::FMUL_VL
@ FMUL_VL
Definition: RISCVISelLowering.h:215
llvm::RISCVISD::RORW
@ RORW
Definition: RISCVISelLowering.h:75
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::RISCVTargetLowering::getRegClassIDForLMUL
static unsigned getRegClassIDForLMUL(RISCVII::VLMUL LMul)
Definition: RISCVISelLowering.cpp:1539
llvm::RISCVISD::VWMULU_VL
@ VWMULU_VL
Definition: RISCVISelLowering.h:242
llvm::RISCVISD::VECREDUCE_UMAX_VL
@ VECREDUCE_UMAX_VL
Definition: RISCVISelLowering.h:174
llvm::RISCVTargetLowering::isFPImmLegal
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
Definition: RISCVISelLowering.cpp:1378
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1757
llvm::KnownBits
Definition: KnownBits.h:23
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:622
llvm::RISCVISD::VMSET_VL
@ VMSET_VL
Definition: RISCVISelLowering.h:273
llvm::RISCVISD::SRLW
@ SRLW
Definition: RISCVISelLowering.h:65
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:248
CallingConvLower.h
llvm::RISCVISD::ADD_TPREL
@ ADD_TPREL
Definition: RISCVISelLowering.h:54
llvm::RISCVISD::FMV_X_SIGNEXTH
@ FMV_X_SIGNEXTH
Definition: RISCVISelLowering.h:93
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::VLOperand
uint8_t VLOperand
Definition: RISCVISelLowering.h:722
llvm::RISCVTargetLowering::CanLowerReturn
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition: RISCVISelLowering.cpp:11495
llvm::RISCVISD::RET_FLAG
@ RET_FLAG
Definition: RISCVISelLowering.h:28
llvm::RISCVISD::FP_ROUND_VL
@ FP_ROUND_VL
Definition: RISCVISelLowering.h:230
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo::hasScalarOperand
bool hasScalarOperand() const
Definition: RISCVISelLowering.h:723
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:145
llvm::RISCVISD::VRGATHER_VV_VL
@ VRGATHER_VV_VL
Definition: RISCVISelLowering.h:278
llvm::RISCVTargetLowering::getTargetConstantFromLoad
const Constant * getTargetConstantFromLoad(LoadSDNode *LD) const override
This method returns the constant pool value that will be loaded by LD.
Definition: RISCVISelLowering.cpp:9719
llvm::RISCVTargetLowering
Definition: RISCVISelLowering.h:324
llvm::RISCVTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: RISCVISelLowering.cpp:3359
llvm::RISCVISD::VMV_X_S
@ VMV_X_S
Definition: RISCVISelLowering.h:128
llvm::RISCVISD::VP_MERGE_VL
@ VP_MERGE_VL
Definition: RISCVISelLowering.h:264
llvm::RISCVTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
Definition: RISCVISelLowering.cpp:12065
llvm::RISCVTargetLowering::getLMUL
static RISCVII::VLMUL getLMUL(MVT VT)
Definition: RISCVISelLowering.cpp:1513
llvm::RISCVTargetLowering::shouldConvertFpToSat
bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override
Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) satur...
Definition: RISCVISelLowering.cpp:12282
llvm::RISCVTargetLowering::shouldScalarizeBinop
bool shouldScalarizeBinop(SDValue VecOp) const override
Try to convert an extract element of a vector binary operation into an extract element followed by a ...
Definition: RISCVISelLowering.cpp:1350
llvm::RISCVISD::VFMV_V_F_VL
@ VFMV_V_F_VL
Definition: RISCVISelLowering.h:125
llvm::RISCVISD::VWMULSU_VL
@ VWMULSU_VL
Definition: RISCVISelLowering.h:243
llvm::RISCVTargetLowering::shouldInsertFencesForAtomic
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
Definition: RISCVISelLowering.h:441
llvm::RISCVISD::UADDSAT_VL
@ UADDSAT_VL
Definition: RISCVISelLowering.h:207
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::RISCVISD::VWADDU_W_VL
@ VWADDU_W_VL
Definition: RISCVISelLowering.h:249
llvm::RISCVISD::VRGATHEREI16_VV_VL
@ VRGATHEREI16_VV_VL
Definition: RISCVISelLowering.h:279
llvm::RISCVISD::VECREDUCE_FADD_VL
@ VECREDUCE_FADD_VL
Definition: RISCVISelLowering.h:181
llvm::RISCVTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Returns the register with the specified architectural or ABI name.
Definition: RISCVISelLowering.cpp:12570
llvm::RISCVISD::UREM_VL
@ UREM_VL
Definition: RISCVISelLowering.h:199
llvm::RISCVISD::TAIL
@ TAIL
Definition: RISCVISelLowering.h:43
llvm::RISCVVIntrinsicsTable::RISCVVIntrinsicInfo
Definition: RISCVISelLowering.h:719
llvm::CombineLevel
CombineLevel
Definition: DAGCombine.h:15
llvm::RISCVISD::NodeType
NodeType
Definition: RISCVISelLowering.h:26
llvm::RISCVISD::FCVT_W_RV64
@ FCVT_W_RV64
Definition: RISCVISelLowering.h:106
llvm::RISCVISD::VECREDUCE_ADD_VL
@ VECREDUCE_ADD_VL
Definition: RISCVISelLowering.h:173
llvm::RISCVTargetLowering::shouldExpandBuildVectorWithShuffles
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
Definition: RISCVISelLowering.cpp:1851
llvm::RISCVISD::UMAX_VL
@ UMAX_VL
Definition: RISCVISelLowering.h:204
llvm::ISD::FIRST_TARGET_MEMORY_OPCODE
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:1319
N
#define N
llvm::RISCVISD::READ_CSR
@ READ_CSR
Definition: RISCVISelLowering.h:292
llvm::RISCVTargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: RISCVISelLowering.cpp:1154
llvm::RISCVTargetLowering::getNumRegistersForCallingConv
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...
Definition: RISCVISelLowering.cpp:1441
llvm::RISCVII::VLMUL
VLMUL
Definition: RISCVBaseInfo.h:108
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::RISCVTargetLowering::getJumpTableEncoding
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
Definition: RISCVISelLowering.cpp:12299
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::RISCVTargetLowering::shouldExtendTypeInLibCall
bool shouldExtendTypeInLibCall(EVT Type) const override
Returns true if arguments should be extended in lib calls.
Definition: RISCVISelLowering.cpp:12360
RegName
#define RegName(no)
llvm::Function::hasMinSize
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:661
llvm::RISCVISD::SRET_FLAG
@ SRET_FLAG
Definition: RISCVISelLowering.h:30
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1474
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:463
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::RISCVTargetLowering::LowerReturn
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition: RISCVISelLowering.cpp:11518
llvm::RISCVTargetLowering::getExtendForAtomicOps
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
Definition: RISCVISelLowering.h:452
llvm::RISCVISD::FDIV_VL
@ FDIV_VL
Definition: RISCVISelLowering.h:216
llvm::RISCVTargetLowering::mayBeEmittedAsTailCall
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
Definition: RISCVISelLowering.cpp:11664
llvm::RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL
@ SPLAT_VECTOR_SPLIT_I64_VL
Definition: RISCVISelLowering.h:136
llvm::RISCVISD::VSLIDE1DOWN_VL
@ VSLIDE1DOWN_VL
Definition: RISCVISelLowering.h:152
llvm::RISCVTargetLowering::shouldSinkOperands
bool shouldSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops) const override
Check if sinking I's operands to I's basic block is profitable, because the operands can be folded in...
Definition: RISCVISelLowering.cpp:1252
llvm::MachineJumpTableInfo
Definition: MachineJumpTableInfo.h:42
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:760
llvm::RISCVTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
Definition: RISCVISelLowering.cpp:985
llvm::RISCVISD::TRUNCATE_VECTOR_VL
@ TRUNCATE_VECTOR_VL
Definition: RISCVISelLowering.h:141
llvm::RISCVISD::SSUBSAT_VL
@ SSUBSAT_VL
Definition: RISCVISelLowering.h:208
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:132
llvm::RISCVISD::FCOPYSIGN_VL
@ FCOPYSIGN_VL
Definition: RISCVISelLowering.h:224
llvm::RISCVTargetLowering::getRegisterTypeForCallingConv
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...
Definition: RISCVISelLowering.cpp:1429
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::RISCVISD::CTZW
@ CTZW
Definition: RISCVISelLowering.h:79
llvm::AtomicCmpXchgInst
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:510
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
llvm::RISCVTargetLowering::getContainerForFixedLengthVector
MVT getContainerForFixedLengthVector(MVT VT) const
Definition: RISCVISelLowering.cpp:1775
llvm::RISCVISD::URET_FLAG
@ URET_FLAG
Definition: RISCVISelLowering.h:29
llvm::RISCVISD::VSLIDEUP_VL
@ VSLIDEUP_VL
Definition: RISCVISelLowering.h:146
llvm::RISCVISD::FSQRT_VL
@ FSQRT_VL
Definition: RISCVISelLowering.h:223
llvm::RISCVISD::UDIV_VL
@ UDIV_VL
Definition: RISCVISelLowering.h:198
llvm::RISCVTargetLowering::isShuffleMaskLegal
bool isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override
Return true if the given shuffle mask can be codegen'd directly, or if it should be stack expanded.
Definition: RISCVISelLowering.cpp:3205
llvm::RISCVABI::ABI
ABI
Definition: RISCVBaseInfo.h:372
llvm::RISCVISD::SRA_VL
@ SRA_VL
Definition: RISCVISelLowering.h:195
llvm::RISCVTargetLowering::shouldExpandAtomicCmpXchgInIR
TargetLowering::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Definition: RISCVISelLowering.cpp:12243
llvm::LLT
Definition: LowLevelTypeImpl.h:39