LLVM  9.0.0svn
RISCVISelLowering.h
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1 //===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that RISCV uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
15 #define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
16 
17 #include "RISCV.h"
20 
21 namespace llvm {
22 class RISCVSubtarget;
23 namespace RISCVISD {
24 enum NodeType : unsigned {
35  // RV64I shifts, directly matching the semantics of the named RISC-V
36  // instructions.
40  // 32-bit operations from RV64M that can't be simply matched with a pattern
41  // at instruction selection time.
45  // FPR32<->GPR transfer operations for RV64. Needed as an i32<->f32 bitcast
46  // is not legal on RV64. FMV_W_X_RV64 matches the semantics of the FMV.W.X.
47  // FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result.
48  // This is a more convenient semantic for producing dagcombines that remove
49  // unnecessary GPR->FPR->GPR moves.
52 };
53 }
54 
56  const RISCVSubtarget &Subtarget;
57 
58 public:
59  explicit RISCVTargetLowering(const TargetMachine &TM,
60  const RISCVSubtarget &STI);
61 
62  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
63  MachineFunction &MF,
64  unsigned Intrinsic) const override;
65  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
66  unsigned AS,
67  Instruction *I = nullptr) const override;
68  bool isLegalICmpImmediate(int64_t Imm) const override;
69  bool isLegalAddImmediate(int64_t Imm) const override;
70  bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
71  bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
72  bool isZExtFree(SDValue Val, EVT VT2) const override;
73  bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
74 
75  bool hasBitPreservingFPLogic(EVT VT) const override;
76 
77  // Provide custom lowering hooks for some operations.
78  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
79  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
80  SelectionDAG &DAG) const override;
81 
82  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
83 
84  unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
85  const APInt &DemandedElts,
86  const SelectionDAG &DAG,
87  unsigned Depth) const override;
88 
89  // This method returns the name of a target specific DAG node.
90  const char *getTargetNodeName(unsigned Opcode) const override;
91 
92  std::pair<unsigned, const TargetRegisterClass *>
93  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
94  StringRef Constraint, MVT VT) const override;
95 
96  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
97  std::vector<SDValue> &Ops,
98  SelectionDAG &DAG) const override;
99 
101  EmitInstrWithCustomInserter(MachineInstr &MI,
102  MachineBasicBlock *BB) const override;
103 
104  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
105  EVT VT) const override;
106 
107  bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
108  return VT.isScalarInteger();
109  }
110 
111  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
112  return isa<LoadInst>(I) || isa<StoreInst>(I);
113  }
114  Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
115  AtomicOrdering Ord) const override;
116  Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
117  AtomicOrdering Ord) const override;
118 
120  return ISD::SIGN_EXTEND;
121  }
122 
123  bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override {
125  return false;
126  return true;
127  }
128  bool isDesirableToCommuteWithShift(const SDNode *N,
129  CombineLevel Level) const override;
130 
131 private:
132  void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
134  bool IsRet) const;
135  void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
137  bool IsRet, CallLoweringInfo *CLI) const;
138  // Lower incoming arguments, copy physregs into vregs
139  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
140  bool IsVarArg,
142  const SDLoc &DL, SelectionDAG &DAG,
143  SmallVectorImpl<SDValue> &InVals) const override;
144  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
145  bool IsVarArg,
147  LLVMContext &Context) const override;
148  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
150  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
151  SelectionDAG &DAG) const override;
153  SmallVectorImpl<SDValue> &InVals) const override;
154  bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
155  Type *Ty) const override {
156  return true;
157  }
158 
159  template <class NodeTy>
160  SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const;
161 
162  SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
163  bool UseGOT) const;
164  SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
165 
166  bool shouldConsiderGEPOffsetSplit() const override { return true; }
167  SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
168  SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
169  SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
170  SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
171  SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
172  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
173  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
174  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
175  SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
176  SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
177 
178  bool isEligibleForTailCallOptimization(
179  CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
180  const SmallVector<CCValAssign, 16> &ArgLocs) const;
181 
183  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
184  virtual Value *emitMaskedAtomicRMWIntrinsic(
185  IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr,
186  Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override;
188  shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override;
189  virtual Value *
190  emitMaskedAtomicCmpXchgIntrinsic(IRBuilder<> &Builder, AtomicCmpXchgInst *CI,
191  Value *AlignedAddr, Value *CmpVal,
192  Value *NewVal, Value *Mask,
193  AtomicOrdering Ord) const override;
194 };
195 }
196 
197 #endif
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:913
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
LLVMContext & Context
This class represents lattice values for constants.
Definition: AllocatorList.h:23
An instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:530
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:145
This class represents a function call, abstracting a target machine&#39;s calling convention.
Function Alias Analysis Results
unsigned const TargetRegisterInfo * TRI
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:693
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a libr...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:38
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:742
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform&#39;s atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
bool convertSetCCLogicToBitwiseLogic(EVT VT) const override
Use bitwise logic to make pairs of compares more efficient.
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:400
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic...
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
CombineLevel
Definition: DAGCombine.h:15
Extended Value Type.
Definition: ValueTypes.h:33
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
CCState - This class holds information needed while lowering arguments and return values...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
const Function & getFunction() const
Return the LLVM function that this machine code represents.
Class for arbitrary precision integers.
Definition: APInt.h:69
Representation of each machine instruction.
Definition: MachineInstr.h:63
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:611
LLVM Value Representation.
Definition: Value.h:72
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
Conversion operators.
Definition: ISDOpcodes.h:489
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
This file describes how to lower LLVM code to machine code.