LLVM 22.0.0git
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#include "NVPTXISelLowering.h"
#include "MCTargetDesc/NVPTXBaseInfo.h"
#include "NVPTX.h"
#include "NVPTXISelDAGToDAG.h"
#include "NVPTXSubtarget.h"
#include "NVPTXTargetMachine.h"
#include "NVPTXTargetObjectFile.h"
#include "NVPTXUtilities.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/Analysis.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetCallingConv.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/CodeGenTypes/MachineValueType.h"
#include "llvm/IR/Argument.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/FPEnv.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/Instruction.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicsNVPTX.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/Value.h"
#include "llvm/Support/Alignment.h"
#include "llvm/Support/AtomicOrdering.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/NVPTXAddrSpace.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include <algorithm>
#include <cassert>
#include <cmath>
#include <cstdint>
#include <iterator>
#include <optional>
#include <string>
#include <tuple>
#include <utility>
#include <vector>
Go to the source code of this file.
Macros | |
#define | DEBUG_TYPE "nvptx-lower" |
#define | MAKE_CASE(V) |
Enumerations | |
enum | OperandSignedness { Signed = 0 , Unsigned , Unknown } |
Variables | |
static cl::opt< bool > | sched4reg ("nvptx-sched4reg", cl::desc("NVPTX Specific: schedule for register pressue"), cl::init(false)) |
static cl::opt< unsigned > | FMAContractLevelOpt ("nvptx-fma-level", cl::Hidden, cl::desc("NVPTX Specific: FMA contraction (0: don't do it" " 1: do it 2: do it aggressively"), cl::init(2)) |
static cl::opt< NVPTX::DivPrecisionLevel > | UsePrecDivF32 ("nvptx-prec-divf32", cl::Hidden, cl::desc("NVPTX Specific: Override the precision of the lowering for f32 fdiv"), cl::values(clEnumValN(NVPTX::DivPrecisionLevel::Approx, "0", "Use div.approx"), clEnumValN(NVPTX::DivPrecisionLevel::Full, "1", "Use div.full"), clEnumValN(NVPTX::DivPrecisionLevel::IEEE754, "2", "Use IEEE Compliant F32 div.rnd if available (default)"), clEnumValN(NVPTX::DivPrecisionLevel::IEEE754_NoFTZ, "3", "Use IEEE Compliant F32 div.rnd if available, no FTZ")), cl::init(NVPTX::DivPrecisionLevel::IEEE754)) |
static cl::opt< bool > | UsePrecSqrtF32 ("nvptx-prec-sqrtf32", cl::Hidden, cl::desc("NVPTX Specific: 0 use sqrt.approx, 1 use sqrt.rn."), cl::init(true)) |
static cl::opt< bool > | UseApproxLog2F32 ("nvptx-approx-log2f32", cl::desc("NVPTX Specific: whether to use lg2.approx for log2"), cl::init(false)) |
Whereas CUDA's implementation (see libdevice) uses ex2.approx for exp2(), it does NOT use lg2.approx for log2, so this is disabled by default. | |
static cl::opt< bool > | ForceMinByValParamAlign ("nvptx-force-min-byval-param-align", cl::Hidden, cl::desc("NVPTX Specific: force 4-byte minimal alignment for byval" " params of device functions."), cl::init(false)) |
#define DEBUG_TYPE "nvptx-lower" |
Definition at line 76 of file NVPTXISelLowering.cpp.
#define MAKE_CASE | ( | V | ) |
enum OperandSignedness |
Enumerator | |
---|---|
Signed | |
Unsigned | |
Unknown |
Definition at line 5795 of file NVPTXISelLowering.cpp.
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AreMulWideOperandsDemotable - Checks if the given LHS and RHS operands can be demoted to OptSize
bits without loss of information.
If the operands contain a constant, it should appear as the RHS operand. The signedness of the operands is placed in IsSigned
.
Definition at line 5831 of file NVPTXISelLowering.cpp.
References llvm::dyn_cast(), llvm::APInt::isIntN(), IsMulWideOperandDemotable(), llvm::APInt::isSignedIntN(), LHS, RHS, Signed, Unknown, and Unsigned.
Referenced by TryMULWIDECombine().
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Reduces the elements using the scalar operations provided.
The operations are sorted descending in number of inputs they take. The flags on the original reduction operation will be propagated to each scalar operation. Nearby elements are grouped in tree reduction, unlike the shuffle reduction used in ExpandReductions and SelectionDAG.
Definition at line 1971 of file NVPTXISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, assert(), DL, E(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), llvm::SelectionDAG::getNode(), I, OpIdx, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::ArrayRef< T >::slice().
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Definition at line 424 of file NVPTXISelLowering.cpp.
References llvm::EVT::getStoreSize(), and llvm::SmallVectorTemplateCommon< T, typename >::size().
Referenced by VectorizePTXValueVTs().
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Definition at line 7009 of file NVPTXISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), and SDValue().
Referenced by simplifyDemandedBitsForPRMT().
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Definition at line 6220 of file NVPTXISelLowering.cpp.
References assert(), llvm::cast(), llvm::dyn_cast(), N, and SDValue().
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Definition at line 5621 of file NVPTXISelLowering.cpp.
References combineUnpackingMovIntoLoad(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), lowerLoadVector(), and N.
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Definition at line 5951 of file NVPTXISelLowering.cpp.
References llvm::ISD::ADD, llvm::Add, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getNode(), matchMADConstOnePattern(), llvm::ISD::MUL, Mul, SDValue(), X, and Y.
Referenced by PerformMULCombineWithOperands().
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Definition at line 5962 of file NVPTXISelLowering.cpp.
References Cond, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getNode(), isConstOne(), matchMADConstOnePattern(), llvm::ISD::MUL, SDValue(), llvm::ISD::SELECT, Select, X, and Y.
Referenced by PerformMULCombineWithOperands().
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Definition at line 5760 of file NVPTXISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::isa(), llvm::ISD::MUL, llvm::NVPTXISD::MUL_WIDE_SIGNED, llvm::NVPTXISD::MUL_WIDE_UNSIGNED, N, llvm::None, RHS, SDValue(), llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.
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Fold packing movs into a store.
ex: v1: v2f16 = BUILD_VECTOR a:f16, b:f16 v2: v2f16 = BUILD_VECTOR c:f16, d:f16 StoreV2 v1, v2
...is turned into...
StoreV4 a, b, c, d
Definition at line 5526 of file NVPTXISelLowering.cpp.
References llvm::SmallVectorImpl< T >::append(), llvm::ISD::BUILD_VECTOR, llvm::cast(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ISD::FP_ROUND, llvm::SelectionDAG::getMemIntrinsicNode(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), llvm::NVPTX::isPackedVectorTy(), llvm_unreachable, N, SDValue(), llvm::NVPTXISD::StoreV2, llvm::NVPTXISD::StoreV4, llvm::NVPTXISD::StoreV8, and llvm::ISD::TRUNCATE.
Referenced by combineSTORE().
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Definition at line 6291 of file NVPTXISelLowering.cpp.
References computePRMT(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::isa(), N, llvm::None, and SDValue().
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Definition at line 6373 of file NVPTXISelLowering.cpp.
References N, Reg, SDValue(), and sinkProxyReg().
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Definition at line 5606 of file NVPTXISelLowering.cpp.
References llvm::cast(), combinePackingMovIntoStore(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), lowerSTOREVector(), N, and SDValue().
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Fold unpacking movs into a load by increasing the number of return values.
ex: L: v2f16,ch = load
a: f16 = extractelt L:0, 0 b: f16 = extractelt L:0, 1 use(a, b)
...is turned into...
L: f16,f16,ch = LoadV2
Definition at line 5413 of file NVPTXISelLowering.cpp.
References llvm::all_of(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), llvm::NVPTX::isPackedVectorTy(), N, and SDValue().
Referenced by combineLOAD().
Definition at line 6946 of file NVPTXISelLowering.cpp.
References assert(), llvm::cast(), llvm::KnownBits::getBitWidth(), llvm::NVPTXDAGToDAGISel::getFromTypeWidthForLoad(), llvm::APInt::setHighBits(), llvm::ISD::SEXTLOAD, and llvm::KnownBits::Zero.
Referenced by llvm::NVPTXTargetLowering::computeKnownBitsForTargetNode().
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Definition at line 6915 of file NVPTXISelLowering.cpp.
References A(), llvm::KnownBits::ashr(), assert(), B(), llvm::SelectionDAG::computeKnownBits(), llvm::KnownBits::concat(), llvm::Depth, llvm::dyn_cast(), llvm::APInt::extractBits(), llvm::ConstantSDNode::getAPIntValue(), llvm::KnownBits::getBitWidth(), llvm::APInt::getHiBits(), llvm::APInt::getLoBits(), getPRMTSelector(), llvm::APInt::getZExtValue(), I, llvm::KnownBits::insertBits(), Mode, and llvm::seq().
Referenced by llvm::NVPTXTargetLowering::computeKnownBitsForTargetNode().
Definition at line 6272 of file NVPTXISelLowering.cpp.
References A(), assert(), B(), llvm::APInt::extractBits(), llvm::APInt::getBitWidth(), llvm::APInt::getHiBits(), llvm::APInt::getLoBits(), getPRMTSelector(), llvm::APInt::getZExtValue(), I, Mode, and llvm::seq().
Referenced by combinePRMT().
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ComputePTXValueVTs - For the given Type Ty
, returns the set of primitive legal-ish MVTs that compose it.
Unlike ComputeValueVTs, this will legalize the types as required by the calling convention (with special handling for i8s). NOTE: This is a band-aid for code that expects ComputeValueVTs to return the same number of types as the Ins/Outs arrays in LowerFormalArguments, LowerCall, and LowerReturn.
Definition at line 301 of file NVPTXISelLowering.cpp.
References assert(), llvm::ComputeValueVTs(), DL, llvm::TargetLoweringBase::getNumRegistersForCallingConv(), llvm::TargetLoweringBase::getRegisterTypeForCallingConv(), llvm::MVT::getStoreSize(), I, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::seq(), and llvm::zip().
Referenced by llvm::NVPTXTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerFormalArguments(), and llvm::NVPTXTargetLowering::LowerReturn().
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Definition at line 1439 of file NVPTXISelLowering.cpp.
References assert(), llvm::EVT::bitsGT(), llvm::EVT::bitsLT(), getExtOpcode(), llvm::SelectionDAG::getNode(), llvm::EVT::isInteger(), and llvm::ISD::TRUNCATE.
Referenced by llvm::NVPTXTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerFormalArguments(), and llvm::NVPTXTargetLowering::LowerReturn().
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Definition at line 3067 of file NVPTXISelLowering.cpp.
References A(), assert(), B(), llvm::NVPTXISD::BUILD_VECTOR, DL, llvm::dyn_cast(), llvm::ISD::FSHL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), High, llvm::Low, SDValue(), and llvm::NVPTXISD::UNPACK_VECTOR.
Referenced by lowerFSH(), and lowerROT().
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Definition at line 366 of file NVPTXISelLowering.cpp.
References llvm::SelectionDAG::ExtractVectorElements(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getContext(), llvm::SDValue::getValueType(), llvm::EVT::getVectorVT(), I, llvm::EVT::isVector(), N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::seq(), llvm::SmallVectorTemplateCommon< T, typename >::size(), and T.
Referenced by llvm::NVPTXTargetLowering::LowerCall(), and llvm::NVPTXTargetLowering::LowerReturn().
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Definition at line 1431 of file NVPTXISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.
Referenced by correctParamType().
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Definition at line 349 of file NVPTXISelLowering.cpp.
References assert(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), I, and llvm::EVT::isVector().
Referenced by llvm::NVPTXTargetLowering::LowerCall(), and llvm::NVPTXTargetLowering::LowerFormalArguments().
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Get 3-input version of a 2-input min/max opcode.
Definition at line 5679 of file NVPTXISelLowering.cpp.
References llvm::NVPTXISD::FMAXIMUM3, llvm::NVPTXISD::FMAXNUM3, llvm::NVPTXISD::FMINIMUM3, llvm::NVPTXISD::FMINNUM3, and llvm_unreachable.
Referenced by PerformFMinMaxCombine().
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Definition at line 1951 of file NVPTXISelLowering.cpp.
References A(), assert(), B(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), Mode, llvm::NVPTX::PTXPrmtMode::NONE, and llvm::NVPTXISD::PRMT.
Referenced by getPRMT(), lowerPrmtIntrinsic(), PerformBUILD_VECTORCombine(), and simplifyDemandedBitsForPRMT().
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Definition at line 1960 of file NVPTXISelLowering.cpp.
References A(), B(), DL, llvm::SelectionDAG::getConstant(), getPRMT(), Mode, and llvm::NVPTX::PTXPrmtMode::NONE.
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Definition at line 6983 of file NVPTXISelLowering.cpp.
References llvm::APInt::extractBits(), llvm::APInt::getHiBits(), llvm::APInt::getLoBits(), llvm::APInt::getZExtValue(), I, llvm::seq(), and llvm::APInt::setBit().
Referenced by simplifyDemandedBitsForPRMT().
Definition at line 6239 of file NVPTXISelLowering.cpp.
References assert(), llvm::NVPTX::PTXPrmtMode::B4E, llvm::NVPTX::PTXPrmtMode::ECL, llvm::NVPTX::PTXPrmtMode::ECR, llvm::NVPTX::PTXPrmtMode::F4E, llvm::APInt::getBitWidth(), llvm::APInt::getZExtValue(), llvm_unreachable, Mode, llvm::NVPTX::PTXPrmtMode::NONE, llvm::NVPTX::PTXPrmtMode::RC16, llvm::NVPTX::PTXPrmtMode::RC8, S1, and llvm::APInt::trunc().
Referenced by computeKnownBitsForPRMT(), computePRMT(), and simplifyDemandedBitsForPRMT().
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Get 3-input scalar reduction opcode.
Definition at line 2035 of file NVPTXISelLowering.cpp.
References llvm::NVPTXISD::FMAXIMUM3, llvm::NVPTXISD::FMAXNUM3, llvm::NVPTXISD::FMINIMUM3, and llvm::NVPTXISD::FMINNUM3.
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Definition at line 2018 of file NVPTXISelLowering.cpp.
References llvm_unreachable.
Definition at line 2662 of file NVPTXISelLowering.cpp.
References llvm_unreachable, llvm::NVPTXISD::TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG1, llvm::NVPTXISD::TCGEN05_MMA_SHARED_DISABLE_OUTPUT_LANE_CG2, llvm::NVPTXISD::TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1, llvm::NVPTXISD::TCGEN05_MMA_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2, llvm::NVPTXISD::TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG1, llvm::NVPTXISD::TCGEN05_MMA_SP_SHARED_DISABLE_OUTPUT_LANE_CG2, llvm::NVPTXISD::TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG1, llvm::NVPTXISD::TCGEN05_MMA_SP_SHARED_SCALE_D_DISABLE_OUTPUT_LANE_CG2, llvm::NVPTXISD::TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1, llvm::NVPTXISD::TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT, llvm::NVPTXISD::TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2, llvm::NVPTXISD::TCGEN05_MMA_SP_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT, llvm::NVPTXISD::TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1, llvm::NVPTXISD::TCGEN05_MMA_SP_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2, llvm::NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1, llvm::NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG1_ASHIFT, llvm::NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2, llvm::NVPTXISD::TCGEN05_MMA_TENSOR_DISABLE_OUTPUT_LANE_CG2_ASHIFT, llvm::NVPTXISD::TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1, llvm::NVPTXISD::TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG1_ASHIFT, llvm::NVPTXISD::TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2, and llvm::NVPTXISD::TCGEN05_MMA_TENSOR_SCALE_D_DISABLE_OUTPUT_LANE_CG2_ASHIFT.
Referenced by LowerTcgen05MMADisableOutputLane().
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Definition at line 340 of file NVPTXISelLowering.cpp.
References llvm::CallingConv::C, llvm::EVT::getScalarType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::EVT::isVector(), and N.
Referenced by llvm::NVPTXTargetLowering::LowerCall(), and llvm::NVPTXTargetLowering::LowerFormalArguments().
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Definition at line 199 of file NVPTXISelLowering.cpp.
References llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::NVPTXSubtarget::has256BitVectorLoadStore(), llvm::NVPTXSubtarget::hasF32x2Instructions(), llvm::EVT::isScalarInteger(), llvm::EVT::isSimple(), llvm::MVT::isVector(), and llvm::MVT::SimpleTy.
Referenced by lowerSTOREVector(), and replaceLoadVector().
Definition at line 5933 of file NVPTXISelLowering.cpp.
References llvm::dyn_cast().
Referenced by combineMulSelectConstOne(), and matchMADConstOnePattern().
Definition at line 5272 of file NVPTXISelLowering.cpp.
References llvm::dyn_cast().
Referenced by PerformADDCombineWithOperands().
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IsMulWideOperandDemotable - Checks if the provided DAG node is an operand that can be demoted to OptSize
bits without loss of information.
The signedness of the operand, if determinable, is placed in S
.
Definition at line 5804 of file NVPTXISelLowering.cpp.
References llvm::EVT::getFixedSizeInBits(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, Signed, Unknown, Unsigned, and llvm::ISD::ZERO_EXTEND.
Referenced by AreMulWideOperandsDemotable().
Definition at line 154 of file NVPTXISelLowering.cpp.
References llvm::MVT::SimpleTy.
Referenced by llvm::NVPTXTargetLowering::NVPTXTargetLowering(), and PerformEXTRACTCombine().
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Definition at line 2876 of file NVPTXISelLowering.cpp.
References llvm::cast(), llvm::NVPTXISD::CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_X, llvm::NVPTXISD::CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Y, llvm::NVPTXISD::CLUSTERLAUNCHCONTROL_QUERY_CANCEL_GET_FIRST_CTAID_Z, llvm::NVPTXISD::CLUSTERLAUNCHCONTROL_QUERY_CANCEL_IS_CANCELED, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm_unreachable, N, and SDValue().
Referenced by lowerIntrinsicWOChain().
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Definition at line 3057 of file NVPTXISelLowering.cpp.
References assert(), DL, llvm::SelectionDAG::getNode(), llvm::SDNodeFlags::NonNeg, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::NVPTXTargetLowering::LowerOperation().
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Definition at line 2916 of file NVPTXISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::NVPTXISD::CVT_E2M1X4_F32X4_RS_SF, llvm::NVPTXISD::CVT_E2M3X4_F32X4_RS_SF, llvm::NVPTXISD::CVT_E3M2X4_F32X4_RS_SF, llvm::NVPTXISD::CVT_E4M3X4_F32X4_RS_SF, llvm::NVPTXISD::CVT_E5M2X4_F32X4_RS_SF, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm_unreachable, and N.
Referenced by lowerIntrinsicWOChain().
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Definition at line 3122 of file NVPTXISelLowering.cpp.
References llvm::SDNodeFlags::AllowContract, DL, llvm::ISD::FDIV, llvm::ISD::FMUL, llvm::ISD::FSUB, llvm::SelectionDAG::getConstantFP(), llvm::APFloat::getInf(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), Mul, llvm::ISD::SETEQ, llvm::Sub, X, and Y.
Referenced by llvm::NVPTXTargetLowering::LowerOperation().
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Definition at line 3111 of file NVPTXISelLowering.cpp.
References expandFSH64().
Referenced by llvm::NVPTXTargetLowering::LowerOperation().
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Definition at line 2796 of file NVPTXISelLowering.cpp.
References llvm::cast(), llvm::SDValue::getNode(), LowerTcgen05MMADisableOutputLane(), lowerTcgen05St(), and N.
Referenced by llvm::NVPTXTargetLowering::LowerOperation().
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Definition at line 3000 of file NVPTXISelLowering.cpp.
References llvm::SelectionDAG::getMergeValues(), lowerTcgen05Ld(), and SDValue().
Referenced by llvm::NVPTXTargetLowering::LowerOperation().
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Definition at line 3021 of file NVPTXISelLowering.cpp.
References LowerClusterLaunchControlQueryCancel(), lowerCvtRSIntrinsics(), and lowerPrmtIntrinsic().
Referenced by llvm::NVPTXTargetLowering::LowerOperation().
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Definition at line 3526 of file NVPTXISelLowering.cpp.
References assert(), llvm::SelectionDAG::getExtLoad(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::ISD::NON_EXTLOAD, llvm::ISD::TRUNCATE, and llvm::ISD::ZEXTLOAD.
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Definition at line 3515 of file NVPTXISelLowering.cpp.
References llvm::SelectionDAG::getMergeValues(), N, replaceLoadVector(), and SDValue().
Referenced by combineLOAD().
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Definition at line 2971 of file NVPTXISelLowering.cpp.
References A(), B(), llvm::NVPTX::PTXPrmtMode::B4E, DL, llvm::NVPTX::PTXPrmtMode::ECL, llvm::NVPTX::PTXPrmtMode::ECR, llvm::NVPTX::PTXPrmtMode::F4E, llvm::SelectionDAG::getConstant(), getPRMT(), llvm_unreachable, Mode, llvm::NVPTX::PTXPrmtMode::NONE, llvm::NVPTX::PTXPrmtMode::RC16, and llvm::NVPTX::PTXPrmtMode::RC8.
Referenced by lowerIntrinsicWOChain().
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Definition at line 3116 of file NVPTXISelLowering.cpp.
References expandFSH64(), llvm::ISD::FSHL, llvm::ISD::FSHR, and llvm::ISD::ROTL.
Referenced by llvm::NVPTXTargetLowering::LowerOperation().
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Definition at line 3150 of file NVPTXISelLowering.cpp.
References llvm::ISD::AND, assert(), Cond, DL, llvm::SelectionDAG::getAnyExtOrTrunc(), llvm::SelectionDAG::getFreeze(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SelectionDAG::getSelect(), llvm::ISD::OR, Select, and llvm::ISD::TRUNCATE.
Referenced by llvm::NVPTXTargetLowering::LowerOperation().
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Definition at line 3561 of file NVPTXISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::ANY_EXTEND, assert(), llvm::cast(), DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::ExtractVectorElements(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNode(), llvm::DataLayout::getPrefTypeAlign(), llvm::EVT::getSizeInBits(), llvm::EVT::getTypeForEVT(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), getVectorLoweringShape(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), I, llvm::EVT::isVector(), N, SDValue(), llvm::seq(), llvm::NVPTXISD::StoreV2, llvm::NVPTXISD::StoreV4, and llvm::NVPTXISD::StoreV8.
Referenced by combineSTORE().
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Definition at line 2753 of file NVPTXISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::BUILD_VECTOR, llvm::cast(), DL, llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), llvm::ISD::INTRINSIC_W_CHAIN, llvm::EVT::isVector(), N, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
Referenced by lowerIntrinsicWChain(), and ReplaceINTRINSIC_W_CHAIN().
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Definition at line 2722 of file NVPTXISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::cast(), DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SelectionDAG::getNode(), getTcgen05MMADisableOutputLane(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), I, llvm::EVT::isVector(), and N.
Referenced by lowerIntrinsicVoid().
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Definition at line 2636 of file NVPTXISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::cast(), DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), I, llvm::ISD::INTRINSIC_VOID, llvm::EVT::isVector(), and N.
Referenced by lowerIntrinsicVoid().
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Definition at line 2616 of file NVPTXISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, DL, E(), llvm::SelectionDAG::getNode(), I, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::transform().
Referenced by llvm::NVPTXTargetLowering::LowerOperation().
Definition at line 5938 of file NVPTXISelLowering.cpp.
References llvm::ISD::ADD, llvm::Add, isConstOne(), and SDValue().
Referenced by combineMADConstOne(), and combineMulSelectConstOne().
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PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
Definition at line 5636 of file NVPTXISelLowering.cpp.
References llvm::SDValue::getValueType(), llvm::EVT::isVector(), N, llvm::None, PerformADDCombineWithOperands(), and SDValue().
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PerformADDCombineWithOperands - Try DAG combinations for an ADD with operands N0 and N1.
This is a helper for PerformADDCombine that is called with the default operands, and if that fails, with commuted operands.
Definition at line 5282 of file NVPTXISelLowering.cpp.
References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSelect(), llvm::SDValue::getValueType(), llvm::SDNode::hasOneUse(), isConstZero(), llvm::ISD::MUL, Mul, N, SDValue(), and llvm::ISD::SELECT.
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Definition at line 6159 of file NVPTXISelLowering.cpp.
References assert(), llvm::cast(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getBitcast(), getPRMT(), llvm::EVT::getVectorNumElements(), llvm::EVT::is32BitVector(), llvm::isa(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), llvm::NVPTX::isPackedVectorTy(), N, SDValue(), llvm::ISD::SRL, and llvm::ISD::TRUNCATE.
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Definition at line 6074 of file NVPTXISelLowering.cpp.
References llvm::ISD::allOperandsUndef(), llvm::ISD::ANY_EXTEND, llvm::EVT::changeTypeToInteger(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::dyn_cast(), llvm::ISD::FREEZE, llvm::SelectionDAG::getConstant(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::NVPTX::isPackedVectorTy(), IsPTXVectorType(), llvm::EVT::isSimple(), N, SDValue(), llvm::ISD::SRA, llvm::ISD::TRUNCATE, and llvm::Vector.
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PerformFADDCombine - Target-specific dag combine xforms for ISD::FADD.
Definition at line 5660 of file NVPTXISelLowering.cpp.
References llvm::SDValue::getValueType(), llvm::EVT::isVector(), N, PerformFADDCombineWithOperands(), and SDValue().
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Definition at line 5322 of file NVPTXISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ISD::FADD, llvm::ISD::FMA, llvm::ISD::FMUL, llvm::SDNode::getFlags(), llvm::SDNode::getIROrder(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNodeFlags::hasAllowContract(), llvm::isa(), N, SDValue(), and llvm::SDNode::users().
Referenced by PerformFADDCombine().
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PerformFMinMaxCombine - Combine (fmaxnum (fmaxnum a, b), c) into (fmaxnum3 a, b, c).
Also covers other llvm min/max intrinsics.
Definition at line 5698 of file NVPTXISelLowering.cpp.
References A(), B(), llvm::CallingConv::C, llvm::TargetLowering::DAGCombinerInfo::DAG, getMinMax3Opcode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), N, and SDValue().
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PerformMULCombine - Runs PTX-specific DAG combine patterns on MUL nodes.
Definition at line 6020 of file NVPTXISelLowering.cpp.
References N, llvm::None, PerformMULCombineWithOperands(), SDValue(), and TryMULWIDECombine().
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Definition at line 5992 of file NVPTXISelLowering.cpp.
References combineMADConstOne(), combineMulSelectConstOne(), DL, llvm::SDValue::getValueType(), llvm::EVT::isVector(), N, and SDValue().
Referenced by PerformMULCombine().
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Definition at line 5728 of file NVPTXISelLowering.cpp.
References assert(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::Default, DL, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::ISD::MUL, N, llvm::ISD::SDIV, SDValue(), llvm::ISD::SREM, llvm::ISD::SUB, llvm::ISD::UDIV, llvm::ISD::UREM, and llvm::SDNode::users().
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Definition at line 6047 of file NVPTXISelLowering.cpp.
References A(), B(), llvm::ISD::BUILD_VECTOR, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), N, SDValue(), llvm::NVPTXISD::SETP_BF16X2, and llvm::NVPTXISD::SETP_F16X2.
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PerformSHLCombine - Runs PTX-specific DAG combine patterns on SHL nodes.
Definition at line 6035 of file NVPTXISelLowering.cpp.
References N, llvm::None, SDValue(), and TryMULWIDECombine().
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Definition at line 6126 of file NVPTXISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, llvm::CallingConv::C, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, E(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getAnyExtOrTrunc(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), I, N, SDValue(), and llvm::ISD::SELECT.
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Definition at line 2500 of file NVPTXISelLowering.cpp.
References DL, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getFPExtendOrRound(), llvm::SelectionDAG::getNode(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorVT(), llvm::EVT::isVector(), and N.
PromoteScalarIntegerPTX Used to make sure the arguments/returns are suitable for passing and promote them to a larger size if they're not.
The promoted type is placed in PromoteVT
if the function returns true.
Definition at line 390 of file NVPTXISelLowering.cpp.
References llvm::EVT::getFixedSizeInBits(), llvm::EVT::isScalarInteger(), llvm_unreachable, and llvm::PowerOf2Ceil().
Referenced by llvm::NVPTXTargetLowering::LowerCall(), and llvm::NVPTXTargetLowering::LowerReturn().
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Definition at line 1407 of file NVPTXISelLowering.cpp.
References llvm::NVPTXAS::ADDRESS_SPACE_GENERIC, llvm::NVPTXAS::ADDRESS_SPACE_LOCAL, llvm::cast(), DL, llvm::ISD::FrameIndex, llvm::SelectionDAG::getAddrSpaceCast(), llvm::TargetLoweringBase::getPointerTy(), and Ptr.
Referenced by llvm::NVPTXTargetLowering::LowerCall().
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Definition at line 6657 of file NVPTXISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, assert(), llvm::NVPTXISD::ATOMIC_CMP_SWAP_B128, llvm::NVPTXISD::ATOMIC_SWAP_B128, llvm::ISD::BUILD_PAIR, llvm::cast(), llvm::LLVMContext::diagnose(), llvm::ISD::EXTRACT_ELEMENT, llvm::SelectionDAG::getContext(), llvm::SDLoc::getDebugLoc(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVTList(), llvm::NVPTXSubtarget::hasAtomSwap128(), N, llvm::SDNode::ops(), and Results.
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Definition at line 6443 of file NVPTXISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), Results, llvm::ISD::SRL, and llvm::ISD::TRUNCATE.
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Definition at line 6617 of file NVPTXISelLowering.cpp.
References assert(), llvm::ISD::BUILD_PAIR, llvm::ISD::CopyFromReg, DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), N, Reg, and Results.
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Definition at line 6465 of file NVPTXISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::SmallVectorImpl< T >::append(), assert(), llvm::cast(), DL, llvm::SDNode::getAsZExtVal(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValue(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), llvm::ISD::INTRINSIC_W_CHAIN, llvm::EVT::isSimple(), llvm::EVT::isVector(), llvm::NVPTXISD::LDUV2, llvm::NVPTXISD::LDUV4, lowerTcgen05Ld(), N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), Results, llvm::MVT::SimpleTy, and llvm::ISD::TRUNCATE.
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replaceLoadVector - Convert vector loads into multi-output scalar loads.
Definition at line 3415 of file NVPTXISelLowering.cpp.
References assert(), llvm::cast(), DL, llvm::SelectionDAG::ExtractVectorElements(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::EVT::getTypeForEVT(), llvm::SDValue::getValue(), llvm::EVT::getVectorElementType(), getVectorLoweringShape(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), I, llvm::EVT::isVector(), llvm::NVPTXISD::LoadV2, llvm::NVPTXISD::LoadV4, llvm::NVPTXISD::LoadV8, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::seq(), llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::SmallVector, and llvm::ISD::TRUNCATE.
Referenced by lowerLoadVector(), and replaceLoadVector().
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Definition at line 3508 of file NVPTXISelLowering.cpp.
References N, replaceLoadVector(), and Results.
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Definition at line 6641 of file NVPTXISelLowering.cpp.
References llvm::SelectionDAG::getAnyExtOrTrunc(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getRegisterType(), N, llvm::NVPTXISD::ProxyReg, Reg, and Results.
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Definition at line 1398 of file NVPTXISelLowering.cpp.
References llvm::dyn_cast(), and llvm::CallBase::getFunctionType().
Referenced by llvm::NVPTXTargetLowering::LowerCall().
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Definition at line 7017 of file NVPTXISelLowering.cpp.
References assert(), canonicalizePRMTInput(), llvm::Depth, llvm::dyn_cast(), llvm::APInt::getLoBits(), getPRMT(), getPRMTDemandedBits(), getPRMTSelector(), llvm::APInt::getZExtValue(), Mode, llvm::NVPTXISD::PRMT, SDValue(), and llvm::TargetLowering::SimplifyMultipleUseDemandedBits().
Referenced by llvm::NVPTXTargetLowering::SimplifyDemandedBitsForTargetNode().
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Definition at line 6317 of file NVPTXISelLowering.cpp.
References A(), AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::ANY_EXTEND, B(), llvm::ISD::BUILD_VECTOR, llvm::ISD::Constant, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getNode(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::NVPTXISD::LoadV2, llvm::NVPTXISD::LoadV4, llvm::ISD::OR, llvm::NVPTXISD::ProxyReg, SDValue(), llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, sinkProxyReg(), llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
Referenced by combineProxyReg(), and sinkProxyReg().
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TryMULWIDECombine - Attempt to replace a multiply of M bits with a multiply of M/2 bits that produces an M-bit result (i.e.
mul.wide). This transform works on both multiply DAG nodes and SHL DAG nodes with a constant shift amount.
Definition at line 5867 of file NVPTXISelLowering.cpp.
References AreMulWideOperandsDemotable(), llvm::BitWidth, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::dyn_cast(), llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::isa(), LHS, llvm::ISD::MUL, llvm::NVPTXISD::MUL_WIDE_SIGNED, llvm::NVPTXISD::MUL_WIDE_UNSIGNED, N, Opc, RHS, SDValue(), llvm::APInt::sge(), llvm::ISD::SHL, Signed, llvm::APInt::slt(), std::swap(), and llvm::ISD::TRUNCATE.
Referenced by PerformMULCombine(), and PerformSHLCombine().
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Definition at line 478 of file NVPTXISelLowering.cpp.
References assert(), canMergeParamLoadStoresStartingAt(), E(), I, and llvm::SmallVectorTemplateCommon< T, typename >::size().
Referenced by llvm::NVPTXTargetLowering::LowerCall(), llvm::NVPTXTargetLowering::LowerFormalArguments(), and llvm::NVPTXTargetLowering::LowerReturn().
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Referenced by llvm::NVPTXTargetLowering::allowFMA().
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Referenced by llvm::NVPTXTargetLowering::getFunctionByValParamAlign().
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Referenced by llvm::NVPTXTargetLowering::NVPTXTargetLowering().
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Whereas CUDA's implementation (see libdevice) uses ex2.approx for exp2(), it does NOT use lg2.approx for log2, so this is disabled by default.
Referenced by llvm::NVPTXTargetLowering::NVPTXTargetLowering().
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Referenced by llvm::NVPTXTargetLowering::getDivF32Level().
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Referenced by llvm::NVPTXTargetLowering::usePrecSqrtF32().