This class defines information used to lower LLVM code to legal SelectionDAG operators that the target instruction selector can accept natively. More...

#include "llvm/CodeGen/TargetLowering.h"

Inheritance diagram for llvm::TargetLowering:

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Classes
struct	AsmOperandInfo
	This contains information for each constraint that we are lowering. More...

struct	CallLoweringInfo
	This structure contains all information that is necessary for lowering calls. More...

struct	DAGCombinerInfo

struct	MakeLibCallOptions
	This structure is used to pass arguments to makeLibCall function. More...

struct	PtrAuthInfo
	This structure contains the information necessary for lowering pointer-authenticating indirect calls. More...

struct	TargetLoweringOpt
	A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetLowering to its clients that want to combine. More...

Public Types
enum	ConstraintType { C_Register , C_RegisterClass , C_Memory , C_Address , C_Immediate , C_Other , C_Unknown }

enum	ConstraintWeight { CW_Invalid = -1 , CW_Okay = 0 , CW_Good = 1 , CW_Better = 2 , CW_Best = 3 , CW_SpecificReg = CW_Okay , CW_Register = CW_Good , CW_Memory = CW_Better , CW_Constant = CW_Best , CW_Default = CW_Okay }

using	AsmOperandInfoVector = std::vector< AsmOperandInfo >

using	ConstraintPair = std::pair< StringRef, TargetLowering::ConstraintType >

using	ConstraintGroup = SmallVector< ConstraintPair >

Public Types inherited from llvm::TargetLoweringBase
enum	LegalizeAction : uint8_t { Legal , Promote , Expand , LibCall , Custom }
	This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid. More...

enum	LegalizeTypeAction : uint8_t { TypeLegal , TypePromoteInteger , TypeExpandInteger , TypeSoftenFloat , TypeExpandFloat , TypeScalarizeVector , TypeSplitVector , TypeWidenVector , TypePromoteFloat , TypeSoftPromoteHalf , TypeScalarizeScalableVector }
	This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid. More...

enum	BooleanContent { UndefinedBooleanContent , ZeroOrOneBooleanContent , ZeroOrNegativeOneBooleanContent }
	Enum that describes how the target represents true/false values. More...

enum	SelectSupportKind { ScalarValSelect , ScalarCondVectorVal , VectorMaskSelect }
	Enum that describes what type of support for selects the target has. More...

enum class	AtomicExpansionKind { None , CastToInteger , LLSC , LLOnly , CmpXChg , MaskedIntrinsic , BitTestIntrinsic , CmpArithIntrinsic , Expand , NotAtomic }
	Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all. More...

enum class	MulExpansionKind { Always , OnlyLegalOrCustom }
	Enum that specifies when a multiplication should be expanded. More...

enum class	NegatibleCost { Cheaper = 0 , Neutral = 1 , Expensive = 2 }
	Enum that specifies when a float negation is beneficial. More...

enum	AndOrSETCCFoldKind : uint8_t { None = 0 , AddAnd = 1 , NotAnd = 2 , ABS = 4 }
	Enum of different potentially desirable ways to fold (and/or (setcc ...), (setcc ...)). More...

enum	ReciprocalEstimate : int { Unspecified = -1 , Disabled = 0 , Enabled = 1 }
	Reciprocal estimate status values used by the functions below. More...

enum class	ShiftLegalizationStrategy { ExpandToParts , ExpandThroughStack , LowerToLibcall }
	Return the preferred strategy to legalize tihs SHIFT instruction, with `ExpansionFactor` being the recursion depth - how many expansion needed. More...

using	LegalizeKind = std::pair< LegalizeTypeAction, EVT >
	LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.

using	ArgListTy = std::vector< ArgListEntry >

Public Member Functions
	TargetLowering (const TargetLowering &)=delete

TargetLowering &	operator= (const TargetLowering &)=delete

	TargetLowering (const TargetMachine &TM)
	NOTE: The TargetMachine owns TLOF.

bool	isPositionIndependent () const

virtual bool	isSDNodeSourceOfDivergence (const SDNode N, FunctionLoweringInfo FLI, UniformityInfo *UA) const

virtual bool	isReassocProfitable (SelectionDAG &DAG, SDValue N0, SDValue N1) const

virtual bool	isReassocProfitable (MachineRegisterInfo &MRI, Register N0, Register N1) const

virtual bool	isSDNodeAlwaysUniform (const SDNode *N) const

virtual bool	getPreIndexedAddressParts (SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
	Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's address can be legally represented as pre-indexed load / store address.

virtual bool	getPostIndexedAddressParts (SDNode , SDNode , SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
	Returns true by value, base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store.

virtual bool	isIndexingLegal (MachineInstr &MI, Register Base, Register Offset, bool IsPre, MachineRegisterInfo &MRI) const
	Returns true if the specified base+offset is a legal indexed addressing mode for this target.

virtual unsigned	getJumpTableEncoding () const
	Return the entry encoding for a jump table in the current function.

virtual MVT	getJumpTableRegTy (const DataLayout &DL) const

virtual const MCExpr *	LowerCustomJumpTableEntry (const MachineJumpTableInfo , const MachineBasicBlock , unsigned, MCContext &) const

virtual SDValue	getPICJumpTableRelocBase (SDValue Table, SelectionDAG &DAG) const
	Returns relocation base for the given PIC jumptable.

virtual const MCExpr *	getPICJumpTableRelocBaseExpr (const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const
	This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.

virtual bool	isOffsetFoldingLegal (const GlobalAddressSDNode *GA) const
	Return true if folding a constant offset with the given GlobalAddress is legal.

virtual bool	isInlineAsmTargetBranch (const SmallVectorImpl< StringRef > &AsmStrs, unsigned OpNo) const
	On x86, return true if the operand with index OpNo is a CALL or JUMP instruction, which can use either a memory constraint or an address constraint.

bool	isInTailCallPosition (SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const
	Check whether a given call node is in tail position within its function.

void	softenSetCCOperands (SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL, const SDValue OldLHS, const SDValue OldRHS) const
	Soften the operands of a comparison.

void	softenSetCCOperands (SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &DL, const SDValue OldLHS, const SDValue OldRHS, SDValue &Chain, bool IsSignaling=false) const

virtual SDValue	visitMaskedLoad (SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, MachineMemOperand *MMO, SDValue &NewLoad, SDValue Ptr, SDValue PassThru, SDValue Mask) const

virtual SDValue	visitMaskedStore (SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, MachineMemOperand *MMO, SDValue Ptr, SDValue Val, SDValue Mask) const

std::pair< SDValue, SDValue >	makeLibCall (SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, MakeLibCallOptions CallOptions, const SDLoc &dl, SDValue Chain=SDValue()) const
	Returns a pair of (return value, chain).

bool	parametersInCSRMatch (const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< SDValue > &OutVals) const
	Check whether parameters to a call that are passed in callee saved registers are the same as from the calling function.

virtual bool	findOptimalMemOpLowering (std::vector< EVT > &MemOps, unsigned Limit, const MemOp &Op, unsigned DstAS, unsigned SrcAS, const AttributeList &FuncAttributes) const
	Determines the optimal series of memory ops to replace the memset / memcpy.

bool	ShrinkDemandedConstant (SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const
	Check to see if the specified operand of the specified instruction is a constant integer.

bool	ShrinkDemandedConstant (SDValue Op, const APInt &DemandedBits, TargetLoweringOpt &TLO) const
	Helper wrapper around ShrinkDemandedConstant, demanding all elements.

virtual bool	targetShrinkDemandedConstant (SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const

bool	ShrinkDemandedOp (SDValue Op, unsigned BitWidth, const APInt &DemandedBits, TargetLoweringOpt &TLO) const
	Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.

bool	SimplifyDemandedBits (SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const
	Look at Op.

bool	SimplifyDemandedBits (SDValue Op, const APInt &DemandedBits, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const
	Helper wrapper around SimplifyDemandedBits, demanding all elements.

bool	SimplifyDemandedBits (SDValue Op, const APInt &DemandedBits, DAGCombinerInfo &DCI) const
	Helper wrapper around SimplifyDemandedBits.

bool	SimplifyDemandedBits (SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, DAGCombinerInfo &DCI) const
	Helper wrapper around SimplifyDemandedBits.

SDValue	SimplifyMultipleUseDemandedBits (SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth=0) const
	More limited version of SimplifyDemandedBits that can be used to "look through" ops that don't contribute to the DemandedBits/DemandedElts - bitwise ops etc.

SDValue	SimplifyMultipleUseDemandedBits (SDValue Op, const APInt &DemandedBits, SelectionDAG &DAG, unsigned Depth=0) const
	Helper wrapper around SimplifyMultipleUseDemandedBits, demanding all elements.

SDValue	SimplifyMultipleUseDemandedVectorElts (SDValue Op, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth=0) const
	Helper wrapper around SimplifyMultipleUseDemandedBits, demanding all bits from only some vector elements.

bool	SimplifyDemandedVectorElts (SDValue Op, const APInt &DemandedEltMask, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0, bool AssumeSingleUse=false) const
	Look at Vector Op.

bool	SimplifyDemandedVectorElts (SDValue Op, const APInt &DemandedElts, DAGCombinerInfo &DCI) const
	Helper wrapper around SimplifyDemandedVectorElts.

virtual bool	shouldSimplifyDemandedVectorElts (SDValue Op, const TargetLoweringOpt &TLO) const
	Return true if the target supports simplifying demanded vector elements by converting them to undefs.

virtual void	computeKnownBitsForTargetNode (const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const
	Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.

virtual void	computeKnownBitsForTargetInstr (GISelKnownBits &Analysis, Register R, KnownBits &Known, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) const
	Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.

virtual Align	computeKnownAlignForTargetInstr (GISelKnownBits &Analysis, Register R, const MachineRegisterInfo &MRI, unsigned Depth=0) const
	Determine the known alignment for the pointer value `R`.

virtual void	computeKnownBitsForFrameIndex (int FIOp, KnownBits &Known, const MachineFunction &MF) const
	Determine which of the bits of FrameIndex `FIOp` are known to be 0.

virtual unsigned	ComputeNumSignBitsForTargetNode (SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const
	This method can be implemented by targets that want to expose additional information about sign bits to the DAG Combiner.

virtual unsigned	computeNumSignBitsForTargetInstr (GISelKnownBits &Analysis, Register R, const APInt &DemandedElts, const MachineRegisterInfo &MRI, unsigned Depth=0) const
	This method can be implemented by targets that want to expose additional information about sign bits to GlobalISel combiners.

virtual bool	SimplifyDemandedVectorEltsForTargetNode (SDValue Op, const APInt &DemandedElts, APInt &KnownUndef, APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth=0) const
	Attempt to simplify any target nodes based on the demanded vector elements, returning true on success.

virtual bool	SimplifyDemandedBitsForTargetNode (SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0) const
	Attempt to simplify any target nodes based on the demanded bits/elts, returning true on success.

virtual SDValue	SimplifyMultipleUseDemandedBitsForTargetNode (SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth) const
	More limited version of SimplifyDemandedBits that can be used to "look through" ops that don't contribute to the DemandedBits/DemandedElts - bitwise ops etc.

virtual bool	isGuaranteedNotToBeUndefOrPoisonForTargetNode (SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, unsigned Depth) const
	Return true if this function can prove that `Op` is never poison and, if `PoisonOnly` is false, does not have undef bits.

virtual bool	canCreateUndefOrPoisonForTargetNode (SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const
	Return true if Op can create undef or poison from non-undef & non-poison operands.

SDValue	buildLegalVectorShuffle (EVT VT, const SDLoc &DL, SDValue N0, SDValue N1, MutableArrayRef< int > Mask, SelectionDAG &DAG) const
	Tries to build a legal vector shuffle using the provided parameters or equivalent variations.

virtual const Constant *	getTargetConstantFromLoad (LoadSDNode *LD) const
	This method returns the constant pool value that will be loaded by LD.

virtual bool	isKnownNeverNaNForTargetNode (SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const
	If `SNaN` is false,.

virtual bool	isSplatValueForTargetNode (SDValue Op, const APInt &DemandedElts, APInt &UndefElts, const SelectionDAG &DAG, unsigned Depth=0) const
	Return true if vector `Op` has the same value across all `DemandedElts`, indicating any elements which may be undef in the output `UndefElts`.

virtual bool	isTargetCanonicalConstantNode (SDValue Op) const
	Returns true if the given Opc is considered a canonical constant for the target, which should not be transformed back into a BUILD_VECTOR.

bool	isConstTrueVal (SDValue N) const
	Return if the N is a constant or constant vector equal to the true value from getBooleanContents().

bool	isConstFalseVal (SDValue N) const
	Return if the N is a constant or constant vector equal to the false value from getBooleanContents().

bool	isExtendedTrueVal (const ConstantSDNode *N, EVT VT, bool SExt) const
	Return if `N` is a True value when extended to `VT`.

SDValue	SimplifySetCC (EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, const SDLoc &dl) const
	Try to simplify a setcc built with the specified operands and cc.

virtual SDValue	unwrapAddress (SDValue N) const

virtual bool	isGAPlusOffset (SDNode N, const GlobalValue &GA, int64_t &Offset) const
	Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.

virtual SDValue	PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const
	This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for.

virtual bool	isDesirableToCommuteWithShift (const SDNode *N, CombineLevel Level) const
	Return true if it is profitable to move this shift by a constant amount through its operand, adjusting any immediate operands as necessary to preserve semantics.

virtual bool	isDesirableToCommuteWithShift (const MachineInstr &MI, bool IsAfterLegal) const
	GlobalISel - return true if it is profitable to move this shift by a constant amount through its operand, adjusting any immediate operands as necessary to preserve semantics.

virtual bool	isDesirableToPullExtFromShl (const MachineInstr &MI) const
	GlobalISel - return true if it's profitable to perform the combine: shl ([sza]ext x), y => zext (shl x, y)

virtual AndOrSETCCFoldKind	isDesirableToCombineLogicOpOfSETCC (const SDNode LogicOp, const SDNode SETCC0, const SDNode *SETCC1) const

virtual bool	isDesirableToCommuteXorWithShift (const SDNode *N) const
	Return true if it is profitable to combine an XOR of a logical shift to create a logical shift of NOT.

virtual bool	isTypeDesirableForOp (unsigned, EVT VT) const
	Return true if the target has native support for the specified value type and it is 'desirable' to use the type for the given node type.

virtual bool	isDesirableToTransformToIntegerOp (unsigned, EVT) const
	Return true if it is profitable for dag combiner to transform a floating point op of specified opcode to a equivalent op of an integer type.

virtual bool	IsDesirableToPromoteOp (SDValue, EVT &) const
	This method query the target whether it is beneficial for dag combiner to promote the specified node.

virtual bool	supportSwiftError () const
	Return true if the target supports swifterror attribute.

virtual bool	supportSplitCSR (MachineFunction *MF) const
	Return true if the target supports that a subset of CSRs for the given machine function is handled explicitly via copies.

virtual bool	supportKCFIBundles () const
	Return true if the target supports kcfi operand bundles.

virtual bool	supportPtrAuthBundles () const
	Return true if the target supports ptrauth operand bundles.

virtual void	initializeSplitCSR (MachineBasicBlock *Entry) const
	Perform necessary initialization to handle a subset of CSRs explicitly via copies.

virtual void	insertCopiesSplitCSR (MachineBasicBlock Entry, const SmallVectorImpl< MachineBasicBlock > &Exits) const
	Insert explicit copies in entry and exit blocks.

virtual SDValue	getNegatedExpression (SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, NegatibleCost &Cost, unsigned Depth=0) const
	Return the newly negated expression if the cost is not expensive and set the cost in `Cost` to indicate that if it is cheaper or neutral to do the negation.

SDValue	getCheaperOrNeutralNegatedExpression (SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, const NegatibleCost CostThreshold=NegatibleCost::Neutral, unsigned Depth=0) const

SDValue	getCheaperNegatedExpression (SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, unsigned Depth=0) const
	This is the helper function to return the newly negated expression only when the cost is cheaper.

SDValue	getNegatedExpression (SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, unsigned Depth=0) const
	This is the helper function to return the newly negated expression if the cost is not expensive.

virtual bool	splitValueIntoRegisterParts (SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, std::optional< CallingConv::ID > CC) const
	Target-specific splitting of values into parts that fit a register storing a legal type.

virtual bool	checkForPhysRegDependency (SDNode Def, SDNode User, unsigned Op, const TargetRegisterInfo TRI, const TargetInstrInfo TII, unsigned &PhysReg, int &Cost) const
	Allows the target to handle physreg-carried dependency in target-specific way.

virtual SDValue	joinRegisterPartsIntoValue (SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, std::optional< CallingConv::ID > CC) const
	Target-specific combining of register parts into its original value.

virtual SDValue	LowerFormalArguments (SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::InputArg > &, const SDLoc &, SelectionDAG &, SmallVectorImpl< SDValue > &) const
	This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array, into the specified DAG.

std::pair< SDValue, SDValue >	LowerCallTo (CallLoweringInfo &CLI) const
	This function lowers an abstract call to a function into an actual call.

virtual SDValue	LowerCall (CallLoweringInfo &, SmallVectorImpl< SDValue > &) const
	This hook must be implemented to lower calls into the specified DAG.

virtual void	HandleByVal (CCState *, unsigned &, Align) const
	Target-specific cleanup for formal ByVal parameters.

virtual bool	CanLowerReturn (CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const
	This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers.

virtual SDValue	LowerReturn (SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::OutputArg > &, const SmallVectorImpl< SDValue > &, const SDLoc &, SelectionDAG &) const
	This hook must be implemented to lower outgoing return values, described by the Outs array, into the specified DAG.

virtual bool	isUsedByReturnOnly (SDNode *, SDValue &) const
	Return true if result of the specified node is used by a return node only.

virtual bool	mayBeEmittedAsTailCall (const CallInst *) const
	Return true if the target may be able emit the call instruction as a tail call.

virtual Register	getRegisterByName (const char *RegName, LLT Ty, const MachineFunction &MF) const
	Return the register ID of the name passed in.

virtual EVT	getTypeForExtReturn (LLVMContext &Context, EVT VT, ISD::NodeType) const
	Return the type that should be used to zero or sign extend a zeroext/signext integer return value.

virtual bool	functionArgumentNeedsConsecutiveRegisters (Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const
	For some targets, an LLVM struct type must be broken down into multiple simple types, but the calling convention specifies that the entire struct must be passed in a block of consecutive registers.

virtual bool	shouldSplitFunctionArgumentsAsLittleEndian (const DataLayout &DL) const
	For most targets, an LLVM type must be broken down into multiple smaller types.

virtual const MCPhysReg *	getScratchRegisters (CallingConv::ID CC) const
	Returns a 0 terminated array of registers that can be safely used as scratch registers.

virtual ArrayRef< MCPhysReg >	getRoundingControlRegisters () const
	Returns a 0 terminated array of rounding control registers that can be attached into strict FP call.

virtual SDValue	prepareVolatileOrAtomicLoad (SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const
	This callback is used to prepare for a volatile or atomic load.

virtual void	LowerOperationWrapper (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
	This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types.

virtual SDValue	LowerOperation (SDValue Op, SelectionDAG &DAG) const
	This callback is invoked for operations that are unsupported by the target, which are registered to use 'custom' lowering, and whose defined values are all legal.

virtual void	ReplaceNodeResults (SDNode *, SmallVectorImpl< SDValue > &, SelectionDAG &) const
	This callback is invoked when a node result type is illegal for the target, and the operation was registered to use 'custom' lowering for that result type.

virtual const char *	getTargetNodeName (unsigned Opcode) const
	This method returns the name of a target specific DAG node.

virtual FastISel *	createFastISel (FunctionLoweringInfo &, const TargetLibraryInfo *) const
	This method returns a target specific FastISel object, or null if the target does not support "fast" ISel.

bool	verifyReturnAddressArgumentIsConstant (SDValue Op, SelectionDAG &DAG) const

virtual void	verifyTargetSDNode (const SDNode *N) const
	Check the given SDNode. Aborts if it is invalid.

virtual bool	ExpandInlineAsm (CallInst *) const
	This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to.

virtual AsmOperandInfoVector	ParseConstraints (const DataLayout &DL, const TargetRegisterInfo *TRI, const CallBase &Call) const
	Split up the constraint string from the inline assembly value into the specific constraints and their prefixes, and also tie in the associated operand values.

virtual ConstraintWeight	getMultipleConstraintMatchWeight (AsmOperandInfo &info, int maIndex) const
	Examine constraint type and operand type and determine a weight value.

virtual ConstraintWeight	getSingleConstraintMatchWeight (AsmOperandInfo &info, const char *constraint) const
	Examine constraint string and operand type and determine a weight value.

virtual void	ComputeConstraintToUse (AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const
	Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.

virtual ConstraintType	getConstraintType (StringRef Constraint) const
	Given a constraint, return the type of constraint it is for this target.

ConstraintGroup	getConstraintPreferences (AsmOperandInfo &OpInfo) const
	Given an OpInfo with list of constraints codes as strings, return a sorted Vector of pairs of constraint codes and their types in priority of what we'd prefer to lower them as.

virtual std::pair< unsigned, const TargetRegisterClass * >	getRegForInlineAsmConstraint (const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
	Given a physical register constraint (e.g.

virtual InlineAsm::ConstraintCode	getInlineAsmMemConstraint (StringRef ConstraintCode) const

virtual const char *	LowerXConstraint (EVT ConstraintVT) const
	Try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand.

virtual void	LowerAsmOperandForConstraint (SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
	Lower the specified operand into the Ops vector.

virtual SDValue	LowerAsmOutputForConstraint (SDValue &Chain, SDValue &Glue, const SDLoc &DL, const AsmOperandInfo &OpInfo, SelectionDAG &DAG) const

virtual void	CollectTargetIntrinsicOperands (const CallInst &I, SmallVectorImpl< SDValue > &Ops, SelectionDAG &DAG) const

SDValue	BuildSDIV (SDNode N, SelectionDAG &DAG, bool IsAfterLegalization, bool IsAfterLegalTypes, SmallVectorImpl< SDNode > &Created) const
	Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number.

SDValue	BuildUDIV (SDNode N, SelectionDAG &DAG, bool IsAfterLegalization, bool IsAfterLegalTypes, SmallVectorImpl< SDNode > &Created) const
	Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number.

SDValue	buildSDIVPow2WithCMov (SDNode N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode > &Created) const
	Build sdiv by power-of-2 with conditional move instructions Ref: "Hacker's Delight" by Henry Warren 10-1 If conditional move/branch is preferred, we lower sdiv x, +/-2k into: bgez x, label add x, x, 2k-1 label: sra res, x, k neg res, res (when the divisor is negative)

virtual SDValue	BuildSDIVPow2 (SDNode N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode > &Created) const
	Targets may override this function to provide custom SDIV lowering for power-of-2 denominators.

virtual SDValue	BuildSREMPow2 (SDNode N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode > &Created) const
	Targets may override this function to provide custom SREM lowering for power-of-2 denominators.

virtual unsigned	combineRepeatedFPDivisors () const
	Indicate whether this target prefers to combine FDIVs with the same divisor.

virtual SDValue	getSqrtEstimate (SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const
	Hooks for building estimates in place of slower divisions and square roots.

SDValue	createSelectForFMINNUM_FMAXNUM (SDNode *Node, SelectionDAG &DAG) const
	Try to convert the fminnum/fmaxnum to a compare/select sequence.

virtual SDValue	getRecipEstimate (SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const
	Return a reciprocal estimate value for the input operand.

virtual SDValue	getSqrtInputTest (SDValue Operand, SelectionDAG &DAG, const DenormalMode &Mode) const
	Return a target-dependent comparison result if the input operand is suitable for use with a square root estimate calculation.

virtual SDValue	getSqrtResultForDenormInput (SDValue Operand, SelectionDAG &DAG) const
	Return a target-dependent result if the input operand is not suitable for use with a square root estimate calculation.

bool	expandMUL_LOHI (unsigned Opcode, EVT VT, const SDLoc &dl, SDValue LHS, SDValue RHS, SmallVectorImpl< SDValue > &Result, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const
	Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes, respectively, each computing an n/2-bit part of the result.

bool	expandMUL (SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, MulExpansionKind Kind, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const
	Expand a MUL into two nodes.

bool	expandDIVREMByConstant (SDNode *N, SmallVectorImpl< SDValue > &Result, EVT HiLoVT, SelectionDAG &DAG, SDValue LL=SDValue(), SDValue LH=SDValue()) const
	Attempt to expand an n-bit div/rem/divrem by constant using a n/2-bit urem by constant and other arithmetic ops.

SDValue	expandFunnelShift (SDNode *N, SelectionDAG &DAG) const
	Expand funnel shift.

SDValue	expandROT (SDNode *N, bool AllowVectorOps, SelectionDAG &DAG) const
	Expand rotations.

void	expandShiftParts (SDNode *N, SDValue &Lo, SDValue &Hi, SelectionDAG &DAG) const
	Expand shift-by-parts.

bool	expandFP_TO_SINT (SDNode *N, SDValue &Result, SelectionDAG &DAG) const
	Expand float(f32) to SINT(i64) conversion.

bool	expandFP_TO_UINT (SDNode *N, SDValue &Result, SDValue &Chain, SelectionDAG &DAG) const
	Expand float to UINT conversion.

bool	expandUINT_TO_FP (SDNode *N, SDValue &Result, SDValue &Chain, SelectionDAG &DAG) const
	Expand UINT(i64) to double(f64) conversion.

SDValue	expandFMINNUM_FMAXNUM (SDNode *N, SelectionDAG &DAG) const
	Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs.

SDValue	expandFMINIMUM_FMAXIMUM (SDNode *N, SelectionDAG &DAG) const
	Expand fminimum/fmaximum into multiple comparison with selects.

SDValue	expandFMINIMUMNUM_FMAXIMUMNUM (SDNode *N, SelectionDAG &DAG) const
	Expand fminimumnum/fmaximumnum into multiple comparison with selects.

SDValue	expandFP_TO_INT_SAT (SDNode *N, SelectionDAG &DAG) const
	Expand FP_TO_[US]INT_SAT into FP_TO_[US]INT and selects or min/max.

SDValue	expandRoundInexactToOdd (EVT ResultVT, SDValue Op, const SDLoc &DL, SelectionDAG &DAG) const
	Truncate Op to ResultVT.

SDValue	expandFP_ROUND (SDNode *Node, SelectionDAG &DAG) const
	Expand round(fp) to fp conversion.

SDValue	expandIS_FPCLASS (EVT ResultVT, SDValue Op, FPClassTest Test, SDNodeFlags Flags, const SDLoc &DL, SelectionDAG &DAG) const
	Expand check for floating point class.

SDValue	expandCTPOP (SDNode *N, SelectionDAG &DAG) const
	Expand CTPOP nodes.

SDValue	expandVPCTPOP (SDNode *N, SelectionDAG &DAG) const
	Expand VP_CTPOP nodes.

SDValue	expandCTLZ (SDNode *N, SelectionDAG &DAG) const
	Expand CTLZ/CTLZ_ZERO_UNDEF nodes.

SDValue	expandVPCTLZ (SDNode *N, SelectionDAG &DAG) const
	Expand VP_CTLZ/VP_CTLZ_ZERO_UNDEF nodes.

SDValue	CTTZTableLookup (SDNode *N, SelectionDAG &DAG, const SDLoc &DL, EVT VT, SDValue Op, unsigned NumBitsPerElt) const
	Expand CTTZ via Table Lookup.

SDValue	expandCTTZ (SDNode *N, SelectionDAG &DAG) const
	Expand CTTZ/CTTZ_ZERO_UNDEF nodes.

SDValue	expandVPCTTZ (SDNode *N, SelectionDAG &DAG) const
	Expand VP_CTTZ/VP_CTTZ_ZERO_UNDEF nodes.

SDValue	expandVPCTTZElements (SDNode *N, SelectionDAG &DAG) const
	Expand VP_CTTZ_ELTS/VP_CTTZ_ELTS_ZERO_UNDEF nodes.

SDValue	expandABS (SDNode *N, SelectionDAG &DAG, bool IsNegative=false) const
	Expand ABS nodes.

SDValue	expandABD (SDNode *N, SelectionDAG &DAG) const
	Expand ABDS/ABDU nodes.

SDValue	expandAVG (SDNode *N, SelectionDAG &DAG) const
	Expand vector/scalar AVGCEILS/AVGCEILU/AVGFLOORS/AVGFLOORU nodes.

SDValue	expandBSWAP (SDNode *N, SelectionDAG &DAG) const
	Expand BSWAP nodes.

SDValue	expandVPBSWAP (SDNode *N, SelectionDAG &DAG) const
	Expand VP_BSWAP nodes.

SDValue	expandBITREVERSE (SDNode *N, SelectionDAG &DAG) const
	Expand BITREVERSE nodes.

SDValue	expandVPBITREVERSE (SDNode *N, SelectionDAG &DAG) const
	Expand VP_BITREVERSE nodes.

std::pair< SDValue, SDValue >	scalarizeVectorLoad (LoadSDNode *LD, SelectionDAG &DAG) const
	Turn load of vector type into a load of the individual elements.

SDValue	scalarizeVectorStore (StoreSDNode *ST, SelectionDAG &DAG) const

std::pair< SDValue, SDValue >	expandUnalignedLoad (LoadSDNode *LD, SelectionDAG &DAG) const
	Expands an unaligned load to 2 half-size loads for an integer, and possibly more for vectors.

SDValue	expandUnalignedStore (StoreSDNode *ST, SelectionDAG &DAG) const
	Expands an unaligned store to 2 half-size stores for integer values, and possibly more for vectors.

SDValue	IncrementMemoryAddress (SDValue Addr, SDValue Mask, const SDLoc &DL, EVT DataVT, SelectionDAG &DAG, bool IsCompressedMemory) const
	Increments memory address `Addr` according to the type of the value `DataVT` that should be stored.

SDValue	getVectorElementPointer (SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, SDValue Index) const
	Get a pointer to vector element `Idx` located in memory for a vector of type `VecVT` starting at a base address of `VecPtr`.

SDValue	getVectorSubVecPointer (SelectionDAG &DAG, SDValue VecPtr, EVT VecVT, EVT SubVecVT, SDValue Index) const
	Get a pointer to a sub-vector of type `SubVecVT` at index `Idx` located in memory for a vector of type `VecVT` starting at a base address of `VecPtr`.

SDValue	expandIntMINMAX (SDNode *Node, SelectionDAG &DAG) const
	Method for building the DAG expansion of ISD::[US][MIN\|MAX].

SDValue	expandAddSubSat (SDNode *Node, SelectionDAG &DAG) const
	Method for building the DAG expansion of ISD::[US][ADD\|SUB]SAT.

SDValue	expandCMP (SDNode *Node, SelectionDAG &DAG) const
	Method for building the DAG expansion of ISD::[US]CMP.

SDValue	expandShlSat (SDNode *Node, SelectionDAG &DAG) const
	Method for building the DAG expansion of ISD::[US]SHLSAT.

SDValue	expandFixedPointMul (SDNode *Node, SelectionDAG &DAG) const
	Method for building the DAG expansion of ISD::[U\|S]MULFIX[SAT].

SDValue	expandFixedPointDiv (unsigned Opcode, const SDLoc &dl, SDValue LHS, SDValue RHS, unsigned Scale, SelectionDAG &DAG) const
	Method for building the DAG expansion of ISD::[US]DIVFIX[SAT].

void	expandUADDSUBO (SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const
	Method for building the DAG expansion of ISD::U(ADD\|SUB)O.

void	expandSADDSUBO (SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const
	Method for building the DAG expansion of ISD::S(ADD\|SUB)O.

bool	expandMULO (SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const
	Method for building the DAG expansion of ISD::[US]MULO.

void	forceExpandWideMUL (SelectionDAG &DAG, const SDLoc &dl, bool Signed, EVT WideVT, const SDValue LL, const SDValue LH, const SDValue RL, const SDValue RH, SDValue &Lo, SDValue &Hi) const
	forceExpandWideMUL - Unconditionally expand a MUL into either a libcall or brute force via a wide multiplication.

void	forceExpandWideMUL (SelectionDAG &DAG, const SDLoc &dl, bool Signed, const SDValue LHS, const SDValue RHS, SDValue &Lo, SDValue &Hi) const
	Same as above, but creates the upper halves of each operand by sign/zero-extending the operands.

SDValue	expandVecReduce (SDNode *Node, SelectionDAG &DAG) const
	Expand a VECREDUCE_* into an explicit calculation.

SDValue	expandVecReduceSeq (SDNode *Node, SelectionDAG &DAG) const
	Expand a VECREDUCE_SEQ_* into an explicit ordered calculation.

bool	expandREM (SDNode *Node, SDValue &Result, SelectionDAG &DAG) const
	Expand an SREM or UREM using SDIV/UDIV or SDIVREM/UDIVREM, if legal.

SDValue	expandVectorSplice (SDNode *Node, SelectionDAG &DAG) const
	Method for building the DAG expansion of ISD::VECTOR_SPLICE.

SDValue	expandVECTOR_COMPRESS (SDNode *Node, SelectionDAG &DAG) const
	Expand a vector VECTOR_COMPRESS into a sequence of extract element, store temporarily, advance store position, before re-loading the final vector.

bool	LegalizeSetCCCondCode (SelectionDAG &DAG, EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, SDValue Mask, SDValue EVL, bool &NeedInvert, const SDLoc &dl, SDValue &Chain, bool IsSignaling=false) const
	Legalize a SETCC or VP_SETCC with given LHS and RHS and condition code CC on the current target.

virtual MachineBasicBlock *	EmitInstrWithCustomInserter (MachineInstr &MI, MachineBasicBlock *MBB) const
	This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag.

virtual void	AdjustInstrPostInstrSelection (MachineInstr &MI, SDNode *Node) const
	This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.

virtual bool	useLoadStackGuardNode (const Module &M) const
	If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.

virtual SDValue	emitStackGuardXorFP (SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const

virtual SDValue	LowerToTLSEmulatedModel (const GlobalAddressSDNode *GA, SelectionDAG &DAG) const
	Lower TLS global address SDNode for target independent emulated TLS model.

virtual SDValue	expandIndirectJTBranch (const SDLoc &dl, SDValue Value, SDValue Addr, int JTI, SelectionDAG &DAG) const
	Expands target specific indirect branch for the case of JumpTable expansion.

SDValue	lowerCmpEqZeroToCtlzSrl (SDValue Op, SelectionDAG &DAG) const

virtual bool	isXAndYEqZeroPreferableToXAndYEqY (ISD::CondCode, EVT) const

SDValue	expandVectorNaryOpBySplitting (SDNode *Node, SelectionDAG &DAG) const

Public Member Functions inherited from llvm::TargetLoweringBase
virtual void	markLibCallAttributes (MachineFunction *MF, unsigned CC, ArgListTy &Args) const

	TargetLoweringBase (const TargetMachine &TM)
	NOTE: The TargetMachine owns TLOF.

	TargetLoweringBase (const TargetLoweringBase &)=delete

TargetLoweringBase &	operator= (const TargetLoweringBase &)=delete

virtual	~TargetLoweringBase ()=default

bool	isStrictFPEnabled () const
	Return true if the target support strict float operation.

const TargetMachine &	getTargetMachine () const

virtual bool	useSoftFloat () const

virtual MVT	getPointerTy (const DataLayout &DL, uint32_t AS=0) const
	Return the pointer type for the given address space, defaults to the pointer type from the data layout.

virtual MVT	getPointerMemTy (const DataLayout &DL, uint32_t AS=0) const
	Return the in-memory pointer type for the given address space, defaults to the pointer type from the data layout.

MVT	getFrameIndexTy (const DataLayout &DL) const
	Return the type for frame index, which is determined by the alloca address space specified through the data layout.

MVT	getProgramPointerTy (const DataLayout &DL) const
	Return the type for code pointers, which is determined by the program address space specified through the data layout.

virtual MVT	getFenceOperandTy (const DataLayout &DL) const
	Return the type for operands of fence.

virtual MVT	getScalarShiftAmountTy (const DataLayout &, EVT) const
	Return the type to use for a scalar shift opcode, given the shifted amount type.

EVT	getShiftAmountTy (EVT LHSTy, const DataLayout &DL) const
	Returns the type for the shift amount of a shift opcode.

virtual LLVM_READONLY LLT	getPreferredShiftAmountTy (LLT ShiftValueTy) const
	Return the preferred type to use for a shift opcode, given the shifted amount type is `ShiftValueTy`.

virtual MVT	getVectorIdxTy (const DataLayout &DL) const
	Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR.

virtual MVT	getVPExplicitVectorLengthTy () const
	Returns the type to be used for the EVL/AVL operand of VP nodes: ISD::VP_ADD, ISD::VP_SUB, etc.

virtual MachineMemOperand::Flags	getTargetMMOFlags (const Instruction &I) const
	This callback is used to inspect load/store instructions and add target-specific MachineMemOperand flags to them.

virtual MachineMemOperand::Flags	getTargetMMOFlags (const MemSDNode &Node) const
	This callback is used to inspect load/store SDNode.

MachineMemOperand::Flags	getLoadMemOperandFlags (const LoadInst &LI, const DataLayout &DL, AssumptionCache AC=nullptr, const TargetLibraryInfo LibInfo=nullptr) const

MachineMemOperand::Flags	getStoreMemOperandFlags (const StoreInst &SI, const DataLayout &DL) const

MachineMemOperand::Flags	getAtomicMemOperandFlags (const Instruction &AI, const DataLayout &DL) const

virtual bool	isSelectSupported (SelectSupportKind) const

virtual bool	shouldExpandPartialReductionIntrinsic (const IntrinsicInst *I) const
	Return true if the @llvm.experimental.vector.partial.reduce.

virtual bool	shouldExpandGetActiveLaneMask (EVT VT, EVT OpVT) const
	Return true if the @llvm.get.active.lane.mask intrinsic should be expanded using generic code in SelectionDAGBuilder.

virtual bool	shouldExpandGetVectorLength (EVT CountVT, unsigned VF, bool IsScalable) const

virtual bool	shouldExpandCttzElements (EVT VT) const
	Return true if the @llvm.experimental.cttz.elts intrinsic should be expanded using generic code in SelectionDAGBuilder.

unsigned	getBitWidthForCttzElements (Type RetTy, ElementCount EC, bool ZeroIsPoison, const ConstantRange VScaleRange) const
	Return the minimum number of bits required to hold the maximum possible number of trailing zero vector elements.

virtual bool	shouldExpandVectorMatch (EVT VT, unsigned SearchSize) const
	Return true if the @llvm.experimental.vector.match intrinsic should be expanded for vector type ‘VT’ and search size ‘SearchSize’ using generic code in SelectionDAGBuilder.

virtual bool	shouldReassociateReduction (unsigned RedOpc, EVT VT) const

virtual bool	reduceSelectOfFPConstantLoads (EVT CmpOpVT) const
	Return true if it is profitable to convert a select of FP constants into a constant pool load whose address depends on the select condition.

bool	hasMultipleConditionRegisters () const
	Return true if multiple condition registers are available.

bool	hasExtractBitsInsn () const
	Return true if the target has BitExtract instructions.

virtual TargetLoweringBase::LegalizeTypeAction	getPreferredVectorAction (MVT VT) const
	Return the preferred vector type legalization action.

virtual bool	softPromoteHalfType () const

virtual bool	useFPRegsForHalfType () const

virtual bool	shouldExpandBuildVectorWithShuffles (EVT, unsigned DefinedValues) const

virtual bool	isIntDivCheap (EVT VT, AttributeList Attr) const
	Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.

virtual bool	hasStandaloneRem (EVT VT) const
	Return true if the target can handle a standalone remainder operation.

virtual bool	isFsqrtCheap (SDValue X, SelectionDAG &DAG) const
	Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).

int	getRecipEstimateSqrtEnabled (EVT VT, MachineFunction &MF) const
	Return a ReciprocalEstimate enum value for a square root of the given type based on the function's attributes.

int	getRecipEstimateDivEnabled (EVT VT, MachineFunction &MF) const
	Return a ReciprocalEstimate enum value for a division of the given type based on the function's attributes.

int	getSqrtRefinementSteps (EVT VT, MachineFunction &MF) const
	Return the refinement step count for a square root of the given type based on the function's attributes.

int	getDivRefinementSteps (EVT VT, MachineFunction &MF) const
	Return the refinement step count for a division of the given type based on the function's attributes.

bool	isSlowDivBypassed () const
	Returns true if target has indicated at least one type should be bypassed.

const DenseMap< unsigned int, unsigned int > &	getBypassSlowDivWidths () const
	Returns map of slow types for division or remainder with corresponding fast types.

virtual bool	isVScaleKnownToBeAPowerOfTwo () const
	Return true only if vscale must be a power of two.

bool	isJumpExpensive () const
	Return true if Flow Control is an expensive operation that should be avoided.

virtual CondMergingParams	getJumpConditionMergingParams (Instruction::BinaryOps, const Value , const Value ) const

bool	isPredictableSelectExpensive () const
	Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right.

virtual bool	fallBackToDAGISel (const Instruction &Inst) const

virtual bool	isLoadBitCastBeneficial (EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const
	Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner.

virtual bool	isStoreBitCastBeneficial (EVT StoreVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const
	Return true if the following transform is beneficial: (store (y (conv x)), y)) -> (store x, (x))

virtual bool	storeOfVectorConstantIsCheap (bool IsZero, EVT MemVT, unsigned NumElem, unsigned AddrSpace) const
	Return true if it is expected to be cheaper to do a store of vector constant with the given size and type for the address space than to store the individual scalar element constants.

virtual bool	mergeStoresAfterLegalization (EVT MemVT) const
	Allow store merging for the specified type after legalization in addition to before legalization.

virtual bool	canMergeStoresTo (unsigned AS, EVT MemVT, const MachineFunction &MF) const
	Returns if it's reasonable to merge stores to MemVT size.

virtual bool	isCheapToSpeculateCttz (Type *Ty) const
	Return true if it is cheap to speculate a call to intrinsic cttz.

virtual bool	isCheapToSpeculateCtlz (Type *Ty) const
	Return true if it is cheap to speculate a call to intrinsic ctlz.

virtual bool	isCtlzFast () const
	Return true if ctlz instruction is fast.

virtual bool	isCtpopFast (EVT VT) const
	Return true if ctpop instruction is fast.

virtual unsigned	getCustomCtpopCost (EVT VT, ISD::CondCode Cond) const
	Return the maximum number of "x & (x - 1)" operations that can be done instead of deferring to a custom CTPOP.

virtual bool	isEqualityCmpFoldedWithSignedCmp () const
	Return true if instruction generated for equality comparison is folded with instruction generated for signed comparison.

virtual bool	preferZeroCompareBranch () const
	Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.

virtual bool	isMultiStoresCheaperThanBitsMerge (EVT LTy, EVT HTy) const
	Return true if it is cheaper to split the store of a merged int val from a pair of smaller values into multiple stores.

virtual bool	isMaskAndCmp0FoldingBeneficial (const Instruction &AndI) const
	Return if the target supports combining a chain like:

virtual bool	areTwoSDNodeTargetMMOFlagsMergeable (const MemSDNode &NodeX, const MemSDNode &NodeY) const
	Return true if it is valid to merge the TargetMMOFlags in two SDNodes.

virtual bool	convertSetCCLogicToBitwiseLogic (EVT VT) const
	Use bitwise logic to make pairs of compares more efficient.

virtual MVT	hasFastEqualityCompare (unsigned NumBits) const
	Return the preferred operand type if the target has a quick way to compare integer values of the given size.

virtual bool	hasAndNotCompare (SDValue Y) const
	Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) != 0.

virtual bool	hasAndNot (SDValue X) const
	Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify select or other instructions.

virtual bool	hasBitTest (SDValue X, SDValue Y) const
	Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be used to prevent breaking the pattern, or creating it if it could be recognized.

virtual bool	shouldFoldMaskToVariableShiftPair (SDValue X) const
	There are two ways to clear extreme bits (either low or high): Mask: x & (-1 << y) (the instcombine canonical form) Shifts: x >> y << y Return true if the variant with 2 variable shifts is preferred.

virtual bool	shouldFoldConstantShiftPairToMask (const SDNode *N, CombineLevel Level) const
	Return true if it is profitable to fold a pair of shifts into a mask.

virtual bool	shouldTransformSignedTruncationCheck (EVT XVT, unsigned KeptBits) const
	Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be truncating or not: (add x, (1 << (KeptBits-1))) srccond (1 << KeptBits) Into it's more traditional form: ((x << C) a>> C) dstcond x Return true if we should transform.

virtual bool	shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd (SDValue X, ConstantSDNode XC, ConstantSDNode CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const
	Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <</l>> Y) & C) ==/!= 0 WARNING: if 'X' is a constant, the fold may deadlock! FIXME: we could avoid passing XC, but we can't use isConstOrConstSplat() here because it can end up being not linked in.

virtual bool	optimizeFMulOrFDivAsShiftAddBitcast (SDNode *N, SDValue FPConst, SDValue IntPow2) const

virtual unsigned	preferedOpcodeForCmpEqPiecesOfOperand (EVT VT, unsigned ShiftOpc, bool MayTransformRotate, const APInt &ShiftOrRotateAmt, const std::optional< APInt > &AndMask) const

virtual bool	preferIncOfAddToSubOfNot (EVT VT) const
	These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR-canonical.

virtual bool	preferABDSToABSWithNSW (EVT VT) const

virtual bool	preferScalarizeSplat (SDNode *N) const

virtual bool	preferSextInRegOfTruncate (EVT TruncVT, EVT VT, EVT ExtVT) const

bool	enableExtLdPromotion () const
	Return true if the target wants to use the optimization that turns ext(promotableInst1(...(promotableInstN(load)))) into promotedInst1(...(promotedInstN(ext(load)))).

virtual bool	canCombineStoreAndExtract (Type VectorTy, Value Idx, unsigned &Cost) const
	Return true if the target can combine store(extractelement VectorTy, Idx).

virtual bool	shallExtractConstSplatVectorElementToStore (Type *VectorTy, unsigned ElemSizeInBits, unsigned &Index) const
	Return true if the target shall perform extract vector element and store given that the vector is known to be splat of constant.

virtual bool	shouldSplatInsEltVarIndex (EVT) const
	Return true if inserting a scalar into a variable element of an undef vector is more efficiently handled by splatting the scalar instead.

virtual bool	enableAggressiveFMAFusion (EVT VT) const
	Return true if target always benefits from combining into FMA for a given value type.

virtual bool	enableAggressiveFMAFusion (LLT Ty) const
	Return true if target always benefits from combining into FMA for a given value type.

virtual EVT	getSetCCResultType (const DataLayout &DL, LLVMContext &Context, EVT VT) const
	Return the ValueType of the result of SETCC operations.

virtual MVT::SimpleValueType	getCmpLibcallReturnType () const
	Return the ValueType for comparison libcalls.

BooleanContent	getBooleanContents (bool isVec, bool isFloat) const
	For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1.

BooleanContent	getBooleanContents (EVT Type) const

SDValue	promoteTargetBoolean (SelectionDAG &DAG, SDValue Bool, EVT ValVT) const
	Promote the given target boolean to a target boolean of the given type.

Sched::Preference	getSchedulingPreference () const
	Return target scheduling preference.

virtual Sched::Preference	getSchedulingPreference (SDNode *) const
	Some scheduler, e.g.

virtual const TargetRegisterClass *	getRegClassFor (MVT VT, bool isDivergent=false) const
	Return the register class that should be used for the specified value type.

virtual bool	requiresUniformRegister (MachineFunction &MF, const Value *) const
	Allows target to decide about the register class of the specific value that is live outside the defining block.

virtual const TargetRegisterClass *	getRepRegClassFor (MVT VT) const
	Return the 'representative' register class for the specified value type.

virtual uint8_t	getRepRegClassCostFor (MVT VT) const
	Return the cost of the 'representative' register class for the specified value type.

virtual ShiftLegalizationStrategy	preferredShiftLegalizationStrategy (SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const

bool	isTypeLegal (EVT VT) const
	Return true if the target has native support for the specified value type.

const ValueTypeActionImpl &	getValueTypeActions () const

LegalizeKind	getTypeConversion (LLVMContext &Context, EVT VT) const
	Return pair that represents the legalization kind (first) that needs to happen to EVT (second) in order to type-legalize it.

LegalizeTypeAction	getTypeAction (LLVMContext &Context, EVT VT) const
	Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand').

LegalizeTypeAction	getTypeAction (MVT VT) const

virtual EVT	getTypeToTransformTo (LLVMContext &Context, EVT VT) const
	For types supported by the target, this is an identity function.

EVT	getTypeToExpandTo (LLVMContext &Context, EVT VT) const
	For types supported by the target, this is an identity function.

unsigned	getVectorTypeBreakdown (LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
	Vector types are broken down into some number of legal first class types.

virtual unsigned	getVectorTypeBreakdownForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
	Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts.

virtual bool	getTgtMemIntrinsic (IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const
	Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory).

virtual bool	isFPImmLegal (const APFloat &, EVT, bool ForCodeSize=false) const
	Returns true if the target can instruction select the specified FP immediate natively.

virtual bool	isShuffleMaskLegal (ArrayRef< int >, EVT) const
	Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.

virtual bool	canOpTrap (unsigned Op, EVT VT) const
	Returns true if the operation can trap for the value type.

virtual bool	isVectorClearMaskLegal (ArrayRef< int >, EVT) const
	Similar to isShuffleMaskLegal.

virtual LegalizeAction	getCustomOperationAction (SDNode &Op) const
	How to legalize this custom operation?

LegalizeAction	getOperationAction (unsigned Op, EVT VT) const
	Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

virtual bool	isSupportedFixedPointOperation (unsigned Op, EVT VT, unsigned Scale) const
	Custom method defined by each target to indicate if an operation which may require a scale is supported natively by the target.

LegalizeAction	getFixedPointOperationAction (unsigned Op, EVT VT, unsigned Scale) const
	Some fixed point operations may be natively supported by the target but only for specific scales.

LegalizeAction	getStrictFPOperationAction (unsigned Op, EVT VT) const

bool	isOperationLegalOrCustom (unsigned Op, EVT VT, bool LegalOnly=false) const
	Return true if the specified operation is legal on this target or can be made legal with custom lowering.

bool	isOperationLegalOrPromote (unsigned Op, EVT VT, bool LegalOnly=false) const
	Return true if the specified operation is legal on this target or can be made legal using promotion.

bool	isOperationLegalOrCustomOrPromote (unsigned Op, EVT VT, bool LegalOnly=false) const
	Return true if the specified operation is legal on this target or can be made legal with custom lowering or using promotion.

bool	isOperationCustom (unsigned Op, EVT VT) const
	Return true if the operation uses custom lowering, regardless of whether the type is legal or not.

virtual bool	areJTsAllowed (const Function *Fn) const
	Return true if lowering to a jump table is allowed.

bool	rangeFitsInWord (const APInt &Low, const APInt &High, const DataLayout &DL) const
	Check whether the range [Low,High] fits in a machine word.

virtual bool	isSuitableForJumpTable (const SwitchInst SI, uint64_t NumCases, uint64_t Range, ProfileSummaryInfo PSI, BlockFrequencyInfo *BFI) const
	Return true if lowering to a jump table is suitable for a set of case clusters which may contain `NumCases` cases, `Range` range of values.

virtual MVT	getPreferredSwitchConditionType (LLVMContext &Context, EVT ConditionVT) const
	Returns preferred type for switch condition.

bool	isSuitableForBitTests (unsigned NumDests, unsigned NumCmps, const APInt &Low, const APInt &High, const DataLayout &DL) const
	Return true if lowering to a bit test is suitable for a set of case clusters which contains `NumDests` unique destinations, `Low` and `High` as its lowest and highest case values, and expects `NumCmps` case value comparisons.

bool	isOperationExpand (unsigned Op, EVT VT) const
	Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering.

bool	isOperationLegal (unsigned Op, EVT VT) const
	Return true if the specified operation is legal on this target.

LegalizeAction	getLoadExtAction (unsigned ExtType, EVT ValVT, EVT MemVT) const
	Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

bool	isLoadExtLegal (unsigned ExtType, EVT ValVT, EVT MemVT) const
	Return true if the specified load with extension is legal on this target.

bool	isLoadExtLegalOrCustom (unsigned ExtType, EVT ValVT, EVT MemVT) const
	Return true if the specified load with extension is legal or custom on this target.

LegalizeAction	getAtomicLoadExtAction (unsigned ExtType, EVT ValVT, EVT MemVT) const
	Same as getLoadExtAction, but for atomic loads.

bool	isAtomicLoadExtLegal (unsigned ExtType, EVT ValVT, EVT MemVT) const
	Return true if the specified atomic load with extension is legal on this target.

LegalizeAction	getTruncStoreAction (EVT ValVT, EVT MemVT) const
	Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

bool	isTruncStoreLegal (EVT ValVT, EVT MemVT) const
	Return true if the specified store with truncation is legal on this target.

bool	isTruncStoreLegalOrCustom (EVT ValVT, EVT MemVT) const
	Return true if the specified store with truncation has solution on this target.

virtual bool	canCombineTruncStore (EVT ValVT, EVT MemVT, bool LegalOnly) const

LegalizeAction	getIndexedLoadAction (unsigned IdxMode, MVT VT) const
	Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

bool	isIndexedLoadLegal (unsigned IdxMode, EVT VT) const
	Return true if the specified indexed load is legal on this target.

LegalizeAction	getIndexedStoreAction (unsigned IdxMode, MVT VT) const
	Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

bool	isIndexedStoreLegal (unsigned IdxMode, EVT VT) const
	Return true if the specified indexed load is legal on this target.

LegalizeAction	getIndexedMaskedLoadAction (unsigned IdxMode, MVT VT) const
	Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

bool	isIndexedMaskedLoadLegal (unsigned IdxMode, EVT VT) const
	Return true if the specified indexed load is legal on this target.

LegalizeAction	getIndexedMaskedStoreAction (unsigned IdxMode, MVT VT) const
	Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

bool	isIndexedMaskedStoreLegal (unsigned IdxMode, EVT VT) const
	Return true if the specified indexed load is legal on this target.

virtual bool	shouldExtendGSIndex (EVT VT, EVT &EltTy) const
	Returns true if the index type for a masked gather/scatter requires extending.

virtual bool	shouldRemoveExtendFromGSIndex (SDValue Extend, EVT DataVT) const

virtual bool	isLegalScaleForGatherScatter (uint64_t Scale, uint64_t ElemSize) const

LegalizeAction	getCondCodeAction (ISD::CondCode CC, MVT VT) const
	Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it.

bool	isCondCodeLegal (ISD::CondCode CC, MVT VT) const
	Return true if the specified condition code is legal for a comparison of the specified types on this target.

bool	isCondCodeLegalOrCustom (ISD::CondCode CC, MVT VT) const
	Return true if the specified condition code is legal or custom for a comparison of the specified types on this target.

MVT	getTypeToPromoteTo (unsigned Op, MVT VT) const
	If the action for this operation is to promote, this method returns the ValueType to promote to.

virtual EVT	getAsmOperandValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const

EVT	getValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
	Return the EVT corresponding to this LLVM type.

EVT	getMemValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const

MVT	getSimpleValueType (const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
	Return the MVT corresponding to this LLVM type. See getValueType.

virtual Align	getByValTypeAlignment (Type *Ty, const DataLayout &DL) const
	Returns the desired alignment for ByVal or InAlloca aggregate function arguments in the caller parameter area.

MVT	getRegisterType (MVT VT) const
	Return the type of registers that this ValueType will eventually require.

MVT	getRegisterType (LLVMContext &Context, EVT VT) const
	Return the type of registers that this ValueType will eventually require.

virtual unsigned	getNumRegisters (LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const
	Return the number of registers that this ValueType will eventually require.

virtual MVT	getRegisterTypeForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT) const
	Certain combinations of ABIs, Targets and features require that types are legal for some operations and not for other operations.

virtual unsigned	getNumRegistersForCallingConv (LLVMContext &Context, CallingConv::ID CC, EVT VT) const
	Certain targets require unusual breakdowns of certain types.

virtual Align	getABIAlignmentForCallingConv (Type *ArgTy, const DataLayout &DL) const
	Certain targets have context sensitive alignment requirements, where one type has the alignment requirement of another type.

virtual bool	ShouldShrinkFPConstant (EVT) const
	If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime.

virtual bool	shouldReduceLoadWidth (SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const
	Return true if it is profitable to reduce a load to a smaller type.

virtual bool	shouldRemoveRedundantExtend (SDValue Op) const
	Return true (the default) if it is profitable to remove a sext_inreg(x) where the sext is redundant, and use x directly.

bool	isPaddedAtMostSignificantBitsWhenStored (EVT VT) const
	Indicates if any padding is guaranteed to go at the most significant bits when storing the type to memory and the type size isn't equal to the store size.

bool	hasBigEndianPartOrdering (EVT VT, const DataLayout &DL) const
	When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first.

bool	hasTargetDAGCombine (ISD::NodeType NT) const
	If true, the target has custom DAG combine transformations that it can perform for the specified node.

unsigned	getGatherAllAliasesMaxDepth () const

virtual unsigned	getVaListSizeInBits (const DataLayout &DL) const
	Returns the size of the platform's va_list object.

unsigned	getMaxStoresPerMemset (bool OptSize) const
	Get maximum # of store operations permitted for llvm.memset.

unsigned	getMaxStoresPerMemcpy (bool OptSize) const
	Get maximum # of store operations permitted for llvm.memcpy.

virtual unsigned	getMaxGluedStoresPerMemcpy () const
	Get maximum # of store operations to be glued together.

unsigned	getMaxExpandSizeMemcmp (bool OptSize) const
	Get maximum # of load operations permitted for memcmp.

unsigned	getMaxStoresPerMemmove (bool OptSize) const
	Get maximum # of store operations permitted for llvm.memmove.

virtual bool	allowsMisalignedMemoryAccesses (EVT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *=nullptr) const
	Determine if the target supports unaligned memory accesses.

virtual bool	allowsMisalignedMemoryAccesses (LLT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *=nullptr) const
	LLT handling variant.

bool	allowsMemoryAccessForAlignment (LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const
	This function returns true if the memory access is aligned or if the target allows this specific unaligned memory access.

bool	allowsMemoryAccessForAlignment (LLVMContext &Context, const DataLayout &DL, EVT VT, const MachineMemOperand &MMO, unsigned *Fast=nullptr) const
	Return true if the memory access of this type is aligned or if the target allows this specific unaligned access for the given MachineMemOperand.

virtual bool	allowsMemoryAccess (LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const
	Return true if the target supports a memory access of this type for the given address space and alignment.

bool	allowsMemoryAccess (LLVMContext &Context, const DataLayout &DL, EVT VT, const MachineMemOperand &MMO, unsigned *Fast=nullptr) const
	Return true if the target supports a memory access of this type for the given MachineMemOperand.

bool	allowsMemoryAccess (LLVMContext &Context, const DataLayout &DL, LLT Ty, const MachineMemOperand &MMO, unsigned *Fast=nullptr) const
	LLT handling variant.

virtual EVT	getOptimalMemOpType (const MemOp &Op, const AttributeList &) const
	Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering.

virtual LLT	getOptimalMemOpLLT (const MemOp &Op, const AttributeList &) const
	LLT returning variant.

virtual bool	isSafeMemOpType (MVT) const
	Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline.

virtual unsigned	getMinimumJumpTableEntries () const
	Return lower limit for number of blocks in a jump table.

unsigned	getMinimumJumpTableDensity (bool OptForSize) const
	Return lower limit of the density in a jump table.

unsigned	getMaximumJumpTableSize () const
	Return upper limit for number of entries in a jump table.

virtual bool	isJumpTableRelative () const

Register	getStackPointerRegisterToSaveRestore () const
	If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.

virtual Register	getExceptionPointerRegister (const Constant *PersonalityFn) const
	If a physical register, this returns the register that receives the exception address on entry to an EH pad.

virtual Register	getExceptionSelectorRegister (const Constant *PersonalityFn) const
	If a physical register, this returns the register that receives the exception typeid on entry to a landing pad.

virtual bool	needsFixedCatchObjects () const

Align	getMinStackArgumentAlignment () const
	Return the minimum stack alignment of an argument.

Align	getMinFunctionAlignment () const
	Return the minimum function alignment.

Align	getPrefFunctionAlignment () const
	Return the preferred function alignment.

virtual Align	getPrefLoopAlignment (MachineLoop *ML=nullptr) const
	Return the preferred loop alignment.

virtual unsigned	getMaxPermittedBytesForAlignment (MachineBasicBlock *MBB) const
	Return the maximum amount of bytes allowed to be emitted when padding for alignment.

virtual bool	alignLoopsWithOptSize () const
	Should loops be aligned even when the function is marked OptSize (but not MinSize).

virtual Value *	getIRStackGuard (IRBuilderBase &IRB) const
	If the target has a standard location for the stack protector guard, returns the address of that location.

virtual void	insertSSPDeclarations (Module &M) const
	Inserts necessary declarations for SSP (stack protection) purpose.

virtual Value *	getSDagStackGuard (const Module &M) const
	Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nullptr.

virtual bool	useStackGuardXorFP () const
	If this function returns true, stack protection checks should XOR the frame pointer (or whichever pointer is used to address locals) into the stack guard value before checking it.

virtual Function *	getSSPStackGuardCheck (const Module &M) const
	If the target has a standard stack protection check function that performs validation and error handling, returns the function.

virtual Value *	getSafeStackPointerLocation (IRBuilderBase &IRB) const
	Returns the target-specific address of the unsafe stack pointer.

virtual bool	hasStackProbeSymbol (const MachineFunction &MF) const
	Returns the name of the symbol used to emit stack probes or the empty string if not applicable.

virtual bool	hasInlineStackProbe (const MachineFunction &MF) const

virtual StringRef	getStackProbeSymbolName (const MachineFunction &MF) const

virtual bool	isFreeAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const
	Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.

virtual bool	shouldAlignPointerArgs (CallInst *, unsigned &, Align &) const
	Return true if the pointer arguments to CI should be aligned by aligning the object whose address is being passed.

virtual void	emitAtomicCmpXchgNoStoreLLBalance (IRBuilderBase &Builder) const

virtual bool	shouldSignExtendTypeInLibCall (Type *Ty, bool IsSigned) const
	Returns true if arguments should be sign-extended in lib calls.

virtual bool	shouldExtendTypeInLibCall (EVT Type) const
	Returns true if arguments should be extended in lib calls.

virtual AtomicExpansionKind	shouldExpandAtomicLoadInIR (LoadInst *LI) const
	Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.

virtual AtomicExpansionKind	shouldCastAtomicLoadInIR (LoadInst *LI) const
	Returns how the given (atomic) load should be cast by the IR-level AtomicExpand pass.

virtual AtomicExpansionKind	shouldExpandAtomicStoreInIR (StoreInst *SI) const
	Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.

virtual AtomicExpansionKind	shouldCastAtomicStoreInIR (StoreInst *SI) const
	Returns how the given (atomic) store should be cast by the IR-level AtomicExpand pass into.

virtual AtomicExpansionKind	shouldExpandAtomicCmpXchgInIR (AtomicCmpXchgInst *AI) const
	Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.

virtual AtomicExpansionKind	shouldExpandAtomicRMWInIR (AtomicRMWInst *RMW) const
	Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.

virtual AtomicExpansionKind	shouldCastAtomicRMWIInIR (AtomicRMWInst *RMWI) const
	Returns how the given atomic atomicrmw should be cast by the IR-level AtomicExpand pass.

virtual LoadInst *	lowerIdempotentRMWIntoFencedLoad (AtomicRMWInst *RMWI) const
	On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can be turned into a fence followed by an atomic load.

virtual ISD::NodeType	getExtendForAtomicOps () const
	Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).

virtual ISD::NodeType	getExtendForAtomicCmpSwapArg () const
	Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_EXTEND, SIGN_EXTEND, or ANY_EXTEND).

virtual bool	shouldNormalizeToSelectSequence (LLVMContext &Context, EVT VT) const
	Returns true if we should normalize select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and select(N0\|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely that it saves us from materializing N0 and N1 in an integer register.

virtual bool	isProfitableToCombineMinNumMaxNum (EVT VT) const

virtual bool	convertSelectOfConstantsToMath (EVT VT) const
	Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops with the condition value.

virtual bool	decomposeMulByConstant (LLVMContext &Context, EVT VT, SDValue C) const
	Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds.

virtual bool	isMulAddWithConstProfitable (SDValue AddNode, SDValue ConstNode) const
	Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2).

virtual bool	shouldUseStrictFP_TO_INT (EVT FpVT, EVT IntVT, bool IsSigned) const
	Return true if it is more correct/profitable to use strict FP_TO_INT conversion operations - canonicalizing the FP source value instead of converting all cases and then selecting based on value.

bool	isBeneficialToExpandPowI (int64_t Exponent, bool OptForSize) const
	Return true if it is beneficial to expand an @llvm.powi.

virtual bool	getAddrModeArguments (IntrinsicInst , SmallVectorImpl< Value > &, Type *&) const
	CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address.

virtual bool	isLegalAddressingMode (const DataLayout &DL, const AddrMode &AM, Type Ty, unsigned AddrSpace, Instruction I=nullptr) const
	Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.

virtual bool	addressingModeSupportsTLS (const GlobalValue &) const
	Returns true if the targets addressing mode can target thread local storage (TLS).

virtual int64_t	getPreferredLargeGEPBaseOffset (int64_t MinOffset, int64_t MaxOffset) const
	Return the prefered common base offset.

virtual bool	isLegalICmpImmediate (int64_t) const
	Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.

virtual bool	isLegalAddImmediate (int64_t) const
	Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register with the immediate without having to materialize the immediate into a register.

virtual bool	isLegalAddScalableImmediate (int64_t) const
	Return true if adding the specified scalable immediate is legal, that is the target has add instructions which can add a register with the immediate (multiplied by vscale) without having to materialize the immediate into a register.

virtual bool	isLegalStoreImmediate (int64_t Value) const
	Return true if the specified immediate is legal for the value input of a store instruction.

virtual Type *	shouldConvertSplatType (ShuffleVectorInst *SVI) const
	Given a shuffle vector SVI representing a vector splat, return a new scalar type of size equal to SVI's scalar type if the new type is more profitable.

virtual bool	shouldConvertPhiType (Type From, Type To) const
	Given a set in interconnected phis of type 'From' that are loaded/stored or bitcast to type 'To', return true if the set should be converted to 'To'.

virtual bool	isCommutativeBinOp (unsigned Opcode) const
	Returns true if the opcode is a commutative binary operation.

virtual bool	isBinOp (unsigned Opcode) const
	Return true if the node is a math/logic binary operator.

virtual bool	isTruncateFree (Type FromTy, Type ToTy) const
	Return true if it's free to truncate a value of type FromTy to type ToTy.

virtual bool	allowTruncateForTailCall (Type FromTy, Type ToTy) const
	Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position.

virtual bool	isTruncateFree (EVT FromVT, EVT ToVT) const

virtual bool	isTruncateFree (LLT FromTy, LLT ToTy, LLVMContext &Ctx) const

virtual bool	isTruncateFree (SDValue Val, EVT VT2) const
	Return true if truncating the specific node Val to type VT2 is free.

virtual bool	isProfitableToHoist (Instruction *I) const

bool	isExtFree (const Instruction *I) const
	Return true if the extension represented by `I` is free.

bool	isExtLoad (const LoadInst Load, const Instruction Ext, const DataLayout &DL) const
	Return true if `Load` and `Ext` can form an ExtLoad.

virtual bool	isZExtFree (Type FromTy, Type ToTy) const
	Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the value to ToTy in the result register.

virtual bool	isZExtFree (EVT FromTy, EVT ToTy) const

virtual bool	isZExtFree (LLT FromTy, LLT ToTy, LLVMContext &Ctx) const

virtual bool	isZExtFree (SDValue Val, EVT VT2) const
	Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads).

virtual bool	isSExtCheaperThanZExt (EVT FromTy, EVT ToTy) const
	Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.

virtual bool	signExtendConstant (const ConstantInt *C) const
	Return true if this constant should be sign extended when promoting to a larger type.

virtual bool	optimizeExtendOrTruncateConversion (Instruction I, Loop L, const TargetTransformInfo &TTI) const
	Try to optimize extending or truncating conversion instructions (like zext, trunc, fptoui, uitofp) for the target.

virtual bool	hasPairedLoad (EVT, Align &) const
	Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory.

virtual bool	hasVectorBlend () const
	Return true if the target has a vector blend instruction.

virtual unsigned	getMaxSupportedInterleaveFactor () const
	Get the maximum supported factor for interleaved memory accesses.

virtual bool	lowerInterleavedLoad (LoadInst LI, ArrayRef< ShuffleVectorInst > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor) const
	Lower an interleaved load to target specific intrinsics.

virtual bool	lowerInterleavedStore (StoreInst SI, ShuffleVectorInst SVI, unsigned Factor) const
	Lower an interleaved store to target specific intrinsics.

virtual bool	lowerDeinterleaveIntrinsicToLoad (IntrinsicInst DI, LoadInst LI, SmallVectorImpl< Instruction * > &DeadInsts) const
	Lower a deinterleave intrinsic to a target specific load intrinsic.

virtual bool	lowerInterleaveIntrinsicToStore (IntrinsicInst II, StoreInst SI, SmallVectorImpl< Instruction * > &DeadInsts) const
	Lower an interleave intrinsic to a target specific store intrinsic.

virtual bool	isFPExtFree (EVT DestVT, EVT SrcVT) const
	Return true if an fpext operation is free (for instance, because single-precision floating-point numbers are implicitly extended to double-precision).

virtual bool	isFPExtFoldable (const MachineInstr &MI, unsigned Opcode, LLT DestTy, LLT SrcTy) const
	Return true if an fpext operation input to an `Opcode` operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.

virtual bool	isFPExtFoldable (const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, EVT SrcVT) const
	Return true if an fpext operation input to an `Opcode` operation is free (for instance, because half-precision floating-point numbers are implicitly extended to float-precision) for an FMA instruction.

virtual bool	isVectorLoadExtDesirable (SDValue ExtVal) const
	Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.

virtual bool	isFNegFree (EVT VT) const
	Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation.

virtual bool	isFAbsFree (EVT VT) const
	Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation.

virtual bool	isFMAFasterThanFMulAndFAdd (const MachineFunction &MF, EVT) const
	Return true if an FMA operation is faster than a pair of fmul and fadd instructions.

virtual bool	isFMAFasterThanFMulAndFAdd (const MachineFunction &MF, LLT) const
	Return true if an FMA operation is faster than a pair of fmul and fadd instructions.

virtual bool	isFMAFasterThanFMulAndFAdd (const Function &F, Type *) const
	IR version.

virtual bool	isFMADLegal (const MachineInstr &MI, LLT Ty) const
	Returns true if `MI` can be combined with another instruction to form TargetOpcode::G_FMAD.

virtual bool	isFMADLegal (const SelectionDAG &DAG, const SDNode *N) const
	Returns true if be combined with to form an ISD::FMAD.

virtual bool	generateFMAsInMachineCombiner (EVT VT, CodeGenOptLevel OptLevel) const

virtual bool	isNarrowingProfitable (SDNode *N, EVT SrcVT, EVT DestVT) const
	Return true if it's profitable to narrow operations of type SrcVT to DestVT.

virtual bool	shouldFoldSelectWithIdentityConstant (unsigned BinOpcode, EVT VT) const
	Return true if pulling a binary operation into a select with an identity constant is profitable.

virtual bool	shouldConvertConstantLoadToIntImm (const APInt &Imm, Type *Ty) const
	Return true if it is beneficial to convert a load of a constant to just the constant itself.

virtual bool	isExtractSubvectorCheap (EVT ResVT, EVT SrcVT, unsigned Index) const
	Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with this index.

virtual bool	shouldScalarizeBinop (SDValue VecOp) const
	Try to convert an extract element of a vector binary operation into an extract element followed by a scalar operation.

virtual bool	isExtractVecEltCheap (EVT VT, unsigned Index) const
	Return true if extraction of a scalar element from the given vector type at the given index is cheap.

virtual bool	shouldFormOverflowOp (unsigned Opcode, EVT VT, bool MathUsed) const
	Try to convert math with an overflow comparison into the corresponding DAG node operation.

virtual bool	aggressivelyPreferBuildVectorSources (EVT VecVT) const

virtual bool	shouldConsiderGEPOffsetSplit () const

virtual bool	shouldAvoidTransformToShift (EVT VT, unsigned Amount) const
	Return true if creating a shift of the type by the given amount is not profitable.

virtual bool	shouldFoldSelectWithSingleBitTest (EVT VT, const APInt &AndMask) const

virtual bool	shouldKeepZExtForFP16Conv () const
	Does this target require the clearing of high-order bits in a register passed to the fp16 to fp conversion library function.

virtual bool	shouldConvertFpToSat (unsigned Op, EVT FPVT, EVT VT) const
	Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) saturation patterns.

virtual bool	shouldExpandCmpUsingSelects (EVT VT) const
	Should we expand [US]CMP nodes using two selects and two compares, or by doing arithmetic on boolean types.

virtual bool	isComplexDeinterleavingSupported () const
	Does this target support complex deinterleaving.

virtual bool	isComplexDeinterleavingOperationSupported (ComplexDeinterleavingOperation Operation, Type *Ty) const
	Does this target support complex deinterleaving with the given operation and type.

virtual Value *	createComplexDeinterleavingIR (IRBuilderBase &B, ComplexDeinterleavingOperation OperationType, ComplexDeinterleavingRotation Rotation, Value InputA, Value InputB, Value *Accumulator=nullptr) const
	Create the IR node for the given complex deinterleaving operation.

void	setLibcallName (RTLIB::Libcall Call, const char *Name)
	Rename the default libcall routine name for the specified libcall.

void	setLibcallName (ArrayRef< RTLIB::Libcall > Calls, const char *Name)

const char *	getLibcallName (RTLIB::Libcall Call) const
	Get the libcall routine name for the specified libcall.

void	setCmpLibcallCC (RTLIB::Libcall Call, ISD::CondCode CC)
	Override the default CondCode to be used to test the result of the comparison libcall against zero.

ISD::CondCode	getCmpLibcallCC (RTLIB::Libcall Call) const
	Get the CondCode that's to be used to test the result of the comparison libcall against zero.

void	setLibcallCallingConv (RTLIB::Libcall Call, CallingConv::ID CC)
	Set the CallingConv that should be used for the specified libcall.

CallingConv::ID	getLibcallCallingConv (RTLIB::Libcall Call) const
	Get the CallingConv that should be used for the specified libcall.

virtual void	finalizeLowering (MachineFunction &MF) const
	Execute target specific actions to finalize target lowering.

virtual bool	shouldLocalize (const MachineInstr &MI, const TargetTransformInfo *TTI) const
	Check whether or not `MI` needs to be moved close to its uses.

int	InstructionOpcodeToISD (unsigned Opcode) const
	Get the ISD node that corresponds to the Instruction class opcode.

unsigned	getMaxAtomicSizeInBitsSupported () const
	Returns the maximum atomic operation size (in bits) supported by the backend.

unsigned	getMaxDivRemBitWidthSupported () const
	Returns the size in bits of the maximum div/rem the backend supports.

unsigned	getMaxLargeFPConvertBitWidthSupported () const
	Returns the size in bits of the maximum larget fp convert the backend supports.

unsigned	getMinCmpXchgSizeInBits () const
	Returns the size of the smallest cmpxchg or ll/sc instruction the backend supports.

bool	supportsUnalignedAtomics () const
	Whether the target supports unaligned atomic operations.

virtual bool	shouldInsertFencesForAtomic (const Instruction *I) const
	Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.

virtual bool	shouldInsertTrailingFenceForAtomicStore (const Instruction *I) const
	Whether AtomicExpandPass should automatically insert a trailing fence without reducing the ordering for this atomic.

virtual Value *	emitLoadLinked (IRBuilderBase &Builder, Type ValueTy, Value Addr, AtomicOrdering Ord) const
	Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.

virtual Value *	emitStoreConditional (IRBuilderBase &Builder, Value Val, Value Addr, AtomicOrdering Ord) const
	Perform a store-conditional operation to Addr.

virtual Value *	emitMaskedAtomicRMWIntrinsic (IRBuilderBase &Builder, AtomicRMWInst AI, Value AlignedAddr, Value Incr, Value Mask, Value *ShiftAmt, AtomicOrdering Ord) const
	Perform a masked atomicrmw using a target-specific intrinsic.

virtual void	emitExpandAtomicRMW (AtomicRMWInst *AI) const
	Perform a atomicrmw expansion using a target-specific way.

virtual void	emitExpandAtomicCmpXchg (AtomicCmpXchgInst *CI) const
	Perform a cmpxchg expansion using a target-specific method.

virtual void	emitBitTestAtomicRMWIntrinsic (AtomicRMWInst *AI) const
	Perform a bit test atomicrmw using a target-specific intrinsic.

virtual void	emitCmpArithAtomicRMWIntrinsic (AtomicRMWInst *AI) const
	Perform a atomicrmw which the result is only used by comparison, using a target-specific intrinsic.

virtual Value *	emitMaskedAtomicCmpXchgIntrinsic (IRBuilderBase &Builder, AtomicCmpXchgInst CI, Value AlignedAddr, Value CmpVal, Value NewVal, Value *Mask, AtomicOrdering Ord) const
	Perform a masked cmpxchg using a target-specific intrinsic.

virtual MachineInstr *	EmitKCFICheck (MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator &MBBI, const TargetInstrInfo *TII) const

virtual Instruction *	emitLeadingFence (IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const
	Inserts in the IR a target-specific intrinsic specifying a fence.

virtual Instruction *	emitTrailingFence (IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const

Additional Inherited Members
Static Public Member Functions inherited from llvm::TargetLoweringBase
static ISD::NodeType	getExtendForContent (BooleanContent Content)

Protected Member Functions inherited from llvm::TargetLoweringBase
void	initActions ()
	Initialize all of the actions to default values.

Value *	getDefaultSafeStackPointerLocation (IRBuilderBase &IRB, bool UseTLS) const

void	setBooleanContents (BooleanContent Ty)
	Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type.

void	setBooleanContents (BooleanContent IntTy, BooleanContent FloatTy)
	Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type.

void	setBooleanVectorContents (BooleanContent Ty)
	Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider type.

void	setSchedulingPreference (Sched::Preference Pref)
	Specify the target scheduling preference.

void	setMinimumJumpTableEntries (unsigned Val)
	Indicate the minimum number of blocks to generate jump tables.

void	setMaximumJumpTableSize (unsigned)
	Indicate the maximum number of entries in jump tables.

void	setStackPointerRegisterToSaveRestore (Register R)
	If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.

void	setHasMultipleConditionRegisters (bool hasManyRegs=true)
	Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches.

void	setHasExtractBitsInsn (bool hasExtractInsn=true)
	Tells the code generator that the target has BitExtract instructions.

void	setJumpIsExpensive (bool isExpensive=true)
	Tells the code generator not to expand logic operations on comparison predicates into separate sequences that increase the amount of flow control.

void	addBypassSlowDiv (unsigned int SlowBitWidth, unsigned int FastBitWidth)
	Tells the code generator which bitwidths to bypass.

void	addRegisterClass (MVT VT, const TargetRegisterClass *RC)
	Add the specified register class as an available regclass for the specified value type.

virtual std::pair< const TargetRegisterClass *, uint8_t >	findRepresentativeClass (const TargetRegisterInfo *TRI, MVT VT) const
	Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".

void	computeRegisterProperties (const TargetRegisterInfo *TRI)
	Once all of the register classes are added, this allows us to compute derived properties we expose.

void	setOperationAction (unsigned Op, MVT VT, LegalizeAction Action)
	Indicate that the specified operation does not work with the specified type and indicate what to do about it.

void	setOperationAction (ArrayRef< unsigned > Ops, MVT VT, LegalizeAction Action)

void	setOperationAction (ArrayRef< unsigned > Ops, ArrayRef< MVT > VTs, LegalizeAction Action)

void	setLoadExtAction (unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
	Indicate that the specified load with extension does not work with the specified type and indicate what to do about it.

void	setLoadExtAction (ArrayRef< unsigned > ExtTypes, MVT ValVT, MVT MemVT, LegalizeAction Action)

void	setLoadExtAction (ArrayRef< unsigned > ExtTypes, MVT ValVT, ArrayRef< MVT > MemVTs, LegalizeAction Action)

void	setAtomicLoadExtAction (unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
	Let target indicate that an extending atomic load of the specified type is legal.

void	setAtomicLoadExtAction (ArrayRef< unsigned > ExtTypes, MVT ValVT, MVT MemVT, LegalizeAction Action)

void	setAtomicLoadExtAction (ArrayRef< unsigned > ExtTypes, MVT ValVT, ArrayRef< MVT > MemVTs, LegalizeAction Action)

void	setTruncStoreAction (MVT ValVT, MVT MemVT, LegalizeAction Action)
	Indicate that the specified truncating store does not work with the specified type and indicate what to do about it.

void	setIndexedLoadAction (ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
	Indicate that the specified indexed load does or does not work with the specified type and indicate what to do abort it.

void	setIndexedLoadAction (ArrayRef< unsigned > IdxModes, ArrayRef< MVT > VTs, LegalizeAction Action)

void	setIndexedStoreAction (ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
	Indicate that the specified indexed store does or does not work with the specified type and indicate what to do about it.

void	setIndexedStoreAction (ArrayRef< unsigned > IdxModes, ArrayRef< MVT > VTs, LegalizeAction Action)

void	setIndexedMaskedLoadAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
	Indicate that the specified indexed masked load does or does not work with the specified type and indicate what to do about it.

void	setIndexedMaskedStoreAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
	Indicate that the specified indexed masked store does or does not work with the specified type and indicate what to do about it.

void	setCondCodeAction (ArrayRef< ISD::CondCode > CCs, MVT VT, LegalizeAction Action)
	Indicate that the specified condition code is or isn't supported on the target and indicate what to do about it.

void	setCondCodeAction (ArrayRef< ISD::CondCode > CCs, ArrayRef< MVT > VTs, LegalizeAction Action)

void	AddPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT)
	If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works.

void	setOperationPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT)
	Convenience method to set an operation to Promote and specify the type in a single call.

void	setOperationPromotedToType (ArrayRef< unsigned > Ops, MVT OrigVT, MVT DestVT)

void	setTargetDAGCombine (ArrayRef< ISD::NodeType > NTs)
	Targets should invoke this method for each target independent node that they want to provide a custom DAG combiner for by implementing the PerformDAGCombine virtual method.

void	setMinFunctionAlignment (Align Alignment)
	Set the target's minimum function alignment.

void	setPrefFunctionAlignment (Align Alignment)
	Set the target's preferred function alignment.

void	setPrefLoopAlignment (Align Alignment)
	Set the target's preferred loop alignment.

void	setMaxBytesForAlignment (unsigned MaxBytes)

void	setMinStackArgumentAlignment (Align Alignment)
	Set the minimum stack alignment of an argument.

void	setMaxAtomicSizeInBitsSupported (unsigned SizeInBits)
	Set the maximum atomic operation size supported by the backend.

void	setMaxDivRemBitWidthSupported (unsigned SizeInBits)
	Set the size in bits of the maximum div/rem the backend supports.

void	setMaxLargeFPConvertBitWidthSupported (unsigned SizeInBits)
	Set the size in bits of the maximum fp convert the backend supports.

void	setMinCmpXchgSizeInBits (unsigned SizeInBits)
	Sets the minimum cmpxchg or ll/sc size supported by the backend.

void	setSupportsUnalignedAtomics (bool UnalignedSupported)
	Sets whether unaligned atomic operations are supported.

virtual bool	isExtFreeImpl (const Instruction *I) const
	Return true if the extension represented by `I` is free.

bool	isLegalRC (const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const
	Return true if the value types that can be represented by the specified register class are all legal.

MachineBasicBlock *	emitPatchPoint (MachineInstr &MI, MachineBasicBlock *MBB) const
	Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter.

Protected Attributes inherited from llvm::TargetLoweringBase
unsigned	GatherAllAliasesMaxDepth
	Depth that GatherAllAliases should continue looking for chain dependencies when trying to find a more preferable chain.

unsigned	MaxStoresPerMemset
	Specify maximum number of store instructions per memset call.

unsigned	MaxStoresPerMemsetOptSize
	Likewise for functions with the OptSize attribute.

unsigned	MaxStoresPerMemcpy
	Specify maximum number of store instructions per memcpy call.

unsigned	MaxStoresPerMemcpyOptSize
	Likewise for functions with the OptSize attribute.

unsigned	MaxGluedStoresPerMemcpy = 0
	Specify max number of store instructions to glue in inlined memcpy.

unsigned	MaxLoadsPerMemcmp
	Specify maximum number of load instructions per memcmp call.

unsigned	MaxLoadsPerMemcmpOptSize
	Likewise for functions with the OptSize attribute.

unsigned	MaxStoresPerMemmove
	Specify maximum number of store instructions per memmove call.

unsigned	MaxStoresPerMemmoveOptSize
	Likewise for functions with the OptSize attribute.

bool	PredictableSelectIsExpensive
	Tells the code generator that select is more expensive than a branch if the branch is usually predicted right.

bool	EnableExtLdPromotion

bool	IsStrictFPEnabled

Detailed Description

This class defines information used to lower LLVM code to legal SelectionDAG operators that the target instruction selector can accept natively.

This class also defines callbacks that targets must implement to lower target-specific constructs to SelectionDAG operators.

Definition at line 3780 of file TargetLowering.h.

Member Typedef Documentation

◆ AsmOperandInfoVector

using llvm::TargetLowering::AsmOperandInfoVector = std::vector<AsmOperandInfo>

Definition at line 5008 of file TargetLowering.h.

◆ ConstraintGroup

using llvm::TargetLowering::ConstraintGroup = SmallVector<ConstraintPair>

Definition at line 5040 of file TargetLowering.h.

◆ ConstraintPair

using llvm::TargetLowering::ConstraintPair = std::pair<StringRef, TargetLowering::ConstraintType>

Definition at line 5039 of file TargetLowering.h.

Member Enumeration Documentation

◆ ConstraintType

enum llvm::TargetLowering::ConstraintType

Enumerator
C_Register
C_RegisterClass
C_Memory
C_Address
C_Immediate
C_Other
C_Unknown

Definition at line 4950 of file TargetLowering.h.

◆ ConstraintWeight

enum llvm::TargetLowering::ConstraintWeight

Enumerator
CW_Invalid
CW_Okay
CW_Good
CW_Better
CW_Best
CW_SpecificReg
CW_Register
CW_Memory
CW_Constant
CW_Default

Definition at line 4960 of file TargetLowering.h.

Constructor & Destructor Documentation

◆ TargetLowering() [1/2]

llvm::TargetLowering::TargetLowering ( const TargetLowering & )

delete

◆ TargetLowering() [2/2]

TargetLowering::TargetLowering ( const TargetMachine & TM )

explicit

NOTE: The TargetMachine owns TLOF.

Definition at line 39 of file TargetLowering.cpp.

Member Function Documentation

◆ AdjustInstrPostInstrSelection()

void TargetLowering::AdjustInstrPostInstrSelection	(	MachineInstr &	MI,
		SDNode *	Node
	)		const

virtual

This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.

These instructions must be adjusted after instruction selection by target hooks. e.g. To fill in optional defs for ARM 's' setting instructions.

Reimplemented in llvm::SITargetLowering, llvm::ARMTargetLowering, llvm::HexagonTargetLowering, llvm::MipsTargetLowering, llvm::RISCVTargetLowering, and llvm::SparcTargetLowering.

Definition at line 325 of file SelectionDAGISel.cpp.

References assert(), and MI.

◆ buildLegalVectorShuffle()

SDValue TargetLowering::buildLegalVectorShuffle	(	EVT	VT,
		const SDLoc &	DL,
		SDValue	N0,
		SDValue	N1,
		MutableArrayRef< int >	Mask,
		SelectionDAG &	DAG
	)		const

Tries to build a legal vector shuffle using the provided parameters or equivalent variations.

The Mask argument maybe be modified as the function tries different variations. Returns an empty SDValue if the operation fails.

Definition at line 3868 of file TargetLowering.cpp.

References llvm::ShuffleVectorSDNode::commuteMask(), DL, llvm::SelectionDAG::getVectorShuffle(), llvm::TargetLoweringBase::isShuffleMaskLegal(), and std::swap().

Referenced by combineConcatVectorOfExtracts(), and reduceBuildVecToShuffleWithZero().

◆ BuildSDIV()

SDValue TargetLowering::BuildSDIV	(	SDNode *	N,
		SelectionDAG &	DAG,
		bool	IsAfterLegalization,
		bool	IsAfterLegalTypes,
		SmallVectorImpl< SDNode * > &	Created
	)		const

Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number.

Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".

Definition at line 6332 of file TargetLowering.cpp.

◆ BuildSDIVPow2()

SDValue TargetLowering::BuildSDIVPow2	(	SDNode *	N,
		const APInt &	Divisor,
		SelectionDAG &	DAG,
		SmallVectorImpl< SDNode * > &	Created
	)		const

virtual

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators.

If the target returns an empty SDValue, LLVM assumes SDIV is expensive and replaces it with a series of other integer operations.

Reimplemented in llvm::PPCTargetLowering.

Definition at line 6266 of file TargetLowering.cpp.

References llvm::Function::getAttributes(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLoweringBase::isIntDivCheap(), and N.

◆ buildSDIVPow2WithCMov()

SDValue TargetLowering::buildSDIVPow2WithCMov	(	SDNode *	N,
		const APInt &	Divisor,
		SelectionDAG &	DAG,
		SmallVectorImpl< SDNode * > &	Created
	)		const

Build sdiv by power-of-2 with conditional move instructions Ref: "Hacker's Delight" by Henry Warren 10-1 If conditional move/branch is preferred, we lower sdiv x, +/-2**k into: bgez x, label add x, x, 2**k-1 label: sra res, x, k neg res, res (when the divisor is negative)

Definition at line 6293 of file TargetLowering.cpp.

References llvm::Add, llvm::ISD::ADD, llvm::APInt::countr_zero(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::APInt::getLowBitsSet(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSetCC(), llvm::TargetLoweringBase::getSetCCResultType(), llvm::EVT::getSizeInBits(), llvm::APInt::isNonNegative(), N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SELECT, llvm::ISD::SETLT, llvm::ISD::SRA, and llvm::ISD::SUB.

◆ BuildSREMPow2()

SDValue TargetLowering::BuildSREMPow2	(	SDNode *	N,
		const APInt &	Divisor,
		SelectionDAG &	DAG,
		SmallVectorImpl< SDNode * > &	Created
	)		const

virtual

Targets may override this function to provide custom SREM lowering for power-of-2 denominators.

If the target returns an empty SDValue, LLVM assumes SREM is expensive and replaces it with a series of other integer operations.

Definition at line 6276 of file TargetLowering.cpp.

References llvm::Function::getAttributes(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLoweringBase::isIntDivCheap(), and N.

◆ BuildUDIV()

SDValue TargetLowering::BuildUDIV	(	SDNode *	N,
		SelectionDAG &	DAG,
		bool	IsAfterLegalization,
		bool	IsAfterLegalTypes,
		SmallVectorImpl< SDNode * > &	Created
	)		const

Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number.

Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".

Definition at line 6500 of file TargetLowering.cpp.

◆ canCreateUndefOrPoisonForTargetNode()

bool TargetLowering::canCreateUndefOrPoisonForTargetNode	(	SDValue	Op,
		const APInt &	DemandedElts,
		const SelectionDAG &	DAG,
		bool	PoisonOnly,
		bool	ConsiderFlags,
		unsigned	Depth
	)		const

virtual

Return true if Op can create undef or poison from non-undef & non-poison operands.

The DemandedElts argument limits the check to the requested vector elements.

Reimplemented in llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 3909 of file TargetLowering.cpp.

References assert(), llvm::ISD::BUILTIN_OP_END, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, and llvm::ISD::INTRINSIC_WO_CHAIN.

Referenced by llvm::SelectionDAG::canCreateUndefOrPoison(), llvm::RISCVTargetLowering::canCreateUndefOrPoisonForTargetNode(), and llvm::X86TargetLowering::canCreateUndefOrPoisonForTargetNode().

◆ CanLowerReturn()

virtual bool llvm::TargetLowering::CanLowerReturn	(	CallingConv::ID	,
		MachineFunction &	,
		bool	,
		const SmallVectorImpl< ISD::OutputArg > &	,
		LLVMContext &
	)		const

inlinevirtual

This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers.

If false is returned, an sret-demotion is performed.

Reimplemented in llvm::VETargetLowering, llvm::SITargetLowering, llvm::HexagonTargetLowering, llvm::LanaiTargetLowering, llvm::LoongArchTargetLowering, llvm::RISCVTargetLowering, llvm::SparcTargetLowering, llvm::SystemZTargetLowering, and llvm::XtensaTargetLowering.

Definition at line 4781 of file TargetLowering.h.

Referenced by llvm::FastISel::lowerCallTo(), LowerCallTo(), and llvm::FunctionLoweringInfo::set().

◆ checkForPhysRegDependency()

virtual bool llvm::TargetLowering::checkForPhysRegDependency	(	SDNode *	Def,
		SDNode *	User,
		unsigned	Op,
		const TargetRegisterInfo *	TRI,
		const TargetInstrInfo *	TII,
		unsigned &	PhysReg,
		int &	Cost
	)		const

inlinevirtual

Allows the target to handle physreg-carried dependency in target-specific way.

Used from the ScheduleDAGSDNodes to decide whether to add the edge to the dependency graph. Def - input: Selection DAG node defininfg physical register User - input: Selection DAG node using physical register Op - input: Number of User operand PhysReg - inout: set to the physical register if the edge is necessary, unchanged otherwise Cost - inout: physical register copy cost. Returns 'true' is the edge is necessary, 'false' otherwise

Reimplemented in llvm::SITargetLowering.

Definition at line 4490 of file TargetLowering.h.

Referenced by CheckForPhysRegDependency().

◆ CollectTargetIntrinsicOperands()

void TargetLowering::CollectTargetIntrinsicOperands	(	const CallInst &	I,
		SmallVectorImpl< SDValue > &	Ops,
		SelectionDAG &	DAG
	)		const

virtual

Reimplemented in llvm::SITargetLowering, and llvm::PPCTargetLowering.

Definition at line 5665 of file TargetLowering.cpp.

◆ combineRepeatedFPDivisors()

virtual unsigned llvm::TargetLowering::combineRepeatedFPDivisors ( ) const

inlinevirtual

Indicate whether this target prefers to combine FDIVs with the same divisor.

If the transform should never be done, return zero. If the transform should be done, return the minimum number of divisor uses that must exist.

Reimplemented in llvm::SITargetLowering, and llvm::NVPTXTargetLowering.

Definition at line 5132 of file TargetLowering.h.

◆ ComputeConstraintToUse()

void TargetLowering::ComputeConstraintToUse	(	AsmOperandInfo &	OpInfo,
		SDValue	Op,
		SelectionDAG *	DAG = `nullptr`
	)		const

virtual

Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.

If the actual operand being passed in is available, it can be passed in as Op, otherwise an empty SDValue can be passed.

Definition at line 6089 of file TargetLowering.cpp.

References assert(), C_Immediate, C_Other, llvm::TargetLowering::AsmOperandInfo::CallOperandVal, llvm::InlineAsm::ConstraintInfo::Codes, llvm::TargetLowering::AsmOperandInfo::ConstraintCode, llvm::TargetLowering::AsmOperandInfo::ConstraintType, llvm::TargetLowering::AsmOperandInfo::ConstraintVT, G, and lowerImmediateIfPossible().

Referenced by llvm::GCNTTIImpl::isInlineAsmSourceOfDivergence(), IsOperandAMemoryOperand(), llvm::SITargetLowering::requiresUniformRegister(), and llvm::FunctionLoweringInfo::set().

◆ computeKnownAlignForTargetInstr()

Align TargetLowering::computeKnownAlignForTargetInstr	(	GISelKnownBits &	Analysis,
		Register	R,
		const MachineRegisterInfo &	MRI,
		unsigned	Depth = `0`
	)		const

virtual

Determine the known alignment for the pointer value R.

This is can typically be inferred from the number of low known 0 bits. However, for a pointer with a non-integral address space, the alignment value may be independent from the known low bits.

Reimplemented in llvm::SITargetLowering.

Definition at line 3802 of file TargetLowering.cpp.

Referenced by llvm::GISelKnownBits::computeKnownAlignment().

◆ computeKnownBitsForFrameIndex()

void TargetLowering::computeKnownBitsForFrameIndex	(	int	FIOp,
		KnownBits &	Known,
		const MachineFunction &	MF
	)		const

virtual

Determine which of the bits of FrameIndex FIOp are known to be 0.

Default implementation computes low bits based on alignment information. This should preserve known bits passed into it.

Reimplemented in llvm::SITargetLowering.

Definition at line 3796 of file TargetLowering.cpp.

References llvm::MachineFunction::getFrameInfo(), llvm::MachineFrameInfo::getObjectAlign(), llvm::Log2(), llvm::APInt::setLowBits(), and llvm::KnownBits::Zero.

Referenced by llvm::SelectionDAG::computeKnownBits(), llvm::SITargetLowering::computeKnownBitsForFrameIndex(), and llvm::GISelKnownBits::computeKnownBitsImpl().

◆ computeKnownBitsForTargetInstr()

void TargetLowering::computeKnownBitsForTargetInstr	(	GISelKnownBits &	Analysis,
		Register	R,
		KnownBits &	Known,
		const APInt &	DemandedElts,
		const MachineRegisterInfo &	MRI,
		unsigned	Depth = `0`
	)		const

virtual

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.

The DemandedElts argument allows us to only collect the known bits that are shared by the requested vector elements. This is for GISel.

Reimplemented in llvm::SITargetLowering.

Definition at line 3789 of file TargetLowering.cpp.

References llvm::KnownBits::resetAll().

Referenced by llvm::GISelKnownBits::computeKnownBitsImpl().

◆ computeKnownBitsForTargetNode()

void TargetLowering::computeKnownBitsForTargetNode	(	const SDValue	Op,
		KnownBits &	Known,
		const APInt &	DemandedElts,
		const SelectionDAG &	DAG,
		unsigned	Depth = `0`
	)		const

virtual

Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.

Determine which of the bits specified in Mask are known to be either zero or one and return them in the Known.

The DemandedElts argument allows us to only collect the known bits that are shared by the requested vector elements.

Reimplemented in llvm::ARMTargetLowering, llvm::RISCVTargetLowering, llvm::AArch64TargetLowering, llvm::AMDGPUTargetLowering, llvm::SITargetLowering, llvm::LanaiTargetLowering, llvm::PPCTargetLowering, llvm::SparcTargetLowering, llvm::SystemZTargetLowering, and llvm::X86TargetLowering.

Definition at line 3775 of file TargetLowering.cpp.

References assert(), llvm::ISD::BUILTIN_OP_END, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, and llvm::KnownBits::resetAll().

Referenced by llvm::SelectionDAG::computeKnownBits().

◆ computeNumSignBitsForTargetInstr()

unsigned TargetLowering::computeNumSignBitsForTargetInstr	(	GISelKnownBits &	Analysis,
		Register	R,
		const APInt &	DemandedElts,
		const MachineRegisterInfo &	MRI,
		unsigned	Depth = `0`
	)		const

virtual

This method can be implemented by targets that want to expose additional information about sign bits to GlobalISel combiners.

The DemandedElts argument allows us to only collect the minimum sign bits that are shared by the requested vector elements.

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 3823 of file TargetLowering.cpp.

Referenced by llvm::GISelKnownBits::computeNumSignBits().

◆ ComputeNumSignBitsForTargetNode()

unsigned TargetLowering::ComputeNumSignBitsForTargetNode	(	SDValue	Op,
		const APInt &	DemandedElts,
		const SelectionDAG &	DAG,
		unsigned	Depth = `0`
	)		const

virtual

This method can be implemented by targets that want to expose additional information about sign bits to the DAG Combiner.

The DemandedElts argument allows us to only collect the minimum sign bits that are shared by the requested vector elements.

Reimplemented in llvm::AArch64TargetLowering, llvm::RISCVTargetLowering, llvm::SystemZTargetLowering, llvm::X86TargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 3810 of file TargetLowering.cpp.

References assert(), llvm::ISD::BUILTIN_OP_END, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, and llvm::ISD::INTRINSIC_WO_CHAIN.

Referenced by llvm::SelectionDAG::ComputeNumSignBits().

◆ createFastISel()

virtual FastISel * llvm::TargetLowering::createFastISel	(	FunctionLoweringInfo &	,
		const TargetLibraryInfo *
	)		const

inlinevirtual

This method returns a target specific FastISel object, or null if the target does not support "fast" ISel.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::MipsTargetLowering, llvm::PPCTargetLowering, and llvm::X86TargetLowering.

Definition at line 4925 of file TargetLowering.h.

◆ createSelectForFMINNUM_FMAXNUM()

SDValue TargetLowering::createSelectForFMINNUM_FMAXNUM	(	SDNode *	Node,
		SelectionDAG &	DAG
	)		const

Try to convert the fminnum/fmaxnum to a compare/select sequence.

This is required for correctness since InstCombine might have canonicalized a fcmp+select sequence to a FMINNUM/FMAXNUM intrinsic. If we were to fall through to the default expansion/soften to libcall, we might introduce a link-time dependency on libm into a file that originally did not have one.

Definition at line 8465 of file TargetLowering.cpp.

References assert(), llvm::ISD::FMAXNUM, llvm::ISD::FMINNUM, llvm::SelectionDAG::getSelectCC(), llvm::EVT::getSimpleVT(), llvm::TargetLoweringBase::isCondCodeLegal(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::EVT::isVector(), llvm::SDNodeFlags::NoSignedZeros, llvm::SDNode::setFlags(), llvm::ISD::SETGT, llvm::ISD::SETLT, llvm::ISD::STRICT_FMAXNUM, llvm::ISD::STRICT_FMINNUM, and llvm::ISD::VSELECT.

◆ CTTZTableLookup()

SDValue TargetLowering::CTTZTableLookup	(	SDNode *	N,
		SelectionDAG &	DAG,
		const SDLoc &	DL,
		EVT	VT,
		SDValue	Op,
		unsigned	NumBitsPerElt
	)		const

Expand CTTZ via Table Lookup.

Parameters

N	Node to expand

Returns: The expansion result or SDValue() if it fails.

Definition at line 9308 of file TargetLowering.cpp.

◆ EmitInstrWithCustomInserter()

MachineBasicBlock * TargetLowering::EmitInstrWithCustomInserter	(	MachineInstr &	MI,
		MachineBasicBlock *	MBB
	)		const

virtual

This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag.

These instructions are special in various ways, which require special support to insert. The specified MachineInstr is created but not inserted into any basic blocks, and this method is called to expand it into a sequence of instructions, potentially also creating new basic blocks and control flow. As long as the returned basic block is different (i.e., we created a new one), the custom inserter is free to modify the rest of MBB.

Definition at line 315 of file SelectionDAGISel.cpp.

References llvm::dbgs(), and llvm_unreachable.

Referenced by llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), and runImpl().

◆ emitStackGuardXorFP()

virtual SDValue llvm::TargetLowering::emitStackGuardXorFP	(	SelectionDAG &	DAG,
		SDValue	Val,
		const SDLoc &	DL
	)		const

inlinevirtual

Reimplemented in llvm::X86TargetLowering.

Definition at line 5591 of file TargetLowering.h.

References llvm_unreachable.

Referenced by llvm::SelectionDAGBuilder::visitSPDescriptorParent().

◆ expandABD()

SDValue TargetLowering::expandABD	(	SDNode *	N,
		SelectionDAG &	DAG
	)		const

Expand ABDS/ABDU nodes.

Expands vector/scalar ABDS/ABDU nodes.

Parameters

N	Node to expand

Returns: The expansion result or SDValue() if it fails.

Definition at line 9512 of file TargetLowering.cpp.

◆ expandABS()

SDValue TargetLowering::expandABS	(	SDNode *	N,
		SelectionDAG &	DAG,
		bool	IsNegative = `false`
	)		const

Expand ABS nodes.

Expands vector/scalar ABS nodes, vector nodes can only succeed if all operations are legal/custom. (ABS x) -> (XOR (ADD x, (SRA x, type_size)), (SRA x, type_size))

Parameters

N	Node to expand
IsNegative	indicate negated abs

Returns: The expansion result or SDValue() if it fails.

Definition at line 9457 of file TargetLowering.cpp.

References llvm::ISD::ADD, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getFreeze(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::TargetLoweringBase::isOperationLegal(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::TargetLoweringBase::isOperationLegalOrCustomOrPromote(), llvm::EVT::isVector(), N, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::SRA, llvm::ISD::SUB, llvm::ISD::UMIN, llvm::Xor, and llvm::ISD::XOR.

◆ expandAddSubSat()

SDValue TargetLowering::expandAddSubSat	(	SDNode *	Node,
		SelectionDAG &	DAG
	)		const

Method for building the DAG expansion of ISD::[US][ADD|SUB]SAT.

This method accepts integers as its arguments.

Definition at line 10635 of file TargetLowering.cpp.

Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().

◆ expandAVG()

SDValue TargetLowering::expandAVG	(	SDNode *	N,
		SelectionDAG &	DAG
	)		const

Expand vector/scalar AVGCEILS/AVGCEILU/AVGFLOORS/AVGFLOORU nodes.

Parameters

N	Node to expand

Returns: The expansion result or SDValue() if it fails.

Definition at line 9586 of file TargetLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::AVGCEILS, llvm::ISD::AVGCEILU, llvm::ISD::AVGFLOORS, llvm::ISD::AVGFLOORU, llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::KnownBits::countMinLeadingZeros(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getFreeze(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::EVT::isScalarInteger(), llvm::TargetLoweringBase::isTruncateFree(), llvm::TargetLoweringBase::isTypeLegal(), LHS, N, llvm::ISD::OR, RHS, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, llvm::ISD::TRUNCATE, llvm::ISD::UADDO, llvm::Xor, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.

◆ expandBITREVERSE()

SDValue TargetLowering::expandBITREVERSE	(	SDNode *	N,
		SelectionDAG &	DAG
	)		const

Expand BITREVERSE nodes.

Expands scalar/vector BITREVERSE nodes. Returns SDValue() if expand fails.

Parameters

N	Node to expand

Returns: The expansion result or SDValue() if it fails.

Definition at line 9802 of file TargetLowering.cpp.

References llvm::ISD::AND, llvm::ISD::BSWAP, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::EVT::getScalarSizeInBits(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::APInt::getSplat(), I, llvm::isPowerOf2_32(), N, llvm::ISD::OR, llvm::ISD::SHL, and llvm::ISD::SRL.

◆ expandBSWAP()

SDValue TargetLowering::expandBSWAP	(	SDNode *	N,
		SelectionDAG &	DAG
	)		const

Expand BSWAP nodes.

Expands scalar/vector BSWAP nodes with i16/i32/i64 scalar types. Returns SDValue() if expand fails.

Parameters

N	Node to expand

Returns: The expansion result or SDValue() if it fails.

Definition at line 9668 of file TargetLowering.cpp.

References llvm::ISD::AND, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarType(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), N, llvm::ISD::OR, llvm::ISD::ROTL, llvm::ISD::SHL, llvm::MVT::SimpleTy, and llvm::ISD::SRL.

◆ expandCMP()

SDValue TargetLowering::expandCMP	(	SDNode *	Node,
		SelectionDAG &	DAG
	)		const

Method for building the DAG expansion of ISD::[US]CMP.

This method accepts integers as its arguments

Definition at line 10751 of file TargetLowering.cpp.

◆ expandCTLZ()

SDValue TargetLowering::expandCTLZ	(	SDNode *	N,
		SelectionDAG &	DAG
	)		const

Expand CTLZ/CTLZ_ZERO_UNDEF nodes.

Expands vector/scalar CTLZ nodes, vector nodes can only succeed if all operations are legal/custom.

Parameters

N	Node to expand

Returns: The expansion result or SDValue() if it fails.

Definition at line 9231 of file TargetLowering.cpp.

References canExpandVectorCTPOP(), llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_UNDEF, llvm::ISD::CTPOP, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::TargetLoweringBase::getSetCCResultType(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::TargetLoweringBase::isOperationLegalOrCustomOrPromote(), llvm::isPowerOf2_32(), llvm::EVT::isVector(), llvm::ISD::OR, llvm::ISD::SETEQ, and llvm::ISD::SRL.

◆ expandCTPOP()

SDValue TargetLowering::expandCTPOP	(	SDNode *	N,
		SelectionDAG &	DAG
	)		const

Expand CTPOP nodes.

Expands vector/scalar CTPOP nodes, vector nodes can only succeed if all operations are legal/custom.

Parameters

N	Node to expand

Returns: The expansion result or SDValue() if it fails.

Definition at line 9085 of file TargetLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, assert(), canExpandVectorCTPOP(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::APInt::getSplat(), llvm::TargetLoweringBase::getTypeToTransformTo(), llvm::EVT::isInteger(), llvm::TargetLoweringBase::isOperationLegalOrCustomOrPromote(), llvm::EVT::isVector(), llvm::ISD::MUL, llvm::ISD::SHL, llvm::ISD::SRL, and llvm::ISD::SUB.

◆ expandCTTZ()

SDValue TargetLowering::expandCTTZ	(	SDNode *	N,
		SelectionDAG &	DAG
	)		const

Expand CTTZ/CTTZ_ZERO_UNDEF nodes.

Expands vector/scalar CTTZ nodes, vector nodes can only succeed if all operations are legal/custom.

Parameters

N	Node to expand

Returns: The expansion result or SDValue() if it fails.

Definition at line 9352 of file TargetLowering.cpp.

References llvm::ISD::AND, canExpandVectorCTPOP(), llvm::ISD::CTLZ, llvm::ISD::CTPOP, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::TargetLoweringBase::getSetCCResultType(), llvm::TargetLoweringBase::isOperationExpand(), llvm::TargetLoweringBase::isOperationLegal(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::TargetLoweringBase::isOperationLegalOrCustomOrPromote(), llvm::isPowerOf2_32(), llvm::EVT::isVector(), llvm::ISD::SETEQ, llvm::ISD::SUB, and llvm::ISD::XOR.

◆ expandDIVREMByConstant()

bool TargetLowering::expandDIVREMByConstant	(	SDNode *	N,
		SmallVectorImpl< SDValue > &	Result,
		EVT	HiLoVT,
		SelectionDAG &	DAG,
		SDValue	LL = `SDValue()`,
		SDValue	LH = `SDValue()`
	)		const

Attempt to expand an n-bit div/rem/divrem by constant using a n/2-bit urem by constant and other arithmetic ops.

The n/2-bit urem by constant will be expanded by DAGCombiner. This is not possible for all constant divisors.

Parameters

N	Node to expand
Result	A vector that will be filled with the lo and high parts of the results. For *DIVREM, this will be the quotient parts followed by the remainder parts.
HiLoVT	The value type to use for the Lo and Hi parts. Should be half of VT.
LL	Low bits of the LHS of the operation. You can use this parameter if you want to control how low bits are extracted from the LHS.
LH	High bits of the LHS of the operation. See LL for meaning.

Returns: true if the node has been expanded, false if it has not.

Definition at line 7816 of file TargetLowering.cpp.

◆ expandFixedPointDiv()

SDValue TargetLowering::expandFixedPointDiv	(	unsigned	Opcode,
		const SDLoc &	dl,
		SDValue	LHS,
		SDValue	RHS,
		unsigned	Scale,
		SelectionDAG &	DAG
	)		const

Method for building the DAG expansion of ISD::[US]DIVFIX[SAT].

This method accepts integers as its arguments. Note: This method may fail if the division could not be performed within the type. Clients must retry with a wider type if this happens.

Definition at line 11099 of file TargetLowering.cpp.

Referenced by earlyExpandDIVFIX().

◆ expandFixedPointMul()

SDValue TargetLowering::expandFixedPointMul	(	SDNode *	Node,
		SelectionDAG &	DAG
	)		const

Method for building the DAG expansion of ISD::[U|S]MULFIX[SAT].

This method accepts integers as its arguments.

Definition at line 10942 of file TargetLowering.cpp.

◆ expandFMINIMUM_FMAXIMUM()

SDValue TargetLowering::expandFMINIMUM_FMAXIMUM	(	SDNode *	N,
		SelectionDAG &	DAG
	)		const

Expand fminimum/fmaximum into multiple comparison with selects.

Definition at line 8547 of file TargetLowering.cpp.

◆ expandFMINIMUMNUM_FMAXIMUMNUM()

SDValue TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM	(	SDNode *	N,
		SelectionDAG &	DAG
	)		const

Expand fminimumnum/fmaximumnum into multiple comparison with selects.

Definition at line 8614 of file TargetLowering.cpp.

◆ expandFMINNUM_FMAXNUM()

SDValue TargetLowering::expandFMINNUM_FMAXNUM	(	SDNode *	N,
		SelectionDAG &	DAG
	)		const

Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs.

Definition at line 8491 of file TargetLowering.cpp.

References llvm::ISD::FCANONICALIZE, llvm::ISD::FMAXIMUM, llvm::ISD::FMAXNUM_IEEE, llvm::ISD::FMINIMUM, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::isKnownNeverNaN(), llvm::SelectionDAG::isKnownNeverSNaN(), llvm::SelectionDAG::isKnownNeverZeroFloat(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::EVT::isScalableVector(), and llvm::report_fatal_error().

◆ expandFP_ROUND()

SDValue TargetLowering::expandFP_ROUND	(	SDNode *	Node,
		SelectionDAG &	DAG
	)		const

Expand round(fp) to fp conversion.

Parameters

N	Node to expand

Returns: The expansion result

Definition at line 11619 of file TargetLowering.cpp.

References llvm::Add, llvm::ISD::ADD, llvm::ISD::AND, assert(), llvm::ISD::BITCAST, llvm::EVT::changeVectorElementType(), F32, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_BF16, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::TargetLoweringBase::getSetCCResultType(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::EVT::isVector(), llvm::ISD::OR, llvm::ISD::SETUO, llvm::ISD::SRL, and llvm::ISD::TRUNCATE.

◆ expandFP_TO_INT_SAT()

SDValue TargetLowering::expandFP_TO_INT_SAT	(	SDNode *	N,
		SelectionDAG &	DAG
	)		const

Expand FP_TO_[US]INT_SAT into FP_TO_[US]INT and selects or min/max.

Parameters

N	Node to expand

Returns: The expansion result

Definition at line 11441 of file TargetLowering.cpp.

References assert(), llvm::APFloat::convertFromAPInt(), llvm::ISD::FMAXNUM, llvm::ISD::FMINNUM, llvm::ISD::FP_EXTEND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_SINT_SAT, llvm::ISD::FP_TO_UINT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::EVT::getFltSemantics(), llvm::APInt::getMaxValue(), llvm::APInt::getMinValue(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::TargetLoweringBase::getSetCCResultType(), llvm::APInt::getSignedMaxValue(), llvm::APInt::getSignedMinValue(), llvm::TargetLoweringBase::isOperationLegal(), llvm::APFloatBase::opInexact, llvm::APFloatBase::rmTowardZero, Select, llvm::ISD::SETOGT, llvm::ISD::SETULT, llvm::ISD::SETUO, llvm::APInt::sext(), and llvm::APInt::zext().

◆ expandFP_TO_SINT()

bool TargetLowering::expandFP_TO_SINT	(	SDNode *	N,
		SDValue &	Result,
		SelectionDAG &	DAG
	)		const

Expand float(f32) to SINT(i64) conversion.

Parameters

N	Node to expand
Result	output after conversion

Returns: True, if the expansion was successful, false otherwise

Definition at line 8231 of file TargetLowering.cpp.

References llvm::ISD::AND, llvm::ISD::BITCAST, llvm::EVT::changeTypeToInteger(), llvm::Exponent, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSelectCC(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::APInt::getSignMask(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::ISD::OR, llvm::ISD::SETGT, llvm::ISD::SETLT, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, and llvm::ISD::XOR.

Referenced by llvm::R600TargetLowering::ReplaceNodeResults().

◆ expandFP_TO_UINT()

bool TargetLowering::expandFP_TO_UINT	(	SDNode *	N,
		SDValue &	Result,
		SDValue &	Chain,
		SelectionDAG &	DAG
	)		const

Expand float to UINT conversion.

Parameters

N	Node to expand
Result	output after conversion
Chain	output chain after conversion

Returns: True, if the expansion was successful, false otherwise

Definition at line 8302 of file TargetLowering.cpp.

References llvm::APFloat::convertFromAPInt(), llvm::ISD::FP_TO_SINT, llvm::ISD::FSUB, llvm::SelectionDAG::getBoolExtOrTrunc(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::EVT::getFltSemantics(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::TargetLoweringBase::getSetCCResultType(), llvm::APInt::getSignMask(), llvm::SDValue::getValue(), llvm::APInt::getZero(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::TargetLoweringBase::isOperationLegalOrCustomOrPromote(), llvm::EVT::isVector(), llvm::APFloatBase::opOverflow, llvm::APFloatBase::rmNearestTiesToEven, llvm::ISD::SETLT, llvm::TargetLoweringBase::shouldUseStrictFP_TO_INT(), llvm::ISD::STRICT_FP_TO_SINT, llvm::ISD::STRICT_FSUB, and llvm::ISD::XOR.

◆ expandFunnelShift()

SDValue TargetLowering::expandFunnelShift	(	SDNode *	N,
		SelectionDAG &	DAG
	)		const

Expand funnel shift.

Parameters

N	Node to expand

Returns: The expansion if successful, SDValue() otherwise

Definition at line 8035 of file TargetLowering.cpp.

References llvm::ISD::AND, DL, expandVPFunnelShift(), llvm::ISD::FSHL, llvm::ISD::FSHR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::EVT::getScalarSizeInBits(), isNonZeroModBitWidthOrUndef(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::TargetLoweringBase::isOperationLegalOrCustomOrPromote(), llvm::isPowerOf2_32(), llvm::EVT::isVector(), llvm::ISD::OR, llvm::ISD::SHL, llvm::ISD::SRL, llvm::ISD::SUB, llvm::ISD::UREM, X, and Y.

◆ expandIndirectJTBranch()

SDValue TargetLowering::expandIndirectJTBranch	(	const SDLoc &	dl,
		SDValue	Value,
		SDValue	Addr,
		int	JTI,
		SelectionDAG &	DAG
	)		const

virtual

Expands target specific indirect branch for the case of JumpTable expansion.

Reimplemented in llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 477 of file TargetLowering.cpp.

References Addr, llvm::ISD::BRIND, llvm::SelectionDAG::getJumpTableDebugInfo(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTarget(), llvm::TargetMachine::getTargetTriple(), and llvm::Triple::isOSBinFormatCOFF().

Referenced by llvm::RISCVTargetLowering::expandIndirectJTBranch(), and llvm::X86TargetLowering::expandIndirectJTBranch().

◆ ExpandInlineAsm()

virtual bool llvm::TargetLowering::ExpandInlineAsm ( CallInst * ) const

inlinevirtual

This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to.

This is useful for turning simple inline asms into LLVM intrinsics, which gives the compiler more information about the behavior of the code.

Reimplemented in llvm::ARMTargetLowering, and llvm::X86TargetLowering.

Definition at line 4946 of file TargetLowering.h.

◆ expandIntMINMAX()

SDValue TargetLowering::expandIntMINMAX	(	SDNode *	Node,
		SelectionDAG &	DAG
	)		const

Method for building the DAG expansion of ISD::[US][MIN|MAX].

This method accepts integers as its arguments.

Definition at line 10554 of file TargetLowering.cpp.

◆ expandIS_FPCLASS()

SDValue TargetLowering::expandIS_FPCLASS	(	EVT	ResultVT,
		SDValue	Op,
		FPClassTest	Test,
		SDNodeFlags	Flags,
		const SDLoc &	DL,
		SelectionDAG &	DAG
	)		const

Expand check for floating point class.

Parameters

ResultVT	The type of intrinsic call result.
Op	The tested value.
Test	The test to perform.
Flags	The optimization flags.

Returns: The expansion result or SDValue() if it fails.

Definition at line 8726 of file TargetLowering.cpp.

◆ expandMUL()

bool TargetLowering::expandMUL	(	SDNode *	N,
		SDValue &	Lo,
		SDValue &	Hi,
		EVT	HiLoVT,
		SelectionDAG &	DAG,
		MulExpansionKind	Kind,
		SDValue	LL = `SDValue()`,
		SDValue	LH = `SDValue()`,
		SDValue	RL = `SDValue()`,
		SDValue	RH = `SDValue()`
	)		const

Expand a MUL into two nodes.

One that computes the high bits of the result and one that computes the low bits.

Parameters

HiLoVT	The value type to use for the Lo and Hi nodes.
LL	Low bits of the LHS of the MUL. You can use this parameter if you want to control how low bits are extracted from the LHS.
LH	High bits of the LHS of the MUL. See LL for meaning.
RL	Low bits of the RHS of the MUL. See LL for meaning
RH	High bits of the RHS of the MUL. See LL for meaning.

Returns: true if the node has been expanded. false if it has not

Definition at line 7779 of file TargetLowering.cpp.

References assert(), llvm::Hi, llvm::Lo, and N.

◆ expandMUL_LOHI()

bool TargetLowering::expandMUL_LOHI	(	unsigned	Opcode,
		EVT	VT,
		const SDLoc &	dl,
		SDValue	LHS,
		SDValue	RHS,
		SmallVectorImpl< SDValue > &	Result,
		EVT	HiLoVT,
		SelectionDAG &	DAG,
		MulExpansionKind	Kind,
		SDValue	LL = `SDValue()`,
		SDValue	LH = `SDValue()`,
		SDValue	RL = `SDValue()`,
		SDValue	RH = `SDValue()`
	)		const

Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes, respectively, each computing an n/2-bit part of the result.

Parameters

Result	A vector that will be filled with the parts of the result in little-endian order.
LL	Low bits of the LHS of the MUL. You can use this parameter if you want to control how low bits are extracted from the LHS.
LH	High bits of the LHS of the MUL. See LL for meaning.
RL	Low bits of the RHS of the MUL. See LL for meaning
RH	High bits of the RHS of the MUL. See LL for meaning.

Returns: true if the node has been expanded, false if it has not

Definition at line 7604 of file TargetLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::ADDE, llvm::TargetLoweringBase::Always, assert(), llvm::SelectionDAG::ComputeMaxSignificantBits(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::APInt::getHighBitsSet(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSelectCC(), llvm::TargetLoweringBase::getSetCCResultType(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::Hi, llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::EVT::isVector(), LHS, llvm::Lo, llvm::SelectionDAG::MaskedValueIsZero(), Merge, llvm::ISD::MUL, llvm::ISD::MULHS, llvm::ISD::MULHU, llvm::ISD::OR, RHS, llvm::ISD::SETLT, llvm::ISD::SHL, Signed, llvm::ISD::SMUL_LOHI, llvm::ISD::SRL, llvm::ISD::SUB, llvm::ISD::TRUNCATE, llvm::ISD::UADDO_CARRY, llvm::ISD::UMUL_LOHI, and llvm::ISD::ZERO_EXTEND.

◆ expandMULO()

bool TargetLowering::expandMULO	(	SDNode *	Node,
		SDValue &	Result,
		SDValue &	Overflow,
		SelectionDAG &	DAG
	)		const

Method for building the DAG expansion of ISD::[US]MULO.

Returns whether expansion was successful and populates the Result and Overflow arguments.

Definition at line 11270 of file TargetLowering.cpp.

References assert(), llvm::EVT::bitsLT(), llvm::CallingConv::C, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSetCC(), llvm::TargetLoweringBase::getSetCCResultType(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValue(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::isConstOrConstSplat(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), isSigned(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), LHS, llvm::Mul, llvm::ISD::MUL, llvm::ISD::MULHS, llvm::ISD::MULHU, RHS, llvm::ISD::SETNE, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SMUL_LOHI, llvm::ISD::SMULO, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::TRUNCATE, llvm::ISD::UMUL_LOHI, and llvm::ISD::ZERO_EXTEND.

◆ expandREM()

bool TargetLowering::expandREM	(	SDNode *	Node,
		SDValue &	Result,
		SelectionDAG &	DAG
	)		const

Expand an SREM or UREM using SDIV/UDIV or SDIVREM/UDIVREM, if legal.

Returns true if the expansion was successful.

Definition at line 11417 of file TargetLowering.cpp.

References llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), isSigned(), llvm::Mul, llvm::ISD::MUL, llvm::ISD::SDIV, llvm::ISD::SDIVREM, llvm::ISD::SREM, llvm::ISD::SUB, llvm::ISD::UDIV, and llvm::ISD::UDIVREM.

◆ expandROT()

SDValue TargetLowering::expandROT	(	SDNode *	N,
		bool	AllowVectorOps,
		SelectionDAG &	DAG
	)		const

Expand rotations.

Parameters

N	Node to expand
AllowVectorOps	expand vector rotate, this should only be performed if the legalization is happening outside of LegalizeVectorOps

Returns: The expansion if successful, SDValue() otherwise

Definition at line 8124 of file TargetLowering.cpp.

References llvm::ISD::AND, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::TargetLoweringBase::isOperationLegalOrCustomOrPromote(), llvm::isPowerOf2_32(), llvm::EVT::isVector(), llvm::ISD::OR, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SHL, llvm::ISD::SRL, llvm::ISD::SUB, and llvm::ISD::UREM.

◆ expandRoundInexactToOdd()

SDValue TargetLowering::expandRoundInexactToOdd	(	EVT	ResultVT,
		SDValue	Op,
		const SDLoc &	DL,
		SelectionDAG &	DAG
	)		const

Truncate Op to ResultVT.

If the result is exact, leave it alone. If it is not exact, force the result to be odd.

Parameters

ResultVT	The type of result.
Op	The value to round.

Returns: The expansion result

Definition at line 11551 of file TargetLowering.cpp.

◆ expandSADDSUBO()

void TargetLowering::expandSADDSUBO	(	SDNode *	Node,
		SDValue &	Result,
		SDValue &	Overflow,
		SelectionDAG &	DAG
	)		const

Method for building the DAG expansion of ISD::S(ADD|SUB)O.

Expansion always suceeds and populates the Result and Overflow arguments.

Definition at line 11230 of file TargetLowering.cpp.

References llvm::ISD::ADD, llvm::SelectionDAG::getBoolExtOrTrunc(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSetCC(), llvm::TargetLoweringBase::getSetCCResultType(), llvm::TargetLoweringBase::isOperationLegal(), LHS, RHS, llvm::ISD::SADDO, llvm::ISD::SADDSAT, llvm::ISD::SETGT, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SSUBSAT, llvm::ISD::SUB, and llvm::ISD::XOR.

◆ expandShiftParts()

void TargetLowering::expandShiftParts	(	SDNode *	N,
		SDValue &	Lo,
		SDValue &	Hi,
		SelectionDAG &	DAG
	)		const

Expand shift-by-parts.

Parameters

N	Node to expand
Lo	lower-output-part after conversion
Hi	upper-output-part after conversion

Definition at line 8179 of file TargetLowering.cpp.

References llvm::ISD::AND, assert(), Cond, llvm::ISD::FSHL, llvm::ISD::FSHR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSetCC(), llvm::TargetLoweringBase::getSetCCResultType(), llvm::SDValue::getValueType(), llvm::Hi, llvm::isPowerOf2_32(), llvm::Lo, llvm::ISD::SELECT, llvm::ISD::SETNE, llvm::ISD::SHL, llvm::ISD::SHL_PARTS, llvm::ISD::SRA, llvm::ISD::SRA_PARTS, and llvm::ISD::SRL.

Referenced by LowerShiftParts().

◆ expandShlSat()

SDValue TargetLowering::expandShlSat	(	SDNode *	Node,
		SelectionDAG &	DAG
	)		const

Method for building the DAG expansion of ISD::[US]SHLSAT.

This method accepts integers as its arguments.

Definition at line 10786 of file TargetLowering.cpp.

References assert(), Cond, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::APInt::getMaxValue(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::TargetLoweringBase::getSetCCResultType(), llvm::APInt::getSignedMaxValue(), llvm::APInt::getSignedMinValue(), llvm::EVT::isInteger(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::EVT::isVector(), LHS, RHS, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SSHLSAT, llvm::SelectionDAG::UnrollVectorOp(), llvm::ISD::USHLSAT, and llvm::ISD::VSELECT.

◆ expandUADDSUBO()

void TargetLowering::expandUADDSUBO	(	SDNode *	Node,
		SDValue &	Result,
		SDValue &	Overflow,
		SelectionDAG &	DAG
	)		const

Method for building the DAG expansion of ISD::U(ADD|SUB)O.

Expansion always suceeds and populates the Result and Overflow arguments.

Definition at line 11184 of file TargetLowering.cpp.

References llvm::ISD::ADD, CC, llvm::SelectionDAG::getBoolExtOrTrunc(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSetCC(), llvm::TargetLoweringBase::getSetCCResultType(), llvm::isAllOnesConstant(), llvm::isOneConstant(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), LHS, RHS, llvm::ISD::SETEQ, llvm::ISD::SETNE, llvm::ISD::SETUGT, llvm::ISD::SETULT, llvm::ISD::SUB, llvm::ISD::UADDO, llvm::ISD::UADDO_CARRY, and llvm::ISD::USUBO_CARRY.

◆ expandUINT_TO_FP()

bool TargetLowering::expandUINT_TO_FP	(	SDNode *	N,
		SDValue &	Result,
		SDValue &	Chain,
		SelectionDAG &	DAG
	)		const

Expand UINT(i64) to double(f64) conversion.

Parameters

N	Node to expand
Result	output after conversion
Chain	output chain after conversion

Returns: True, if the expansion was successful, false otherwise

Definition at line 8404 of file TargetLowering.cpp.

References llvm::ISD::AND, llvm::ISD::FADD, llvm::ISD::FSUB, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::Hi, llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::TargetLoweringBase::isOperationLegalOrCustomOrPromote(), llvm::EVT::isVector(), llvm::Lo, llvm::ISD::OR, llvm::ISD::SINT_TO_FP, and llvm::ISD::SRL.

◆ expandUnalignedLoad()

std::pair< SDValue, SDValue > TargetLowering::expandUnalignedLoad	(	LoadSDNode *	LD,
		SelectionDAG &	DAG
	)		const

Expands an unaligned load to 2 half-size loads for an integer, and possibly more for vectors.

Definition at line 10093 of file TargetLowering.cpp.

Referenced by llvm::HexagonTargetLowering::LowerUnalignedLoad(), and llvm::AMDGPUTargetLowering::performLoadCombine().

◆ expandUnalignedStore()

SDValue TargetLowering::expandUnalignedStore	(	StoreSDNode *	ST,
		SelectionDAG &	DAG
	)		const

Expands an unaligned store to 2 half-size stores for integer values, and possibly more for vectors.

Definition at line 10242 of file TargetLowering.cpp.

Referenced by llvm::HexagonTargetLowering::LowerStore(), and llvm::AMDGPUTargetLowering::performStoreCombine().

◆ expandVecReduce()

SDValue TargetLowering::expandVecReduce	(	SDNode *	Node,
		SelectionDAG &	DAG
	)		const

Expand a VECREDUCE_* into an explicit calculation.

If Count is specified, only the first Count elements of the vector are used.

Definition at line 11350 of file TargetLowering.cpp.

References llvm::ISD::ANY_EXTEND, llvm::SelectionDAG::ExtractVectorElements(), llvm::SelectionDAG::getContext(), llvm::EVT::getHalfNumVectorElementsVT(), llvm::SelectionDAG::getNode(), llvm::ISD::getVecReduceBaseOpcode(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::Hi, llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::EVT::isPow2VectorType(), llvm::EVT::isScalableVector(), llvm::Lo, llvm::report_fatal_error(), and llvm::SelectionDAG::SplitVector().

◆ expandVecReduceSeq()

SDValue TargetLowering::expandVecReduceSeq	(	SDNode *	Node,
		SelectionDAG &	DAG
	)		const

Expand a VECREDUCE_SEQ_* into an explicit ordered calculation.

Definition at line 11390 of file TargetLowering.cpp.

References llvm::SelectionDAG::ExtractVectorElements(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::ISD::getVecReduceBaseOpcode(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::isScalableVector(), and llvm::report_fatal_error().

◆ expandVECTOR_COMPRESS()

SDValue TargetLowering::expandVECTOR_COMPRESS	(	SDNode *	Node,
		SelectionDAG &	DAG
	)		const

Expand a vector VECTOR_COMPRESS into a sequence of extract element, store temporarily, advance store position, before re-loading the final vector.

Definition at line 11747 of file TargetLowering.cpp.

◆ expandVectorNaryOpBySplitting()

SDValue TargetLowering::expandVectorNaryOpBySplitting	(	SDNode *	Node,
		SelectionDAG &	DAG
	)		const

Definition at line 12044 of file TargetLowering.cpp.

References llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::GetSplitDestVTs(), llvm::EVT::getVectorElementCount(), llvm::Hi, llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isKnownMultipleOf(), llvm::TargetLoweringBase::isOperationLegalOrCustomOrPromote(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::Lo, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::SelectionDAG::SplitVector().

◆ expandVectorSplice()

SDValue TargetLowering::expandVectorSplice	(	SDNode *	Node,
		SelectionDAG &	DAG
	)		const

Method for building the DAG expansion of ISD::VECTOR_SPLICE.

This method accepts vectors as its arguments.

Definition at line 11673 of file TargetLowering.cpp.

◆ expandVPBITREVERSE()

SDValue TargetLowering::expandVPBITREVERSE	(	SDNode *	N,
		SelectionDAG &	DAG
	)		const

Expand VP_BITREVERSE nodes.

Expands VP_BITREVERSE nodes with i8/i16/i32/i64 scalar types.

Parameters

N	Node to expand

Returns: The expansion result or SDValue() if it fails.

Definition at line 9863 of file TargetLowering.cpp.

References assert(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::APInt::getSplat(), llvm::isPowerOf2_32(), and N.

◆ expandVPBSWAP()

SDValue TargetLowering::expandVPBSWAP	(	SDNode *	N,
		SelectionDAG &	DAG
	)		const

Expand VP_BSWAP nodes.

Expands VP_BSWAP nodes with i16/i32/i64 scalar types. Returns SDValue() if expand fails.

Parameters

N	Node to expand

Returns: The expansion result or SDValue() if it fails.

Definition at line 9726 of file TargetLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarType(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), N, and llvm::MVT::SimpleTy.

◆ expandVPCTLZ()

SDValue TargetLowering::expandVPCTLZ	(	SDNode *	N,
		SelectionDAG &	DAG
	)		const

Expand VP_CTLZ/VP_CTLZ_ZERO_UNDEF nodes.

Parameters

N	Node to expand

Returns: The expansion result or SDValue() if it fails.

Definition at line 9281 of file TargetLowering.cpp.

References llvm::SelectionDAG::getAllOnesConstant(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), and llvm::TargetLoweringBase::getShiftAmountTy().

◆ expandVPCTPOP()

SDValue TargetLowering::expandVPCTPOP	(	SDNode *	N,
		SelectionDAG &	DAG
	)		const

Expand VP_CTPOP nodes.

Returns: The expansion result or SDValue() if it fails.

Definition at line 9162 of file TargetLowering.cpp.

References assert(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::APInt::getSplat(), llvm::TargetLoweringBase::getTypeToTransformTo(), llvm::EVT::isInteger(), and llvm::TargetLoweringBase::isOperationLegalOrCustomOrPromote().

◆ expandVPCTTZ()

SDValue TargetLowering::expandVPCTTZ	(	SDNode *	N,
		SelectionDAG &	DAG
	)		const

Expand VP_CTTZ/VP_CTTZ_ZERO_UNDEF nodes.

Parameters

N	Node to expand

Returns: The expansion result or SDValue() if it fails.

Definition at line 9408 of file TargetLowering.cpp.

References llvm::SelectionDAG::getAllOnesConstant(), llvm::SelectionDAG::getConstant(), and llvm::SelectionDAG::getNode().

◆ expandVPCTTZElements()

SDValue TargetLowering::expandVPCTTZElements	(	SDNode *	N,
		SelectionDAG &	DAG
	)		const

Expand VP_CTTZ_ELTS/VP_CTTZ_ELTS_ZERO_UNDEF nodes.

Parameters

N	Node to expand

Returns: The expansion result or SDValue() if it fails.

Definition at line 9424 of file TargetLowering.cpp.

References DL, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getSplat(), llvm::SelectionDAG::getStepVector(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorVT(), llvm::SelectionDAG::getZExtOrTrunc(), N, Select, llvm::ISD::SETNE, and llvm::Splat.

◆ findOptimalMemOpLowering()

bool TargetLowering::findOptimalMemOpLowering	(	std::vector< EVT > &	MemOps,
		unsigned	Limit,
		const MemOp &	Op,
		unsigned	DstAS,
		unsigned	SrcAS,
		const AttributeList &	FuncAttributes
	)		const

virtual

Determines the optimal series of memory ops to replace the memset / memcpy.

Return true if the number of memory ops is below the threshold (Limit). Note that this is always the case when Limit is ~0. It returns the types of the sequence of memory ops to perform memset / memcpy by reference.

Reimplemented in llvm::SystemZTargetLowering.

Definition at line 199 of file TargetLowering.cpp.

References llvm::TargetLoweringBase::allowsMisalignedMemoryAccesses(), assert(), llvm::EVT::bitsGT(), llvm::CallingConv::Fast, llvm::TargetLoweringBase::getOptimalMemOpType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::MVT::isInteger(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), llvm::TargetLoweringBase::isSafeMemOpType(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::MachineMemOperand::MONone, llvm::MVT::SimpleTy, Size, and llvm::ISD::STORE.

Referenced by llvm::SystemZTargetLowering::findOptimalMemOpLowering(), getMemcpyLoadsAndStores(), getMemmoveLoadsAndStores(), and getMemsetStores().

◆ forceExpandWideMUL() [1/2]

void TargetLowering::forceExpandWideMUL	(	SelectionDAG &	DAG,
		const SDLoc &	dl,
		bool	Signed,
		const SDValue	LHS,
		const SDValue	RHS,
		SDValue &	Lo,
		SDValue &	Hi
	)		const

Same as above, but creates the upper halves of each operand by sign/zero-extending the operands.

Definition at line 10914 of file TargetLowering.cpp.

References assert(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::EVT::getFixedSizeInBits(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getSizeInBits(), llvm::Hi, LHS, llvm::Lo, RHS, Signed, and llvm::ISD::SRA.

◆ forceExpandWideMUL() [2/2]

void TargetLowering::forceExpandWideMUL	(	SelectionDAG &	DAG,
		const SDLoc &	dl,
		bool	Signed,
		EVT	WideVT,
		const SDValue	LL,
		const SDValue	LH,
		const SDValue	RL,
		const SDValue	RH,
		SDValue &	Lo,
		SDValue &	Hi
	)		const

forceExpandWideMUL - Unconditionally expand a MUL into either a libcall or brute force via a wide multiplication.

The expansion works by attempting to do a multiplication on a wider type twice the size of the original operands. LL and LH represent the lower and upper halves of the first operand. RL and RH represent the lower and upper halves of the second operand. The upper and lower halves of the result are stored in Lo and Hi.

Definition at line 10825 of file TargetLowering.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, assert(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::TargetLoweringBase::getLibcallName(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::Hi, llvm::DataLayout::isLittleEndian(), llvm::Lo, llvm::ISD::MERGE_VALUES, llvm::ISD::MUL, llvm::TargetLowering::MakeLibCallOptions::setIsPostTypeLegalization(), llvm::TargetLowering::MakeLibCallOptions::setIsSigned(), llvm::ISD::SHL, Signed, and llvm::ISD::SRL.

◆ functionArgumentNeedsConsecutiveRegisters()

virtual bool llvm::TargetLowering::functionArgumentNeedsConsecutiveRegisters	(	Type *	Ty,
		CallingConv::ID	CallConv,
		bool	isVarArg,
		const DataLayout &	DL
	)		const

inlinevirtual

For some targets, an LLVM struct type must be broken down into multiple simple types, but the calling convention specifies that the entire struct must be passed in a block of consecutive registers.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, and llvm::PPCTargetLowering.

Definition at line 4842 of file TargetLowering.h.

Referenced by llvm::FastISel::lowerCallTo(), LowerCallTo(), and llvm::CallLowering::splitToValueTypes().

◆ getCheaperNegatedExpression()

SDValue llvm::TargetLowering::getCheaperNegatedExpression	(	SDValue	Op,
		SelectionDAG &	DAG,
		bool	LegalOps,
		bool	OptForSize,
		unsigned	Depth = `0`
	)		const

inline

This is the helper function to return the newly negated expression only when the cost is cheaper.

Definition at line 4452 of file TargetLowering.h.

References llvm::TargetLoweringBase::Cheaper, llvm::Depth, and getCheaperOrNeutralNegatedExpression().

Referenced by combineFMA(), combineFMADDSUB(), and llvm::X86TargetLowering::getNegatedExpression().

◆ getCheaperOrNeutralNegatedExpression()

SDValue llvm::TargetLowering::getCheaperOrNeutralNegatedExpression	(	SDValue	Op,
		SelectionDAG &	DAG,
		bool	LegalOps,
		bool	OptForSize,
		const NegatibleCost	CostThreshold = `NegatibleCost::Neutral`,
		unsigned	Depth = `0`
	)		const

inline

Definition at line 4431 of file TargetLowering.h.

References CostThreshold, llvm::Depth, llvm::TargetLoweringBase::Expensive, getNegatedExpression(), llvm::SDValue::getNode(), llvm::SelectionDAG::RemoveDeadNode(), and llvm::SDNode::use_empty().

Referenced by getCheaperNegatedExpression().

◆ getConstraintPreferences()

TargetLowering::ConstraintGroup TargetLowering::getConstraintPreferences ( TargetLowering::AsmOperandInfo & OpInfo ) const

Given an OpInfo with list of constraints codes as strings, return a sorted Vector of pairs of constraint codes and their types in priority of what we'd prefer to lower them as.

If there are multiple different constraints that we could pick for this operand (e.g.

This may contain immediates that cannot be lowered, but it is meant to be a machine agnostic order of preferences.

"imr") try to pick the 'best' one. This is somewhat tricky: constraints (TargetLowering::ConstraintType) fall into seven classes: Register -> one specific register RegisterClass -> a group of regs Memory -> memory Address -> a symbolic memory reference Immediate -> immediate values Other -> magic values (such as "Flag Output Operands") Unknown -> something we don't recognize yet and can't handle Ideally, we would pick the most specific constraint possible: if we have something that fits into a register, we would pick it. The problem here is that if we have something that could either be in a register or in memory that use of the register could cause selection of other operands to fail: they might only succeed if we pick memory. Because of this the heuristic we use is:

1) If there is an 'other' constraint, and if the operand is valid for that constraint, use it. This makes us take advantage of 'i' constraints when available. 2) Otherwise, pick the most general constraint present. This prefers 'm' over 'r', for example.

Definition at line 6039 of file TargetLowering.cpp.

References C_Memory, C_Register, C_RegisterClass, llvm::InlineAsm::ConstraintInfo::Codes, llvm::InlineAsm::ConstraintInfo::hasMatchingInput(), and llvm::InlineAsm::ConstraintInfo::isIndirect.

Referenced by computeConstraintToUse().

◆ getConstraintType()

TargetLowering::ConstraintType TargetLowering::getConstraintType ( StringRef Constraint ) const

virtual

Given a constraint, return the type of constraint it is for this target.

Reimplemented in llvm::SITargetLowering, llvm::ARMTargetLowering, llvm::AVRTargetLowering, llvm::BPFTargetLowering, llvm::HexagonTargetLowering, llvm::MSP430TargetLowering, llvm::NVPTXTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::SparcTargetLowering, llvm::SystemZTargetLowering, llvm::VETargetLowering, llvm::X86TargetLowering, llvm::XtensaTargetLowering, and llvm::M68kTargetLowering.

Definition at line 5526 of file TargetLowering.cpp.

References llvm::StringRef::size(), and llvm::StringRef::substr().

◆ getInlineAsmMemConstraint()

virtual InlineAsm::ConstraintCode llvm::TargetLowering::getInlineAsmMemConstraint ( StringRef ConstraintCode ) const

inlinevirtual

◆ getJumpTableEncoding()

unsigned TargetLowering::getJumpTableEncoding ( ) const

virtual

Return the entry encoding for a jump table in the current function.

The returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.

Reimplemented in llvm::ARMTargetLowering, llvm::M68kTargetLowering, llvm::NVPTXTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::VETargetLowering, llvm::X86TargetLowering, and llvm::XCoreTargetLowering.

Definition at line 443 of file TargetLowering.cpp.

References llvm::MachineJumpTableInfo::EK_BlockAddress, llvm::MachineJumpTableInfo::EK_GPRel32BlockAddress, llvm::MachineJumpTableInfo::EK_LabelDifference32, and llvm::TargetLoweringBase::getTargetMachine().

Referenced by llvm::PPCTargetLowering::getJumpTableEncoding(), llvm::RISCVTargetLowering::getJumpTableEncoding(), llvm::VETargetLowering::getJumpTableEncoding(), and llvm::X86TargetLowering::getJumpTableEncoding().

◆ getJumpTableRegTy()

virtual MVT llvm::TargetLowering::getJumpTableRegTy ( const DataLayout & DL ) const

inlinevirtual

Reimplemented in llvm::NVPTXTargetLowering.

Definition at line 3857 of file TargetLowering.h.

References DL, and llvm::TargetLoweringBase::getPointerTy().

Referenced by llvm::SelectionDAGBuilder::visitJumpTable(), and llvm::SelectionDAGBuilder::visitJumpTableHeader().

◆ getMultipleConstraintMatchWeight()

TargetLowering::ConstraintWeight TargetLowering::getMultipleConstraintMatchWeight	(	AsmOperandInfo &	info,
		int	maIndex
	)		const

virtual

Examine constraint type and operand type and determine a weight value.

The operand object must already have been set up with the operand type.

This object must already have been set up with the operand type and the current alternative constraint selected.

Definition at line 5946 of file TargetLowering.cpp.

References info.

◆ getNegatedExpression() [1/2]

SDValue TargetLowering::getNegatedExpression	(	SDValue	Op,
		SelectionDAG &	DAG,
		bool	LegalOps,
		bool	OptForSize,
		NegatibleCost &	Cost,
		unsigned	Depth = `0`
	)		const

virtual

Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate that if it is cheaper or neutral to do the negation.

Reimplemented in llvm::AMDGPUTargetLowering, llvm::X86TargetLowering, and llvm::PPCTargetLowering.

Definition at line 7296 of file TargetLowering.cpp.

References llvm::all_of(), llvm::any_of(), llvm::ISD::BUILD_VECTOR, llvm::CallingConv::C, llvm::TargetLoweringBase::Cheaper, llvm::ISD::ConstantFP, llvm::Depth, DL, llvm::TargetLoweringBase::Expensive, llvm::ISD::FADD, llvm::ISD::FDIV, llvm::ISD::FMA, llvm::ISD::FMAD, llvm::ISD::FMUL, llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FSIN, llvm::ISD::FSUB, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getTarget(), llvm::isConstOrConstSplatFP(), llvm::TargetLoweringBase::isFPExtFree(), llvm::TargetLoweringBase::isFPImmLegal(), llvm::TargetLoweringBase::isOperationLegal(), llvm::TargetLoweringBase::isOperationLegalOrCustom(), LHS, llvm::SelectionDAG::MaxRecursionDepth, N, llvm::neg(), llvm::TargetLoweringBase::Neutral, llvm::TargetMachine::Options, Options, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SelectionDAG::RemoveDeadNode(), RHS, llvm::ISD::SELECT, llvm::SDValue::use_empty(), llvm::ISD::VSELECT, X, and Y.

Referenced by combineFneg(), getCheaperOrNeutralNegatedExpression(), llvm::AMDGPUTargetLowering::getNegatedExpression(), llvm::X86TargetLowering::getNegatedExpression(), llvm::PPCTargetLowering::getNegatedExpression(), and getNegatedExpression().

◆ getNegatedExpression() [2/2]

SDValue llvm::TargetLowering::getNegatedExpression	(	SDValue	Op,
		SelectionDAG &	DAG,
		bool	LegalOps,
		bool	OptForSize,
		unsigned	Depth = `0`
	)		const

inline

This is the helper function to return the newly negated expression if the cost is not expensive.

Definition at line 4461 of file TargetLowering.h.

References llvm::Depth, llvm::TargetLoweringBase::Expensive, and getNegatedExpression().

◆ getPICJumpTableRelocBase()

SDValue TargetLowering::getPICJumpTableRelocBase	(	SDValue	Table,
		SelectionDAG &	DAG
	)		const

virtual

Returns relocation base for the given PIC jumptable.

Reimplemented in llvm::HexagonTargetLowering, llvm::M68kTargetLowering, llvm::PPCTargetLowering, llvm::VETargetLowering, and llvm::X86TargetLowering.

Definition at line 456 of file TargetLowering.cpp.

References llvm::MachineJumpTableInfo::EK_GPRel32BlockAddress, llvm::MachineJumpTableInfo::EK_GPRel64BlockAddress, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getGLOBAL_OFFSET_TABLE(), and llvm::TargetLoweringBase::getPointerTy().

Referenced by llvm::PPCTargetLowering::getPICJumpTableRelocBase().

◆ getPICJumpTableRelocBaseExpr()

const MCExpr * TargetLowering::getPICJumpTableRelocBaseExpr	(	const MachineFunction *	MF,
		unsigned	JTI,
		MCContext &	Ctx
	)		const

virtual

This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.

Reimplemented in llvm::M68kTargetLowering, llvm::PPCTargetLowering, and llvm::X86TargetLowering.

Definition at line 471 of file TargetLowering.cpp.

References llvm::MCSymbolRefExpr::create(), and llvm::MachineFunction::getJTISymbol().

Referenced by llvm::AsmPrinter::emitJumpTableInfo(), llvm::AsmPrinter::getCodeViewJumpTableInfo(), llvm::PPCTargetLowering::getPICJumpTableRelocBaseExpr(), and llvm::X86TargetLowering::getPICJumpTableRelocBaseExpr().

◆ getPostIndexedAddressParts()

virtual bool llvm::TargetLowering::getPostIndexedAddressParts	(	SDNode *	,
		SDNode *	,
		SDValue &	,
		SDValue &	,
		ISD::MemIndexedMode &	,
		SelectionDAG &
	)		const

inlinevirtual

Returns true by value, base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store.

Reimplemented in llvm::ARMTargetLowering, llvm::AVRTargetLowering, llvm::HexagonTargetLowering, and llvm::RISCVTargetLowering.

Definition at line 3837 of file TargetLowering.h.

Referenced by shouldCombineToPostInc().

◆ getPreIndexedAddressParts()

virtual bool llvm::TargetLowering::getPreIndexedAddressParts	(	SDNode *	,
		SDValue &	,
		SDValue &	,
		ISD::MemIndexedMode &	,
		SelectionDAG &
	)		const

inlinevirtual

Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's address can be legally represented as pre-indexed load / store address.

Reimplemented in llvm::ARMTargetLowering, llvm::AVRTargetLowering, llvm::PPCTargetLowering, and llvm::RISCVTargetLowering.

Definition at line 3827 of file TargetLowering.h.

◆ getRecipEstimate()

virtual SDValue llvm::TargetLowering::getRecipEstimate	(	SDValue	Operand,
		SelectionDAG &	DAG,
		int	Enabled,
		int &	RefinementSteps
	)		const

inlinevirtual

Return a reciprocal estimate value for the input operand.

Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or 'Enabled' as set by a potential default override attribute. If RefinementSteps is 'Unspecified', the number of Newton-Raphson refinement iterations required to generate a sufficient (though not necessarily IEEE-754 compliant) estimate is returned in that parameter. A target may choose to implement its own refinement within this function. If that's true, then return '0' as the number of RefinementSteps to avoid any further refinement of the estimate. An empty SDValue return means no estimate sequence can be created.

Reimplemented in llvm::AMDGPUTargetLowering, and llvm::LoongArchTargetLowering.

Definition at line 5177 of file TargetLowering.h.

◆ getRegForInlineAsmConstraint()

std::pair< unsigned, const TargetRegisterClass * > TargetLowering::getRegForInlineAsmConstraint	(	const TargetRegisterInfo *	TRI,
		StringRef	Constraint,
		MVT	VT
	)		const

virtual

Given a physical register constraint (e.g.

{edx}), return the register number and the register class for the register.

Given a register class constraint, like 'r', if this corresponds directly to an LLVM register class, return a register of 0 and the register class pointer.

This should only be used for C_Register constraints. On error, this returns a register number of 0 and a null register class pointer.

Reimplemented in llvm::SITargetLowering, llvm::ARMTargetLowering, llvm::AVRTargetLowering, llvm::BPFTargetLowering, llvm::HexagonTargetLowering, llvm::LanaiTargetLowering, llvm::M68kTargetLowering, llvm::MSP430TargetLowering, llvm::NVPTXTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::SparcTargetLowering, llvm::SPIRVTargetLowering, llvm::SystemZTargetLowering, llvm::VETargetLowering, llvm::X86TargetLowering, and llvm::XtensaTargetLowering.

Definition at line 5670 of file TargetLowering.cpp.

References assert(), llvm::StringRef::data(), llvm::StringRef::end(), llvm::TargetRegisterInfo::getRegAsmName(), llvm::TargetLoweringBase::isLegalRC(), llvm::TargetRegisterInfo::isTypeLegalForClass(), llvm::TargetRegisterInfo::regclasses(), RegName, llvm::StringRef::size(), and llvm::StringRef::starts_with().

◆ getRegisterByName()

virtual Register llvm::TargetLowering::getRegisterByName	(	const char *	RegName,
		LLT	Ty,
		const MachineFunction &	MF
	)		const

inlinevirtual

Return the register ID of the name passed in.

Used by named register global variables extension. There is no target-independent behaviour so the default action is to bail.

Reimplemented in llvm::SITargetLowering, llvm::AVRTargetLowering, llvm::HexagonTargetLowering, llvm::LanaiTargetLowering, llvm::LoongArchTargetLowering, llvm::MipsTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::SparcTargetLowering, llvm::SystemZTargetLowering, llvm::VETargetLowering, and llvm::X86TargetLowering.

Definition at line 4821 of file TargetLowering.h.

References llvm::report_fatal_error().

Referenced by llvm::LegalizerHelper::lowerReadWriteRegister().

◆ getRoundingControlRegisters()

virtual ArrayRef< MCPhysReg > llvm::TargetLowering::getRoundingControlRegisters ( ) const

inlinevirtual

Returns a 0 terminated array of rounding control registers that can be attached into strict FP call.

Reimplemented in llvm::AArch64TargetLowering, and llvm::SITargetLowering.

Definition at line 4865 of file TargetLowering.h.

Referenced by llvm::InlineAsmLowering::lowerInlineAsm().

◆ getScratchRegisters()

virtual const MCPhysReg * llvm::TargetLowering::getScratchRegisters ( CallingConv::ID CC ) const

inlinevirtual

Returns a 0 terminated array of registers that can be safely used as scratch registers.

Reimplemented in llvm::AArch64TargetLowering, llvm::PPCTargetLowering, and llvm::SystemZTargetLowering.

Definition at line 4859 of file TargetLowering.h.

Referenced by llvm::FastISel::selectPatchpoint(), and llvm::FastISel::selectStackmap().

◆ getSingleConstraintMatchWeight()

TargetLowering::ConstraintWeight TargetLowering::getSingleConstraintMatchWeight	(	AsmOperandInfo &	info,
		const char *	constraint
	)		const

virtual

Examine constraint string and operand type and determine a weight value.

Examine constraint type and operand type and determine a weight value.

The operand object must already have been set up with the operand type.

This object must already have been set up with the operand type and the current alternative constraint selected.

Reimplemented in llvm::ARMTargetLowering, llvm::AVRTargetLowering, llvm::LanaiTargetLowering, llvm::PPCTargetLowering, llvm::SparcTargetLowering, llvm::SystemZTargetLowering, llvm::X86TargetLowering, and llvm::XtensaTargetLowering.

Definition at line 5970 of file TargetLowering.cpp.

References llvm::Value::getType(), info, and llvm::Type::isIntegerTy().

◆ getSqrtEstimate()

virtual SDValue llvm::TargetLowering::getSqrtEstimate	(	SDValue	Operand,
		SelectionDAG &	DAG,
		int	Enabled,
		int &	RefinementSteps,
		bool &	UseOneConstNR,
		bool	Reciprocal
	)		const

inlinevirtual

Hooks for building estimates in place of slower divisions and square roots.

Return either a square root or its reciprocal estimate value for the input operand. Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or 'Enabled' as set by a potential default override attribute. If RefinementSteps is 'Unspecified', the number of Newton-Raphson refinement iterations required to generate a sufficient (though not necessarily IEEE-754 compliant) estimate is returned in that parameter. The boolean UseOneConstNR output is used to select a Newton-Raphson algorithm implementation that uses either one or two constants. The boolean Reciprocal is used to select whether the estimate is for the square root of the input operand or the reciprocal of its square root. A target may choose to implement its own refinement within this function. If that's true, then return '0' as the number of RefinementSteps to avoid any further refinement of the estimate. An empty SDValue return means no estimate sequence can be created.

Reimplemented in llvm::NVPTXTargetLowering, llvm::AMDGPUTargetLowering, and llvm::LoongArchTargetLowering.

Definition at line 5154 of file TargetLowering.h.

◆ getSqrtInputTest()

SDValue TargetLowering::getSqrtInputTest	(	SDValue	Operand,
		SelectionDAG &	DAG,
		const DenormalMode &	Mode
	)		const

virtual

Return a target-dependent comparison result if the input operand is suitable for use with a square root estimate calculation.

For example, the comparison may check if the operand is NAN, INF, zero, normal, etc. The result should be used as the condition operand for a select or branch.

Definition at line 7271 of file TargetLowering.cpp.

References DL, llvm::ISD::FABS, llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::EVT::getFltSemantics(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSetCC(), llvm::TargetLoweringBase::getSetCCResultType(), llvm::APFloat::getSmallestNormalized(), llvm::DenormalMode::PositiveZero, llvm::DenormalMode::PreserveSign, llvm::ISD::SETEQ, and llvm::ISD::SETLT.

◆ getSqrtResultForDenormInput()

virtual SDValue llvm::TargetLowering::getSqrtResultForDenormInput	(	SDValue	Operand,
		SelectionDAG &	DAG
	)		const

inlinevirtual

Return a target-dependent result if the input operand is not suitable for use with a square root estimate calculation.

Definition at line 5191 of file TargetLowering.h.

References llvm::SelectionDAG::getConstantFP(), and llvm::SDValue::getValueType().

◆ getTargetConstantFromLoad()

const Constant * TargetLowering::getTargetConstantFromLoad ( LoadSDNode * LD ) const

virtual

This method returns the constant pool value that will be loaded by LD.

NOTE: You must check for implicit extensions of the constant by LD.

Reimplemented in llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 3884 of file TargetLowering.cpp.

Referenced by llvm::SelectionDAG::computeKnownBits(), and llvm::SelectionDAG::ComputeNumSignBits().

◆ getTargetNodeName()

const char * TargetLowering::getTargetNodeName ( unsigned Opcode ) const

virtual

This method returns the name of a target specific DAG node.

Definition at line 42 of file TargetLowering.cpp.

Referenced by llvm::SDNode::getOperationName().

◆ getTypeForExtReturn()

virtual EVT llvm::TargetLowering::getTypeForExtReturn	(	LLVMContext &	Context,
		EVT	VT,
		ISD::NodeType
	)		const

inlinevirtual

Return the type that should be used to zero or sign extend a zeroext/signext integer return value.

FIXME: Some C calling conventions require the return type to be promoted, but this is not true all the time, e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling conventions. The frontend should handle this and include all of the necessary information.

Reimplemented in llvm::AMDGPUTargetLowering, and llvm::MipsTargetLowering.

Definition at line 4832 of file TargetLowering.h.

References llvm::EVT::bitsLT(), and llvm::TargetLoweringBase::getRegisterType().

Referenced by llvm::GetReturnInfo().

◆ getVectorElementPointer()

SDValue TargetLowering::getVectorElementPointer	(	SelectionDAG &	DAG,
		SDValue	VecPtr,
		EVT	VecVT,
		SDValue	Index
	)		const

Get a pointer to vector element Idx located in memory for a vector of type VecVT starting at a base address of VecPtr.

If Idx is out of bounds the returned pointer is unspecified, but will be within the vector bounds.

Definition at line 10448 of file TargetLowering.cpp.

References llvm::SelectionDAG::getContext(), llvm::EVT::getVectorElementType(), and llvm::EVT::getVectorVT().

Referenced by combineExtractFromVectorLoad().

◆ getVectorSubVecPointer()

SDValue TargetLowering::getVectorSubVecPointer	(	SelectionDAG &	DAG,
		SDValue	VecPtr,
		EVT	VecVT,
		EVT	SubVecVT,
		SDValue	Index
	)		const

Get a pointer to a sub-vector of type SubVecVT at index Idx located in memory for a vector of type VecVT starting at a base address of VecPtr.

If Idx plus the size of SubVecVT is out of bounds the returned pointer is unspecified, but the value returned will be such that the entire subvector would be within the vector bounds.

Definition at line 10457 of file TargetLowering.cpp.

References assert(), clampDynamicVectorIndex(), llvm::SelectionDAG::getConstant(), llvm::EVT::getFixedSizeInBits(), llvm::SelectionDAG::getMemBasePlusOffset(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::SelectionDAG::getVScale(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::EVT::isScalableVector(), and llvm::ISD::MUL.

◆ HandleByVal()

virtual void llvm::TargetLowering::HandleByVal	(	CCState *	,
		unsigned &	,
		Align
	)		const

inlinevirtual

Target-specific cleanup for formal ByVal parameters.

Reimplemented in llvm::MipsTargetLowering.

Definition at line 4776 of file TargetLowering.h.

Referenced by llvm::CCState::HandleByVal().

◆ IncrementMemoryAddress()

SDValue TargetLowering::IncrementMemoryAddress	(	SDValue	Addr,
		SDValue	Mask,
		const SDLoc &	DL,
		EVT	DataVT,
		SelectionDAG &	DAG,
		bool	IsCompressedMemory
	)		const

Increments memory address Addr according to the type of the value DataVT that should be stored.

If the data is stored in compressed form, the memory address should be incremented according to the number of the stored elements. This number is equal to the number of '1's bits in the Mask. DataVT is a vector type. Mask is a vector value. DataVT and Mask have the same number of vector elements.

Definition at line 10376 of file TargetLowering.cpp.

References llvm::ISD::ADD, Addr, assert(), llvm::ISD::CTPOP, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getFixedSizeInBits(), llvm::EVT::getIntegerVT(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::EVT::getStoreSize(), llvm::EVT::getVectorElementCount(), llvm::SelectionDAG::getVScale(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::EVT::isScalableVector(), llvm::ISD::MUL, llvm::report_fatal_error(), and llvm::ISD::ZERO_EXTEND.

◆ initializeSplitCSR()

virtual void llvm::TargetLowering::initializeSplitCSR ( MachineBasicBlock * Entry ) const

inlinevirtual

Perform necessary initialization to handle a subset of CSRs explicitly via copies.

This function is called at the beginning of instruction selection.

Reimplemented in llvm::AArch64TargetLowering, and llvm::SITargetLowering.

Definition at line 4409 of file TargetLowering.h.

References llvm_unreachable.

Referenced by llvm::SelectionDAGISel::runOnMachineFunction().

◆ insertCopiesSplitCSR()

virtual void llvm::TargetLowering::insertCopiesSplitCSR	(	MachineBasicBlock *	Entry,
		const SmallVectorImpl< MachineBasicBlock * > &	Exits
	)		const

inlinevirtual

Insert explicit copies in entry and exit blocks.

We copy a subset of CSRs to virtual registers in the entry block, and copy them back to physical registers in the exit blocks. This function is called at the end of instruction selection.

Reimplemented in llvm::AArch64TargetLowering, and llvm::SITargetLowering.

Definition at line 4417 of file TargetLowering.h.

References llvm_unreachable.

Referenced by llvm::SelectionDAGISel::runOnMachineFunction().

◆ isConstFalseVal()

bool TargetLowering::isConstFalseVal ( SDValue N ) const

Return if the N is a constant or constant vector equal to the false value from getBooleanContents().

Definition at line 3982 of file TargetLowering.cpp.

References llvm::ConstantSDNode::getAPIntValue(), llvm::TargetLoweringBase::getBooleanContents(), llvm::BuildVectorSDNode::getConstantSplatNode(), llvm::ConstantSDNode::isZero(), N, and llvm::TargetLoweringBase::UndefinedBooleanContent.

◆ isConstTrueVal()

bool TargetLowering::isConstTrueVal ( SDValue N ) const

Return if the N is a constant or constant vector equal to the true value from getBooleanContents().

Definition at line 3952 of file TargetLowering.cpp.

References llvm::APInt::getBitWidth(), llvm::TargetLoweringBase::getBooleanContents(), llvm::APInt::isAllOnes(), llvm::isConstOrConstSplat(), llvm::APInt::isOne(), llvm_unreachable, N, llvm::APInt::trunc(), llvm::TargetLoweringBase::UndefinedBooleanContent, llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, and llvm::TargetLoweringBase::ZeroOrOneBooleanContent.

Referenced by PerformXORCombine().

◆ isDesirableToCombineLogicOpOfSETCC()

virtual AndOrSETCCFoldKind llvm::TargetLowering::isDesirableToCombineLogicOpOfSETCC	(	const SDNode *	LogicOp,
		const SDNode *	SETCC0,
		const SDNode *	SETCC1
	)		const

inlinevirtual

Reimplemented in llvm::X86TargetLowering.

Definition at line 4351 of file TargetLowering.h.

References llvm::TargetLoweringBase::None.

Referenced by foldAndOrOfSETCC().

◆ isDesirableToCommuteWithShift() [1/2]

virtual bool llvm::TargetLowering::isDesirableToCommuteWithShift	(	const MachineInstr &	MI,
		bool	IsAfterLegal
	)		const

inlinevirtual

GlobalISel - return true if it is profitable to move this shift by a constant amount through its operand, adjusting any immediate operands as necessary to preserve semantics.

This transformation may not be desirable if it disrupts a particularly auspicious target-specific tree (e.g. bitfield extraction in AArch64). By default, it returns true.

Parameters

MI	the shift instruction
IsAfterLegal	true if running after legalization.

Definition at line 4322 of file TargetLowering.h.

◆ isDesirableToCommuteWithShift() [2/2]

virtual bool llvm::TargetLowering::isDesirableToCommuteWithShift	(	const SDNode *	N,
		CombineLevel	Level
	)		const

inlinevirtual

Return true if it is profitable to move this shift by a constant amount through its operand, adjusting any immediate operands as necessary to preserve semantics.

This transformation may not be desirable if it disrupts a particularly auspicious target-specific tree (e.g. bitfield extraction in AArch64). By default, it returns true.

Parameters

N	the shift node
Level	the current DAGCombine legalization level.

Reimplemented in llvm::AArch64TargetLowering, llvm::AMDGPUTargetLowering, llvm::ARMTargetLowering, and llvm::RISCVTargetLowering.

Definition at line 4303 of file TargetLowering.h.

References llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::hasOneUse(), N, and llvm::ISD::SIGN_EXTEND.

◆ isDesirableToCommuteXorWithShift()

virtual bool llvm::TargetLowering::isDesirableToCommuteXorWithShift ( const SDNode * N ) const

inlinevirtual

Return true if it is profitable to combine an XOR of a logical shift to create a logical shift of NOT.

This transformation may not be desirable if it disrupts a particularly auspicious target-specific tree (e.g. BIC on ARM/AArch64). By default, it returns true.

Reimplemented in llvm::AArch64TargetLowering, and llvm::ARMTargetLowering.

Definition at line 4360 of file TargetLowering.h.

◆ IsDesirableToPromoteOp()

virtual bool llvm::TargetLowering::IsDesirableToPromoteOp	(	SDValue	,
		EVT &
	)		const

inlinevirtual

This method query the target whether it is beneficial for dag combiner to promote the specified node.

If true, it should return the desired promotion type by reference.

Reimplemented in llvm::X86TargetLowering.

Definition at line 4384 of file TargetLowering.h.

◆ isDesirableToPullExtFromShl()

virtual bool llvm::TargetLowering::isDesirableToPullExtFromShl ( const MachineInstr & MI ) const

inlinevirtual

GlobalISel - return true if it's profitable to perform the combine: shl ([sza]ext x), y => zext (shl x, y)

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 4329 of file TargetLowering.h.

◆ isDesirableToTransformToIntegerOp()

virtual bool llvm::TargetLowering::isDesirableToTransformToIntegerOp	(	unsigned	,
		EVT
	)		const

inlinevirtual

Return true if it is profitable for dag combiner to transform a floating point op of specified opcode to a equivalent op of an integer type.

e.g. f32 load -> i32 load can be profitable on ARM.

Reimplemented in llvm::ARMTargetLowering, and llvm::PPCTargetLowering.

Definition at line 4376 of file TargetLowering.h.

◆ isExtendedTrueVal()

bool TargetLowering::isExtendedTrueVal	(	const ConstantSDNode *	N,
		EVT	VT,
		bool	SExt
	)		const

Return if N is a True value when extended to VT.

Definition at line 4006 of file TargetLowering.cpp.

References llvm::TargetLoweringBase::getBooleanContents(), llvm_unreachable, N, llvm::TargetLoweringBase::UndefinedBooleanContent, llvm::TargetLoweringBase::ZeroOrNegativeOneBooleanContent, and llvm::TargetLoweringBase::ZeroOrOneBooleanContent.

◆ isGAPlusOffset()

bool TargetLowering::isGAPlusOffset	(	SDNode *	N,
		const GlobalValue *&	GA,
		int64_t &	Offset
	)		const

virtual

Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.

Definition at line 5485 of file TargetLowering.cpp.

References llvm::ISD::ADD, llvm::SDValue::getNode(), N, and llvm::Offset.

Referenced by llvm::SelectionDAG::InferPtrAlign(), and isConsecutiveLSLoc().

◆ isGuaranteedNotToBeUndefOrPoisonForTargetNode()

bool TargetLowering::isGuaranteedNotToBeUndefOrPoisonForTargetNode	(	SDValue	Op,
		const APInt &	DemandedElts,
		const SelectionDAG &	DAG,
		bool	PoisonOnly,
		unsigned	Depth
	)		const

virtual

Return true if this function can prove that Op is never poison and, if PoisonOnly is false, does not have undef bits.

The DemandedElts argument limits the check to the requested vector elements.

Reimplemented in llvm::SystemZTargetLowering, and llvm::X86TargetLowering.

Definition at line 3888 of file TargetLowering.cpp.

References llvm::all_of(), assert(), llvm::ISD::BUILTIN_OP_END, llvm::Depth, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, and PoisonOnly.

Referenced by llvm::SelectionDAG::isGuaranteedNotToBeUndefOrPoison(), and llvm::X86TargetLowering::isGuaranteedNotToBeUndefOrPoisonForTargetNode().

◆ isIndexingLegal()

virtual bool llvm::TargetLowering::isIndexingLegal	(	MachineInstr &	MI,
		Register	Base,
		Register	Offset,
		bool	IsPre,
		MachineRegisterInfo &	MRI
	)		const

inlinevirtual

Returns true if the specified base+offset is a legal indexed addressing mode for this target.

MI is the load or store instruction that is being considered for transformation.

Definition at line 3848 of file TargetLowering.h.

◆ isInlineAsmTargetBranch()

virtual bool llvm::TargetLowering::isInlineAsmTargetBranch	(	const SmallVectorImpl< StringRef > &	AsmStrs,
		unsigned	OpNo
	)		const

inlinevirtual

On x86, return true if the operand with index OpNo is a CALL or JUMP instruction, which can use either a memory constraint or an address constraint.

-fasm-blocks "__asm call foo" lowers to call void asm sideeffect inteldialect "call ${0:P}", "*m..."

This function is used by a hack to choose the address constraint, lowering to a direct call.

Reimplemented in llvm::X86TargetLowering.

Definition at line 3890 of file TargetLowering.h.

◆ isInTailCallPosition()

bool TargetLowering::isInTailCallPosition	(	SelectionDAG &	DAG,
		SDNode *	Node,
		SDValue &	Chain
	)		const

Check whether a given call node is in tail position within its function.

If so, it sets Chain to the input chain of the tail call.

Definition at line 52 of file TargetLowering.cpp.

References llvm::AttrBuilder::contains(), F, llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::AttrBuilder::hasAttributes(), isUsedByReturnOnly(), and llvm::AttrBuilder::removeAttribute().

◆ isKnownNeverNaNForTargetNode()

bool TargetLowering::isKnownNeverNaNForTargetNode	(	SDValue	Op,
		const SelectionDAG &	DAG,
		bool	SNaN = `false`,
		unsigned	Depth = `0`
	)		const

virtual

If SNaN is false,.

Returns: true if Op is known to never be any NaN. If sNaN is true, returns if Op is known to never be a signaling NaN.

Reimplemented in llvm::AMDGPUTargetLowering, and llvm::SITargetLowering.

Definition at line 3922 of file TargetLowering.cpp.

References assert(), llvm::ISD::BUILTIN_OP_END, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, and llvm::ISD::INTRINSIC_WO_CHAIN.

Referenced by llvm::SelectionDAG::isKnownNeverNaN().

◆ isOffsetFoldingLegal()

bool TargetLowering::isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const

virtual

Return true if folding a constant offset with the given GlobalAddress is legal.

It is frequently not legal in PIC relocation models.

Reimplemented in llvm::AArch64TargetLowering, llvm::SITargetLowering, llvm::ARMTargetLowering, llvm::AVRTargetLowering, llvm::BPFTargetLowering, llvm::HexagonTargetLowering, llvm::LoongArchTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::SparcTargetLowering, llvm::VETargetLowering, and llvm::XtensaTargetLowering.

Definition at line 489 of file TargetLowering.cpp.

References llvm::GlobalAddressSDNode::getGlobal(), and llvm::TargetLoweringBase::getTargetMachine().

Referenced by llvm::SelectionDAG::FoldSymbolOffset(), and llvm::SelectionDAG::isConstantIntBuildVectorOrConstantInt().

◆ isPositionIndependent()

bool TargetLowering::isPositionIndependent ( ) const

Definition at line 46 of file TargetLowering.cpp.

References llvm::TargetLoweringBase::getTargetMachine(), and llvm::TargetMachine::isPositionIndependent().

◆ isReassocProfitable() [1/2]

virtual bool llvm::TargetLowering::isReassocProfitable	(	MachineRegisterInfo &	MRI,
		Register	N0,
		Register	N1
	)		const

inlinevirtual

Reimplemented in llvm::AMDGPUTargetLowering, and llvm::SITargetLowering.

Definition at line 3815 of file TargetLowering.h.

References MRI.

◆ isReassocProfitable() [2/2]

virtual bool llvm::TargetLowering::isReassocProfitable	(	SelectionDAG &	DAG,
		SDValue	N0,
		SDValue	N1
	)		const

inlinevirtual

Reimplemented in llvm::AArch64TargetLowering, and llvm::SITargetLowering.

Definition at line 3804 of file TargetLowering.h.

References llvm::SDValue::hasOneUse().

Referenced by llvm::CombinerHelper::tryReassocBinOp().

◆ isSDNodeAlwaysUniform()

virtual bool llvm::TargetLowering::isSDNodeAlwaysUniform ( const SDNode * N ) const

inlinevirtual

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 3820 of file TargetLowering.h.

Referenced by llvm::SelectionDAG::calculateDivergence().

◆ isSDNodeSourceOfDivergence()

virtual bool llvm::TargetLowering::isSDNodeSourceOfDivergence	(	const SDNode *	N,
		FunctionLoweringInfo *	FLI,
		UniformityInfo *	UA
	)		const

inlinevirtual

Reimplemented in llvm::SITargetLowering.

Definition at line 3792 of file TargetLowering.h.

Referenced by llvm::SelectionDAG::calculateDivergence(), and llvm::SelectionDAG::getRegister().

◆ isSplatValueForTargetNode()

bool TargetLowering::isSplatValueForTargetNode	(	SDValue	Op,
		const APInt &	DemandedElts,
		APInt &	UndefElts,
		const SelectionDAG &	DAG,
		unsigned	Depth = `0`
	)		const

virtual

Return true if vector Op has the same value across all DemandedElts, indicating any elements which may be undef in the output UndefElts.

Reimplemented in llvm::X86TargetLowering.

Definition at line 3935 of file TargetLowering.cpp.

References assert(), llvm::ISD::BUILTIN_OP_END, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, and llvm::ISD::INTRINSIC_WO_CHAIN.

Referenced by llvm::SelectionDAG::isSplatValue(), and llvm::X86TargetLowering::isSplatValueForTargetNode().

◆ isTargetCanonicalConstantNode()

virtual bool llvm::TargetLowering::isTargetCanonicalConstantNode ( SDValue Op ) const

inlinevirtual

Returns true if the given Opc is considered a canonical constant for the target, which should not be transformed back into a BUILD_VECTOR.

Reimplemented in llvm::HexagonTargetLowering, and llvm::X86TargetLowering.

Definition at line 4223 of file TargetLowering.h.

References llvm::ISD::SPLAT_VECTOR, and llvm::ISD::SPLAT_VECTOR_PARTS.

Referenced by llvm::HexagonTargetLowering::isTargetCanonicalConstantNode(), and llvm::X86TargetLowering::isTargetCanonicalConstantNode().

◆ isTypeDesirableForOp()

virtual bool llvm::TargetLowering::isTypeDesirableForOp	(	unsigned	,
		EVT	VT
	)		const

inlinevirtual

Return true if the target has native support for the specified value type and it is 'desirable' to use the type for the given node type.

e.g. On x86 i16 is legal, but undesirable since i16 instruction encodings are longer and some i16 instructions are slow.

Reimplemented in llvm::SITargetLowering, llvm::AArch64TargetLowering, and llvm::X86TargetLowering.

Definition at line 4368 of file TargetLowering.h.

References llvm::TargetLoweringBase::isTypeLegal().

Referenced by foldToSaturated(), llvm::SITargetLowering::isTypeDesirableForOp(), and llvm::AArch64TargetLowering::isTypeDesirableForOp().

◆ isUsedByReturnOnly()

virtual bool llvm::TargetLowering::isUsedByReturnOnly	(	SDNode *	,
		SDValue &
	)		const

inlinevirtual

Return true if result of the specified node is used by a return node only.

It also compute and return the input chain for the tail call.

This is used to determine whether it is possible to codegen a libcall as tail call at legalization time.

Reimplemented in llvm::LoongArchTargetLowering, and llvm::RISCVTargetLowering.

Definition at line 4807 of file TargetLowering.h.

Referenced by isInTailCallPosition().

◆ isXAndYEqZeroPreferableToXAndYEqY()

virtual bool llvm::TargetLowering::isXAndYEqZeroPreferableToXAndYEqY	(	ISD::CondCode	,
		EVT
	)		const

inlinevirtual

Reimplemented in llvm::X86TargetLowering.

Definition at line 5613 of file TargetLowering.h.

◆ joinRegisterPartsIntoValue()

virtual SDValue llvm::TargetLowering::joinRegisterPartsIntoValue	(	SelectionDAG &	DAG,
		const SDLoc &	DL,
		const SDValue *	Parts,
		unsigned	NumParts,
		MVT	PartVT,
		EVT	ValueVT,
		std::optional< CallingConv::ID >	CC
	)		const

inlinevirtual

Target-specific combining of register parts into its original value.

Reimplemented in llvm::RISCVTargetLowering, and llvm::SystemZTargetLowering.

Definition at line 4499 of file TargetLowering.h.

Referenced by getCopyFromParts().

◆ LegalizeSetCCCondCode()

bool TargetLowering::LegalizeSetCCCondCode	(	SelectionDAG &	DAG,
		EVT	VT,
		SDValue &	LHS,
		SDValue &	RHS,
		SDValue &	CC,
		SDValue	Mask,
		SDValue	EVL,
		bool &	NeedInvert,
		const SDLoc &	dl,
		SDValue &	Chain,
		bool	IsSignaling = `false`
	)		const

Legalize a SETCC or VP_SETCC with given LHS and RHS and condition code CC on the current target.

A VP_SETCC will additionally be given a Mask and/or EVL not equal to SDValue().

If the SETCC has been legalized using AND / OR, then the legalized node will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert will be set to false. This will also hold if the VP_SETCC has been legalized using VP_AND / VP_OR.

If the SETCC / VP_SETCC has been legalized by using getSetCCSwappedOperands(), then the values of LHS and RHS will be swapped, CC will be set to the new condition, and NeedInvert will be set to false.

If the SETCC / VP_SETCC has been legalized using the inverse condcode, then LHS and RHS will be unchanged, CC will set to the inverted condcode, and NeedInvert will be set to true. The caller must invert the result of the SETCC with SelectionDAG::getLogicalNOT() or take equivalent action to swap the effect of a true/false result.

Returns: true if the SETCC / VP_SETCC has been legalized, false if it hasn't.

Definition at line 11851 of file TargetLowering.cpp.

References llvm::ISD::AND, assert(), CC, llvm::TargetLoweringBase::Expand, llvm::SelectionDAG::getCondCode(), llvm::TargetLoweringBase::getCondCodeAction(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SelectionDAG::getSetCC(), llvm::ISD::getSetCCSwappedOperands(), llvm::SelectionDAG::getSetCCVP(), llvm::SDValue::getValue(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::TargetLoweringBase::isCondCodeLegal(), llvm::TargetLoweringBase::isCondCodeLegalOrCustom(), llvm::MVT::isInteger(), llvm::TargetLoweringBase::Legal, LHS, llvm_unreachable, llvm::ISD::OR, RHS, llvm::ISD::SETCC_INVALID, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, std::swap(), llvm::ISD::TokenFactor, and llvm::ISD::XOR.

◆ LowerAsmOperandForConstraint()

void TargetLowering::LowerAsmOperandForConstraint	(	SDValue	Op,
		StringRef	Constraint,
		std::vector< SDValue > &	Ops,
		SelectionDAG &	DAG
	)		const

virtual

Lower the specified operand into the Ops vector.

If it is invalid, don't add anything to Ops.

Reimplemented in llvm::SITargetLowering, llvm::ARMTargetLowering, llvm::AVRTargetLowering, llvm::LanaiTargetLowering, llvm::M68kTargetLowering, llvm::NVPTXTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::SparcTargetLowering, llvm::SystemZTargetLowering, llvm::X86TargetLowering, and llvm::XtensaTargetLowering.

Definition at line 5588 of file TargetLowering.cpp.

References llvm::ISD::ADD, llvm::CallingConv::C, llvm::TargetLoweringBase::getBooleanContents(), llvm::TargetLoweringBase::getExtendForContent(), llvm::SelectionDAG::getTargetBlockAddress(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::Offset, llvm::ISD::SIGN_EXTEND, llvm::StringRef::size(), llvm::ISD::SUB, and llvm::ISD::ZERO_EXTEND.

◆ LowerAsmOutputForConstraint()

SDValue TargetLowering::LowerAsmOutputForConstraint	(	SDValue &	Chain,
		SDValue &	Glue,
		const SDLoc &	DL,
		const AsmOperandInfo &	OpInfo,
		SelectionDAG &	DAG
	)		const

virtual

Reimplemented in llvm::X86TargetLowering.

Definition at line 5580 of file TargetLowering.cpp.

◆ LowerCall()

virtual SDValue llvm::TargetLowering::LowerCall	(	CallLoweringInfo &	,
		SmallVectorImpl< SDValue > &
	)		const

inlinevirtual

This hook must be implemented to lower calls into the specified DAG.

The outgoing arguments to the call are described by the Outs array, and the values to be returned by the call are described by the Ins array. The implementation should fill in the InVals array with legal-type return values from the call, and return the resulting token chain value.

Reimplemented in llvm::AMDGPUTargetLowering, llvm::SITargetLowering, llvm::NVPTXTargetLowering, llvm::SystemZTargetLowering, llvm::XtensaTargetLowering, llvm::HexagonTargetLowering, llvm::LoongArchTargetLowering, llvm::RISCVTargetLowering, llvm::SparcTargetLowering, and llvm::VETargetLowering.

Definition at line 4770 of file TargetLowering.h.

References llvm_unreachable.

Referenced by LowerCallTo().

◆ LowerCallTo()

std::pair< SDValue, SDValue > TargetLowering::LowerCallTo ( TargetLowering::CallLoweringInfo & CLI ) const

This function lowers an abstract call to a function into an actual call.

TargetLowering::LowerCallTo - This is the default LowerCallTo implementation, which just calls LowerCall.

This returns a pair of operands. The first element is the return value for the function (if RetTy is not VoidTy). The second element is the outgoing token chain. It calls LowerCall to do the actual lowering.

FIXME: When all targets are migrated to using LowerCall, this hook should be integrated into SDISel.

Definition at line 10979 of file SelectionDAGBuilder.cpp.

◆ lowerCmpEqZeroToCtlzSrl()

SDValue TargetLowering::lowerCmpEqZeroToCtlzSrl	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

Definition at line 10531 of file TargetLowering.cpp.

References assert(), llvm::EVT::bitsLT(), CC, llvm::ISD::CTLZ, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::TargetLoweringBase::isCtlzFast(), llvm::isNullConstant(), llvm::Log2_32(), llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SRL, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.

◆ LowerCustomJumpTableEntry()

virtual const MCExpr * llvm::TargetLowering::LowerCustomJumpTableEntry	(	const MachineJumpTableInfo *	,
		const MachineBasicBlock *	,
		unsigned	,
		MCContext &
	)		const

inlinevirtual

Reimplemented in llvm::M68kTargetLowering, llvm::RISCVTargetLowering, llvm::VETargetLowering, and llvm::X86TargetLowering.

Definition at line 3862 of file TargetLowering.h.

References llvm_unreachable.

◆ LowerFormalArguments()

virtual SDValue llvm::TargetLowering::LowerFormalArguments	(	SDValue	,
		CallingConv::ID	,
		bool	,
		const SmallVectorImpl< ISD::InputArg > &	,
		const SDLoc &	,
		SelectionDAG &	,
		SmallVectorImpl< SDValue > &
	)		const

inlinevirtual

This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array, into the specified DAG.

The implementation should fill in the InVals array with legal-type argument values, and return the resulting token chain value.

Reimplemented in llvm::R600TargetLowering, llvm::SITargetLowering, llvm::HexagonTargetLowering, llvm::LoongArchTargetLowering, llvm::NVPTXTargetLowering, llvm::RISCVTargetLowering, llvm::SparcTargetLowering, llvm::SystemZTargetLowering, llvm::VETargetLowering, and llvm::XtensaTargetLowering.

Definition at line 4510 of file TargetLowering.h.

References llvm_unreachable.

◆ LowerOperation()

SDValue TargetLowering::LowerOperation	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

virtual

This callback is invoked for operations that are unsupported by the target, which are registered to use 'custom' lowering, and whose defined values are all legal.

If the target has no operations that require custom lowering, it need not implement this. The default implementation of this aborts.

Definition at line 11393 of file SelectionDAGBuilder.cpp.

References llvm_unreachable.

Referenced by LowerOperationWrapper().

◆ LowerOperationWrapper()

void TargetLowering::LowerOperationWrapper	(	SDNode *	N,
		SmallVectorImpl< SDValue > &	Results,
		SelectionDAG &	DAG
	)		const

virtual

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types.

Places new result values for the node in Results (their number and types must exactly match those of the original return values of the node), or leaves Results empty, which indicates that the node is not to be custom lowered after all.

It replaces the LowerOperation callback in the type Legalizer. The reason we can not do away with LowerOperation entirely is that LegalizeDAG isn't yet ready to use this callback.

TODO: Consider merging with ReplaceNodeResults.

The target places new result values for the node in Results (their number and types must exactly match those of the original return values of the node), or leaves Results empty, which indicates that the node is not to be custom lowered after all. The default implementation calls LowerOperation.

Reimplemented in llvm::HexagonTargetLowering, and llvm::SystemZTargetLowering.

Definition at line 11368 of file SelectionDAGBuilder.cpp.

References assert(), llvm::SDValue::getNode(), llvm::SDNode::getNumValues(), llvm::SDValue::getValue(), I, LowerOperation(), N, and Results.

Referenced by llvm::HexagonTargetLowering::LowerOperationWrapper(), and llvm::MipsTargetLowering::ReplaceNodeResults().

◆ LowerReturn()

virtual SDValue llvm::TargetLowering::LowerReturn	(	SDValue	,
		CallingConv::ID	,
		bool	,
		const SmallVectorImpl< ISD::OutputArg > &	,
		const SmallVectorImpl< SDValue > &	,
		const SDLoc &	,
		SelectionDAG &
	)		const

inlinevirtual

This hook must be implemented to lower outgoing return values, described by the Outs array, into the specified DAG.

The implementation should return the resulting token chain value.

Reimplemented in llvm::AMDGPUTargetLowering, llvm::SITargetLowering, llvm::HexagonTargetLowering, llvm::LoongArchTargetLowering, llvm::NVPTXTargetLowering, llvm::RISCVTargetLowering, llvm::SparcTargetLowering, llvm::SystemZTargetLowering, llvm::VETargetLowering, and llvm::XtensaTargetLowering.

Definition at line 4793 of file TargetLowering.h.

References llvm_unreachable.

◆ LowerToTLSEmulatedModel()

SDValue TargetLowering::LowerToTLSEmulatedModel	(	const GlobalAddressSDNode *	GA,
		SelectionDAG &	DAG
	)		const

virtual

Lower TLS global address SDNode for target independent emulated TLS model.

Definition at line 10491 of file TargetLowering.cpp.

References assert(), llvm::CallingConv::C, llvm::PointerType::get(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getExternalSymbol(), llvm::MachineFunction::getFrameInfo(), llvm::GlobalAddressSDNode::getGlobal(), llvm::SelectionDAG::getGlobalAddress(), llvm::SelectionDAG::getMachineFunction(), llvm::Value::getName(), llvm::Module::getNamedGlobal(), llvm::GlobalAddressSDNode::getOffset(), llvm::GlobalValue::getParent(), llvm::TargetLoweringBase::getPointerTy(), llvm::MachineFrameInfo::setAdjustsStack(), llvm::TargetLowering::CallLoweringInfo::setChain(), llvm::TargetLowering::CallLoweringInfo::setDebugLoc(), llvm::MachineFrameInfo::setHasCalls(), llvm::TargetLowering::CallLoweringInfo::setLibCallee(), and llvm::Value::stripPointerCastsAndAliases().

Referenced by llvm::SparcTargetLowering::LowerGlobalTLSAddress().

◆ LowerXConstraint()

const char * TargetLowering::LowerXConstraint ( EVT ConstraintVT ) const

virtual

Try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand.

This returns null if there is no replacement to make.

Reimplemented in llvm::ARMTargetLowering, and llvm::X86TargetLowering.

Definition at line 5572 of file TargetLowering.cpp.

References llvm::EVT::isFloatingPoint(), and llvm::EVT::isInteger().

Referenced by computeConstraintToUse(), and llvm::X86TargetLowering::LowerXConstraint().

◆ makeLibCall()

std::pair< SDValue, SDValue > TargetLowering::makeLibCall	(	SelectionDAG &	DAG,
		RTLIB::Libcall	LC,
		EVT	RetVT,
		ArrayRef< SDValue >	Ops,
		MakeLibCallOptions	CallOptions,
		const SDLoc &	dl,
		SDValue	Chain = `SDValue()`
	)		const

Returns a pair of (return value, chain).

Generate a libcall taking the given operands as arguments and returning a result of type RetVT.

It is an error to pass RTLIB::UNKNOWN_LIBCALL as LC.

Definition at line 146 of file TargetLowering.cpp.

Referenced by llvm::RISCVTargetLowering::LowerOperation(), llvm::LoongArchTargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::ReplaceNodeResults(), and llvm::SelectionDAGBuilder::visitSPDescriptorFailure().

◆ mayBeEmittedAsTailCall()

virtual bool llvm::TargetLowering::mayBeEmittedAsTailCall ( const CallInst * ) const

inlinevirtual

Return true if the target may be able emit the call instruction as a tail call.

This is used by optimization passes to determine if it's profitable to duplicate return instructions to enable tailcall optimization.

Reimplemented in llvm::SITargetLowering, llvm::HexagonTargetLowering, llvm::LoongArchTargetLowering, llvm::RISCVTargetLowering, and llvm::SystemZTargetLowering.

Definition at line 4814 of file TargetLowering.h.

◆ operator=()

TargetLowering & llvm::TargetLowering::operator= ( const TargetLowering & )

delete

◆ parametersInCSRMatch()

bool TargetLowering::parametersInCSRMatch	(	const MachineRegisterInfo &	MRI,
		const uint32_t *	CallerPreservedMask,
		const SmallVectorImpl< CCValAssign > &	ArgLocs,
		const SmallVectorImpl< SDValue > &	OutVals
	)		const

Check whether parameters to a call that are passed in callee saved registers are the same as from the calling function.

This needs to be checked for tail call eligibility.

Definition at line 82 of file TargetLowering.cpp.

References llvm::ISD::AssertZext, llvm::MachineOperand::clobbersPhysReg(), llvm::ISD::CopyFromReg, llvm::CCValAssign::getLocReg(), I, llvm::CCValAssign::isRegLoc(), MRI, and llvm::SmallVectorBase< Size_T >::size().

Referenced by llvm::SITargetLowering::isEligibleForTailCallOptimization().

◆ ParseConstraints()

TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints	(	const DataLayout &	DL,
		const TargetRegisterInfo *	TRI,
		const CallBase &	Call
	)		const

virtual

Split up the constraint string from the inline assembly value into the specific constraints and their prefixes, and also tie in the associated operand values.

If this returns an empty vector, and if the constraint string itself isn't empty, there was an error parsing.

Information about all of the constraints.

Definition at line 5732 of file TargetLowering.cpp.

References assert(), llvm::TargetLowering::AsmOperandInfo::CallOperandVal, llvm::TargetLowering::AsmOperandInfo::ConstraintCode, llvm::TargetLowering::AsmOperandInfo::ConstraintVT, DL, llvm::IntegerType::get(), llvm::TargetLoweringBase::getAsmOperandValueType(), llvm::Type::getContext(), llvm::EVT::getSimpleVT(), llvm::MVT::getSizeInBits(), llvm::Value::getType(), llvm::InlineAsm::ConstraintInfo::hasMatchingInput(), llvm::InlineAsm::isClobber, llvm::MVT::isFloatingPoint(), llvm::InlineAsm::ConstraintInfo::isIndirect, llvm::InlineAsm::isInput, llvm::MVT::isInteger(), llvm::InlineAsm::isLabel, llvm::InlineAsm::isOutput, llvm::EVT::isSimple(), llvm::Type::isSingleValueType(), llvm::Type::isSized(), llvm::InlineAsm::ConstraintInfo::MatchingInput, llvm::InlineAsm::ConstraintInfo::multipleAlternatives, llvm::report_fatal_error(), TRI, and llvm::InlineAsm::ConstraintInfo::Type.

Referenced by llvm::GCNTTIImpl::isInlineAsmSourceOfDivergence(), IsOperandAMemoryOperand(), llvm::InlineAsmLowering::lowerInlineAsm(), llvm::SITargetLowering::requiresUniformRegister(), and llvm::FunctionLoweringInfo::set().

◆ PerformDAGCombine()

SDValue TargetLowering::PerformDAGCombine	(	SDNode *	N,
		DAGCombinerInfo &	DCI
	)		const

virtual

This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for.

The semantics are as follows: Return Value: SDValue.Val == 0 - No change was made SDValue.Val == N - N was replaced, is dead, and is already handled. otherwise - N should be replaced by the returned Operand.

In addition, methods provided by DAGCombinerInfo may be used to perform more complex transformations.

Reimplemented in llvm::AArch64TargetLowering, llvm::AMDGPUTargetLowering, llvm::R600TargetLowering, llvm::SITargetLowering, llvm::ARMTargetLowering, llvm::HexagonTargetLowering, llvm::LanaiTargetLowering, llvm::LoongArchTargetLowering, llvm::MipsTargetLowering, llvm::MipsSETargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::SparcTargetLowering, llvm::SystemZTargetLowering, llvm::VETargetLowering, and llvm::X86TargetLowering.

Definition at line 5515 of file TargetLowering.cpp.

◆ prepareVolatileOrAtomicLoad()

virtual SDValue llvm::TargetLowering::prepareVolatileOrAtomicLoad	(	SDValue	Chain,
		const SDLoc &	DL,
		SelectionDAG &	DAG
	)		const

inlinevirtual

This callback is used to prepare for a volatile or atomic load.

It takes a chain node as input and returns the chain for the load itself.

Having a callback like this is necessary for targets like SystemZ, which allows a CPU to reuse the result of a previous load indefinitely, even if a cache-coherent store is performed by another CPU. The default implementation does nothing.

Definition at line 4876 of file TargetLowering.h.

◆ ReplaceNodeResults()

virtual void llvm::TargetLowering::ReplaceNodeResults	(	SDNode *	,
		SmallVectorImpl< SDValue > &	,
		SelectionDAG &
	)		const

inlinevirtual

This callback is invoked when a node result type is illegal for the target, and the operation was registered to use 'custom' lowering for that result type.

The target places new result values for the node in Results (their number and types must exactly match those of the original return values of the node), or leaves Results empty, which indicates that the node is not to be custom lowered after all.

If the target has no operations that require custom lowering, it need not implement this. The default implementation aborts.

Reimplemented in llvm::AMDGPUTargetLowering, llvm::R600TargetLowering, llvm::SITargetLowering, llvm::ARMTargetLowering, llvm::AVRTargetLowering, llvm::HexagonTargetLowering, llvm::LoongArchTargetLowering, llvm::MipsTargetLowering, llvm::PPCTargetLowering, llvm::RISCVTargetLowering, llvm::SparcTargetLowering, llvm::SystemZTargetLowering, llvm::VETargetLowering, llvm::X86TargetLowering, and llvm::XCoreTargetLowering.

Definition at line 4914 of file TargetLowering.h.

References llvm_unreachable.

◆ scalarizeVectorLoad()

std::pair< SDValue, SDValue > TargetLowering::scalarizeVectorLoad	(	LoadSDNode *	LD,
		SelectionDAG &	DAG
	)		const

Turn load of vector type into a load of the individual elements.

Parameters

LD	load to expand

Returns: BUILD_VECTOR and TokenFactor nodes.

Definition at line 9926 of file TargetLowering.cpp.

Referenced by llvm::AMDGPUTargetLowering::SplitVectorLoad().

◆ scalarizeVectorStore()

SDValue TargetLowering::scalarizeVectorStore	(	StoreSDNode *	ST,
		SelectionDAG &	DAG
	)		const

Parameters

ST	Store with a vector value type

Returns: TokenFactor of the individual store chains.

Definition at line 10015 of file TargetLowering.cpp.

Referenced by llvm::AMDGPUTargetLowering::SplitVectorStore().

◆ shouldSimplifyDemandedVectorElts()

virtual bool llvm::TargetLowering::shouldSimplifyDemandedVectorElts	(	SDValue	Op,
		const TargetLoweringOpt &	TLO
	)		const

inlinevirtual

Return true if the target supports simplifying demanded vector elements by converting them to undefs.

Definition at line 4091 of file TargetLowering.h.

◆ shouldSplitFunctionArgumentsAsLittleEndian()

virtual bool llvm::TargetLowering::shouldSplitFunctionArgumentsAsLittleEndian ( const DataLayout & DL ) const

inlinevirtual

For most targets, an LLVM type must be broken down into multiple smaller types.

Usually the halves are ordered according to the endianness but for some platform that would break. So this method will default to matching the endianness but can be overridden.

Reimplemented in llvm::AVRTargetLowering.

Definition at line 4853 of file TargetLowering.h.

References DL.

◆ ShrinkDemandedConstant() [1/2]

bool TargetLowering::ShrinkDemandedConstant	(	SDValue	Op,
		const APInt &	DemandedBits,
		const APInt &	DemandedElts,
		TargetLoweringOpt &	TLO
	)		const

Check to see if the specified operand of the specified instruction is a constant integer.

If the specified instruction has a constant integer operand and there are bits set in that constant that are not demanded, then clear those bits and return true.

If so, check to see if there are any bits set in the constant that are not demanded. If so, shrink the constant and return true.

Definition at line 513 of file TargetLowering.cpp.

References llvm::ISD::AND, llvm::CallingConv::C, llvm::TargetLowering::TargetLoweringOpt::CombineTo(), llvm::TargetLowering::TargetLoweringOpt::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::APInt::isZero(), llvm::TargetLowering::TargetLoweringOpt::New, llvm::ISD::OR, and llvm::ISD::XOR.

Referenced by llvm::AMDGPUTargetLowering::PerformDAGCombine(), and llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode().

◆ ShrinkDemandedConstant() [2/2]

bool TargetLowering::ShrinkDemandedConstant	(	SDValue	Op,
		const APInt &	DemandedBits,
		TargetLoweringOpt &	TLO
	)		const

Helper wrapper around ShrinkDemandedConstant, demanding all elements.

Definition at line 560 of file TargetLowering.cpp.

References llvm::APInt::getAllOnes(), llvm::EVT::getVectorNumElements(), llvm::EVT::isVector(), and ShrinkDemandedConstant().

◆ ShrinkDemandedOp()

bool TargetLowering::ShrinkDemandedOp	(	SDValue	Op,
		unsigned	BitWidth,
		const APInt &	DemandedBits,
		TargetLoweringOpt &	TLO
	)		const

Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.

This uses isTruncateFree/isZExtFree and ANY_EXTEND for the widening cast, but it could be generalized for targets with other types of implicit widening casts.

Definition at line 574 of file TargetLowering.cpp.

References llvm::ISD::ANY_EXTEND, assert(), llvm::bit_ceil(), llvm::BitWidth, llvm::TargetLowering::TargetLoweringOpt::CombineTo(), llvm::TargetLowering::TargetLoweringOpt::DAG, llvm::SDNodeFlags::Disjoint, llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::DWARFExpression::Operation::getNumOperands(), llvm::TargetLoweringBase::isTruncateFree(), llvm::EVT::isVector(), llvm::TargetLoweringBase::isZExtFree(), llvm::NextPowerOf2(), llvm::SDNodeFlags::None, llvm::ISD::TRUNCATE, and X.

◆ SimplifyDemandedBits() [1/4]

bool TargetLowering::SimplifyDemandedBits	(	SDValue	Op,
		const APInt &	DemandedBits,
		const APInt &	DemandedElts,
		DAGCombinerInfo &	DCI
	)		const

Helper wrapper around SimplifyDemandedBits.

Adds Op back to the worklist upon success.

Definition at line 639 of file TargetLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::TargetLowering::DAGCombinerInfo::CommitTargetLoweringOpt(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), and llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps().

◆ SimplifyDemandedBits() [2/4]

bool TargetLowering::SimplifyDemandedBits	(	SDValue	Op,
		const APInt &	OriginalDemandedBits,
		const APInt &	OriginalDemandedElts,
		KnownBits &	Known,
		TargetLoweringOpt &	TLO,
		unsigned	Depth = `0`,
		bool	AssumeSingleUse = `false`
	)		const

Look at Op.

At this point, we know that only the DemandedBits bits of the result of Op are ever used downstream. If we can use this information to simplify Op, create a new simplified DAG node and return true, returning the original and new nodes in Old and New. Otherwise, analyze the expression and return a mask of KnownOne and KnownZero bits for the expression (used to simplify the caller). The KnownZero/One bits may only be accurate for those bits in the Demanded masks. AssumeSingleUse When this parameter is true, this function will attempt to simplify Op even if there are multiple uses. Callers are responsible for correctly updating the DAG based on the results of this function, because simply replacing TLO.Old with TLO.New will be incorrect when this parameter is true and TLO.Old has multiple uses.

At this point, we know that only the OriginalDemandedBits of the result of Op are ever used downstream. If we can use this information to simplify Op, create a new simplified DAG node and return true, returning the original and new nodes in Old and New. Otherwise, analyze the expression and return a mask of Known bits for the expression (used to simplify the caller). The Known bits may only be accurate for those bits in the OriginalDemandedBits and OriginalDemandedElts.

Definition at line 1133 of file TargetLowering.cpp.

Referenced by combineAnd(), combineAndnp(), combineBEXTR(), combineBT(), combineExtractVectorElt(), combineGatherScatter(), combineMaskedLoad(), combineMaskedStore(), combineMOVMSK(), combinePDEP(), combinePMULDQ(), combineTESTP(), combineVectorInsert(), combineVectorShiftImm(), combineVSelectToBLENDV(), combineVTRUNC(), combineX86GatherScatter(), llvm::AArch64TargetLowering::PerformDAGCombine(), llvm::AMDGPUTargetLowering::PerformDAGCombine(), llvm::ARMTargetLowering::PerformDAGCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::ARMTargetLowering::PerformIntrinsicCombine(), PerformPREDICATE_CASTCombine(), performTBISimplification(), performVectorShiftCombine(), PerformVMOVhrCombine(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), and simplifyMul24().

◆ SimplifyDemandedBits() [3/4]

bool TargetLowering::SimplifyDemandedBits	(	SDValue	Op,
		const APInt &	DemandedBits,
		DAGCombinerInfo &	DCI
	)		const

Helper wrapper around SimplifyDemandedBits.

Adds Op back to the worklist upon success.

Definition at line 624 of file TargetLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::TargetLowering::DAGCombinerInfo::CommitTargetLoweringOpt(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), and llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps().

◆ SimplifyDemandedBits() [4/4]

bool TargetLowering::SimplifyDemandedBits	(	SDValue	Op,
		const APInt &	DemandedBits,
		KnownBits &	Known,
		TargetLoweringOpt &	TLO,
		unsigned	Depth = `0`,
		bool	AssumeSingleUse = `false`
	)		const

Helper wrapper around SimplifyDemandedBits, demanding all elements.

Adds Op back to the worklist upon success.

Definition at line 656 of file TargetLowering.cpp.

References llvm::Depth, llvm::APInt::getAllOnes(), llvm::EVT::getVectorNumElements(), and llvm::EVT::isFixedLengthVector().

◆ SimplifyDemandedBitsForTargetNode()

bool TargetLowering::SimplifyDemandedBitsForTargetNode	(	SDValue	Op,
		const APInt &	DemandedBits,
		const APInt &	DemandedElts,
		KnownBits &	Known,
		TargetLoweringOpt &	TLO,
		unsigned	Depth = `0`
	)		const

virtual

Attempt to simplify any target nodes based on the demanded bits/elts, returning true on success.

Otherwise, analyze the expression and return a mask of KnownOne and KnownZero bits for the expression (used to simplify the caller). The KnownZero/One bits may only be accurate for those bits in the Demanded masks.

Reimplemented in llvm::X86TargetLowering, and llvm::ARMTargetLowering.

Definition at line 3841 of file TargetLowering.cpp.

References assert(), llvm::ISD::BUILTIN_OP_END, llvm::TargetLowering::TargetLoweringOpt::DAG, llvm::Depth, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, and llvm::ISD::INTRINSIC_WO_CHAIN.

Referenced by llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), and llvm::ARMTargetLowering::SimplifyDemandedBitsForTargetNode().

◆ SimplifyDemandedVectorElts() [1/2]

bool TargetLowering::SimplifyDemandedVectorElts	(	SDValue	Op,
		const APInt &	DemandedEltMask,
		APInt &	KnownUndef,
		APInt &	KnownZero,
		TargetLoweringOpt &	TLO,
		unsigned	Depth = `0`,
		bool	AssumeSingleUse = `false`
	)		const

Look at Vector Op.

At this point, we know that only the DemandedElts elements of the result of Op are ever used downstream. If we can use this information to simplify Op, create a new simplified DAG node and return true, storing the original and new nodes in TLO. Otherwise, analyze the expression and return a mask of KnownUndef and KnownZero elements for the expression (used to simplify the caller). The KnownUndef/Zero elements may only be accurate for those bits in the DemandedMask. AssumeSingleUse When this parameter is true, this function will attempt to simplify Op even if there are multiple uses. Callers are responsible for correctly updating the DAG based on the results of this function, because simply replacing TLO.Old with TLO.New will be incorrect when this parameter is true and TLO.Old has multiple uses.

Definition at line 3078 of file TargetLowering.cpp.

Referenced by combineAnd(), combineAndnp(), combineCVTPH2PS(), combineKSHIFT(), combineOr(), combineShuffle(), combineVectorShiftVar(), combineVEXTRACT_STORE(), combineVPMADD(), combineX86INT_TO_FP(), PerformVMOVNCombine(), PerformVQMOVNCombine(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), and llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetShuffle().

◆ SimplifyDemandedVectorElts() [2/2]

bool TargetLowering::SimplifyDemandedVectorElts	(	SDValue	Op,
		const APInt &	DemandedElts,
		DAGCombinerInfo &	DCI
	)		const

Helper wrapper around SimplifyDemandedVectorElts.

Adds Op back to the worklist upon success.

Definition at line 3012 of file TargetLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::TargetLowering::DAGCombinerInfo::CommitTargetLoweringOpt(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), and llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalizeOps().

◆ SimplifyDemandedVectorEltsForTargetNode()

bool TargetLowering::SimplifyDemandedVectorEltsForTargetNode	(	SDValue	Op,
		const APInt &	DemandedElts,
		APInt &	KnownUndef,
		APInt &	KnownZero,
		TargetLoweringOpt &	TLO,
		unsigned	Depth = `0`
	)		const

virtual

Attempt to simplify any target nodes based on the demanded vector elements, returning true on success.

Otherwise, analyze the expression and return a mask of KnownUndef and KnownZero elements for the expression (used to simplify the caller). The KnownUndef/Zero elements may only be accurate for those bits in the DemandedMask.

Reimplemented in llvm::X86TargetLowering.

Definition at line 3829 of file TargetLowering.cpp.

References assert(), llvm::ISD::BUILTIN_OP_END, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, and llvm::ISD::INTRINSIC_WO_CHAIN.

◆ SimplifyMultipleUseDemandedBits() [1/2]

SDValue TargetLowering::SimplifyMultipleUseDemandedBits	(	SDValue	Op,
		const APInt &	DemandedBits,
		const APInt &	DemandedElts,
		SelectionDAG &	DAG,
		unsigned	Depth = `0`
	)		const

More limited version of SimplifyDemandedBits that can be used to "look through" ops that don't contribute to the DemandedBits/DemandedElts - bitwise ops etc.

Definition at line 674 of file TargetLowering.cpp.

Referenced by combineAnd(), combineMaskedLoad(), combineMaskedStore(), combinePTESTCC(), combineVSelectToBLENDV(), matchRotateSub(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), and simplifyMul24().

◆ SimplifyMultipleUseDemandedBits() [2/2]

SDValue TargetLowering::SimplifyMultipleUseDemandedBits	(	SDValue	Op,
		const APInt &	DemandedBits,
		SelectionDAG &	DAG,
		unsigned	Depth = `0`
	)		const

Helper wrapper around SimplifyMultipleUseDemandedBits, demanding all elements.

Definition at line 962 of file TargetLowering.cpp.

References llvm::Depth, llvm::APInt::getAllOnes(), llvm::EVT::getVectorNumElements(), and llvm::EVT::isFixedLengthVector().

◆ SimplifyMultipleUseDemandedBitsForTargetNode()

SDValue TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode	(	SDValue	Op,
		const APInt &	DemandedBits,
		const APInt &	DemandedElts,
		SelectionDAG &	DAG,
		unsigned	Depth
	)		const

virtual

More limited version of SimplifyDemandedBits that can be used to "look through" ops that don't contribute to the DemandedBits/DemandedElts - bitwise ops etc.

Reimplemented in llvm::X86TargetLowering.

Definition at line 3854 of file TargetLowering.cpp.

References assert(), llvm::ISD::BUILTIN_OP_END, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, and llvm::ISD::INTRINSIC_WO_CHAIN.

Referenced by llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode().

◆ SimplifyMultipleUseDemandedVectorElts()

SDValue TargetLowering::SimplifyMultipleUseDemandedVectorElts	(	SDValue	Op,
		const APInt &	DemandedElts,
		SelectionDAG &	DAG,
		unsigned	Depth = `0`
	)		const

Helper wrapper around SimplifyMultipleUseDemandedBits, demanding all bits from only some vector elements.

Definition at line 976 of file TargetLowering.cpp.

References llvm::Depth, and llvm::APInt::getAllOnes().

Referenced by combineX86ShufflesRecursively(), and llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode().

◆ SimplifySetCC()

SDValue TargetLowering::SimplifySetCC	(	EVT	VT,
		SDValue	N0,
		SDValue	N1,
		ISD::CondCode	Cond,
		bool	foldBooleans,
		DAGCombinerInfo &	DCI,
		const SDLoc &	dl
	)		const

Try to simplify a setcc built with the specified operands and cc.

If it is unable to simplify it, return a null SDValue.

Definition at line 4506 of file TargetLowering.cpp.

◆ softenSetCCOperands() [1/2]

void TargetLowering::softenSetCCOperands	(	SelectionDAG &	DAG,
		EVT	VT,
		SDValue &	NewLHS,
		SDValue &	NewRHS,
		ISD::CondCode &	CCCode,
		const SDLoc &	dl,
		const SDValue	OldLHS,
		const SDValue	OldRHS
	)		const

Soften the operands of a comparison.

This code is shared among BR_CC, SELECT_CC, and SETCC handlers.

Definition at line 291 of file TargetLowering.cpp.

◆ softenSetCCOperands() [2/2]

void TargetLowering::softenSetCCOperands	(	SelectionDAG &	DAG,
		EVT	VT,
		SDValue &	NewLHS,
		SDValue &	NewRHS,
		ISD::CondCode &	CCCode,
		const SDLoc &	DL,
		const SDValue	OldLHS,
		const SDValue	OldRHS,
		SDValue &	Chain,
		bool	IsSignaling = `false`
	)		const

Definition at line 301 of file TargetLowering.cpp.

References llvm::ISD::AND, assert(), llvm::TargetLoweringBase::getCmpLibcallCC(), llvm::TargetLoweringBase::getCmpLibcallReturnType(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSetCC(), llvm::TargetLoweringBase::getSetCCResultType(), llvm::SDValue::getValueType(), llvm::EVT::isInteger(), llvm_unreachable, llvm::ISD::OR, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::TargetLowering::MakeLibCallOptions::setTypeListBeforeSoften(), llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, and llvm::ISD::TokenFactor.

◆ splitValueIntoRegisterParts()

virtual bool llvm::TargetLowering::splitValueIntoRegisterParts	(	SelectionDAG &	DAG,
		const SDLoc &	DL,
		SDValue	Val,
		SDValue *	Parts,
		unsigned	NumParts,
		MVT	PartVT,
		std::optional< CallingConv::ID >	CC
	)		const

inlinevirtual

Target-specific splitting of values into parts that fit a register storing a legal type.

Reimplemented in llvm::PPCTargetLowering, llvm::RISCVTargetLowering, and llvm::SystemZTargetLowering.

Definition at line 4474 of file TargetLowering.h.

Referenced by getCopyToParts().

◆ supportKCFIBundles()

virtual bool llvm::TargetLowering::supportKCFIBundles ( ) const

inlinevirtual

Return true if the target supports kcfi operand bundles.

Reimplemented in llvm::AArch64TargetLowering, llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 4401 of file TargetLowering.h.

Referenced by llvm::SelectionDAGBuilder::LowerCallTo().

◆ supportPtrAuthBundles()

virtual bool llvm::TargetLowering::supportPtrAuthBundles ( ) const

inlinevirtual

Return true if the target supports ptrauth operand bundles.

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 4404 of file TargetLowering.h.

Referenced by llvm::SelectionDAGBuilder::LowerCallTo().

◆ supportSplitCSR()

virtual bool llvm::TargetLowering::supportSplitCSR ( MachineFunction * MF ) const

inlinevirtual

Return true if the target supports that a subset of CSRs for the given machine function is handled explicitly via copies.

Reimplemented in llvm::AArch64TargetLowering, and llvm::SITargetLowering.

Definition at line 4396 of file TargetLowering.h.

Referenced by llvm::SelectionDAGISel::runOnMachineFunction().

◆ supportSwiftError()

virtual bool llvm::TargetLowering::supportSwiftError ( ) const

inlinevirtual

Return true if the target supports swifterror attribute.

It optimizes loads and stores to reading and writing a specific register.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::SystemZTargetLowering, and llvm::X86TargetLowering.

Definition at line 4390 of file TargetLowering.h.

Referenced by llvm::SwiftErrorValueTracking::createEntriesInEntryBlock(), llvm::SystemZELFRegisters::getCalleeSavedRegs(), llvm::SystemZELFRegisters::getCallPreservedMask(), LowerCallTo(), llvm::SelectionDAGBuilder::LowerCallTo(), llvm::SwiftErrorValueTracking::preassignVRegs(), llvm::SwiftErrorValueTracking::propagateVRegs(), and llvm::SwiftErrorValueTracking::setFunction().

◆ targetShrinkDemandedConstant()

virtual bool llvm::TargetLowering::targetShrinkDemandedConstant	(	SDValue	Op,
		const APInt &	DemandedBits,
		const APInt &	DemandedElts,
		TargetLoweringOpt &	TLO
	)		const

inlinevirtual

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::RISCVTargetLowering, and llvm::X86TargetLowering.

Definition at line 3992 of file TargetLowering.h.

◆ unwrapAddress()

virtual SDValue llvm::TargetLowering::unwrapAddress ( SDValue N ) const

inlinevirtual

Reimplemented in llvm::X86TargetLowering.

Definition at line 4273 of file TargetLowering.h.

References N.

Referenced by matchLSNode().

◆ useLoadStackGuardNode()

virtual bool llvm::TargetLowering::useLoadStackGuardNode ( const Module & M ) const

inlinevirtual

If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::PPCTargetLowering, llvm::SparcTargetLowering, llvm::SystemZTargetLowering, and llvm::X86TargetLowering.

Definition at line 5589 of file TargetLowering.h.

Referenced by llvm::AArch64TargetLowering::useLoadStackGuardNode(), llvm::PPCTargetLowering::useLoadStackGuardNode(), llvm::SparcTargetLowering::useLoadStackGuardNode(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().

◆ verifyReturnAddressArgumentIsConstant()

bool TargetLowering::verifyReturnAddressArgumentIsConstant	(	SDValue	Op,
		SelectionDAG &	DAG
	)		const

Definition at line 7260 of file TargetLowering.cpp.

References llvm::LLVMContext::emitError(), and llvm::SelectionDAG::getContext().

Referenced by llvm::HexagonTargetLowering::LowerRETURNADDR(), llvm::MSP430TargetLowering::LowerRETURNADDR(), LowerRETURNADDR(), and lowerRETURNADDR().

◆ verifyTargetSDNode()

virtual void llvm::TargetLowering::verifyTargetSDNode ( const SDNode * N ) const

inlinevirtual

Check the given SDNode. Aborts if it is invalid.

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 4935 of file TargetLowering.h.

Referenced by VerifySDNode().

◆ visitMaskedLoad()

virtual SDValue llvm::TargetLowering::visitMaskedLoad	(	SelectionDAG &	DAG,
		const SDLoc &	DL,
		SDValue	Chain,
		MachineMemOperand *	MMO,
		SDValue &	NewLoad,
		SDValue	Ptr,
		SDValue	PassThru,
		SDValue	Mask
	)		const

inlinevirtual

Reimplemented in llvm::X86TargetLowering.

Definition at line 3909 of file TargetLowering.h.

References llvm_unreachable.

◆ visitMaskedStore()

virtual SDValue llvm::TargetLowering::visitMaskedStore	(	SelectionDAG &	DAG,
		const SDLoc &	DL,
		SDValue	Chain,
		MachineMemOperand *	MMO,
		SDValue	Ptr,
		SDValue	Val,
		SDValue	Mask
	)		const

inlinevirtual

Reimplemented in llvm::X86TargetLowering.

Definition at line 3916 of file TargetLowering.h.

References llvm_unreachable.

The documentation for this class was generated from the following files:

include/llvm/CodeGen/TargetLowering.h
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
lib/CodeGen/SelectionDAG/TargetLowering.cpp

Classes

Public Types

Public Member Functions

Additional Inherited Members

Detailed Description

Member Typedef Documentation

◆ AsmOperandInfoVector

◆ ConstraintGroup

◆ ConstraintPair

Member Enumeration Documentation

◆ ConstraintType

◆ ConstraintWeight

Constructor & Destructor Documentation

◆ TargetLowering() [1/2]

◆ TargetLowering() [2/2]

Member Function Documentation

◆ AdjustInstrPostInstrSelection()

◆ buildLegalVectorShuffle()

◆ BuildSDIV()

◆ BuildSDIVPow2()

◆ buildSDIVPow2WithCMov()

◆ BuildSREMPow2()

◆ BuildUDIV()

◆ canCreateUndefOrPoisonForTargetNode()

◆ CanLowerReturn()

◆ checkForPhysRegDependency()

◆ CollectTargetIntrinsicOperands()

◆ combineRepeatedFPDivisors()

◆ ComputeConstraintToUse()

◆ computeKnownAlignForTargetInstr()

◆ computeKnownBitsForFrameIndex()

◆ computeKnownBitsForTargetInstr()

◆ computeKnownBitsForTargetNode()

◆ computeNumSignBitsForTargetInstr()

◆ ComputeNumSignBitsForTargetNode()

◆ createFastISel()

◆ createSelectForFMINNUM_FMAXNUM()

◆ CTTZTableLookup()

◆ EmitInstrWithCustomInserter()

◆ emitStackGuardXorFP()

◆ expandABD()

◆ expandABS()

◆ expandAddSubSat()

◆ expandAVG()

◆ expandBITREVERSE()

◆ expandBSWAP()

◆ expandCMP()

◆ expandCTLZ()

◆ expandCTPOP()

◆ expandCTTZ()

◆ expandDIVREMByConstant()

◆ expandFixedPointDiv()

◆ expandFixedPointMul()

◆ expandFMINIMUM_FMAXIMUM()

◆ expandFMINIMUMNUM_FMAXIMUMNUM()

◆ expandFMINNUM_FMAXNUM()

◆ expandFP_ROUND()

◆ expandFP_TO_INT_SAT()

◆ expandFP_TO_SINT()

◆ expandFP_TO_UINT()

◆ expandFunnelShift()

◆ expandIndirectJTBranch()

◆ ExpandInlineAsm()

◆ expandIntMINMAX()

◆ expandIS_FPCLASS()

◆ expandMUL()

◆ expandMUL_LOHI()

◆ expandMULO()

◆ expandREM()

◆ expandROT()

◆ expandRoundInexactToOdd()

◆ expandSADDSUBO()

◆ expandShiftParts()

◆ expandShlSat()

◆ expandUADDSUBO()

◆ expandUINT_TO_FP()

◆ expandUnalignedLoad()

◆ expandUnalignedStore()

◆ expandVecReduce()

◆ expandVecReduceSeq()