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26 StackProtectorDescriptor::addSuccessorMBB(
34 MF->
insert(++BBI, SuccMBB);
53 if (!
MI.isCopy() && !
MI.isImplicitDef()) {
58 if (
MI.isDebugInstr())
63 switch (
MI.getOpcode()) {
64 case TargetOpcode::G_TRUNC:
65 case TargetOpcode::G_ZEXT:
66 case TargetOpcode::G_ANYEXT:
67 case TargetOpcode::G_SEXT:
68 case TargetOpcode::G_MERGE_VALUES:
69 case TargetOpcode::G_UNMERGE_VALUES:
70 case TargetOpcode::G_CONCAT_VECTORS:
71 case TargetOpcode::G_BUILD_VECTOR:
72 case TargetOpcode::G_EXTRACT:
92 if (
MI.isImplicitDef())
99 &&
"Should have a copy implying we should have 2 arguments.");
127 if (SplitPoint ==
BB->begin())
134 }
while (Previous != Start && Previous->isDebugInstr());
137 Previous->getOpcode() ==
TII.getCallFrameDestroyOpcode()) {
156 if (Previous->isCall())
158 }
while(Previous->getOpcode() !=
TII.getCallFrameSetupOpcode());
164 SplitPoint = Previous;
165 if (Previous == Start)
175 switch (InvertedTest) {
bool isTailCall(const MachineInstr &MI) const override
This is an optimization pass for GlobalISel generic memory operations.
unsigned getInvertedFPClassTest(unsigned Test)
Evaluates if the specified FP class test is an inversion of a simpler test.
void insert(iterator MBBI, MachineBasicBlock *MBB)
LLVM Basic Block Representation.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
TargetInstrInfo - Interface to description of machine instruction set.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const HexagonInstrInfo * TII
MachineOperand class - Representation of each machine instruction operand.
static BranchProbability getBranchProbStackProtector(bool IsLikely)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Register getReg() const
getReg - Returns the register number.
Iterator for intrusive lists based on ilist_node.
static bool MIIsInTerminatorSequence(const MachineInstr &MI)
Given that the input MI is before a partial terminator sequence TSeq, return true if M + TSeq also a ...
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
MachineBasicBlock::iterator findSplitPointForStackProtector(MachineBasicBlock *BB, const TargetInstrInfo &TII)
Find the split point at which to splice the end of BB into its success stack protector check machine ...