LLVM  16.0.0git
CodeGenCommonISel.cpp
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1 //===-- CodeGenCommonISel.cpp ---------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines common utilies that are shared between SelectionDAG and
10 // GlobalISel frameworks.
11 //
12 //===----------------------------------------------------------------------===//
13 
21 
22 #define DEBUG_TYPE "codegen-common"
23 
24 using namespace llvm;
25 
26 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
27 /// is 0.
29 StackProtectorDescriptor::addSuccessorMBB(
30  const BasicBlock *BB, MachineBasicBlock *ParentMBB, bool IsLikely,
31  MachineBasicBlock *SuccMBB) {
32  // If SuccBB has not been created yet, create it.
33  if (!SuccMBB) {
34  MachineFunction *MF = ParentMBB->getParent();
35  MachineFunction::iterator BBI(ParentMBB);
36  SuccMBB = MF->CreateMachineBasicBlock(BB);
37  MF->insert(++BBI, SuccMBB);
38  }
39  // Add it as a successor of ParentMBB.
40  ParentMBB->addSuccessor(
42  return SuccMBB;
43 }
44 
45 /// Given that the input MI is before a partial terminator sequence TSeq, return
46 /// true if M + TSeq also a partial terminator sequence.
47 ///
48 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
49 /// lowering copy vregs into physical registers, which are then passed into
50 /// terminator instructors so we can satisfy ABI constraints. A partial
51 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
52 /// may be the whole terminator sequence).
54  // If we do not have a copy or an implicit def, we return true if and only if
55  // MI is a debug value.
56  if (!MI.isCopy() && !MI.isImplicitDef()) {
57  // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
58  // physical registers if there is debug info associated with the terminator
59  // of our mbb. We want to include said debug info in our terminator
60  // sequence, so we return true in that case.
61  if (MI.isDebugInstr())
62  return true;
63 
64  // For GlobalISel, we may have extension instructions for arguments within
65  // copy sequences. Allow these.
66  switch (MI.getOpcode()) {
67  case TargetOpcode::G_TRUNC:
68  case TargetOpcode::G_ZEXT:
69  case TargetOpcode::G_ANYEXT:
70  case TargetOpcode::G_SEXT:
71  case TargetOpcode::G_MERGE_VALUES:
72  case TargetOpcode::G_UNMERGE_VALUES:
73  case TargetOpcode::G_CONCAT_VECTORS:
74  case TargetOpcode::G_BUILD_VECTOR:
75  case TargetOpcode::G_EXTRACT:
76  return true;
77  default:
78  return false;
79  }
80  }
81 
82  // We have left the terminator sequence if we are not doing one of the
83  // following:
84  //
85  // 1. Copying a vreg into a physical register.
86  // 2. Copying a vreg into a vreg.
87  // 3. Defining a register via an implicit def.
88 
89  // OPI should always be a register definition...
90  MachineInstr::const_mop_iterator OPI = MI.operands_begin();
91  if (!OPI->isReg() || !OPI->isDef())
92  return false;
93 
94  // Defining any register via an implicit def is always ok.
95  if (MI.isImplicitDef())
96  return true;
97 
98  // Grab the copy source...
100  ++OPI2;
101  assert(OPI2 != MI.operands_end()
102  && "Should have a copy implying we should have 2 arguments.");
103 
104  // Make sure that the copy dest is not a vreg when the copy source is a
105  // physical register.
106  if (!OPI2->isReg() || (!Register::isPhysicalRegister(OPI->getReg()) &&
108  return false;
109 
110  return true;
111 }
112 
113 /// Find the split point at which to splice the end of BB into its success stack
114 /// protector check machine basic block.
115 ///
116 /// On many platforms, due to ABI constraints, terminators, even before register
117 /// allocation, use physical registers. This creates an issue for us since
118 /// physical registers at this point can not travel across basic
119 /// blocks. Luckily, selectiondag always moves physical registers into vregs
120 /// when they enter functions and moves them through a sequence of copies back
121 /// into the physical registers right before the terminator creating a
122 /// ``Terminator Sequence''. This function is searching for the beginning of the
123 /// terminator sequence so that we can ensure that we splice off not just the
124 /// terminator, but additionally the copies that move the vregs into the
125 /// physical registers.
128  const TargetInstrInfo &TII) {
129  MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
130  if (SplitPoint == BB->begin())
131  return SplitPoint;
132 
133  MachineBasicBlock::iterator Start = BB->begin();
134  MachineBasicBlock::iterator Previous = SplitPoint;
135  do {
136  --Previous;
137  } while (Previous != Start && Previous->isDebugInstr());
138 
139  if (TII.isTailCall(*SplitPoint) &&
140  Previous->getOpcode() == TII.getCallFrameDestroyOpcode()) {
141  // Call frames cannot be nested, so if this frame is describing the tail
142  // call itself, then we must insert before the sequence even starts. For
143  // example:
144  // <split point>
145  // ADJCALLSTACKDOWN ...
146  // <Moves>
147  // ADJCALLSTACKUP ...
148  // TAILJMP somewhere
149  // On the other hand, it could be an unrelated call in which case this tail
150  // call has no register moves of its own and should be the split point. For
151  // example:
152  // ADJCALLSTACKDOWN
153  // CALL something_else
154  // ADJCALLSTACKUP
155  // <split point>
156  // TAILJMP somewhere
157  do {
158  --Previous;
159  if (Previous->isCall())
160  return SplitPoint;
161  } while(Previous->getOpcode() != TII.getCallFrameSetupOpcode());
162 
163  return Previous;
164  }
165 
166  while (MIIsInTerminatorSequence(*Previous)) {
167  SplitPoint = Previous;
168  if (Previous == Start)
169  break;
170  --Previous;
171  }
172 
173  return SplitPoint;
174 }
175 
176 unsigned llvm::getInvertedFPClassTest(unsigned Test) {
177  unsigned InvertedTest = ~Test & fcAllFlags;
178  switch (InvertedTest) {
179  default:
180  break;
181  case fcNan:
182  case fcSNan:
183  case fcQNan:
184  case fcInf:
185  case fcPosInf:
186  case fcNegInf:
187  case fcNormal:
188  case fcPosNormal:
189  case fcNegNormal:
190  case fcSubnormal:
191  case fcPosSubnormal:
192  case fcNegSubnormal:
193  case fcZero:
194  case fcPosZero:
195  case fcNegZero:
196  case fcFinite:
197  case fcPosFinite:
198  case fcNegFinite:
199  return InvertedTest;
200  }
201  return 0;
202 }
203 
205  MachineInstr &Copy) {
206  assert(Copy.getOpcode() == TargetOpcode::COPY && "Must be a COPY");
207 
208  return &Copy.getOperand(1);
209 }
210 
212  MachineInstr &Trunc,
214  assert(Trunc.getOpcode() == TargetOpcode::G_TRUNC && "Must be a G_TRUNC");
215 
216  const auto FromLLT = MRI.getType(Trunc.getOperand(1).getReg());
217  const auto ToLLT = MRI.getType(Trunc.defs().begin()->getReg());
218 
219  // TODO: Support non-scalar types.
220  if (!FromLLT.isScalar()) {
221  return nullptr;
222  }
223 
224  auto ExtOps = DIExpression::getExtOps(FromLLT.getSizeInBits(),
225  ToLLT.getSizeInBits(), false);
226  Ops.append(ExtOps.begin(), ExtOps.end());
227  return &Trunc.getOperand(1);
228 }
229 
231  MachineInstr &MI,
233  switch (MI.getOpcode()) {
234  case TargetOpcode::G_TRUNC:
235  return getSalvageOpsForTrunc(MRI, MI, Ops);
236  case TargetOpcode::COPY:
237  return getSalvageOpsForCopy(MRI, MI);
238  default:
239  return nullptr;
240  }
241 }
242 
244  MachineInstr &MI,
245  ArrayRef<MachineOperand *> DbgUsers) {
246  // These are arbitrary chosen limits on the maximum number of values and the
247  // maximum size of a debug expression we can salvage up to, used for
248  // performance reasons.
249  const unsigned MaxExpressionSize = 128;
250 
251  for (auto *DefMO : DbgUsers) {
252  MachineInstr *DbgMI = DefMO->getParent();
253  if (DbgMI->isIndirectDebugValue()) {
254  continue;
255  }
256 
257  int UseMOIdx = DbgMI->findRegisterUseOperandIdx(DefMO->getReg());
258  assert(UseMOIdx != -1 && DbgMI->hasDebugOperandForReg(DefMO->getReg()) &&
259  "Must use salvaged instruction as its location");
260 
261  // TODO: Support DBG_VALUE_LIST.
262  if (DbgMI->getOpcode() != TargetOpcode::DBG_VALUE) {
263  assert(DbgMI->getOpcode() == TargetOpcode::DBG_VALUE_LIST &&
264  "Must be either DBG_VALUE or DBG_VALUE_LIST");
265  continue;
266  }
267 
268  const DIExpression *SalvagedExpr = DbgMI->getDebugExpression();
269 
271  auto Op0 = salvageDebugInfoImpl(MRI, MI, Ops);
272  if (!Op0)
273  continue;
274  SalvagedExpr = DIExpression::appendOpsToArg(SalvagedExpr, Ops, 0, true);
275 
276  bool IsValidSalvageExpr =
277  SalvagedExpr->getNumElements() <= MaxExpressionSize;
278  if (IsValidSalvageExpr) {
279  auto &UseMO = DbgMI->getOperand(UseMOIdx);
280  UseMO.setReg(Op0->getReg());
281  UseMO.setSubReg(Op0->getSubReg());
282  DbgMI->getDebugExpressionOp().setMetadata(SalvagedExpr);
283 
284  LLVM_DEBUG(dbgs() << "SALVAGE: " << *DbgMI << '\n');
285  }
286  }
287 }
llvm::HexagonInstrInfo::isTailCall
bool isTailCall(const MachineInstr &MI) const override
Definition: HexagonInstrInfo.cpp:2645
llvm::MachineInstr::getDebugExpressionOp
const MachineOperand & getDebugExpressionOp() const
Return the operand for the complex address expression referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:854
fcQNan
@ fcQNan
Definition: FloatingPointMode.h:201
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::salvageDebugInfoForDbgValue
void salvageDebugInfoForDbgValue(const MachineRegisterInfo &MRI, MachineInstr &MI, ArrayRef< MachineOperand * > DbgUsers)
Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...
Definition: CodeGenCommonISel.cpp:243
llvm::getInvertedFPClassTest
unsigned getInvertedFPClassTest(unsigned Test)
Evaluates if the specified FP class test is an inversion of a simpler test.
Definition: CodeGenCommonISel.cpp:176
DebugInfoMetadata.h
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::MachineInstr::isIndirectDebugValue
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the location operand is a register and the offset operand is an immediate...
Definition: MachineInstr.h:1280
llvm::SmallVector< uint64_t, 16 >
fcPosZero
@ fcPosZero
Definition: FloatingPointMode.h:206
MachineBasicBlock.h
llvm::MachineInstr::defs
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:678
llvm::MachineOperand::setMetadata
void setMetadata(const MDNode *MD)
Definition: MachineOperand.h:693
fcNormal
@ fcNormal
Definition: FloatingPointMode.h:213
fcNan
@ fcNan
Definition: FloatingPointMode.h:211
TargetInstrInfo.h
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:873
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2596
llvm::MachineInstr::hasDebugOperandForReg
bool hasDebugOperandForReg(Register Reg) const
Returns whether this debug value has at least one debug operand with the register Reg.
Definition: MachineInstr.h:555
fcPosNormal
@ fcPosNormal
Definition: FloatingPointMode.h:208
fcPosInf
@ fcPosInf
Definition: FloatingPointMode.h:209
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
fcPosFinite
@ fcPosFinite
Definition: FloatingPointMode.h:216
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
fcNegZero
@ fcNegZero
Definition: FloatingPointMode.h:205
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:762
llvm::DIExpression::appendOpsToArg
static DIExpression * appendOpsToArg(const DIExpression *Expr, ArrayRef< uint64_t > Ops, unsigned ArgNo, bool StackValue=false)
Create a copy of Expr by appending the given list of Ops to each instance of the operand DW_OP_LLVM_a...
Definition: DebugInfoMetadata.cpp:1508
fcAllFlags
@ fcAllFlags
Definition: FloatingPointMode.h:219
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::PGSOQueryType::Test
@ Test
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:526
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
fcNegFinite
@ fcNegFinite
Definition: FloatingPointMode.h:217
TargetOpcodes.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::SmallVectorImpl::append
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:687
fcNegSubnormal
@ fcNegSubnormal
Definition: FloatingPointMode.h:204
llvm::BranchProbabilityInfo::getBranchProbStackProtector
static BranchProbability getBranchProbStackProtector(bool IsLikely)
Definition: BranchProbabilityInfo.h:192
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
BranchProbabilityInfo.h
llvm::MachineInstr::getDebugExpression
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
Definition: MachineInstr.cpp:866
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
fcZero
@ fcZero
Definition: FloatingPointMode.h:215
fcInf
@ fcInf
Definition: FloatingPointMode.h:212
getSalvageOpsForTrunc
static MachineOperand * getSalvageOpsForTrunc(const MachineRegisterInfo &MRI, MachineInstr &Trunc, SmallVectorImpl< uint64_t > &Ops)
Definition: CodeGenCommonISel.cpp:211
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:439
fcPosSubnormal
@ fcPosSubnormal
Definition: FloatingPointMode.h:207
fcSNan
@ fcSNan
Definition: FloatingPointMode.h:200
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:261
CodeGenCommonISel.h
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:516
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:374
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:313
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
fcSubnormal
@ fcSubnormal
Definition: FloatingPointMode.h:214
llvm::salvageDebugInfoImpl
Value * salvageDebugInfoImpl(Instruction &I, uint64_t CurrentLocOps, SmallVectorImpl< uint64_t > &Ops, SmallVectorImpl< Value * > &AdditionalValues)
Definition: Local.cpp:2005
fcFinite
@ fcFinite
Definition: FloatingPointMode.h:218
llvm::DIExpression::getExtOps
static ExtOps getExtOps(unsigned FromSize, unsigned ToSize, bool Signed)
Returns the ops for a zero- or sign-extension in a DIExpression.
Definition: DebugInfoMetadata.cpp:1782
fcNegNormal
@ fcNegNormal
Definition: FloatingPointMode.h:203
fcNegInf
@ fcNegInf
Definition: FloatingPointMode.h:202
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:745
MIIsInTerminatorSequence
static bool MIIsInTerminatorSequence(const MachineInstr &MI)
Given that the input MI is before a partial terminator sequence TSeq, return true if M + TSeq also a ...
Definition: CodeGenCommonISel.cpp:53
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:56
llvm::DIExpression::getNumElements
unsigned getNumElements() const
Definition: DebugInfoMetadata.h:2622
llvm::SmallVectorImpl< uint64_t >
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
getSalvageOpsForCopy
static MachineOperand * getSalvageOpsForCopy(const MachineRegisterInfo &MRI, MachineInstr &Copy)
Definition: CodeGenCommonISel.cpp:204
MachineFunction.h
llvm::MachineInstrBundleIterator
MachineBasicBlock iterator that automatically skips over MIs that are inside bundles (i....
Definition: MachineInstrBundleIterator.h:108
llvm::findSplitPointForStackProtector
MachineBasicBlock::iterator findSplitPointForStackProtector(MachineBasicBlock *BB, const TargetInstrInfo &TII)
Find the split point at which to splice the end of BB into its success stack protector check machine ...
Definition: CodeGenCommonISel.cpp:127
llvm::MachineInstr::findRegisterUseOperandIdx
int findRegisterUseOperandIdx(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found.
Definition: MachineInstr.cpp:987