LLVM  14.0.0git
CodeGenCommonISel.cpp
Go to the documentation of this file.
1 //===-- CodeGenCommonISel.cpp ---------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines common utilies that are shared between SelectionDAG and
10 // GlobalISel frameworks.
11 //
12 //===----------------------------------------------------------------------===//
13 
20 
21 using namespace llvm;
22 
23 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
24 /// is 0.
26 StackProtectorDescriptor::addSuccessorMBB(
27  const BasicBlock *BB, MachineBasicBlock *ParentMBB, bool IsLikely,
28  MachineBasicBlock *SuccMBB) {
29  // If SuccBB has not been created yet, create it.
30  if (!SuccMBB) {
31  MachineFunction *MF = ParentMBB->getParent();
32  MachineFunction::iterator BBI(ParentMBB);
33  SuccMBB = MF->CreateMachineBasicBlock(BB);
34  MF->insert(++BBI, SuccMBB);
35  }
36  // Add it as a successor of ParentMBB.
37  ParentMBB->addSuccessor(
39  return SuccMBB;
40 }
41 
42 /// Given that the input MI is before a partial terminator sequence TSeq, return
43 /// true if M + TSeq also a partial terminator sequence.
44 ///
45 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
46 /// lowering copy vregs into physical registers, which are then passed into
47 /// terminator instructors so we can satisfy ABI constraints. A partial
48 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
49 /// may be the whole terminator sequence).
51  // If we do not have a copy or an implicit def, we return true if and only if
52  // MI is a debug value.
53  if (!MI.isCopy() && !MI.isImplicitDef()) {
54  // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
55  // physical registers if there is debug info associated with the terminator
56  // of our mbb. We want to include said debug info in our terminator
57  // sequence, so we return true in that case.
58  if (MI.isDebugInstr())
59  return true;
60 
61  // For GlobalISel, we may have extension instructions for arguments within
62  // copy sequences. Allow these.
63  switch (MI.getOpcode()) {
64  case TargetOpcode::G_TRUNC:
65  case TargetOpcode::G_ZEXT:
66  case TargetOpcode::G_ANYEXT:
67  case TargetOpcode::G_SEXT:
68  case TargetOpcode::G_MERGE_VALUES:
69  case TargetOpcode::G_UNMERGE_VALUES:
70  case TargetOpcode::G_CONCAT_VECTORS:
71  case TargetOpcode::G_BUILD_VECTOR:
72  case TargetOpcode::G_EXTRACT:
73  return true;
74  default:
75  return false;
76  }
77  }
78 
79  // We have left the terminator sequence if we are not doing one of the
80  // following:
81  //
82  // 1. Copying a vreg into a physical register.
83  // 2. Copying a vreg into a vreg.
84  // 3. Defining a register via an implicit def.
85 
86  // OPI should always be a register definition...
87  MachineInstr::const_mop_iterator OPI = MI.operands_begin();
88  if (!OPI->isReg() || !OPI->isDef())
89  return false;
90 
91  // Defining any register via an implicit def is always ok.
92  if (MI.isImplicitDef())
93  return true;
94 
95  // Grab the copy source...
97  ++OPI2;
98  assert(OPI2 != MI.operands_end()
99  && "Should have a copy implying we should have 2 arguments.");
100 
101  // Make sure that the copy dest is not a vreg when the copy source is a
102  // physical register.
103  if (!OPI2->isReg() || (!Register::isPhysicalRegister(OPI->getReg()) &&
105  return false;
106 
107  return true;
108 }
109 
110 /// Find the split point at which to splice the end of BB into its success stack
111 /// protector check machine basic block.
112 ///
113 /// On many platforms, due to ABI constraints, terminators, even before register
114 /// allocation, use physical registers. This creates an issue for us since
115 /// physical registers at this point can not travel across basic
116 /// blocks. Luckily, selectiondag always moves physical registers into vregs
117 /// when they enter functions and moves them through a sequence of copies back
118 /// into the physical registers right before the terminator creating a
119 /// ``Terminator Sequence''. This function is searching for the beginning of the
120 /// terminator sequence so that we can ensure that we splice off not just the
121 /// terminator, but additionally the copies that move the vregs into the
122 /// physical registers.
125  const TargetInstrInfo &TII) {
126  MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
127  if (SplitPoint == BB->begin())
128  return SplitPoint;
129 
130  MachineBasicBlock::iterator Start = BB->begin();
131  MachineBasicBlock::iterator Previous = SplitPoint;
132  --Previous;
133 
134  if (TII.isTailCall(*SplitPoint) &&
135  Previous->getOpcode() == TII.getCallFrameDestroyOpcode()) {
136  // Call frames cannot be nested, so if this frame is describing the tail
137  // call itself, then we must insert before the sequence even starts. For
138  // example:
139  // <split point>
140  // ADJCALLSTACKDOWN ...
141  // <Moves>
142  // ADJCALLSTACKUP ...
143  // TAILJMP somewhere
144  // On the other hand, it could be an unrelated call in which case this tail
145  // call has to register moves of its own and should be the split point. For
146  // example:
147  // ADJCALLSTACKDOWN
148  // CALL something_else
149  // ADJCALLSTACKUP
150  // <split point>
151  // TAILJMP somewhere
152  do {
153  --Previous;
154  if (Previous->isCall())
155  return SplitPoint;
156  } while(Previous->getOpcode() != TII.getCallFrameSetupOpcode());
157 
158  return Previous;
159  }
160 
161  while (MIIsInTerminatorSequence(*Previous)) {
162  SplitPoint = Previous;
163  if (Previous == Start)
164  break;
165  --Previous;
166  }
167 
168  return SplitPoint;
169 }
llvm::HexagonInstrInfo::isTailCall
bool isTailCall(const MachineInstr &MI) const override
Definition: HexagonInstrInfo.cpp:2608
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
MachineBasicBlock.h
TargetInstrInfo.h
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:842
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:58
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:750
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
TargetOpcodes.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::BranchProbabilityInfo::getBranchProbStackProtector
static BranchProbability getBranchProbStackProtector(bool IsLikely)
Definition: BranchProbabilityInfo.h:194
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
BranchProbabilityInfo.h
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:418
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
CodeGenCommonISel.h
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:375
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
MIIsInTerminatorSequence
static bool MIIsInTerminatorSequence(const MachineInstr &MI)
Given that the input MI is before a partial terminator sequence TSeq, return true if M + TSeq also a ...
Definition: CodeGenCommonISel.cpp:50
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
MachineFunction.h
llvm::MachineInstrBundleIterator
MachineBasicBlock iterator that automatically skips over MIs that are inside bundles (i....
Definition: MachineInstrBundleIterator.h:108
llvm::findSplitPointForStackProtector
MachineBasicBlock::iterator findSplitPointForStackProtector(MachineBasicBlock *BB, const TargetInstrInfo &TII)
Find the split point at which to splice the end of BB into its success stack protector check machine ...
Definition: CodeGenCommonISel.cpp:124