llvm::MachineOperand Class Reference

MachineOperand class - Representation of each machine instruction operand. More...

#include "llvm/CodeGen/MachineOperand.h"

Public Types
enum	MachineOperandType : unsigned char {   MO_Register , MO_Immediate , MO_CImmediate , MO_FPImmediate ,   MO_MachineBasicBlock , MO_FrameIndex , MO_ConstantPoolIndex , MO_TargetIndex ,   MO_JumpTableIndex , MO_ExternalSymbol , MO_GlobalAddress , MO_BlockAddress ,   MO_RegisterMask , MO_RegisterLiveOut , MO_Metadata , MO_MCSymbol ,   MO_CFIIndex , MO_IntrinsicID , MO_Predicate , MO_ShuffleMask ,   MO_DbgInstrRef , MO_Last = MO_DbgInstrRef }

Public Member Functions
MachineOperandType	getType () const
	getType - Returns the MachineOperandType for this operand.
unsigned	getTargetFlags () const
void	setTargetFlags (unsigned F)
void	addTargetFlag (unsigned F)
MachineInstr *	getParent ()
	getParent - Return the instruction that this operand belongs to.
const MachineInstr *	getParent () const
void	clearParent ()
	clearParent - Reset the parent pointer.
unsigned	getOperandNo () const
	Returns the index of this operand in the instruction that it belongs to.
void	print (raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
	Print the MachineOperand to os.
void	print (raw_ostream &os, ModuleSlotTracker &MST, LLT TypeToPrint, std::optional< unsigned > OpIdx, bool PrintDef, bool IsStandalone, bool ShouldPrintRegisterTies, unsigned TiedOperandIdx, const TargetRegisterInfo *TRI, const TargetIntrinsicInfo *IntrinsicInfo) const
	More complex way of printing a MachineOperand.
void	print (raw_ostream &os, LLT TypeToPrint, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
	Same as print(os, TRI, IntrinsicInfo), but allows to specify the low-level type to be printed the same way the full version of print(...) does it.
void	dump () const
bool	isReg () const
	isReg - Tests if this is a MO_Register operand.
bool	isImm () const
	isImm - Tests if this is a MO_Immediate operand.
bool	isCImm () const
	isCImm - Test if this is a MO_CImmediate operand.
bool	isFPImm () const
	isFPImm - Tests if this is a MO_FPImmediate operand.
bool	isMBB () const
	isMBB - Tests if this is a MO_MachineBasicBlock operand.
bool	isFI () const
	isFI - Tests if this is a MO_FrameIndex operand.
bool	isCPI () const
	isCPI - Tests if this is a MO_ConstantPoolIndex operand.
bool	isTargetIndex () const
	isTargetIndex - Tests if this is a MO_TargetIndex operand.
bool	isJTI () const
	isJTI - Tests if this is a MO_JumpTableIndex operand.
bool	isGlobal () const
	isGlobal - Tests if this is a MO_GlobalAddress operand.
bool	isSymbol () const
	isSymbol - Tests if this is a MO_ExternalSymbol operand.
bool	isBlockAddress () const
	isBlockAddress - Tests if this is a MO_BlockAddress operand.
bool	isRegMask () const
	isRegMask - Tests if this is a MO_RegisterMask operand.
bool	isRegLiveOut () const
	isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.
bool	isMetadata () const
	isMetadata - Tests if this is a MO_Metadata operand.
bool	isMCSymbol () const
bool	isDbgInstrRef () const
bool	isCFIIndex () const
bool	isIntrinsicID () const
bool	isPredicate () const
bool	isShuffleMask () const
Register	getReg () const
	getReg - Returns the register number.
unsigned	getSubReg () const
bool	isUse () const
bool	isDef () const
bool	isImplicit () const
bool	isDead () const
bool	isKill () const
bool	isUndef () const
bool	isRenamable () const
	isRenamable - Returns true if this register may be renamed, i.e.
bool	isInternalRead () const
bool	isEarlyClobber () const
bool	isTied () const
bool	isDebug () const
bool	readsReg () const
	readsReg - Returns true if this operand reads the previous value of its register.
bool	isValidExcessOperand () const
	Return true if this operand can validly be appended to an arbitrary operand list.
void	setReg (Register Reg)
	Change the register this operand corresponds to.
void	setSubReg (unsigned subReg)
void	substVirtReg (Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
	substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
void	substPhysReg (MCRegister Reg, const TargetRegisterInfo &)
	substPhysReg - Substitute the current register with the physical register Reg, taking any existing SubReg into account.
void	setIsUse (bool Val=true)
void	setIsDef (bool Val=true)
	Change a def to a use, or a use to a def.
void	setImplicit (bool Val=true)
void	setIsKill (bool Val=true)
void	setIsDead (bool Val=true)
void	setIsUndef (bool Val=true)
void	setIsRenamable (bool Val=true)
void	setIsInternalRead (bool Val=true)
void	setIsEarlyClobber (bool Val=true)
void	setIsDebug (bool Val=true)
int64_t	getImm () const
const ConstantInt *	getCImm () const
const ConstantFP *	getFPImm () const
MachineBasicBlock *	getMBB () const
int	getIndex () const
const GlobalValue *	getGlobal () const
const BlockAddress *	getBlockAddress () const
MCSymbol *	getMCSymbol () const
unsigned	getInstrRefInstrIndex () const
unsigned	getInstrRefOpIndex () const
unsigned	getCFIIndex () const
Intrinsic::ID	getIntrinsicID () const
unsigned	getPredicate () const
ArrayRef< int >	getShuffleMask () const
int64_t	getOffset () const
	Return the offset from the symbol in this operand.
const char *	getSymbolName () const
bool	clobbersPhysReg (MCRegister PhysReg) const
	clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
const uint32_t *	getRegMask () const
	getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
const uint32_t *	getRegLiveOut () const
	getRegLiveOut - Returns a bit mask of live-out registers.
const MDNode *	getMetadata () const
void	setImm (int64_t immVal)
void	setCImm (const ConstantInt *CI)
void	setFPImm (const ConstantFP *CFP)
void	setOffset (int64_t Offset)
void	setIndex (int Idx)
void	setMetadata (const MDNode *MD)
void	setInstrRefInstrIndex (unsigned InstrIdx)
void	setInstrRefOpIndex (unsigned OpIdx)
void	setMBB (MachineBasicBlock *MBB)
void	setRegMask (const uint32_t *RegMaskPtr)
	Sets value of register mask operand referencing Mask.
void	setIntrinsicID (Intrinsic::ID IID)
void	setPredicate (unsigned Predicate)
bool	isIdenticalTo (const MachineOperand &Other) const
	Returns true if this operand is identical to the specified operand except for liveness related flags (isKill, isUndef and isDead).
void	ChangeToImmediate (int64_t ImmVal, unsigned TargetFlags=0)
	ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
void	ChangeToFPImmediate (const ConstantFP *FPImm, unsigned TargetFlags=0)
	ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value.
void	ChangeToES (const char *SymName, unsigned TargetFlags=0)
	ChangeToES - Replace this operand with a new external symbol operand.
void	ChangeToGA (const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
	ChangeToGA - Replace this operand with a new global address operand.
void	ChangeToBA (const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
	ChangeToBA - Replace this operand with a new block address operand.
void	ChangeToMCSymbol (MCSymbol *Sym, unsigned TargetFlags=0)
	ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
void	ChangeToFrameIndex (int Idx, unsigned TargetFlags=0)
	Replace this operand with a frame index.
void	ChangeToTargetIndex (unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
	Replace this operand with a target index.
void	ChangeToDbgInstrRef (unsigned InstrIdx, unsigned OpIdx, unsigned TargetFlags=0)
	Replace this operand with an Instruction Reference.
void	ChangeToRegister (Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
	ChangeToRegister - Replace this operand with a new register operand of the specified value.
const char *	getTargetIndexName () const
	getTargetIndexName - If this MachineOperand is a TargetIndex that has a name, attempt to get the name.

Static Public Member Functions
static void	printSubRegIdx (raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
	Print a subreg index operand.
static void	printTargetFlags (raw_ostream &OS, const MachineOperand &Op)
	Print operand target flags.
static void	printSymbol (raw_ostream &OS, MCSymbol &Sym)
	Print a MCSymbol as an operand.
static void	printStackObjectReference (raw_ostream &OS, unsigned FrameIndex, bool IsFixed, StringRef Name)
	Print a stack object reference.
static void	printOperandOffset (raw_ostream &OS, int64_t Offset)
	Print the offset with explicit +/- signs.
static void	printIRSlotNumber (raw_ostream &OS, int Slot)
	Print an IRSlotNumber.
static bool	clobbersPhysReg (const uint32_t *RegMask, MCRegister PhysReg)
	clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
static unsigned	getRegMaskSize (unsigned NumRegs)
	Returns number of elements needed for a regmask array.
static MachineOperand	CreateImm (int64_t Val)
static MachineOperand	CreateCImm (const ConstantInt *CI)
static MachineOperand	CreateFPImm (const ConstantFP *CFP)
static MachineOperand	CreateReg (Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
static MachineOperand	CreateMBB (MachineBasicBlock *MBB, unsigned TargetFlags=0)
static MachineOperand	CreateFI (int Idx)
static MachineOperand	CreateCPI (unsigned Idx, int Offset, unsigned TargetFlags=0)
static MachineOperand	CreateTargetIndex (unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
static MachineOperand	CreateJTI (unsigned Idx, unsigned TargetFlags=0)
static MachineOperand	CreateGA (const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
static MachineOperand	CreateES (const char *SymName, unsigned TargetFlags=0)
static MachineOperand	CreateBA (const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
static MachineOperand	CreateRegMask (const uint32_t *Mask)
	CreateRegMask - Creates a register mask operand referencing Mask.
static MachineOperand	CreateRegLiveOut (const uint32_t *Mask)
static MachineOperand	CreateMetadata (const MDNode *Meta)
static MachineOperand	CreateMCSymbol (MCSymbol *Sym, unsigned TargetFlags=0)
static MachineOperand	CreateDbgInstrRef (unsigned InstrIdx, unsigned OpIdx)
static MachineOperand	CreateCFIIndex (unsigned CFIIndex)
static MachineOperand	CreateIntrinsicID (Intrinsic::ID ID)
static MachineOperand	CreatePredicate (unsigned Pred)
static MachineOperand	CreateShuffleMask (ArrayRef< int > Mask)

Friends
class	MachineInstr
class	MachineRegisterInfo
struct	DenseMapInfo< MachineOperand >
hash_code	hash_value (const MachineOperand &MO)
	MachineOperand hash_value overload.

Detailed Description

MachineOperand class - Representation of each machine instruction operand.

This class isn't a POD type because it has a private constructor, but its destructor must be trivial. Functions like MachineInstr::addOperand(), MachineRegisterInfo::moveOperands(), and MF::DeleteMachineInstr() depend on not having to call the MachineOperand destructor.

Definition at line 48 of file MachineOperand.h.

Member Enumeration Documentation

MachineOperandType

enum llvm::MachineOperand::MachineOperandType : unsigned char

Enumerator
MO_Register	Register operand.
MO_Immediate	Immediate operand.
MO_CImmediate	Immediate >64bit operand.
MO_FPImmediate	Floating-point immediate operand.
MO_MachineBasicBlock	MachineBasicBlock reference.
MO_FrameIndex	Abstract Stack Frame Index.
MO_ConstantPoolIndex	Address of indexed Constant in Constant Pool.
MO_TargetIndex	Target-dependent index+offset operand.
MO_JumpTableIndex	Address of indexed Jump Table for switch.
MO_ExternalSymbol	Name of external global symbol.
MO_GlobalAddress	Address of a global value.
MO_BlockAddress	Address of a basic block.
MO_RegisterMask	Mask of preserved registers.
MO_RegisterLiveOut	Mask of live-out registers.
MO_Metadata	Metadata reference (for debug info)
MO_MCSymbol	MCSymbol reference (for debug/eh info)
MO_CFIIndex	MCCFIInstruction index.
MO_IntrinsicID	Intrinsic ID for ISel.
MO_Predicate	Generic predicate for ISel.
MO_ShuffleMask	Other IR Constant for ISel (shuffle masks)
MO_DbgInstrRef	Integer indices referring to an instruction+operand.
MO_Last

Definition at line 50 of file MachineOperand.h.

Member Function Documentation

addTargetFlag()

void llvm::MachineOperand::addTargetFlag ( unsigned  F )

inline

Definition at line 234 of file MachineOperand.h.

References assert(), F, and isReg().

Referenced by llvm::HexagonInstrInfo::immediateExtend().

ChangeToBA()

void MachineOperand::ChangeToBA	(	const BlockAddress *	BA,
		int64_t	Offset,
		unsigned	TargetFlags = 0
	)

ChangeToBA - Replace this operand with a new block address operand.

Definition at line 209 of file MachineOperand.cpp.

References assert(), isReg(), isTied(), MO_BlockAddress, llvm::Offset, setOffset(), and setTargetFlags().

ChangeToDbgInstrRef()

void MachineOperand::ChangeToDbgInstrRef	(	unsigned	InstrIdx,
		unsigned	OpIdx,
		unsigned	TargetFlags = 0
	)

Replace this operand with an Instruction Reference.

Definition at line 257 of file MachineOperand.cpp.

References assert(), isReg(), isTied(), MO_DbgInstrRef, setInstrRefInstrIndex(), setInstrRefOpIndex(), and setTargetFlags().

ChangeToES()

void MachineOperand::ChangeToES	(	const char *	SymName,
		unsigned	TargetFlags = 0
	)

ChangeToES - Replace this operand with a new external symbol operand.

Definition at line 183 of file MachineOperand.cpp.

References assert(), isReg(), isTied(), MO_ExternalSymbol, setOffset(), and setTargetFlags().

ChangeToFPImmediate()

void MachineOperand::ChangeToFPImmediate	(	const ConstantFP *	FPImm,
		unsigned	TargetFlags = 0
	)

ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value.

If an operand is known to be an FP immediate already, the setFPImm method should be used.

Definition at line 172 of file MachineOperand.cpp.

References assert(), isReg(), isTied(), MO_FPImmediate, and setTargetFlags().

ChangeToFrameIndex()

void MachineOperand::ChangeToFrameIndex	(	int	Idx,
		unsigned	TargetFlags = 0
	)

Replace this operand with a frame index.

Definition at line 233 of file MachineOperand.cpp.

References assert(), Idx, isReg(), isTied(), MO_FrameIndex, setIndex(), and setTargetFlags().

Referenced by swapRegAndNonRegOperand().

ChangeToGA()

void MachineOperand::ChangeToGA	(	const GlobalValue *	GV,
		int64_t	Offset,
		unsigned	TargetFlags = 0
	)

ChangeToGA - Replace this operand with a new global address operand.

Definition at line 196 of file MachineOperand.cpp.

References assert(), isReg(), isTied(), MO_GlobalAddress, llvm::Offset, setOffset(), and setTargetFlags().

Referenced by swapRegAndNonRegOperand().

ChangeToImmediate()

void MachineOperand::ChangeToImmediate	(	int64_t	ImmVal,
		unsigned	TargetFlags = 0
	)

ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.

If an operand is known to be an immediate already, the setImm method should be used.

Definition at line 162 of file MachineOperand.cpp.

References assert(), isReg(), isTied(), MO_Immediate, and setTargetFlags().

Referenced by llvm::AArch64RegisterInfo::eliminateFrameIndex(), llvm::M68kRegisterInfo::eliminateFrameIndex(), llvm::X86RegisterInfo::eliminateFrameIndex(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::SIInstrInfo::foldImmediate(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::rewriteARMFrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), llvm::rewriteT2FrameIndex(), swapRegAndNonRegOperand(), and llvm::updateDbgValueForSpill().

ChangeToMCSymbol()

void MachineOperand::ChangeToMCSymbol	(	MCSymbol *	Sym,
		unsigned	TargetFlags = 0
	)

ChangeToMCSymbol - Replace this operand with a new MC symbol operand.

Definition at line 222 of file MachineOperand.cpp.

References assert(), isReg(), isTied(), MO_MCSymbol, setTargetFlags(), and Sym.

ChangeToRegister()

void MachineOperand::ChangeToRegister	(	Register	Reg,
		bool	isDef,
		bool	isImp = false,
		bool	isKill = false,
		bool	isDead = false,
		bool	isUndef = false,
		bool	isDebug = false
	)

ChangeToRegister - Replace this operand with a new register operand of the specified value.

If an operand is known to be an register already, the setReg method should be used.

Definition at line 273 of file MachineOperand.cpp.

References llvm::MachineRegisterInfo::addRegOperandToUseList(), assert(), getMFIfAvailable(), getParent(), isDead(), isDebug(), isDef(), isKill(), isReg(), isUndef(), MI, MO_Register, and llvm::MachineRegisterInfo::removeRegOperandFromUseList().

Referenced by llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::legalizeOperandsVOP3(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::SIRegisterInfo::resolveFrameIndex(), swapRegAndNonRegOperand(), and llvm::X86InstrInfo::unfoldMemoryOperand().

ChangeToTargetIndex()

void MachineOperand::ChangeToTargetIndex	(	unsigned	Idx,
		int64_t	Offset,
		unsigned	TargetFlags = 0
	)

Replace this operand with a target index.

Definition at line 244 of file MachineOperand.cpp.

References assert(), Idx, isReg(), isTied(), MO_TargetIndex, llvm::Offset, setIndex(), setOffset(), and setTargetFlags().

clearParent()

void llvm::MachineOperand::clearParent ( )

inline

clearParent - Reset the parent pointer.

The MachineOperand copy constructor also copies ParentMI, expecting the original to be deleted. If a MachineOperand is ever stored outside a MachineInstr, the parent pointer must be cleared.

Never call clearParent() on an operand in a MachineInstr.

Definition at line 254 of file MachineOperand.h.

clobbersPhysReg() [1/2]

static bool llvm::MachineOperand::clobbersPhysReg ( const uint32_t *  RegMask, MCRegister  PhysReg  )

inlinestatic

clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.

It is sometimes necessary to detach the register mask pointer from its machine operand. This static method can be used for such detached bit mask pointers.

Definition at line 646 of file MachineOperand.h.

References assert().

Referenced by llvm::LiveRegUnits::addRegsInMask(), canClobberPhysRegDefs(), canClobberReachingPhysRegUse(), CheckForLiveRegDefMasked(), clobbersAllYmmAndZmmRegs(), clobbersPhysReg(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::M68kRegisterInfo::getReservedRegs(), handleRegMaskClobber(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::CallLowering::parametersInCSRMatch(), llvm::TargetLowering::parametersInCSRMatch(), llvm::PhysicalRegisterUsageInfo::print(), llvm::LivePhysRegs::removeRegsInMask(), llvm::LiveRegUnits::removeRegsNotPreserved(), llvm::LivePhysRegs::stepForward(), and LiveDebugValues::MLocTracker::writeRegMask().

clobbersPhysReg() [2/2]

bool llvm::MachineOperand::clobbersPhysReg ( MCRegister  PhysReg ) const

inline

clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.

Definition at line 653 of file MachineOperand.h.

References clobbersPhysReg(), and getRegMask().

CreateBA()

static MachineOperand llvm::MachineOperand::CreateBA ( const BlockAddress *  BA, int64_t  Offset, unsigned  TargetFlags = 0  )

inlinestatic

Definition at line 912 of file MachineOperand.h.

References MO_BlockAddress, and llvm::Offset.

Referenced by llvm::MachineInstrBuilder::addBlockAddress().

CreateCFIIndex()

static MachineOperand llvm::MachineOperand::CreateCFIIndex ( unsigned  CFIIndex )

inlinestatic

Definition at line 966 of file MachineOperand.h.

References MO_CFIIndex.

Referenced by llvm::MachineInstrBuilder::addCFIIndex().

CreateCImm()

static MachineOperand llvm::MachineOperand::CreateCImm ( const ConstantInt *  CI )

inlinestatic

Definition at line 825 of file MachineOperand.h.

References MO_CImmediate.

Referenced by llvm::MachineInstrBuilder::addCImm(), llvm::CSEMIRBuilder::buildConstant(), GetMOForConstDbgOp(), and processSwitches().

CreateCPI()

static MachineOperand llvm::MachineOperand::CreateCPI ( unsigned  Idx, int  Offset, unsigned  TargetFlags = 0  )

inlinestatic

Definition at line 874 of file MachineOperand.h.

References Idx, MO_ConstantPoolIndex, and llvm::Offset.

Referenced by llvm::MachineInstrBuilder::addConstantPoolIndex(), and llvm::X86InstrInfo::foldMemoryOperandImpl().

CreateDbgInstrRef()

static MachineOperand llvm::MachineOperand::CreateDbgInstrRef ( unsigned  InstrIdx, unsigned  OpIdx  )

inlinestatic

Definition at line 959 of file MachineOperand.h.

References MO_DbgInstrRef.

Referenced by llvm::InstrEmitter::EmitDbgInstrRef().

CreateES()

static MachineOperand llvm::MachineOperand::CreateES ( const char *  SymName, unsigned  TargetFlags = 0  )

inlinestatic

Definition at line 904 of file MachineOperand.h.

References MO_ExternalSymbol.

Referenced by llvm::MachineInstrBuilder::addExternalSymbol(), createAtomicLibcall(), llvm::createLibcall(), llvm::createMemLibcall(), and getMovOperand().

CreateFI()

static MachineOperand llvm::MachineOperand::CreateFI ( int  Idx )

inlinestatic

Definition at line 869 of file MachineOperand.h.

References Idx, and MO_FrameIndex.

Referenced by llvm::MachineInstrBuilder::addFrameIndex(), llvm::X86InstrInfo::foldMemoryOperandImpl(), llvm::X86AddressMode::getFullAddress(), and llvm::FastISel::lowerDbgValue().

CreateFPImm()

static MachineOperand llvm::MachineOperand::CreateFPImm ( const ConstantFP *  CFP )

inlinestatic

Definition at line 831 of file MachineOperand.h.

References MO_FPImmediate.

Referenced by llvm::MachineInstrBuilder::addFPImm(), llvm::CSEMIRBuilder::buildFConstant(), convertImplicitDefToConstZero(), GetMOForConstDbgOp(), and llvm::SPIRVInlineAsmLowering::lowerAsmOperandForConstraint().

CreateGA()

static MachineOperand llvm::MachineOperand::CreateGA ( const GlobalValue *  GV, int64_t  Offset, unsigned  TargetFlags = 0  )

inlinestatic

Definition at line 896 of file MachineOperand.h.

References MO_GlobalAddress, and llvm::Offset.

Referenced by llvm::MachineInstrBuilder::addGlobalAddress(), llvm::X86AddressMode::getFullAddress(), getMovOperand(), llvm::CallLowering::lowerCall(), llvm::AMDGPUCallLowering::lowerChainCall(), and llvm::FastISel::selectPatchpoint().

CreateImm()

static MachineOperand llvm::MachineOperand::CreateImm ( int64_t  Val )

inlinestatic

Definition at line 819 of file MachineOperand.h.

References MO_Immediate.

Referenced by llvm::MachineInstrBuilder::addImm(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::HexagonInstrInfo::analyzeBranch(), llvm::MSP430InstrInfo::analyzeBranch(), llvm::PPCInstrInfo::analyzeBranch(), llvm::SystemZInstrInfo::analyzeBranch(), llvm::XCoreInstrInfo::analyzeBranch(), llvm::ARMBaseInstrInfo::analyzeBranch(), llvm::AVRInstrInfo::analyzeBranch(), llvm::WebAssemblyInstrInfo::analyzeBranch(), llvm::LanaiInstrInfo::analyzeBranch(), llvm::M68kInstrInfo::AnalyzeBranchImpl(), llvm::SIInstrInfo::analyzeBranchImpl(), llvm::AArch64InstrInfo::analyzeBranchPredicate(), llvm::X86InstrInfo::analyzeBranchPredicate(), llvm::SIInstrInfo::buildExtractSubRegOrImm(), llvm::X86InstrInfo::commuteInstructionImpl(), convertImplicitDefToConstZero(), llvm::AArch64InstrInfo::describeLoadedValue(), llvm::X86InstrInfo::describeLoadedValue(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), llvm::AArch64FrameLowering::emitPrologue(), emitVFROUND_NOEXCEPT_MASK(), foldConstantsIntoIntrinsics(), llvm::X86InstrInfo::foldMemoryOperandImpl(), llvm::X86AddressMode::getFullAddress(), GetMOForConstDbgOp(), getMovOperand(), llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic(), llvm::InlineAsmLowering::lowerAsmOperandForConstraint(), parseCondBranch(), llvm::predOps(), llvm::WebAssemblyInstrInfo::reverseBranchCondition(), llvm::FastISel::selectPatchpoint(), llvm::FastISel::selectStackmap(), and llvm::HexagonInstrInfo::setBundleNoShuf().

CreateIntrinsicID()

static MachineOperand llvm::MachineOperand::CreateIntrinsicID ( Intrinsic::ID  ID )

inlinestatic

Definition at line 972 of file MachineOperand.h.

References MO_IntrinsicID.

Referenced by llvm::MachineInstrBuilder::addIntrinsicID().

CreateJTI()

static MachineOperand llvm::MachineOperand::CreateJTI ( unsigned  Idx, unsigned  TargetFlags = 0  )

inlinestatic

Definition at line 890 of file MachineOperand.h.

References Idx, and MO_JumpTableIndex.

Referenced by llvm::MachineInstrBuilder::addJumpTableIndex(), and getMovOperand().

CreateMBB()

static MachineOperand llvm::MachineOperand::CreateMBB ( MachineBasicBlock *  MBB, unsigned  TargetFlags = 0  )

inlinestatic

Definition at line 862 of file MachineOperand.h.

References MBB, and MO_MachineBasicBlock.

Referenced by llvm::MachineInstrBuilder::addMBB(), llvm::PeelingModuloScheduleExpander::peelPrologAndEpilogs(), processSwitches(), and splitEdge().

CreateMCSymbol()

static MachineOperand llvm::MachineOperand::CreateMCSymbol ( MCSymbol *  Sym, unsigned  TargetFlags = 0  )

inlinestatic

Definition at line 950 of file MachineOperand.h.

References MO_MCSymbol, and Sym.

Referenced by llvm::MachineInstrBuilder::addSym(), and llvm::MipsTargetLowering::AdjustInstrPostInstrSelection().

CreateMetadata()

static MachineOperand llvm::MachineOperand::CreateMetadata ( const MDNode *  Meta )

inlinestatic

Definition at line 944 of file MachineOperand.h.

References MO_Metadata.

Referenced by llvm::MachineInstrBuilder::addMetadata().

CreatePredicate()

static MachineOperand llvm::MachineOperand::CreatePredicate ( unsigned  Pred )

inlinestatic

Definition at line 978 of file MachineOperand.h.

References MO_Predicate.

Referenced by llvm::MachineInstrBuilder::addPredicate().

CreateReg()

static MachineOperand llvm::MachineOperand::CreateReg ( Register  Reg, bool  isDef, bool  isImp = false, bool  isKill = false, bool  isDead = false, bool  isUndef = false, bool  isEarlyClobber = false, unsigned  SubReg = 0, bool  isDebug = false, bool  isInternalRead = false, bool  isRenamable = false  )

inlinestatic

Definition at line 837 of file MachineOperand.h.

References assert(), isDead(), isDebug(), isDef(), isEarlyClobber(), isInternalRead(), isKill(), isRenamable(), isUndef(), MO_Register, Reg, and SubReg.

Referenced by addConstantsToTrack(), llvm::MachineInstr::addImplicitDefUseOperands(), llvm::SITargetLowering::AddMemOpInit(), llvm::GISelInstProfileBuilder::addNodeIDRegType(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::addRegisterDead(), llvm::MachineInstr::addRegisterDefined(), llvm::MachineInstr::addRegisterKilled(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::RISCVTargetLowering::AdjustInstrPostInstrSelection(), llvm::R600InstrInfo::analyzeBranch(), llvm::PPCInstrInfo::analyzeBranch(), llvm::SIInstrInfo::buildExtractSubRegOrImm(), llvm::condCodeOp(), llvm::X86InstrInfo::convertToThreeAddress(), createCallWithOps(), llvm::TargetInstrInfo::describeLoadedValue(), llvm::MipsInstrInfo::describeLoadedValue(), describeMOVrrLoadedValue(), describeORRLoadedValue(), llvm::InstrEmitter::EmitDbgInstrRef(), llvm::RISCVTargetLowering::EmitInstrWithCustomInserter(), llvm::AArch64TargetLowering::EmitInstrWithCustomInserter(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), LiveDebugValues::MLocTracker::emitLoc(), llvm::HexagonFrameLowering::emitPrologue(), emitVFROUND_NOEXCEPT_MASK(), llvm::SIInstrInfo::enforceOperandRCAlignment(), expandSGPRCopy(), llvm::X86InstrInfo::foldMemoryOperandImpl(), llvm::X86AddressMode::getFullAddress(), GetMOForConstDbgOp(), imposeStackOrdering(), INITIALIZE_PASS(), llvm::AArch64CallLowering::lowerCall(), llvm::CallLowering::lowerCall(), llvm::AMDGPUCallLowering::lowerChainCall(), llvm::FastISel::lowerDbgDeclare(), llvm::FastISel::lowerDbgValue(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::RISCVInstrInfo::optimizeCondBranch(), parseCondBranch(), llvm::PeelingModuloScheduleExpander::peelPrologAndEpilogs(), llvm::predOps(), TransferTracker::recoverAsEntryValue(), llvm::rewriteT2FrameIndex(), llvm::FastISel::selectPatchpoint(), llvm::FastISel::selectStackmap(), llvm::FastISel::selectXRayCustomEvent(), llvm::FastISel::selectXRayTypedEvent(), llvm::t1CondCodeOp(), and llvm::tryFoldSPUpdateIntoPushPop().

CreateRegLiveOut()

static MachineOperand llvm::MachineOperand::CreateRegLiveOut ( const uint32_t *  Mask )

inlinestatic

Definition at line 938 of file MachineOperand.h.

References assert(), and MO_RegisterLiveOut.

CreateRegMask()

static MachineOperand llvm::MachineOperand::CreateRegMask ( const uint32_t *  Mask )

inlinestatic

CreateRegMask - Creates a register mask operand referencing Mask.

The operand does not take ownership of the memory referenced by Mask, it must remain valid for the lifetime of the operand.

A RegMask operand represents a set of non-clobbered physical registers on an instruction that clobbers many registers, typically a call. The bit mask has a bit set for each physreg that is preserved by this instruction, as described in the documentation for TargetRegisterInfo::getCallPreservedMask().

Any physreg with a 0 bit in the mask is clobbered by the instruction.

Definition at line 932 of file MachineOperand.h.

References assert(), and MO_RegisterMask.

Referenced by llvm::MachineInstrBuilder::addRegMask(), and llvm::FastISel::selectPatchpoint().

CreateShuffleMask()

static MachineOperand llvm::MachineOperand::CreateShuffleMask ( ArrayRef< int >  Mask )

inlinestatic

Definition at line 984 of file MachineOperand.h.

References MO_ShuffleMask.

Referenced by llvm::MachineInstrBuilder::addShuffleMask().

CreateTargetIndex()

static MachineOperand llvm::MachineOperand::CreateTargetIndex ( unsigned  Idx, int64_t  Offset, unsigned  TargetFlags = 0  )

inlinestatic

Definition at line 882 of file MachineOperand.h.

References Idx, MO_TargetIndex, and llvm::Offset.

Referenced by llvm::MachineInstrBuilder::addTargetIndex().

dump()

LLVM_DUMP_METHOD void MachineOperand::dump

(

)

const

Definition at line 1028 of file MachineOperand.cpp.

References llvm::dbgs().

Referenced by rescheduleCanonically().

getBlockAddress()

const BlockAddress * llvm::MachineOperand::getBlockAddress ( ) const

inline

Definition at line 587 of file MachineOperand.h.

References assert(), and isBlockAddress().

Referenced by llvm::MachineInstrBuilder::addDisp(), llvm::LanaiMCInstLower::GetBlockAddressSymbol(), llvm::MSP430MCInstLower::GetBlockAddressSymbol(), llvm::SystemZMCInstLower::getExpr(), getMCSymbolForTOCPseudoMO(), llvm::hash_value(), INITIALIZE_PASS(), isIdenticalTo(), isSimilarDispOp(), llvm::lowerLoongArchMachineOperandToMCOperand(), llvm::M68kMCInstLower::LowerOperand(), LowerOperand(), llvm::ARMAsmPrinter::lowerOperand(), llvm::AArch64MCInstLower::lowerOperand(), llvm::CSKYMCInstLower::lowerOperand(), llvm::LowerPPCMachineOperandToMCOperand(), LowerSymbolOperand(), llvm::XtensaAsmPrinter::LowerSymbolOperand(), print(), llvm::M68kAsmPrinter::PrintAsmMemoryOperand(), llvm::CSKYAsmPrinter::PrintAsmOperand(), llvm::MipsAsmPrinter::printOperand(), and processSwitches().

getCFIIndex()

unsigned llvm::MachineOperand::getCFIIndex ( ) const

inline

Definition at line 607 of file MachineOperand.h.

References assert(), and isCFIIndex().

Referenced by llvm::hash_value(), isIdenticalTo(), print(), and llvm::stableHashValue().

getCImm()

const ConstantInt * llvm::MachineOperand::getCImm ( ) const

inline

Definition at line 561 of file MachineOperand.h.

References assert(), and isCImm().

Referenced by llvm::GISelInstProfileBuilder::addNodeIDMachineOperand(), llvm::GIMatchTableExecutor::executeMatchTable(), foldConstantsIntoIntrinsics(), foldImm(), generateAssignInstrs(), llvm::generateGroupUniformInst(), llvm::generateSpecConstantInst(), getArrayComponentCount(), llvm::getConstFromIntrinsic(), getImmedFromMO(), llvm::GVScale::getSrc(), llvm::hash_value(), isIdenticalTo(), llvm::LegalizerHelper::lowerConstant(), llvm::CombinerHelper::matchCombineUnmergeConstant(), llvm::matchUnaryPredicate(), print(), llvm::stableHashValue(), and llvm::LegalizerHelper::widenScalar().

getFPImm()

const ConstantFP * llvm::MachineOperand::getFPImm ( ) const

inline

Definition at line 566 of file MachineOperand.h.

References assert(), and isFPImm().

Referenced by llvm::GISelInstProfileBuilder::addNodeIDMachineOperand(), generateAssignInstrs(), llvm::generateSpecConstantInst(), llvm::hash_value(), isIdenticalTo(), isSameScalarConst(), llvm::WebAssemblyMCInstLower::lower(), llvm::SPIRVMCInstLower::lower(), llvm::LegalizerHelper::lowerFConstant(), llvm::ARMAsmPrinter::lowerOperand(), llvm::CombinerHelper::matchCombineUnmergeConstant(), print(), llvm::stableHashValue(), and llvm::LegalizerHelper::widenScalar().

getGlobal()

const GlobalValue * llvm::MachineOperand::getGlobal ( ) const

inline

Definition at line 582 of file MachineOperand.h.

References assert(), and isGlobal().

Referenced by llvm::MachineInstrBuilder::addDisp(), llvm::X86FrameLowering::adjustForHiPEPrologue(), llvm::BTFDebug::beginInstruction(), llvm::buildEnqueueKernel(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::getAddressFromInstr(), getCodeModel(), llvm::SystemZMCInstLower::getExpr(), llvm::AArch64MCInstLower::GetGlobalAddressSymbol(), llvm::BPFMCInstLower::GetGlobalAddressSymbol(), llvm::LanaiMCInstLower::GetGlobalAddressSymbol(), llvm::MSP430MCInstLower::GetGlobalAddressSymbol(), getMCSymbolForTOCPseudoMO(), getMovOperand(), llvm::M68kMCInstLower::GetSymbolFromOperand(), GetSymbolFromOperand(), GetSymbolRef(), getTOCEntryTypeForMO(), llvm::hash_value(), INITIALIZE_PASS(), llvm::BTFDebug::InstLower(), IsCallReturnTwice(), isIdenticalTo(), isSameScalarConst(), isSignExtendedW(), llvm::PPCInstrInfo::isSignOrZeroExtended(), isSimilarDispOp(), llvm::SPIRVMCInstLower::lower(), llvm::lowerLoongArchMachineOperandToMCOperand(), LowerOperand(), llvm::ARMAsmPrinter::lowerOperand(), AMDGPUMCInstLower::lowerOperand(), llvm::CSKYMCInstLower::lowerOperand(), LowerSymbolOperand(), llvm::XtensaAsmPrinter::LowerSymbolOperand(), llvm::AVRMCInstLower::lowerSymbolOperand(), llvm::AArch64MCInstLower::lowerSymbolOperandELF(), llvm::WebAssembly::mayThrow(), print(), llvm::AVRAsmPrinter::printOperand(), llvm::ARMAsmPrinter::PrintSymbolOperand(), llvm::AsmPrinter::PrintSymbolOperand(), llvm::ARMBaseInstrInfo::produceSameValue(), queryCallee(), llvm::DetectRoundChange::runOnMachineFunction(), smallData(), swapRegAndNonRegOperand(), and validateFunCall().

getImm()

int64_t llvm::MachineOperand::getImm ( ) const

inline

Definition at line 556 of file MachineOperand.h.

References assert(), and isImm().

Referenced by AddAtomicFloatRequirements(), addConstantComments(), llvm::MachineInstrBuilder::addDisp(), llvm::R600InstrInfo::addFlag(), addInstrRequirements(), llvm::SITargetLowering::AddMemOpInit(), llvm::GISelInstProfileBuilder::addNodeIDMachineOperand(), llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::buildAtomicCompareExchangeInst(), llvm::buildBoolRegister(), llvm::buildEnqueueKernel(), llvm::R600InstrInfo::buildSlotOfVectorInstruction(), canCombineShiftIntoShXAdd(), canCompareBeNewValueJump(), llvm::AArch64InstrInfo::canFoldIntoAddrMode(), llvm::RISCVInstrInfo::canFoldIntoAddrMode(), canFoldIntoCSel(), canInstrSubstituteCmpInstr(), llvm::R600InstrInfo::clearFlag(), llvm::PPCInstrInfo::combineRLWINM(), compareMachineOp(), llvm::SIInstrInfo::convertToThreeAddress(), createNewPtrType(), createPHIsForSelects(), llvm::ARCFrameLowering::eliminateCallFramePseudoInstr(), llvm::XCoreFrameLowering::eliminateCallFramePseudoInstr(), llvm::M68kRegisterInfo::eliminateFrameIndex(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::AArch64FrameLowering::emitEpilogue(), llvm::PPCFrameLowering::emitEpilogue(), EmitLoweredCascadedSelect(), llvm::GIMatchTableExecutor::executeMatchTable(), llvm::M68kInstrInfo::ExpandMOVEM(), llvm::M68kInstrInfo::ExpandMOVI(), ExpandMOVImmSExti8(), llvm::HexagonInstrInfo::expandPostRAPseudo(), expandSHXDROT(), llvm::RISCVInstrInfo::finalizeInsInstrs(), llvm::MachineInstr::findInlineAsmFlagIdx(), findRedundantFlagInstr(), llvm::MachineInstr::findTiedOperandIdx(), fixupCalleeSaveRestoreStackOffset(), fixupSEHOpcode(), foldImm(), llvm::SIInstrInfo::foldImmediate(), foldInlineAsmMemOperand(), llvm::AArch64InstrInfo::genAlternativeCodeSequence(), llvm::generateImageMiscQueryInst(), llvm::generateImageSizeQueryInst(), genIndexedMultiply(), genShXAddAddShift(), llvm::getAddressFromInstr(), llvm::X86InstrInfo::getAddrModeFromMemoryOp(), getArgumentStackToRestore(), llvm::HexagonInstrInfo::getBaseAndOffset(), llvm::HexagonInstrInfo::getBundleNoShuf(), llvm::PatchPointOpers::getCallingConv(), llvm::ARMAsmPrinter::getCodeViewJumpTableInfo(), llvm::HexagonInstrInfo::getCompoundOpcode(), llvm::X86InstrInfo::getConstValDefinedInReg(), llvm::TargetInstrInfo::getExtractSubregInputs(), llvm::SIRegisterInfo::getFrameIndexInstrOffset(), llvm::ARMBaseRegisterInfo::getFrameIndexInstrOffset(), llvm::StatepointOpers::getGCPointerMap(), getHWReg(), llvm::PatchPointOpers::getID(), getImmedFromMO(), llvm::HexagonInstrInfo::getIncrementValue(), llvm::MachineInstr::getInlineAsmDialect(), llvm::TargetInstrInfo::getInsertSubregInputs(), llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs(), getLoadStoreOffsetSizeInBits(), llvm::SIInstrInfo::getMemOperandsWithOffsetWidth(), llvm::X86InstrInfo::getMemOperandsWithOffsetWidth(), llvm::LanaiInstrInfo::getMemOperandWithOffsetWidth(), llvm::PPCInstrInfo::getMemOperandWithOffsetWidth(), llvm::RISCVInstrInfo::getMemOperandWithOffsetWidth(), llvm::AArch64InstrInfo::getMemOperandWithOffsetWidth(), getMovOperand(), llvm::PatchPointOpers::getNumPatchBytes(), llvm::getNumSizeComponents(), llvm::SPIRVGlobalRegistry::getOrCreateConsIntVector(), llvm::SPIRVGlobalRegistry::getOrCreateConstVector(), getRegImmPairPreventingCompression(), llvm::TargetInstrInfo::getRegSequenceInputs(), llvm::R600InstrInfo::getSrcs(), getStoreOffset(), hasAllNBitUsers(), llvm::RISCV::hasEqualFRM(), llvm::hash_value(), llvm::SIInstrInfo::hasModifiersSet(), llvm::MachineInstr::hasUnmodeledSideEffects(), INITIALIZE_PASS(), llvm::SystemZELFFrameLowering::inlineStackProbe(), insertInlineAsmProcess(), llvm::isAArch64FrameOffsetLegal(), llvm::PPCInstrInfo::isADDIInstrEligibleForFolding(), llvm::MipsInstrInfo::isAddImmediate(), isAddressLdStPair(), isAddSub2RegAndConstOnePair(), llvm::HexagonInstrInfo::isConstExtended(), llvm::MachineInstr::isConvergent(), isConvertibleLEA(), isIdenticalTo(), isIdentityValue(), llvm::PPCInstrInfo::isImmInstrEligibleForFolding(), llvm::SIInstrInfo::isInlineConstant(), isLdOffsetInRangeOfSt(), isLiteralsPair(), llvm::HexagonInstrInfo::isLoadFromStackSlot(), isLoadStoreThatCanHandleDisplacement(), isMatchingStartStopPair(), llvm::SIInstrInfo::isOperandLegal(), llvm::GIndexedLoad::isPre(), llvm::GIndexedStore::isPre(), isRedundantFlagInstr(), isRelevantAddressingMode(), isSafeToFoldImmIntoCopy(), isSameScalarConst(), llvm::SPIRVGlobalRegistry::isScalarOrVectorSigned(), llvm::isScale(), llvm::MachineInstr::isStackAligningInlineAsm(), llvm::HexagonInstrInfo::isStoreToStackSlot(), llvm::RISCVLegalizerInfo::legalizeCustom(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::WebAssemblyMCInstLower::lower(), llvm::SPIRVMCInstLower::lower(), llvm::lowerLoongArchMachineOperandToMCOperand(), llvm::M68kMCInstLower::LowerOperand(), LowerOperand(), llvm::SystemZMCInstLower::lowerOperand(), llvm::MipsMCInstLower::LowerOperand(), llvm::ARMAsmPrinter::lowerOperand(), llvm::AArch64MCInstLower::lowerOperand(), AMDGPUMCInstLower::lowerOperand(), llvm::CSKYMCInstLower::lowerOperand(), llvm::ARCMCInstLower::LowerOperand(), llvm::XCoreMCInstLower::LowerOperand(), llvm::XtensaAsmPrinter::lowerOperand(), llvm::LowerPPCMachineOperandToMCOperand(), lowerRISCVVMachineInstrToMCInst(), llvm::SPIRV::make_descr_sampled_image(), llvm::MachineInstr::mayFoldInlineAsmRegOp(), llvm::MachineInstr::mayLoad(), mayOverlapWrite(), llvm::MachineInstr::mayStore(), llvm::SIInstrInfo::moveFlatAddrToVGPR(), llvm::SIInstrInfo::moveToVALUImpl(), llvm::SIInstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCondBranch(), parseCondBranch(), llvm::SystemZInstrInfo::prepareCompareSwapOperands(), llvm::MachineInstr::print(), print(), llvm::LoongArchAsmPrinter::PrintAsmMemoryOperand(), llvm::M68kAsmPrinter::PrintAsmMemoryOperand(), llvm::MipsAsmPrinter::PrintAsmMemoryOperand(), llvm::AMDGPUAsmPrinter::PrintAsmOperand(), llvm::MipsAsmPrinter::PrintAsmOperand(), llvm::X86AsmPrinter::PrintAsmOperand(), llvm::AsmPrinter::PrintAsmOperand(), llvm::CSKYAsmPrinter::PrintAsmOperand(), llvm::LoongArchAsmPrinter::PrintAsmOperand(), llvm::WebAssemblyAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::PrintAsmOperand(), llvm::MipsAsmPrinter::printFCCOperand(), llvm::ARMAsmPrinter::printOperand(), llvm::MipsAsmPrinter::printOperand(), llvm::AVRAsmPrinter::printOperand(), llvm::HexagonAsmPrinter::printOperand(), llvm::SIInstrInfo::reMaterialize(), llvm::SIRegisterInfo::resolveFrameIndex(), llvm::R600InstrInfo::reverseBranchCondition(), llvm::ARMBlockPlacement::revertWhileToDoLoop(), llvm::rewriteT2FrameIndex(), llvm::HexagonInstrInfo::setBundleNoShuf(), llvm::AArch64InstrInfo::shouldClusterMemOps(), llvm::stableHashValue(), swapRegAndNonRegOperand(), llvm::SIInstrInfo::swapSourceModifiers(), llvm::X86InstrInfo::unfoldMemoryOperand(), updateOperandIfDifferent(), updateOperands(), validateGroupAsyncCopyPtr(), validateLifetimeStart(), verifyInsExtInstruction(), llvm::SIInstrInfo::verifyInstruction(), and llvm::RISCVInstrInfo::verifyInstruction().

getIndex()

int llvm::MachineOperand::getIndex ( ) const

inline

Definition at line 576 of file MachineOperand.h.

References assert(), isCPI(), isFI(), isJTI(), and isTargetIndex().

Referenced by llvm::MachineInstrBuilder::addDisp(), llvm::ARCRegisterInfo::eliminateFrameIndex(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::ARMAsmPrinter::emitJumpTableAddrs(), llvm::ARMAsmPrinter::emitJumpTableInsts(), llvm::ARMAsmPrinter::emitJumpTableTBInst(), llvm::TargetLoweringBase::emitPatchPoint(), llvm::getAddressFromInstr(), llvm::X86::getConstantFromPool(), llvm::LanaiMCInstLower::GetConstantPoolIndexSymbol(), llvm::MSP430MCInstLower::GetConstantPoolIndexSymbol(), llvm::XtensaAsmPrinter::GetConstantPoolIndexSymbol(), llvm::SystemZMCInstLower::getExpr(), getJumpTableIndexFromAddr(), llvm::LanaiMCInstLower::GetJumpTableSymbol(), llvm::MSP430MCInstLower::GetJumpTableSymbol(), llvm::XtensaAsmPrinter::GetJumpTableSymbol(), getMCSymbolForTOCPseudoMO(), getMovOperand(), getStartOrEndSlot(), getTargetIndexName(), llvm::hash_value(), hasSameBaseOpValue(), INITIALIZE_PASS(), isIdenticalTo(), llvm::HexagonInstrInfo::isLoadFromStackSlot(), isSimilarDispOp(), llvm::HexagonInstrInfo::isStoreToStackSlot(), llvm::lowerLoongArchMachineOperandToMCOperand(), llvm::M68kMCInstLower::LowerOperand(), LowerOperand(), llvm::ARMAsmPrinter::lowerOperand(), llvm::AArch64MCInstLower::lowerOperand(), llvm::CSKYMCInstLower::lowerOperand(), llvm::LowerPPCMachineOperandToMCOperand(), LowerSymbolOperand(), llvm::AArch64FrameLowering::orderFrameObjects(), llvm::SystemZELFFrameLowering::orderFrameObjects(), print(), llvm::ARMAsmPrinter::printOperand(), llvm::MipsAsmPrinter::printOperand(), llvm::HexagonAsmPrinter::printOperand(), llvm::ARMBaseInstrInfo::produceSameValue(), llvm::ARMBaseInstrInfo::reMaterialize(), llvm::AArch64InstrInfo::shouldClusterMemOps(), llvm::PPCInstrInfo::shouldClusterMemOps(), smallData(), llvm::stableHashValue(), and swapRegAndNonRegOperand().

getInstrRefInstrIndex()

unsigned llvm::MachineOperand::getInstrRefInstrIndex ( ) const

inline

Definition at line 597 of file MachineOperand.h.

References assert(), and isDbgInstrRef().

Referenced by llvm::hash_value(), isIdenticalTo(), print(), and llvm::stableHashValue().

getInstrRefOpIndex()

unsigned llvm::MachineOperand::getInstrRefOpIndex ( ) const

inline

Definition at line 602 of file MachineOperand.h.

References assert(), and isDbgInstrRef().

Referenced by llvm::hash_value(), isIdenticalTo(), print(), and llvm::stableHashValue().

getIntrinsicID()

Intrinsic::ID llvm::MachineOperand::getIntrinsicID ( ) const

inline

Definition at line 612 of file MachineOperand.h.

References assert(), and isIntrinsicID().

Referenced by llvm::GIMatchTableExecutor::executeMatchTable(), llvm::AArch64GISelUtils::extractPtrauthBlendDiscriminators(), llvm::GIntrinsic::getIntrinsicID(), llvm::hash_value(), isIdenticalTo(), print(), and llvm::stableHashValue().

getMBB()

MachineBasicBlock * llvm::MachineOperand::getMBB ( ) const

inline

Definition at line 571 of file MachineOperand.h.

References assert(), and isMBB().

Referenced by addIncomingValuesToPHIs(), llvm::R600InstrInfo::analyzeBranch(), llvm::HexagonInstrInfo::analyzeBranch(), llvm::NVPTXInstrInfo::analyzeBranch(), llvm::PPCInstrInfo::analyzeBranch(), llvm::XCoreInstrInfo::analyzeBranch(), llvm::MipsInstrInfo::analyzeBranch(), llvm::AArch64InstrInfo::analyzeBranch(), llvm::SparcInstrInfo::analyzeBranch(), llvm::VEInstrInfo::analyzeBranch(), llvm::AArch64InstrInfo::analyzeBranchPredicate(), llvm::CombinerHelper::applyOptBrCondByInvertingCond(), BBIsJumpedOver(), bbIsJumpedOver(), llvm::HexagonEvaluator::evaluate(), findLoopComponents(), llvm::HexagonInstrInfo::getDotNewPredJumpOp(), llvm::SystemZMCInstLower::getExpr(), llvm::GPhi::getIncomingBlock(), llvm::PeelingModuloScheduleExpander::getPhiCanonicalReg(), llvm::M68kMCInstLower::GetSymbolFromOperand(), getTargetMBB(), llvm::hash_value(), INITIALIZE_PASS(), insertPHI(), isIdenticalTo(), isSimilarDispOp(), llvm::SPIRVMCInstLower::lower(), llvm::lowerLoongArchMachineOperandToMCOperand(), LowerOperand(), llvm::ARMAsmPrinter::lowerOperand(), llvm::AArch64MCInstLower::lowerOperand(), AMDGPUMCInstLower::lowerOperand(), llvm::CSKYMCInstLower::lowerOperand(), llvm::LowerPPCMachineOperandToMCOperand(), LowerSymbolOperand(), llvm::XtensaAsmPrinter::LowerSymbolOperand(), llvm::CombinerHelper::matchOptBrCondByInvertingCond(), parseCondBranch(), print(), llvm::WebAssemblyAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::printOperand(), llvm::MipsAsmPrinter::printOperand(), llvm::AVRAsmPrinter::printOperand(), llvm::HexagonAsmPrinter::printOperand(), llvm::MachineBasicBlock::replacePhiUsesWith(), llvm::ARMBlockPlacement::revertWhileToDoLoop(), splitBlock(), splitEdge(), splitMBB(), updatePHIs(), and verifyCFIntrinsic().

getMCSymbol()

MCSymbol * llvm::MachineOperand::getMCSymbol ( ) const

inline

Definition at line 592 of file MachineOperand.h.

References assert(), and isMCSymbol().

Referenced by emitDirectiveRelocJalr(), llvm::MipsInstrInfo::genInstrWithNewOpc(), llvm::hash_value(), isIdenticalTo(), isSimilarDispOp(), llvm::WebAssemblyMCInstLower::lower(), llvm::M68kMCInstLower::LowerOperand(), llvm::AArch64MCInstLower::lowerOperand(), AMDGPUMCInstLower::lowerOperand(), llvm::CSKYMCInstLower::lowerOperand(), llvm::LowerPPCMachineOperandToMCOperand(), print(), and llvm::stableHashValue().

getMetadata()

const MDNode * llvm::MachineOperand::getMetadata ( ) const

inline

Definition at line 675 of file MachineOperand.h.

References assert(), and isMetadata().

Referenced by llvm::getMachineInstrType(), llvm::hash_value(), isIdenticalTo(), llvm::MachineInstr::print(), and print().

getOffset()

int64_t llvm::MachineOperand::getOffset ( ) const

inline

Return the offset from the symbol in this operand.

This always returns 0 for ExternalSymbol operands.

Definition at line 629 of file MachineOperand.h.

References assert(), isBlockAddress(), isCPI(), isGlobal(), isMCSymbol(), isSymbol(), and isTargetIndex().

Referenced by llvm::MachineInstrBuilder::addDisp(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::X86::getConstantFromPool(), llvm::SystemZMCInstLower::getExpr(), getMovOperand(), GetSymbolRef(), llvm::hash_value(), INITIALIZE_PASS(), isIdenticalTo(), AMDGPUMCInstLower::lowerOperand(), LowerSymbolOperand(), llvm::XtensaAsmPrinter::LowerSymbolOperand(), llvm::BPFMCInstLower::LowerSymbolOperand(), llvm::LanaiMCInstLower::LowerSymbolOperand(), llvm::M68kMCInstLower::LowerSymbolOperand(), llvm::MSP430MCInstLower::LowerSymbolOperand(), lowerSymbolOperand(), llvm::AVRMCInstLower::lowerSymbolOperand(), llvm::AArch64MCInstLower::lowerSymbolOperandCOFF(), llvm::AArch64MCInstLower::lowerSymbolOperandELF(), llvm::AArch64MCInstLower::lowerSymbolOperandMachO(), print(), llvm::WebAssemblyAsmPrinter::PrintAsmOperand(), llvm::MipsAsmPrinter::printOperand(), llvm::ARMAsmPrinter::PrintSymbolOperand(), llvm::AsmPrinter::PrintSymbolOperand(), llvm::ARMBaseInstrInfo::produceSameValue(), llvm::stableHashValue(), and swapRegAndNonRegOperand().

getOperandNo()

unsigned MachineOperand::getOperandNo

(

)

const

Returns the index of this operand in the instruction that it belongs to.

Definition at line 56 of file MachineOperand.cpp.

References assert(), llvm::MachineInstr::getOperandNo(), and getParent().

Referenced by isCandidateStore(), isCrossCopy(), llvm::SIInstrInfo::isInlineConstant(), llvm::M68kInstrInfo::isPCRelRegisterOperandLegal(), producesFalseLanesZero(), llvm::DeadLaneDetector::transferUsedLanes(), and vectorPseudoHasAllNBitUsers().

getParent() [1/2]

MachineInstr * llvm::MachineOperand::getParent ( )

inline

getParent - Return the instruction that this operand belongs to.

Definition at line 243 of file MachineOperand.h.

Referenced by llvm::AnalyzeVirtRegInBundle(), llvm::CombinerHelper::applyCombineExtendingLoads(), canRenameMOP(), llvm::MachineInstr::changeDebugValuesDefReg(), ChangeToRegister(), llvm::constrainOperandRegClass(), createDeadDef(), findSingleRegUse(), findUseBetween(), getFoldableImm(), getImmedFromMO(), getLoadStoreOffsetSizeInBits(), getMFIfAvailable(), getOperandNo(), GetSymbolRef(), llvm::MachineInstr::insert(), llvm::SIInstrInfo::isIgnorableUse(), llvm::SIInstrInfo::isInlineConstant(), llvm::SIInstrInfo::isLegalRegOperand(), isNoReturnDef(), llvm::M68kInstrInfo::isPCRelRegisterOperandLegal(), isRenamable(), isTiedToNotUndef(), oneUseDominatesOtherUses(), print(), printAsmMRegister(), printAsmVRegister(), llvm::SPIRVGlobalRegistry::recordFunctionDefinition(), llvm::CombinerHelper::replaceRegOpWith(), scavengeVReg(), llvm::AArch64InstrInfo::shouldClusterMemOps(), llvm::PPCInstrInfo::shouldClusterMemOps(), llvm::stableHashValue(), llvm::RegBankSelect::tryAvoidingSplit(), llvm::FastISel::tryToFoldLoad(), vectorPseudoHasAllNBitUsers(), and llvm::MachineRegisterInfo::verifyUseList().

getParent() [2/2]

const MachineInstr * llvm::MachineOperand::getParent ( ) const

inline

Definition at line 244 of file MachineOperand.h.

getPredicate()

unsigned llvm::MachineOperand::getPredicate ( ) const

inline

Definition at line 617 of file MachineOperand.h.

References assert(), and isPredicate().

Referenced by llvm::GISelInstProfileBuilder::addNodeIDMachineOperand(), llvm::CombinerHelper::applyNotCmp(), llvm::GIMatchTableExecutor::executeMatchTable(), llvm::GAnyCmp::getCond(), llvm::hash_value(), isIdenticalTo(), llvm::MIPatternMatch::CompareOp_match< Pred_P, LHS_P, RHS_P, Opcode, Commutable >::match(), print(), and llvm::stableHashValue().

getReg()

Register llvm::MachineOperand::getReg ( ) const

inline

getReg - Returns the register number.

Definition at line 369 of file MachineOperand.h.

References assert(), and isReg().

Referenced by addInstrRequirements(), llvm::GISelInstProfileBuilder::addNodeIDMachineOperand(), llvm::ScheduleDAGInstrs::addPhysRegDataDeps(), llvm::ScheduleDAGInstrs::addPhysRegDeps(), llvm::MachineInstr::addRegisterDead(), llvm::MachineInstr::addRegisterDefined(), llvm::MachineInstr::addRegisterKilled(), llvm::MachineRegisterInfo::addRegOperandToUseList(), llvm::SrcOp::addSrcToMIB(), llvm::ScheduleDAGInstrs::addVRegDefDeps(), llvm::ScheduleDAGInstrs::addVRegUseDeps(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::AArch64Subtarget::adjustSchedDependency(), llvm::HexagonSubtarget::adjustSchedDependency(), allPhiOperandsUndefined(), llvm::AArch64InstrInfo::analyzeLoopForPipelining(), llvm::AnalyzeVirtRegInBundle(), llvm::HexagonSubtarget::BankConflictMutation::apply(), llvm::CombinerHelper::applyBuildFnMO(), llvm::CombinerHelper::applyCombineDivRem(), llvm::CombinerHelper::applyCombineExtendingLoads(), llvm::CombinerHelper::applyCombineTruncOfShift(), llvm::CombinerHelper::applyCombineUnmergeZExtToZExt(), llvm::RegisterBankInfo::applyDefaultMapping(), llvm::CombinerHelper::applyExtendThroughPhis(), llvm::AMDGPUCombinerHelper::applyFoldableFneg(), llvm::RegBankSelect::applyMapping(), llvm::CombinerHelper::applyOptBrCondByInvertingCond(), llvm::CombinerHelper::applyShiftOfShiftedLogic(), llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(), attemptDebugCopyProp(), llvm::CriticalAntiDepBreaker::BreakAntiDependencies(), llvm::ARMBaseInstrInfo::breakPartialRegDependency(), llvm::buildEnqueueKernel(), llvm::SIInstrInfo::buildExtractSubReg(), llvm::SPIRVGlobalRegistry::buildGlobalVariable(), llvm::BuildMI(), llvm::buildNDRange(), buildRegSequence(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::R600InstrInfo::buildSlotOfVectorInstruction(), llvm::ModuloScheduleExpanderMVE::canApply(), canCombine(), canCombineFPFusedMultiply(), canCreateUndefOrPoison(), canEmitConjunction(), llvm::HexagonInstrInfo::canExecuteInBundle(), canFoldCopy(), llvm::AArch64InstrInfo::canFoldIntoAddrMode(), llvm::RISCVInstrInfo::canFoldIntoAddrMode(), canFoldIntoCSel(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), canRenameMOP(), canRenameUntilSecondLoad(), canRenameUpToDef(), llvm::SIInstrInfo::canShrink(), castBufferRsrcArgToV4I32(), castBufferRsrcFromV4I32(), llvm::MachineInstr::changeDebugValuesDefReg(), llvm::checkVOPDRegConstraints(), clearKillFlags(), llvm::MachineInstr::clearRegisterDeads(), llvm::MachineInstr::clearRegisterKills(), cloneInstr(), collectRegDefs(), CombineCVTAToLocal(), combineFPFusedMultiply(), llvm::PPCInstrInfo::combineRLWINM(), compareMachineOp(), CompressEVEXImpl(), llvm::RegBankSelect::computeMapping(), llvm::TargetSchedModel::computeOutputLatency(), ConsecutiveInstr(), llvm::constrainOperandRegClass(), llvm::constrainSelectedInstRegOperands(), llvm::PPCInstrInfo::convertToImmediateForm(), llvm::SIInstrInfo::convertToThreeAddress(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::convertToThreeAddress(), createCallWithOps(), llvm::ScheduleDAGInstrs::deadDefHasNoUse(), llvm::ShapeT::deduceImm(), llvm::X86InstrInfo::describeLoadedValue(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), emitIndirectDst(), llvm::HexagonHazardRecognizer::EmitInstruction(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::AArch64InstrInfo::emitLdStWithAddr(), llvm::RISCVInstrInfo::emitLdStWithAddr(), EmitLoweredCascadedSelect(), eraseGPOpnd(), llvm::GIMatchTableExecutor::executeMatchTable(), Expand2AddrUndef(), llvm::M68kInstrInfo::ExpandMOVEM(), llvm::M68kInstrInfo::ExpandMOVI(), llvm::M68kInstrInfo::ExpandMOVSZX_RM(), llvm::M68kInstrInfo::ExpandMOVSZX_RR(), llvm::M68kInstrInfo::ExpandMOVX_RR(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::X86InstrInfo::expandPostRAPseudo(), llvm::M68kInstrInfo::ExpandPUSH_POP(), llvm::AArch64GISelUtils::extractPtrauthBlendDiscriminators(), llvm::PPCInstrInfo::finalizeInsInstrs(), findAssignTypeInstr(), findDeadCallerSavedReg(), findLoopComponents(), findNextInsertLocation(), findRedundantFlagInstr(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::findRegisterUseOperandIdx(), findStartOfTree(), llvm::ScheduleDAGInstrs::fixupKills(), llvm::SwingSchedulerDAG::fixupRegisterOverlaps(), foldConstantsIntoIntrinsics(), llvm::PPCInstrInfo::foldFrameOffset(), foldImm(), llvm::SIInstrInfo::foldImmediate(), llvm::ARMBaseInstrInfo::foldImmediate(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), foldPatchpoint(), foldVGPRCopyIntoRegSequence(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), llvm::RISCVInstrInfo::genAlternativeCodeSequence(), genAlternativeDpCodeSequence(), generateAssignInstrs(), llvm::generateCoopMatrInst(), llvm::generateImageSizeQueryInst(), genFNegatedMAD(), genFusedMultiply(), genIndexedMultiply(), genMaddR(), genShXAddAddShift(), genSubAdd2SubSub(), llvm::getAddressFromInstr(), llvm::X86InstrInfo::getAddrModeFromMemoryOp(), getArrayComponentCount(), getBaseAddressRegister(), llvm::GIndexedLoad::getBaseReg(), llvm::GIndexedStore::getBaseReg(), llvm::getBlockStructInstr(), getCallTargetRegOpnd(), llvm::HexagonInstrInfo::getCompoundOpcode(), llvm::getConstFromIntrinsic(), llvm::SIRegisterInfo::getConstrainedRegClassForOperand(), llvm::X86InstrInfo::getConstValDefinedInReg(), llvm::getDefInstrMaybeConstant(), getDefRegMask(), llvm::getDefSrcRegIgnoringCopies(), llvm::GIndexedLoad::getDstReg(), llvm::GAnyLoad::getDstReg(), llvm::GInsertVectorElement::getElementReg(), llvm::TargetInstrInfo::getExtractSubregInputs(), llvm::ARMBaseInstrInfo::getExtractSubregLikeInputs(), llvm::MachineInstr::getFirst2RegLLTs(), llvm::MachineInstr::getFirst3RegLLTs(), llvm::MachineInstr::getFirst4RegLLTs(), llvm::MachineInstr::getFirst5RegLLTs(), llvm::PPCInstrInfo::getFMAPatterns(), getFMULPatterns(), getFNEGPatterns(), getFoldableImm(), getFPReg(), llvm::MachineInstrExpressionTrait::getHashValue(), llvm::ARMBankConflictHazardRecognizer::getHazardType(), getImmedFromMO(), llvm::GPhi::getIncomingValue(), llvm::GExtractVectorElement::getIndexReg(), llvm::GInsertVectorElement::getIndexReg(), llvm::TargetInstrInfo::getInsertSubregInputs(), llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs(), getInstReadLaneMask(), llvm::ARMRegisterBankInfo::getInstrMapping(), llvm::RegisterBankInfo::getInstrMappingImpl(), llvm::SIInstrInfo::getInstructionUniformity(), getIsFloat(), llvm::ScheduleDAGInstrs::getLaneMaskForMO(), llvm::GBinOpCarryOut::getLHSReg(), llvm::GSUCmp::getLHSReg(), llvm::SrcOp::getLLTTy(), llvm::getMachineInstrType(), llvm::ReachingDefAnalysis::getMIOperand(), getMopState(), getNewSource(), llvm::GIndexedLoad::getOffsetReg(), llvm::GIndexedStore::getOffsetReg(), llvm::ARMBaseInstrInfo::getOperandLatency(), llvm::HexagonInstrInfo::getOperandLatency(), llvm::PPCInstrInfo::getOperandLatency(), llvm::SPIRVGlobalRegistry::getOrCreateConstIntArray(), llvm::SPIRVGlobalRegistry::getOrCreateOpTypeSampledImage(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), llvm::X86InstrInfo::getPartialRegUpdateClearance(), llvm::PeelingModuloScheduleExpander::getPhiCanonicalReg(), llvm::SPIRVGlobalRegistry::getPointeeType(), llvm::GLoadStore::getPointerReg(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::GetPoisonVal(), getRC32(), llvm::SrcOp::getReg(), llvm::GenericMachineInstr::getReg(), llvm::PPCRegisterInfo::getRegAllocationHints(), llvm::SystemZRegisterInfo::getRegAllocationHints(), getRegClass(), llvm::SIRegisterInfo::getRegClassForOperandReg(), llvm::TargetInstrInfo::getRegSequenceInputs(), llvm::ARMBaseInstrInfo::getRegSequenceLikeInputs(), llvm::getRegState(), llvm::RegBankSelect::getRepairCost(), llvm::GBinOpCarryOut::getRHSReg(), llvm::GSUCmp::getRHSReg(), getSalvageOpsForTrunc(), llvm::GShl::getShiftReg(), getShuffleComment(), llvm::GUnmerge::getSourceReg(), llvm::GFreeze::getSourceReg(), llvm::GShuffleVector::getSrc1Reg(), llvm::GShuffleVector::getSrc2Reg(), llvm::GCastOp::getSrcReg(), llvm::GShl::getSrcReg(), llvm::R600InstrInfo::getSrcs(), getTypeReg(), llvm::X86InstrInfo::getUndefRegClearance(), llvm::MachineSSAUpdater::GetValueInMiddleOfBlock(), llvm::GIndexedStore::getValueReg(), llvm::GStore::getValueReg(), llvm::GExtractVectorElement::getVectorReg(), llvm::GInsertVectorElement::getVectorReg(), llvm::getVRegSubRegDef(), llvm::GIndexedLoad::getWritebackReg(), llvm::GIndexedStore::getWritebackReg(), handleADRP(), llvm::hash_value(), hasLiveThroughUse(), hasMoreUses(), hasRAWHazard(), llvm::TargetInstrInfo::hasReassociableOperands(), llvm::RISCVInstrInfo::hasReassociableOperands(), llvm::TargetInstrInfo::hasReassociableSibling(), llvm::RISCVInstrInfo::hasReassociableSibling(), hasRegisterDependency(), llvm::MachineInstr::hasRegisterImplicitUseOperand(), hasSameBaseOpValue(), indirectCopyToAGPR(), INITIALIZE_PASS(), llvm::HexagonInstrInfo::insertBranch(), insertDivByZeroTrap(), insertInlineAsmProcess(), insertSEH(), instrToSignature(), llvm::AArch64InstrInfo::isAddImmediate(), llvm::ARMBaseInstrInfo::isAddImmediate(), llvm::MipsInstrInfo::isAddImmediate(), llvm::RISCVInstrInfo::isAddImmediate(), isAGPRCopy(), isArithmeticBccPair(), isBackwardPropagatableCopy(), llvm::GIMatchTableExecutor::isBaseWithConstantOffset(), isCandidate(), llvm::WebAssembly::isChild(), llvm::AArch64GISelUtils::isCMN(), llvm::MachineInstr::isConstantValuePHI(), isConstReg(), isConvertibleLEA(), isCrossCopy(), llvm::AArch64InstrInfo::isExtendLikelyToBeFolded(), isExtractHiElt(), isFIPlusImmOrVGPR(), isIdenticalOp(), llvm::MachineInstr::isIdenticalTo(), isIdenticalTo(), llvm::MachineInstr::isIdentityCopy(), llvm::SIInstrInfo::isIgnorableUse(), isImm(), llvm::PPCInstrInfo::isImmInstrEligibleForFolding(), isInvariantStore(), llvm::isKnownNeverNaN(), isLdStSafeToCluster(), llvm::SIInstrInfo::isLegalRegOperand(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), isLogicalOpOnExec(), llvm::SMSchedule::isLoopCarriedDefOfUse(), llvm::SwingSchedulerDAG::isLoopCarriedDep(), isMatchingStartStopPair(), isMMSourceRegister(), isMMThreeBitGPRegister(), isNonFoldablePartialRegisterLoad(), llvm::GIMatchTableExecutor::isOperandImmEqual(), isOperandKill(), llvm::SIInstrInfo::isOperandLegal(), isPromotableZeroStoreInst(), isRedundantFlagInstr(), isRegInClass(), isRelevantAddressingMode(), isRenamable(), IsSafeAndProfitableToMove(), llvm::SIInstrInfo::isSGPRStackAccess(), llvm::SIInstrInfo::isStackAccess(), isSubRegOf(), isSVERegOp(), isTileDef(), isTileRegDef(), llvm::HexagonInstrInfo::isToBeScheduledASAP(), isTwoAddrUse(), isValidRegDefOf(), isValidRegUseOf(), llvm::PPCInstrInfo::isValidToBeChangedReg(), isVirtualRegisterOperand(), isWaitInstr(), llvm::AArch64LegalizerInfo::legalizeIntrinsic(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsFLAT(), llvm::SIInstrInfo::legalizeOperandsSMRD(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::legalizeOperandsVOP3(), llvm::WebAssemblyMCInstLower::lower(), llvm::SPIRVMCInstLower::lower(), LowerCallResults(), llvm::TargetInstrInfo::lowerCopy(), llvm::lowerLoongArchMachineOperandToMCOperand(), llvm::M68kMCInstLower::LowerOperand(), LowerOperand(), llvm::SystemZMCInstLower::lowerOperand(), llvm::MipsMCInstLower::LowerOperand(), llvm::ARMAsmPrinter::lowerOperand(), llvm::AArch64MCInstLower::lowerOperand(), AMDGPUMCInstLower::lowerOperand(), llvm::CSKYMCInstLower::lowerOperand(), llvm::ARCMCInstLower::LowerOperand(), llvm::XCoreMCInstLower::LowerOperand(), llvm::XtensaAsmPrinter::lowerOperand(), llvm::LowerPPCMachineOperandToMCOperand(), lowerRISCVVMachineInstrToMCInst(), llvm::MIPatternMatch::BinaryOp_match< LHS_P, RHS_P, Opcode, Commutable >::match(), llvm::MIPatternMatch::BinaryOpc_match< LHS_P, RHS_P, Commutable >::match(), llvm::MIPatternMatch::UnaryOp_match< SrcTy, Opcode >::match(), llvm::MIPatternMatch::CompareOp_match< Pred_P, LHS_P, RHS_P, Opcode, Commutable >::match(), llvm::MIPatternMatch::TernaryOp_match< Src0Ty, Src1Ty, Src2Ty, Opcode >::match(), llvm::CombinerHelper::matchAddOfVScale(), llvm::CombinerHelper::matchCombineExtractedVectorLoad(), llvm::CombinerHelper::matchCombineFAddFMAFMulToFMadOrFMA(), llvm::CombinerHelper::matchCombineFAddFpExtFMulToFMadOrFMA(), llvm::CombinerHelper::matchCombineFAddFpExtFMulToFMadOrFMAAggressive(), llvm::CombinerHelper::matchCombineFSubFNegFMulToFMadOrFMA(), llvm::CombinerHelper::matchCombineFSubFpExtFMulToFMadOrFMA(), llvm::CombinerHelper::matchCombineFSubFpExtFNegFMulToFMadOrFMA(), llvm::CombinerHelper::matchCombineInsertVecElts(), llvm::CombinerHelper::matchCombineTruncOfShift(), llvm::CombinerHelper::matchConstantFPOp(), llvm::CombinerHelper::matchConstantOp(), llvm::CombinerHelper::matchEqualDefs(), llvm::CombinerHelper::matchExtractVecEltBuildVec(), llvm::CombinerHelper::matchExtractVectorElementWithBuildVector(), llvm::CombinerHelper::matchExtractVectorElementWithBuildVectorTrunc(), llvm::CombinerHelper::matchExtractVectorElementWithDifferentIndices(), llvm::CombinerHelper::matchExtractVectorElementWithShuffleVector(), llvm::AMDGPUCombinerHelper::matchFoldableFneg(), llvm::CombinerHelper::matchFreezeOfSingleMaybePoisonOperand(), llvm::CombinerHelper::matchHoistLogicOpWithSameOpcodeHands(), llvm::CombinerHelper::matchMulOfVScale(), llvm::CombinerHelper::matchNarrowBinopFeedingAnd(), llvm::CombinerHelper::matchNonNegZext(), llvm::CombinerHelper::matchOperandIsKnownToBeAPowerOfTwo(), llvm::CombinerHelper::matchOperandIsUndef(), llvm::CombinerHelper::matchPtrAddImmedChain(), llvm::CombinerHelper::matchSelectIMinMax(), llvm::CombinerHelper::matchSextOfTrunc(), llvm::CombinerHelper::matchShiftImmedChain(), llvm::CombinerHelper::matchShiftOfShiftedLogic(), llvm::CombinerHelper::matchShlOfVScale(), llvm::CombinerHelper::matchSubOfVScale(), llvm::CombinerHelper::matchZextOfTrunc(), MIIsInTerminatorSequence(), llvm::LegalizerHelper::moreElementsVectorDst(), llvm::SIInstrInfo::moveFlatAddrToVGPR(), llvm::PeelingModuloScheduleExpander::moveStageBetweenBlocks(), llvm::SIInstrInfo::moveToVALUImpl(), MoveVPNOTBeforeFirstUser(), oneUseDominatesOtherUses(), llvm::ShapeT::operator==(), llvm::PPCInstrInfo::optimizeCmpPostRA(), llvm::AArch64InstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::X86InstrInfo::optimizeLoadInstr(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), llvm::RISCVInstrInfo::optimizeSelect(), llvm::CallLowering::parametersInCSRMatch(), parseCondBranch(), llvm::PeelSingleBlockLoop(), print(), llvm::CSKYAsmPrinter::PrintAsmMemoryOperand(), llvm::LoongArchAsmPrinter::PrintAsmMemoryOperand(), llvm::M68kAsmPrinter::PrintAsmMemoryOperand(), llvm::ARMAsmPrinter::PrintAsmMemoryOperand(), llvm::MipsAsmPrinter::PrintAsmMemoryOperand(), printAsmMRegister(), llvm::AMDGPUAsmPrinter::PrintAsmOperand(), llvm::MipsAsmPrinter::PrintAsmOperand(), llvm::CSKYAsmPrinter::PrintAsmOperand(), llvm::HexagonAsmPrinter::PrintAsmOperand(), llvm::LoongArchAsmPrinter::PrintAsmOperand(), llvm::SystemZAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::PrintAsmOperand(), llvm::AVRAsmPrinter::PrintAsmOperand(), printAsmVRegister(), printDstRegisterName(), llvm::ARMAsmPrinter::printOperand(), llvm::MipsAsmPrinter::printOperand(), llvm::AVRAsmPrinter::printOperand(), llvm::HexagonAsmPrinter::printOperand(), processNewInstrs(), llvm::ARMBaseInstrInfo::produceSameValue(), producesFalseLanesZero(), llvm::MachineInstr::readsWritesVirtualRegister(), llvm::TargetInstrInfo::reassociateOps(), TransferTracker::redefVar(), reduceDbgValsForwardScan(), llvm::WebAssemblyAsmPrinter::regToString(), reinsertVectorIndexAdd(), llvm::SIInstrInfo::reMaterialize(), llvm::ARMBaseInstrInfo::reMaterialize(), llvm::X86InstrInfo::reMaterialize(), removeCopies(), RemoveDeadAddBetweenLEAAndJT(), llvm::MachineRegisterInfo::removeRegOperandFromUseList(), llvm::LiveVariables::removeVirtualRegistersKilled(), llvm::RegBankSelect::RepairingPlacement::RepairingPlacement(), llvm::RegBankSelect::repairReg(), rescheduleCanonically(), llvm::R600InstrInfo::reverseBranchCondition(), llvm::MachineSSAUpdater::RewriteUse(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::MachineFunction::salvageCopySSAImpl(), llvm::R600SchedStrategy::schedNode(), setIsRenamable(), llvm::MachineInstr::setPhysRegsDeadExcept(), setReg(), llvm::MachineInstr::setRegisterDefReadUndef(), llvm::AArch64InstrInfo::shouldClusterMemOps(), llvm::PPCInstrInfo::shouldClusterMemOps(), SinkingPreventsImplicitNullCheck(), splitMBB(), llvm::stableHashValue(), llvm::MachineInstr::substituteRegister(), swapRegAndNonRegOperand(), llvm::RegBankSelect::tryAvoidingSplit(), llvm::LegalizationArtifactCombiner::tryCombineExtract(), llvm::LegalizationArtifactCombiner::tryCombineUnmergeValues(), llvm::tryFoldSPUpdateIntoPushPop(), llvm::LegalizationArtifactCombiner::tryFoldUnmergeCast(), llvm::CombinerHelper::tryReassocBinOp(), llvm::X86InstrInfo::unfoldMemoryOperand(), UpdateCPSRDef(), UpdateCPSRUse(), llvm::HexagonPacketizerList::updateOffset(), UpdateOperandRegClass(), updateOperandRegConstraints(), updatePhysDepsDownwards(), UseReg(), llvm::SIInstrInfo::usesConstantBus(), validateAccessChain(), validateFunCallMachineDef(), validateGroupAsyncCopyPtr(), validateGroupWaitEventsPtr(), validatePtrTypes(), valueIsKnownNeverF32Denorm(), llvm::RegisterBankInfo::InstructionMapping::verify(), verifyCFIntrinsic(), llvm::SIInstrInfo::verifyInstruction(), VerifyLowRegs(), llvm::MachineRegisterInfo::verifyUseList(), and llvm::VirtRegAuxInfo::weightCalcHelper().

getRegLiveOut()

const uint32_t * llvm::MachineOperand::getRegLiveOut ( ) const

inline

getRegLiveOut - Returns a bit mask of live-out registers.

Definition at line 670 of file MachineOperand.h.

References assert(), and isRegLiveOut().

Referenced by print().

getRegMask()

const uint32_t * llvm::MachineOperand::getRegMask ( ) const

inline

getRegMask - Returns a bit mask of registers preserved by this RegMask operand.

Definition at line 659 of file MachineOperand.h.

References assert(), and isRegMask().

Referenced by clobbersPhysReg(), llvm::ScheduleDAGInstrs::fixupKills(), llvm::hash_value(), isIdenticalTo(), isMatchingStartStopPair(), print(), llvm::MIRParserImpl::setupRegisterInfo(), and llvm::stableHashValue().

getRegMaskSize()

static unsigned llvm::MachineOperand::getRegMaskSize ( unsigned  NumRegs )

inlinestatic

Returns number of elements needed for a regmask array.

Definition at line 665 of file MachineOperand.h.

Referenced by llvm::MachineFunction::allocateRegMask(), llvm::hash_value(), isIdenticalTo(), llvm::stableHashValue(), and llvm::AArch64RegisterInfo::UpdateCustomCallPreservedMask().

getShuffleMask()

ArrayRef< int > llvm::MachineOperand::getShuffleMask ( ) const

inline

Definition at line 622 of file MachineOperand.h.

References assert(), and isShuffleMask().

Referenced by llvm::GShuffleVector::getMask(), llvm::hash_value(), isExtractHiElt(), isIdenticalTo(), print(), and llvm::stableHashValue().

getSubReg()

unsigned llvm::MachineOperand::getSubReg ( ) const

inline

Definition at line 374 of file MachineOperand.h.

References assert(), and isReg().

Referenced by llvm::MachineInstr::addRegisterDefined(), llvm::ScheduleDAGInstrs::addVRegDefDeps(), llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(), attemptDebugCopyProp(), llvm::SIInstrInfo::buildExtractSubReg(), canFoldCopy(), llvm::HexagonInstrInfo::expandPostRAPseudo(), findUseBetween(), llvm::SIInstrInfo::foldImmediate(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), foldPatchpoint(), foldVGPRCopyIntoRegSequence(), llvm::HexagonInstrInfo::getBaseAndOffset(), getDefRegMask(), llvm::TargetInstrInfo::getExtractSubregInputs(), llvm::ARMBaseInstrInfo::getExtractSubregLikeInputs(), llvm::TargetInstrInfo::getInsertSubregInputs(), llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs(), getInstReadLaneMask(), llvm::ScheduleDAGInstrs::getLaneMaskForMO(), getNewSource(), llvm::SIInstrInfo::getOpSize(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), getRC32(), llvm::PPCRegisterInfo::getRegAllocationHints(), llvm::RISCVRegisterInfo::getRegAllocationHints(), llvm::SystemZRegisterInfo::getRegAllocationHints(), llvm::MachineInstr::getRegClassConstraintEffect(), llvm::SIRegisterInfo::getRegClassForOperandReg(), llvm::TargetInstrInfo::getRegSequenceInputs(), llvm::ARMBaseInstrInfo::getRegSequenceLikeInputs(), llvm::hash_value(), INITIALIZE_PASS(), instrToSignature(), isAGPRCopy(), isCrossCopy(), llvm::MachineInstr::isFullCopy(), llvm::TargetInstrInfo::isFullCopyInstr(), isIdenticalTo(), llvm::MachineInstr::isIdentityCopy(), llvm::SIInstrInfo::isLegalRegOperand(), llvm::SIInstrInfo::isOperandLegal(), isSSA(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::ARMAsmPrinter::lowerOperand(), llvm::LowerPPCMachineOperandToMCOperand(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeLoadInstr(), print(), llvm::ARMAsmPrinter::printOperand(), readsReg(), llvm::MachineInstr::readsWritesVirtualRegister(), llvm::SIInstrInfo::reMaterialize(), llvm::MachineInstr::setRegisterDefReadUndef(), llvm::TailDuplicator::shouldTailDuplicate(), llvm::stableHashValue(), substPhysReg(), substVirtReg(), swapRegAndNonRegOperand(), llvm::SIInstrInfo::verifyInstruction(), and llvm::VirtRegAuxInfo::weightCalcHelper().

getSymbolName()

const char * llvm::MachineOperand::getSymbolName ( ) const

inline

Definition at line 637 of file MachineOperand.h.

References assert(), and isSymbol().

Referenced by llvm::BTFDebug::beginInstruction(), llvm::SystemZMCInstLower::getExpr(), llvm::AArch64MCInstLower::GetExternalSymbolSymbol(), llvm::BPFMCInstLower::GetExternalSymbolSymbol(), llvm::LanaiMCInstLower::GetExternalSymbolSymbol(), llvm::MSP430MCInstLower::GetExternalSymbolSymbol(), getMovOperand(), llvm::M68kMCInstLower::GetSymbolFromOperand(), GetSymbolFromOperand(), llvm::hash_value(), isIdenticalTo(), isSimilarDispOp(), llvm::lowerLoongArchMachineOperandToMCOperand(), LowerOperand(), llvm::ARMAsmPrinter::lowerOperand(), AMDGPUMCInstLower::lowerOperand(), llvm::CSKYMCInstLower::lowerOperand(), LowerSymbolOperand(), llvm::XtensaAsmPrinter::LowerSymbolOperand(), llvm::AArch64MCInstLower::lowerSymbolOperandELF(), llvm::WebAssembly::mayThrow(), optimizeCall(), print(), llvm::WebAssemblyAsmPrinter::PrintAsmOperand(), llvm::AVRAsmPrinter::printOperand(), and llvm::stableHashValue().

getTargetFlags()

unsigned llvm::MachineOperand::getTargetFlags ( ) const

inline

Definition at line 226 of file MachineOperand.h.

References isReg().

Referenced by llvm::MachineInstrBuilder::addDisp(), emitDirectiveRelocJalr(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::MipsInstrInfo::genInstrWithNewOpc(), llvm::MSP430MCInstLower::GetBlockAddressSymbol(), llvm::MSP430MCInstLower::GetConstantPoolIndexSymbol(), llvm::MSP430MCInstLower::GetExternalSymbolSymbol(), llvm::AArch64MCInstLower::GetGlobalAddressSymbol(), llvm::MSP430MCInstLower::GetGlobalAddressSymbol(), llvm::MSP430MCInstLower::GetJumpTableSymbol(), getMovOperand(), GetSymbolRef(), getTOCEntryTypeForMO(), llvm::hash_value(), INITIALIZE_PASS(), llvm::HexagonInstrInfo::isConstExtended(), isIdenticalTo(), llvm::WebAssemblyMCInstLower::lower(), llvm::SystemZMCInstLower::lowerOperand(), llvm::ARMAsmPrinter::lowerOperand(), AMDGPUMCInstLower::lowerOperand(), LowerSymbolOperand(), llvm::CSKYMCInstLower::lowerSymbolOperand(), llvm::LanaiMCInstLower::LowerSymbolOperand(), llvm::M68kMCInstLower::LowerSymbolOperand(), llvm::MSP430MCInstLower::LowerSymbolOperand(), lowerSymbolOperand(), llvm::AVRMCInstLower::lowerSymbolOperand(), llvm::AArch64MCInstLower::lowerSymbolOperandCOFF(), llvm::AArch64MCInstLower::lowerSymbolOperandELF(), llvm::AArch64MCInstLower::lowerSymbolOperandMachO(), llvm::ARMAsmPrinter::printOperand(), llvm::MipsAsmPrinter::printOperand(), llvm::ARMAsmPrinter::PrintSymbolOperand(), llvm::stableHashValue(), and swapRegAndNonRegOperand().

getTargetIndexName()

const char * MachineOperand::getTargetIndexName

(

)

const

getTargetIndexName - If this MachineOperand is a TargetIndex that has a name, attempt to get the name.

Returns nullptr if the TargetIndex does not have a name. Asserts if MO is not a TargetIndex.

Definition at line 476 of file MachineOperand.cpp.

References getIndex(), getMFIfAvailable(), and getTargetIndexName().

Referenced by getTargetIndexName(), print(), and llvm::stableHashValue().

getType()

MachineOperandType llvm::MachineOperand::getType ( ) const

inline

getType - Returns the MachineOperandType for this operand.

Definition at line 224 of file MachineOperand.h.

Referenced by llvm::MachineInstrBuilder::addDisp(), compareMachineOp(), getCodeModel(), llvm::SystemZMCInstLower::getExpr(), getMCSymbolForTOCPseudoMO(), getMovOperand(), getTOCEntryTypeForMO(), llvm::hash_value(), INITIALIZE_PASS(), instrToSignature(), IsAnAddressOperand(), isIdenticalTo(), llvm::WebAssemblyMCInstLower::lower(), llvm::SPIRVMCInstLower::lower(), llvm::lowerLoongArchMachineOperandToMCOperand(), llvm::M68kMCInstLower::LowerOperand(), LowerOperand(), llvm::SystemZMCInstLower::lowerOperand(), llvm::MipsMCInstLower::LowerOperand(), llvm::ARMAsmPrinter::lowerOperand(), llvm::AArch64MCInstLower::lowerOperand(), AMDGPUMCInstLower::lowerOperand(), llvm::CSKYMCInstLower::lowerOperand(), llvm::ARCMCInstLower::LowerOperand(), llvm::XCoreMCInstLower::LowerOperand(), llvm::XtensaAsmPrinter::lowerOperand(), llvm::LowerPPCMachineOperandToMCOperand(), lowerRISCVVMachineInstrToMCInst(), LowerSymbolOperand(), print(), llvm::M68kAsmPrinter::PrintAsmMemoryOperand(), llvm::X86AsmPrinter::PrintAsmOperand(), llvm::CSKYAsmPrinter::PrintAsmOperand(), llvm::LoongArchAsmPrinter::PrintAsmOperand(), llvm::WebAssemblyAsmPrinter::PrintAsmOperand(), llvm::AVRAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::printOperand(), llvm::MipsAsmPrinter::printOperand(), llvm::AVRAsmPrinter::printOperand(), llvm::HexagonAsmPrinter::printOperand(), llvm::AArch64InstrInfo::shouldClusterMemOps(), and llvm::stableHashValue().

isBlockAddress()

bool llvm::MachineOperand::isBlockAddress ( ) const

inline

isBlockAddress - Tests if this is a MO_BlockAddress operand.

Definition at line 351 of file MachineOperand.h.

References MO_BlockAddress.

Referenced by getBlockAddress(), getOffset(), INITIALIZE_PASS(), llvm::HexagonInstrInfo::isConstExtended(), isSimilarDispOp(), isValidDispOp(), llvm::LoongArchAsmPrinter::PrintAsmMemoryOperand(), processSwitches(), and setOffset().

isCFIIndex()

bool llvm::MachineOperand::isCFIIndex ( ) const

inline

Definition at line 360 of file MachineOperand.h.

References MO_CFIIndex.

Referenced by getCFIIndex().

isCImm()

bool llvm::MachineOperand::isCImm ( ) const

inline

isCImm - Test if this is a MO_CImmediate operand.

Definition at line 333 of file MachineOperand.h.

References MO_CImmediate.

Referenced by llvm::GISelInstProfileBuilder::addNodeIDMachineOperand(), llvm::GIMatchTableExecutor::executeMatchTable(), llvm::generateGroupUniformInst(), llvm::generateSpecConstantInst(), getCImm(), llvm::getConstFromIntrinsic(), getImmedFromMO(), isCandidate(), setCImm(), and llvm::stableHashValue().

isCPI()

bool llvm::MachineOperand::isCPI ( ) const

inline

isCPI - Tests if this is a MO_ConstantPoolIndex operand.

Definition at line 341 of file MachineOperand.h.

References MO_ConstantPoolIndex.

Referenced by llvm::X86::getConstantFromPool(), getIndex(), getOffset(), INITIALIZE_PASS(), isAnImmediateOperand(), isCandidate(), llvm::HexagonInstrInfo::isConstExtended(), isSimilarDispOp(), isValidDispOp(), setIndex(), setOffset(), and smallData().

isDbgInstrRef()

bool llvm::MachineOperand::isDbgInstrRef ( ) const

inline

Definition at line 359 of file MachineOperand.h.

References MO_DbgInstrRef.

Referenced by getInstrRefInstrIndex(), getInstrRefOpIndex(), setInstrRefInstrIndex(), and setInstrRefOpIndex().

isDead()

bool llvm::MachineOperand::isDead ( ) const

inline

Definition at line 394 of file MachineOperand.h.

References assert(), and isReg().

Referenced by llvm::ScheduleDAGInstrs::addPhysRegDeps(), llvm::MachineInstr::addRegisterDead(), llvm::ScheduleDAGInstrs::addVRegDefDeps(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::MachineInstr::allDefsAreDead(), llvm::MachineInstr::allImplicitDefsAreDead(), ChangeToRegister(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), CreateReg(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::ARMBaseInstrInfo::foldImmediate(), getClobberType(), getMopState(), llvm::getRegState(), llvm::X86InstrInfo::hasReassociableOperands(), isCandidate(), llvm::MachineInstr::isIdenticalTo(), moveAndTeeForMultiUse(), print(), llvm::X86InstrInfo::setSpecialOperandAttr(), swapRegAndNonRegOperand(), and UpdateCPSRDef().

isDebug()

bool llvm::MachineOperand::isDebug ( ) const

inline

Definition at line 455 of file MachineOperand.h.

References assert(), and isReg().

Referenced by llvm::MachineInstr::addRegisterKilled(), canRenameUpToDef(), ChangeToRegister(), CreateReg(), llvm::getRegState(), setIsDef(), setIsKill(), and swapRegAndNonRegOperand().

isDef()

bool llvm::MachineOperand::isDef ( ) const

inline

Definition at line 384 of file MachineOperand.h.

References assert(), and isReg().

Referenced by llvm::GISelInstProfileBuilder::addNodeIDMachineOperand(), llvm::ScheduleDAGInstrs::addPhysRegDataDeps(), llvm::MachineInstr::addRegisterDead(), llvm::MachineInstr::addRegisterDefined(), llvm::MachineRegisterInfo::addRegOperandToUseList(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::AnalyzeVirtRegInBundle(), llvm::BTFDebug::beginInstruction(), llvm::CriticalAntiDepBreaker::BreakAntiDependencies(), llvm::ScheduleDAGInstrs::buildSchedGraph(), canRenameMOP(), canRenameUpToDef(), ChangeToRegister(), llvm::MachineInstr::clearRegisterDeads(), llvm::constrainOperandRegClass(), llvm::PPCInstrInfo::convertToImmediateForm(), CreateReg(), llvm::HexagonHazardRecognizer::EmitInstruction(), findDeadCallerSavedReg(), findDefIdx(), llvm::MachineInstr::findRegisterDefOperandIdx(), findUseIdx(), llvm::ScheduleDAGInstrs::fixupKills(), llvm::X86InstrInfo::foldMemoryOperandImpl(), getDefRegMask(), llvm::MachineInstrExpressionTrait::getHashValue(), getInstReadLaneMask(), llvm::PPCInstrInfo::getInstrLatency(), llvm::PatchPointOpers::getNextScratchIdx(), llvm::MachineInstr::getNumExplicitDefs(), llvm::getRegState(), llvm::RegBankSelect::getRepairCost(), llvm::hash_value(), hasRegisterDependency(), INITIALIZE_PASS(), insertInlineAsmProcess(), instrToSignature(), isCandidate(), llvm::WebAssembly::isChild(), llvm::MachineInstr::isIdenticalTo(), isIdenticalTo(), llvm::MachineInstr::isRegTiedToUseOperand(), isRenamable(), IsSafeAndProfitableToMove(), isValidRegDef(), MIIsInTerminatorSequence(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeLoadInstr(), llvm::MachineInstr::print(), print(), printImplicitRegisterFlag(), llvm::RegBankSelect::RepairingPlacement::RepairingPlacement(), llvm::RegBankSelect::repairReg(), rescheduleCanonically(), llvm::MachineInstr::setPhysRegsDeadExcept(), llvm::MachineInstr::setRegisterDefReadUndef(), llvm::stableHashValue(), substPhysReg(), llvm::MachineInstr::tieOperands(), llvm::RegBankSelect::tryAvoidingSplit(), and UpdateCPSRUse().

isEarlyClobber()

bool llvm::MachineOperand::isEarlyClobber ( ) const

inline

Definition at line 445 of file MachineOperand.h.

References assert(), and isReg().

Referenced by canRenameMOP(), createDeadDef(), CreateReg(), dumpMachineInstrRangeWithSlotIndex(), getMopState(), llvm::PatchPointOpers::getNextScratchIdx(), and print().

isFI()

bool llvm::MachineOperand::isFI ( ) const

inline

isFI - Tests if this is a MO_FrameIndex operand.

Definition at line 339 of file MachineOperand.h.

References MO_FrameIndex.

Referenced by llvm::X86InstrInfo::describeLoadedValue(), llvm::TargetLoweringBase::emitPatchPoint(), getIndex(), llvm::SIInstrInfo::getMemOperandsWithOffsetWidth(), llvm::PPCInstrInfo::getMemOperandWithOffsetWidth(), llvm::RISCVInstrInfo::getMemOperandWithOffsetWidth(), llvm::AArch64InstrInfo::getMemOperandWithOffsetWidth(), isFIPlusImmOrVGPR(), llvm::SIInstrInfo::isImmOperandLegal(), isLdStSafeToCluster(), llvm::SIInstrInfo::isLegalVSrcOperand(), llvm::HexagonInstrInfo::isLoadFromStackSlot(), llvm::SIInstrInfo::isOperandLegal(), isRegOrFI(), llvm::HexagonInstrInfo::isStoreToStackSlot(), LowerCallResults(), llvm::AArch64FrameLowering::orderFrameObjects(), llvm::SystemZELFFrameLowering::orderFrameObjects(), llvm::SIRegisterInfo::resolveFrameIndex(), setIndex(), llvm::AArch64InstrInfo::shouldClusterMemOps(), llvm::PPCInstrInfo::shouldClusterMemOps(), swapRegAndNonRegOperand(), UpdateOperandRegClass(), and llvm::SIInstrInfo::verifyInstruction().

isFPImm()

bool llvm::MachineOperand::isFPImm ( ) const

inline

isFPImm - Tests if this is a MO_FPImmediate operand.

Definition at line 335 of file MachineOperand.h.

References MO_FPImmediate.

Referenced by llvm::GISelInstProfileBuilder::addNodeIDMachineOperand(), getFPImm(), isCandidate(), llvm::HexagonInstrInfo::isConstExtended(), isSameScalarConst(), setFPImm(), and llvm::SIInstrInfo::verifyInstruction().

isGlobal()

bool llvm::MachineOperand::isGlobal ( ) const

inline

isGlobal - Tests if this is a MO_GlobalAddress operand.

Definition at line 347 of file MachineOperand.h.

References MO_GlobalAddress.

Referenced by llvm::X86FrameLowering::adjustForHiPEPrologue(), llvm::BTFDebug::beginInstruction(), createCall(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::getAddressFromInstr(), getGlobal(), getOffset(), llvm::R600InstrInfo::getSrcs(), llvm::M68kMCInstLower::GetSymbolFromOperand(), GetSymbolFromOperand(), GetSymbolRef(), INITIALIZE_PASS(), llvm::BTFDebug::InstLower(), isAnImmediateOperand(), IsCallReturnTwice(), isCandidate(), llvm::HexagonInstrInfo::isConstExtended(), llvm::SIInstrInfo::isImmOperandLegal(), llvm::SIInstrInfo::isLegalVSrcOperand(), llvm::SIInstrInfo::isOperandLegal(), isSameScalarConst(), isSignExtendedW(), llvm::PPCInstrInfo::isSignOrZeroExtended(), isSimilarDispOp(), isValidDispOp(), llvm::AVRMCInstLower::lowerSymbolOperand(), llvm::AArch64MCInstLower::lowerSymbolOperandELF(), llvm::WebAssembly::mayThrow(), llvm::LoongArchAsmPrinter::PrintAsmMemoryOperand(), llvm::AsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::PrintSymbolOperand(), llvm::AsmPrinter::PrintSymbolOperand(), queryCallee(), llvm::DetectRoundChange::runOnMachineFunction(), setOffset(), smallData(), and swapRegAndNonRegOperand().

isIdenticalTo()

bool MachineOperand::isIdenticalTo

(

const MachineOperand &

Other

)

const

Returns true if this operand is identical to the specified operand except for liveness related flags (isKill, isUndef and isDead).

isIdenticalTo - Return true if this operand is identical to the specified operand.

Note that this should stay in sync with the hash_value overload below.

Definition at line 319 of file MachineOperand.cpp.

References getBlockAddress(), getCFIIndex(), getCImm(), getFPImm(), getGlobal(), getImm(), getIndex(), getInstrRefInstrIndex(), getInstrRefOpIndex(), getIntrinsicID(), getMBB(), getMCSymbol(), getMetadata(), getMFIfAvailable(), getOffset(), getPredicate(), getReg(), getRegMask(), getRegMaskSize(), getShuffleMask(), getSubReg(), getSymbolName(), getTargetFlags(), getType(), isDef(), llvm_unreachable, MO_BlockAddress, MO_CFIIndex, MO_CImmediate, MO_ConstantPoolIndex, MO_DbgInstrRef, MO_ExternalSymbol, MO_FPImmediate, MO_FrameIndex, MO_GlobalAddress, MO_Immediate, MO_IntrinsicID, MO_JumpTableIndex, MO_MachineBasicBlock, MO_MCSymbol, MO_Metadata, MO_Predicate, MO_Register, MO_RegisterLiveOut, MO_RegisterMask, MO_ShuffleMask, MO_TargetIndex, llvm::Other, and TRI.

Referenced by llvm::X86InstrInfo::analyzeBranchPredicate(), llvm::AArch64InstrInfo::areMemAccessesTriviallyDisjoint(), llvm::LanaiInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::PPCInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::RISCVInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::MachineInstr::isEquivalentDbgInstr(), isIdenticalOp(), llvm::MachineInstr::isIdenticalTo(), isImplicitOperandIn(), IsVPNOTEquivalent(), mayOverlapWrite(), LiveDebugValues::ResolvedDbgOp::operator==(), llvm::ARMBaseInstrInfo::produceSameValue(), llvm::AArch64InstrInfo::shouldClusterMemOps(), and llvm::SIInstrInfo::verifyInstruction().

isImm()

bool llvm::MachineOperand::isImm ( ) const

inline

isImm - Tests if this is a MO_Immediate operand.

Definition at line 331 of file MachineOperand.h.

References MO_Immediate.

Referenced by addConstantComments(), llvm::GISelInstProfileBuilder::addNodeIDMachineOperand(), llvm::HexagonInstrInfo::analyzeCompare(), areCombinableOperations(), llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::R600InstrInfo::buildSlotOfVectorInstruction(), canCompareBeNewValueJump(), llvm::RISCVInstrInfo::canFoldIntoAddrMode(), canFoldIntoCSel(), canInstrSubstituteCmpInstr(), llvm::PPCInstrInfo::combineRLWINM(), llvm::SIInstrInfo::convertToThreeAddress(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::PPCFrameLowering::emitEpilogue(), llvm::GIMatchTableExecutor::executeMatchTable(), llvm::MachineInstr::findInlineAsmFlagIdx(), llvm::MachineInstr::findTiedOperandIdx(), llvm::SIInstrInfo::foldImmediate(), llvm::AArch64InstrInfo::genAlternativeCodeSequence(), llvm::X86InstrInfo::getAddrModeFromMemoryOp(), llvm::HexagonInstrInfo::getBaseAndOffset(), llvm::HexagonInstrInfo::getBundleNoShuf(), llvm::HexagonInstrInfo::getCompoundOpcode(), llvm::X86InstrInfo::getConstValDefinedInReg(), llvm::TargetInstrInfo::getExtractSubregInputs(), llvm::R600InstrInfo::getFlagOp(), llvm::SIRegisterInfo::getFrameIndexInstrOffset(), getImm(), getImmedFromMO(), llvm::HexagonInstrInfo::getIncrementValue(), llvm::TargetInstrInfo::getInsertSubregInputs(), llvm::AArch64InstrInfo::getMemOpBaseRegImmOfsOffsetOperand(), llvm::X86InstrInfo::getMemOperandsWithOffsetWidth(), llvm::LanaiInstrInfo::getMemOperandWithOffsetWidth(), llvm::PPCInstrInfo::getMemOperandWithOffsetWidth(), llvm::RISCVInstrInfo::getMemOperandWithOffsetWidth(), llvm::AArch64InstrInfo::getMemOperandWithOffsetWidth(), getRegImmPairPreventingCompression(), llvm::TargetInstrInfo::getRegSequenceInputs(), llvm::R600InstrInfo::getSrcs(), getStoreOffset(), llvm::HexagonInstrInfo::immediateExtend(), indirectCopyToAGPR(), INITIALIZE_PASS(), insertInlineAsmProcess(), llvm::PPCInstrInfo::isADDIInstrEligibleForFolding(), llvm::MipsInstrInfo::isAddImmediate(), isAddSub2RegAndConstOnePair(), isAnImmediateOperand(), isCandidate(), llvm::HexagonInstrInfo::isConstExtended(), isConvertibleLEA(), llvm::MachineInstr::isDebugOffsetImm(), isFIPlusImmOrVGPR(), isIdentityValue(), llvm::PPCInstrInfo::isImmInstrEligibleForFolding(), llvm::SIInstrInfo::isImmOperandLegal(), llvm::SIInstrInfo::isInlineConstant(), isInvariantStore(), llvm::SIInstrInfo::isLegalVSrcOperand(), llvm::HexagonInstrInfo::isLoadFromStackSlot(), isLoadStoreThatCanHandleDisplacement(), llvm::SIInstrInfo::isOperandLegal(), isRelevantAddressingMode(), isSafeToFoldImmIntoCopy(), isSameScalarConst(), llvm::isScale(), isSimilarDispOp(), llvm::HexagonInstrInfo::isStoreToStackSlot(), isValidDispOp(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::MachineInstr::mayFoldInlineAsmRegOp(), llvm::SIInstrInfo::moveFlatAddrToVGPR(), llvm::SIInstrInfo::moveToVALUImpl(), needReorderStoreMI(), llvm::SIInstrInfo::optimizeCompareInstr(), llvm::TargetInstrInfo::PredicateInstruction(), llvm::MachineInstr::print(), llvm::LoongArchAsmPrinter::PrintAsmMemoryOperand(), llvm::MipsAsmPrinter::PrintAsmMemoryOperand(), llvm::AMDGPUAsmPrinter::PrintAsmOperand(), llvm::MipsAsmPrinter::PrintAsmOperand(), llvm::X86AsmPrinter::PrintAsmOperand(), llvm::AsmPrinter::PrintAsmOperand(), llvm::LoongArchAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::PrintAsmOperand(), llvm::recomputeVPTBlockMask(), llvm::SIRegisterInfo::resolveFrameIndex(), llvm::HexagonInstrInfo::setBundleNoShuf(), setImm(), swapRegAndNonRegOperand(), llvm::X86InstrInfo::unfoldMemoryOperand(), verifyInsExtInstruction(), llvm::SIInstrInfo::verifyInstruction(), and llvm::RISCVInstrInfo::verifyInstruction().

isImplicit()

bool llvm::MachineOperand::isImplicit ( ) const

inline

Definition at line 389 of file MachineOperand.h.

References assert(), and isReg().

Referenced by llvm::GISelInstProfileBuilder::addNodeIDMachineOperand(), llvm::AggressiveAntiDepBreaker::BreakAntiDependencies(), canRenameMOP(), llvm::TargetSchedModel::computeOperandLatency(), llvm::MachineInstr::copyImplicitOps(), llvm::HexagonHazardRecognizer::EmitInstruction(), llvm::PPCInstrInfo::getInstrLatency(), getMopState(), llvm::PatchPointOpers::getNextScratchIdx(), llvm::MachineInstr::getNumExplicitDefs(), llvm::MachineInstr::getNumExplicitOperands(), llvm::HexagonInstrInfo::getOperandLatency(), llvm::getRegState(), llvm::MachineInstr::hasRegisterImplicitUseOperand(), insertSEH(), isCandidate(), llvm::WebAssembly::isChild(), llvm::SIInstrInfo::isIgnorableUse(), isValidExcessOperand(), llvm::WebAssemblyMCInstLower::lower(), llvm::lowerLoongArchMachineOperandToMCOperand(), llvm::M68kMCInstLower::LowerOperand(), LowerOperand(), llvm::MipsMCInstLower::LowerOperand(), llvm::ARMAsmPrinter::lowerOperand(), llvm::AArch64MCInstLower::lowerOperand(), llvm::CSKYMCInstLower::lowerOperand(), llvm::ARCMCInstLower::LowerOperand(), llvm::XCoreMCInstLower::LowerOperand(), llvm::XtensaAsmPrinter::lowerOperand(), llvm::LowerPPCMachineOperandToMCOperand(), llvm::MachineInstr::print(), print(), printImplicitRegisterFlag(), llvm::PPCInstrInfo::replaceInstrOperandWithImm(), llvm::tryFoldSPUpdateIntoPushPop(), llvm::SIInstrInfo::usesConstantBus(), llvm::SIInstrInfo::verifyInstruction(), and VerifyLowRegs().

isInternalRead()

bool llvm::MachineOperand::isInternalRead ( ) const

inline

Definition at line 440 of file MachineOperand.h.

References assert(), and isReg().

Referenced by CreateReg(), llvm::getRegState(), print(), and readsReg().

isIntrinsicID()

bool llvm::MachineOperand::isIntrinsicID ( ) const

inline

Definition at line 361 of file MachineOperand.h.

References MO_IntrinsicID.

Referenced by llvm::GIMatchTableExecutor::executeMatchTable(), getIntrinsicID(), and setIntrinsicID().

isJTI()

bool llvm::MachineOperand::isJTI ( ) const

inline

isJTI - Tests if this is a MO_JumpTableIndex operand.

Definition at line 345 of file MachineOperand.h.

References MO_JumpTableIndex.

Referenced by getIndex(), getJumpTableIndexFromAddr(), GetSymbolRef(), llvm::HexagonInstrInfo::isConstExtended(), isSimilarDispOp(), isValidDispOp(), LowerSymbolOperand(), llvm::BPFMCInstLower::LowerSymbolOperand(), llvm::LanaiMCInstLower::LowerSymbolOperand(), llvm::M68kMCInstLower::LowerSymbolOperand(), llvm::MSP430MCInstLower::LowerSymbolOperand(), lowerSymbolOperand(), llvm::AVRMCInstLower::lowerSymbolOperand(), llvm::AArch64MCInstLower::lowerSymbolOperandCOFF(), llvm::AArch64MCInstLower::lowerSymbolOperandELF(), llvm::AArch64MCInstLower::lowerSymbolOperandMachO(), setIndex(), and smallData().

isKill()

bool llvm::MachineOperand::isKill ( ) const

inline

Definition at line 399 of file MachineOperand.h.

References assert(), and isReg().

Referenced by llvm::MachineInstr::addRegisterKilled(), ChangeToRegister(), llvm::MachineInstr::clearRegisterKills(), combineFPFusedMultiply(), llvm::PPCInstrInfo::combineRLWINM(), copyFlagsToImplicitVCC(), CreateReg(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::MachineInstr::findRegisterUseOperandIdx(), llvm::PPCInstrInfo::foldFrameOffset(), llvm::SIInstrInfo::foldImmediate(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), genAlternativeDpCodeSequence(), genFNegatedMAD(), genFusedMultiply(), genSubAdd2SubSub(), getMopState(), llvm::getRegState(), insertDivByZeroTrap(), isBackwardPropagatableCopy(), llvm::MachineInstr::isIdenticalTo(), llvm::PPCInstrInfo::isImmInstrEligibleForFolding(), isOperandKill(), llvm::PPCInstrInfo::isValidToBeChangedReg(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::TargetInstrInfo::lowerCopy(), preserveCondRegFlags(), print(), llvm::TargetInstrInfo::reassociateOps(), llvm::LiveVariables::removeVirtualRegistersKilled(), swapRegAndNonRegOperand(), UpdateCPSRUse(), and updateKillStatus().

isMBB()

bool llvm::MachineOperand::isMBB ( ) const

inline

isMBB - Tests if this is a MO_MachineBasicBlock operand.

Definition at line 337 of file MachineOperand.h.

References MO_MachineBasicBlock.

Referenced by llvm::HexagonInstrInfo::analyzeBranch(), llvm::PPCInstrInfo::analyzeBranch(), llvm::HexagonInstrInfo::getDotNewPredJumpOp(), getMBB(), llvm::M68kMCInstLower::GetSymbolFromOperand(), getTargetMBB(), llvm::HexagonInstrInfo::immediateExtend(), llvm::HexagonInstrInfo::isConstExtended(), isSimilarDispOp(), isValidDispOp(), LowerSymbolOperand(), llvm::M68kMCInstLower::LowerSymbolOperand(), lowerSymbolOperand(), llvm::TargetInstrInfo::PredicateInstruction(), setMBB(), and splitEdge().

isMCSymbol()

bool llvm::MachineOperand::isMCSymbol ( ) const

inline

Definition at line 358 of file MachineOperand.h.

References MO_MCSymbol.

Referenced by emitDirectiveRelocJalr(), llvm::MipsInstrInfo::genInstrWithNewOpc(), getMCSymbol(), getOffset(), INITIALIZE_PASS(), isSimilarDispOp(), isValidDispOp(), isValidExcessOperand(), llvm::LoongArchAsmPrinter::PrintAsmMemoryOperand(), and setOffset().

isMetadata()

bool llvm::MachineOperand::isMetadata ( ) const

inline

isMetadata - Tests if this is a MO_Metadata operand.

Definition at line 357 of file MachineOperand.h.

References MO_Metadata.

Referenced by getMetadata(), insertInlineAsmProcess(), isValidExcessOperand(), llvm::MachineInstr::print(), and setMetadata().

isPredicate()

bool llvm::MachineOperand::isPredicate ( ) const

inline

Definition at line 362 of file MachineOperand.h.

References MO_Predicate.

Referenced by llvm::GISelInstProfileBuilder::addNodeIDMachineOperand(), llvm::GIMatchTableExecutor::executeMatchTable(), getPredicate(), and setPredicate().

isReg()

bool llvm::MachineOperand::isReg ( ) const

inline

isReg - Tests if this is a MO_Register operand.

Definition at line 329 of file MachineOperand.h.

References MO_Register.

Referenced by addInstrRequirements(), llvm::GISelInstProfileBuilder::addNodeIDMachineOperand(), llvm::MachineInstr::addOperand(), llvm::MachineInstr::addRegisterDead(), llvm::MachineInstr::addRegisterDefined(), llvm::MachineInstr::addRegisterKilled(), addTargetFlag(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::HexagonSubtarget::adjustSchedDependency(), llvm::MachineInstr::allDefsAreDead(), llvm::MachineInstr::allImplicitDefsAreDead(), llvm::AnalyzeVirtRegInBundle(), llvm::HexagonSubtarget::BankConflictMutation::apply(), llvm::RegisterBankInfo::applyDefaultMapping(), llvm::BTFDebug::beginInstruction(), llvm::CriticalAntiDepBreaker::BreakAntiDependencies(), llvm::buildAtomicCompareExchangeInst(), llvm::buildEnqueueKernel(), llvm::BuildMI(), llvm::buildNDRange(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::ModuloScheduleExpanderMVE::canApply(), canCombine(), canCombineFPFusedMultiply(), llvm::HexagonInstrInfo::canExecuteInBundle(), llvm::AArch64InstrInfo::canFoldIntoAddrMode(), llvm::RISCVInstrInfo::canFoldIntoAddrMode(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), canRenameMOP(), canRenameUpToDef(), llvm::SIInstrInfo::canShrink(), ChangeToBA(), ChangeToDbgInstrRef(), ChangeToES(), ChangeToFPImmediate(), ChangeToFrameIndex(), ChangeToGA(), ChangeToImmediate(), ChangeToMCSymbol(), ChangeToRegister(), ChangeToTargetIndex(), llvm::checkVOPDRegConstraints(), llvm::MachineInstr::clearKillInfo(), llvm::MachineInstr::clearRegisterDeads(), llvm::MachineInstr::clearRegisterKills(), llvm::SIInstrInfo::commuteInstructionImpl(), CompressEVEXImpl(), llvm::RegBankSelect::computeMapping(), llvm::constrainSelectedInstRegOperands(), llvm::PPCInstrInfo::convertToImmediateForm(), llvm::SIInstrInfo::convertToThreeAddress(), llvm::MachineInstr::copyImplicitOps(), copyRegOperand(), createCall(), createCallWithOps(), llvm::X86InstrInfo::describeLoadedValue(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), emitIndirectDst(), llvm::HexagonHazardRecognizer::EmitInstruction(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::TargetLoweringBase::emitPatchPoint(), eraseGPOpnd(), llvm::GIMatchTableExecutor::executeMatchTable(), findDeadCallerSavedReg(), findDefIdx(), findNextInsertLocation(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::findRegisterUseOperandIdx(), llvm::MachineInstr::findTiedOperandIdx(), findUseIdx(), llvm::ScheduleDAGInstrs::fixupKills(), llvm::SwingSchedulerDAG::fixupRegisterOverlaps(), llvm::SIInstrInfo::foldImmediate(), fuseInst(), llvm::getAddressFromInstr(), getArrayComponentCount(), getBaseAddressRegister(), llvm::getBlockStructInstr(), getCallTargetRegOpnd(), llvm::getConstFromIntrinsic(), getDefRegMask(), getFMAPatterns(), getFMULPatterns(), getFoldableImm(), getFPReg(), llvm::MachineInstrExpressionTrait::getHashValue(), getImmedFromMO(), getInstReadLaneMask(), llvm::PPCInstrInfo::getInstrLatency(), llvm::ARMRegisterBankInfo::getInstrMapping(), llvm::RegisterBankInfo::getInstrMappingImpl(), llvm::SIInstrInfo::getInstructionUniformity(), getMaddPatterns(), llvm::SIInstrInfo::getMemOperandsWithOffsetWidth(), llvm::HexagonInstrInfo::getMemOperandsWithOffsetWidth(), llvm::X86InstrInfo::getMemOperandsWithOffsetWidth(), llvm::LanaiInstrInfo::getMemOperandWithOffsetWidth(), llvm::PPCInstrInfo::getMemOperandWithOffsetWidth(), llvm::RISCVInstrInfo::getMemOperandWithOffsetWidth(), llvm::AArch64InstrInfo::getMemOperandWithOffsetWidth(), llvm::ReachingDefAnalysis::getMIOperand(), llvm::PatchPointOpers::getNextScratchIdx(), llvm::MachineInstr::getNumExplicitDefs(), llvm::MachineInstr::getNumExplicitOperands(), llvm::HexagonInstrInfo::getOperandLatency(), llvm::SIInstrInfo::getOpSize(), getPostIncrementOperand(), getReg(), llvm::MachineInstr::getRegClassConstraintEffect(), getRegOrUndef(), llvm::getRegState(), llvm::RegBankSelect::getRepairCost(), getShuffleComment(), getSubReg(), getTargetFlags(), llvm::getVRegSubRegDef(), hasLiveThroughUse(), llvm::TargetInstrInfo::hasReassociableOperands(), llvm::RISCVInstrInfo::hasReassociableOperands(), hasRegisterDependency(), llvm::MachineInstr::hasRegisterImplicitUseOperand(), hasSameBaseOpValue(), indirectCopyToAGPR(), INITIALIZE_PASS(), llvm::MachineInstr::insert(), insertInlineAsmProcess(), insertSEH(), instrToSignature(), llvm::AArch64InstrInfo::isAddImmediate(), llvm::ARMBaseInstrInfo::isAddImmediate(), llvm::MipsInstrInfo::isAddImmediate(), llvm::RISCVInstrInfo::isAddImmediate(), isArithmeticBccPair(), llvm::GIMatchTableExecutor::isBaseWithConstantOffset(), isCandidate(), llvm::WebAssembly::isChild(), isConstReg(), isDead(), isDebug(), isDef(), isEarlyClobber(), isFIPlusImmOrVGPR(), isIdenticalOp(), llvm::MachineInstr::isIdenticalTo(), isImm(), llvm::PPCInstrInfo::isImmInstrEligibleForFolding(), isImplicit(), llvm::MachineInstr::isIndirectDebugValue(), llvm::SIInstrInfo::isInlineConstant(), isInternalRead(), isInvariantStore(), isKill(), isLdStSafeToCluster(), llvm::SIInstrInfo::isLegalRegOperand(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), llvm::SIInstrInfo::isLegalVSrcOperand(), isLogicalOpOnExec(), llvm::SMSchedule::isLoopCarriedDefOfUse(), isMatchingStartStopPair(), isMMSourceRegister(), isMMThreeBitGPRegister(), llvm::GIMatchTableExecutor::isOperandImmEqual(), llvm::SIInstrInfo::isOperandLegal(), llvm::M68kInstrInfo::isPCRelRegisterOperandLegal(), isRedundantFlagInstr(), isRegInClass(), isRegOrFI(), llvm::MachineInstr::isRegTiedToDefOperand(), llvm::MachineInstr::isRegTiedToUseOperand(), isRelevantAddressingMode(), isRenamable(), IsSafeAndProfitableToMove(), isSVERegOp(), isTied(), isTileDef(), isTileRegDef(), llvm::HexagonInstrInfo::isToBeScheduledASAP(), isTwoAddrUse(), isUndef(), isUse(), isValidExcessOperand(), isVirtualRegisterOperand(), isWaitInstr(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::legalizeOperandsVOP3(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::WebAssemblyMCInstLower::lower(), LowerCallResults(), lowerRISCVVMachineInstrToMCInst(), llvm::MIPatternMatch::operand_type_match::match(), llvm::CombinerHelper::matchConstantFPOp(), llvm::CombinerHelper::matchConstantOp(), llvm::CombinerHelper::matchEqualDefs(), llvm::CombinerHelper::matchHoistLogicOpWithSameOpcodeHands(), llvm::CombinerHelper::matchOperandIsUndef(), mergeOperations(), MIIsInTerminatorSequence(), llvm::PeelingModuloScheduleExpander::moveStageBetweenBlocks(), oneUseDominatesOtherUses(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeLoadInstr(), llvm::TargetInstrInfo::PredicateInstruction(), llvm::MachineInstr::print(), llvm::CSKYAsmPrinter::PrintAsmMemoryOperand(), llvm::LoongArchAsmPrinter::PrintAsmMemoryOperand(), llvm::ARMAsmPrinter::PrintAsmMemoryOperand(), llvm::AVRAsmPrinter::PrintAsmMemoryOperand(), llvm::MipsAsmPrinter::PrintAsmMemoryOperand(), llvm::AMDGPUAsmPrinter::PrintAsmOperand(), llvm::MipsAsmPrinter::PrintAsmOperand(), llvm::X86AsmPrinter::PrintAsmOperand(), llvm::AsmPrinter::PrintAsmOperand(), llvm::HexagonAsmPrinter::PrintAsmOperand(), llvm::SystemZAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::PrintAsmOperand(), llvm::AVRAsmPrinter::PrintAsmOperand(), producesFalseLanesZero(), readsReg(), llvm::MachineInstr::readsWritesVirtualRegister(), TransferTracker::redefVar(), reduceDbgValsBackwardScan(), reduceDbgValsForwardScan(), removeRegisterOperands(), llvm::LiveVariables::removeVirtualRegistersKilled(), llvm::RegBankSelect::RepairingPlacement::RepairingPlacement(), rescheduleCanonically(), llvm::R600SchedStrategy::schedNode(), setImplicit(), setIsDead(), setIsDebug(), setIsDef(), setIsEarlyClobber(), setIsInternalRead(), setIsKill(), setIsRenamable(), setIsUndef(), llvm::MachineInstr::setPhysRegsDeadExcept(), llvm::MachineInstr::setRegisterDefReadUndef(), setSubReg(), setTargetFlags(), llvm::AArch64InstrInfo::shouldClusterMemOps(), llvm::PPCInstrInfo::shouldClusterMemOps(), SinkingPreventsImplicitNullCheck(), llvm::MachineInstr::substituteRegister(), llvm::tryFoldSPUpdateIntoPushPop(), llvm::X86InstrInfo::unfoldMemoryOperand(), llvm::MachineInstr::untieRegOperand(), UpdateCPSRDef(), UpdateCPSRUse(), updateKillStatus(), UpdateOperandRegClass(), updateOperandRegConstraints(), UseReg(), llvm::SIInstrInfo::usesConstantBus(), llvm::RegisterBankInfo::InstructionMapping::verify(), llvm::SIInstrInfo::verifyInstruction(), VerifyLowRegs(), and llvm::MachineRegisterInfo::verifyUseList().

isRegLiveOut()

bool llvm::MachineOperand::isRegLiveOut ( ) const

inline

isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.

Definition at line 355 of file MachineOperand.h.

References MO_RegisterLiveOut.

Referenced by getRegLiveOut().

isRegMask()

bool llvm::MachineOperand::isRegMask ( ) const

inline

isRegMask - Tests if this is a MO_RegisterMask operand.

Definition at line 353 of file MachineOperand.h.

References MO_RegisterMask.

Referenced by llvm::MachineInstr::copyImplicitOps(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::ScheduleDAGInstrs::fixupKills(), getRegMask(), isValidExcessOperand(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::MachineInstr::setPhysRegsDeadExcept(), setRegMask(), and llvm::MIRParserImpl::setupRegisterInfo().

isRenamable()

bool MachineOperand::isRenamable

(

)

const

isRenamable - Returns true if this register may be renamed, i.e.

it does not generate a value that is somehow read in a way that is not represented by the Machine IR (e.g. to meet an ABI or ISA requirement). This is only valid on physical register operands. Virtual registers are assumed to always be renamable regardless of the value of this field.

Operands that are renamable can freely be changed to any other register that is a member of the register class returned by MI->getRegClassConstraint().

isRenamable can return false for several different reasons:

• ABI constraints (since liveness is not always precisely modeled). We conservatively handle these cases by setting all physical register operands that didn’t start out as virtual regs to not be renamable. Also any physical register operands created after register allocation or whose register is changed after register allocation will not be renamable. This state is tracked in the MachineOperand::IsRenamable bit.
• Opcode/target constraints: for opcodes that have complex register class requirements (e.g. that depend on other operands/instructions), we set hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq in the machine opcode description. Operands belonging to instructions with opcodes that are marked hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq return false from isRenamable(). Additionally, the AllowRegisterRenaming target property prevents any operands from being marked renamable for targets that don't have detailed opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq values.

Definition at line 124 of file MachineOperand.cpp.

References assert(), getParent(), getReg(), llvm::MachineInstr::IgnoreBundle, isDef(), isReg(), isUse(), and MI.

Referenced by canRenameMOP(), CreateReg(), getMopState(), llvm::getRegState(), isBackwardPropagatableCopy(), and print().

isShuffleMask()

bool llvm::MachineOperand::isShuffleMask ( ) const

inline

Definition at line 363 of file MachineOperand.h.

References MO_ShuffleMask.

Referenced by getShuffleMask().

isSymbol()

bool llvm::MachineOperand::isSymbol ( ) const

inline

isSymbol - Tests if this is a MO_ExternalSymbol operand.

Definition at line 349 of file MachineOperand.h.

References MO_ExternalSymbol.

Referenced by getOffset(), llvm::M68kMCInstLower::GetSymbolFromOperand(), GetSymbolFromOperand(), getSymbolName(), isCandidate(), llvm::HexagonInstrInfo::isConstExtended(), isSimilarDispOp(), isValidDispOp(), llvm::AArch64MCInstLower::lowerSymbolOperandELF(), llvm::WebAssembly::mayThrow(), optimizeCall(), and setOffset().

isTargetIndex()

bool llvm::MachineOperand::isTargetIndex ( ) const

inline

isTargetIndex - Tests if this is a MO_TargetIndex operand.

Definition at line 343 of file MachineOperand.h.

References MO_TargetIndex.

Referenced by getIndex(), getOffset(), llvm::SIInstrInfo::isImmOperandLegal(), llvm::SIInstrInfo::isLegalVSrcOperand(), llvm::SIInstrInfo::isOperandLegal(), setIndex(), and setOffset().

isTied()

bool llvm::MachineOperand::isTied ( ) const

inline

Definition at line 450 of file MachineOperand.h.

References assert(), and isReg().

Referenced by canRenameMOP(), ChangeToBA(), ChangeToDbgInstrRef(), ChangeToES(), ChangeToFPImmediate(), ChangeToFrameIndex(), ChangeToGA(), ChangeToImmediate(), ChangeToMCSymbol(), ChangeToTargetIndex(), llvm::TargetLoweringBase::emitPatchPoint(), llvm::MachineInstr::findTiedOperandIdx(), llvm::MachineInstr::insert(), llvm::MachineInstr::isRegTiedToDefOperand(), llvm::MachineInstr::isRegTiedToUseOperand(), isTiedToNotUndef(), lowerRISCVVMachineInstrToMCInst(), llvm::MachineInstr::print(), print(), llvm::MachineInstr::tieOperands(), and llvm::MachineInstr::untieRegOperand().

isUndef()

bool llvm::MachineOperand::isUndef ( ) const

inline

Definition at line 404 of file MachineOperand.h.

References assert(), and isReg().

Referenced by llvm::MachineInstr::addRegisterKilled(), llvm::ScheduleDAGInstrs::addVRegDefDeps(), allPhiOperandsUndefined(), ChangeToRegister(), copyFlagsToImplicitVCC(), createCallWithOps(), CreateReg(), llvm::HexagonInstrInfo::expandPostRAPseudo(), expandSHXDROT(), findUseBetween(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::TargetInstrInfo::getExtractSubregInputs(), llvm::ARMBaseInstrInfo::getExtractSubregLikeInputs(), llvm::TargetInstrInfo::getInsertSubregInputs(), llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs(), getInstReadLaneMask(), getMopState(), getRegOrUndef(), llvm::TargetInstrInfo::getRegSequenceInputs(), llvm::ARMBaseInstrInfo::getRegSequenceLikeInputs(), llvm::getRegState(), llvm::getVRegSubRegDef(), llvm::HexagonInstrInfo::insertBranch(), isTiedToNotUndef(), llvm::TargetInstrInfo::lowerCopy(), mergeOperations(), preserveCondRegFlags(), print(), readsReg(), llvm::MachineInstr::readsWritesVirtualRegister(), swapRegAndNonRegOperand(), UpdateCPSRDef(), and UpdateCPSRUse().

isUse()

bool llvm::MachineOperand::isUse ( ) const

inline

Definition at line 379 of file MachineOperand.h.

References assert(), and isReg().

Referenced by llvm::MachineInstr::addOperand(), llvm::ScheduleDAGInstrs::addPhysRegDeps(), llvm::MachineInstr::addRegisterKilled(), llvm::HexagonSubtarget::adjustSchedDependency(), llvm::MachineInstr::allDefsAreDead(), llvm::MachineInstr::allImplicitDefsAreDead(), llvm::CriticalAntiDepBreaker::BreakAntiDependencies(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::MachineInstr::clearKillInfo(), llvm::MachineInstr::clearRegisterKills(), llvm::constrainOperandRegClass(), llvm::constrainSelectedInstRegOperands(), copyRegOperand(), llvm::MachineInstr::findRegisterUseOperandIdx(), llvm::MachineInstr::findTiedOperandIdx(), llvm::SwingSchedulerDAG::fixupRegisterOverlaps(), getCallTargetRegOpnd(), getInstReadLaneMask(), hasRegisterDependency(), llvm::MachineInstr::hasRegisterImplicitUseOperand(), llvm::MachineInstr::isRegTiedToDefOperand(), isRenamable(), isTwoAddrUse(), isValidRegUse(), producesFalseLanesZero(), readsReg(), llvm::MachineInstr::readsWritesVirtualRegister(), llvm::MachineInstr::tieOperands(), UpdateCPSRDef(), llvm::SIInstrInfo::usesConstantBus(), and llvm::SIInstrInfo::verifyInstruction().

isValidExcessOperand()

bool llvm::MachineOperand::isValidExcessOperand ( ) const

inline

Return true if this operand can validly be appended to an arbitrary operand list.

i.e. this behaves like an implicit operand.

Definition at line 474 of file MachineOperand.h.

References isImplicit(), isMCSymbol(), isMetadata(), isReg(), and isRegMask().

print() [1/3]

void MachineOperand::print	(	raw_ostream &	os,
		const TargetRegisterInfo *	TRI = nullptr,
		const TargetIntrinsicInfo *	IntrinsicInfo = nullptr
	)		const

Print the MachineOperand to os.

Providing a valid TRI and IntrinsicInfo results in a more target-specific printing. If TRI and IntrinsicInfo are null, the function will try to pick it up from the parent.

Definition at line 779 of file MachineOperand.cpp.

References OS, print(), and TRI.

Referenced by llvm::operator<<(), print(), and llvm::MachineInstr::print().

print() [2/3]

void MachineOperand::print	(	raw_ostream &	os,
		LLT	TypeToPrint,
		const TargetRegisterInfo *	TRI = nullptr,
		const TargetIntrinsicInfo *	IntrinsicInfo = nullptr
	)		const

Same as print(os, TRI, IntrinsicInfo), but allows to specify the low-level type to be printed the same way the full version of print(...) does it.

Definition at line 784 of file MachineOperand.cpp.

References OS, print(), TRI, and tryToGetTargetInfo().

print() [3/3]

void MachineOperand::print	(	raw_ostream &	os,
		ModuleSlotTracker &	MST,
		LLT	TypeToPrint,
		std::optional< unsigned >	OpIdx,
		bool	PrintDef,
		bool	IsStandalone,
		bool	ShouldPrintRegisterTies,
		unsigned	TiedOperandIdx,
		const TargetRegisterInfo *	TRI,
		const TargetIntrinsicInfo *	IntrinsicInfo
	)		const

More complex way of printing a MachineOperand.

Parameters

TypeToPrint	specifies the generic type to be printed on uses and defs. It can be determined using MachineInstr::getTypeToPrint.
OpIdx	- specifies the index of the operand in machine instruction. This will be used by target dependent MIR formatter. Could be std::nullopt if the index is unknown, e.g. called by dump().
PrintDef	- whether we want to print def on an operand which isDef. Sometimes, if the operand is printed before '=', we don't print def.
IsStandalone	- whether we want a verbose output of the MO. This prints extra information that can be easily inferred when printing the whole function, but not when printing only a fragment of it.
ShouldPrintRegisterTies	- whether we want to print register ties. Sometimes they are easily determined by the instruction's descriptor (MachineInstr::hasComplexRegiterTies can determine if it's needed).
TiedOperandIdx	- if we need to print register ties this needs to provide the index of the tied register. If not, it will be ignored.
TRI	- provide more target-specific information to the printer. Unlike the previous function, this one will not try and get the information from it's parent.
IntrinsicInfo	- same as TRI.

Definition at line 795 of file MachineOperand.cpp.

References assert(), llvm::Intrinsic::getBaseName(), getBlockAddress(), getCFIIndex(), getCImm(), getFPImm(), llvm::BlockAddress::getFunction(), getGlobal(), getImm(), getIndex(), getInstrRefInstrIndex(), getInstrRefOpIndex(), getIntrinsicID(), getMBB(), getMCSymbol(), getMetadata(), getMFIfAvailable(), llvm::TargetIntrinsicInfo::getName(), getOffset(), getParent(), getPredicate(), getReg(), getRegLiveOut(), getRegMask(), getShuffleMask(), getSubReg(), getSymbolName(), getTargetIndexName(), getType(), isDead(), isDef(), isEarlyClobber(), isImplicit(), isInternalRead(), llvm::CmpInst::isIntPredicate(), isKill(), llvm::Register::isPhysical(), isRenamable(), isTied(), isUndef(), llvm::LLT::isValid(), MO_BlockAddress, MO_CFIIndex, MO_CImmediate, MO_ConstantPoolIndex, MO_DbgInstrRef, MO_ExternalSymbol, MO_FPImmediate, MO_FrameIndex, MO_GlobalAddress, MO_Immediate, MO_IntrinsicID, MO_JumpTableIndex, MO_MachineBasicBlock, MO_MCSymbol, MO_Metadata, MO_Predicate, MO_Register, MO_RegisterLiveOut, MO_RegisterMask, MO_ShuffleMask, MO_TargetIndex, MRI, Name, OS, llvm::Value::printAsOperand(), llvm::Metadata::printAsOperand(), printCFI(), printFrameIndex(), llvm::MIRFormatter::printImm(), printIRBlockReference(), llvm::printJumpTableEntryReference(), llvm::printLLVMNameWithoutPrefix(), llvm::printMBBReference(), printOperandOffset(), llvm::printReg(), llvm::printRegClassOrBank(), PrintRegMaskNumRegs, printSymbol(), printTargetFlags(), SubReg, TII, and TRI.

printIRSlotNumber()

void MachineOperand::printIRSlotNumber ( raw_ostream &  OS, int  Slot  )

static

Print an IRSlotNumber.

Definition at line 657 of file MachineOperand.cpp.

References OS.

Referenced by printIRBlockReference(), and llvm::MIRFormatter::printIRValue().

printOperandOffset()

void MachineOperand::printOperandOffset ( raw_ostream &  OS, int64_t  Offset  )

static

Print the offset with explicit +/- signs.

Definition at line 647 of file MachineOperand.cpp.

References llvm::Offset, and OS.

Referenced by print(), and llvm::MachineMemOperand::print().

printStackObjectReference()

void MachineOperand::printStackObjectReference ( raw_ostream &  OS, unsigned  FrameIndex, bool  IsFixed, StringRef  Name  )

static

Print a stack object reference.

Definition at line 634 of file MachineOperand.cpp.

References Name, and OS.

Referenced by printFrameIndex(), and llvm::MIPrinter::printStackObjectReference().

printSubRegIdx()

void MachineOperand::printSubRegIdx ( raw_ostream &  OS, uint64_t  Index, const TargetRegisterInfo *  TRI  )

static

Print a subreg index operand.

MO_Immediate operands can also be subreg idices. If it's the case, the subreg index name will be printed. MachineInstr::isOperandSubregIdx can be called to check this.

Definition at line 569 of file MachineOperand.cpp.

References OS, and TRI.

Referenced by llvm::MIPrinter::print(), and llvm::MachineInstr::print().

printSymbol()

void MachineOperand::printSymbol ( raw_ostream &  OS, MCSymbol &  Sym  )

static

Print a MCSymbol as an operand.

Definition at line 630 of file MachineOperand.cpp.

References OS, and Sym.

Referenced by llvm::MIPrinter::print(), llvm::MachineInstr::print(), print(), and printCFI().

printTargetFlags()

void MachineOperand::printTargetFlags ( raw_ostream &  OS, const MachineOperand &  Op  )

static

Print operand target flags.

Definition at line 578 of file MachineOperand.cpp.

References assert(), llvm::HexagonInstrInfo::decomposeMachineOperandsTargetFlags(), llvm::TargetSubtargetInfo::getInstrInfo(), getMFIfAvailable(), llvm::HexagonInstrInfo::getSerializableBitmaskMachineOperandTargetFlags(), llvm::MachineFunction::getSubtarget(), getTargetFlagName(), Name, OS, and TII.

Referenced by llvm::MIPrinter::print(), and print().

readsReg()

bool llvm::MachineOperand::readsReg ( ) const

inline

readsReg - Returns true if this operand reads the previous value of its register.

A use operand with the <undef> flag set doesn't read its register. A sub-register def implicitly reads the other parts of the register being redefined unless the <undef> flag is set.

This refers to reading the register value from before the current instruction or bundle. Internal bundle reads are not included.

Definition at line 467 of file MachineOperand.h.

References assert(), getSubReg(), isInternalRead(), isReg(), isUndef(), and isUse().

Referenced by llvm::AnalyzeVirtRegInBundle(), llvm::ScheduleDAGInstrs::buildSchedGraph(), findUseIdx(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), and llvm::X86InstrInfo::getPartialRegUpdateClearance().

setCImm()

void llvm::MachineOperand::setCImm ( const ConstantInt *  CI )

inline

Definition at line 689 of file MachineOperand.h.

References assert(), and isCImm().

Referenced by llvm::LegalizerHelper::widenScalar().

setFPImm()

void llvm::MachineOperand::setFPImm ( const ConstantFP *  CFP )

inline

Definition at line 694 of file MachineOperand.h.

References assert(), and isFPImm().

setImm()

void llvm::MachineOperand::setImm ( int64_t  immVal )

inline

Definition at line 684 of file MachineOperand.h.

References assert(), and isImm().

Referenced by llvm::R600InstrInfo::addFlag(), llvm::SwingSchedulerDAG::applyInstrChange(), llvm::R600InstrInfo::buildSlotOfVectorInstruction(), llvm::R600InstrInfo::clearFlag(), llvm::X86InstrInfo::commuteInstructionImpl(), llvm::ARMBaseInstrInfo::commuteInstructionImpl(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), fixupCalleeSaveRestoreStackOffset(), llvm::SwingSchedulerDAG::fixupRegisterOverlaps(), fixupSEHOpcode(), llvm::PPCInstrInfo::foldFrameOffset(), foldInlineAsmMemOperand(), llvm::R600InstrInfo::insertBranch(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::TargetInstrInfo::PredicateInstruction(), llvm::ARMBaseInstrInfo::PredicateInstruction(), llvm::SystemZInstrInfo::prepareCompareSwapOperands(), llvm::recomputeVPTBlockMask(), llvm::SIInstrInfo::reMaterialize(), llvm::SIRegisterInfo::resolveFrameIndex(), llvm::R600InstrInfo::reverseBranchCondition(), llvm::HexagonInstrInfo::setBundleNoShuf(), llvm::SIInstrInfo::swapSourceModifiers(), updateOperandIfDifferent(), and updateOperands().

setImplicit()

void llvm::MachineOperand::setImplicit ( bool  Val = true )

inline

Definition at line 514 of file MachineOperand.h.

References assert(), and isReg().

Referenced by llvm::X86InstrInfo::classifyLEAReg(), llvm::SIInstrInfo::insertVectorSelect(), makeImplicit(), llvm::LanaiInstrInfo::optimizeSelect(), and llvm::ARMBaseInstrInfo::optimizeSelect().

setIndex()

void llvm::MachineOperand::setIndex ( int  Idx )

inline

Definition at line 707 of file MachineOperand.h.

References assert(), Idx, isCPI(), isFI(), isJTI(), and isTargetIndex().

Referenced by ChangeToFrameIndex(), and ChangeToTargetIndex().

setInstrRefInstrIndex()

void llvm::MachineOperand::setInstrRefInstrIndex ( unsigned  InstrIdx )

inline

Definition at line 718 of file MachineOperand.h.

References assert(), and isDbgInstrRef().

Referenced by ChangeToDbgInstrRef().

setInstrRefOpIndex()

void llvm::MachineOperand::setInstrRefOpIndex ( unsigned  OpIdx )

inline

Definition at line 722 of file MachineOperand.h.

References assert(), and isDbgInstrRef().

Referenced by ChangeToDbgInstrRef().

setIntrinsicID()

void llvm::MachineOperand::setIntrinsicID ( Intrinsic::ID  IID )

inline

Definition at line 741 of file MachineOperand.h.

References assert(), and isIntrinsicID().

setIsDead()

void llvm::MachineOperand::setIsDead ( bool  Val = true )

inline

Definition at line 525 of file MachineOperand.h.

References assert(), and isReg().

Referenced by llvm::MachineInstr::addRegisterDead(), buildScratchExecCopy(), llvm::MachineInstr::clearRegisterDeads(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), copyRegOperand(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::SIInstrInfo::insertScratchExecCopy(), maybeRewriteToDrop(), llvm::SIInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::SGPRSpillBuilder::readWriteTmpVGPR(), llvm::X86FrameLowering::restoreWin32EHStackPointers(), llvm::MachineInstr::setPhysRegsDeadExcept(), llvm::X86InstrInfo::setSpecialOperandAttr(), and transferDeadCC().

setIsDebug()

void llvm::MachineOperand::setIsDebug ( bool  Val = true )

inline

Definition at line 547 of file MachineOperand.h.

References assert(), and isReg().

Referenced by llvm::MachineInstr::addOperand().

setIsDef()

void MachineOperand::setIsDef

(

bool

Val = true

)

Change a def to a use, or a use to a def.

Definition at line 107 of file MachineOperand.cpp.

References assert(), getMFIfAvailable(), isDebug(), isReg(), and MRI.

Referenced by llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::RevertLoopDec(), and setIsUse().

setIsEarlyClobber()

void llvm::MachineOperand::setIsEarlyClobber ( bool  Val = true )

inline

Definition at line 542 of file MachineOperand.h.

References assert(), and isReg().

Referenced by llvm::MachineInstr::addOperand().

setIsInternalRead()

void llvm::MachineOperand::setIsInternalRead ( bool  Val = true )

inline

Definition at line 537 of file MachineOperand.h.

References assert(), and isReg().

Referenced by llvm::TargetInstrInfo::commuteInstructionImpl().

setIsKill()

void llvm::MachineOperand::setIsKill ( bool  Val = true )

inline

Definition at line 519 of file MachineOperand.h.

References assert(), isDebug(), and isReg().

Referenced by llvm::ScheduleDAGInstrs::addPhysRegDeps(), llvm::MachineInstr::addRegisterKilled(), clearKillFlags(), llvm::MachineInstr::clearKillInfo(), llvm::MachineInstr::clearRegisterKills(), llvm::PPCInstrInfo::combineRLWINM(), llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::R600InstrInfo::copyPhysReg(), copyRegOperand(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::SIInstrInfo::foldImmediate(), indirectCopyToAGPR(), llvm::SIInstrInfo::insertBranch(), insertDivByZeroTrap(), llvm::X86InstrInfo::loadStoreTileReg(), MoveVPNOTBeforeFirstUser(), llvm::AArch64InstrInfo::optimizeCondBranch(), preserveCondRegFlags(), llvm::LiveVariables::removeVirtualRegistersKilled(), llvm::X86InstrInfo::unfoldMemoryOperand(), and updateKillStatus().

setIsRenamable()

void MachineOperand::setIsRenamable

(

bool

Val = true

)

Definition at line 142 of file MachineOperand.cpp.

References assert(), getReg(), and isReg().

Referenced by llvm::TargetInstrInfo::commuteInstructionImpl().

setIsUndef()

void llvm::MachineOperand::setIsUndef ( bool  Val = true )

inline

Definition at line 530 of file MachineOperand.h.

References assert(), and isReg().

Referenced by llvm::ScheduleDAGInstrs::addVRegDefDeps(), llvm::TargetInstrInfo::commuteInstructionImpl(), copyRegOperand(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::X86InstrInfo::expandPostRAPseudo(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::SIInstrInfo::insertBranch(), mergeOperations(), preserveCondRegFlags(), llvm::MachineInstr::setRegisterDefReadUndef(), and substPhysReg().

setIsUse()

void llvm::MachineOperand::setIsUse ( bool  Val = true )

inline

Definition at line 509 of file MachineOperand.h.

References setIsDef().

setMBB()

void llvm::MachineOperand::setMBB ( MachineBasicBlock *  MBB )

inline

Definition at line 727 of file MachineOperand.h.

References assert(), isMBB(), and MBB.

Referenced by llvm::CombinerHelper::applyOptBrCondByInvertingCond(), llvm::LoongArchInstrInfo::insertIndirectBranch(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), llvm::PeelingModuloScheduleExpander::moveStageBetweenBlocks(), llvm::TargetInstrInfo::PredicateInstruction(), llvm::MachineBasicBlock::replacePhiUsesWith(), splitEdge(), and updatePHIs().

setMetadata()

void llvm::MachineOperand::setMetadata ( const MDNode *  MD )

inline

Definition at line 713 of file MachineOperand.h.

References assert(), and isMetadata().

Referenced by llvm::salvageDebugInfoForDbgValue(), and llvm::updateDbgValueForSpill().

setOffset()

void llvm::MachineOperand::setOffset ( int64_t  Offset )

inline

Definition at line 699 of file MachineOperand.h.

References assert(), isBlockAddress(), isCPI(), isGlobal(), isMCSymbol(), isSymbol(), isTargetIndex(), and llvm::Offset.

Referenced by ChangeToBA(), ChangeToES(), ChangeToGA(), ChangeToTargetIndex(), and llvm::SIInstrInfo::expandPostRAPseudo().

setPredicate()

void llvm::MachineOperand::setPredicate ( unsigned  Predicate )

inline

Definition at line 746 of file MachineOperand.h.

References assert(), and isPredicate().

Referenced by llvm::CombinerHelper::applyNotCmp().

setReg()

void MachineOperand::setReg

(

Register

Reg

)

Change the register this operand corresponds to.

Definition at line 61 of file MachineOperand.cpp.

References getMFIfAvailable(), getReg(), and MRI.

Referenced by llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::CombinerHelper::applyCombineExtendingLoads(), llvm::RegisterBankInfo::applyDefaultMapping(), llvm::SwingSchedulerDAG::applyInstrChange(), llvm::CombinerHelper::applyOptBrCondByInvertingCond(), llvm::LegalizerHelper::bitcastDst(), llvm::R600InstrInfo::buildSlotOfVectorInstruction(), castBufferRsrcArgToV4I32(), castBufferRsrcFromV4I32(), cloneInstr(), llvm::WebAssemblyDebugValueManager::cloneSink(), llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::constrainOperandRegClass(), copyRegOperand(), copySubReg(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::M68kInstrInfo::ExpandCCR(), llvm::M68kInstrInfo::ExpandMOVI(), ExpandMOVImmSExti8(), llvm::M68kInstrInfo::ExpandMOVSZX_RM(), llvm::M68kInstrInfo::ExpandMOVX_RR(), expandNOVLXLoad(), expandNOVLXStore(), llvm::X86InstrInfo::expandPostRAPseudo(), llvm::SwingSchedulerDAG::fixupRegisterOverlaps(), llvm::SIInstrInfo::foldImmediate(), llvm::X86InstrInfo::foldMemoryOperandImpl(), genAlternativeDpCodeSequence(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsFLAT(), llvm::SIInstrInfo::legalizeOperandsSMRD(), llvm::X86InstrInfo::loadStoreTileReg(), llvm::X86CallLowering::lowerCall(), llvm::AMDGPUCallLowering::lowerTailCall(), maybeRewriteToDrop(), llvm::LegalizerHelper::moreElementsVector(), llvm::LegalizerHelper::moreElementsVectorDst(), llvm::LegalizerHelper::moreElementsVectorSrc(), llvm::PeelingModuloScheduleExpander::moveStageBetweenBlocks(), llvm::SIInstrInfo::moveToVALUImpl(), llvm::LegalizerHelper::narrowScalar(), llvm::LegalizerHelper::narrowScalarDst(), llvm::LegalizerHelper::narrowScalarSrc(), llvm::PeelSingleBlockLoop(), llvm::TargetInstrInfo::PredicateInstruction(), llvm::R600InstrInfo::PredicateInstruction(), llvm::processInstr(), reinsertVectorIndexAdd(), llvm::SIInstrInfo::reMaterialize(), llvm::CombinerHelper::replaceRegOpWith(), llvm::R600InstrInfo::reverseBranchCondition(), llvm::salvageDebugInfoForDbgValue(), selectCopy(), substituteSimpleCopyRegs(), substPhysReg(), substVirtReg(), llvm::WebAssemblyDebugValueManager::updateReg(), llvm::LegalizerHelper::widenScalarDst(), and llvm::LegalizerHelper::widenScalarSrc().

setRegMask()

void llvm::MachineOperand::setRegMask ( const uint32_t *  RegMaskPtr )

inline

Sets value of register mask operand referencing Mask.

The operand does not take ownership of the memory referenced by Mask, it must remain valid for the lifetime of the operand. See CreateRegMask(). Any physreg with a 0 bit in the mask is clobbered by the instruction.

Definition at line 736 of file MachineOperand.h.

References assert(), and isRegMask().

setSubReg()

void llvm::MachineOperand::setSubReg ( unsigned  subReg )

inline

Definition at line 490 of file MachineOperand.h.

References assert(), and isReg().

Referenced by llvm::TargetInstrInfo::commuteInstructionImpl(), copyRegOperand(), llvm::SIInstrInfo::foldImmediate(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), INITIALIZE_PASS(), insertDivByZeroTrap(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::SIInstrInfo::reMaterialize(), substPhysReg(), substVirtReg(), and swapRegAndNonRegOperand().

setTargetFlags()

void llvm::MachineOperand::setTargetFlags ( unsigned  F )

inline

Definition at line 229 of file MachineOperand.h.

References assert(), F, and isReg().

Referenced by ChangeToBA(), ChangeToDbgInstrRef(), ChangeToES(), ChangeToFPImmediate(), ChangeToFrameIndex(), ChangeToGA(), ChangeToImmediate(), ChangeToMCSymbol(), ChangeToTargetIndex(), llvm::MipsCallLowering::lowerCall(), and swapRegAndNonRegOperand().

substPhysReg()

void MachineOperand::substPhysReg	(	MCRegister	Reg,
		const TargetRegisterInfo &	TRI
	)

substPhysReg - Substitute the current register with the physical register Reg, taking any existing SubReg into account.

For instance, substPhysReg(eax) will change reg1024:sub_8bit to al.

Definition at line 93 of file MachineOperand.cpp.

References assert(), getSubReg(), isDef(), llvm::Register::isPhysicalRegister(), setIsUndef(), setReg(), setSubReg(), and TRI.

Referenced by llvm::MachineInstr::substituteRegister().

substVirtReg()

void MachineOperand::substVirtReg	(	Register	Reg,
		unsigned	SubIdx,
		const TargetRegisterInfo &	TRI
	)

substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.

Take any existing SubReg index into account, using TargetRegisterInfo to compose the subreg indices if necessary. Reg must be a virtual register, SubIdx can be 0.

Definition at line 83 of file MachineOperand.cpp.

References assert(), getSubReg(), setReg(), setSubReg(), and TRI.

Referenced by llvm::MachineInstr::substituteRegister().

Friends And Related Function Documentation

DenseMapInfo< MachineOperand >

friend struct DenseMapInfo< MachineOperand >

friend

Definition at line 996 of file MachineOperand.h.

hash_value

hash_code hash_value ( const MachineOperand &  MO )

friend

MachineOperand hash_value overload.

Note that this includes the same information in the hash that isIdenticalTo uses for comparison. It is thus suited for use in hash tables which use that function for equality comparisons only. This must stay exactly in sync with isIdenticalTo above.

MachineInstr

friend class MachineInstr

friend

Definition at line 990 of file MachineOperand.h.

MachineRegisterInfo

friend class MachineRegisterInfo

friend

Definition at line 991 of file MachineOperand.h.

Member Data Documentation

OffsetLo

unsigned llvm::MachineOperand::OffsetLo

Definition at line 160 of file MachineOperand.h.

RegNo

unsigned llvm::MachineOperand::RegNo

Definition at line 159 of file MachineOperand.h.

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The documentation for this class was generated from the following files:

• include/llvm/CodeGen/MachineOperand.h
• lib/CodeGen/MachineOperand.cpp