LLVM  10.0.0svn
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llvm::MachineOperand Class Reference

MachineOperand class - Representation of each machine instruction operand. More...

#include "llvm/CodeGen/MachineOperand.h"

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Public Types

enum  MachineOperandType : unsigned char {
  MO_Register, MO_Immediate, MO_CImmediate, MO_FPImmediate,
  MO_MachineBasicBlock, MO_FrameIndex, MO_ConstantPoolIndex, MO_TargetIndex,
  MO_JumpTableIndex, MO_ExternalSymbol, MO_GlobalAddress, MO_BlockAddress,
  MO_RegisterMask, MO_RegisterLiveOut, MO_Metadata, MO_MCSymbol,
  MO_CFIIndex, MO_IntrinsicID, MO_Predicate, MO_ShuffleMask,
  MO_Last = MO_ShuffleMask
}
 

Public Member Functions

MachineOperandType getType () const
 getType - Returns the MachineOperandType for this operand. More...
 
unsigned getTargetFlags () const
 
void setTargetFlags (unsigned F)
 
void addTargetFlag (unsigned F)
 
MachineInstrgetParent ()
 getParent - Return the instruction that this operand belongs to. More...
 
const MachineInstrgetParent () const
 
void clearParent ()
 clearParent - Reset the parent pointer. More...
 
void print (raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
 Print the MachineOperand to os. More...
 
void print (raw_ostream &os, ModuleSlotTracker &MST, LLT TypeToPrint, bool PrintDef, bool IsStandalone, bool ShouldPrintRegisterTies, unsigned TiedOperandIdx, const TargetRegisterInfo *TRI, const TargetIntrinsicInfo *IntrinsicInfo) const
 More complex way of printing a MachineOperand. More...
 
void print (raw_ostream &os, LLT TypeToPrint, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
 Same as print(os, TRI, IntrinsicInfo), but allows to specify the low-level type to be printed the same way the full version of print(...) does it. More...
 
void dump () const
 
bool isReg () const
 isReg - Tests if this is a MO_Register operand. More...
 
bool isImm () const
 isImm - Tests if this is a MO_Immediate operand. More...
 
bool isCImm () const
 isCImm - Test if this is a MO_CImmediate operand. More...
 
bool isFPImm () const
 isFPImm - Tests if this is a MO_FPImmediate operand. More...
 
bool isMBB () const
 isMBB - Tests if this is a MO_MachineBasicBlock operand. More...
 
bool isFI () const
 isFI - Tests if this is a MO_FrameIndex operand. More...
 
bool isCPI () const
 isCPI - Tests if this is a MO_ConstantPoolIndex operand. More...
 
bool isTargetIndex () const
 isTargetIndex - Tests if this is a MO_TargetIndex operand. More...
 
bool isJTI () const
 isJTI - Tests if this is a MO_JumpTableIndex operand. More...
 
bool isGlobal () const
 isGlobal - Tests if this is a MO_GlobalAddress operand. More...
 
bool isSymbol () const
 isSymbol - Tests if this is a MO_ExternalSymbol operand. More...
 
bool isBlockAddress () const
 isBlockAddress - Tests if this is a MO_BlockAddress operand. More...
 
bool isRegMask () const
 isRegMask - Tests if this is a MO_RegisterMask operand. More...
 
bool isRegLiveOut () const
 isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand. More...
 
bool isMetadata () const
 isMetadata - Tests if this is a MO_Metadata operand. More...
 
bool isMCSymbol () const
 
bool isCFIIndex () const
 
bool isIntrinsicID () const
 
bool isPredicate () const
 
bool isShuffleMask () const
 
Register getReg () const
 getReg - Returns the register number. More...
 
unsigned getSubReg () const
 
bool isUse () const
 
bool isDef () const
 
bool isImplicit () const
 
bool isDead () const
 
bool isKill () const
 
bool isUndef () const
 
bool isRenamable () const
 isRenamable - Returns true if this register may be renamed, i.e. More...
 
bool isInternalRead () const
 
bool isEarlyClobber () const
 
bool isTied () const
 
bool isDebug () const
 
bool readsReg () const
 readsReg - Returns true if this operand reads the previous value of its register. More...
 
void setReg (Register Reg)
 Change the register this operand corresponds to. More...
 
void setSubReg (unsigned subReg)
 
void substVirtReg (Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
 substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg. More...
 
void substPhysReg (MCRegister Reg, const TargetRegisterInfo &)
 substPhysReg - Substitute the current register with the physical register Reg, taking any existing SubReg into account. More...
 
void setIsUse (bool Val=true)
 
void setIsDef (bool Val=true)
 Change a def to a use, or a use to a def. More...
 
void setImplicit (bool Val=true)
 
void setIsKill (bool Val=true)
 
void setIsDead (bool Val=true)
 
void setIsUndef (bool Val=true)
 
void setIsRenamable (bool Val=true)
 
void setIsInternalRead (bool Val=true)
 
void setIsEarlyClobber (bool Val=true)
 
void setIsDebug (bool Val=true)
 
int64_t getImm () const
 
const ConstantIntgetCImm () const
 
const ConstantFPgetFPImm () const
 
MachineBasicBlockgetMBB () const
 
int getIndex () const
 
const GlobalValuegetGlobal () const
 
const BlockAddressgetBlockAddress () const
 
MCSymbolgetMCSymbol () const
 
unsigned getCFIIndex () const
 
Intrinsic::ID getIntrinsicID () const
 
unsigned getPredicate () const
 
const ConstantgetShuffleMask () const
 
int64_t getOffset () const
 Return the offset from the symbol in this operand. More...
 
const chargetSymbolName () const
 
bool clobbersPhysReg (unsigned PhysReg) const
 clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg. More...
 
const uint32_tgetRegMask () const
 getRegMask - Returns a bit mask of registers preserved by this RegMask operand. More...
 
const uint32_tgetRegLiveOut () const
 getRegLiveOut - Returns a bit mask of live-out registers. More...
 
const MDNodegetMetadata () const
 
void setImm (int64_t immVal)
 
void setCImm (const ConstantInt *CI)
 
void setFPImm (const ConstantFP *CFP)
 
void setOffset (int64_t Offset)
 
void setIndex (int Idx)
 
void setMetadata (const MDNode *MD)
 
void setMBB (MachineBasicBlock *MBB)
 
void setRegMask (const uint32_t *RegMaskPtr)
 Sets value of register mask operand referencing Mask. More...
 
void setPredicate (unsigned Predicate)
 
bool isIdenticalTo (const MachineOperand &Other) const
 Returns true if this operand is identical to the specified operand except for liveness related flags (isKill, isUndef and isDead). More...
 
void ChangeToImmediate (int64_t ImmVal)
 ChangeToImmediate - Replace this operand with a new immediate operand of the specified value. More...
 
void ChangeToFPImmediate (const ConstantFP *FPImm)
 ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value. More...
 
void ChangeToES (const char *SymName, unsigned TargetFlags=0)
 ChangeToES - Replace this operand with a new external symbol operand. More...
 
void ChangeToGA (const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
 ChangeToGA - Replace this operand with a new global address operand. More...
 
void ChangeToMCSymbol (MCSymbol *Sym)
 ChangeToMCSymbol - Replace this operand with a new MC symbol operand. More...
 
void ChangeToFrameIndex (int Idx)
 Replace this operand with a frame index. More...
 
void ChangeToTargetIndex (unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
 Replace this operand with a target index. More...
 
void ChangeToRegister (Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
 ChangeToRegister - Replace this operand with a new register operand of the specified value. More...
 

Static Public Member Functions

static void printSubRegIdx (raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
 Print a subreg index operand. More...
 
static void printTargetFlags (raw_ostream &OS, const MachineOperand &Op)
 Print operand target flags. More...
 
static void printSymbol (raw_ostream &OS, MCSymbol &Sym)
 Print a MCSymbol as an operand. More...
 
static void printStackObjectReference (raw_ostream &OS, unsigned FrameIndex, bool IsFixed, StringRef Name)
 Print a stack object reference. More...
 
static void printOperandOffset (raw_ostream &OS, int64_t Offset)
 Print the offset with explicit +/- signs. More...
 
static void printIRSlotNumber (raw_ostream &OS, int Slot)
 Print an IRSlotNumber. More...
 
static bool clobbersPhysReg (const uint32_t *RegMask, unsigned PhysReg)
 clobbersPhysReg - Returns true if this RegMask clobbers PhysReg. More...
 
static unsigned getRegMaskSize (unsigned NumRegs)
 Returns number of elements needed for a regmask array. More...
 
static MachineOperand CreateImm (int64_t Val)
 
static MachineOperand CreateCImm (const ConstantInt *CI)
 
static MachineOperand CreateFPImm (const ConstantFP *CFP)
 
static MachineOperand CreateReg (Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
 
static MachineOperand CreateMBB (MachineBasicBlock *MBB, unsigned TargetFlags=0)
 
static MachineOperand CreateFI (int Idx)
 
static MachineOperand CreateCPI (unsigned Idx, int Offset, unsigned TargetFlags=0)
 
static MachineOperand CreateTargetIndex (unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
 
static MachineOperand CreateJTI (unsigned Idx, unsigned TargetFlags=0)
 
static MachineOperand CreateGA (const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
 
static MachineOperand CreateES (const char *SymName, unsigned TargetFlags=0)
 
static MachineOperand CreateBA (const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
 
static MachineOperand CreateRegMask (const uint32_t *Mask)
 CreateRegMask - Creates a register mask operand referencing Mask. More...
 
static MachineOperand CreateRegLiveOut (const uint32_t *Mask)
 
static MachineOperand CreateMetadata (const MDNode *Meta)
 
static MachineOperand CreateMCSymbol (MCSymbol *Sym, unsigned TargetFlags=0)
 
static MachineOperand CreateCFIIndex (unsigned CFIIndex)
 
static MachineOperand CreateIntrinsicID (Intrinsic::ID ID)
 
static MachineOperand CreatePredicate (unsigned Pred)
 
static MachineOperand CreateShuffleMask (const Constant *C)
 

Friends

class MachineInstr
 
class MachineRegisterInfo
 
struct DenseMapInfo< MachineOperand >
 
hash_code hash_value (const MachineOperand &MO)
 MachineOperand hash_value overload. More...
 

Detailed Description

MachineOperand class - Representation of each machine instruction operand.

This class isn't a POD type because it has a private constructor, but its destructor must be trivial. Functions like MachineInstr::addOperand(), MachineRegisterInfo::moveOperands(), and MF::DeleteMachineInstr() depend on not having to call the MachineOperand destructor.

Definition at line 50 of file MachineOperand.h.

Member Enumeration Documentation

◆ MachineOperandType

Enumerator
MO_Register 

Register operand.

MO_Immediate 

Immediate operand.

MO_CImmediate 

Immediate >64bit operand.

MO_FPImmediate 

Floating-point immediate operand.

MO_MachineBasicBlock 

MachineBasicBlock reference.

MO_FrameIndex 

Abstract Stack Frame Index.

MO_ConstantPoolIndex 

Address of indexed Constant in Constant Pool.

MO_TargetIndex 

Target-dependent index+offset operand.

MO_JumpTableIndex 

Address of indexed Jump Table for switch.

MO_ExternalSymbol 

Name of external global symbol.

MO_GlobalAddress 

Address of a global value.

MO_BlockAddress 

Address of a basic block.

MO_RegisterMask 

Mask of preserved registers.

MO_RegisterLiveOut 

Mask of live-out registers.

MO_Metadata 

Metadata reference (for debug info)

MO_MCSymbol 

MCSymbol reference (for debug/eh info)

MO_CFIIndex 

MCCFIInstruction index.

MO_IntrinsicID 

Intrinsic ID for ISel.

MO_Predicate 

Generic predicate for ISel.

MO_ShuffleMask 

Other IR Constant for ISel (shuffle masks)

MO_Last 

Definition at line 52 of file MachineOperand.h.

Member Function Documentation

◆ addTargetFlag()

void llvm::MachineOperand::addTargetFlag ( unsigned  F)
inline

Definition at line 226 of file MachineOperand.h.

References assert(), F(), and isReg().

Referenced by llvm::HexagonInstrInfo::immediateExtend().

◆ ChangeToES()

void MachineOperand::ChangeToES ( const char SymName,
unsigned  TargetFlags = 0 
)

ChangeToES - Replace this operand with a new external symbol operand.

Definition at line 171 of file MachineOperand.cpp.

References assert(), isReg(), isTied(), MO_ExternalSymbol, setOffset(), and setTargetFlags().

Referenced by getRetpolineSymbol(), and setPredicate().

◆ ChangeToFPImmediate()

void MachineOperand::ChangeToFPImmediate ( const ConstantFP FPImm)

ChangeToFPImmediate - Replace this operand with a new FP immediate operand of the specified value.

If an operand is known to be an FP immediate already, the setFPImm method should be used.

Definition at line 162 of file MachineOperand.cpp.

References assert(), isReg(), isTied(), and MO_FPImmediate.

Referenced by setPredicate().

◆ ChangeToFrameIndex()

void MachineOperand::ChangeToFrameIndex ( int  Idx)

◆ ChangeToGA()

void MachineOperand::ChangeToGA ( const GlobalValue GV,
int64_t  Offset,
unsigned  TargetFlags = 0 
)

ChangeToGA - Replace this operand with a new global address operand.

Definition at line 184 of file MachineOperand.cpp.

References assert(), GV, isReg(), isTied(), MO_GlobalAddress, setOffset(), and setTargetFlags().

Referenced by setPredicate(), and updateOperand().

◆ ChangeToImmediate()

void MachineOperand::ChangeToImmediate ( int64_t  ImmVal)

ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.

If an operand is known to be an immediate already, the setImm method should be used.

Definition at line 153 of file MachineOperand.cpp.

References assert(), ImmVal, isReg(), isTied(), and MO_Immediate.

Referenced by changeFCMPPredToAArch64CC(), llvm::BPFRegisterInfo::eliminateFrameIndex(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::RISCVRegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::AVRRegisterInfo::eliminateFrameIndex(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::ARCRegisterInfo::eliminateFrameIndex(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::NVPTXRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::AArch64RegisterInfo::eliminateFrameIndex(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::X86RegisterInfo::eliminateFrameIndex(), llvm::SystemZInstrInfo::FoldImmediate(), llvm::ARMBaseInstrInfo::FoldImmediate(), llvm::SIInstrInfo::FoldImmediate(), llvm::X86InstrInfo::foldMemoryOperandImpl(), getFPTrueImmVal(), getLeaOP(), getLoadStoreOffsetAlign(), hoistAndMergeSGPRInits(), INITIALIZE_PASS(), llvm::Mips16RegisterInfo::intRegClass(), llvm::SIInstrInfo::legalizeOperandsVOP2(), replaceFI(), llvm::PPCInstrInfo::replaceInstrOperandWithImm(), llvm::PPCRegisterInfo::resolveFrameIndex(), llvm::rewriteAArch64FrameIndex(), llvm::rewriteARMFrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), llvm::rewriteT2FrameIndex(), llvm::setDirectAddressInInstr(), setPredicate(), shrinkScalarLogicOp(), swapRegAndNonRegOperand(), tryConstantFoldOp(), tryToFoldACImm(), llvm::updateDbgValueForSpill(), and updateOperand().

◆ ChangeToMCSymbol()

void MachineOperand::ChangeToMCSymbol ( MCSymbol Sym)

ChangeToMCSymbol - Replace this operand with a new MC symbol operand.

Definition at line 197 of file MachineOperand.cpp.

References assert(), isReg(), isTied(), MO_MCSymbol, and Sym.

Referenced by setPredicate().

◆ ChangeToRegister()

void MachineOperand::ChangeToRegister ( Register  Reg,
bool  isDef,
bool  isImp = false,
bool  isKill = false,
bool  isDead = false,
bool  isUndef = false,
bool  isDebug = false 
)

ChangeToRegister - Replace this operand with a new register operand of the specified value.

If an operand is known to be an register already, the setReg method should be used.

Definition at line 233 of file MachineOperand.cpp.

References llvm::MachineRegisterInfo::addRegOperandToUseList(), assert(), getMFIfAvailable(), isDead(), isDebug(), isDef(), isReg(), isUndef(), MO_Register, Reg, and llvm::MachineRegisterInfo::removeRegOperandFromUseList().

Referenced by AssignProtectedObjSet(), changeFCMPPredToAArch64CC(), llvm::BPFRegisterInfo::eliminateFrameIndex(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::RISCVRegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::AVRRegisterInfo::eliminateFrameIndex(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::ARCRegisterInfo::eliminateFrameIndex(), llvm::NVPTXRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::AArch64RegisterInfo::eliminateFrameIndex(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::X86RegisterInfo::eliminateFrameIndex(), findSingleRegDef(), getLoadStoreOffsetAlign(), hoistAndMergeSGPRInits(), INITIALIZE_PASS(), llvm::Mips16RegisterInfo::intRegClass(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::legalizeOperandsVOP3(), llvm::SIInstrInfo::legalizeOpWithMove(), replaceFI(), llvm::SIRegisterInfo::resolveFrameIndex(), llvm::PPCRegisterInfo::resolveFrameIndex(), llvm::rewriteAArch64FrameIndex(), llvm::rewriteARMFrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), llvm::rewriteT2FrameIndex(), llvm::setDirectAddressInInstr(), setPredicate(), shrinkScalarLogicOp(), swapMIOperands(), swapRegAndNonRegOperand(), and llvm::X86InstrInfo::unfoldMemoryOperand().

◆ ChangeToTargetIndex()

void MachineOperand::ChangeToTargetIndex ( unsigned  Idx,
int64_t  Offset,
unsigned  TargetFlags = 0 
)

Replace this operand with a target index.

Definition at line 217 of file MachineOperand.cpp.

References assert(), isReg(), isTied(), MO_TargetIndex, setIndex(), setOffset(), and setTargetFlags().

Referenced by setPredicate().

◆ clearParent()

void llvm::MachineOperand::clearParent ( )
inline

clearParent - Reset the parent pointer.

The MachineOperand copy constructor also copies ParentMI, expecting the original to be deleted. If a MachineOperand is ever stored outside a MachineInstr, the parent pointer must be cleared.

Never call clearParent() on an operand in a MachineInstr.

Definition at line 246 of file MachineOperand.h.

References dump(), llvm::ISD::FrameIndex, Index, Name, print(), printIRSlotNumber(), printOperandOffset(), printStackObjectReference(), printSubRegIdx(), printSymbol(), printTargetFlags(), Sym, and TRI.

◆ clobbersPhysReg() [1/2]

static bool llvm::MachineOperand::clobbersPhysReg ( const uint32_t RegMask,
unsigned  PhysReg 
)
inlinestatic

◆ clobbersPhysReg() [2/2]

bool llvm::MachineOperand::clobbersPhysReg ( unsigned  PhysReg) const
inline

clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.

Definition at line 617 of file MachineOperand.h.

References clobbersPhysReg(), and getRegMask().

◆ CreateBA()

static MachineOperand llvm::MachineOperand::CreateBA ( const BlockAddress BA,
int64_t  Offset,
unsigned  TargetFlags = 0 
)
inlinestatic

◆ CreateCFIIndex()

static MachineOperand llvm::MachineOperand::CreateCFIIndex ( unsigned  CFIIndex)
inlinestatic

Definition at line 896 of file MachineOperand.h.

References CFIIndex, and MO_CFIIndex.

Referenced by llvm::MachineInstrBuilder::addCFIIndex(), and verifyAddrSpace().

◆ CreateCImm()

static MachineOperand llvm::MachineOperand::CreateCImm ( const ConstantInt CI)
inlinestatic

◆ CreateCPI()

static MachineOperand llvm::MachineOperand::CreateCPI ( unsigned  Idx,
int  Offset,
unsigned  TargetFlags = 0 
)
inlinestatic

◆ CreateES()

static MachineOperand llvm::MachineOperand::CreateES ( const char SymName,
unsigned  TargetFlags = 0 
)
inlinestatic

◆ CreateFI()

static MachineOperand llvm::MachineOperand::CreateFI ( int  Idx)
inlinestatic

◆ CreateFPImm()

static MachineOperand llvm::MachineOperand::CreateFPImm ( const ConstantFP CFP)
inlinestatic

◆ CreateGA()

static MachineOperand llvm::MachineOperand::CreateGA ( const GlobalValue GV,
int64_t  Offset,
unsigned  TargetFlags = 0 
)
inlinestatic

◆ CreateImm()

static MachineOperand llvm::MachineOperand::CreateImm ( int64_t  Val)
inlinestatic

◆ CreateIntrinsicID()

static MachineOperand llvm::MachineOperand::CreateIntrinsicID ( Intrinsic::ID  ID)
inlinestatic

Definition at line 902 of file MachineOperand.h.

References IntrinsicID, and MO_IntrinsicID.

Referenced by llvm::MachineInstrBuilder::addIntrinsicID(), and verifyAddrSpace().

◆ CreateJTI()

static MachineOperand llvm::MachineOperand::CreateJTI ( unsigned  Idx,
unsigned  TargetFlags = 0 
)
inlinestatic

◆ CreateMBB()

static MachineOperand llvm::MachineOperand::CreateMBB ( MachineBasicBlock MBB,
unsigned  TargetFlags = 0 
)
inlinestatic

◆ CreateMCSymbol()

static MachineOperand llvm::MachineOperand::CreateMCSymbol ( MCSymbol Sym,
unsigned  TargetFlags = 0 
)
inlinestatic

◆ CreateMetadata()

static MachineOperand llvm::MachineOperand::CreateMetadata ( const MDNode Meta)
inlinestatic

Definition at line 881 of file MachineOperand.h.

References MD, and MO_Metadata.

Referenced by llvm::MachineInstrBuilder::addMetadata(), and verifyAddrSpace().

◆ CreatePredicate()

static MachineOperand llvm::MachineOperand::CreatePredicate ( unsigned  Pred)
inlinestatic

Definition at line 908 of file MachineOperand.h.

References MO_Predicate, and Pred.

Referenced by llvm::MachineInstrBuilder::addPredicate(), and verifyAddrSpace().

◆ CreateReg()

static MachineOperand llvm::MachineOperand::CreateReg ( Register  Reg,
bool  isDef,
bool  isImp = false,
bool  isKill = false,
bool  isDead = false,
bool  isUndef = false,
bool  isEarlyClobber = false,
unsigned  SubReg = 0,
bool  isDebug = false,
bool  isInternalRead = false,
bool  isRenamable = false 
)
inlinestatic

Definition at line 774 of file MachineOperand.h.

References assert(), isDead(), isDebug(), isDef(), isEarlyClobber(), isInternalRead(), isKill(), isRenamable(), isUndef(), MO_Register, Reg, RegNo, setSubReg(), and SubReg.

Referenced by llvm::MachineInstr::addImplicitDefUseOperands(), llvm::GISelInstProfileBuilder::addNodeIDRegType(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::addRegisterDead(), llvm::MachineInstr::addRegisterDefined(), llvm::MachineInstr::addRegisterKilled(), llvm::SIInstrInfo::buildExtractSubRegOrImm(), combineKnownAdjacentMMOs(), llvm::condCodeOp(), convertImplicitDefToConstZero(), llvm::X86InstrInfo::convertToThreeAddress(), createPHIsForSelects(), llvm::createSIWholeQuadModePass(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), llvm::HexagonFrameLowering::emitPrologue(), enableAllocFrameElim(), findNextInsertLocation(), fixupGlobalSaddr(), llvm::X86InstrInfo::foldMemoryOperandImpl(), llvm::HexagonFrameLowering::getAlignaInstr(), llvm::X86AddressMode::getFullAddress(), getLogicalBitOpcode(), getUnderlyingArgRegs(), llvm::LiveVariables::HandleVirtRegDef(), imposeStackOrdering(), INITIALIZE_PASS(), isConstant(), isCopy(), isFunctionEntryBlock(), isImplicitOperandIn(), isSCC(), llvm::SIInstrInfo::legalizeGenericOperand(), llvm::CallLowering::lowerCall(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::predOps(), removeExternalCFGEdges(), llvm::rewriteT2FrameIndex(), llvm::FastISel::selectGetElementPtr(), llvm::FastISel::selectIntrinsicCall(), llvm::FastISel::selectPatchpoint(), llvm::FastISel::selectStackmap(), llvm::FastISel::selectXRayCustomEvent(), llvm::FastISel::selectXRayTypedEvent(), llvm::t1CondCodeOp(), llvm::tryFoldSPUpdateIntoPushPop(), and llvm::LiveDebugVariables::~LiveDebugVariables().

◆ CreateRegLiveOut()

static MachineOperand llvm::MachineOperand::CreateRegLiveOut ( const uint32_t Mask)
inlinestatic

◆ CreateRegMask()

static MachineOperand llvm::MachineOperand::CreateRegMask ( const uint32_t Mask)
inlinestatic

CreateRegMask - Creates a register mask operand referencing Mask.

The operand does not take ownership of the memory referenced by Mask, it must remain valid for the lifetime of the operand.

A RegMask operand represents a set of non-clobbered physical registers on an instruction that clobbers many registers, typically a call. The bit mask has a bit set for each physreg that is preserved by this instruction, as described in the documentation for TargetRegisterInfo::getCallPreservedMask().

Any physreg with a 0 bit in the mask is clobbered by the instruction.

Definition at line 869 of file MachineOperand.h.

References assert(), llvm::BitmaskEnumDetail::Mask(), MO_RegisterMask, and RegMask.

Referenced by llvm::MachineInstrBuilder::addRegMask(), llvm::FastISel::selectPatchpoint(), and verifyAddrSpace().

◆ CreateShuffleMask()

static MachineOperand llvm::MachineOperand::CreateShuffleMask ( const Constant C)
inlinestatic

Definition at line 914 of file MachineOperand.h.

References C, MO_ShuffleMask, and ShuffleMask.

Referenced by llvm::MachineInstrBuilder::addShuffleMask(), and verifyAddrSpace().

◆ CreateTargetIndex()

static MachineOperand llvm::MachineOperand::CreateTargetIndex ( unsigned  Idx,
int64_t  Offset,
unsigned  TargetFlags = 0 
)
inlinestatic

◆ dump()

LLVM_DUMP_METHOD void MachineOperand::dump ( ) const

Definition at line 959 of file MachineOperand.cpp.

References llvm::dbgs().

Referenced by clearParent(), and rescheduleCanonically().

◆ getBlockAddress()

const BlockAddress* llvm::MachineOperand::getBlockAddress ( ) const
inline

◆ getCFIIndex()

unsigned llvm::MachineOperand::getCFIIndex ( ) const
inline

◆ getCImm()

const ConstantInt* llvm::MachineOperand::getCImm ( ) const
inline

◆ getFPImm()

const ConstantFP* llvm::MachineOperand::getFPImm ( ) const
inline

◆ getGlobal()

const GlobalValue* llvm::MachineOperand::getGlobal ( ) const
inline

Definition at line 556 of file MachineOperand.h.

References assert(), and isGlobal().

Referenced by llvm::MachineInstrBuilder::addDisp(), addExclusiveRegPair(), llvm::X86FrameLowering::adjustForHiPEPrologue(), llvm::ARCMCInstLower::ARCMCInstLower(), llvm::EHStreamer::callToNoUnwindFunction(), changeFCMPPredToAArch64CC(), collectCallSiteParameters(), createPHIsForCMOVsInSinkBB(), llvm::PPCFrameLowering::emitEpilogue(), llvm::X86AsmPrinter::EmitFunctionBodyEnd(), llvm::ARMAsmPrinter::EmitInstruction(), llvm::BTFDebug::endFunctionImpl(), eraseDeadBBsAndChildren(), foldImmediates(), for(), llvm::getAddressFromInstr(), llvm::SystemZMCInstLower::getExpr(), llvm::MSP430MCInstLower::GetGlobalAddressSymbol(), llvm::BPFMCInstLower::GetGlobalAddressSymbol(), llvm::LanaiMCInstLower::GetGlobalAddressSymbol(), llvm::AArch64MCInstLower::GetGlobalAddressSymbol(), getLeaOP(), getMCSymbolForTOCPseudoMO(), GetSymbolFromOperand(), getVariantKind(), hasAnyNonFlatUseOfReg(), llvm::hash_value(), llvm::HexagonLowerToMC(), llvm::XCoreMCInstLower::Initialize(), llvm::MipsMCInstLower::Initialize(), INITIALIZE_PASS(), llvm::BTFDebug::InstLower(), IsCallReturnTwice(), llvm::AArch64CallLowering::isEligibleForTailCallOptimization(), isIdenticalTo(), llvm::PPCInstrInfo::isSignOrZeroExtended(), isSimilarDispOp(), llvm::AMDGPULegalizerInfo::legalizeGlobalValue(), llvm::MipsCallLowering::lowerCall(), llvm::ARMAsmPrinter::lowerOperand(), llvm::LowerRISCVMachineOperandToMCOperand(), LowerSymbolOperand(), llvm::AVRMCInstLower::lowerSymbolOperand(), llvm::AArch64MCInstLower::lowerSymbolOperandELF(), makeImplicit(), llvm::WebAssembly::mayThrow(), llvm::rdf::operator<<(), print(), llvm::AVRAsmPrinter::printOperand(), llvm::ARMAsmPrinter::PrintSymbolOperand(), llvm::AsmPrinter::PrintSymbolOperand(), llvm::ARMBaseInstrInfo::produceSameValue(), queryCallee(), llvm::DetectRoundChange::runOnMachineFunction(), swapMIOperands(), and VisitGlobalVariableForEmission().

◆ getImm()

int64_t llvm::MachineOperand::getImm ( ) const
inline

Definition at line 530 of file MachineOperand.h.

References assert(), and isImm().

Referenced by llvm::DwarfUnit::addConstantValue(), llvm::MachineInstrBuilder::addDisp(), addExclusiveRegPair(), llvm::R600InstrInfo::addFlag(), llvm::GISelInstProfileBuilder::addNodeIDMachineOperand(), addRegsToSet(), adjustDefLatency(), llvm::LanaiInstrInfo::analyzeCompare(), llvm::AArch64InstrInfo::analyzeCompare(), llvm::SystemZInstrInfo::analyzeCompare(), llvm::HexagonInstrInfo::analyzeCompare(), llvm::ARMBaseInstrInfo::analyzeCompare(), llvm::PPCInstrInfo::analyzeCompare(), llvm::X86InstrInfo::analyzeCompare(), llvm::SwingSchedulerDAG::applyInstrChange(), areCandidatesToMergeOrPair(), llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(), AssignProtectedObjSet(), llvm::SIInstrInfo::buildExtractSubRegOrImm(), llvm::R600InstrInfo::buildSlotOfVectorInstruction(), callWaitsOnFunctionReturn(), canBeExpandedToORR(), canCompareBeNewValueJump(), canFoldIntoCSel(), llvm::X86InstrInfo::canMakeTailCallConditional(), canTurnIntoCOPY(), changeFCMPPredToAArch64CC(), llvm::X86InstrInfo::classifyLEAReg(), llvm::R600InstrInfo::clearFlag(), combineKnownAdjacentMMOs(), llvm::PPCInstrInfo::commuteInstructionImpl(), llvm::X86InstrInfo::commuteInstructionImpl(), compareMachineOp(), CompareMBBNumbers(), computeExprForSpill(), ConvertDoubleToBytes(), llvm::PPCInstrInfo::convertToImmediateForm(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::convertToThreeAddress(), llvm::SystemZInstrInfo::convertToThreeAddress(), llvm::SIInstrInfo::convertToThreeAddress(), createPHIsForCMOVsInSinkBB(), createPHIsForSelects(), llvm::createR600ExpandSpecialInstrsPass(), llvm::createSIAddIMGInitPass(), llvm::createSIModeRegisterPass(), llvm::createSparcDelaySlotFillerPass(), llvm::X86InstrInfo::describeLoadedValue(), llvm::ARMFrameLowering::determineCalleeSaves(), llvm::SparcFrameLowering::eliminateCallFramePseudoInstr(), llvm::XCoreFrameLowering::eliminateCallFramePseudoInstr(), llvm::ARCFrameLowering::eliminateCallFramePseudoInstr(), llvm::BPFRegisterInfo::eliminateFrameIndex(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::SparcRegisterInfo::eliminateFrameIndex(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::RISCVRegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::AVRRegisterInfo::eliminateFrameIndex(), llvm::NVPTXRegisterInfo::eliminateFrameIndex(), llvm::ARCRegisterInfo::eliminateFrameIndex(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::AArch64RegisterInfo::eliminateFrameIndex(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::X86RegisterInfo::eliminateFrameIndex(), emitDebugValueComment(), llvm::AArch64FrameLowering::emitEpilogue(), llvm::PPCFrameLowering::emitEpilogue(), llvm::AArch64TargetLowering::EmitF128CSEL(), llvm::AsmPrinter::emitFrameAlloc(), llvm::X86AsmPrinter::EmitFunctionBodyEnd(), EmitHiLo(), emitIndirectDst(), emitIndirectSrc(), llvm::SystemZAsmPrinter::EmitInstruction(), llvm::ARMAsmPrinter::EmitInstruction(), llvm::X86AsmPrinter::EmitInstruction(), llvm::MipsAsmPrinter::EmitInstruction(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::BPFTargetLowering::EmitInstrWithCustomInserter(), llvm::AVRTargetLowering::EmitInstrWithCustomInserter(), llvm::MSP430TargetLowering::EmitInstrWithCustomInserter(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::ARMAsmPrinter::EmitJumpTableTBInst(), EmitNop(), EmitNops(), emitPostSt(), emitSelectPseudo(), emitXBegin(), llvm::HexagonEvaluator::evaluate(), llvm::BitTracker::MachineEvaluator::evaluate(), llvm::SIInstrInfo::expandMovDPP64(), ExpandMOVImmSExti8(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::R600InstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::SystemZInstrInfo::expandPostRAPseudo(), llvm::SparcTargetLowering::expandSelectCC(), expandSHXDROT(), extractDLC(), llvm::X86InstrInfo::findCommutedOpIndices(), findCondCodeUsedByInstr(), llvm::MachineInstr::findInlineAsmFlagIdx(), findSingleRegDef(), findStartOfTree(), llvm::MachineInstr::findTiedOperandIdx(), findUncondBrI(), llvm::SwingSchedulerDAG::fixupRegisterOverlaps(), fixupSEHOpcode(), llvm::foldFrameOffset(), llvm::SystemZInstrInfo::FoldImmediate(), llvm::PPCInstrInfo::FoldImmediate(), llvm::ARMBaseInstrInfo::FoldImmediate(), llvm::SIInstrInfo::FoldImmediate(), foldImmediates(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), followSubRegDef(), for(), llvm::AArch64InstrInfo::genAlternativeCodeSequence(), genFusedMultiply(), llvm::getAddressFromInstr(), getADDriFromLEA(), getAdjustedCmp(), llvm::HexagonInstrInfo::getBaseAndOffset(), getBaseWithConstantOffset(), llvm::SystemZInstrInfo::getBranchInfo(), getBufferStoreFormatOpcode(), getCmpForPseudo(), getComparePred(), getCompareSourceReg(), llvm::HexagonInstrInfo::getCompoundCandidateGroup(), llvm::HexagonInstrInfo::getCompoundOpcode(), llvm::getConstantVRegValWithLookThrough(), getDebugLocValue(), llvm::HexagonInstrInfo::getDuplexCandidateGroup(), getDwarfRegNum(), llvm::X86InstrInfo::getExecutionDomainCustom(), llvm::TargetInstrInfo::getExtractSubregInputs(), getFPTrueImmVal(), llvm::X86InstrInfo::getFrameAdjustment(), llvm::ARMBaseRegisterInfo::getFrameIndexInstrOffset(), llvm::MSP430InstrInfo::getFramePoppedByCallee(), llvm::TargetInstrInfo::getFrameSize(), llvm::TargetInstrInfo::getFrameTotalSize(), llvm::SystemZInstrInfo::getFusedCompare(), getHWReg(), llvm::StackMapOpers::getID(), GetImm(), getImmedFromMO(), getINCDECFromLEA(), llvm::HexagonInstrInfo::getIncrementValue(), llvm::MachineInstr::getInlineAsmDialect(), llvm::TargetInstrInfo::getInsertSubregInputs(), llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs(), llvm::getInstrPredicate(), llvm::AArch64InstrInfo::getInstSizeInBytes(), llvm::MipsInstrInfo::getInstSizeInBytes(), llvm::ARMBaseInstrInfo::getInstSizeInBytes(), getLeaOP(), getLoadStoreOffsetAlign(), getLoadStoreOffsetSizeInBits(), getLogicalBitOpcode(), getLSMultipleTransferSize(), getMappedOp(), getMCSymbolForTOCPseudoMO(), llvm::SIInstrInfo::getMemOperandWithOffset(), llvm::X86InstrInfo::getMemOperandWithOffset(), llvm::LanaiInstrInfo::getMemOperandWithOffsetWidth(), llvm::AArch64InstrInfo::getMemOperandWithOffsetWidth(), llvm::PPCInstrInfo::getMemOperandWithOffsetWidth(), getMemoryOpOffset(), llvm::SIRegisterInfo::getMUBUFInstrOffset(), llvm::SIInstrInfo::getNamedImmOperand(), getNewValueJumpOpcode(), llvm::PatchPointOpers::getNumCallArgs(), getNumMicroOpsSwiftLdSt(), llvm::StackMapOpers::getNumPatchBytes(), llvm::SIInstrInfo::getNumWaitStates(), getOModValue(), llvm::AArch64InstrInfo::getOutliningType(), getPostIndexedLoadStoreOpcode(), llvm::ARMBaseInstrInfo::getPredicate(), getReassignedChan(), llvm::MachineInstr::getRegClassConstraint(), llvm::TargetInstrInfo::getRegSequenceInputs(), llvm::getRegSequenceSubReg(), getRetOpcode(), llvm::X86InstrInfo::getSPAdjust(), getSrcFromCopy(), llvm::R600InstrInfo::getSrcs(), getStoreOffset(), getTruncatedShiftCount(), getUnconditionalBrDisp(), getVariantKind(), llvm::getVPTInstrPredicate(), getWinAllocaAmount(), llvm::hash_value(), HashMachineInstr(), hasLEAOffset(), llvm::SIInstrInfo::hasModifiersSet(), llvm::MachineInstr::hasUnmodeledSideEffects(), llvm::HexagonLowerToMC(), hoistAndMergeSGPRInits(), INITIALIZE_PASS(), llvm::Mips16RegisterInfo::intRegClass(), llvm::isAArch64FrameOffsetLegal(), isAddConstantOp(), llvm::ARMBaseInstrInfo::isAddrMode3OpMinusReg(), llvm::ARMBaseInstrInfo::isAm2ScaledReg(), llvm::AArch64InstrInfo::isAsCheapAsAMove(), llvm::PPCInstrInfo::isBDNZ(), llvm::AArch64InstrInfo::isCoalescableExtInstr(), isCompareZero(), isConstant(), llvm::HexagonInstrInfo::isConstExtended(), llvm::MachineInstr::isConvergent(), llvm::MipsSEInstrInfo::isCopyInstrImpl(), llvm::AArch64InstrInfo::isCopyInstrImpl(), isCrossCopy(), isDbgValueDescribedByReg(), llvm::AArch64InstrInfo::isFalkorShiftExtFast(), isFpMulInstruction(), llvm::PPCRegisterInfo::isFrameOffsetLegal(), llvm::AArch64InstrInfo::isGPRCopy(), llvm::AArch64InstrInfo::isGPRZero(), isGreaterThanNBitTFRI(), isIdenticalTo(), isIdentityValue(), isImplicitlyDef(), isIncrementOrDecrement(), llvm::SIInstrInfo::isInlineConstant(), isIntersect(), isKImmOperand(), isKImmOrKUImmOperand(), isKUImmOperand(), isLdOffsetInRangeOfSt(), llvm::ARMBaseInstrInfo::isLdstScaledReg(), llvm::ARMBaseInstrInfo::isLdstScaledRegNotPlusLsl2(), llvm::ARMBaseInstrInfo::isLdstSoMinusReg(), llvm::RISCVInstrInfo::isLoadFromStackSlot(), llvm::LanaiInstrInfo::isLoadFromStackSlot(), llvm::SparcInstrInfo::isLoadFromStackSlot(), llvm::HexagonInstrInfo::isLoadFromStackSlot(), llvm::AArch64InstrInfo::isLoadFromStackSlot(), llvm::AVRInstrInfo::isLoadFromStackSlot(), llvm::ARMBaseInstrInfo::isLoadFromStackSlot(), isLoadStoreThatCanHandleDisplacement(), isMergeableLdStUpdate(), llvm::R600InstrInfo::isPredicable(), llvm::ARMBaseInstrInfo::isPredicated(), isRedundantFlagInstr(), isRelevantAddressingMode(), isReverseInlineImm(), isSafeToFoldImmIntoCopy(), llvm::isScale(), isSCC(), llvm::AArch64InstrInfo::isSchedulingBoundary(), isSendMsgTraceDataOrGDS(), isSignExtendingOp(), isSimpleBD12Move(), isSimpleMove(), llvm::MachineInstr::isStackAligningInlineAsm(), llvm::SystemZInstrInfo::isStackSlotCopy(), llvm::RISCVInstrInfo::isStoreToStackSlot(), llvm::LanaiInstrInfo::isStoreToStackSlot(), llvm::AArch64InstrInfo::isStoreToStackSlot(), llvm::SparcInstrInfo::isStoreToStackSlot(), llvm::HexagonInstrInfo::isStoreToStackSlot(), llvm::AVRInstrInfo::isStoreToStackSlot(), llvm::ARMBaseInstrInfo::isStoreToStackSlot(), isSuitableForMask(), llvm::ARMBaseInstrInfo::isSwiftFastImmShift(), llvm::PPCInstrInfo::isTOCSaveMI(), isVRegCompatibleReg(), isZeroExtendingOp(), isZeroImm(), llvm::MipsInstrInfo::isZeroImm(), llvm::AArch64LegalizerInfo::legalizeIntrinsic(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::MSP430MCInstLower::Lower(), llvm::BPFMCInstLower::Lower(), llvm::LanaiMCInstLower::Lower(), llvm::WebAssemblyMCInstLower::lower(), llvm::LegalizerHelper::lower(), llvm::LegalizerHelper::lowerDynStackAlloc(), llvm::LegalizerHelper::lowerExtract(), llvm::LegalizerHelper::lowerInsert(), llvm::XCoreMCInstLower::LowerOperand(), llvm::ARCMCInstLower::LowerOperand(), llvm::SystemZMCInstLower::lowerOperand(), llvm::AArch64MCInstLower::lowerOperand(), llvm::MipsMCInstLower::LowerOperand(), LowerOperand(), llvm::ARMAsmPrinter::lowerOperand(), llvm::LowerPPCMachineOperandToMCOperand(), lowerRIEfLow(), lowerRIHigh(), lowerRILow(), llvm::LowerRISCVMachineOperandToMCOperand(), lowerSubvectorLoad(), lowerSubvectorStore(), makeImplicit(), matchSwap(), llvm::MachineInstr::mayLoad(), llvm::MachineInstr::mayStore(), Mips16WhichOp8uOr16simm(), llvm::SIInstrInfo::moveToVALU(), llvm::LegalizerHelper::narrowScalar(), llvm::LegalizerHelper::narrowScalarExtract(), llvm::LegalizerHelper::narrowScalarInsert(), llvm::PPCRegisterInfo::needsFrameBaseReg(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), optimizeVcndVcmpPair(), performCustomAdjustments(), llvm::MIPrinter::print(), print(), llvm::MachineInstr::print(), llvm::SystemZAsmPrinter::PrintAsmMemoryOperand(), llvm::AVRAsmPrinter::PrintAsmMemoryOperand(), llvm::HexagonAsmPrinter::PrintAsmMemoryOperand(), llvm::MipsAsmPrinter::PrintAsmMemoryOperand(), llvm::AVRAsmPrinter::PrintAsmOperand(), llvm::WebAssemblyAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::PrintAsmOperand(), llvm::X86AsmPrinter::PrintAsmOperand(), llvm::MipsAsmPrinter::PrintAsmOperand(), llvm::AsmPrinter::PrintAsmOperand(), printConstant(), llvm::MipsAsmPrinter::printFCCOperand(), llvm::AVRAsmPrinter::printOperand(), llvm::HexagonAsmPrinter::printOperand(), llvm::ARMAsmPrinter::printOperand(), llvm::MipsAsmPrinter::printOperand(), profitImm(), llvm::StackMaps::recordStackMap(), RemoveDeadAddBetweenLEAAndJT(), removeRedundantBlockingStores(), llvm::SIRegisterInfo::resolveFrameIndex(), llvm::PPCRegisterInfo::resolveFrameIndex(), llvm::rewriteAArch64FrameIndex(), llvm::rewriteARMFrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), rewriteP2Align(), llvm::rewriteT2FrameIndex(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::X86InstrInfo::setExecutionDomainCustom(), llvm::AArch64InstrInfo::shouldClusterMemOps(), shrinkScalarCompare(), shrinkScalarLogicOp(), swapMIOperands(), swapRegAndNonRegOperand(), llvm::SIInstrInfo::swapSourceModifiers(), llvm::SystemZInstrInfo::SystemZInstrInfo(), tieOpsIfNeeded(), llvm::LegalizationArtifactCombiner::tryCombineExtract(), tryConstantFoldOp(), tryFoldInst(), tryOptimizeLEAtoMOV(), tryToFoldACImm(), llvm::X86InstrInfo::unfoldMemoryOperand(), updateKillStatus(), updateOperand(), llvm::HexagonPacketizerList::useCalleesSP(), llvm::HexagonPacketizerList::useCallersSP(), verifyInsExtInstruction(), llvm::RISCVInstrInfo::verifyInstruction(), llvm::SIInstrInfo::verifyInstruction(), VerifyLowRegs(), and VisitGlobalVariableForEmission().

◆ getIndex()

int llvm::MachineOperand::getIndex ( ) const
inline

Definition at line 550 of file MachineOperand.h.

References assert(), isCPI(), isFI(), isJTI(), and isTargetIndex().

Referenced by llvm::MachineInstrBuilder::addDisp(), llvm::ARCMCInstLower::ARCMCInstLower(), llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), AssignProtectedObjSet(), BBHasFallthrough(), BBIsJumpedOver(), changeFCMPPredToAArch64CC(), llvm::HexagonFrameLowering::determineCalleeSaves(), llvm::BPFRegisterInfo::eliminateFrameIndex(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::SparcRegisterInfo::eliminateFrameIndex(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::RISCVRegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::AVRRegisterInfo::eliminateFrameIndex(), llvm::ARCRegisterInfo::eliminateFrameIndex(), llvm::NVPTXRegisterInfo::eliminateFrameIndex(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::MipsRegisterInfo::eliminateFrameIndex(), llvm::AArch64RegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::X86RegisterInfo::eliminateFrameIndex(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), emitDebugValueComment(), llvm::X86AsmPrinter::EmitFunctionBodyEnd(), EmitHiLo(), llvm::ARMAsmPrinter::EmitInstruction(), llvm::MipsAsmPrinter::EmitInstruction(), llvm::ARMAsmPrinter::EmitJumpTableAddrs(), llvm::ARMAsmPrinter::EmitJumpTableInsts(), llvm::ARMAsmPrinter::EmitJumpTableTBInst(), llvm::TargetLoweringBase::emitPatchPoint(), foldImmediates(), for(), llvm::getAddressFromInstr(), getConstantFromPool(), llvm::MSP430MCInstLower::GetConstantPoolIndexSymbol(), llvm::LanaiMCInstLower::GetConstantPoolIndexSymbol(), llvm::SystemZMCInstLower::getExpr(), llvm::MSP430MCInstLower::GetJumpTableSymbol(), llvm::LanaiMCInstLower::GetJumpTableSymbol(), getMCSymbolForTOCPseudoMO(), getMemsetValue(), getRetOpcode(), llvm::X86InstrInfo::getSPAdjust(), getStartOrEndSlot(), getUnconditionalBrDisp(), llvm::hash_value(), HashMachineInstr(), hasSameBaseOpValue(), llvm::HexagonLowerToMC(), llvm::GISelKnownBits::inferPtrAlignment(), llvm::XCoreMCInstLower::Initialize(), llvm::MipsMCInstLower::Initialize(), INITIALIZE_PASS(), insertCSRRestores(), isIdenticalTo(), llvm::RISCVInstrInfo::isLoadFromStackSlot(), llvm::MipsSEInstrInfo::isLoadFromStackSlot(), llvm::ARCInstrInfo::isLoadFromStackSlot(), llvm::XCoreInstrInfo::isLoadFromStackSlot(), llvm::LanaiInstrInfo::isLoadFromStackSlot(), llvm::SparcInstrInfo::isLoadFromStackSlot(), llvm::HexagonInstrInfo::isLoadFromStackSlot(), llvm::AArch64InstrInfo::isLoadFromStackSlot(), llvm::AVRInstrInfo::isLoadFromStackSlot(), llvm::ARMBaseInstrInfo::isLoadFromStackSlot(), llvm::SIInstrInfo::isSGPRStackAccess(), isSimilarDispOp(), isSimpleMove(), llvm::SIInstrInfo::isStackAccess(), isStackPtrRelative(), llvm::SystemZInstrInfo::isStackSlotCopy(), llvm::RISCVInstrInfo::isStoreToStackSlot(), llvm::MipsSEInstrInfo::isStoreToStackSlot(), llvm::LanaiInstrInfo::isStoreToStackSlot(), llvm::ARCInstrInfo::isStoreToStackSlot(), llvm::XCoreInstrInfo::isStoreToStackSlot(), llvm::AArch64InstrInfo::isStoreToStackSlot(), llvm::SparcInstrInfo::isStoreToStackSlot(), llvm::HexagonInstrInfo::isStoreToStackSlot(), llvm::AVRInstrInfo::isStoreToStackSlot(), llvm::ARMBaseInstrInfo::isStoreToStackSlot(), lookupCandidateBaseReg(), llvm::AArch64MCInstLower::lowerOperand(), llvm::ARMAsmPrinter::lowerOperand(), llvm::LowerPPCMachineOperandToMCOperand(), llvm::LowerRISCVMachineOperandToMCOperand(), LowerSymbolOperand(), MatchingStackOffset(), false::IntervalSorter::operator()(), llvm::MIPrinter::print(), print(), llvm::HexagonAsmPrinter::printOperand(), llvm::ARMAsmPrinter::printOperand(), llvm::MipsAsmPrinter::printOperand(), llvm::ARMBaseInstrInfo::produceSameValue(), llvm::ARMBaseInstrInfo::reMaterialize(), llvm::ScheduleDAGMILive::scheduleMI(), llvm::AArch64InstrInfo::shouldClusterMemOps(), swapRegAndNonRegOperand(), tryToFoldACImm(), and X86SelectAddress().

◆ getIntrinsicID()

Intrinsic::ID llvm::MachineOperand::getIntrinsicID ( ) const
inline

◆ getMBB()

MachineBasicBlock* llvm::MachineOperand::getMBB ( ) const
inline

Definition at line 545 of file MachineOperand.h.

References assert(), and isMBB().

Referenced by addIncomingValuesToPHIs(), allPhiOperandsUndefined(), llvm::MipsInstrInfo::analyzeBranch(), llvm::CombinerHelper::applyCombineShuffleVector(), llvm::CombinerHelper::applyElideBrByInvertingCond(), llvm::SwingSchedulerDAG::applyInstrChange(), llvm::ARCMCInstLower::ARCMCInstLower(), BBIsJumpedOver(), canTurnIntoCOPY(), changeFCMPPredToAArch64CC(), ConvertDoubleToBytes(), llvm::LiveRangeCalc::createDeadDefs(), llvm::createHexagonHardwareLoops(), createPHIsForCMOVsInSinkBB(), dominatesAllUsesOf(), EmitHiLo(), llvm::ARMAsmPrinter::EmitInstruction(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), EmitNops(), eraseDeadBBsAndChildren(), llvm::HexagonEvaluator::evaluate(), llvm::BitTracker::MachineEvaluator::evaluate(), llvm::AArch64InstrInfo::expandPostRAPseudo(), llvm::LegalizerHelper::fewerElementsVectorPhi(), findCorrespondingPred(), fixPHIsInSucc(), llvm::RISCVInstrInfo::getBranchDestBlock(), llvm::AVRInstrInfo::getBranchDestBlock(), llvm::AArch64InstrInfo::getBranchDestBlock(), llvm::SIInstrInfo::getBranchDestBlock(), getCmpForPseudo(), llvm::HexagonInstrInfo::getDotNewPredJumpOp(), llvm::SystemZMCInstLower::getExpr(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::PHI_iterator::getIncomingBlock(), getInitPhiReg(), getLoopPhiReg(), llvm::SystemZII::Branch::getMBBTarget(), getNewValueJumpOpcode(), getPHIDeps(), getPHIPred(), getPhiRegs(), getPHISrcRegOpIdx(), getRegsUsedByPHIs(), getTargetMBB(), getUnconditionalBrDisp(), getVariantKind(), llvm::hash_value(), HashMachineInstr(), hasVulnerableLoad(), llvm::HexagonLowerToMC(), llvm::XCoreMCInstLower::Initialize(), llvm::MipsMCInstLower::Initialize(), INITIALIZE_PASS(), insertPHI(), isConstant(), isIdenticalTo(), isImmValidForOpcode(), isSimilarDispOp(), IsUnconditionalJump(), llvm::SIInstrInfo::legalizeOperands(), llvm::MSP430MCInstLower::Lower(), llvm::BPFMCInstLower::Lower(), llvm::LanaiMCInstLower::Lower(), llvm::AArch64MCInstLower::lowerOperand(), llvm::MipsMCInstLower::LowerOperand(), llvm::ARMAsmPrinter::lowerOperand(), llvm::LowerPPCMachineOperandToMCOperand(), llvm::LowerRISCVMachineOperandToMCOperand(), LowerSymbolOperand(), llvm::LegalizerHelper::moreElementsVectorPhi(), llvm::LegalizerHelper::narrowScalar(), llvm::rdf::operator<<(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::PeelSingleBlockLoop(), llvm::PPCInstrInfo::PredicateInstruction(), print(), llvm::WebAssemblyAsmPrinter::PrintAsmOperand(), llvm::AVRAsmPrinter::printOperand(), llvm::HexagonAsmPrinter::printOperand(), llvm::ARMAsmPrinter::printOperand(), llvm::MipsAsmPrinter::printOperand(), llvm::RegBankSelect::RepairingPlacement::RepairingPlacement(), llvm::MachineBasicBlock::replacePhiUsesWith(), llvm::X86FrameLowering::spillCalleeSavedRegisters(), splitBlock(), splitEdge(), splitMBB(), updatePHIs(), VisitGlobalVariableForEmission(), and llvm::LegalizerHelper::widenScalar().

◆ getMCSymbol()

MCSymbol* llvm::MachineOperand::getMCSymbol ( ) const
inline

◆ getMetadata()

const MDNode* llvm::MachineOperand::getMetadata ( ) const
inline

◆ getOffset()

int64_t llvm::MachineOperand::getOffset ( ) const
inline

◆ getParent() [1/2]

MachineInstr* llvm::MachineOperand::getParent ( )
inline

getParent - Return the instruction that this operand belongs to.

Definition at line 235 of file MachineOperand.h.

Referenced by addSegmentsWithValNo(), llvm::MachineOperandIteratorBase::analyzeVirtReg(), llvm::CombinerHelper::applyCombineShuffleVector(), createBBSelectReg(), createDeadDef(), CriticalPathStep(), llvm::LiveRangeEdit::eraseVirtReg(), llvm::ModuloScheduleExpander::expand(), findSingleRegDef(), findSingleRegUse(), llvm::Localizer::getAnalysisUsage(), llvm::RegBankSelect::getAnalysisUsage(), getExtendTypeForInst(), getFoldableImm(), getImmedFromMO(), getLoadStoreOffsetSizeInBits(), getMFIfAvailable(), llvm::MachineRegisterInfo::defusechain_iterator< ReturnUses, ReturnDefs, SkipDebug, ByOperand, ByInstr, ByBundle >::getOperandNo(), getShiftTypeForInst(), GetSymbolRef(), getUsedRegMask(), getVariantKind(), INITIALIZE_PASS(), isCrossCopy(), isIdentityValue(), llvm::SIInstrInfo::isInlineConstant(), isKilled(), isKImmOperand(), isKUImmOperand(), isNoReturnDef(), isRenamable(), isSCC(), isStackPtrRelative(), isVirtualRegisterOperand(), moveForSingleUse(), llvm::SIInstrInfo::moveToVALU(), oneUseDominatesOtherUses(), llvm::MachineRegisterInfo::defusechain_instr_iterator< ReturnUses, ReturnDefs, SkipDebug, ByOperand, ByInstr, ByBundle >::operator*(), llvm::MachineRegisterInfo::defusechain_iterator< ReturnUses, ReturnDefs, SkipDebug, ByOperand, ByInstr, ByBundle >::operator++(), llvm::MachineRegisterInfo::defusechain_instr_iterator< ReturnUses, ReturnDefs, SkipDebug, ByOperand, ByInstr, ByBundle >::operator++(), llvm::MIPrinter::print(), rematerializeCheapDef(), replaceDominatedUses(), llvm::CombinerHelper::replaceRegOpWith(), replaceRegUsesAfterLoop(), llvm::MachineSSAUpdater::RewriteUse(), scavengeVReg(), llvm::ScheduleDAGMILive::scheduleMI(), llvm::AMDGPUInstructionSelector::select(), llvm::AArch64InstrInfo::shouldClusterMemOps(), llvm::SIInstrInfo::shouldClusterMemOps(), false::Chain::str(), llvm::TailDuplicator::tailDuplicateAndUpdate(), tryFoldInst(), tryToFoldACImm(), llvm::FastISel::tryToFoldLoad(), updateKillStatus(), UpdatePredRedefs(), llvm::MachineTraceMetrics::Ensemble::verify(), llvm::MachineFunction::verify(), and llvm::MachineRegisterInfo::verifyUseList().

◆ getParent() [2/2]

const MachineInstr* llvm::MachineOperand::getParent ( ) const
inline

Definition at line 236 of file MachineOperand.h.

◆ getPredicate()

unsigned llvm::MachineOperand::getPredicate ( ) const
inline

◆ getReg()

Register llvm::MachineOperand::getReg ( ) const
inline

getReg - Returns the register number.

Definition at line 353 of file MachineOperand.h.

References assert(), isReg(), and Register.

Referenced by llvm::AArch64CallLowering::AArch64CallLowering(), addExclusiveRegPair(), addLiveInRegs(), llvm::AMDGPURegisterBankInfo::addMappingFromTable(), llvm::GISelInstProfileBuilder::addNodeIDMachineOperand(), llvm::ScheduleDAGInstrs::addPhysRegDataDeps(), llvm::ScheduleDAGInstrs::addPhysRegDeps(), llvm::MachineInstr::addRegisterDead(), llvm::MachineInstr::addRegisterKilled(), llvm::MachineRegisterInfo::addRegOperandToUseList(), addRegsToSet(), addSegmentsWithValNo(), llvm::ScheduleDAGInstrs::addVRegDefDeps(), llvm::ScheduleDAGInstrs::addVRegUseDeps(), llvm::SITargetLowering::AdjustInstrPostInstrSelection(), llvm::HexagonSubtarget::adjustSchedDependency(), allPhiOperandsUndefined(), llvm::analyzeArguments(), llvm::LanaiInstrInfo::analyzeCompare(), llvm::AArch64InstrInfo::analyzeCompare(), llvm::SystemZInstrInfo::analyzeCompare(), llvm::HexagonInstrInfo::analyzeCompare(), llvm::ARMBaseInstrInfo::analyzeCompare(), llvm::PPCInstrInfo::analyzeCompare(), llvm::X86InstrInfo::analyzeCompare(), llvm::MachineOperandIteratorBase::analyzePhysReg(), llvm::MachineOperandIteratorBase::analyzeVirtReg(), AnyAliasLiveIn(), llvm::LiveRangeEdit::anyRematerializable(), llvm::HexagonSubtarget::CallMutation::apply(), llvm::HexagonSubtarget::BankConflictMutation::apply(), llvm::CombinerHelper::applyCombineConcatVectors(), llvm::CombinerHelper::applyCombineCopy(), llvm::CombinerHelper::applyCombineExtendingLoads(), llvm::CombinerHelper::applyCombineShuffleVector(), llvm::RegisterBankInfo::applyDefaultMapping(), llvm::CombinerHelper::applyElideBrByInvertingCond(), llvm::SwingSchedulerDAG::applyInstrChange(), areCandidatesToMergeOrPair(), llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), atomicReadDroppedOnZero(), llvm::biasPhysReg(), llvm::ARMBaseInstrInfo::breakPartialRegDependency(), llvm::X86InstrInfo::breakPartialRegDependency(), llvm::SIInstrInfo::buildExtractSubReg(), llvm::BuildMI(), buildMUBUFOffsetLoadStore(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::SIInstrInfo::buildShrunkInst(), llvm::R600InstrInfo::buildSlotOfVectorInstruction(), callWaitsOnFunctionReturn(), canCombine(), canCompareBeNewValueJump(), llvm::HexagonInstrInfo::canExecuteInBundle(), canFoldCopy(), canFoldIntoCSel(), canFoldIntoSelect(), llvm::HexagonPacketizerList::canPromoteToDotCur(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), llvm::SIInstrInfo::canShrink(), canTurnIntoCOPY(), llvm::MachineInstr::changeDebugValuesDefReg(), changeFCMPPredToAArch64CC(), CheckXWPInstr(), llvm::X86InstrInfo::classifyLEAReg(), llvm::HexagonPacketizerList::cleanUpDotCur(), clearKillFlags(), clobbersCTR(), collectCallSiteParameters(), llvm::MachineInstr::collectDebugValues(), CombineCVTAToLocal(), combineKnownAdjacentMMOs(), llvm::WebAssemblyInstrInfo::commuteInstructionImpl(), llvm::ARMBaseInstrInfo::commuteInstructionImpl(), llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::PPCInstrInfo::commuteInstructionImpl(), llvm::X86InstrInfo::commuteInstructionImpl(), compareMachineOp(), computeBranchTargetAndInversion(), computeBytesPoppedByCalleeForSRet(), llvm::GISelKnownBits::computeKnownBitsImpl(), llvm::TargetSchedModel::computeOutputLatency(), ConsecutiveInstr(), llvm::constrainOperandRegClass(), llvm::constrainSelectedInstRegOperands(), ContainsReg(), conversionLibcall(), ConvertDoubleToBytes(), convertImplicitDefToConstZero(), llvm::PPCInstrInfo::convertToImmediateForm(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::convertToThreeAddress(), llvm::SIInstrInfo::convertToThreeAddress(), copyHint(), llvm::SIInstrInfo::copyPhysReg(), copyRegOperand(), llvm::createBreakFalseDeps(), llvm::createCopyConstrainDAGMutation(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::CreateEmptyPHI(), llvm::createHexagonHardwareLoops(), llvm::createLanaiDelaySlotFillerPass(), llvm::createMemLibcall(), createPHIsForCMOVsInSinkBB(), createPHIsForSelects(), llvm::createR600ExpandSpecialInstrsPass(), llvm::createSIPreAllocateWWMRegsPass(), llvm::createSIWholeQuadModePass(), llvm::createSparcDelaySlotFillerPass(), llvm::createX86FixupBWInsts(), llvm::createX86FixupSetCC(), llvm::createXCoreFrameToArgsOffsetEliminationPass(), CriticalPathStep(), llvm::ScheduleDAGInstrs::deadDefHasNoUse(), definesFullReg(), llvm::ARMBaseInstrInfo::DefinesPredicate(), llvm::HexagonInstrInfo::DefinesPredicate(), llvm::PPCInstrInfo::DefinesPredicate(), llvm::X86InstrInfo::describeLoadedValue(), llvm::CombinerHelper::dominates(), dumpMachineInstrRangeWithSlotIndex(), llvm::BPFRegisterInfo::eliminateFrameIndex(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::SparcRegisterInfo::eliminateFrameIndex(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::AVRRegisterInfo::eliminateFrameIndex(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::ARCRegisterInfo::eliminateFrameIndex(), llvm::ThumbRegisterInfo::eliminateFrameIndex(), llvm::AArch64RegisterInfo::eliminateFrameIndex(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::PPCTargetLowering::EmitAtomicBinary(), emitBuildPairF64Pseudo(), emitDebugValueComment(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::AArch64TargetLowering::EmitF128CSEL(), llvm::X86AsmPrinter::EmitFunctionBodyEnd(), EmitHiLo(), llvm::AsmPrinter::emitImplicitDef(), emitIndirectDst(), emitIndirectSrc(), llvm::SystemZAsmPrinter::EmitInstruction(), llvm::ARMAsmPrinter::EmitInstruction(), llvm::X86AsmPrinter::EmitInstruction(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::BPFTargetLowering::EmitInstrWithCustomInserter(), llvm::AVRTargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::MSP430TargetLowering::EmitInstrWithCustomInserter(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::MipsTargetLowering::EmitInstrWithCustomInserter(), llvm::X86TargetLowering::EmitInstrWithCustomInserter(), llvm::ARMAsmPrinter::EmitJumpTableTBInst(), emitKill(), emitLoadM0FromVGPRLoop(), emitLoadSRsrcFromVGPRLoop(), EmitNop(), EmitNops(), llvm::PPCTargetLowering::EmitPartwordAtomicBinary(), emitPostSt(), emitReadCycleWidePseudo(), emitSelectPseudo(), llvm::MSP430TargetLowering::EmitShiftInstr(), emitSplitF64Pseudo(), emitXBegin(), eraseDeadBBsAndChildren(), eraseGPOpnd(), llvm::LiveRangeEdit::eraseVirtReg(), llvm::InstructionSelector::executeMatchTable(), llvm::ModuloScheduleExpander::expand(), Expand2AddrUndef(), expandLoadStackGuard(), expandMOV32r1(), llvm::SIInstrInfo::expandMovDPP64(), ExpandMOVImmSExti8(), expandNOVLXLoad(), expandNOVLXStore(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::R600InstrInfo::expandPostRAPseudo(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::AArch64InstrInfo::expandPostRAPseudo(), llvm::SystemZInstrInfo::expandPostRAPseudo(), llvm::PPCInstrInfo::expandPostRAPseudo(), llvm::SparcTargetLowering::expandSelectCC(), expandSHXDROT(), llvm::PPCInstrInfo::expandVSXMemPseudo(), llvm::CallLowering::ValueHandler::extendRegister(), extractDLC(), llvm::DbgVariableLocation::extractFromMachineInstruction(), llvm::LegalizerHelper::fewerElementsVectorBasic(), llvm::LegalizerHelper::fewerElementsVectorBuildVector(), llvm::LegalizerHelper::fewerElementsVectorCasts(), llvm::LegalizerHelper::fewerElementsVectorCmp(), llvm::LegalizerHelper::fewerElementsVectorImplicitDef(), llvm::LegalizerHelper::fewerElementsVectorMultiEltType(), llvm::LegalizerHelper::fewerElementsVectorPhi(), llvm::LegalizerHelper::fewerElementsVectorSelect(), llvm::LegalizerHelper::fewerElementsVectorUnmergeValues(), llvm::finalizeBundle(), findDeadCallerSavedReg(), findIncDecAfter(), findIntrinsicID(), findNextInsertLocation(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::findRegisterUseOperandIdx(), findSingleRegDef(), findSingleRegUse(), findSRegBaseAndIndex(), findStartOfTree(), findUncondBrI(), llvm::SIInstrInfo::fixImplicitOperands(), llvm::fixStackStores(), fixupCalleeSaveRestoreStackOffset(), llvm::PPCInstrInfo::fixupIsDeadOrKill(), llvm::ScheduleDAGInstrs::fixupKills(), llvm::SwingSchedulerDAG::fixupRegisterOverlaps(), llvm::foldFrameOffset(), llvm::SystemZInstrInfo::FoldImmediate(), llvm::PPCInstrInfo::FoldImmediate(), llvm::ARMBaseInstrInfo::FoldImmediate(), llvm::SIInstrInfo::FoldImmediate(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), foldPatchpoint(), foldVGPRCopyIntoRegSequence(), for(), forceReg(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), genFusedMultiply(), genMaddR(), llvm::getAddressFromInstr(), llvm::Localizer::getAnalysisUsage(), llvm::RegBankSelect::getAnalysisUsage(), getAssignFnsForCC(), getBaseAddressRegister(), getBaseWithConstantOffset(), getBufferStoreFormatOpcode(), getCallTargetRegOpnd(), getCmpForPseudo(), getComparePred(), getCompareSourceReg(), llvm::HexagonInstrInfo::getCompoundCandidateGroup(), llvm::HexagonInstrInfo::getCompoundOpcode(), llvm::getConstantVRegValWithLookThrough(), llvm::SIRegisterInfo::getConstrainedRegClassForOperand(), getCopyRegClasses(), getDataDeps(), llvm::getDefIgnoringCopies(), llvm::PPCInstrInfo::getDefMIPostRA(), getDefRegMask(), GetDSubRegs(), llvm::HexagonInstrInfo::getDuplexCandidateGroup(), getDwarfRegNum(), llvm::X86InstrInfo::getExecutionDomainCustom(), getExtendTypeForInst(), llvm::TargetInstrInfo::getExtractSubregInputs(), llvm::ARMBaseInstrInfo::getExtractSubregLikeInputs(), getFoldableImm(), getFPReg(), getFPTrueImmVal(), llvm::ARMBaseInstrInfo::getFramePred(), llvm::NVPTXAsmPrinter::getFunctionFrameSymbol(), llvm::SystemZInstrInfo::getFusedCompare(), getHalfSizedType(), llvm::HexagonHazardRecognizer::getHazardType(), getImmedFromMO(), getImmOrMaterializedImm(), getINCDECFromLEA(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::PHI_iterator::getIncomingValue(), getInitPhiReg(), llvm::TargetInstrInfo::getInsertSubregInputs(), llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs(), getInsertVecEltOpInfo(), llvm::X86RegisterBankInfo::getInstrAlternativeMappings(), llvm::AArch64RegisterBankInfo::getInstrAlternativeMappings(), llvm::AMDGPURegisterBankInfo::getInstrAlternativeMappings(), llvm::MipsRegisterBankInfo::getInstrMapping(), llvm::ARMRegisterBankInfo::getInstrMapping(), llvm::X86RegisterBankInfo::getInstrMapping(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), llvm::RegisterBankInfo::getInstrMappingImpl(), llvm::getInstrPredicate(), getInstrVecReg(), llvm::GISelKnownBits::getKnownBits(), getLaneCopyOpcode(), llvm::ScheduleDAGInstrs::getLaneMaskForMO(), getLeaOP(), getLiveLanesAt(), getLoadInfo(), getLogicalBitOpcode(), getLoopPhiReg(), getLSMultipleTransferSize(), getMappedOp(), getMCSymbolForTOCPseudoMO(), llvm::SIInstrInfo::getMemOperandWithOffset(), llvm::X86InstrInfo::getMemOperandWithOffset(), getMopState(), getNewSource(), getNewValueJumpOpcode(), llvm::rdf::DataFlowGraph::getNextShadow(), getNumMicroOpsSwiftLdSt(), getOffsetFromIndices(), getOModValue(), llvm::PPCInstrInfo::getOperandLatency(), llvm::HexagonInstrInfo::getOperandLatency(), llvm::ARMBaseInstrInfo::getOperandLatency(), llvm::SIInstrInfo::getOpRegClass(), llvm::SIInstrInfo::getOpSize(), getOtherVRegDef(), llvm::AArch64InstrInfo::getOutliningCandidateInfo(), llvm::AArch64InstrInfo::getOutliningType(), llvm::X86GenRegisterBankInfo::getPartialMappingIdx(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), llvm::X86InstrInfo::getPartialRegUpdateClearance(), llvm::R600AsmPrinter::getPassName(), getPHIDeps(), getPHIDestReg(), getPhiRegs(), getPHISourceReg(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::GetPHIValue(), getPostIndexedLoadStoreOpcode(), getRC32(), getReassignedChan(), llvm::MachineInstrBuilder::getReg(), llvm::SystemZRegisterInfo::getRegAllocationHints(), llvm::MachineInstr::getRegClassConstraintEffectForVReg(), getRegClassesForCopy(), getRegClassForUnfoldedLoad(), getRegClassFromGRPhysReg(), llvm::TargetInstrInfo::getRegSequenceInputs(), llvm::ARMBaseInstrInfo::getRegSequenceLikeInputs(), llvm::getRegState(), llvm::getRegSubRegPair(), getRegsUsedByPHIs(), getRetOpcode(), getRetpolineSymbol(), getShiftTypeForInst(), getShuffleComment(), getSingleDef(), llvm::X86InstrInfo::getSPAdjust(), getSrcFromCopy(), llvm::R600InstrInfo::getSrcs(), getSubOpcode(), getTag(), getTypeFromTypeIdx(), llvm::MachineInstr::getTypeToPrint(), getUnconditionalBrDisp(), llvm::X86InstrInfo::getUndefRegClearance(), llvm::SSAUpdaterTraits< MachineSSAUpdater >::GetUndefVal(), getUnderlyingObjects(), getUsedRegMask(), getV_CMPOpcode(), llvm::MachineSSAUpdater::GetValueInMiddleOfBlock(), llvm::SIInstrInfo::getVALUOp(), getVariantKind(), llvm::getVPTInstrPredicate(), getWinAllocaAmount(), llvm::MipsTargetLowering::HandleByVal(), handleNormalInst(), llvm::LiveVariables::HandleVirtRegDef(), HandleVRSaveUpdate(), llvm::hash_value(), HashMachineInstr(), hasInefficientLEABaseReg(), llvm::X86InstrInfo::hasLiveCondCodeDef(), hasOneNonDBGUseInst(), hasRAWHazard(), llvm::X86InstrInfo::hasReassociableOperands(), llvm::TargetInstrInfo::hasReassociableOperands(), llvm::TargetInstrInfo::hasReassociableSibling(), hasRegisterDependency(), llvm::MachineInstr::hasRegisterImplicitUseOperand(), hasSameBaseOpValue(), hasUseAfterLoop(), hasVectorOperands(), llvm::HexagonLowerToMC(), hoistAndMergeSGPRInits(), INITIALIZE_PASS(), insertCopy(), insertDivByZeroTrap(), InsertLDR_STR(), insertPHI(), llvm::BTFDebug::InstLower(), llvm::rdf::CopyPropagation::interpretAsCopy(), llvm::Mips16RegisterInfo::intRegClass(), llvm::ARMBaseInstrInfo::isAddrMode3OpImm(), llvm::ARMBaseInstrInfo::isAddrMode3OpMinusReg(), isAmbiguous(), llvm::AArch64InstrInfo::isAsCheapAsAMove(), llvm::RISCVInstrInfo::isAsCheapAsAMove(), llvm::InstructionSelector::isBaseWithConstantOffset(), isCallerPreservedOrConstPhysReg(), isCandidateStore(), llvm::AArch64InstrInfo::isCandidateToMergeOrPair(), llvm::WebAssembly::isChild(), isCoalescable(), llvm::AArch64InstrInfo::isCoalescableExtInstr(), llvm::X86InstrInfo::isCoalescableExtInstr(), llvm::PPCInstrInfo::isCoalescableExtInstr(), isCompareZero(), isConstant(), llvm::MachineInstr::isConstantValuePHI(), isCopy(), isCopyFeedingInvariantStore(), isCopyFromExec(), llvm::ARMBaseInstrInfo::isCopyInstrImpl(), llvm::AArch64InstrInfo::isCopyInstrImpl(), isCopyToExec(), isCopyToReg(), llvm::IsCPSRDead< MachineInstr >(), isCrossCopy(), isCSRestore(), isDbgValueDescribedByReg(), isDebug(), isDefInSubRange(), isDescribedByReg(), isEFLAGSLive(), llvm::rdf::TargetOperandInfo::isFixedReg(), isFpMulInstruction(), llvm::AArch64InstrInfo::isFPRCopy(), isFullCopyOf(), isFullExecCopy(), llvm::AArch64InstrInfo::isGPRCopy(), llvm::AArch64InstrInfo::isGPRZero(), isIdenticalOp(), isIdenticalTo(), llvm::MachineInstr::isIdenticalTo(), llvm::MachineInstr::isIdentityCopy(), isIdentityValue(), isImmValidForOpcode(), isImplicitlyDef(), isIncrementOrDecrement(), isIntersect(), llvm::ARMBaseInstrInfo::isLDMBaseRegInList(), isLEA(), llvm::SIInstrInfo::isLegalRegOperand(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), isLiveOut(), llvm::RISCVInstrInfo::isLoadFromStackSlot(), llvm::MipsSEInstrInfo::isLoadFromStackSlot(), llvm::ARCInstrInfo::isLoadFromStackSlot(), llvm::LanaiInstrInfo::isLoadFromStackSlot(), llvm::XCoreInstrInfo::isLoadFromStackSlot(), llvm::SparcInstrInfo::isLoadFromStackSlot(), llvm::HexagonInstrInfo::isLoadFromStackSlot(), llvm::AArch64InstrInfo::isLoadFromStackSlot(), llvm::AVRInstrInfo::isLoadFromStackSlot(), llvm::X86InstrInfo::isLoadFromStackSlot(), llvm::ARMBaseInstrInfo::isLoadFromStackSlot(), isLoadStoreThatCanHandleDisplacement(), isLocalCopy(), isLogicalOpOnExec(), llvm::SMSchedule::isLoopCarriedDefOfUse(), llvm::SwingSchedulerDAG::isLoopCarriedDep(), isMergeableLdStUpdate(), isMMSourceRegister(), isMMThreeBitGPRegister(), IsMovepDestinationRegPair(), isNonFoldablePartialRegisterLoad(), isNopCopy(), llvm::InstructionSelector::isOperandImmEqual(), isOperandKill(), llvm::SIInstrInfo::isOperandLegal(), isORCopyInst(), isPhysicalRegCopy(), llvm::R600InstrInfo::isPredicated(), isPreISelGenericFloatingPointOpcode(), isPromotableZeroStoreInst(), llvm::X86InstrInfo::isReallyTriviallyReMaterializable(), isRedundantFlagInstr(), isRelevantAddressingMode(), isRematerializable(), isRenamable(), IsSafeAndProfitableToMove(), isSameReg(), isSCC(), isSecondInstructionInSequence(), isSExtLoad(), llvm::SIInstrInfo::isSGPRStackAccess(), llvm::PPCInstrInfo::isSignOrZeroExtended(), isSimpleBD12Move(), isSimpleIf(), isSimpleIndexCalc(), isSimpleMove(), llvm::SIInstrInfo::isStackAccess(), isStackPtrRelative(), llvm::RISCVInstrInfo::isStoreToStackSlot(), llvm::MipsSEInstrInfo::isStoreToStackSlot(), llvm::LanaiInstrInfo::isStoreToStackSlot(), llvm::ARCInstrInfo::isStoreToStackSlot(), llvm::XCoreInstrInfo::isStoreToStackSlot(), llvm::AArch64InstrInfo::isStoreToStackSlot(), llvm::SparcInstrInfo::isStoreToStackSlot(), llvm::HexagonInstrInfo::isStoreToStackSlot(), llvm::AVRInstrInfo::isStoreToStackSlot(), llvm::ARMBaseInstrInfo::isStoreToStackSlot(), llvm::X86InstrInfo::isStoreToStackSlot(), isSubRegOf(), isSuitableForMask(), llvm::HexagonInstrInfo::isToBeScheduledASAP(), llvm::PPCInstrInfo::isTOCSaveMI(), isTransformable(), isTwoAddrUse(), isUncheckedLoadOrStoreOpcode(), llvm::MachineInstr::isUndefDebugValue(), isValidCopy(), llvm::SIInstrInfo::isVGPRCopy(), isVirtualRegisterOperand(), isVRegCompatibleReg(), llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast(), llvm::MipsLegalizerInfo::legalizeCustom(), llvm::ARMLegalizerInfo::legalizeCustom(), llvm::AMDGPULegalizerInfo::legalizeExtractVectorElt(), llvm::AMDGPULegalizerInfo::legalizeFastUnsafeFDIV(), llvm::AMDGPULegalizerInfo::legalizeFceil(), llvm::AMDGPULegalizerInfo::legalizeFDIVFastIntrin(), llvm::AMDGPULegalizerInfo::legalizeFMad(), llvm::AMDGPULegalizerInfo::legalizeFrint(), llvm::SIInstrInfo::legalizeGenericOperand(), llvm::AMDGPULegalizerInfo::legalizeGlobalValue(), llvm::AMDGPULegalizerInfo::legalizeImplicitArgPtr(), llvm::AMDGPULegalizerInfo::legalizeInsertVectorElt(), llvm::AArch64LegalizerInfo::legalizeIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc(), llvm::AMDGPULegalizerInfo::legalizeIsAddrSpace(), llvm::AMDGPULegalizerInfo::legalizeITOFP(), llvm::AMDGPULegalizerInfo::legalizeLoad(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsSMRD(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::legalizeOperandsVOP3(), llvm::AMDGPULegalizerInfo::legalizePreloadedArgIntrin(), llvm::AMDGPULegalizerInfo::legalizeRawBufferStore(), llvm::AMDGPULegalizerInfo::legalizeSinCos(), llvm::LegalizerHelper::libcall(), llvm::MipsSEInstrInfo::loadImmediate(), llvm::Mips16InstrInfo::loadImmediate(), loadM0FromVGPR(), llvm::Localizer::Localizer(), llvm::TargetRegisterInfo::lookThruCopyLike(), llvm::MSP430MCInstLower::Lower(), llvm::LanaiMCInstLower::Lower(), llvm::BPFMCInstLower::Lower(), llvm::WebAssemblyMCInstLower::lower(), llvm::LegalizerHelper::lower(), llvm::LegalizerHelper::lowerBitCount(), llvm::ARMCallLowering::lowerCall(), llvm::PPCRegisterInfo::lowerCRBitRestore(), llvm::PPCRegisterInfo::lowerCRBitSpilling(), llvm::PPCRegisterInfo::lowerCRRestore(), llvm::PPCRegisterInfo::lowerCRSpilling(), llvm::PPCRegisterInfo::lowerDynamicAlloc(), llvm::PPCRegisterInfo::lowerDynamicAreaOffset(), llvm::LegalizerHelper::lowerDynStackAlloc(), llvm::LegalizerHelper::lowerExtract(), llvm::LegalizerHelper::lowerFCopySign(), llvm::LegalizerHelper::lowerFMad(), llvm::LegalizerHelper::lowerFMinNumMaxNum(), LowerFPToInt(), llvm::LegalizerHelper::lowerFPTOUI(), llvm::LegalizerHelper::lowerInsert(), llvm::LegalizerHelper::lowerMinMax(), llvm::XCoreMCInstLower::LowerOperand(), llvm::ARCMCInstLower::LowerOperand(), llvm::SystemZMCInstLower::lowerOperand(), llvm::AArch64MCInstLower::lowerOperand(), llvm::MipsMCInstLower::LowerOperand(), LowerOperand(), llvm::ARMAsmPrinter::lowerOperand(), llvm::LowerPPCMachineOperandToMCOperand(), lowerRIEfLow(), lowerRIHigh(), lowerRILow(), llvm::LowerRISCVMachineOperandToMCOperand(), llvm::LegalizerHelper::lowerSADDO_SSUBO(), llvm::LegalizerHelper::lowerShuffleVector(), llvm::LegalizerHelper::lowerSITOFP(), lowerSubvectorLoad(), lowerSubvectorStore(), llvm::LegalizerHelper::lowerU64ToF32BitOps(), llvm::LegalizerHelper::lowerUITOFP(), llvm::LegalizerHelper::lowerUnmergeValues(), llvm::PPCRegisterInfo::lowerVRSAVERestore(), llvm::PPCRegisterInfo::lowerVRSAVESpilling(), makeImplicit(), llvm::rdf::DataFlowGraph::makeRegRef(), llvm::MIPatternMatch::BinaryOp_match< LHS_P, RHS_P, Opcode, Commutable >::match(), llvm::MIPatternMatch::UnaryOp_match< SrcTy, Opcode >::match(), llvm::CombinerHelper::matchCombineConcatVectors(), llvm::CombinerHelper::matchCombineCopy(), llvm::CombinerHelper::matchCombineShuffleVector(), llvm::CombinerHelper::matchElideBrByInvertingCond(), matchSwap(), mayAlias(), mayCombineMisaligned(), llvm::SIInstrInfo::mayReadEXEC(), MIIsInTerminatorSequence(), Mips16WhichOp8uOr16simm(), llvm::LegalizerHelper::moreElementsVector(), moveAndTeeForMultiUse(), llvm::MachineRegisterInfo::moveOperands(), llvm::SIInstrInfo::moveToVALU(), llvm::LegalizerHelper::narrowScalar(), llvm::LegalizerHelper::narrowScalarBasic(), llvm::LegalizerHelper::narrowScalarExtract(), llvm::LegalizerHelper::narrowScalarInsert(), llvm::LegalizerHelper::narrowScalarMul(), llvm::LegalizerHelper::narrowScalarSelect(), llvm::LegalizerHelper::narrowScalarShift(), llvm::LegalizerHelper::narrowScalarShiftByConstant(), llvm::AggressiveAntiDepBreaker::Observe(), oneUseDominatesOtherUses(), optimizeCall(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::X86InstrInfo::optimizeLoadInstr(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::ARMBaseInstrInfo::optimizeSelect(), optimizeVcndVcmpPair(), llvm::SMSchedule::orderDependence(), parseOperands(), llvm::PeelSingleBlockLoop(), performSink(), preservesValueOf(), print(), llvm::SystemZAsmPrinter::PrintAsmMemoryOperand(), llvm::AVRAsmPrinter::PrintAsmMemoryOperand(), llvm::ARMAsmPrinter::PrintAsmMemoryOperand(), printAsmMRegister(), llvm::AVRAsmPrinter::PrintAsmOperand(), llvm::HexagonAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::PrintAsmOperand(), llvm::AMDGPUAsmPrinter::PrintAsmOperand(), llvm::MipsAsmPrinter::PrintAsmOperand(), llvm::AVRAsmPrinter::printOperand(), llvm::HexagonAsmPrinter::printOperand(), llvm::ARMAsmPrinter::printOperand(), llvm::MipsAsmPrinter::printOperand(), llvm::ARMBaseInstrInfo::produceSameValue(), profitImm(), pushDepHeight(), llvm::MachineInstr::readsWritesVirtualRegister(), llvm::TargetInstrInfo::reassociateOps(), llvm::LegalizerHelper::reduceLoadStoreWidth(), regOverlapsSet(), llvm::WebAssemblyAsmPrinter::regToString(), llvm::R600SchedStrategy::releaseBottomNode(), llvm::X86InstrInfo::reMaterialize(), llvm::ARMBaseInstrInfo::reMaterialize(), llvm::TargetInstrInfo::reMaterialize(), removeCopies(), RemoveDeadAddBetweenLEAAndJT(), removeKillInfo(), llvm::MachineRegisterInfo::removeRegOperandFromUseList(), llvm::LiveVariables::removeVirtualRegisterDead(), llvm::LiveVariables::removeVirtualRegisterKilled(), llvm::LiveVariables::removeVirtualRegistersKilled(), llvm::RegBankSelect::RepairingPlacement::RepairingPlacement(), llvm::PPCFrameLowering::replaceFPWithRealFP(), llvm::PPCInstrInfo::replaceInstrOperandWithImm(), rescheduleCanonically(), llvm::SIRegisterInfo::resolveFrameIndex(), resultTests(), llvm::rewriteAArch64FrameIndex(), llvm::ThumbRegisterInfo::rewriteFrameIndex(), llvm::rewriteT2FrameIndex(), llvm::UnreachableBlockElimPass::run(), runOnBasicBlock(), llvm::InstructionSelect::runOnMachineFunction(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::MachinePipeliner::runOnMachineFunction(), llvm::R600SchedStrategy::schedNode(), llvm::ScheduleDAGMILive::scheduleMI(), llvm::AMDGPUInstructionSelector::select(), selectCopy(), selectFCMPOpc(), selectMergeValues(), selectSelectOpc(), selectSubregisterCopy(), selectUnmergeValues(), llvm::ARMBaseInstrInfo::setExecutionDomain(), llvm::X86InstrInfo::setExecutionDomainCustom(), setIsRenamable(), setM0ToIndexFromSGPR(), setReg(), llvm::MipsRegisterBankInfo::setRegBank(), llvm::X86InstrInfo::setSpecialOperandAttr(), llvm::AArch64InstrInfo::shouldClusterMemOps(), llvm::SIInstrInfo::shouldClusterMemOps(), llvm::HexagonRegisterInfo::shouldCoalesce(), llvm::SystemZRegisterInfo::shouldCoalesce(), shouldPreventUndefRegUpdateMemFold(), shouldUseAndMask(), shrinkScalarCompare(), shrinkScalarLogicOp(), simpleLibcall(), SinkingPreventsImplicitNullCheck(), sizeToSubRegIndex(), splitBlock(), splitMBB(), llvm::LiveDebugVariables::splitRegister(), false::Chain::str(), swapMIOperands(), swapRegAndNonRegOperand(), llvm::SystemZInstrInfo::SystemZInstrInfo(), llvm::TailDuplicator::tailDuplicateAndUpdate(), tieOpsIfNeeded(), tryAddToFoldList(), tryChangeVGPRtoSGPRinCopy(), llvm::LegalizationArtifactCombiner::tryCombineAnyExt(), llvm::LegalizationArtifactCombiner::tryCombineExtract(), llvm::CombinerHelper::tryCombineIndexedLoadStore(), llvm::LegalizationArtifactCombiner::tryCombineInstruction(), llvm::CombinerHelper::tryCombineMemCpyFamily(), llvm::LegalizationArtifactCombiner::tryCombineMerges(), llvm::LegalizationArtifactCombiner::tryCombineSExt(), llvm::LegalizationArtifactCombiner::tryCombineZExt(), tryConstantFoldOp(), llvm::LegalizationArtifactCombiner::tryFoldImplicitDef(), tryFoldInst(), llvm::tryFoldSPUpdateIntoPushPop(), tryOptimizeLEAtoMOV(), tryToFoldACImm(), llvm::X86InstrInfo::unfoldMemoryOperand(), unstackifyVRegsUsedInSplitBB(), unsupportedBinOp(), llvm::AntiDepBreaker::UpdateDbgValue(), updateLiveIn(), llvm::HexagonPacketizerList::updateOffset(), updateOperand(), UpdateOperandRegClass(), updateOperandRegConstraints(), updatePhysDepsDownwards(), updatePhysDepsUpwards(), llvm::HexagonSubtarget::usePredicatedCalls(), UseReg(), llvm::SIInstrInfo::usesConstantBus(), llvm::RegisterBankInfo::InstructionMapping::verify(), verifyCFIntrinsic(), llvm::SIInstrInfo::verifyInstruction(), VerifyLowRegs(), llvm::MachineRegisterInfo::verifyUseList(), VisitGlobalVariableForEmission(), llvm::LegalizerHelper::widenScalar(), llvm::X86CallLowering::X86CallLowering(), X86SelectAddress(), and llvm::LiveDebugVariables::~LiveDebugVariables().

◆ getRegLiveOut()

const uint32_t* llvm::MachineOperand::getRegLiveOut ( ) const
inline

getRegLiveOut - Returns a bit mask of live-out registers.

Definition at line 634 of file MachineOperand.h.

References assert(), and isRegLiveOut().

Referenced by getDwarfRegNum(), and print().

◆ getRegMask()

const uint32_t* llvm::MachineOperand::getRegMask ( ) const
inline

◆ getRegMaskSize()

static unsigned llvm::MachineOperand::getRegMaskSize ( unsigned  NumRegs)
inlinestatic

Returns number of elements needed for a regmask array.

Definition at line 629 of file MachineOperand.h.

Referenced by llvm::MachineFunction::allocateRegMask(), getMOVL(), isCallableFunction(), and llvm::AArch64RegisterInfo::UpdateCustomCallPreservedMask().

◆ getShuffleMask()

const Constant* llvm::MachineOperand::getShuffleMask ( ) const
inline

◆ getSubReg()

unsigned llvm::MachineOperand::getSubReg ( ) const
inline

Definition at line 358 of file MachineOperand.h.

References assert(), and isReg().

Referenced by addSegmentsWithValNo(), llvm::ScheduleDAGInstrs::addVRegDefDeps(), allPhiOperandsUndefined(), llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::SIInstrInfo::buildExtractSubReg(), canFoldCopy(), combineKnownAdjacentMMOs(), llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::PPCInstrInfo::commuteInstructionImpl(), computeBranchTargetAndInversion(), llvm::GISelKnownBits::computeKnownBitsImpl(), copyHint(), copyRegOperand(), llvm::createSIPreAllocateWWMRegsPass(), definesFullReg(), dumpMachineInstrRangeWithSlotIndex(), emitLoadM0FromVGPRLoop(), llvm::LiveRangeEdit::eraseVirtReg(), llvm::HexagonInstrInfo::expandPostRAPseudo(), findSingleRegDef(), findSRegBaseAndIndex(), llvm::SIInstrInfo::FoldImmediate(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), foldPatchpoint(), foldVGPRCopyIntoRegSequence(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), llvm::HexagonInstrInfo::getBaseAndOffset(), getDefRegMask(), getDwarfRegNum(), llvm::X86InstrInfo::getExecutionDomainCustom(), llvm::TargetInstrInfo::getExtractSubregInputs(), llvm::ARMBaseInstrInfo::getExtractSubregLikeInputs(), getImmOrMaterializedImm(), llvm::TargetInstrInfo::getInsertSubregInputs(), llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs(), llvm::ScheduleDAGInstrs::getLaneMaskForMO(), getLiveLanesAt(), getNewSource(), getOModValue(), llvm::SIInstrInfo::getOpSize(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), getRC32(), llvm::SystemZRegisterInfo::getRegAllocationHints(), llvm::MachineInstr::getRegClassConstraintEffect(), llvm::TargetInstrInfo::getRegSequenceInputs(), llvm::ARMBaseInstrInfo::getRegSequenceLikeInputs(), llvm::getRegSubRegPair(), getRegsUsedByPHIs(), getSrcFromCopy(), getUsedRegMask(), llvm::hash_value(), hoistAndMergeSGPRInits(), INITIALIZE_PASS(), insertPHI(), llvm::rdf::CopyPropagation::interpretAsCopy(), isCoalescable(), llvm::X86InstrInfo::isCoalescableExtInstr(), isCopy(), isCrossCopy(), isDebug(), llvm::rdf::TargetOperandInfo::isFixedReg(), llvm::MachineInstr::isFullCopy(), isFullUndefDef(), isIdenticalTo(), llvm::MachineInstr::isIdentityCopy(), llvm::SIInstrInfo::isLegalRegOperand(), llvm::AArch64InstrInfo::isLoadFromStackSlot(), llvm::X86InstrInfo::isLoadFromStackSlot(), llvm::ARMBaseInstrInfo::isLoadFromStackSlot(), llvm::SIInstrInfo::isOperandLegal(), isSafeToFoldImmIntoCopy(), isSameReg(), isSCC(), isSExtLoad(), isSimpleIf(), llvm::AArch64InstrInfo::isStoreToStackSlot(), llvm::ARMBaseInstrInfo::isStoreToStackSlot(), llvm::X86InstrInfo::isStoreToStackSlot(), isSubRegOf(), isVirtualRegisterOperand(), isVRegCompatibleReg(), llvm::SIInstrInfo::legalizeGenericOperand(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::ARMAsmPrinter::lowerOperand(), llvm::LowerPPCMachineOperandToMCOperand(), llvm::rdf::DataFlowGraph::makeRegRef(), matchSwap(), llvm::PPCInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeLoadInstr(), optimizeVcndVcmpPair(), print(), llvm::ARMAsmPrinter::printOperand(), profitImm(), readsReg(), llvm::MachineInstr::readsWritesVirtualRegister(), llvm::R600SchedStrategy::releaseBottomNode(), llvm::UnreachableBlockElimPass::run(), llvm::MachinePipeliner::runOnMachineFunction(), llvm::X86InstrInfo::setExecutionDomainCustom(), llvm::TailDuplicator::shouldTailDuplicate(), llvm::LiveDebugVariables::splitRegister(), substPhysReg(), substVirtReg(), swapRegAndNonRegOperand(), tryFoldInst(), tryToFoldACImm(), and updateOperand().

◆ getSymbolName()

const char* llvm::MachineOperand::getSymbolName ( ) const
inline

Definition at line 601 of file MachineOperand.h.

References assert(), and isSymbol().

Referenced by addExclusiveRegPair(), llvm::ARCMCInstLower::ARCMCInstLower(), llvm::BTFDebug::beginInstruction(), EmitHiLo(), llvm::ARMAsmPrinter::EmitInstruction(), for(), llvm::SystemZMCInstLower::getExpr(), llvm::MSP430MCInstLower::GetExternalSymbolSymbol(), llvm::BPFMCInstLower::GetExternalSymbolSymbol(), llvm::LanaiMCInstLower::GetExternalSymbolSymbol(), llvm::AArch64MCInstLower::GetExternalSymbolSymbol(), llvm::AArch64InstrInfo::getInstSizeInBytes(), llvm::ARCInstrInfo::getInstSizeInBytes(), llvm::MSP430InstrInfo::getInstSizeInBytes(), llvm::RISCVInstrInfo::getInstSizeInBytes(), llvm::AVRInstrInfo::getInstSizeInBytes(), llvm::MipsInstrInfo::getInstSizeInBytes(), llvm::ARMBaseInstrInfo::getInstSizeInBytes(), llvm::SystemZInstrInfo::getInstSizeInBytes(), llvm::PPCInstrInfo::getInstSizeInBytes(), llvm::SIInstrInfo::getInstSizeInBytes(), llvm::HexagonInstrInfo::getSize(), GetSymbolFromOperand(), getVariantKind(), llvm::hash_value(), llvm::HexagonLowerToMC(), llvm::XCoreMCInstLower::Initialize(), llvm::MipsMCInstLower::Initialize(), INITIALIZE_PASS(), isIdenticalTo(), isSimilarDispOp(), llvm::ARMAsmPrinter::lowerOperand(), llvm::LowerRISCVMachineOperandToMCOperand(), LowerSymbolOperand(), llvm::AArch64MCInstLower::lowerSymbolOperandELF(), makeImplicit(), llvm::WebAssembly::mayThrow(), llvm::rdf::operator<<(), optimizeCall(), print(), llvm::WebAssemblyAsmPrinter::PrintAsmOperand(), llvm::AVRAsmPrinter::printOperand(), query(), and VisitGlobalVariableForEmission().

◆ getTargetFlags()

unsigned llvm::MachineOperand::getTargetFlags ( ) const
inline

Definition at line 218 of file MachineOperand.h.

References isReg().

Referenced by llvm::MachineInstrBuilder::addDisp(), addExclusiveRegPair(), canDefBePartOfLOH(), createPHIsForCMOVsInSinkBB(), llvm::AArch64RegisterInfo::eliminateFrameIndex(), emitDirectiveRelocJalr(), llvm::X86AsmPrinter::EmitFunctionBodyEnd(), EmitHiLo(), llvm::ARMAsmPrinter::EmitInstruction(), llvm::X86AsmPrinter::EmitInstruction(), foldImmediates(), llvm::X86InstrInfo::foldMemoryOperandImpl(), for(), llvm::MipsInstrInfo::genInstrWithNewOpc(), llvm::MSP430MCInstLower::GetBlockAddressSymbol(), llvm::MSP430MCInstLower::GetConstantPoolIndexSymbol(), llvm::MSP430MCInstLower::GetExternalSymbolSymbol(), llvm::MSP430MCInstLower::GetGlobalAddressSymbol(), llvm::AArch64MCInstLower::GetGlobalAddressSymbol(), llvm::MSP430MCInstLower::GetJumpTableSymbol(), GetSymbolFromOperand(), GetSymbolRef(), getVariantKind(), handleMiddleInst(), handleUse(), llvm::hash_value(), llvm::HexagonLowerToMC(), llvm::MipsMCInstLower::Initialize(), INITIALIZE_PASS(), isCandidateLoad(), llvm::HexagonInstrInfo::isConstExtended(), isIdenticalTo(), llvm::WebAssemblyMCInstLower::lower(), llvm::SystemZMCInstLower::lowerOperand(), llvm::MipsMCInstLower::LowerOperand(), llvm::ARMAsmPrinter::lowerOperand(), lowerSymbolOperand(), LowerSymbolOperand(), llvm::AVRMCInstLower::lowerSymbolOperand(), llvm::MSP430MCInstLower::LowerSymbolOperand(), llvm::LanaiMCInstLower::LowerSymbolOperand(), llvm::AArch64MCInstLower::lowerSymbolOperandCOFF(), llvm::AArch64MCInstLower::lowerSymbolOperandDarwin(), llvm::AArch64MCInstLower::lowerSymbolOperandELF(), makeImplicit(), llvm::ARMAsmPrinter::printOperand(), llvm::MipsAsmPrinter::printOperand(), llvm::ARMAsmPrinter::PrintSymbolOperand(), and printTargetFlags().

◆ getType()

MachineOperandType llvm::MachineOperand::getType ( ) const
inline

getType - Returns the MachineOperandType for this operand.

Definition at line 216 of file MachineOperand.h.

Referenced by llvm::MachineInstrBuilder::addDisp(), llvm::MachineInstr::addOperand(), canDefBePartOfLOH(), compareMachineOp(), ConvertDoubleToBytes(), llvm::X86AsmPrinter::EmitFunctionBodyEnd(), EmitHiLo(), EmitNops(), llvm::SystemZMCInstLower::getExpr(), getMCSymbolForTOCPseudoMO(), getRetOpcode(), getVariantKind(), llvm::hash_value(), HashMachineInstr(), llvm::HexagonLowerToMC(), INITIALIZE_PASS(), IsAnAddressOperand(), llvm::DenseMapInfo< MachineOperand >::isEqual(), isIdenticalTo(), llvm::SIInstrInfo::isLiteralConstantLike(), llvm::MSP430MCInstLower::Lower(), llvm::BPFMCInstLower::Lower(), llvm::LanaiMCInstLower::Lower(), llvm::WebAssemblyMCInstLower::lower(), llvm::XCoreMCInstLower::LowerOperand(), llvm::ARCMCInstLower::LowerOperand(), llvm::SystemZMCInstLower::lowerOperand(), llvm::AArch64MCInstLower::lowerOperand(), llvm::MipsMCInstLower::LowerOperand(), LowerOperand(), llvm::ARMAsmPrinter::lowerOperand(), llvm::LowerPPCMachineOperandToMCOperand(), llvm::LowerRISCVMachineOperandToMCOperand(), LowerSymbolOperand(), makeImplicit(), llvm::MIPrinter::print(), print(), llvm::WebAssemblyAsmPrinter::PrintAsmOperand(), llvm::X86AsmPrinter::PrintAsmOperand(), llvm::MipsAsmPrinter::PrintAsmOperand(), llvm::AVRAsmPrinter::printOperand(), llvm::HexagonAsmPrinter::printOperand(), llvm::ARMAsmPrinter::printOperand(), llvm::MipsAsmPrinter::printOperand(), llvm::ScheduleDAGMILive::scheduleMI(), llvm::AArch64InstrInfo::shouldClusterMemOps(), and VisitGlobalVariableForEmission().

◆ isBlockAddress()

bool llvm::MachineOperand::isBlockAddress ( ) const
inline

isBlockAddress - Tests if this is a MO_BlockAddress operand.

Definition at line 336 of file MachineOperand.h.

References MO_BlockAddress.

Referenced by getBlockAddress(), getMCSymbolForTOCPseudoMO(), getOffset(), llvm::HexagonInstrInfo::isConstExtended(), isSimilarDispOp(), isValidDispOp(), and setOffset().

◆ isCFIIndex()

bool llvm::MachineOperand::isCFIIndex ( ) const
inline

Definition at line 344 of file MachineOperand.h.

References MO_CFIIndex.

Referenced by getCFIIndex().

◆ isCImm()

bool llvm::MachineOperand::isCImm ( ) const
inline

◆ isCPI()

bool llvm::MachineOperand::isCPI ( ) const
inline

◆ isDead()

bool llvm::MachineOperand::isDead ( ) const
inline

Definition at line 378 of file MachineOperand.h.

References assert(), and isReg().

Referenced by addExclusiveRegPair(), llvm::ScheduleDAGInstrs::addPhysRegDeps(), llvm::MachineInstr::addRegisterDead(), llvm::ScheduleDAGInstrs::addVRegDefDeps(), allPhiOperandsUndefined(), llvm::MachineOperandIteratorBase::analyzePhysReg(), atomicReadDroppedOnZero(), canFoldIntoSelect(), ChangeToRegister(), llvm::X86InstrInfo::classifyLEAReg(), llvm::ARMBaseInstrInfo::commuteInstructionImpl(), llvm::PPCInstrInfo::commuteInstructionImpl(), ContainsReg(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::convertToThreeAddress(), copyRegOperand(), llvm::createCopyConstrainDAGMutation(), CreateReg(), definesFullReg(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::finalizeBundle(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::PPCInstrInfo::fixupIsDeadOrKill(), llvm::ARMBaseInstrInfo::FoldImmediate(), for(), GetDSubRegs(), getFPReg(), getLiveLanesAt(), getMopState(), getNewSource(), llvm::rdf::DataFlowGraph::getNextShadow(), llvm::getRegState(), llvm::LiveVariables::HandleVirtRegDef(), llvm::X86InstrInfo::hasLiveCondCodeDef(), llvm::X86InstrInfo::hasReassociableOperands(), INITIALIZE_PASS(), InsertLDR_STR(), isCallerPreservedOrConstPhysReg(), llvm::rdf::TargetOperandInfo::isClobbering(), isCoalescable(), llvm::IsCPSRDead< MachineInstr >(), isCrossCopy(), isDataInvariant(), isDataInvariantLoad(), isFpMulInstruction(), isFullUndefDef(), llvm::MachineInstr::isIdenticalTo(), isLoadAndTestAsCmp(), isNopCopy(), isSCC(), isVirtualRegisterOperand(), makeImplicit(), moveAndTeeForMultiUse(), llvm::SIInstrInfo::moveToVALU(), print(), setPredicate(), llvm::X86InstrInfo::setSpecialOperandAttr(), swapRegAndNonRegOperand(), UpdateCPSRUse(), updatePhysDepsDownwards(), and VerifyLowRegs().

◆ isDebug()

bool llvm::MachineOperand::isDebug ( ) const
inline

◆ isDef()

bool llvm::MachineOperand::isDef ( ) const
inline

Definition at line 368 of file MachineOperand.h.

References assert(), and isReg().

Referenced by addLiveInRegs(), llvm::GISelInstProfileBuilder::addNodeIDMachineOperand(), llvm::ScheduleDAGInstrs::addPhysRegDataDeps(), llvm::ScheduleDAGInstrs::addPhysRegDeps(), llvm::MachineInstr::addRegisterDead(), llvm::MachineRegisterInfo::addRegOperandToUseList(), addRegsToSet(), llvm::ScheduleDAGInstrs::addVRegDefDeps(), llvm::MachineOperandIteratorBase::analyzePhysReg(), llvm::MachineOperandIteratorBase::analyzeVirtReg(), llvm::HexagonSubtarget::CallMutation::apply(), atomicReadDroppedOnZero(), llvm::BTFDebug::beginInstruction(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::HexagonInstrInfo::canExecuteInBundle(), canFoldIntoSelect(), ChangeToRegister(), clobbersCTR(), llvm::ARMBaseInstrInfo::commuteInstructionImpl(), computeBytesPoppedByCalleeForSRet(), llvm::constrainOperandRegClass(), ContainsReg(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), createBBSelectReg(), llvm::createLanaiDelaySlotFillerPass(), CreateReg(), llvm::createSparcDelaySlotFillerPass(), CriticalPathStep(), definesFullReg(), llvm::ARMBaseInstrInfo::DefinesPredicate(), llvm::HexagonInstrInfo::DefinesPredicate(), llvm::PPCInstrInfo::DefinesPredicate(), dumpMachineInstrRangeWithSlotIndex(), emitKill(), llvm::LiveRangeEdit::eraseVirtReg(), llvm::HexagonEvaluator::evaluate(), llvm::ModuloScheduleExpander::expand(), llvm::finalizeBundle(), findDeadCallerSavedReg(), findDefIdx(), llvm::MachineInstr::findRegisterDefOperandIdx(), findSingleRegUse(), findUseIdx(), llvm::ScheduleDAGInstrs::fixupKills(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::X86InstrInfo::foldMemoryOperandImpl(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), llvm::RegBankSelect::getAnalysisUsage(), getDefRegMask(), llvm::PPCInstrInfo::getInstrLatency(), getInstrVecReg(), getLiveLanesAt(), getNewSource(), getNewValueJumpOpcode(), llvm::PatchPointOpers::getNextScratchIdx(), llvm::rdf::DataFlowGraph::getNextShadow(), llvm::MachineInstr::getNumExplicitDefs(), llvm::getRegState(), getRegsUsedByPHIs(), llvm::HexagonInstrInfo::getSize(), handleNormalInst(), llvm::LiveVariables::HandleVirtRegDef(), llvm::hash_value(), llvm::MachineInstr::hasImplicitDef(), llvm::X86InstrInfo::hasLiveCondCodeDef(), hasRegisterDependency(), hasUseAfterLoop(), INITIALIZE_PASS(), isCallerPreservedOrConstPhysReg(), llvm::WebAssembly::isChild(), llvm::rdf::TargetOperandInfo::isClobbering(), isCoalescable(), isCopyFeedingInvariantStore(), isCrossCopy(), isDebug(), llvm::rdf::TargetOperandInfo::isFixedReg(), isIdenticalTo(), llvm::MachineInstr::isIdenticalTo(), isLEA(), llvm::SMSchedule::isLoopCarriedDefOfUse(), isNopCopy(), llvm::MachineInstr::isRegTiedToUseOperand(), isRenamable(), IsSafeAndProfitableToMove(), isSCC(), isSimpleIndexCalc(), isVirtualRegisterOperand(), llvm::Mips16InstrInfo::loadImmediate(), MIIsInTerminatorSequence(), llvm::SIInstrInfo::moveToVALU(), llvm::AggressiveAntiDepBreaker::Observe(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeLoadInstr(), llvm::SMSchedule::orderDependence(), parseOperands(), llvm::PatchPointOpers::PatchPointOpers(), llvm::MIPrinter::print(), print(), llvm::MachineInstr::print(), printImplicitRegisterFlag(), llvm::R600SchedStrategy::releaseBottomNode(), RemoveDeadAddBetweenLEAAndJT(), llvm::LiveVariables::removeVirtualRegisterDead(), llvm::RegBankSelect::RepairingPlacement::RepairingPlacement(), rescheduleCanonically(), resultTests(), setPredicate(), substPhysReg(), llvm::MachineInstr::tieOperands(), tryAddToFoldList(), updateOperand(), updatePhysDepsDownwards(), updatePhysDepsUpwards(), and llvm::HexagonSubtarget::usePredicatedCalls().

◆ isEarlyClobber()

bool llvm::MachineOperand::isEarlyClobber ( ) const
inline

◆ isFI()

bool llvm::MachineOperand::isFI ( ) const
inline

isFI - Tests if this is a MO_FrameIndex operand.

Definition at line 324 of file MachineOperand.h.

References MO_FrameIndex.

Referenced by llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), AssignProtectedObjSet(), canFoldIntoSelect(), llvm::ARMBaseInstrInfo::commuteInstructionImpl(), llvm::X86InstrInfo::describeLoadedValue(), llvm::HexagonFrameLowering::determineCalleeSaves(), llvm::BPFRegisterInfo::eliminateFrameIndex(), emitDebugValueComment(), llvm::TargetLoweringBase::emitPatchPoint(), findNextInsertLocation(), foldImmediates(), frameIndexMayFold(), llvm::HexagonFrameLowering::getAlignaInstr(), getFrameIndexOperandNum(), getIndex(), llvm::SIInstrInfo::getMemOperandWithOffset(), llvm::AArch64InstrInfo::getMemOperandWithOffsetWidth(), getOModValue(), llvm::X86InstrInfo::getSPAdjust(), llvm::AArch64InstrInfo::isCandidateToMergeOrPair(), isCSRestore(), isEFLAGSLive(), llvm::PPCRegisterInfo::isFrameOffsetLegal(), llvm::ARMBaseRegisterInfo::isFrameOffsetLegal(), llvm::SIInstrInfo::isImmOperandLegal(), llvm::isLeaMem(), llvm::SIInstrInfo::isLegalVSrcOperand(), llvm::RISCVInstrInfo::isLoadFromStackSlot(), llvm::MipsSEInstrInfo::isLoadFromStackSlot(), llvm::ARCInstrInfo::isLoadFromStackSlot(), llvm::XCoreInstrInfo::isLoadFromStackSlot(), llvm::LanaiInstrInfo::isLoadFromStackSlot(), llvm::SparcInstrInfo::isLoadFromStackSlot(), llvm::HexagonInstrInfo::isLoadFromStackSlot(), llvm::AArch64InstrInfo::isLoadFromStackSlot(), llvm::AVRInstrInfo::isLoadFromStackSlot(), llvm::ARMBaseInstrInfo::isLoadFromStackSlot(), llvm::isMem(), llvm::SIInstrInfo::isOperandLegal(), isRelevantAddressingMode(), llvm::SIInstrInfo::isSGPRStackAccess(), isSimpleMove(), llvm::SIInstrInfo::isStackAccess(), llvm::SystemZInstrInfo::isStackSlotCopy(), llvm::RISCVInstrInfo::isStoreToStackSlot(), llvm::MipsSEInstrInfo::isStoreToStackSlot(), llvm::LanaiInstrInfo::isStoreToStackSlot(), llvm::ARCInstrInfo::isStoreToStackSlot(), llvm::XCoreInstrInfo::isStoreToStackSlot(), llvm::AArch64InstrInfo::isStoreToStackSlot(), llvm::SparcInstrInfo::isStoreToStackSlot(), llvm::HexagonInstrInfo::isStoreToStackSlot(), llvm::AVRInstrInfo::isStoreToStackSlot(), llvm::ARMBaseInstrInfo::isStoreToStackSlot(), lookupCandidateBaseReg(), MatchingStackOffset(), llvm::AArch64RegisterInfo::needsFrameBaseReg(), llvm::ARMBaseRegisterInfo::needsFrameBaseReg(), false::IntervalSorter::operator()(), llvm::ThumbRegisterInfo::resolveFrameIndex(), llvm::SIRegisterInfo::resolveFrameIndex(), llvm::AArch64RegisterInfo::resolveFrameIndex(), llvm::PPCRegisterInfo::resolveFrameIndex(), llvm::ARMBaseRegisterInfo::resolveFrameIndex(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::ScheduleDAGMILive::scheduleMI(), setIndex(), llvm::AArch64InstrInfo::shouldClusterMemOps(), swapRegAndNonRegOperand(), tryAddToFoldList(), tryFoldInst(), tryToFoldACImm(), UpdateOperandRegClass(), and llvm::SIInstrInfo::verifyInstruction().

◆ isFPImm()

bool llvm::MachineOperand::isFPImm ( ) const
inline

◆ isGlobal()

bool llvm::MachineOperand::isGlobal ( ) const
inline

isGlobal - Tests if this is a MO_GlobalAddress operand.

Definition at line 332 of file MachineOperand.h.

References MO_GlobalAddress.

Referenced by addExclusiveRegPair(), llvm::X86FrameLowering::adjustForHiPEPrologue(), llvm::EHStreamer::callToNoUnwindFunction(), collectCallSiteParameters(), createPHIsForCMOVsInSinkBB(), llvm::createSparcDelaySlotFillerPass(), EmitHiLo(), llvm::ARMAsmPrinter::EmitInstruction(), EmitNop(), llvm::BTFDebug::endFunctionImpl(), eraseDeadBBsAndChildren(), foldImmediates(), for(), llvm::getAddressFromInstr(), llvm::HexagonInstrInfo::getDuplexCandidateGroup(), getGlobal(), getMCSymbolForTOCPseudoMO(), llvm::rdf::DataFlowGraph::getNextShadow(), getOffset(), getOModValue(), llvm::R600InstrInfo::getSrcs(), GetSymbolFromOperand(), hasLEAOffset(), INITIALIZE_PASS(), llvm::BTFDebug::InstLower(), isAnImmediateOperand(), IsCallReturnTwice(), llvm::HexagonInstrInfo::isConstExtended(), llvm::AArch64CallLowering::isEligibleForTailCallOptimization(), llvm::SIInstrInfo::isImmOperandLegal(), llvm::isLeaMem(), llvm::SIInstrInfo::isLegalVSrcOperand(), llvm::SIInstrInfo::isOperandLegal(), llvm::X86InstrInfo::isReallyTriviallyReMaterializable(), llvm::PPCInstrInfo::isSignOrZeroExtended(), isSimilarDispOp(), isValidDispOp(), llvm::MipsCallLowering::lowerCall(), llvm::AVRMCInstLower::lowerSymbolOperand(), llvm::AArch64MCInstLower::lowerSymbolOperandELF(), llvm::WebAssembly::mayThrow(), llvm::rdf::operator<<(), llvm::AsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::PrintSymbolOperand(), llvm::AsmPrinter::PrintSymbolOperand(), queryCallee(), llvm::DetectRoundChange::runOnMachineFunction(), setOffset(), swapMIOperands(), tryAddToFoldList(), tryFoldInst(), tryToFoldACImm(), and llvm::SIInstrInfo::verifyInstruction().

◆ isIdenticalTo()

bool MachineOperand::isIdenticalTo ( const MachineOperand Other) const

Returns true if this operand is identical to the specified operand except for liveness related flags (isKill, isUndef and isDead).

isIdenticalTo - Return true if this operand is identical to the specified operand.

Note that this should stay in sync with the hash_value overload below.

Definition at line 274 of file MachineOperand.cpp.

References llvm::lltok::equal, getBlockAddress(), getCFIIndex(), getCImm(), getFPImm(), getGlobal(), getImm(), getIndex(), getIntrinsicID(), getMBB(), getMCSymbol(), getMetadata(), getMFIfAvailable(), llvm::MCRegisterInfo::getNumRegs(), getOffset(), getPredicate(), getReg(), getRegMask(), getShuffleMask(), getSubReg(), getSymbolName(), getTargetFlags(), getType(), isDef(), llvm_unreachable, MO_BlockAddress, MO_CFIIndex, MO_CImmediate, MO_ConstantPoolIndex, MO_ExternalSymbol, MO_FPImmediate, MO_FrameIndex, MO_GlobalAddress, MO_Immediate, MO_IntrinsicID, MO_JumpTableIndex, MO_MachineBasicBlock, MO_MCSymbol, MO_Metadata, MO_Predicate, MO_Register, MO_RegisterLiveOut, MO_RegisterMask, MO_ShuffleMask, MO_TargetIndex, RegMask, and TRI.

Referenced by llvm::LanaiInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::AArch64InstrInfo::areMemAccessesTriviallyDisjoint(), llvm::PPCInstrInfo::areMemAccessesTriviallyDisjoint(), createPHIsForSelects(), getOModValue(), getUnderlyingObjects(), llvm::DenseMapInfo< MachineOperand >::isEqual(), isIdenticalOp(), llvm::MachineInstr::isIdenticalTo(), isImplicitOperandIn(), llvm::SwingSchedulerDAG::isLoopCarriedDep(), memOpsHaveSameBasePtr(), offsetsDoNotOverlap(), llvm::ARMBaseInstrInfo::produceSameValue(), setPredicate(), llvm::AArch64InstrInfo::shouldClusterMemOps(), and tryFoldInst().

◆ isImm()

bool llvm::MachineOperand::isImm ( ) const
inline

isImm - Tests if this is a MO_Immediate operand.

Definition at line 316 of file MachineOperand.h.

References MO_Immediate.

Referenced by llvm::DwarfUnit::addConstantValue(), llvm::GISelInstProfileBuilder::addNodeIDMachineOperand(), llvm::SystemZInstrInfo::analyzeCompare(), llvm::HexagonInstrInfo::analyzeCompare(), llvm::X86InstrInfo::analyzeCompare(), areCandidatesToMergeOrPair(), areCombinableOperations(), llvm::HexagonInstrInfo::areMemAccessesTriviallyDisjoint(), llvm::SIInstrInfo::buildExtractSubRegOrImm(), llvm::R600InstrInfo::buildSlotOfVectorInstruction(), canCompareBeNewValueJump(), canFoldIntoCSel(), changeFCMPPredToAArch64CC(), combineKnownAdjacentMMOs(), ConvertDoubleToBytes(), llvm::PPCInstrInfo::convertToImmediateForm(), llvm::X86InstrInfo::convertToThreeAddress(), llvm::SIInstrInfo::copyPhysReg(), llvm::createSparcDelaySlotFillerPass(), llvm::X86InstrInfo::describeLoadedValue(), llvm::X86RegisterInfo::eliminateFrameIndex(), emitDebugValueComment(), llvm::PPCFrameLowering::emitEpilogue(), llvm::X86AsmPrinter::EmitFunctionBodyEnd(), EmitHiLo(), EmitNop(), EmitNops(), llvm::HexagonEvaluator::evaluate(), llvm::SIInstrInfo::expandMovDPP64(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::MachineInstr::findInlineAsmFlagIdx(), findSingleRegDef(), llvm::MachineInstr::findTiedOperandIdx(), findUncondBrI(), llvm::PPCInstrInfo::FoldImmediate(), llvm::ARMBaseInstrInfo::FoldImmediate(), llvm::SIInstrInfo::FoldImmediate(), foldImmediates(), llvm::AArch64InstrInfo::genAlternativeCodeSequence(), getADDriFromLEA(), llvm::HexagonInstrInfo::getBaseAndOffset(), llvm::ARCInstrInfo::getBaseAndOffsetPosition(), llvm::HexagonInstrInfo::getBaseAndOffsetPosition(), getBaseWithConstantOffset(), llvm::HexagonInstrInfo::getCompoundCandidateGroup(), llvm::HexagonInstrInfo::getCompoundOpcode(), llvm::getConstantVRegValWithLookThrough(), getDebugLocValue(), llvm::HexagonInstrInfo::getDuplexCandidateGroup(), getDwarfRegNum(), llvm::X86InstrInfo::getExecutionDomainCustom(), llvm::TargetInstrInfo::getExtractSubregInputs(), llvm::R600InstrInfo::getFlagOp(), GetImm(), getImm(), getImmedFromMO(), getImmOrMaterializedImm(), getINCDECFromLEA(), llvm::HexagonInstrInfo::getIncrementValue(), llvm::TargetInstrInfo::getInsertSubregInputs(), getLeaOP(), llvm::X86InstrInfo::getMemOperandWithOffset(), llvm::LanaiInstrInfo::getMemOperandWithOffsetWidth(), llvm::AArch64InstrInfo::getMemOperandWithOffsetWidth(), llvm::PPCInstrInfo::getMemOperandWithOffsetWidth(), getOModValue(), llvm::AArch64InstrInfo::getOutliningType(), llvm::TargetInstrInfo::getRegSequenceInputs(), llvm::X86InstrInfo::getSPAdjust(), llvm::R600InstrInfo::getSrcs(), getStoreOffset(), getUnconditionalBrDisp(), getWinAllocaAmount(), hasLEAOffset(), hoistAndMergeSGPRInits(), llvm::HexagonInstrInfo::immediateExtend(), INITIALIZE_PASS(), isAddConstantOp(), llvm::ARMBaseInstrInfo::isAddrMode3OpMinusReg(), isAnImmediateOperand(), llvm::AArch64InstrInfo::isCandidateToMergeOrPair(), isCompareZero(), llvm::HexagonInstrInfo::isConstExtended(), llvm::MipsSEInstrInfo::isCopyInstrImpl(), isDbgValueDescribedByReg(), llvm::AArch64InstrInfo::isGPRZero(), isGreaterThanNBitTFRI(), isIdentityValue(), llvm::SIInstrInfo::isImmOperandLegal(), llvm::MachineInstr::isIndirectDebugValue(), llvm::SIInstrInfo::isInlineConstant(), llvm::isLeaMem(), llvm::SIInstrInfo::isLegalVSrcOperand(), llvm::SIInstrInfo::isLiteralConstant(), llvm::RISCVInstrInfo::isLoadFromStackSlot(), llvm::MipsSEInstrInfo::isLoadFromStackSlot(), llvm::ARCInstrInfo::isLoadFromStackSlot(), llvm::LanaiInstrInfo::isLoadFromStackSlot(), llvm::XCoreInstrInfo::isLoadFromStackSlot(), llvm::SparcInstrInfo::isLoadFromStackSlot(), llvm::HexagonInstrInfo::isLoadFromStackSlot(), llvm::AArch64InstrInfo::isLoadFromStackSlot(), llvm::AVRInstrInfo::isLoadFromStackSlot(), llvm::ARMBaseInstrInfo::isLoadFromStackSlot(), isLoadStoreThatCanHandleDisplacement(), llvm::SIInstrInfo::isOperandLegal(), llvm::X86InstrInfo::isReallyTriviallyReMaterializable(), isRelevantAddressingMode(), isSafeToFoldImmIntoCopy(), llvm::isScale(), isSCC(), isSimilarDispOp(), llvm::RISCVInstrInfo::isStoreToStackSlot(), llvm::MipsSEInstrInfo::isStoreToStackSlot(), llvm::LanaiInstrInfo::isStoreToStackSlot(), llvm::ARCInstrInfo::isStoreToStackSlot(), llvm::XCoreInstrInfo::isStoreToStackSlot(), llvm::AArch64InstrInfo::isStoreToStackSlot(), llvm::SparcInstrInfo::isStoreToStackSlot(), llvm::HexagonInstrInfo::isStoreToStackSlot(), llvm::AVRInstrInfo::isStoreToStackSlot(), llvm::ARMBaseInstrInfo::isStoreToStackSlot(), llvm::PPCInstrInfo::isTOCSaveMI(), isValidDispOp(), isVRegCompatibleReg(), isZeroImm(), llvm::MipsInstrInfo::isZeroImm(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::LegalizerHelper::lower(), makeImplicit(), matchSwap(), llvm::SIInstrInfo::moveToVALU(), llvm::LegalizerHelper::narrowScalar(), optimizeVcndVcmpPair(), llvm::TargetInstrInfo::PredicateInstruction(), llvm::MachineInstr::print(), llvm::HexagonAsmPrinter::PrintAsmMemoryOperand(), llvm::MipsAsmPrinter::PrintAsmMemoryOperand(), llvm::HexagonAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::PrintAsmOperand(), llvm::X86AsmPrinter::PrintAsmOperand(), llvm::MipsAsmPrinter::PrintAsmOperand(), llvm::AsmPrinter::PrintAsmOperand(), profitImm(), llvm::X86InstrInfo::setExecutionDomainCustom(), setImm(), llvm::R600InstrInfo::setImmOperand(), shrinkScalarCompare(), shrinkScalarLogicOp(), swapMIOperands(), swapRegAndNonRegOperand(), tryAddToFoldList(), tryConstantFoldOp(), tryFoldInst(), tryToFoldACImm(), llvm::SIInstrInfo::usesConstantBus(), validThroughout(), verifyInsExtInstruction(), llvm::RISCVInstrInfo::verifyInstruction(), llvm::SIInstrInfo::verifyInstruction(), VerifyLowRegs(), and VisitGlobalVariableForEmission().

◆ isImplicit()

bool llvm::MachineOperand::isImplicit ( ) const
inline

Definition at line 373 of file MachineOperand.h.

References assert(), and isReg().

Referenced by llvm::GISelInstProfileBuilder::addNodeIDMachineOperand(), llvm::MachineInstr::addOperand(), atomicReadDroppedOnZero(), llvm::TargetSchedModel::computeOperandLatency(), ContainsReg(), copyExtraImplicitOps(), llvm::MachineInstr::copyImplicitOps(), llvm::createSparcDelaySlotFillerPass(), definesFullReg(), dumpMachineInstrRangeWithSlotIndex(), llvm::ARMAsmPrinter::EmitJumpTableTBInst(), llvm::PPCInstrInfo::getDefMIPostRA(), getDwarfRegNum(), llvm::PPCInstrInfo::getInstrLatency(), getMopState(), getNewSource(), llvm::PatchPointOpers::getNextScratchIdx(), llvm::rdf::DataFlowGraph::getNextShadow(), llvm::MachineInstr::getNumExplicitDefs(), llvm::MachineInstr::getNumExplicitOperands(), llvm::HexagonInstrInfo::getOperandLatency(), llvm::ARMBaseInstrInfo::getOperandLatency(), llvm::getRegState(), getRetOpcode(), llvm::MachineInstr::hasImplicitDef(), llvm::MachineInstr::hasRegisterImplicitUseOperand(), hasVulnerableLoad(), llvm::HexagonLowerToMC(), INITIALIZE_PASS(), isCallerPreservedOrConstPhysReg(), llvm::WebAssembly::isChild(), isCoalescable(), isCopyFeedingInvariantStore(), isNopCopy(), isSCC(), isVirtualRegisterOperand(), llvm::SystemZMCInstLower::lower(), llvm::MSP430MCInstLower::Lower(), llvm::BPFMCInstLower::Lower(), llvm::LanaiMCInstLower::Lower(), llvm::WebAssemblyMCInstLower::lower(), llvm::XCoreMCInstLower::LowerOperand(), llvm::ARCMCInstLower::LowerOperand(), llvm::AArch64MCInstLower::lowerOperand(), llvm::MipsMCInstLower::LowerOperand(), LowerOperand(), llvm::ARMAsmPrinter::lowerOperand(), llvm::LowerRISCVMachineOperandToMCOperand(), moveAndTeeForMultiUse(), llvm::AggressiveAntiDepBreaker::Observe(), llvm::PatchPointOpers::PatchPointOpers(), llvm::MIPrinter::print(), print(), llvm::MachineInstr::print(), printImplicitRegisterFlag(), llvm::PPCInstrInfo::replaceInstrOperandWithImm(), shrinkScalarCompare(), llvm::tryFoldSPUpdateIntoPushPop(), tryToFoldACImm(), llvm::X86InstrInfo::unfoldMemoryOperand(), llvm::SIInstrInfo::usesConstantBus(), llvm::SIInstrInfo::verifyInstruction(), and VerifyLowRegs().

◆ isInternalRead()

bool llvm::MachineOperand::isInternalRead ( ) const
inline

◆ isIntrinsicID()

bool llvm::MachineOperand::isIntrinsicID ( ) const
inline

◆ isJTI()

bool llvm::MachineOperand::isJTI ( ) const
inline

◆ isKill()

bool llvm::MachineOperand::isKill ( ) const
inline

Definition at line 383 of file MachineOperand.h.

References assert(), and isReg().

Referenced by addExclusiveRegPair(), llvm::MachineInstr::addRegisterKilled(), llvm::MachineOperandIteratorBase::analyzePhysReg(), llvm::HexagonFrameLowering::assignCalleeSavedSpillSlots(), llvm::X86InstrInfo::classifyLEAReg(), llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::PPCInstrInfo::commuteInstructionImpl(), ContainsReg(), llvm::PPCInstrInfo::convertToImmediateForm(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::convertToThreeAddress(), copyFlagsToImplicitVCC(), copyRegOperand(), CreateReg(), llvm::SIRegisterInfo::eliminateFrameIndex(), emitBuildPairF64Pseudo(), llvm::AArch64TargetLowering::EmitF128CSEL(), llvm::ARMAsmPrinter::EmitInstruction(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), emitSplitF64Pseudo(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), llvm::finalizeBundle(), findIncDecAfter(), findPotentialBlockers(), llvm::MachineInstr::findRegisterUseOperandIdx(), findSingleRegDef(), llvm::fixStackStores(), llvm::PPCInstrInfo::fixupIsDeadOrKill(), llvm::ARMBaseInstrInfo::FoldImmediate(), llvm::SIInstrInfo::FoldImmediate(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), genFusedMultiply(), genMaddR(), GetDSubRegs(), getINCDECFromLEA(), getMopState(), getNewValueJumpOpcode(), getPostIndexedLoadStoreOpcode(), llvm::getRegState(), INITIALIZE_PASS(), insertDivByZeroTrap(), InsertFPConstInst(), InsertFPImmInst(), InsertLDR_STR(), InsertSPConstInst(), InsertSPImmInst(), isCoalescable(), isFpMulInstruction(), llvm::MachineInstr::isIdenticalTo(), isOperandKill(), isSCC(), isSimpleIndexCalc(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::MipsSEInstrInfo::loadImmediate(), llvm::PPCRegisterInfo::lowerCRBitSpilling(), llvm::PPCRegisterInfo::lowerCRSpilling(), llvm::PPCRegisterInfo::lowerDynamicAlloc(), llvm::PPCRegisterInfo::lowerVRSAVESpilling(), preserveCondRegFlags(), print(), llvm::TargetInstrInfo::reassociateOps(), RemoveDeadAddBetweenLEAAndJT(), removeKillInfo(), llvm::LiveVariables::removeVirtualRegisterKilled(), llvm::LiveVariables::removeVirtualRegistersKilled(), ReplaceFrameIndex(), setPredicate(), shrinkScalarCompare(), false::Chain::str(), swapMIOperands(), swapRegAndNonRegOperand(), llvm::SystemZInstrInfo::SystemZInstrInfo(), tryOptimizeLEAtoMOV(), UpdateCPSRUse(), updateKillStatus(), updatePhysDepsDownwards(), and VerifyLowRegs().

◆ isMBB()

bool llvm::MachineOperand::isMBB ( ) const
inline

◆ isMCSymbol()

bool llvm::MachineOperand::isMCSymbol ( ) const
inline

◆ isMetadata()

bool llvm::MachineOperand::isMetadata ( ) const
inline

isMetadata - Tests if this is a MO_Metadata operand.

Definition at line 342 of file MachineOperand.h.

References MO_Metadata.

Referenced by getMetadata(), llvm::MachineInstr::print(), and setMetadata().

◆ isPredicate()

bool llvm::MachineOperand::isPredicate ( ) const
inline

◆ isReg()

bool llvm::MachineOperand::isReg ( ) const
inline

isReg - Tests if this is a MO_Register operand.

Definition at line 314 of file MachineOperand.h.

References MO_Register.

Referenced by addLiveInRegs(), llvm::GISelInstProfileBuilder::addNodeIDMachineOperand(), llvm::MachineInstr::addOperand(), llvm::MachineInstr::addRegisterDead(), llvm::MachineInstr::addRegisterKilled(), addRegsToSet(), addTargetFlag(), llvm::ScheduleDAGInstrs::addVRegDefDeps(), llvm::HexagonSubtarget::adjustSchedDependency(), llvm::AArch64InstrInfo::analyzeCompare(), llvm::SystemZInstrInfo::analyzeCompare(), llvm::MachineOperandIteratorBase::analyzePhysReg(), llvm::MachineOperandIteratorBase::analyzeVirtReg(), AnyAliasLiveIn(), llvm::LiveRangeEdit::anyRematerializable(), llvm::HexagonSubtarget::CallMutation::apply(), llvm::HexagonSubtarget::BankConflictMutation::apply(), llvm::RegisterBankInfo::applyDefaultMapping(), atomicReadDroppedOnZero(), llvm::BTFDebug::beginInstruction(), llvm::BuildMI(), llvm::ScheduleDAGInstrs::buildSchedGraph(), callWaitsOnFunctionReturn(), canCombine(), llvm::HexagonInstrInfo::canExecuteInBundle(), canFoldIntoSelect(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), llvm::SIInstrInfo::canShrink(), changeFCMPPredToAArch64CC(), ChangeToES(), ChangeToFPImmediate(), ChangeToFrameIndex(), ChangeToGA(), ChangeToImmediate(), ChangeToMCSymbol(), ChangeToRegister(), ChangeToTargetIndex(), checkRegOnlyPHIInputs(), clobbersCTR(), collectCallSiteParameters(), llvm::MachineInstr::collectDebugValues(), combineKnownAdjacentMMOs(), llvm::ARMBaseInstrInfo::commuteInstructionImpl(), llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::SIInstrInfo::commuteInstructionImpl(), llvm::HexagonEvaluator::composeWithSubRegIndex(), computeBytesPoppedByCalleeForSRet(), computeExprForSpill(), llvm::constrainSelectedInstRegOperands(), ContainsReg(), llvm::PPCInstrInfo::convertToImmediateForm(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), llvm::X86InstrInfo::convertToThreeAddress(), llvm::SIInstrInfo::convertToThreeAddress(), copyExtraImplicitOps(), llvm::MachineInstr::copyImplicitOps(), llvm::SIInstrInfo::copyPhysReg(), copyRegOperand(), llvm::createBreakFalseDeps(), llvm::createLanaiDelaySlotFillerPass(), llvm::createSIPreAllocateWWMRegsPass(), llvm::createSIWholeQuadModePass(), llvm::createSparcDelaySlotFillerPass(), CriticalPathStep(), definesFullReg(), llvm::ARMBaseInstrInfo::DefinesPredicate(), llvm::HexagonInstrInfo::DefinesPredicate(), llvm::PPCInstrInfo::DefinesPredicate(), llvm::X86InstrInfo::describeLoadedValue(), dumpMachineInstrRangeWithSlotIndex(), earlyUseOperand(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), emitDebugValueComment(), EmitHiLo(), emitIndirectDst(), llvm::ARMAsmPrinter::EmitInstruction(), emitKill(), eraseGPOpnd(), llvm::LiveRangeEdit::eraseVirtReg(), llvm::HexagonEvaluator::evaluate(), llvm::BitTracker::MachineEvaluator::evaluate(), llvm::InstructionSelector::executeMatchTable(), llvm::ModuloScheduleExpander::expand(), llvm::SIInstrInfo::expandMovDPP64(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::PPCInstrInfo::expandPostRAPseudo(), extractDLC(), llvm::DbgVariableLocation::extractFromMachineInstruction(), llvm::finalizeBundle(), llvm::MipsInstrInfo::findCommutedOpIndices(), llvm::X86InstrInfo::findCommutedOpIndices(), llvm::TargetInstrInfo::findCommutedOpIndices(), findDeadCallerSavedReg(), findDefIdx(), findNextInsertLocation(), findPotentialBlockers(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::MachineInstr::findRegisterUseOperandIdx(), findSingleRegDef(), findSingleRegUse(), findSRegBaseAndIndex(), llvm::MachineInstr::findTiedOperandIdx(), findUseIdx(), llvm::SIInstrInfo::fixImplicitOperands(), llvm::PPCInstrInfo::fixupIsDeadOrKill(), llvm::ScheduleDAGInstrs::fixupKills(), llvm::SwingSchedulerDAG::fixupRegisterOverlaps(), llvm::PPCInstrInfo::FoldImmediate(), llvm::SIInstrInfo::FoldImmediate(), llvm::X86InstrInfo::foldMemoryOperandImpl(), for(), forceReg(), FuseInst(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), llvm::getAddressFromInstr(), llvm::RegBankSelect::getAnalysisUsage(), getBaseAddressRegister(), llvm::ARCInstrInfo::getBaseAndOffsetPosition(), llvm::HexagonInstrInfo::getBaseAndOffsetPosition(), getCallTargetRegOpnd(), getDataDeps(), getDebugLocValue(), llvm::PPCInstrInfo::getDefMIPostRA(), getDefRegMask(), getDwarfRegNum(), getExtendTypeForInst(), getFMAPatterns(), getFoldableImm(), getFPReg(), llvm::HexagonHazardRecognizer::getHazardType(), getImmedFromMO(), getImmOrMaterializedImm(), getINCDECFromLEA(), getInsertVecEltOpInfo(), llvm::PPCInstrInfo::getInstrLatency(), llvm::ARMRegisterBankInfo::getInstrMapping(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), llvm::RegisterBankInfo::getInstrMappingImpl(), getInstrVecReg(), getLiveLanesAt(), getMaddPatterns(), getMCSymbolForTOCPseudoMO(), llvm::SIInstrInfo::getMemOperandWithOffset(), llvm::HexagonInstrInfo::getMemOperandWithOffset(), llvm::X86InstrInfo::getMemOperandWithOffset(), llvm::LanaiInstrInfo::getMemOperandWithOffsetWidth(), llvm::AArch64InstrInfo::getMemOperandWithOffsetWidth(), llvm::PPCInstrInfo::getMemOperandWithOffsetWidth(), getNewSource(), getNewValueJumpOpcode(), llvm::PatchPointOpers::getNextScratchIdx(), llvm::rdf::DataFlowGraph::getNextShadow(), llvm::MachineInstr::getNumExplicitDefs(), llvm::MachineInstr::getNumExplicitOperands(), getOModValue(), llvm::HexagonInstrInfo::getOperandLatency(), llvm::SIInstrInfo::getOpSize(), getOtherVRegDef(), llvm::AArch64InstrInfo::getOutliningCandidateInfo(), llvm::AArch64InstrInfo::getOutliningType(), llvm::X86GenRegisterBankInfo::getPartialMappingIdx(), llvm::R600AsmPrinter::getPassName(), getPostIncrementOperand(), getReg(), llvm::MachineInstr::getRegClassConstraintEffect(), llvm::MachineInstr::getRegClassConstraintEffectForVReg(), getRegOrUndef(), llvm::getRegState(), llvm::getRegSubRegPair(), getRegsUsedByPHIs(), getRetpolineSymbol(), getShiftTypeForInst(), getShuffleComment(), llvm::HexagonInstrInfo::getSize(), llvm::X86InstrInfo::getSPAdjust(), getStoreTarget(), getSubReg(), getTag(), getTargetFlags(), llvm::MachineInstr::getTypeToPrint(), getUnderlyingArgRegs(), getUsedRegMask(), llvm::SIInstrInfo::getVALUOp(), getWinAllocaAmount(), handleNormalInst(), llvm::LiveVariables::HandleVirtRegDef(), HandleVRSaveUpdate(), hasInefficientLEABaseReg(), llvm::X86InstrInfo::hasLiveCondCodeDef(), llvm::X86InstrInfo::hasReassociableOperands(), llvm::TargetInstrInfo::hasReassociableOperands(), hasRegisterDependency(), llvm::MachineInstr::hasRegisterImplicitUseOperand(), hasSameBaseOpValue(), hasUseAfterLoop(), hasVectorOperands(), hoistAndMergeSGPRInits(), INITIALIZE_PASS(), llvm::Mips16RegisterInfo::intRegClass(), llvm::ARMBaseInstrInfo::isAddrMode3OpMinusReg(), llvm::RISCVInstrInfo::isAsCheapAsAMove(), llvm::InstructionSelector::isBaseWithConstantOffset(), isCallerPreservedOrConstPhysReg(), llvm::AArch64InstrInfo::isCandidateToMergeOrPair(), llvm::WebAssembly::isChild(), llvm::rdf::TargetOperandInfo::isClobbering(), isCoalescable(), isCompareZero(), isCopyFeedingInvariantStore(), isCopyFromExec(), isCopyToExec(), llvm::IsCPSRDead< MachineInstr >(), isCrossCopy(), isDbgValueDescribedByReg(), isDead(), isDebug(), isDebug(), isDef(), isDescribedByReg(), isEarlyClobber(), isEFLAGSLive(), llvm::AArch64InstrInfo::isFPRCopy(), isFullCopyOf(), isIdenticalOp(), llvm::MachineInstr::isIdenticalTo(), isIdentityValue(), isImplicit(), llvm::SystemZII::Branch::isIndirect(), llvm::MachineInstr::isIndirectDebugValue(), isInternalRead(), isIntersect(), isKill(), isLEA(), llvm::isLeaMem(), llvm::SIInstrInfo::isLegalRegOperand(), llvm::HexagonPacketizerList::isLegalToPacketizeTogether(), llvm::SIInstrInfo::isLegalVSrcOperand(), isLiveOut(), llvm::ARMBaseInstrInfo::isLoadFromStackSlot(), isLoadStoreThatCanHandleDisplacement(), isLogicalOpOnExec(), llvm::SMSchedule::isLoopCarriedDefOfUse(), llvm::isMem(), isMemoryOp(), isMMSourceRegister(), isMMThreeBitGPRegister(), isNopCopy(), llvm::InstructionSelector::isOperandImmEqual(), llvm::SIInstrInfo::isOperandLegal(), llvm::X86InstrInfo::isReallyTriviallyReMaterializable(), isRedundantFlagInstr(), llvm::MachineInstr::isRegTiedToDefOperand(), llvm::MachineInstr::isRegTiedToUseOperand(), isRelevantAddressingMode(), isRenamable(), IsSafeAndProfitableToMove(), isSameReg(), isSCC(), llvm::PPCInstrInfo::isSignOrZeroExtended(), isSimpleIndexCalc(), llvm::ARMBaseInstrInfo::isStoreToStackSlot(), isTied(), llvm::HexagonInstrInfo::isToBeScheduledASAP(), llvm::PPCInstrInfo::isTOCSaveMI(), isTwoAddrUse(), isUncheckedLoadOrStoreOpcode(), isUndef(), llvm::MachineInstr::isUndefDebugValue(), isUse(), isVirtualRegisterOperand(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::legalizeOperandsVOP3(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::Mips16InstrInfo::loadImmediate(), llvm::SystemZMCInstLower::lower(), llvm::WebAssemblyMCInstLower::lower(), llvm::X86CallLowering::lowerCall(), llvm::ARMCallLowering::lowerCall(), llvm::AArch64CallLowering::lowerCall(), llvm::MipsCallLowering::lowerCall(), llvm::rdf::DataFlowGraph::makeRegRef(), llvm::MIPatternMatch::operand_type_match::match(), matchSwap(), memOpsHaveSameBasePtr(), mergeOperations(), MIIsInTerminatorSequence(), moveAndTeeForMultiUse(), llvm::MachineRegisterInfo::moveOperands(), llvm::SIInstrInfo::moveToVALU(), llvm::AggressiveAntiDepBreaker::Observe(), oneUseDominatesOtherUses(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeLoadInstr(), optimizeVcndVcmpPair(), llvm::SMSchedule::orderDependence(), parseOperands(), performSink(), llvm::TargetInstrInfo::PredicateInstruction(), llvm::MIPrinter::print(), llvm::MachineInstr::print(), llvm::AVRAsmPrinter::PrintAsmMemoryOperand(), llvm::HexagonAsmPrinter::PrintAsmMemoryOperand(), llvm::ARMAsmPrinter::PrintAsmMemoryOperand(), llvm::AVRAsmPrinter::PrintAsmOperand(), llvm::HexagonAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::PrintAsmOperand(), llvm::X86AsmPrinter::PrintAsmOperand(), llvm::AMDGPUAsmPrinter::PrintAsmOperand(), llvm::MipsAsmPrinter::PrintAsmOperand(), llvm::AsmPrinter::PrintAsmOperand(), readsReg(), llvm::MachineInstr::readsWritesVirtualRegister(), llvm::R600SchedStrategy::releaseBottomNode(), RemoveDeadAddBetweenLEAAndJT(), removeKillInfo(), removeRegisterOperands(), llvm::LiveVariables::removeVirtualRegisterDead(), llvm::LiveVariables::removeVirtualRegisterKilled(), llvm::LiveVariables::removeVirtualRegistersKilled(), llvm::RegBankSelect::RepairingPlacement::RepairingPlacement(), llvm::PPCFrameLowering::replaceFPWithRealFP(), llvm::PPCInstrInfo::replaceInstrOperandWithImm(), rescheduleCanonically(), resultTests(), llvm::R600SchedStrategy::schedNode(), llvm::ScheduleDAGMILive::scheduleMI(), setImplicit(), setIsDead(), setIsDebug(), setIsDef(), setIsEarlyClobber(), setIsInternalRead(), setIsKill(), setIsRenamable(), setIsUndef(), llvm::X86InstrInfo::setSpecialOperandAttr(), setSubReg(), setTargetFlags(), llvm::AArch64InstrInfo::shouldClusterMemOps(), shouldPreventUndefRegUpdateMemFold(), shrinkScalarCompare(), shrinkScalarLogicOp(), SinkingPreventsImplicitNullCheck(), splitBlock(), llvm::LiveDebugVariables::splitRegister(), false::Chain::str(), llvm::SystemZInstrInfo::SystemZInstrInfo(), toString(), tryAddToFoldList(), tryConstantFoldOp(), tryFoldInst(), llvm::tryFoldSPUpdateIntoPushPop(), tryToFoldACImm(), llvm::X86InstrInfo::unfoldMemoryOperand(), llvm::MachineInstr::untieRegOperand(), llvm::AntiDepBreaker::UpdateDbgValue(), updateKillStatus(), updateOperand(), UpdateOperandRegClass(), updateOperandRegConstraints(), updatePhysDepsDownwards(), updatePhysDepsUpwards(), llvm::HexagonSubtarget::usePredicatedCalls(), UseReg(), llvm::SIInstrInfo::usesConstantBus(), llvm::RegisterBankInfo::InstructionMapping::verify(), verifyAddrSpace(), llvm::SIInstrInfo::verifyInstruction(), VerifyLowRegs(), llvm::MachineRegisterInfo::verifyUseList(), X86SelectAddress(), and llvm::LiveDebugVariables::~LiveDebugVariables().

◆ isRegLiveOut()

bool llvm::MachineOperand::isRegLiveOut ( ) const
inline

isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.

Definition at line 340 of file MachineOperand.h.

References MO_RegisterLiveOut.

Referenced by getDwarfRegNum(), and getRegLiveOut().

◆ isRegMask()

bool llvm::MachineOperand::isRegMask ( ) const
inline

◆ isRenamable()

bool MachineOperand::isRenamable ( ) const

isRenamable - Returns true if this register may be renamed, i.e.

it does not generate a value that is somehow read in a way that is not represented by the Machine IR (e.g. to meet an ABI or ISA requirement). This is only valid on physical register operands. Virtual registers are assumed to always be renamable regardless of the value of this field.

Operands that are renamable can freely be changed to any other register that is a member of the register class returned by MI->getRegClassConstraint().

isRenamable can return false for several different reasons:

  • ABI constraints (since liveness is not always precisely modeled). We conservatively handle these cases by setting all physical register operands that didn’t start out as virtual regs to not be renamable. Also any physical register operands created after register allocation or whose register is changed after register allocation will not be renamable. This state is tracked in the MachineOperand::IsRenamable bit.
  • Opcode/target constraints: for opcodes that have complex register class requirements (e.g. that depend on other operands/instructions), we set hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq in the machine opcode description. Operands belonging to instructions with opcodes that are marked hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq return false from isRenamable(). Additionally, the AllowRegisterRenaming target property prevents any operands from being marked renamable for targets that don't have detailed opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq values.

Definition at line 115 of file MachineOperand.cpp.

References assert(), getParent(), getReg(), llvm::MachineInstr::hasExtraDefRegAllocReq(), llvm::MachineInstr::hasExtraSrcRegAllocReq(), llvm::MachineInstr::IgnoreBundle, isDef(), llvm::Register::isPhysicalRegister(), isReg(), isUse(), and MI.

Referenced by llvm::TargetInstrInfo::commuteInstructionImpl(), CreateReg(), getMopState(), llvm::getRegState(), getRegUnits(), isNopCopy(), isUndef(), and print().

◆ isShuffleMask()

bool llvm::MachineOperand::isShuffleMask ( ) const
inline

Definition at line 347 of file MachineOperand.h.

References MO_ShuffleMask.

Referenced by getShuffleMask().

◆ isSymbol()

bool llvm::MachineOperand::isSymbol ( ) const
inline

◆ isTargetIndex()

bool llvm::MachineOperand::isTargetIndex ( ) const
inline

isTargetIndex - Tests if this is a MO_TargetIndex operand.

Definition at line 328 of file MachineOperand.h.

References MO_TargetIndex.

Referenced by getIndex(), getOffset(), llvm::SIInstrInfo::isImmOperandLegal(), llvm::SIInstrInfo::isLegalVSrcOperand(), llvm::SIInstrInfo::isOperandLegal(), setIndex(), and setOffset().

◆ isTied()

bool llvm::MachineOperand::isTied ( ) const
inline

◆ isUndef()

bool llvm::MachineOperand::isUndef ( ) const
inline

Definition at line 388 of file MachineOperand.h.

References assert(), isReg(), and isRenamable().

Referenced by addExclusiveRegPair(), llvm::MachineInstr::addRegisterKilled(), addSegmentsWithValNo(), llvm::ScheduleDAGInstrs::addVRegDefDeps(), allPhiOperandsUndefined(), ChangeToRegister(), llvm::X86InstrInfo::classifyLEAReg(), llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::X86InstrInfo::convertToThreeAddress(), copyFlagsToImplicitVCC(), copyRegOperand(), llvm::createBreakFalseDeps(), CreateReg(), llvm::createSIWholeQuadModePass(), definesFullReg(), llvm::ARMAsmPrinter::EmitJumpTableTBInst(), emitLoadM0FromVGPRLoop(), emitLoadSRsrcFromVGPRLoop(), llvm::SIInstrInfo::expandMovDPP64(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::expandPostRAPseudo(), expandSHXDROT(), llvm::finalizeBundle(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), for(), GetDSubRegs(), llvm::TargetInstrInfo::getExtractSubregInputs(), llvm::ARMBaseInstrInfo::getExtractSubregLikeInputs(), llvm::TargetInstrInfo::getInsertSubregInputs(), llvm::ARMBaseInstrInfo::getInsertSubregLikeInputs(), getLiveLanesAt(), getLogicalBitOpcode(), getMopState(), llvm::rdf::DataFlowGraph::getNextShadow(), getRegOrUndef(), llvm::TargetInstrInfo::getRegSequenceInputs(), llvm::ARMBaseInstrInfo::getRegSequenceLikeInputs(), llvm::getRegState(), llvm::X86InstrInfo::getUndefRegClearance(), INITIALIZE_PASS(), InsertLDR_STR(), isCoalescable(), llvm::IsCPSRDead< MachineInstr >(), isLocalCopy(), isMemoryOp(), isNopCopy(), isSCC(), isUseSafeToFold(), isVirtualRegisterOperand(), makeImplicit(), mayCombineMisaligned(), mergeOperations(), optimizeVcndVcmpPair(), preserveCondRegFlags(), print(), readsReg(), readsVCCZ(), llvm::MachineInstr::readsWritesVirtualRegister(), llvm::R600SchedStrategy::releaseBottomNode(), replaceDominatedUses(), llvm::UnreachableBlockElimPass::run(), setPredicate(), shouldPreventUndefRegUpdateMemFold(), shrinkScalarCompare(), swapRegAndNonRegOperand(), llvm::SystemZInstrInfo::SystemZInstrInfo(), and updateOperand().

◆ isUse()

bool llvm::MachineOperand::isUse ( ) const
inline

Definition at line 363 of file MachineOperand.h.

References assert(), and isReg().

Referenced by llvm::MachineInstr::addOperand(), llvm::ScheduleDAGInstrs::addPhysRegDeps(), llvm::MachineInstr::addRegisterKilled(), llvm::HexagonSubtarget::adjustSchedDependency(), llvm::HexagonSubtarget::CallMutation::apply(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::HexagonInstrInfo::canExecuteInBundle(), llvm::constrainOperandRegClass(), llvm::constrainSelectedInstRegOperands(), llvm::ARMBaseInstrInfo::convertToThreeAddress(), copyRegOperand(), llvm::createBreakFalseDeps(), llvm::createLanaiDelaySlotFillerPass(), llvm::createSparcDelaySlotFillerPass(), CriticalPathStep(), llvm::BitTracker::MachineEvaluator::evaluate(), llvm::MachineInstr::findRegisterUseOperandIdx(), llvm::MachineInstr::findTiedOperandIdx(), llvm::PPCInstrInfo::fixupIsDeadOrKill(), llvm::SwingSchedulerDAG::fixupRegisterOverlaps(), llvm::TargetInstrInfo::foldMemoryOperand(), for(), llvm::TargetInstrInfo::genAlternativeCodeSequence(), getCallTargetRegOpnd(), llvm::PPCInstrInfo::getDefMIPostRA(), getHalfSizedType(), getLiveLanesAt(), llvm::rdf::DataFlowGraph::getNextShadow(), getUsedRegMask(), handleNormalInst(), llvm::LiveVariables::HandleVirtRegDef(), hasRegisterDependency(), llvm::MachineInstr::hasRegisterImplicitUseOperand(), INITIALIZE_PASS(), isCoalescable(), isCopyFeedingInvariantStore(), llvm::IsCPSRDead< MachineInstr >(), isCrossCopy(), isDebug(), isFullCopyOf(), isFullUndefDef(), isMergeableLdStUpdate(), llvm::MachineInstr::isRegTiedToDefOperand(), isRenamable(), isSimpleIndexCalc(), isTwoAddrUse(), moveAndTeeForMultiUse(), llvm::SMSchedule::orderDependence(), parseOperands(), readsReg(), llvm::MachineInstr::readsWritesVirtualRegister(), RemoveDeadAddBetweenLEAAndJT(), resultTests(), llvm::SystemZInstrInfo::SystemZInstrInfo(), llvm::MachineInstr::tieOperands(), llvm::HexagonSubtarget::usePredicatedCalls(), llvm::SIInstrInfo::usesConstantBus(), and llvm::SIInstrInfo::verifyInstruction().

◆ print() [1/3]

void MachineOperand::print ( raw_ostream os,
const TargetRegisterInfo TRI = nullptr,
const TargetIntrinsicInfo IntrinsicInfo = nullptr 
) const

Print the MachineOperand to os.

Providing a valid TRI and IntrinsicInfo results in a more target-specific printing. If TRI and IntrinsicInfo are null, the function will try to pick it up from the parent.

Definition at line 727 of file MachineOperand.cpp.

References TRI.

Referenced by clearParent(), llvm::operator<<(), llvm::MIPrinter::print(), print(), llvm::MachineInstr::print(), and llvm::MachineFunction::verify().

◆ print() [2/3]

void MachineOperand::print ( raw_ostream os,
ModuleSlotTracker MST,
LLT  TypeToPrint,
bool  PrintDef,
bool  IsStandalone,
bool  ShouldPrintRegisterTies,
unsigned  TiedOperandIdx,
const TargetRegisterInfo TRI,
const TargetIntrinsicInfo IntrinsicInfo 
) const

More complex way of printing a MachineOperand.

Parameters
TypeToPrintspecifies the generic type to be printed on uses and defs. It can be determined using MachineInstr::getTypeToPrint.
PrintDef- whether we want to print def on an operand which isDef. Sometimes, if the operand is printed before '=', we don't print def.
IsStandalone- whether we want a verbose output of the MO. This prints extra information that can be easily inferred when printing the whole function, but not when printing only a fragment of it.
ShouldPrintRegisterTies- whether we want to print register ties. Sometimes they are easily determined by the instruction's descriptor (MachineInstr::hasComplexRegiterTies can determine if it's needed).
TiedOperandIdx- if we need to print register ties this needs to provide the index of the tied register. If not, it will be ignored.
TRI- provide more target-specific information to the printer. Unlike the previous function, this one will not try and get the information from it's parent.
IntrinsicInfo- same as TRI.

Definition at line 742 of file MachineOperand.cpp.

References C, llvm::MachineRegisterInfo::def_empty(), E, llvm::StringRef::empty(), llvm::ISD::FrameIndex, llvm::Constant::getAggregateElement(), getBlockAddress(), getCFIIndex(), getCImm(), getFPImm(), llvm::BlockAddress::getFunction(), getGlobal(), getImm(), getIndex(), getIntrinsicID(), getMBB(), getMCSymbol(), getMetadata(), getMFIfAvailable(), llvm::TargetIntrinsicInfo::getName(), llvm::Intrinsic::getName(), llvm::MCRegisterInfo::getNumRegs(), getOffset(), getPredicate(), llvm::CmpInst::getPredicateName(), getReg(), getRegLiveOut(), getRegMask(), getShuffleMask(), getSubReg(), llvm::TargetRegisterInfo::getSubRegIndexName(), getSymbolName(), getTargetIndexName(), getType(), llvm::Value::getType(), llvm::Type::getVectorNumElements(), I, isDead(), isDef(), isEarlyClobber(), isImplicit(), isInternalRead(), llvm::CmpInst::isIntPredicate(), isKill(), llvm::Register::isPhysicalRegister(), isRenamable(), isTied(), isUndef(), llvm::LLT::isValid(), llvm::Register::isVirtualRegister(), MO_BlockAddress, MO_CFIIndex, MO_CImmediate, MO_ConstantPoolIndex, MO_ExternalSymbol, MO_FPImmediate, MO_FrameIndex, MO_GlobalAddress, MO_Immediate, MO_IntrinsicID, MO_JumpTableIndex, MO_MachineBasicBlock, MO_MCSymbol, MO_Metadata, MO_Predicate, MO_Register, MO_RegisterLiveOut, MO_RegisterMask, MO_ShuffleMask, MO_TargetIndex, MRI, Name, llvm::None, llvm::Intrinsic::num_intrinsics, Pred, llvm::Metadata::printAsOperand(), llvm::Value::printAsOperand(), printCFI(), printFrameIndex(), printIRBlockReference(), llvm::printJumpTableEntryReference(), llvm::printLLVMNameWithoutPrefix(), llvm::printMBBReference(), printOperandOffset(), llvm::printReg(), llvm::printRegClassOrBank(), PrintRegMaskNumRegs, printSymbol(), printTargetFlags(), Reg, RegMask, SubReg, and TRI.

◆ print() [3/3]

void MachineOperand::print ( raw_ostream os,
LLT  TypeToPrint,
const TargetRegisterInfo TRI = nullptr,
const TargetIntrinsicInfo IntrinsicInfo = nullptr 
) const

Same as print(os, TRI, IntrinsicInfo), but allows to specify the low-level type to be printed the same way the full version of print(...) does it.

Definition at line 732 of file MachineOperand.cpp.

References print(), and tryToGetTargetInfo().

◆ printIRSlotNumber()

void MachineOperand::printIRSlotNumber ( raw_ostream OS,
int  Slot 
)
static

Print an IRSlotNumber.

Definition at line 613 of file MachineOperand.cpp.

Referenced by clearParent(), printIRBlockReference(), and printIRValueReference().

◆ printOperandOffset()

void MachineOperand::printOperandOffset ( raw_ostream OS,
int64_t  Offset 
)
static

Print the offset with explicit +/- signs.

Definition at line 603 of file MachineOperand.cpp.

Referenced by clearParent(), llvm::MachineMemOperand::print(), and print().

◆ printStackObjectReference()

void MachineOperand::printStackObjectReference ( raw_ostream OS,
unsigned  FrameIndex,
bool  IsFixed,
StringRef  Name 
)
static

Print a stack object reference.

Definition at line 590 of file MachineOperand.cpp.

References llvm::StringRef::empty(), and llvm::ISD::FrameIndex.

Referenced by clearParent(), printFrameIndex(), and llvm::MIPrinter::printStackObjectReference().

◆ printSubRegIdx()

void MachineOperand::printSubRegIdx ( raw_ostream OS,
uint64_t  Index,
const TargetRegisterInfo TRI 
)
static

Print a subreg index operand.

MO_Immediate operands can also be subreg idices. If it's the case, the subreg index name will be printed. MachineInstr::isOperandSubregIdx can be called to check this.

Definition at line 525 of file MachineOperand.cpp.

References llvm::TargetRegisterInfo::getSubRegIndexName(), and Index.

Referenced by clearParent(), llvm::MIPrinter::print(), and llvm::MachineInstr::print().

◆ printSymbol()

void MachineOperand::printSymbol ( raw_ostream OS,
MCSymbol Sym 
)
static

Print a MCSymbol as an operand.

Definition at line 586 of file MachineOperand.cpp.

Referenced by clearParent(), llvm::MIPrinter::print(), print(), llvm::MachineInstr::print(), and printCFI().

◆ printTargetFlags()

void MachineOperand::printTargetFlags ( raw_ostream OS,
const MachineOperand Op 
)
static

◆ readsReg()

bool llvm::MachineOperand::readsReg ( ) const
inline

readsReg - Returns true if this operand reads the previous value of its register.

A use operand with the <undef> flag set doesn't read its register. A sub-register def implicitly reads the other parts of the register being redefined unless the <undef> flag is set.

This refers to reading the register value from before the current instruction or bundle. Internal bundle reads are not included.

Definition at line 451 of file MachineOperand.h.

References assert(), getSubReg(), isInternalRead(), isReg(), isUndef(), isUse(), Reg, and setReg().

Referenced by llvm::MachineOperandIteratorBase::analyzePhysReg(), llvm::MachineOperandIteratorBase::analyzeVirtReg(), llvm::LiveRangeEdit::anyRematerializable(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::createCopyConstrainDAGMutation(), llvm::ConnectedVNInfoEqClasses::Distribute(), findUseIdx(), getDataDeps(), getLiveLanesAt(), llvm::ARMBaseInstrInfo::getPartialRegUpdateClearance(), llvm::X86InstrInfo::getPartialRegUpdateClearance(), getTag(), llvm::LiveVariables::HandleVirtRegDef(), isCrossCopy(), updatePhysDepsDownwards(), and updatePhysDepsUpwards().

◆ setCImm()

void llvm::MachineOperand::setCImm ( const ConstantInt CI)
inline

Definition at line 653 of file MachineOperand.h.

References assert(), CI, and isCImm().

Referenced by llvm::LegalizerHelper::widenScalar().

◆ setFPImm()

void llvm::MachineOperand::setFPImm ( const ConstantFP CFP)
inline

Definition at line 658 of file MachineOperand.h.

References assert(), CFP, and isFPImm().

Referenced by llvm::LegalizerHelper::widenScalar().

◆ setImm()

void llvm::MachineOperand::setImm ( int64_t  immVal)
inline

Definition at line 648 of file MachineOperand.h.

References assert(), and isImm().

Referenced by llvm::R600InstrInfo::addFlag(), llvm::SwingSchedulerDAG::applyInstrChange(), AssignProtectedObjSet(), llvm::R600InstrInfo::buildSlotOfVectorInstruction(), canTurnIntoCOPY(), changeFCMPPredToAArch64CC(), llvm::R600InstrInfo::clearFlag(), combineKnownAdjacentMMOs(), llvm::PPCInstrInfo::commuteInstructionImpl(), llvm::PPCInstrInfo::convertToImmediateForm(), CreateImm(), createPHIsForSelects(), llvm::createSIWholeQuadModePass(), llvm::WebAssemblyRegisterInfo::eliminateFrameIndex(), llvm::LanaiRegisterInfo::eliminateFrameIndex(), llvm::SystemZInstrInfo::expandPostRAPseudo(), findSingleRegDef(), llvm::SwingSchedulerDAG::fixupRegisterOverlaps(), fixupSEHOpcode(), getCallOpcode(), getLSMultipleTransferSize(), getOModValue(), llvm::AArch64InstrInfo::getOutliningType(), getReassignedChan(), getUnconditionalBrDisp(), hasOneNonDBGUseInst(), INITIALIZE_PASS(), isIntersect(), matchSwap(), llvm::LegalizerHelper::narrowScalar(), llvm::PPCInstrInfo::optimizeCompareInstr(), performCustomAdjustments(), llvm::ARMBaseInstrInfo::PredicateInstruction(), llvm::R600InstrInfo::PredicateInstruction(), llvm::TargetInstrInfo::PredicateInstruction(), rewriteP2Align(), llvm::HexagonInstrInfo::setBundleNoShuf(), llvm::setDirectAddressInInstr(), llvm::X86InstrInfo::setExecutionDomainCustom(), llvm::X86InstrInfo::setFrameAdjustment(), llvm::R600InstrInfo::setImmOperand(), shrinkScalarLogicOp(), llvm::SIInstrInfo::swapSourceModifiers(), llvm::SystemZInstrInfo::SystemZInstrInfo(), tieOpsIfNeeded(), llvm::HexagonPacketizerList::undoChangedOffset(), updateOperand(), llvm::HexagonPacketizerList::useCalleesSP(), and llvm::HexagonPacketizerList::useCallersSP().

◆ setImplicit()

void llvm::MachineOperand::setImplicit ( bool  Val = true)
inline

◆ setIndex()

void llvm::MachineOperand::setIndex ( int  Idx)
inline

◆ setIsDead()

void llvm::MachineOperand::setIsDead ( bool  Val = true)
inline

◆ setIsDebug()

void llvm::MachineOperand::setIsDebug ( bool  Val = true)
inline

Definition at line 521 of file MachineOperand.h.

References assert(), isReg(), and Val.

Referenced by AssignProtectedObjSet(), INITIALIZE_PASS(), and toString().

◆ setIsDef()

void MachineOperand::setIsDef ( bool  Val = true)

◆ setIsEarlyClobber()

void llvm::MachineOperand::setIsEarlyClobber ( bool  Val = true)
inline

Definition at line 516 of file MachineOperand.h.

References assert(), isReg(), and Val.

Referenced by llvm::MachineInstr::addOperand(), and llvm::LiveVariables::HandleVirtRegDef().

◆ setIsInternalRead()

void llvm::MachineOperand::setIsInternalRead ( bool  Val = true)
inline

◆ setIsKill()

void llvm::MachineOperand::setIsKill ( bool  Val = true)
inline

Definition at line 493 of file MachineOperand.h.

References assert(), isDebug(), isReg(), and Val.

Referenced by addExclusiveRegPair(), llvm::ScheduleDAGInstrs::addPhysRegDeps(), llvm::MachineInstr::addRegisterKilled(), addSegmentsWithValNo(), AnyAliasLiveIn(), clearKillFlags(), llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::PPCInstrInfo::commuteInstructionImpl(), llvm::R600InstrInfo::copyPhysReg(), llvm::SIInstrInfo::copyPhysReg(), copyRegOperand(), earlyUseOperand(), emitLoadSRsrcFromVGPRLoop(), llvm::HexagonInstrInfo::expandPostRAPseudo(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), findPotentialBlockers(), findStartOfTree(), llvm::PPCInstrInfo::fixupIsDeadOrKill(), llvm::ARMBaseInstrInfo::FoldImmediate(), llvm::SIInstrInfo::FoldImmediate(), getNewValueJumpOpcode(), getRegClassForUnfoldedLoad(), getRegsUsedByPHIs(), llvm::LiveVariables::HandleVirtRegDef(), INITIALIZE_PASS(), llvm::SIInstrInfo::insertBranch(), insertDivByZeroTrap(), llvm::CoalescerPair::isCoalescable(), isCoalescable(), isCopy(), isEFLAGSLive(), isFullCopyOf(), isFullUndefDef(), isMergeableLdStUpdate(), llvm::SIInstrInfo::legalizeOperands(), matchSwap(), llvm::AArch64InstrInfo::optimizeCondBranch(), preserveCondRegFlags(), RemoveDeadAddBetweenLEAAndJT(), removeKillInfo(), llvm::LiveVariables::removeVirtualRegisterKilled(), llvm::LiveVariables::removeVirtualRegistersKilled(), shrinkScalarCompare(), llvm::SystemZInstrInfo::SystemZInstrInfo(), tryToFoldACImm(), llvm::X86InstrInfo::unfoldMemoryOperand(), updateKillStatus(), and VerifyLowRegs().

◆ setIsRenamable()

void MachineOperand::setIsRenamable ( bool  Val = true)

◆ setIsUndef()

void llvm::MachineOperand::setIsUndef ( bool  Val = true)
inline

◆ setIsUse()

void llvm::MachineOperand::setIsUse ( bool  Val = true)
inline

Definition at line 483 of file MachineOperand.h.

References setIsDef(), and Val.

◆ setMBB()

void llvm::MachineOperand::setMBB ( MachineBasicBlock MBB)
inline

◆ setMetadata()

void llvm::MachineOperand::setMetadata ( const MDNode MD)
inline

Definition at line 677 of file MachineOperand.h.

References assert(), isMetadata(), and MD.

Referenced by AssignProtectedObjSet(), and llvm::updateDbgValueForSpill().

◆ setOffset()

void llvm::MachineOperand::setOffset ( int64_t  Offset)
inline

◆ setPredicate()

void llvm::MachineOperand::setPredicate ( unsigned  Predicate)
inline

◆ setReg()

void MachineOperand::setReg ( Register  Reg)

Change the register this operand corresponds to.

Definition at line 52 of file MachineOperand.cpp.

References llvm::MachineRegisterInfo::addRegOperandToUseList(), getMFIfAvailable(), getReg(), MRI, Reg, and llvm::MachineRegisterInfo::removeRegOperandFromUseList().

Referenced by addSegmentsWithValNo(), llvm::CombinerHelper::applyCombineExtendingLoads(), llvm::RegisterBankInfo::applyDefaultMapping(), llvm::SwingSchedulerDAG::applyInstrChange(), atomicReadDroppedOnZero(), llvm::R600InstrInfo::buildSlotOfVectorInstruction(), changeFCMPPredToAArch64CC(), llvm::WebAssemblyDebugValueManager::clone(), combineKnownAdjacentMMOs(), llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::PPCInstrInfo::commuteInstructionImpl(), computeBytesPoppedByCalleeForSRet(), llvm::constrainSelectedInstRegOperands(), copyRegOperand(), createBBSelectReg(), llvm::createBreakFalseDeps(), llvm::createR600ExpandSpecialInstrsPass(), llvm::createSIPreAllocateWWMRegsPass(), llvm::ConnectedVNInfoEqClasses::Distribute(), llvm::SparcRegisterInfo::eliminateFrameIndex(), llvm::SIRegisterInfo::eliminateFrameIndex(), emitLoadSRsrcFromVGPRLoop(), emitPostSt(), ExpandMOVImmSExti8(), expandNOVLXLoad(), expandNOVLXStore(), llvm::ARMBaseInstrInfo::expandPostRAPseudo(), findStartOfTree(), llvm::SIInstrInfo::fixImplicitOperands(), llvm::fixStackStores(), llvm::SwingSchedulerDAG::fixupRegisterOverlaps(), llvm::PPCInstrInfo::FoldImmediate(), llvm::ARMBaseInstrInfo::FoldImmediate(), llvm::SIInstrInfo::FoldImmediate(), llvm::X86InstrInfo::foldMemoryOperandImpl(), foldVGPRCopyIntoRegSequence(), llvm::Localizer::getAnalysisUsage(), getCallOpcode(), getHalfSizedType(), getInsertVecEltOpInfo(), getOtherVRegDef(), getRegClassFromGRPhysReg(), getRegsUsedByPHIs(), getTag(), hoistAndMergeSGPRInits(), INITIALIZE_PASS(), InsertLDR_STR(), insertPHI(), isCoalescable(), isEFLAGSLive(), isFullCopyOf(), isFullUndefDef(), isMergeableLdStUpdate(), isNopCopy(), llvm::SIInstrInfo::legalizeGenericOperand(), llvm::AArch64LegalizerInfo::legalizeIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeLoad(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsSMRD(), llvm::AMDGPULegalizerInfo::legalizeRawBufferStore(), llvm::LegalizerHelper::lowerBitCount(), llvm::X86CallLowering::lowerCall(), llvm::AArch64CallLowering::lowerCall(), llvm::MachineRegisterInfo::markUsesInDebugValueAsUndef(), maybeRewriteToDrop(), moveAndTeeForMultiUse(), moveForSingleUse(), llvm::SIInstrInfo::moveToVALU(), llvm::LegalizerHelper::narrowScalar(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::PeelSingleBlockLoop(), llvm::ARMBaseInstrInfo::PredicateInstruction(), llvm::R600InstrInfo::PredicateInstruction(), llvm::TargetInstrInfo::PredicateInstruction(), readsReg(), rematerializeCheapDef(), RemoveDeadAddBetweenLEAAndJT(), replaceDominatedUses(), llvm::PPCFrameLowering::replaceFPWithRealFP(), llvm::CombinerHelper::replaceRegOpWith(), replaceRegUsesAfterLoop(), llvm::MachineRegisterInfo::replaceRegWith(), llvm::MachineSSAUpdater::RewriteUse(), llvm::rdf::CopyPropagation::run(), llvm::MachinePipeliner::runOnMachineFunction(), selectCopy(), selectSubregisterCopy(), llvm::setDirectAddressInInstr(), shrinkScalarCompare(), llvm::LiveDebugVariables::splitRegister(), false::Chain::str(), substPhysReg(), substVirtReg(), llvm::SystemZInstrInfo::SystemZInstrInfo(), tieOpsIfNeeded(), tryToFoldACImm(), llvm::AntiDepBreaker::UpdateDbgValue(), updateOperand(), and llvm::LegalizerHelper::widenScalar().

◆ setRegMask()

void llvm::MachineOperand::setRegMask ( const uint32_t RegMaskPtr)
inline

Sets value of register mask operand referencing Mask.

The operand does not take ownership of the memory referenced by Mask, it must remain valid for the lifetime of the operand. See CreateRegMask(). Any physreg with a 0 bit in the mask is clobbered by the instruction.

Definition at line 691 of file MachineOperand.h.

References assert(), and isRegMask().

◆ setSubReg()

void llvm::MachineOperand::setSubReg ( unsigned  subReg)
inline

◆ setTargetFlags()

void llvm::MachineOperand::setTargetFlags ( unsigned  F)
inline

◆ substPhysReg()

void MachineOperand::substPhysReg ( MCRegister  Reg,
const TargetRegisterInfo TRI 
)

substPhysReg - Substitute the current register with the physical register Reg, taking any existing SubReg into account.

For instance, substPhysReg(eax) will change reg1024:sub_8bit to al.

Definition at line 84 of file MachineOperand.cpp.

References assert(), getSubReg(), llvm::TargetRegisterInfo::getSubReg(), isDef(), llvm::MCRegister::isPhysical(), setIsUndef(), setReg(), and setSubReg().

Referenced by addSegmentsWithValNo(), getRegClassFromGRPhysReg(), llvm::MachineRegisterInfo::replaceRegWith(), setSubReg(), and llvm::LiveDebugVariables::splitRegister().

◆ substVirtReg()

void MachineOperand::substVirtReg ( Register  Reg,
unsigned  SubIdx,
const TargetRegisterInfo TRI 
)

substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.

Take any existing SubReg index into account, using TargetRegisterInfo to compose the subreg indices if necessary. Reg must be a virtual register, SubIdx can be 0.

Definition at line 74 of file MachineOperand.cpp.

References assert(), llvm::TargetRegisterInfo::composeSubRegIndices(), getSubReg(), llvm::Register::isVirtual(), setReg(), and setSubReg().

Referenced by setSubReg(), and updateOperand().

Friends And Related Function Documentation

◆ DenseMapInfo< MachineOperand >

friend struct DenseMapInfo< MachineOperand >
friend

Definition at line 934 of file MachineOperand.h.

◆ hash_value

hash_code hash_value ( const MachineOperand MO)
friend

MachineOperand hash_value overload.

Note that this includes the same information in the hash that isIdenticalTo uses for comparison. It is thus suited for use in hash tables which use that function for equality comparisons only. This must stay exactly in sync with isIdenticalTo above.

Referenced by llvm::DenseMapInfo< MachineOperand >::getHashValue(), llvm::operator<<(), and setPredicate().

◆ MachineInstr

friend class MachineInstr
friend

Definition at line 920 of file MachineOperand.h.

◆ MachineRegisterInfo

friend class MachineRegisterInfo
friend

Definition at line 921 of file MachineOperand.h.

Member Data Documentation

◆ BA

const BlockAddress* llvm::MachineOperand::BA

Definition at line 192 of file MachineOperand.h.

Referenced by CreateBA().

◆ CFIIndex

unsigned llvm::MachineOperand::CFIIndex

Definition at line 174 of file MachineOperand.h.

Referenced by CreateCFIIndex().

◆ CFP

const ConstantFP* llvm::MachineOperand::CFP

Definition at line 168 of file MachineOperand.h.

Referenced by CreateFPImm(), and setFPImm().

◆ CI

const ConstantInt* llvm::MachineOperand::CI

Definition at line 169 of file MachineOperand.h.

Referenced by CreateCImm(), and setCImm().

◆ GV

const GlobalValue* llvm::MachineOperand::GV

Definition at line 191 of file MachineOperand.h.

Referenced by ChangeToGA(), CreateGA(), and setPredicate().

◆ ImmVal

int64_t llvm::MachineOperand::ImmVal

Definition at line 170 of file MachineOperand.h.

Referenced by ChangeToImmediate(), and setPredicate().

◆ Index

int llvm::MachineOperand::Index

Definition at line 189 of file MachineOperand.h.

Referenced by clearParent(), getTargetIndexName(), and printSubRegIdx().

◆ IntrinsicID

Intrinsic::ID llvm::MachineOperand::IntrinsicID

Definition at line 175 of file MachineOperand.h.

Referenced by CreateIntrinsicID().

◆ MBB

MachineBasicBlock* llvm::MachineOperand::MBB

Definition at line 167 of file MachineOperand.h.

Referenced by setMBB().

◆ MD

const MDNode* llvm::MachineOperand::MD

Definition at line 172 of file MachineOperand.h.

Referenced by CreateMetadata(), and setMetadata().

◆ Next

MachineOperand* llvm::MachineOperand::Next

Definition at line 182 of file MachineOperand.h.

◆ OffsetedInfo

struct { ... } llvm::MachineOperand::OffsetedInfo

OffsetedInfo - This struct contains the offset and an object identifier.

this represent the object as with an optional offset from it.

Referenced by CreateBA(), CreateES(), and CreateGA().

◆ OffsetHi

int llvm::MachineOperand::OffsetHi

Definition at line 195 of file MachineOperand.h.

◆ OffsetLo

unsigned llvm::MachineOperand::OffsetLo

Definition at line 158 of file MachineOperand.h.

◆ Pred

unsigned llvm::MachineOperand::Pred

Definition at line 176 of file MachineOperand.h.

Referenced by CreatePredicate(), and print().

◆ Prev

MachineOperand* llvm::MachineOperand::Prev

Definition at line 181 of file MachineOperand.h.

◆ Reg

struct { ... } llvm::MachineOperand::Reg

◆ RegMask

const uint32_t* llvm::MachineOperand::RegMask

Definition at line 171 of file MachineOperand.h.

Referenced by CreateRegLiveOut(), CreateRegMask(), isIdenticalTo(), and print().

◆ RegNo

unsigned llvm::MachineOperand::RegNo

Definition at line 157 of file MachineOperand.h.

Referenced by CreateReg().

◆ ShuffleMask

const Constant* llvm::MachineOperand::ShuffleMask

Definition at line 177 of file MachineOperand.h.

Referenced by CreateShuffleMask().

◆ Sym

MCSymbol* llvm::MachineOperand::Sym

Definition at line 173 of file MachineOperand.h.

Referenced by ChangeToMCSymbol(), clearParent(), and CreateMCSymbol().

◆ SymbolName

const char* llvm::MachineOperand::SymbolName

Definition at line 190 of file MachineOperand.h.

◆ Val

union { ... } llvm::MachineOperand::Val

The documentation for this class was generated from the following files: