LLVM  14.0.0git
SIFormMemoryClauses.cpp
Go to the documentation of this file.
1 //===-- SIFormMemoryClauses.cpp -------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This pass extends the live ranges of registers used as pointers in
10 /// sequences of adjacent SMEM and VMEM instructions if XNACK is enabled. A
11 /// load that would overwrite a pointer would require breaking the soft clause.
12 /// Artificially extend the live ranges of the pointer operands by adding
13 /// implicit-def early-clobber operands throughout the soft clause.
14 ///
15 //===----------------------------------------------------------------------===//
16 
17 #include "AMDGPU.h"
18 #include "GCNRegPressure.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/InitializePasses.h"
21 
22 using namespace llvm;
23 
24 #define DEBUG_TYPE "si-form-memory-clauses"
25 
26 // Clauses longer then 15 instructions would overflow one of the counters
27 // and stall. They can stall even earlier if there are outstanding counters.
28 static cl::opt<unsigned>
29 MaxClause("amdgpu-max-memory-clause", cl::Hidden, cl::init(15),
30  cl::desc("Maximum length of a memory clause, instructions"));
31 
32 namespace {
33 
34 class SIFormMemoryClauses : public MachineFunctionPass {
36 
37 public:
38  static char ID;
39 
40 public:
41  SIFormMemoryClauses() : MachineFunctionPass(ID) {
43  }
44 
45  bool runOnMachineFunction(MachineFunction &MF) override;
46 
47  StringRef getPassName() const override {
48  return "SI Form memory clauses";
49  }
50 
51  void getAnalysisUsage(AnalysisUsage &AU) const override {
53  AU.setPreservesAll();
55  }
56 
57  MachineFunctionProperties getClearedProperties() const override {
60  }
61 
62 private:
63  bool canBundle(const MachineInstr &MI, const RegUse &Defs,
64  const RegUse &Uses) const;
65  bool checkPressure(const MachineInstr &MI, GCNDownwardRPTracker &RPT);
66  void collectRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses) const;
67  bool processRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses,
69 
70  const GCNSubtarget *ST;
71  const SIRegisterInfo *TRI;
72  const MachineRegisterInfo *MRI;
74 
75  unsigned LastRecordedOccupancy;
76  unsigned MaxVGPRs;
77  unsigned MaxSGPRs;
78 };
79 
80 } // End anonymous namespace.
81 
82 INITIALIZE_PASS_BEGIN(SIFormMemoryClauses, DEBUG_TYPE,
83  "SI Form memory clauses", false, false)
85 INITIALIZE_PASS_END(SIFormMemoryClauses, DEBUG_TYPE,
86  "SI Form memory clauses", false, false)
87 
88 
89 char SIFormMemoryClauses::ID = 0;
90 
91 char &llvm::SIFormMemoryClausesID = SIFormMemoryClauses::ID;
92 
94  return new SIFormMemoryClauses();
95 }
96 
97 static bool isVMEMClauseInst(const MachineInstr &MI) {
99 }
100 
101 static bool isSMEMClauseInst(const MachineInstr &MI) {
102  return SIInstrInfo::isSMRD(MI);
103 }
104 
105 // There no sense to create store clauses, they do not define anything,
106 // thus there is nothing to set early-clobber.
107 static bool isValidClauseInst(const MachineInstr &MI, bool IsVMEMClause) {
108  assert(!MI.isDebugInstr() && "debug instructions should not reach here");
109  if (MI.isBundled())
110  return false;
111  if (!MI.mayLoad() || MI.mayStore())
112  return false;
114  return false;
115  if (IsVMEMClause && !isVMEMClauseInst(MI))
116  return false;
117  if (!IsVMEMClause && !isSMEMClauseInst(MI))
118  return false;
119  // If this is a load instruction where the result has been coalesced with an operand, then we cannot clause it.
120  for (const MachineOperand &ResMO : MI.defs()) {
121  Register ResReg = ResMO.getReg();
122  for (const MachineOperand &MO : MI.uses()) {
123  if (!MO.isReg() || MO.isDef())
124  continue;
125  if (MO.getReg() == ResReg)
126  return false;
127  }
128  break; // Only check the first def.
129  }
130  return true;
131 }
132 
133 static unsigned getMopState(const MachineOperand &MO) {
134  unsigned S = 0;
135  if (MO.isImplicit())
137  if (MO.isDead())
138  S |= RegState::Dead;
139  if (MO.isUndef())
140  S |= RegState::Undef;
141  if (MO.isKill())
142  S |= RegState::Kill;
143  if (MO.isEarlyClobber())
145  if (MO.getReg().isPhysical() && MO.isRenamable())
147  return S;
148 }
149 
150 // Returns false if there is a use of a def already in the map.
151 // In this case we must break the clause.
152 bool SIFormMemoryClauses::canBundle(const MachineInstr &MI, const RegUse &Defs,
153  const RegUse &Uses) const {
154  // Check interference with defs.
155  for (const MachineOperand &MO : MI.operands()) {
156  // TODO: Prologue/Epilogue Insertion pass does not process bundled
157  // instructions.
158  if (MO.isFI())
159  return false;
160 
161  if (!MO.isReg())
162  continue;
163 
164  Register Reg = MO.getReg();
165 
166  // If it is tied we will need to write same register as we read.
167  if (MO.isTied())
168  return false;
169 
170  const RegUse &Map = MO.isDef() ? Uses : Defs;
171  auto Conflict = Map.find(Reg);
172  if (Conflict == Map.end())
173  continue;
174 
175  if (Reg.isPhysical())
176  return false;
177 
178  LaneBitmask Mask = TRI->getSubRegIndexLaneMask(MO.getSubReg());
179  if ((Conflict->second.second & Mask).any())
180  return false;
181  }
182 
183  return true;
184 }
185 
186 // Since all defs in the clause are early clobber we can run out of registers.
187 // Function returns false if pressure would hit the limit if instruction is
188 // bundled into a memory clause.
189 bool SIFormMemoryClauses::checkPressure(const MachineInstr &MI,
190  GCNDownwardRPTracker &RPT) {
191  // NB: skip advanceBeforeNext() call. Since all defs will be marked
192  // early-clobber they will all stay alive at least to the end of the
193  // clause. Therefor we should not decrease pressure even if load
194  // pointer becomes dead and could otherwise be reused for destination.
195  RPT.advanceToNext();
196  GCNRegPressure MaxPressure = RPT.moveMaxPressure();
197  unsigned Occupancy = MaxPressure.getOccupancy(*ST);
198 
199  // Don't push over half the register budget. We don't want to introduce
200  // spilling just to form a soft clause.
201  //
202  // FIXME: This pressure check is fundamentally broken. First, this is checking
203  // the global pressure, not the pressure at this specific point in the
204  // program. Second, it's not accounting for the increased liveness of the use
205  // operands due to the early clobber we will introduce. Third, the pressure
206  // tracking does not account for the alignment requirements for SGPRs, or the
207  // fragmentation of registers the allocator will need to satisfy.
208  if (Occupancy >= MFI->getMinAllowedOccupancy() &&
209  MaxPressure.getVGPRNum(ST->hasGFX90AInsts()) <= MaxVGPRs / 2 &&
210  MaxPressure.getSGPRNum() <= MaxSGPRs / 2) {
211  LastRecordedOccupancy = Occupancy;
212  return true;
213  }
214  return false;
215 }
216 
217 // Collect register defs and uses along with their lane masks and states.
218 void SIFormMemoryClauses::collectRegUses(const MachineInstr &MI,
219  RegUse &Defs, RegUse &Uses) const {
220  for (const MachineOperand &MO : MI.operands()) {
221  if (!MO.isReg())
222  continue;
223  Register Reg = MO.getReg();
224  if (!Reg)
225  continue;
226 
227  LaneBitmask Mask = Reg.isVirtual()
228  ? TRI->getSubRegIndexLaneMask(MO.getSubReg())
230  RegUse &Map = MO.isDef() ? Defs : Uses;
231 
232  auto Loc = Map.find(Reg);
233  unsigned State = getMopState(MO);
234  if (Loc == Map.end()) {
235  Map[Reg] = std::make_pair(State, Mask);
236  } else {
237  Loc->second.first |= State;
238  Loc->second.second |= Mask;
239  }
240  }
241 }
242 
243 // Check register def/use conflicts, occupancy limits and collect def/use maps.
244 // Return true if instruction can be bundled with previous. It it cannot
245 // def/use maps are not updated.
246 bool SIFormMemoryClauses::processRegUses(const MachineInstr &MI,
247  RegUse &Defs, RegUse &Uses,
248  GCNDownwardRPTracker &RPT) {
249  if (!canBundle(MI, Defs, Uses))
250  return false;
251 
252  if (!checkPressure(MI, RPT))
253  return false;
254 
255  collectRegUses(MI, Defs, Uses);
256  return true;
257 }
258 
259 bool SIFormMemoryClauses::runOnMachineFunction(MachineFunction &MF) {
260  if (skipFunction(MF.getFunction()))
261  return false;
262 
263  ST = &MF.getSubtarget<GCNSubtarget>();
264  if (!ST->isXNACKEnabled())
265  return false;
266 
267  const SIInstrInfo *TII = ST->getInstrInfo();
268  TRI = ST->getRegisterInfo();
269  MRI = &MF.getRegInfo();
270  MFI = MF.getInfo<SIMachineFunctionInfo>();
271  LiveIntervals *LIS = &getAnalysis<LiveIntervals>();
272  SlotIndexes *Ind = LIS->getSlotIndexes();
273  bool Changed = false;
274 
275  MaxVGPRs = TRI->getAllocatableSet(MF, &AMDGPU::VGPR_32RegClass).count();
276  MaxSGPRs = TRI->getAllocatableSet(MF, &AMDGPU::SGPR_32RegClass).count();
277  unsigned FuncMaxClause = AMDGPU::getIntegerAttribute(
278  MF.getFunction(), "amdgpu-max-memory-clause", MaxClause);
279 
280  for (MachineBasicBlock &MBB : MF) {
281  GCNDownwardRPTracker RPT(*LIS);
283  for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; I = Next) {
284  MachineInstr &MI = *I;
285  Next = std::next(I);
286 
287  if (MI.isMetaInstruction())
288  continue;
289 
290  bool IsVMEM = isVMEMClauseInst(MI);
291 
292  if (!isValidClauseInst(MI, IsVMEM))
293  continue;
294 
295  if (!RPT.getNext().isValid())
296  RPT.reset(MI);
297  else { // Advance the state to the current MI.
299  RPT.advanceBeforeNext();
300  }
301 
302  const GCNRPTracker::LiveRegSet LiveRegsCopy(RPT.getLiveRegs());
303  RegUse Defs, Uses;
304  if (!processRegUses(MI, Defs, Uses, RPT)) {
305  RPT.reset(MI, &LiveRegsCopy);
306  continue;
307  }
308 
309  MachineBasicBlock::iterator LastClauseInst = Next;
310  unsigned Length = 1;
311  for ( ; Next != E && Length < FuncMaxClause; ++Next) {
312  // Debug instructions should not change the kill insertion.
313  if (Next->isMetaInstruction())
314  continue;
315 
316  if (!isValidClauseInst(*Next, IsVMEM))
317  break;
318 
319  // A load from pointer which was loaded inside the same bundle is an
320  // impossible clause because we will need to write and read the same
321  // register inside. In this case processRegUses will return false.
322  if (!processRegUses(*Next, Defs, Uses, RPT))
323  break;
324 
325  LastClauseInst = Next;
326  ++Length;
327  }
328  if (Length < 2) {
329  RPT.reset(MI, &LiveRegsCopy);
330  continue;
331  }
332 
333  Changed = true;
334  MFI->limitOccupancy(LastRecordedOccupancy);
335 
336  assert(!LastClauseInst->isMetaInstruction());
337 
338  SlotIndex ClauseLiveInIdx = LIS->getInstructionIndex(MI);
339  SlotIndex ClauseLiveOutIdx =
340  LIS->getInstructionIndex(*LastClauseInst).getNextIndex();
341 
342  // Track the last inserted kill.
344 
345  // Insert one kill per register, with operands covering all necessary
346  // subregisters.
347  for (auto &&R : Uses) {
348  Register Reg = R.first;
349  if (Reg.isPhysical())
350  continue;
351 
352  // Collect the register operands we should extend the live ranges of.
354  const LiveInterval &LI = LIS->getInterval(R.first);
355 
356  if (!LI.hasSubRanges()) {
357  if (!LI.liveAt(ClauseLiveOutIdx)) {
358  KillOps.emplace_back(R.second.first | RegState::Kill,
359  AMDGPU::NoSubRegister);
360  }
361  } else {
362  LaneBitmask KilledMask;
363  for (const LiveInterval::SubRange &SR : LI.subranges()) {
364  if (SR.liveAt(ClauseLiveInIdx) && !SR.liveAt(ClauseLiveOutIdx))
365  KilledMask |= SR.LaneMask;
366  }
367 
368  if (KilledMask.none())
369  continue;
370 
371  SmallVector<unsigned> KilledIndexes;
373  *MRI, MRI->getRegClass(Reg), KilledMask, KilledIndexes);
374  (void)Success;
375  assert(Success && "Failed to find subregister mask to cover lanes");
376  for (unsigned SubReg : KilledIndexes) {
377  KillOps.emplace_back(R.second.first | RegState::Kill, SubReg);
378  }
379  }
380 
381  if (KillOps.empty())
382  continue;
383 
384  // We only want to extend the live ranges of used registers. If they
385  // already have existing uses beyond the bundle, we don't need the kill.
386  //
387  // It's possible all of the use registers were already live past the
388  // bundle.
389  Kill = BuildMI(*MI.getParent(), std::next(LastClauseInst),
390  DebugLoc(), TII->get(AMDGPU::KILL));
391  for (auto &Op : KillOps)
392  Kill.addUse(Reg, std::get<0>(Op), std::get<1>(Op));
394  }
395 
396  if (!Kill) {
397  RPT.reset(MI, &LiveRegsCopy);
398  continue;
399  }
400 
401  // Restore the state after processing the end of the bundle.
402  RPT.reset(*Kill, &LiveRegsCopy);
403 
404  for (auto &&R : Defs) {
405  Register Reg = R.first;
406  Uses.erase(Reg);
407  if (Reg.isPhysical())
408  continue;
409  LIS->removeInterval(Reg);
410  LIS->createAndComputeVirtRegInterval(Reg);
411  }
412 
413  for (auto &&R : Uses) {
414  Register Reg = R.first;
415  if (Reg.isPhysical())
416  continue;
417  LIS->removeInterval(Reg);
418  LIS->createAndComputeVirtRegInterval(Reg);
419  }
420  }
421  }
422 
423  return Changed;
424 }
llvm::LaneBitmask
Definition: LaneBitmask.h:40
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(SIFormMemoryClauses, DEBUG_TYPE, "SI Form memory clauses", false, false) INITIALIZE_PASS_END(SIFormMemoryClauses
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::GCNRegPressure
Definition: GCNRegPressure.h:30
Reg
unsigned Reg
Definition: MachineSink.cpp:1558
llvm::GCNRPTracker::getLiveRegs
const decltype(LiveRegs) & getLiveRegs() const
Definition: GCNRegPressure.h:125
SIMachineFunctionInfo.h
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::dwarf::Form
Form
Definition: Dwarf.h:131
llvm::TargetRegisterInfo::getAllocatableSet
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not.
Definition: TargetRegisterInfo.cpp:255
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::MachineFunctionProperties::Property::IsSSA
@ IsSSA
llvm::MachineFunctionProperties
Properties which a MachineFunction may have at a given point in time.
Definition: MachineFunction.h:111
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:207
llvm::GCNDownwardRPTracker
Definition: GCNRegPressure.h:161
Uses
SmallPtrSet< MachineInstr *, 2 > Uses
Definition: ARMLowOverheadLoops.cpp:589
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:390
llvm::GCNRPTracker::moveMaxPressure
decltype(MaxPressure) moveMaxPressure()
Definition: GCNRegPressure.h:131
llvm::Register::isPhysical
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
llvm::MachineOperand::isRenamable
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
Definition: MachineOperand.cpp:118
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:644
isVMEMClauseInst
static bool isVMEMClauseInst(const MachineInstr &MI)
Definition: SIFormMemoryClauses.cpp:97
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:380
llvm::LiveRange::liveAt
bool liveAt(SlotIndex index) const
Definition: LiveInterval.h:393
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::msgpack::Type::Map
@ Map
llvm::TargetRegisterInfo::getSubRegIndexLaneMask
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
Definition: TargetRegisterInfo.h:377
llvm::GCNRegPressure::getSGPRNum
unsigned getSGPRNum() const
Definition: GCNRegPressure.h:49
llvm::GCNDownwardRPTracker::advanceBeforeNext
bool advanceBeforeNext()
Definition: GCNRegPressure.cpp:355
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:732
llvm::MachineInstrBundleIterator::isValid
bool isValid() const
Check for null.
Definition: MachineInstrBundleIterator.h:182
llvm::BitVector::count
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:154
llvm::GCNRegPressure::getOccupancy
unsigned getOccupancy(const GCNSubtarget &ST) const
Definition: GCNRegPressure.h:63
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
false
Definition: StackSlotColoring.cpp:142
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineFunctionProperties::set
MachineFunctionProperties & set(Property P)
Definition: MachineFunction.h:173
llvm::SlotIndexes
SlotIndexes pass.
Definition: SlotIndexes.h:314
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:30
llvm::LiveInterval
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:680
llvm::SlotIndex
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:83
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
llvm::SlotIndexes::insertMachineInstrInMaps
SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late=false)
Insert the given machine instruction into the mapping.
Definition: SlotIndexes.h:535
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::GCNDownwardRPTracker::advance
bool advance()
Definition: GCNRegPressure.cpp:410
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:634
llvm::cl::opt
Definition: CommandLine.h:1432
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:395
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::RegState::EarlyClobber
@ EarlyClobber
Register definition happens before uses.
Definition: MachineInstrBuilder.h:54
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
llvm::AMDGPU::getIntegerAttribute
int getIntegerAttribute(const Function &F, StringRef Name, int Default)
Definition: AMDGPUBaseInfo.cpp:854
llvm::DenseMap
Definition: DenseMap.h:714
llvm::MachineOperand::isDead
bool isDead() const
Definition: MachineOperand.h:385
llvm::SIInstrInfo::isSMRD
static bool isSMRD(const MachineInstr &MI)
Definition: SIInstrInfo.h:478
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
llvm::SIFormMemoryClausesID
char & SIFormMemoryClausesID
Definition: SIFormMemoryClauses.cpp:91
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::GCNDownwardRPTracker::reset
bool reset(const MachineInstr &MI, const LiveRegSet *LiveRegs=nullptr)
Definition: GCNRegPressure.cpp:342
llvm::MachineOperand::isEarlyClobber
bool isEarlyClobber() const
Definition: MachineOperand.h:436
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::SIInstrInfo::isAtomic
static bool isAtomic(const MachineInstr &MI)
Definition: SIInstrInfo.h:575
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::MachineBasicBlock::instr_begin
instr_iterator instr_begin()
Definition: MachineBasicBlock.h:252
llvm::MachineBasicBlock::instr_end
instr_iterator instr_end()
Definition: MachineBasicBlock.h:254
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::createSIFormMemoryClausesPass
FunctionPass * createSIFormMemoryClausesPass()
Definition: SIFormMemoryClauses.cpp:93
getMopState
static unsigned getMopState(const MachineOperand &MO)
Definition: SIFormMemoryClauses.cpp:133
llvm::initializeSIFormMemoryClausesPass
void initializeSIFormMemoryClausesPass(PassRegistry &)
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
AMDGPU.h
llvm::LaneBitmask::none
constexpr bool none() const
Definition: LaneBitmask.h:52
llvm::TargetRegisterInfo::getCoveringSubRegIndexes
bool getCoveringSubRegIndexes(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, LaneBitmask LaneMask, SmallVectorImpl< unsigned > &Indexes) const
Try to find one or more subregister indexes to cover LaneMask.
Definition: TargetRegisterInfo.cpp:523
llvm::SlotIndex::getNextIndex
SlotIndex getNextIndex() const
Returns the next index.
Definition: SlotIndexes.h:279
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
MaxClause
static cl::opt< unsigned > MaxClause("amdgpu-max-memory-clause", cl::Hidden, cl::init(15), cl::desc("Maximum length of a memory clause, instructions"))
llvm::LiveInterval::SubRange
A live range for subregisters.
Definition: LiveInterval.h:687
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::GCNDownwardRPTracker::getNext
MachineBasicBlock::const_iterator getNext() const
Definition: GCNRegPressure.h:170
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:52
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:600
llvm::AnalysisUsage::setPreservesAll
void setPreservesAll()
Set by analyses that do not transform their input at all.
Definition: PassAnalysisSupport.h:130
llvm::GCNRegPressure::getVGPRNum
unsigned getVGPRNum(bool UnifiedVGPRFile) const
Definition: GCNRegPressure.h:50
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
Success
#define Success
Definition: AArch64Disassembler.cpp:260
llvm::SIInstrInfo::isVMEM
static bool isVMEM(const MachineInstr &MI)
Definition: SIInstrInfo.h:366
GCNRegPressure.h
llvm::RegState::Renamable
@ Renamable
Register that may be renamed.
Definition: MachineInstrBuilder.h:61
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::GCNDownwardRPTracker::advanceToNext
void advanceToNext()
Definition: GCNRegPressure.cpp:390
llvm::SIInstrInfo
Definition: SIInstrInfo.h:38
DEBUG_TYPE
#define DEBUG_TYPE
Definition: SIFormMemoryClauses.cpp:24
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::SIMachineFunctionInfo
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:335
llvm::LiveInterval::hasSubRanges
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:797
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
llvm::AnalysisUsage::addRequired
AnalysisUsage & addRequired()
Definition: PassAnalysisSupport.h:75
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::SIInstrInfo::isFLAT
static bool isFLAT(const MachineInstr &MI)
Definition: SIInstrInfo.h:514
clauses
SI Form memory clauses
Definition: SIFormMemoryClauses.cpp:86
llvm::cl::desc
Definition: CommandLine.h:412
llvm::MachineInstrBundleIterator< const MachineInstr >
isValidClauseInst
static bool isValidClauseInst(const MachineInstr &MI, bool IsVMEMClause)
Definition: SIFormMemoryClauses.cpp:107
InitializePasses.h
llvm::RegState::Dead
@ Dead
Unused definition.
Definition: MachineInstrBuilder.h:50
isSMEMClauseInst
static bool isSMEMClauseInst(const MachineInstr &MI)
Definition: SIFormMemoryClauses.cpp:101
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::LaneBitmask::getAll
static constexpr LaneBitmask getAll()
Definition: LaneBitmask.h:84
llvm::SmallVectorImpl::emplace_back
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:908
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::LiveInterval::subranges
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:769