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14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
17 #define GET_REGINFO_HEADER
18 #include "AMDGPUGenRegisterInfo.inc"
28 struct SGPRSpillBuilder;
42 static std::array<std::vector<int16_t>, 16> RegSplitParts;
47 static std::array<std::array<uint16_t, 32>, 9> SubRegFromChannelTable;
70 return SpillSGPRToVGPR;
113 int Idx)
const override;
118 int64_t
Offset)
const override;
121 int64_t
Offset)
const override;
124 int64_t
Offset)
const override;
137 bool IsLoad,
bool IsKill =
true)
const;
142 bool OnlyToVGPR =
false)
const;
146 bool OnlyToVGPR =
false)
const;
157 unsigned FIOperandNum,
169 return getEncodingValue(
Reg) & 0xff;
256 unsigned SubIdx)
const;
261 unsigned SrcSubReg)
const override;
275 bool ReserveHighestVGPR =
false)
const;
294 unsigned EltSize)
const;
308 unsigned Idx)
const override;
327 return isWave32 ? &AMDGPU::SReg_32RegClass
328 : &AMDGPU::SReg_64RegClass;
332 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass
333 : &AMDGPU::SReg_64_XEXECRegClass;
370 return SubReg ? (getSubRegIdxOffset(
SubReg) + 31) / 32 : 0;
410 bool ValueIsKill,
MCRegister ScratchOffsetReg,
const LLVM_READONLY TargetRegisterClass * getVGPRClassForBitWidth(unsigned BitWidth) const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
const TargetRegisterClass * getEquivalentVGPRClass(const TargetRegisterClass *SRC) const
static bool isAGPRClass(const TargetRegisterClass *RC)
This is an optimization pass for GlobalISel generic memory operations.
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
const TargetRegisterClass * getRegClass(unsigned RCID) const
bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
ArrayRef< MCPhysReg > getAllSGPR128(const MachineFunction &MF) const
Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget.
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
const int * getRegUnitPressureSets(unsigned RegUnit) const override
int64_t getScratchInstrOffset(const MachineInstr *MI) const
ArrayRef< MCPhysReg > getAllSGPR64(const MachineFunction &MF) const
Return all SGPR64 which satisfy the waves per execution unit requirement of the subtarget.
Reg
All possible values of the reg field in the ModR/M byte.
static bool hasSGPRs(const TargetRegisterClass *RC)
bool isSGPRClassID(unsigned RCID) const
A set of physical registers with utility functions to track liveness when walking backward/forward th...
SIRegisterInfo(const GCNSubtarget &ST)
const LLVM_READONLY TargetRegisterClass * getVectorSuperClassForBitWidth(unsigned BitWidth) const
unsigned getCSRFirstUseCost() const override
const TargetRegisterClass * getWaveMaskRegClass() const
MCRegister getExec() const
A description of a memory reference used in the backend.
const TargetRegisterClass * getRegClassForSizeOnBank(unsigned Size, const RegisterBank &Bank) const
const TargetRegisterClass * getEquivalentAGPRClass(const TargetRegisterClass *SRC) const
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
bool spillSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr, bool OnlyToVGPR=false) const
If OnlyToVGPR is true, this will only succeed if this.
const uint32_t * getAllAllocatableSRegMask() const
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
const TargetRegisterClass * getProperlyAlignedRC(const TargetRegisterClass *RC) const
bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const override
void buildVGPRSpillLoadStore(SGPRSpillBuilder &SB, int Index, int Offset, bool IsLoad, bool IsKill=true) const
MachineInstr * findReachingDef(Register Reg, unsigned SubReg, MachineInstr &Use, MachineRegisterInfo &MRI, LiveIntervals *LIS) const
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
Returns a legal register class to copy a register in the specified class to or from.
Register getFrameRegister(const MachineFunction &MF) const override
This class implements the register bank concept.
int popcount(T Value) noexcept
Count the number of set bits in a value.
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
MCRegister getReturnAddressReg(const MachineFunction &MF) const
const TargetRegisterClass * getRegClassForReg(const MachineRegisterInfo &MRI, Register Reg) const
bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const
unsigned getHWRegIndex(MCRegister Reg) const
unsigned getChannelFromSubReg(unsigned SubReg) const
MachineOperand class - Representation of each machine instruction operand.
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
bool supportsBackwardScavenger() const override
unsigned getNumChannelsFromSubReg(unsigned SubReg) const
static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs=1)
static bool isSGPRClass(const TargetRegisterClass *RC)
static bool hasVGPRs(const TargetRegisterClass *RC)
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
MCRegister getVCC() const
const TargetRegisterClass * getVGPR64Class() const
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
bool eliminateSGPRToVGPRSpillFrameIndex(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr) const
Special case of eliminateFrameIndex.
bool isDivergentRegClass(const TargetRegisterClass *RC) const override
bool opCanUseLiteralConstant(unsigned OpType) const
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
Register getBaseRegister() const
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
const uint32_t * getAllVGPRRegMask() const
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
bool shouldRealignStack(const MachineFunction &MF) const override
Representation of each machine instruction.
StringRef getRegAsmName(MCRegister Reg) const override
const uint8_t TSFlags
Configurable target specific flags.
static bool isVGPRClass(const TargetRegisterClass *RC)
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
bool hasBasePointer(const MachineFunction &MF) const
const uint32_t * getAllVectorRegMask() const
bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const
bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const
const TargetRegisterClass * getBoolRC() const
const TargetRegisterClass * getRegClassForOperandReg(const MachineRegisterInfo &MRI, const MachineOperand &MO) const
bool restoreSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr, bool OnlyToVGPR=false) const
ArrayRef< int16_t > getRegSplitParts(const TargetRegisterClass *RC, unsigned EltSize) const
const uint32_t * getAllAGPRRegMask() const
bool isVSSuperClass(const TargetRegisterClass *RC) const
const uint32_t * getNoPreservedMask() const override
MCPhysReg get32BitRegister(MCPhysReg Reg) const
static bool hasVectorRegisters(const TargetRegisterClass *RC)
bool isVectorSuperClass(const TargetRegisterClass *RC) const
static unsigned getNumCoveredRegs(LaneBitmask LM)
StringRef - Represent a constant reference to a string, i.e.
bool isProperlyAlignedRC(const TargetRegisterClass &RC) const
bool spillSGPRToVGPR() const
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
constexpr Type getAsInteger() const
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
SpilledReg(Register R, int L)
void buildSpillLoadStore(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned LoadStoreOp, int Index, Register ValueReg, bool ValueIsKill, MCRegister ScratchOffsetReg, int64_t InstrOffset, MachineMemOperand *MMO, RegScavenger *RS, LivePhysRegs *LiveRegs=nullptr) const
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override
ArrayRef< MCPhysReg > getAllSGPR32(const MachineFunction &MF) const
Return all SGPR32 which satisfy the waves per execution unit requirement of the subtarget.
const TargetRegisterClass * getRegClassForTypeOnBank(LLT Ty, const RegisterBank &Bank) const
constexpr unsigned BitWidth
bool requiresRegisterScavenging(const MachineFunction &Fn) const override
const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const override
MCRegister findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF, bool ReserveHighestVGPR=false) const
Returns a lowest register that is not used at any point in the function.
const TargetRegisterClass * getCompatibleSubRegClass(const TargetRegisterClass *SuperRC, const TargetRegisterClass *SubRC, unsigned SubIdx) const
Returns a register class which is compatible with SuperRC, such that a subregister exists with class ...
const LLVM_READONLY TargetRegisterClass * getAGPRClassForBitWidth(unsigned BitWidth) const
bool opCanUseInlineConstant(unsigned OpType) const
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
bool isVectorRegister(const MachineRegisterInfo &MRI, Register Reg) const
bool spillEmergencySGPR(MachineBasicBlock::iterator MI, MachineBasicBlock &RestoreMBB, Register SGPR, RegScavenger *RS) const
const TargetRegisterClass * getEquivalentSGPRClass(const TargetRegisterClass *VRC) const
MCRegister reservedPrivateSegmentBufferReg(const MachineFunction &MF) const
Return the end register initially reserved for the scratch buffer in case spilling is needed.
BitVector getReservedRegs(const MachineFunction &MF) const override
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
A Use represents the edge between a Value definition and its users.
static bool hasAGPRs(const TargetRegisterClass *RC)
Wrapper class representing physical registers. Should be passed by value.
static const LLVM_READONLY TargetRegisterClass * getSGPRClassForBitWidth(unsigned BitWidth)