LLVM 18.0.0git
SIRegisterInfo.h
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1//===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Interface definition for SIRegisterInfo
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
15#define LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
16
17#define GET_REGINFO_HEADER
18#include "AMDGPUGenRegisterInfo.inc"
19
20#include "SIDefines.h"
21
22namespace llvm {
23
24class GCNSubtarget;
25class LiveIntervals;
26class LiveRegUnits;
27class RegisterBank;
28struct SGPRSpillBuilder;
29
31private:
32 const GCNSubtarget &ST;
33 bool SpillSGPRToVGPR;
34 bool isWave32;
35 BitVector RegPressureIgnoredUnits;
36
37 /// Sub reg indexes for getRegSplitParts.
38 /// First index represents subreg size from 1 to 16 DWORDs.
39 /// The inner vector is sorted by bit offset.
40 /// Provided a register can be fully split with given subregs,
41 /// all elements of the inner vector combined give a full lane mask.
42 static std::array<std::vector<int16_t>, 16> RegSplitParts;
43
44 // Table representing sub reg of given width and offset.
45 // First index is subreg size: 32, 64, 96, 128, 160, 192, 224, 256, 512.
46 // Second index is 32 different dword offsets.
47 static std::array<std::array<uint16_t, 32>, 9> SubRegFromChannelTable;
48
49 void reserveRegisterTuples(BitVector &, MCRegister Reg) const;
50
51public:
53
54 struct SpilledReg {
56 int Lane = -1;
57
58 SpilledReg() = default;
59 SpilledReg(Register R, int L) : VGPR(R), Lane(L) {}
60
61 bool hasLane() { return Lane != -1; }
62 bool hasReg() { return VGPR != 0; }
63 };
64
65 /// \returns the sub reg enum value for the given \p Channel
66 /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)
67 static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs = 1);
68
69 bool spillSGPRToVGPR() const {
70 return SpillSGPRToVGPR;
71 }
72
73 /// Return the largest available SGPR aligned to \p Align for the register
74 /// class \p RC.
76 const unsigned Align,
77 const TargetRegisterClass *RC) const;
78
79 /// Return the end register initially reserved for the scratch buffer in case
80 /// spilling is needed.
82
83 BitVector getReservedRegs(const MachineFunction &MF) const override;
84 bool isAsmClobberable(const MachineFunction &MF,
85 MCRegister PhysReg) const override;
86
87 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
90 CallingConv::ID) const override;
91 const uint32_t *getNoPreservedMask() const override;
92
93 // Stack access is very expensive. CSRs are also the high registers, and we
94 // want to minimize the number of used registers.
95 unsigned getCSRFirstUseCost() const override {
96 return 100;
97 }
98
101 const MachineFunction &MF) const override;
102
103 Register getFrameRegister(const MachineFunction &MF) const override;
104
105 bool hasBasePointer(const MachineFunction &MF) const;
107
108 bool shouldRealignStack(const MachineFunction &MF) const override;
109 bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
110
111 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
113 const MachineFunction &MF) const override;
114 bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override;
115
116 int64_t getScratchInstrOffset(const MachineInstr *MI) const;
117
119 int Idx) const override;
120
121 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
122
124 int64_t Offset) const override;
125
127 int64_t Offset) const override;
128
129 bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
130 int64_t Offset) const override;
131
133 const MachineFunction &MF, unsigned Kind = 0) const override;
134
135 /// Returns a legal register class to copy a register in the specified class
136 /// to or from. If it is possible to copy the register directly without using
137 /// a cross register class copy, return the specified RC. Returns NULL if it
138 /// is not possible to copy between two registers of the specified class.
139 const TargetRegisterClass *
140 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
141
143 bool IsLoad, bool IsKill = true) const;
144
145 /// If \p OnlyToVGPR is true, this will only succeed if this manages to find a
146 /// free VGPR lane to spill.
148 SlotIndexes *Indexes = nullptr, LiveIntervals *LIS = nullptr,
149 bool OnlyToVGPR = false,
150 bool SpillToPhysVGPRLane = false) const;
151
153 SlotIndexes *Indexes = nullptr, LiveIntervals *LIS = nullptr,
154 bool OnlyToVGPR = false,
155 bool SpillToPhysVGPRLane = false) const;
156
158 MachineBasicBlock &RestoreMBB, Register SGPR,
159 RegScavenger *RS) const;
160
162 unsigned FIOperandNum,
163 RegScavenger *RS) const override;
164
167 SlotIndexes *Indexes = nullptr, LiveIntervals *LIS = nullptr,
168 bool SpillToPhysVGPRLane = false) const;
169
170 StringRef getRegAsmName(MCRegister Reg) const override;
171
172 // Pseudo regs are not allowed
173 unsigned getHWRegIndex(MCRegister Reg) const {
174 return getEncodingValue(Reg) & 0xff;
175 }
176
179
182
184 const TargetRegisterClass *
186
189
190 /// \returns true if this class contains only SGPR registers
191 static bool isSGPRClass(const TargetRegisterClass *RC) {
192 return hasSGPRs(RC) && !hasVGPRs(RC) && !hasAGPRs(RC);
193 }
194
195 /// \returns true if this class ID contains only SGPR registers
196 bool isSGPRClassID(unsigned RCID) const {
197 return isSGPRClass(getRegClass(RCID));
198 }
199
200 bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const;
201
202 /// \returns true if this class contains only VGPR registers
203 static bool isVGPRClass(const TargetRegisterClass *RC) {
204 return hasVGPRs(RC) && !hasAGPRs(RC) && !hasSGPRs(RC);
205 }
206
207 /// \returns true if this class contains only AGPR registers
208 static bool isAGPRClass(const TargetRegisterClass *RC) {
209 return hasAGPRs(RC) && !hasVGPRs(RC) && !hasSGPRs(RC);
210 }
211
212 /// \returns true only if this class contains both VGPR and AGPR registers
214 return hasVGPRs(RC) && hasAGPRs(RC) && !hasSGPRs(RC);
215 }
216
217 /// \returns true only if this class contains both VGPR and SGPR registers
218 bool isVSSuperClass(const TargetRegisterClass *RC) const {
219 return hasVGPRs(RC) && hasSGPRs(RC) && !hasAGPRs(RC);
220 }
221
222 /// \returns true if this class contains VGPR registers.
223 static bool hasVGPRs(const TargetRegisterClass *RC) {
224 return RC->TSFlags & SIRCFlags::HasVGPR;
225 }
226
227 /// \returns true if this class contains AGPR registers.
228 static bool hasAGPRs(const TargetRegisterClass *RC) {
229 return RC->TSFlags & SIRCFlags::HasAGPR;
230 }
231
232 /// \returns true if this class contains SGPR registers.
233 static bool hasSGPRs(const TargetRegisterClass *RC) {
234 return RC->TSFlags & SIRCFlags::HasSGPR;
235 }
236
237 /// \returns true if this class contains any vector registers.
239 return hasVGPRs(RC) || hasAGPRs(RC);
240 }
241
242 /// \returns A VGPR reg class with the same width as \p SRC
243 const TargetRegisterClass *
245
246 /// \returns An AGPR reg class with the same width as \p SRC
247 const TargetRegisterClass *
249
250 /// \returns A SGPR reg class with the same width as \p SRC
251 const TargetRegisterClass *
253
254 /// Returns a register class which is compatible with \p SuperRC, such that a
255 /// subregister exists with class \p SubRC with subregister index \p
256 /// SubIdx. If this is impossible (e.g., an unaligned subregister index within
257 /// a register tuple), return null.
258 const TargetRegisterClass *
260 const TargetRegisterClass *SubRC,
261 unsigned SubIdx) const;
262
264 unsigned DefSubReg,
265 const TargetRegisterClass *SrcRC,
266 unsigned SrcSubReg) const override;
267
268 /// \returns True if operands defined with this operand type can accept
269 /// a literal constant (i.e. any 32-bit immediate).
270 bool opCanUseLiteralConstant(unsigned OpType) const;
271
272 /// \returns True if operands defined with this operand type can accept
273 /// an inline constant. i.e. An integer value in the range (-16, 64) or
274 /// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.
275 bool opCanUseInlineConstant(unsigned OpType) const;
276
278 const TargetRegisterClass *RC,
279 const MachineFunction &MF,
280 bool ReserveHighestVGPR = false) const;
281
283 Register Reg) const;
284 const TargetRegisterClass *
286 const MachineOperand &MO) const;
287
288 bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const;
289 bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const;
291 return isVGPR(MRI, Reg) || isAGPR(MRI, Reg);
292 }
293
294 // FIXME: SGPRs are assumed to be uniform, but this is not true for i1 SGPRs
295 // (such as VCC) which hold a wave-wide vector of boolean values. Examining
296 // just the register class is not suffcient; it needs to be combined with a
297 // value type. The next predicate isUniformReg() does this correctly.
298 bool isDivergentRegClass(const TargetRegisterClass *RC) const override {
299 return !isSGPRClass(RC);
300 }
301
303 Register Reg) const override;
304
306 unsigned EltSize) const;
307
309 const TargetRegisterClass *SrcRC,
310 unsigned SubReg,
311 const TargetRegisterClass *DstRC,
312 unsigned DstSubReg,
313 const TargetRegisterClass *NewRC,
314 LiveIntervals &LIS) const override;
315
316 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
317 MachineFunction &MF) const override;
318
319 unsigned getRegPressureSetLimit(const MachineFunction &MF,
320 unsigned Idx) const override;
321
322 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
323
325
326 const TargetRegisterClass *
327 getRegClassForSizeOnBank(unsigned Size, const RegisterBank &Bank) const;
328
329 const TargetRegisterClass *
331 return getRegClassForSizeOnBank(Ty.getSizeInBits(), Bank);
332 }
333
334 const TargetRegisterClass *
336 const MachineRegisterInfo &MRI) const override;
337
339 return isWave32 ? &AMDGPU::SReg_32RegClass
340 : &AMDGPU::SReg_64RegClass;
341 }
342
344 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass
345 : &AMDGPU::SReg_64_XEXECRegClass;
346 }
347
348 // Return the appropriate register class to use for 64-bit VGPRs for the
349 // subtarget.
350 const TargetRegisterClass *getVGPR64Class() const;
351
352 MCRegister getVCC() const;
353
354 MCRegister getExec() const;
355
356 const TargetRegisterClass *getRegClass(unsigned RCID) const;
357
358 // Find reaching register definition
362 LiveIntervals *LIS) const;
363
364 const uint32_t *getAllVGPRRegMask() const;
365 const uint32_t *getAllAGPRRegMask() const;
366 const uint32_t *getAllVectorRegMask() const;
367 const uint32_t *getAllAllocatableSRegMask() const;
368
369 // \returns number of 32 bit registers covered by a \p LM
370 static unsigned getNumCoveredRegs(LaneBitmask LM) {
371 // The assumption is that every lo16 subreg is an even bit and every hi16
372 // is an adjacent odd bit or vice versa.
373 uint64_t Mask = LM.getAsInteger();
374 uint64_t Even = Mask & 0xAAAAAAAAAAAAAAAAULL;
375 Mask = (Even >> 1) | Mask;
376 uint64_t Odd = Mask & 0x5555555555555555ULL;
377 return llvm::popcount(Odd);
378 }
379
380 // \returns a DWORD offset of a \p SubReg
381 unsigned getChannelFromSubReg(unsigned SubReg) const {
382 return SubReg ? (getSubRegIdxOffset(SubReg) + 31) / 32 : 0;
383 }
384
385 // \returns a DWORD size of a \p SubReg
386 unsigned getNumChannelsFromSubReg(unsigned SubReg) const {
387 return getNumCoveredRegs(getSubRegIndexLaneMask(SubReg));
388 }
389
390 // For a given 16 bit \p Reg \returns a 32 bit register holding it.
391 // \returns \p Reg otherwise.
393
394 // Returns true if a given register class is properly aligned for
395 // the subtarget.
396 bool isProperlyAlignedRC(const TargetRegisterClass &RC) const;
397
398 // Given \p RC returns corresponding aligned register class if required
399 // by the subtarget.
400 const TargetRegisterClass *
402
403 /// Return all SGPR128 which satisfy the waves per execution unit requirement
404 /// of the subtarget.
406
407 /// Return all SGPR64 which satisfy the waves per execution unit requirement
408 /// of the subtarget.
410
411 /// Return all SGPR32 which satisfy the waves per execution unit requirement
412 /// of the subtarget.
414
415 // Insert spill or restore instructions.
416 // When lowering spill pseudos, the RegScavenger should be set.
417 // For creating spill instructions during frame lowering, where no scavenger
418 // is available, LiveUnits can be used.
421 unsigned LoadStoreOp, int Index, Register ValueReg,
422 bool ValueIsKill, MCRegister ScratchOffsetReg,
423 int64_t InstrOffset, MachineMemOperand *MMO,
424 RegScavenger *RS,
425 LiveRegUnits *LiveUnits = nullptr) const;
426
427 // Return alignment in register file of first register in a register tuple.
429 return (RC->TSFlags & SIRCFlags::RegTupleAlignUnitsMask) * 32;
430 }
431
432 // Check if register class RC has required alignment.
434 unsigned AlignNumBits) const {
435 assert(AlignNumBits != 0);
436 unsigned RCAlign = getRegClassAlignmentNumBits(RC);
437 return RCAlign == AlignNumBits ||
438 (RCAlign > AlignNumBits && (RCAlign % AlignNumBits) == 0);
439 }
440
441 // Return alignment of a SubReg relative to start of a register in RC class.
442 // No check if the subreg is supported by the current RC is made.
444 unsigned SubReg) const;
445};
446
447namespace AMDGPU {
448/// Get the size in bits of a register from the register class \p RC.
449unsigned getRegBitWidth(const TargetRegisterClass &RC);
450} // namespace AMDGPU
451
452} // End namespace llvm
453
454#endif
unsigned SubReg
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
#define LLVM_READONLY
Definition: Compiler.h:208
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
uint64_t Size
IRTranslator LLVM IR MI
unsigned Reg
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A debug info location.
Definition: DebugLoc.h:33
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelType.h:175
A set of register units used to track register liveness.
Definition: LiveRegUnits.h:30
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Representation of each machine instruction.
Definition: MachineInstr.h:68
A description of a memory reference used in the backend.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Holds all the information related to register banks.
This class implements the register bank concept.
Definition: RegisterBank.h:28
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
int64_t getScratchInstrOffset(const MachineInstr *MI) const
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
const TargetRegisterClass * getRegClass(unsigned RCID) const
const TargetRegisterClass * getCompatibleSubRegClass(const TargetRegisterClass *SuperRC, const TargetRegisterClass *SubRC, unsigned SubIdx) const
Returns a register class which is compatible with SuperRC, such that a subregister exists with class ...
ArrayRef< MCPhysReg > getAllSGPR64(const MachineFunction &MF) const
Return all SGPR64 which satisfy the waves per execution unit requirement of the subtarget.
MCRegister findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF, bool ReserveHighestVGPR=false) const
Returns a lowest register that is not used at any point in the function.
static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs=1)
static unsigned getNumCoveredRegs(LaneBitmask LM)
MCPhysReg get32BitRegister(MCPhysReg Reg) const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const override
const TargetRegisterClass * getProperlyAlignedRC(const TargetRegisterClass *RC) const
bool shouldRealignStack(const MachineFunction &MF) const override
bool restoreSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr, bool OnlyToVGPR=false, bool SpillToPhysVGPRLane=false) const
bool isProperlyAlignedRC(const TargetRegisterClass &RC) const
static bool hasVectorRegisters(const TargetRegisterClass *RC)
const TargetRegisterClass * getEquivalentVGPRClass(const TargetRegisterClass *SRC) const
Register getFrameRegister(const MachineFunction &MF) const override
LLVM_READONLY const TargetRegisterClass * getVectorSuperClassForBitWidth(unsigned BitWidth) const
bool spillEmergencySGPR(MachineBasicBlock::iterator MI, MachineBasicBlock &RestoreMBB, Register SGPR, RegScavenger *RS) const
const uint32_t * getAllVGPRRegMask() const
MCRegister getReturnAddressReg(const MachineFunction &MF) const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
bool hasBasePointer(const MachineFunction &MF) const
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
Returns a legal register class to copy a register in the specified class to or from.
ArrayRef< int16_t > getRegSplitParts(const TargetRegisterClass *RC, unsigned EltSize) const
ArrayRef< MCPhysReg > getAllSGPR32(const MachineFunction &MF) const
Return all SGPR32 which satisfy the waves per execution unit requirement of the subtarget.
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
MCRegister reservedPrivateSegmentBufferReg(const MachineFunction &MF) const
Return the end register initially reserved for the scratch buffer in case spilling is needed.
bool eliminateSGPRToVGPRSpillFrameIndex(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr, bool SpillToPhysVGPRLane=false) const
Special case of eliminateFrameIndex.
bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const
void buildSpillLoadStore(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned LoadStoreOp, int Index, Register ValueReg, bool ValueIsKill, MCRegister ScratchOffsetReg, int64_t InstrOffset, MachineMemOperand *MMO, RegScavenger *RS, LiveRegUnits *LiveUnits=nullptr) const
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
LLVM_READONLY const TargetRegisterClass * getAGPRClassForBitWidth(unsigned BitWidth) const
bool requiresRegisterScavenging(const MachineFunction &Fn) const override
bool opCanUseInlineConstant(unsigned OpType) const
const TargetRegisterClass * getRegClassForSizeOnBank(unsigned Size, const RegisterBank &Bank) const
const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const override
bool isUniformReg(const MachineRegisterInfo &MRI, const RegisterBankInfo &RBI, Register Reg) const override
const uint32_t * getNoPreservedMask() const override
StringRef getRegAsmName(MCRegister Reg) const override
const uint32_t * getAllAllocatableSRegMask() const
bool isVectorRegister(const MachineRegisterInfo &MRI, Register Reg) const
MCRegister getAlignedHighSGPRForRC(const MachineFunction &MF, const unsigned Align, const TargetRegisterClass *RC) const
Return the largest available SGPR aligned to Align for the register class RC.
const TargetRegisterClass * getRegClassForReg(const MachineRegisterInfo &MRI, Register Reg) const
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
const uint32_t * getAllVectorRegMask() const
const TargetRegisterClass * getEquivalentAGPRClass(const TargetRegisterClass *SRC) const
static LLVM_READONLY const TargetRegisterClass * getSGPRClassForBitWidth(unsigned BitWidth)
const TargetRegisterClass * getRegClassForTypeOnBank(LLT Ty, const RegisterBank &Bank) const
bool opCanUseLiteralConstant(unsigned OpType) const
Register getBaseRegister() const
LLVM_READONLY const TargetRegisterClass * getVGPRClassForBitWidth(unsigned BitWidth) const
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
static bool hasVGPRs(const TargetRegisterClass *RC)
static bool isVGPRClass(const TargetRegisterClass *RC)
unsigned getHWRegIndex(MCRegister Reg) const
MachineInstr * findReachingDef(Register Reg, unsigned SubReg, MachineInstr &Use, MachineRegisterInfo &MRI, LiveIntervals *LIS) const
bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const
const TargetRegisterClass * getEquivalentSGPRClass(const TargetRegisterClass *VRC) const
unsigned getNumChannelsFromSubReg(unsigned SubReg) const
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
ArrayRef< MCPhysReg > getAllSGPR128(const MachineFunction &MF) const
Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget.
unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override
unsigned getCSRFirstUseCost() const override
BitVector getReservedRegs(const MachineFunction &MF) const override
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
const TargetRegisterClass * getRegClassForOperandReg(const MachineRegisterInfo &MRI, const MachineOperand &MO) const
bool isSGPRClassID(unsigned RCID) const
const uint32_t * getAllAGPRRegMask() const
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
bool isDivergentRegClass(const TargetRegisterClass *RC) const override
const TargetRegisterClass * getBoolRC() const
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
bool isVSSuperClass(const TargetRegisterClass *RC) const
bool spillSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr, bool OnlyToVGPR=false, bool SpillToPhysVGPRLane=false) const
If OnlyToVGPR is true, this will only succeed if this manages to find a free VGPR lane to spill.
unsigned getChannelFromSubReg(unsigned SubReg) const
MCRegister getExec() const
MCRegister getVCC() const
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
bool isVectorSuperClass(const TargetRegisterClass *RC) const
bool isRegClassAligned(const TargetRegisterClass *RC, unsigned AlignNumBits) const
static bool hasAGPRs(const TargetRegisterClass *RC)
const TargetRegisterClass * getWaveMaskRegClass() const
unsigned getSubRegAlignmentNumBits(const TargetRegisterClass *RC, unsigned SubReg) const
static bool hasSGPRs(const TargetRegisterClass *RC)
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override
bool spillSGPRToVGPR() const
const TargetRegisterClass * getVGPR64Class() const
void buildVGPRSpillLoadStore(SGPRSpillBuilder &SB, int Index, int Offset, bool IsLoad, bool IsKill=true) const
unsigned getRegClassAlignmentNumBits(const TargetRegisterClass *RC) const
static bool isSGPRClass(const TargetRegisterClass *RC)
static bool isAGPRClass(const TargetRegisterClass *RC)
const int * getRegUnitPressureSets(unsigned RegUnit) const override
SlotIndexes pass.
Definition: SlotIndexes.h:301
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
const uint8_t TSFlags
Configurable target specific flags.
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
unsigned getRegBitWidth(const TargetRegisterClass &RC)
Get the size in bits of a register from the register class RC.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:440
int popcount(T Value) noexcept
Count the number of set bits in a value.
Definition: bit.h:349
@ HasSGPR
Definition: SIDefines.h:26
@ RegTupleAlignUnitsMask
Definition: SIDefines.h:28
@ HasVGPR
Definition: SIDefines.h:24
@ HasAGPR
Definition: SIDefines.h:25
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:184
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
constexpr Type getAsInteger() const
Definition: LaneBitmask.h:74