LLVM  15.0.0git
SIRegisterInfo.h
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1 //===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Interface definition for SIRegisterInfo
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
16 
17 #define GET_REGINFO_HEADER
18 #include "AMDGPUGenRegisterInfo.inc"
19 
20 #include "SIDefines.h"
21 
22 namespace llvm {
23 
24 class GCNSubtarget;
25 class LiveIntervals;
26 class LivePhysRegs;
27 class RegisterBank;
28 struct SGPRSpillBuilder;
29 
30 class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
31 private:
32  const GCNSubtarget &ST;
33  bool SpillSGPRToVGPR;
34  bool isWave32;
35  BitVector RegPressureIgnoredUnits;
36 
37  /// Sub reg indexes for getRegSplitParts.
38  /// First index represents subreg size from 1 to 16 DWORDs.
39  /// The inner vector is sorted by bit offset.
40  /// Provided a register can be fully split with given subregs,
41  /// all elements of the inner vector combined give a full lane mask.
42  static std::array<std::vector<int16_t>, 16> RegSplitParts;
43 
44  // Table representing sub reg of given width and offset.
45  // First index is subreg size: 32, 64, 96, 128, 160, 192, 224, 256, 512.
46  // Second index is 32 different dword offsets.
47  static std::array<std::array<uint16_t, 32>, 9> SubRegFromChannelTable;
48 
49  void reserveRegisterTuples(BitVector &, MCRegister Reg) const;
50 
51 public:
52  SIRegisterInfo(const GCNSubtarget &ST);
53 
54  struct SpilledReg {
56  int Lane = -1;
57 
58  SpilledReg() = default;
59  SpilledReg(Register R, int L) : VGPR(R), Lane(L) {}
60 
61  bool hasLane() { return Lane != -1; }
62  bool hasReg() { return VGPR != 0; }
63  };
64 
65  /// \returns the sub reg enum value for the given \p Channel
66  /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)
67  static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs = 1);
68 
69  bool spillSGPRToVGPR() const {
70  return SpillSGPRToVGPR;
71  }
72 
73  /// Return the end register initially reserved for the scratch buffer in case
74  /// spilling is needed.
76 
77  BitVector getReservedRegs(const MachineFunction &MF) const override;
78  bool isAsmClobberable(const MachineFunction &MF,
79  MCRegister PhysReg) const override;
80 
81  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
82  const MCPhysReg *getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
84  CallingConv::ID) const override;
85  const uint32_t *getNoPreservedMask() const override;
86 
87  // Stack access is very expensive. CSRs are also the high registers, and we
88  // want to minimize the number of used registers.
89  unsigned getCSRFirstUseCost() const override {
90  return 100;
91  }
92 
93  const TargetRegisterClass *
95  const MachineFunction &MF) const override;
96 
97  Register getFrameRegister(const MachineFunction &MF) const override;
98 
99  bool hasBasePointer(const MachineFunction &MF) const;
100  Register getBaseRegister() const;
101 
102  bool shouldRealignStack(const MachineFunction &MF) const override;
103  bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
104 
105  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
107  const MachineFunction &MF) const override;
108  bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override;
109 
110  int64_t getScratchInstrOffset(const MachineInstr *MI) const;
111 
113  int Idx) const override;
114 
115  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
116 
118  int64_t Offset) const override;
119 
120  void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
121  int64_t Offset) const override;
122 
123  bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
124  int64_t Offset) const override;
125 
127  const MachineFunction &MF, unsigned Kind = 0) const override;
128 
129  /// Returns a legal register class to copy a register in the specified class
130  /// to or from. If it is possible to copy the register directly without using
131  /// a cross register class copy, return the specified RC. Returns NULL if it
132  /// is not possible to copy between two registers of the specified class.
133  const TargetRegisterClass *
134  getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
135 
136  void buildVGPRSpillLoadStore(SGPRSpillBuilder &SB, int Index, int Offset,
137  bool IsLoad, bool IsKill = true) const;
138 
139  /// If \p OnlyToVGPR is true, this will only succeed if this
141  int FI, RegScavenger *RS,
142  LiveIntervals *LIS = nullptr,
143  bool OnlyToVGPR = false) const;
144 
146  int FI, RegScavenger *RS,
147  LiveIntervals *LIS = nullptr,
148  bool OnlyToVGPR = false) const;
149 
151  MachineBasicBlock &RestoreMBB, Register SGPR,
152  RegScavenger *RS) const;
153 
155  unsigned FIOperandNum,
156  RegScavenger *RS) const override;
157 
159  int FI, RegScavenger *RS,
160  LiveIntervals *LIS = nullptr) const;
161 
162  StringRef getRegAsmName(MCRegister Reg) const override;
163 
164  // Pseudo regs are not allowed
165  unsigned getHWRegIndex(MCRegister Reg) const {
166  return getEncodingValue(Reg) & 0xff;
167  }
168 
171 
174 
176  const TargetRegisterClass *
178 
180  static const TargetRegisterClass *getSGPRClassForBitWidth(unsigned BitWidth);
181 
182  /// Return the 'base' register class for this register.
183  /// e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.
185 
186  /// \returns true if this class contains only SGPR registers
187  static bool isSGPRClass(const TargetRegisterClass *RC) {
188  return hasSGPRs(RC) && !hasVGPRs(RC) && !hasAGPRs(RC);
189  }
190 
191  /// \returns true if this class ID contains only SGPR registers
192  bool isSGPRClassID(unsigned RCID) const {
193  return isSGPRClass(getRegClass(RCID));
194  }
195 
196  bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const;
197 
198  /// \returns true if this class contains only VGPR registers
199  static bool isVGPRClass(const TargetRegisterClass *RC) {
200  return hasVGPRs(RC) && !hasAGPRs(RC) && !hasSGPRs(RC);
201  }
202 
203  /// \returns true if this class contains only AGPR registers
204  static bool isAGPRClass(const TargetRegisterClass *RC) {
205  return hasAGPRs(RC) && !hasVGPRs(RC) && !hasSGPRs(RC);
206  }
207 
208  /// \returns true only if this class contains both VGPR and AGPR registers
209  bool isVectorSuperClass(const TargetRegisterClass *RC) const {
210  return hasVGPRs(RC) && hasAGPRs(RC) && !hasSGPRs(RC);
211  }
212 
213  /// \returns true only if this class contains both VGPR and SGPR registers
214  bool isVSSuperClass(const TargetRegisterClass *RC) const {
215  return hasVGPRs(RC) && hasSGPRs(RC) && !hasAGPRs(RC);
216  }
217 
218  /// \returns true if this class contains VGPR registers.
219  static bool hasVGPRs(const TargetRegisterClass *RC) {
220  return RC->TSFlags & SIRCFlags::HasVGPR;
221  }
222 
223  /// \returns true if this class contains AGPR registers.
224  static bool hasAGPRs(const TargetRegisterClass *RC) {
225  return RC->TSFlags & SIRCFlags::HasAGPR;
226  }
227 
228  /// \returns true if this class contains SGPR registers.
229  static bool hasSGPRs(const TargetRegisterClass *RC) {
230  return RC->TSFlags & SIRCFlags::HasSGPR;
231  }
232 
233  /// \returns true if this class contains any vector registers.
234  static bool hasVectorRegisters(const TargetRegisterClass *RC) {
235  return hasVGPRs(RC) || hasAGPRs(RC);
236  }
237 
238  /// \returns A VGPR reg class with the same width as \p SRC
239  const TargetRegisterClass *
241 
242  /// \returns An AGPR reg class with the same width as \p SRC
243  const TargetRegisterClass *
245 
246  /// \returns A SGPR reg class with the same width as \p SRC
247  const TargetRegisterClass *
249 
250  /// \returns The canonical register class that is used for a sub-register of
251  /// \p RC for the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC
252  /// will be returned.
254  unsigned SubIdx) const;
255 
256  /// Returns a register class which is compatible with \p SuperRC, such that a
257  /// subregister exists with class \p SubRC with subregister index \p
258  /// SubIdx. If this is impossible (e.g., an unaligned subregister index within
259  /// a register tuple), return null.
260  const TargetRegisterClass *
262  const TargetRegisterClass *SubRC,
263  unsigned SubIdx) const;
264 
265  bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
266  unsigned DefSubReg,
267  const TargetRegisterClass *SrcRC,
268  unsigned SrcSubReg) const override;
269 
270  /// \returns True if operands defined with this operand type can accept
271  /// a literal constant (i.e. any 32-bit immediate).
272  bool opCanUseLiteralConstant(unsigned OpType) const;
273 
274  /// \returns True if operands defined with this operand type can accept
275  /// an inline constant. i.e. An integer value in the range (-16, 64) or
276  /// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.
277  bool opCanUseInlineConstant(unsigned OpType) const;
278 
280  const TargetRegisterClass *RC,
281  const MachineFunction &MF,
282  bool ReserveHighestVGPR = false) const;
283 
285  Register Reg) const;
286  bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const;
287  bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const;
289  return isVGPR(MRI, Reg) || isAGPR(MRI, Reg);
290  }
291 
292  bool isConstantPhysReg(MCRegister PhysReg) const override;
293 
294  bool isDivergentRegClass(const TargetRegisterClass *RC) const override {
295  return !isSGPRClass(RC);
296  }
297 
299  unsigned EltSize) const;
300 
302  const TargetRegisterClass *SrcRC,
303  unsigned SubReg,
304  const TargetRegisterClass *DstRC,
305  unsigned DstSubReg,
306  const TargetRegisterClass *NewRC,
307  LiveIntervals &LIS) const override;
308 
309  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
310  MachineFunction &MF) const override;
311 
312  unsigned getRegPressureSetLimit(const MachineFunction &MF,
313  unsigned Idx) const override;
314 
315  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
316 
318 
319  const TargetRegisterClass *
320  getRegClassForSizeOnBank(unsigned Size, const RegisterBank &Bank) const;
321 
322  const TargetRegisterClass *
323  getRegClassForTypeOnBank(LLT Ty, const RegisterBank &Bank) const {
324  return getRegClassForSizeOnBank(Ty.getSizeInBits(), Bank);
325  }
326 
327  const TargetRegisterClass *
329  const MachineRegisterInfo &MRI) const override;
330 
332  return isWave32 ? &AMDGPU::SReg_32RegClass
333  : &AMDGPU::SReg_64RegClass;
334  }
335 
337  return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass
338  : &AMDGPU::SReg_64_XEXECRegClass;
339  }
340 
341  // Return the appropriate register class to use for 64-bit VGPRs for the
342  // subtarget.
343  const TargetRegisterClass *getVGPR64Class() const;
344 
345  MCRegister getVCC() const;
346 
347  const TargetRegisterClass *getRegClass(unsigned RCID) const;
348 
349  // Find reaching register definition
351  MachineInstr &Use,
353  LiveIntervals *LIS) const;
354 
355  const uint32_t *getAllVGPRRegMask() const;
356  const uint32_t *getAllAGPRRegMask() const;
357  const uint32_t *getAllVectorRegMask() const;
358  const uint32_t *getAllAllocatableSRegMask() const;
359 
360  // \returns number of 32 bit registers covered by a \p LM
361  static unsigned getNumCoveredRegs(LaneBitmask LM) {
362  // The assumption is that every lo16 subreg is an even bit and every hi16
363  // is an adjacent odd bit or vice versa.
364  uint64_t Mask = LM.getAsInteger();
365  uint64_t Even = Mask & 0xAAAAAAAAAAAAAAAAULL;
366  Mask = (Even >> 1) | Mask;
367  uint64_t Odd = Mask & 0x5555555555555555ULL;
368  return countPopulation(Odd);
369  }
370 
371  // \returns a DWORD offset of a \p SubReg
372  unsigned getChannelFromSubReg(unsigned SubReg) const {
373  return SubReg ? (getSubRegIdxOffset(SubReg) + 31) / 32 : 0;
374  }
375 
376  // \returns a DWORD size of a \p SubReg
377  unsigned getNumChannelsFromSubReg(unsigned SubReg) const {
378  return getNumCoveredRegs(getSubRegIndexLaneMask(SubReg));
379  }
380 
381  // For a given 16 bit \p Reg \returns a 32 bit register holding it.
382  // \returns \p Reg otherwise.
384 
385  // Returns true if a given register class is properly aligned for
386  // the subtarget.
387  bool isProperlyAlignedRC(const TargetRegisterClass &RC) const;
388 
389  // Given \p RC returns corresponding aligned register class if required
390  // by the subtarget.
391  const TargetRegisterClass *
392  getProperlyAlignedRC(const TargetRegisterClass *RC) const;
393 
394  /// Return all SGPR128 which satisfy the waves per execution unit requirement
395  /// of the subtarget.
397 
398  /// Return all SGPR64 which satisfy the waves per execution unit requirement
399  /// of the subtarget.
401 
402  /// Return all SGPR32 which satisfy the waves per execution unit requirement
403  /// of the subtarget.
405 
406  // Insert spill or restore instructions.
407  // When lowering spill pseudos, the RegScavenger should be set.
408  // For creating spill instructions during frame lowering, where no scavenger
409  // is available, LiveRegs can be used.
412  unsigned LoadStoreOp, int Index, Register ValueReg,
413  bool ValueIsKill, MCRegister ScratchOffsetReg,
414  int64_t InstrOffset, MachineMemOperand *MMO,
415  RegScavenger *RS,
416  LivePhysRegs *LiveRegs = nullptr) const;
417 };
418 
419 } // End namespace llvm
420 
421 #endif
llvm::LaneBitmask
Definition: LaneBitmask.h:40
llvm::SIRegisterInfo::getVGPRClassForBitWidth
const LLVM_READONLY TargetRegisterClass * getVGPRClassForBitWidth(unsigned BitWidth) const
Definition: SIRegisterInfo.cpp:2444
llvm::SIRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Definition: SIRegisterInfo.cpp:390
llvm::SIRegisterInfo::getEquivalentVGPRClass
const TargetRegisterClass * getEquivalentVGPRClass(const TargetRegisterClass *SRC) const
Definition: SIRegisterInfo.cpp:2682
llvm::SIRegisterInfo::isAGPRClass
static bool isAGPRClass(const TargetRegisterClass *RC)
Definition: SIRegisterInfo.h:204
LLVM_READONLY
#define LLVM_READONLY
Definition: Compiler.h:206
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::SIRegisterInfo::isConstantPhysReg
bool isConstantPhysReg(MCRegister PhysReg) const override
Definition: SIRegisterInfo.cpp:3063
llvm::SIRegisterInfo::needsFrameBaseReg
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
Definition: SIRegisterInfo.cpp:792
llvm::SIRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned RCID) const
Definition: SIRegisterInfo.cpp:2943
llvm::SIRegisterInfo::requiresVirtualBaseRegisters
bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override
Definition: SIRegisterInfo.cpp:764
llvm::SIRegisterInfo::restoreSGPR
bool restoreSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, LiveIntervals *LIS=nullptr, bool OnlyToVGPR=false) const
Definition: SIRegisterInfo.cpp:1788
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::SIRegisterInfo::getAllSGPR128
ArrayRef< MCPhysReg > getAllSGPR128(const MachineFunction &MF) const
Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget.
Definition: SIRegisterInfo.cpp:3078
llvm::SIRegisterInfo::getFrameIndexInstrOffset
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
Definition: SIRegisterInfo.cpp:778
llvm::SIRegisterInfo::getRegUnitPressureSets
const int * getRegUnitPressureSets(unsigned RegUnit) const override
Definition: SIRegisterInfo.cpp:2886
llvm::SIRegisterInfo::getScratchInstrOffset
int64_t getScratchInstrOffset(const MachineInstr *MI) const
Definition: SIRegisterInfo.cpp:770
llvm::SIRegisterInfo::getAllSGPR64
ArrayRef< MCPhysReg > getAllSGPR64(const MachineFunction &MF) const
Return all SGPR64 which satisfy the waves per execution unit requirement of the subtarget.
Definition: SIRegisterInfo.cpp:3084
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::SIRegisterInfo::hasSGPRs
static bool hasSGPRs(const TargetRegisterClass *RC)
Definition: SIRegisterInfo.h:229
llvm::SIRegisterInfo::SpilledReg
Definition: SIRegisterInfo.h:54
llvm::SIRegisterInfo::isSGPRClassID
bool isSGPRClassID(unsigned RCID) const
Definition: SIRegisterInfo.h:192
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:50
llvm::SIRegisterInfo::SIRegisterInfo
SIRegisterInfo(const GCNSubtarget &ST)
Definition: SIRegisterInfo.cpp:319
llvm::SIRegisterInfo::getVectorSuperClassForBitWidth
const LLVM_READONLY TargetRegisterClass * getVectorSuperClassForBitWidth(unsigned BitWidth) const
Definition: SIRegisterInfo.cpp:2562
llvm::SIRegisterInfo::getCSRFirstUseCost
unsigned getCSRFirstUseCost() const override
Definition: SIRegisterInfo.h:89
llvm::SIRegisterInfo::getWaveMaskRegClass
const TargetRegisterClass * getWaveMaskRegClass() const
Definition: SIRegisterInfo.h:336
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::SIRegisterInfo::getRegClassForSizeOnBank
const TargetRegisterClass * getRegClassForSizeOnBank(unsigned Size, const RegisterBank &Bank) const
Definition: SIRegisterInfo.cpp:2901
llvm::SIRegisterInfo::getEquivalentAGPRClass
const TargetRegisterClass * getEquivalentAGPRClass(const TargetRegisterClass *SRC) const
Definition: SIRegisterInfo.cpp:2690
llvm::SIRegisterInfo::materializeFrameBaseRegister
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
Definition: SIRegisterInfo.cpp:806
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::SIRegisterInfo::getAllAllocatableSRegMask
const uint32_t * getAllAllocatableSRegMask() const
Definition: SIRegisterInfo.cpp:525
llvm::SIRegisterInfo::isAsmClobberable
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
Definition: SIRegisterInfo.cpp:720
llvm::SIRegisterInfo::getProperlyAlignedRC
const TargetRegisterClass * getProperlyAlignedRC(const TargetRegisterClass *RC) const
Definition: SIRegisterInfo.cpp:3045
llvm::SIRegisterInfo::requiresFrameIndexReplacementScavenging
bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:758
llvm::SIRegisterInfo::getSubRegClass
const TargetRegisterClass * getSubRegClass(const TargetRegisterClass *RC, unsigned SubIdx) const
Definition: SIRegisterInfo.cpp:2707
llvm::SIRegisterInfo::buildVGPRSpillLoadStore
void buildVGPRSpillLoadStore(SGPRSpillBuilder &SB, int Index, int Offset, bool IsLoad, bool IsKill=true) const
Definition: SIRegisterInfo.cpp:1636
llvm::SIRegisterInfo::findReachingDef
MachineInstr * findReachingDef(Register Reg, unsigned SubReg, MachineInstr &Use, MachineRegisterInfo &MRI, LiveIntervals *LIS) const
Definition: SIRegisterInfo.cpp:2958
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::SIRegisterInfo::getCrossCopyRegClass
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
Returns a legal register class to copy a register in the specified class to or from.
Definition: SIRegisterInfo.cpp:931
llvm::SIRegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:490
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::LLT::getSizeInBits
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:152
llvm::SIRegisterInfo::SpilledReg::hasReg
bool hasReg()
Definition: SIRegisterInfo.h:62
llvm::SIRegisterInfo::getLargestLegalSuperClass
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:436
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::SIRegisterInfo::getReturnAddressReg
MCRegister getReturnAddressReg(const MachineFunction &MF) const
Definition: SIRegisterInfo.cpp:2895
llvm::SIRegisterInfo::getRegClassForReg
const TargetRegisterClass * getRegClassForReg(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2812
llvm::SIRegisterInfo::isAGPR
bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2824
llvm::SIRegisterInfo::getHWRegIndex
unsigned getHWRegIndex(MCRegister Reg) const
Definition: SIRegisterInfo.h:165
llvm::SIRegisterInfo::getChannelFromSubReg
unsigned getChannelFromSubReg(unsigned SubReg) const
Definition: SIRegisterInfo.h:372
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::SIRegisterInfo::eliminateFrameIndex
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
Definition: SIRegisterInfo.cpp:1973
llvm::SIRegisterInfo::getRegPressureLimit
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:2853
llvm::SIRegisterInfo::SpilledReg::VGPR
Register VGPR
Definition: SIRegisterInfo.h:55
llvm::SIRegisterInfo::getNumChannelsFromSubReg
unsigned getNumChannelsFromSubReg(unsigned SubReg) const
Definition: SIRegisterInfo.h:377
llvm::SIRegisterInfo::getSubRegFromChannel
static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs=1)
Definition: SIRegisterInfo.cpp:529
llvm::SIRegisterInfo::isSGPRClass
static bool isSGPRClass(const TargetRegisterClass *RC)
Definition: SIRegisterInfo.h:187
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:30
llvm::SIRegisterInfo::hasVGPRs
static bool hasVGPRs(const TargetRegisterClass *RC)
Definition: SIRegisterInfo.h:219
llvm::SIRegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Definition: SIRegisterInfo.cpp:415
llvm::SIRegisterInfo::getVCC
MCRegister getVCC() const
Definition: SIRegisterInfo.cpp:2932
llvm::BitVector
Definition: BitVector.h:75
llvm::SIRegisterInfo::getVGPR64Class
const TargetRegisterClass * getVGPR64Class() const
Definition: SIRegisterInfo.cpp:2936
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::SIRegisterInfo::isDivergentRegClass
bool isDivergentRegClass(const TargetRegisterClass *RC) const override
Definition: SIRegisterInfo.h:294
llvm::SIRegisterInfo::opCanUseLiteralConstant
bool opCanUseLiteralConstant(unsigned OpType) const
Definition: SIRegisterInfo.cpp:2770
llvm::SIRegisterInfo::isFrameOffsetLegal
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
Definition: SIRegisterInfo.cpp:906
llvm::SIRegisterInfo::getBaseRegister
Register getBaseRegister() const
Definition: SIRegisterInfo.cpp:511
llvm::SIRegisterInfo::getAllVGPRRegMask
const uint32_t * getAllVGPRRegMask() const
Definition: SIRegisterInfo.cpp:513
llvm::countPopulation
unsigned countPopulation(T Value)
Count the number of set bits in a value.
Definition: MathExtras.h:567
llvm::SIRegisterInfo::SpilledReg::SpilledReg
SpilledReg()=default
llvm::SIRegisterInfo::shouldRewriteCopySrc
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
Definition: SIRegisterInfo.cpp:2746
llvm::SIRegisterInfo::shouldRealignStack
bool shouldRealignStack(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:725
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::SIRegisterInfo::getRegAsmName
StringRef getRegAsmName(MCRegister Reg) const override
Definition: SIRegisterInfo.cpp:2391
uint64_t
llvm::TargetRegisterClass::TSFlags
const uint8_t TSFlags
Configurable target specific flags.
Definition: TargetRegisterInfo.h:62
llvm::SIRegisterInfo::isVGPRClass
static bool isVGPRClass(const TargetRegisterClass *RC)
Definition: SIRegisterInfo.h:199
llvm::SIRegisterInfo::requiresFrameIndexScavenging
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:749
llvm::SIRegisterInfo::hasBasePointer
bool hasBasePointer(const MachineFunction &MF) const
Definition: SIRegisterInfo.cpp:504
llvm::SIRegisterInfo::getAllVectorRegMask
const uint32_t * getAllVectorRegMask() const
Definition: SIRegisterInfo.cpp:521
llvm::SIRegisterInfo::isSGPRReg
bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2671
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::SIRegisterInfo::isVGPR
bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2817
llvm::SIRegisterInfo::getBoolRC
const TargetRegisterClass * getBoolRC() const
Definition: SIRegisterInfo.h:331
llvm::SIRegisterInfo::SpilledReg::Lane
int Lane
Definition: SIRegisterInfo.h:56
llvm::SIRegisterInfo::getRegSplitParts
ArrayRef< int16_t > getRegSplitParts(const TargetRegisterClass *RC, unsigned EltSize) const
Definition: SIRegisterInfo.cpp:2796
llvm::HasVGPR
@ HasVGPR
Definition: SIDefines.h:20
llvm::HasSGPR
@ HasSGPR
Definition: SIDefines.h:22
llvm::SIRegisterInfo::getAllAGPRRegMask
const uint32_t * getAllAGPRRegMask() const
Definition: SIRegisterInfo.cpp:517
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::SIRegisterInfo::isVSSuperClass
bool isVSSuperClass(const TargetRegisterClass *RC) const
Definition: SIRegisterInfo.h:214
llvm::SIRegisterInfo::getNoPreservedMask
const uint32_t * getNoPreservedMask() const override
Definition: SIRegisterInfo.cpp:431
llvm::SIRegisterInfo::get32BitRegister
MCPhysReg get32BitRegister(MCPhysReg Reg) const
Definition: SIRegisterInfo.cpp:3012
llvm::SIRegisterInfo::hasVectorRegisters
static bool hasVectorRegisters(const TargetRegisterClass *RC)
Definition: SIRegisterInfo.h:234
llvm::ArrayRef< int16_t >
llvm::SIRegisterInfo::isVectorSuperClass
bool isVectorSuperClass(const TargetRegisterClass *RC) const
Definition: SIRegisterInfo.h:209
llvm::SIRegisterInfo::getNumCoveredRegs
static unsigned getNumCoveredRegs(LaneBitmask LM)
Definition: SIRegisterInfo.h:361
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::HasAGPR
@ HasAGPR
Definition: SIDefines.h:21
llvm::SIRegisterInfo::SpilledReg::hasLane
bool hasLane()
Definition: SIRegisterInfo.h:61
llvm::SIRegisterInfo::isProperlyAlignedRC
bool isProperlyAlignedRC(const TargetRegisterClass &RC) const
Definition: SIRegisterInfo.cpp:3029
llvm::SIRegisterInfo::spillSGPRToVGPR
bool spillSGPRToVGPR() const
Definition: SIRegisterInfo.h:69
uint32_t
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::LaneBitmask::getAsInteger
constexpr Type getAsInteger() const
Definition: LaneBitmask.h:74
llvm::SIRegisterInfo::getCalleeSavedRegsViaCopy
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
Definition: SIRegisterInfo.cpp:411
llvm::SIRegisterInfo::resolveFrameIndex
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
Definition: SIRegisterInfo.cpp:857
llvm::SIRegisterInfo::SpilledReg::SpilledReg
SpilledReg(Register R, int L)
Definition: SIRegisterInfo.h:59
llvm::SIRegisterInfo::buildSpillLoadStore
void buildSpillLoadStore(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned LoadStoreOp, int Index, Register ValueReg, bool ValueIsKill, MCRegister ScratchOffsetReg, int64_t InstrOffset, MachineMemOperand *MMO, RegScavenger *RS, LivePhysRegs *LiveRegs=nullptr) const
Definition: SIRegisterInfo.cpp:1270
llvm::SGPRSpillBuilder
Definition: SIRegisterInfo.cpp:72
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SIRegisterInfo::getRegPressureSetLimit
unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override
Definition: SIRegisterInfo.cpp:2872
llvm::SIRegisterInfo::getAllSGPR32
ArrayRef< MCPhysReg > getAllSGPR32(const MachineFunction &MF) const
Return all SGPR32 which satisfy the waves per execution unit requirement of the subtarget.
Definition: SIRegisterInfo.cpp:3090
llvm::SIRegisterInfo::getRegClassForTypeOnBank
const TargetRegisterClass * getRegClassForTypeOnBank(LLT Ty, const RegisterBank &Bank) const
Definition: SIRegisterInfo.h:323
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
uint16_t
llvm::SIRegisterInfo::eliminateSGPRToVGPRSpillFrameIndex
bool eliminateSGPRToVGPRSpillFrameIndex(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, LiveIntervals *LIS=nullptr) const
Special case of eliminateFrameIndex.
Definition: SIRegisterInfo.cpp:1940
SIDefines.h
AMDGPUGenRegisterInfo
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::SIRegisterInfo::spillSGPR
bool spillSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, LiveIntervals *LIS=nullptr, bool OnlyToVGPR=false) const
If OnlyToVGPR is true, this will only succeed if this.
Definition: SIRegisterInfo.cpp:1669
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::SIRegisterInfo::requiresRegisterScavenging
bool requiresRegisterScavenging(const MachineFunction &Fn) const override
Definition: SIRegisterInfo.cpp:738
llvm::SIRegisterInfo::getConstrainedRegClassForOperand
const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const override
Definition: SIRegisterInfo.cpp:2920
llvm::SIRegisterInfo::findUnusedRegister
MCRegister findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF, bool ReserveHighestVGPR=false) const
Returns a lowest register that is not used at any point in the function.
Definition: SIRegisterInfo.cpp:2780
llvm::SIRegisterInfo::getCompatibleSubRegClass
const TargetRegisterClass * getCompatibleSubRegClass(const TargetRegisterClass *SuperRC, const TargetRegisterClass *SubRC, unsigned SubIdx) const
Returns a register class which is compatible with SuperRC, such that a subregister exists with class ...
Definition: SIRegisterInfo.cpp:2728
llvm::SIRegisterInfo::getAGPRClassForBitWidth
const LLVM_READONLY TargetRegisterClass * getAGPRClassForBitWidth(unsigned BitWidth) const
Definition: SIRegisterInfo.cpp:2504
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::SIRegisterInfo::opCanUseInlineConstant
bool opCanUseInlineConstant(unsigned OpType) const
Definition: SIRegisterInfo.cpp:2737
llvm::SIRegisterInfo::shouldCoalesce
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
Definition: SIRegisterInfo.cpp:2832
llvm::SIRegisterInfo::isVectorRegister
bool isVectorRegister(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.h:288
llvm::SIRegisterInfo::spillEmergencySGPR
bool spillEmergencySGPR(MachineBasicBlock::iterator MI, MachineBasicBlock &RestoreMBB, Register SGPR, RegScavenger *RS) const
Definition: SIRegisterInfo.cpp:1868
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::SIRegisterInfo::getEquivalentSGPRClass
const TargetRegisterClass * getEquivalentSGPRClass(const TargetRegisterClass *VRC) const
Definition: SIRegisterInfo.cpp:2698
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::SIRegisterInfo::reservedPrivateSegmentBufferReg
MCRegister reservedPrivateSegmentBufferReg(const MachineFunction &MF) const
Return the end register initially reserved for the scratch buffer in case spilling is needed.
Definition: SIRegisterInfo.cpp:538
llvm::SIRegisterInfo::getPhysRegClass
const TargetRegisterClass * getPhysRegClass(MCRegister Reg) const
Return the 'base' register class for this register.
Definition: SIRegisterInfo.cpp:2603
llvm::SIRegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:545
llvm::SIRegisterInfo::getPointerRegClass
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
Definition: SIRegisterInfo.cpp:922
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
llvm::SIRegisterInfo::hasAGPRs
static bool hasAGPRs(const TargetRegisterClass *RC)
Definition: SIRegisterInfo.h:224
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::SIRegisterInfo::getSGPRClassForBitWidth
static const LLVM_READONLY TargetRegisterClass * getSGPRClassForBitWidth(unsigned BitWidth)
Definition: SIRegisterInfo.cpp:2573
llvm::LLT
Definition: LowLevelTypeImpl.h:39