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SIRegisterInfo.h
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1 //===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Interface definition for SIRegisterInfo
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
16 
17 #include "AMDGPURegisterInfo.h"
18 #include "SIDefines.h"
20 
21 namespace llvm {
22 
23 class GCNSubtarget;
24 class LiveIntervals;
25 class MachineRegisterInfo;
26 class SIMachineFunctionInfo;
27 
28 class SIRegisterInfo final : public AMDGPURegisterInfo {
29 private:
30  unsigned SGPRSetID;
31  unsigned VGPRSetID;
32  BitVector SGPRPressureSets;
33  BitVector VGPRPressureSets;
34  bool SpillSGPRToVGPR;
35  bool SpillSGPRToSMEM;
36  bool isWave32;
37 
38  void classifyPressureSet(unsigned PSetID, unsigned Reg,
39  BitVector &PressureSets) const;
40 public:
42 
43  bool spillSGPRToVGPR() const {
44  return SpillSGPRToVGPR;
45  }
46 
47  bool spillSGPRToSMEM() const {
48  return SpillSGPRToSMEM;
49  }
50 
51  /// Return the end register initially reserved for the scratch buffer in case
52  /// spilling is needed.
53  unsigned reservedPrivateSegmentBufferReg(const MachineFunction &MF) const;
54 
55  /// Return the end register initially reserved for the scratch wave offset in
56  /// case spilling is needed.
58  const MachineFunction &MF) const;
59 
60  BitVector getReservedRegs(const MachineFunction &MF) const override;
61 
62  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
63  const MCPhysReg *getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
65  CallingConv::ID) const override;
66 
67  // Stack access is very expensive. CSRs are also the high registers, and we
68  // want to minimize the number of used registers.
69  unsigned getCSRFirstUseCost() const override {
70  return 100;
71  }
72 
73  unsigned getFrameRegister(const MachineFunction &MF) const override;
74 
75  bool canRealignStack(const MachineFunction &MF) const override;
76  bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
77 
78  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
80  const MachineFunction &MF) const override;
81  bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override;
82  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
83 
84  int64_t getMUBUFInstrOffset(const MachineInstr *MI) const;
85 
86  int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
87  int Idx) const override;
88 
89  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
90 
92  unsigned BaseReg, int FrameIdx,
93  int64_t Offset) const override;
94 
95  void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
96  int64_t Offset) const override;
97 
98  bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
99  int64_t Offset) const override;
100 
102  const MachineFunction &MF, unsigned Kind = 0) const override;
103 
104  /// If \p OnlyToVGPR is true, this will only succeed if this
106  int FI, RegScavenger *RS,
107  bool OnlyToVGPR = false) const;
108 
110  int FI, RegScavenger *RS,
111  bool OnlyToVGPR = false) const;
112 
114  unsigned FIOperandNum,
115  RegScavenger *RS) const override;
116 
118  int FI, RegScavenger *RS) const;
119 
120  StringRef getRegAsmName(unsigned Reg) const override;
121 
122  unsigned getHWRegIndex(unsigned Reg) const {
123  return getEncodingValue(Reg) & 0xff;
124  }
125 
126  /// Return the 'base' register class for this register.
127  /// e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.
128  const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
129 
130  /// \returns true if this class contains only SGPR registers
131  bool isSGPRClass(const TargetRegisterClass *RC) const {
132  return !hasVGPRs(RC);
133  }
134 
135  /// \returns true if this class ID contains only SGPR registers
136  bool isSGPRClassID(unsigned RCID) const {
137  return isSGPRClass(getRegClass(RCID));
138  }
139 
140  bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const {
141  const TargetRegisterClass *RC;
143  RC = MRI.getRegClass(Reg);
144  else
145  RC = getPhysRegClass(Reg);
146  return isSGPRClass(RC);
147  }
148 
149  /// \returns true if this class contains VGPR registers.
150  bool hasVGPRs(const TargetRegisterClass *RC) const;
151 
152  /// \returns A VGPR reg class with the same width as \p SRC
154  const TargetRegisterClass *SRC) const;
155 
156  /// \returns A SGPR reg class with the same width as \p SRC
158  const TargetRegisterClass *VRC) const;
159 
160  /// \returns The register class that is used for a sub-register of \p RC for
161  /// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will
162  /// be returned.
164  unsigned SubIdx) const;
165 
166  bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
167  unsigned DefSubReg,
168  const TargetRegisterClass *SrcRC,
169  unsigned SrcSubReg) const override;
170 
171  /// \returns True if operands defined with this operand type can accept
172  /// a literal constant (i.e. any 32-bit immediate).
173  bool opCanUseLiteralConstant(unsigned OpType) const {
174  // TODO: 64-bit operands have extending behavior from 32-bit literal.
175  return OpType >= AMDGPU::OPERAND_REG_IMM_FIRST &&
177  }
178 
179  /// \returns True if operands defined with this operand type can accept
180  /// an inline constant. i.e. An integer value in the range (-16, 64) or
181  /// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.
182  bool opCanUseInlineConstant(unsigned OpType) const {
183  return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
184  OpType <= AMDGPU::OPERAND_SRC_LAST;
185  }
186 
188  const TargetRegisterClass *RC,
189  const MachineFunction &MF) const;
190 
191  unsigned getSGPRPressureSet() const { return SGPRSetID; };
192  unsigned getVGPRPressureSet() const { return VGPRSetID; };
193 
195  unsigned Reg) const;
196  bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
197 
198  virtual bool
199  isDivergentRegClass(const TargetRegisterClass *RC) const override {
200  return !isSGPRClass(RC);
201  }
202 
203  bool isSGPRPressureSet(unsigned SetID) const {
204  return SGPRPressureSets.test(SetID) && !VGPRPressureSets.test(SetID);
205  }
206  bool isVGPRPressureSet(unsigned SetID) const {
207  return VGPRPressureSets.test(SetID) && !SGPRPressureSets.test(SetID);
208  }
209 
211  unsigned EltSize) const;
212 
213  bool shouldCoalesce(MachineInstr *MI,
214  const TargetRegisterClass *SrcRC,
215  unsigned SubReg,
216  const TargetRegisterClass *DstRC,
217  unsigned DstSubReg,
218  const TargetRegisterClass *NewRC,
219  LiveIntervals &LIS) const override;
220 
221  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
222  MachineFunction &MF) const override;
223 
224  unsigned getRegPressureSetLimit(const MachineFunction &MF,
225  unsigned Idx) const override;
226 
227  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
228 
229  unsigned getReturnAddressReg(const MachineFunction &MF) const;
230 
231  const TargetRegisterClass *
233  const MachineRegisterInfo &MRI) const override;
234 
236  return isWave32 ? &AMDGPU::SReg_32_XM0RegClass
237  : &AMDGPU::SReg_64RegClass;
238  }
239 
241  return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass
242  : &AMDGPU::SReg_64_XEXECRegClass;
243  }
244 
245  unsigned getVCC() const;
246 
247  const TargetRegisterClass *getRegClass(unsigned RCID) const;
248 
249  // Find reaching register definition
250  MachineInstr *findReachingDef(unsigned Reg, unsigned SubReg,
251  MachineInstr &Use,
252  MachineRegisterInfo &MRI,
253  LiveIntervals *LIS) const;
254 
255 private:
256  void buildSpillLoadStore(MachineBasicBlock::iterator MI,
257  unsigned LoadStoreOp,
258  int Index,
259  unsigned ValueReg,
260  bool ValueIsKill,
261  unsigned ScratchRsrcReg,
262  unsigned ScratchOffsetReg,
263  int64_t InstrOffset,
264  MachineMemOperand *MMO,
265  RegScavenger *RS) const;
266 };
267 
268 } // End namespace llvm
269 
270 #endif
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
bool requiresRegisterScavenging(const MachineFunction &Fn) const override
unsigned getVCC() const
unsigned reservedPrivateSegmentBufferReg(const MachineFunction &MF) const
Return the end register initially reserved for the scratch buffer in case spilling is needed...
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
const TargetRegisterClass * getRegClass(unsigned Reg) const
Return the register class of the specified virtual register.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isSGPRClassID(unsigned RCID) const
SIRegisterInfo(const GCNSubtarget &ST)
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
StringRef getRegAsmName(unsigned Reg) const override
const TargetRegisterClass * getEquivalentVGPRClass(const TargetRegisterClass *SRC) const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
unsigned Reg
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
bool test(unsigned Idx) const
Definition: BitVector.h:501
bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override
const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const override
const TargetRegisterClass * getEquivalentSGPRClass(const TargetRegisterClass *VRC) const
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
bool canRealignStack(const MachineFunction &MF) const override
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
A description of a memory reference used in the backend.
MachineInstr * findReachingDef(unsigned Reg, unsigned SubReg, MachineInstr &Use, MachineRegisterInfo &MRI, LiveIntervals *LIS) const
bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const
A Use represents the edge between a Value definition and its users.
Definition: Use.h:55
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
unsigned SubReg
bool opCanUseInlineConstant(unsigned OpType) const
bool opCanUseLiteralConstant(unsigned OpType) const
bool isSGPRClass(const TargetRegisterClass *RC) const
TargetRegisterInfo interface that is implemented by all hw codegen targets.
bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
bool isSGPRPressureSet(unsigned SetID) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
ArrayRef< int16_t > getRegSplitParts(const TargetRegisterClass *RC, unsigned EltSize) const
unsigned getCSRFirstUseCost() const override
bool spillSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, bool OnlyToVGPR=false) const
If OnlyToVGPR is true, this will only succeed if this.
bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const override
const int * getRegUnitPressureSets(unsigned RegUnit) const override
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const override
unsigned const MachineRegisterInfo * MRI
unsigned getFrameRegister(const MachineFunction &MF) const override
unsigned reservedPrivateSegmentWaveByteOffsetReg(const MachineFunction &MF) const
Return the end register initially reserved for the scratch wave offset in case spilling is needed...
unsigned getReturnAddressReg(const MachineFunction &MF) const
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
bool hasVGPRs(const TargetRegisterClass *RC) const
int64_t getMUBUFInstrOffset(const MachineInstr *MI) const
unsigned getSGPRPressureSet() const
const TargetRegisterClass * getSubRegClass(const TargetRegisterClass *RC, unsigned SubIdx) const
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
bool restoreSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, bool OnlyToVGPR=false) const
unsigned getVGPRPressureSet() const
unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override
MachineOperand class - Representation of each machine instruction operand.
unsigned findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF) const
Returns a register that is not used at any point in the function.
const TargetRegisterClass * getRegClassForReg(const MachineRegisterInfo &MRI, unsigned Reg) const
bool eliminateSGPRToVGPRSpillFrameIndex(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS) const
Special case of eliminateFrameIndex.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:63
const TargetRegisterClass * getBoolRC() const
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
bool spillSGPRToVGPR() const
bool spillSGPRToSMEM() const
const TargetRegisterClass * getWaveMaskRegClass() const
bool isVGPRPressureSet(unsigned SetID) const
const TargetRegisterClass * getRegClass(unsigned RCID) const
const TargetRegisterClass * getPhysRegClass(unsigned Reg) const
Return the &#39;base&#39; register class for this register.
unsigned getHWRegIndex(unsigned Reg) const
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48