LLVM  14.0.0git
SIRegisterInfo.h
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1 //===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Interface definition for SIRegisterInfo
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
16 
17 #define GET_REGINFO_HEADER
18 #include "AMDGPUGenRegisterInfo.inc"
19 
20 #include "SIDefines.h"
21 
22 namespace llvm {
23 
24 class GCNSubtarget;
25 class LiveIntervals;
26 class LivePhysRegs;
27 class RegisterBank;
28 struct SGPRSpillBuilder;
29 
30 class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
31 private:
32  const GCNSubtarget &ST;
33  bool SpillSGPRToVGPR;
34  bool isWave32;
35  BitVector RegPressureIgnoredUnits;
36 
37  /// Sub reg indexes for getRegSplitParts.
38  /// First index represents subreg size from 1 to 16 DWORDs.
39  /// The inner vector is sorted by bit offset.
40  /// Provided a register can be fully split with given subregs,
41  /// all elements of the inner vector combined give a full lane mask.
42  static std::array<std::vector<int16_t>, 16> RegSplitParts;
43 
44  // Table representing sub reg of given width and offset.
45  // First index is subreg size: 32, 64, 96, 128, 160, 192, 224, 256, 512.
46  // Second index is 32 different dword offsets.
47  static std::array<std::array<uint16_t, 32>, 9> SubRegFromChannelTable;
48 
49  void reserveRegisterTuples(BitVector &, MCRegister Reg) const;
50 
51 public:
52  SIRegisterInfo(const GCNSubtarget &ST);
53 
54  /// \returns the sub reg enum value for the given \p Channel
55  /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)
56  static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs = 1);
57 
58  bool spillSGPRToVGPR() const {
59  return SpillSGPRToVGPR;
60  }
61 
62  /// Return the end register initially reserved for the scratch buffer in case
63  /// spilling is needed.
65 
66  BitVector getReservedRegs(const MachineFunction &MF) const override;
67 
68  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
69  const MCPhysReg *getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
71  CallingConv::ID) const override;
72  const uint32_t *getNoPreservedMask() const override;
73 
74  // Stack access is very expensive. CSRs are also the high registers, and we
75  // want to minimize the number of used registers.
76  unsigned getCSRFirstUseCost() const override {
77  return 100;
78  }
79 
80  const TargetRegisterClass *
82  const MachineFunction &MF) const override;
83 
84  Register getFrameRegister(const MachineFunction &MF) const override;
85 
86  bool hasBasePointer(const MachineFunction &MF) const;
87  Register getBaseRegister() const;
88 
89  bool shouldRealignStack(const MachineFunction &MF) const override;
90  bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
91 
92  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
94  const MachineFunction &MF) const override;
95  bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override;
96 
97  int64_t getScratchInstrOffset(const MachineInstr *MI) const;
98 
100  int Idx) const override;
101 
102  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
103 
105  int64_t Offset) const override;
106 
107  void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
108  int64_t Offset) const override;
109 
110  bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
111  int64_t Offset) const override;
112 
114  const MachineFunction &MF, unsigned Kind = 0) const override;
115 
116  /// Returns a legal register class to copy a register in the specified class
117  /// to or from. If it is possible to copy the register directly without using
118  /// a cross register class copy, return the specified RC. Returns NULL if it
119  /// is not possible to copy between two registers of the specified class.
120  const TargetRegisterClass *
121  getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
122 
124  bool IsLoad, bool IsKill = true) const;
125 
126  /// If \p OnlyToVGPR is true, this will only succeed if this
128  int FI, RegScavenger *RS,
129  LiveIntervals *LIS = nullptr,
130  bool OnlyToVGPR = false) const;
131 
133  int FI, RegScavenger *RS,
134  LiveIntervals *LIS = nullptr,
135  bool OnlyToVGPR = false) const;
136 
138  MachineBasicBlock &RestoreMBB, Register SGPR,
139  RegScavenger *RS) const;
140 
142  unsigned FIOperandNum,
143  RegScavenger *RS) const override;
144 
146  int FI, RegScavenger *RS,
147  LiveIntervals *LIS = nullptr) const;
148 
149  StringRef getRegAsmName(MCRegister Reg) const override;
150 
151  // Pseudo regs are not allowed
152  unsigned getHWRegIndex(MCRegister Reg) const {
153  return getEncodingValue(Reg) & 0xff;
154  }
155 
158 
161 
163  const TargetRegisterClass *
165 
167  static const TargetRegisterClass *getSGPRClassForBitWidth(unsigned BitWidth);
168 
169  /// Return the 'base' register class for this register.
170  /// e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.
172 
173  /// \returns true if this class contains only SGPR registers
174  static bool isSGPRClass(const TargetRegisterClass *RC) {
175  return hasSGPRs(RC) && !hasVGPRs(RC) && !hasAGPRs(RC);
176  }
177 
178  /// \returns true if this class ID contains only SGPR registers
179  bool isSGPRClassID(unsigned RCID) const {
180  return isSGPRClass(getRegClass(RCID));
181  }
182 
183  bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const;
184 
185  /// \returns true if this class contains only VGPR registers
186  static bool isVGPRClass(const TargetRegisterClass *RC) {
187  return hasVGPRs(RC) && !hasAGPRs(RC) && !hasSGPRs(RC);
188  }
189 
190  /// \returns true if this class contains only AGPR registers
191  static bool isAGPRClass(const TargetRegisterClass *RC) {
192  return hasAGPRs(RC) && !hasVGPRs(RC) && !hasSGPRs(RC);
193  }
194 
195  /// \returns true only if this class contains both VGPR and AGPR registers
196  bool isVectorSuperClass(const TargetRegisterClass *RC) const {
197  return hasVGPRs(RC) && hasAGPRs(RC) && !hasSGPRs(RC);
198  }
199 
200  /// \returns true only if this class contains both VGPR and SGPR registers
201  bool isVSSuperClass(const TargetRegisterClass *RC) const {
202  return hasVGPRs(RC) && hasSGPRs(RC) && !hasAGPRs(RC);
203  }
204 
205  /// \returns true if this class contains VGPR registers.
206  static bool hasVGPRs(const TargetRegisterClass *RC) {
207  return RC->TSFlags & SIRCFlags::HasVGPR;
208  }
209 
210  /// \returns true if this class contains AGPR registers.
211  static bool hasAGPRs(const TargetRegisterClass *RC) {
212  return RC->TSFlags & SIRCFlags::HasAGPR;
213  }
214 
215  /// \returns true if this class contains SGPR registers.
216  static bool hasSGPRs(const TargetRegisterClass *RC) {
217  return RC->TSFlags & SIRCFlags::HasSGPR;
218  }
219 
220  /// \returns true if this class contains any vector registers.
221  static bool hasVectorRegisters(const TargetRegisterClass *RC) {
222  return hasVGPRs(RC) || hasAGPRs(RC);
223  }
224 
225  /// \returns A VGPR reg class with the same width as \p SRC
226  const TargetRegisterClass *
228 
229  /// \returns An AGPR reg class with the same width as \p SRC
230  const TargetRegisterClass *
232 
233  /// \returns A SGPR reg class with the same width as \p SRC
234  const TargetRegisterClass *
236 
237  /// \returns The canonical register class that is used for a sub-register of
238  /// \p RC for the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC
239  /// will be returned.
241  unsigned SubIdx) const;
242 
243  /// Returns a register class which is compatible with \p SuperRC, such that a
244  /// subregister exists with class \p SubRC with subregister index \p
245  /// SubIdx. If this is impossible (e.g., an unaligned subregister index within
246  /// a register tuple), return null.
247  const TargetRegisterClass *
249  const TargetRegisterClass *SubRC,
250  unsigned SubIdx) const;
251 
252  bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
253  unsigned DefSubReg,
254  const TargetRegisterClass *SrcRC,
255  unsigned SrcSubReg) const override;
256 
257  /// \returns True if operands defined with this operand type can accept
258  /// a literal constant (i.e. any 32-bit immediate).
259  bool opCanUseLiteralConstant(unsigned OpType) const;
260 
261  /// \returns True if operands defined with this operand type can accept
262  /// an inline constant. i.e. An integer value in the range (-16, 64) or
263  /// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.
264  bool opCanUseInlineConstant(unsigned OpType) const;
265 
267  const TargetRegisterClass *RC,
268  const MachineFunction &MF,
269  bool ReserveHighestVGPR = false) const;
270 
272  Register Reg) const;
273  bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const;
274  bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const;
276  return isVGPR(MRI, Reg) || isAGPR(MRI, Reg);
277  }
278 
279  bool isConstantPhysReg(MCRegister PhysReg) const override;
280 
281  bool isDivergentRegClass(const TargetRegisterClass *RC) const override {
282  return !isSGPRClass(RC);
283  }
284 
286  unsigned EltSize) const;
287 
289  const TargetRegisterClass *SrcRC,
290  unsigned SubReg,
291  const TargetRegisterClass *DstRC,
292  unsigned DstSubReg,
293  const TargetRegisterClass *NewRC,
294  LiveIntervals &LIS) const override;
295 
296  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
297  MachineFunction &MF) const override;
298 
299  unsigned getRegPressureSetLimit(const MachineFunction &MF,
300  unsigned Idx) const override;
301 
302  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
303 
305 
306  const TargetRegisterClass *
308  const RegisterBank &Bank,
309  const MachineRegisterInfo &MRI) const;
310 
311  const TargetRegisterClass *
313  const RegisterBank &Bank,
314  const MachineRegisterInfo &MRI) const {
315  return getRegClassForSizeOnBank(Ty.getSizeInBits(), Bank, MRI);
316  }
317 
318  const TargetRegisterClass *
320  const MachineRegisterInfo &MRI) const override;
321 
323  return isWave32 ? &AMDGPU::SReg_32RegClass
324  : &AMDGPU::SReg_64RegClass;
325  }
326 
328  return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass
329  : &AMDGPU::SReg_64_XEXECRegClass;
330  }
331 
332  // Return the appropriate register class to use for 64-bit VGPRs for the
333  // subtarget.
334  const TargetRegisterClass *getVGPR64Class() const;
335 
336  MCRegister getVCC() const;
337 
338  const TargetRegisterClass *getRegClass(unsigned RCID) const;
339 
340  // Find reaching register definition
342  MachineInstr &Use,
344  LiveIntervals *LIS) const;
345 
346  const uint32_t *getAllVGPRRegMask() const;
347  const uint32_t *getAllAGPRRegMask() const;
348  const uint32_t *getAllVectorRegMask() const;
349  const uint32_t *getAllAllocatableSRegMask() const;
350 
351  // \returns number of 32 bit registers covered by a \p LM
352  static unsigned getNumCoveredRegs(LaneBitmask LM) {
353  // The assumption is that every lo16 subreg is an even bit and every hi16
354  // is an adjacent odd bit or vice versa.
355  uint64_t Mask = LM.getAsInteger();
356  uint64_t Even = Mask & 0xAAAAAAAAAAAAAAAAULL;
357  Mask = (Even >> 1) | Mask;
358  uint64_t Odd = Mask & 0x5555555555555555ULL;
359  return countPopulation(Odd);
360  }
361 
362  // \returns a DWORD offset of a \p SubReg
363  unsigned getChannelFromSubReg(unsigned SubReg) const {
364  return SubReg ? (getSubRegIdxOffset(SubReg) + 31) / 32 : 0;
365  }
366 
367  // \returns a DWORD size of a \p SubReg
368  unsigned getNumChannelsFromSubReg(unsigned SubReg) const {
369  return getNumCoveredRegs(getSubRegIndexLaneMask(SubReg));
370  }
371 
372  // For a given 16 bit \p Reg \returns a 32 bit register holding it.
373  // \returns \p Reg otherwise.
375 
376  // Returns true if a given register class is properly aligned for
377  // the subtarget.
378  bool isProperlyAlignedRC(const TargetRegisterClass &RC) const;
379 
380  /// Return all SGPR128 which satisfy the waves per execution unit requirement
381  /// of the subtarget.
383 
384  /// Return all SGPR64 which satisfy the waves per execution unit requirement
385  /// of the subtarget.
387 
388  /// Return all SGPR32 which satisfy the waves per execution unit requirement
389  /// of the subtarget.
391 
392  // Insert spill or restore instructions.
393  // When lowering spill pseudos, the RegScavenger should be set.
394  // For creating spill instructions during frame lowering, where no scavenger
395  // is available, LiveRegs can be used.
398  unsigned LoadStoreOp, int Index, Register ValueReg,
399  bool ValueIsKill, MCRegister ScratchOffsetReg,
400  int64_t InstrOffset, MachineMemOperand *MMO,
401  RegScavenger *RS,
402  LivePhysRegs *LiveRegs = nullptr) const;
403 };
404 
405 } // End namespace llvm
406 
407 #endif
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::LaneBitmask
Definition: LaneBitmask.h:40
llvm::SIRegisterInfo::getVGPRClassForBitWidth
const LLVM_READONLY TargetRegisterClass * getVGPRClassForBitWidth(unsigned BitWidth) const
Definition: SIRegisterInfo.cpp:2210
llvm::SIRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Definition: SIRegisterInfo.cpp:360
llvm::SIRegisterInfo::getEquivalentVGPRClass
const TargetRegisterClass * getEquivalentVGPRClass(const TargetRegisterClass *SRC) const
Definition: SIRegisterInfo.cpp:2448
llvm::SIRegisterInfo::isAGPRClass
static bool isAGPRClass(const TargetRegisterClass *RC)
Definition: SIRegisterInfo.h:191
LLVM_READONLY
#define LLVM_READONLY
Definition: Compiler.h:216
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1558
llvm::SIRegisterInfo::isConstantPhysReg
bool isConstantPhysReg(MCRegister PhysReg) const override
Definition: SIRegisterInfo.cpp:2811
llvm::SIRegisterInfo::needsFrameBaseReg
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
Definition: SIRegisterInfo.cpp:760
llvm::SIRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned RCID) const
Definition: SIRegisterInfo.cpp:2710
llvm::SIRegisterInfo::requiresVirtualBaseRegisters
bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override
Definition: SIRegisterInfo.cpp:732
llvm::SIRegisterInfo::restoreSGPR
bool restoreSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, LiveIntervals *LIS=nullptr, bool OnlyToVGPR=false) const
Definition: SIRegisterInfo.cpp:1582
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::SIRegisterInfo::getAllSGPR128
ArrayRef< MCPhysReg > getAllSGPR128(const MachineFunction &MF) const
Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget.
Definition: SIRegisterInfo.cpp:2825
llvm::SIRegisterInfo::getFrameIndexInstrOffset
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
Definition: SIRegisterInfo.cpp:746
llvm::SIRegisterInfo::getRegUnitPressureSets
const int * getRegUnitPressureSets(unsigned RegUnit) const override
Definition: SIRegisterInfo.cpp:2652
llvm::SIRegisterInfo::getScratchInstrOffset
int64_t getScratchInstrOffset(const MachineInstr *MI) const
Definition: SIRegisterInfo.cpp:738
llvm::SIRegisterInfo::getAllSGPR64
ArrayRef< MCPhysReg > getAllSGPR64(const MachineFunction &MF) const
Return all SGPR64 which satisfy the waves per execution unit requirement of the subtarget.
Definition: SIRegisterInfo.cpp:2831
llvm::SIRegisterInfo::hasSGPRs
static bool hasSGPRs(const TargetRegisterClass *RC)
Definition: SIRegisterInfo.h:216
llvm::SIRegisterInfo::isSGPRClassID
bool isSGPRClassID(unsigned RCID) const
Definition: SIRegisterInfo.h:179
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:48
llvm::SIRegisterInfo::SIRegisterInfo
SIRegisterInfo(const GCNSubtarget &ST)
Definition: SIRegisterInfo.cpp:289
llvm::SIRegisterInfo::getVectorSuperClassForBitWidth
const LLVM_READONLY TargetRegisterClass * getVectorSuperClassForBitWidth(unsigned BitWidth) const
Definition: SIRegisterInfo.cpp:2328
llvm::SIRegisterInfo::getCSRFirstUseCost
unsigned getCSRFirstUseCost() const override
Definition: SIRegisterInfo.h:76
llvm::SIRegisterInfo::getWaveMaskRegClass
const TargetRegisterClass * getWaveMaskRegClass() const
Definition: SIRegisterInfo.h:327
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
llvm::SIRegisterInfo::getEquivalentAGPRClass
const TargetRegisterClass * getEquivalentAGPRClass(const TargetRegisterClass *SRC) const
Definition: SIRegisterInfo.cpp:2456
llvm::SIRegisterInfo::materializeFrameBaseRegister
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
Definition: SIRegisterInfo.cpp:774
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:80
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::SIRegisterInfo::getAllAllocatableSRegMask
const uint32_t * getAllAllocatableSRegMask() const
Definition: SIRegisterInfo.cpp:501
llvm::SIRegisterInfo::requiresFrameIndexReplacementScavenging
bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:726
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::SIRegisterInfo::getSubRegClass
const TargetRegisterClass * getSubRegClass(const TargetRegisterClass *RC, unsigned SubIdx) const
Definition: SIRegisterInfo.cpp:2473
llvm::SIRegisterInfo::buildVGPRSpillLoadStore
void buildVGPRSpillLoadStore(SGPRSpillBuilder &SB, int Index, int Offset, bool IsLoad, bool IsKill=true) const
Definition: SIRegisterInfo.cpp:1429
llvm::SIRegisterInfo::findReachingDef
MachineInstr * findReachingDef(Register Reg, unsigned SubReg, MachineInstr &Use, MachineRegisterInfo &MRI, LiveIntervals *LIS) const
Definition: SIRegisterInfo.cpp:2725
llvm::SIRegisterInfo::getRegClassForTypeOnBank
const TargetRegisterClass * getRegClassForTypeOnBank(LLT Ty, const RegisterBank &Bank, const MachineRegisterInfo &MRI) const
Definition: SIRegisterInfo.h:312
llvm::SIRegisterInfo::getCrossCopyRegClass
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
Returns a legal register class to copy a register in the specified class to or from.
Definition: SIRegisterInfo.cpp:899
llvm::SIRegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:465
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::LLT::getSizeInBits
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:152
llvm::SIRegisterInfo::getLargestLegalSuperClass
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:410
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::SIRegisterInfo::getReturnAddressReg
MCRegister getReturnAddressReg(const MachineFunction &MF) const
Definition: SIRegisterInfo.cpp:2661
llvm::SIRegisterInfo::getRegClassForReg
const TargetRegisterClass * getRegClassForReg(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2578
llvm::SIRegisterInfo::isAGPR
bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2590
llvm::SIRegisterInfo::getHWRegIndex
unsigned getHWRegIndex(MCRegister Reg) const
Definition: SIRegisterInfo.h:152
llvm::SIRegisterInfo::getChannelFromSubReg
unsigned getChannelFromSubReg(unsigned SubReg) const
Definition: SIRegisterInfo.h:363
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::SIRegisterInfo::eliminateFrameIndex
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
Definition: SIRegisterInfo.cpp:1768
llvm::SIRegisterInfo::getRegPressureLimit
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:2619
llvm::SIRegisterInfo::getNumChannelsFromSubReg
unsigned getNumChannelsFromSubReg(unsigned SubReg) const
Definition: SIRegisterInfo.h:368
llvm::SIRegisterInfo::getSubRegFromChannel
static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs=1)
Definition: SIRegisterInfo.cpp:505
llvm::SIRegisterInfo::isSGPRClass
static bool isSGPRClass(const TargetRegisterClass *RC)
Definition: SIRegisterInfo.h:174
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:30
llvm::SIRegisterInfo::hasVGPRs
static bool hasVGPRs(const TargetRegisterClass *RC)
Definition: SIRegisterInfo.h:206
llvm::SIRegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Definition: SIRegisterInfo.cpp:387
llvm::SIRegisterInfo::getVCC
MCRegister getVCC() const
Definition: SIRegisterInfo.cpp:2699
llvm::BitVector
Definition: BitVector.h:74
llvm::SIRegisterInfo::getVGPR64Class
const TargetRegisterClass * getVGPR64Class() const
Definition: SIRegisterInfo.cpp:2703
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::SIRegisterInfo::isDivergentRegClass
bool isDivergentRegClass(const TargetRegisterClass *RC) const override
Definition: SIRegisterInfo.h:281
llvm::SIRegisterInfo::opCanUseLiteralConstant
bool opCanUseLiteralConstant(unsigned OpType) const
Definition: SIRegisterInfo.cpp:2536
llvm::SIRegisterInfo::isFrameOffsetLegal
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
Definition: SIRegisterInfo.cpp:874
llvm::SIRegisterInfo::getBaseRegister
Register getBaseRegister() const
Definition: SIRegisterInfo.cpp:487
llvm::SIRegisterInfo::getAllVGPRRegMask
const uint32_t * getAllVGPRRegMask() const
Definition: SIRegisterInfo.cpp:489
llvm::countPopulation
unsigned countPopulation(T Value)
Count the number of set bits in a value.
Definition: MathExtras.h:567
llvm::SIRegisterInfo::shouldRewriteCopySrc
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
Definition: SIRegisterInfo.cpp:2512
llvm::SIRegisterInfo::shouldRealignStack
bool shouldRealignStack(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:693
Index
uint32_t Index
Definition: ELFObjHandler.cpp:83
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::SIRegisterInfo::getRegAsmName
StringRef getRegAsmName(MCRegister Reg) const override
Definition: SIRegisterInfo.cpp:2157
uint64_t
llvm::TargetRegisterClass::TSFlags
const uint8_t TSFlags
Configurable target specific flags.
Definition: TargetRegisterInfo.h:61
llvm::SIRegisterInfo::isVGPRClass
static bool isVGPRClass(const TargetRegisterClass *RC)
Definition: SIRegisterInfo.h:186
llvm::SIRegisterInfo::requiresFrameIndexScavenging
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:717
llvm::SIRegisterInfo::hasBasePointer
bool hasBasePointer(const MachineFunction &MF) const
Definition: SIRegisterInfo.cpp:480
llvm::SIRegisterInfo::getAllVectorRegMask
const uint32_t * getAllVectorRegMask() const
Definition: SIRegisterInfo.cpp:497
llvm::SIRegisterInfo::getRegClassForSizeOnBank
const TargetRegisterClass * getRegClassForSizeOnBank(unsigned Size, const RegisterBank &Bank, const MachineRegisterInfo &MRI) const
Definition: SIRegisterInfo.cpp:2667
llvm::SIRegisterInfo::isSGPRReg
bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2437
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::SIRegisterInfo::isVGPR
bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2583
llvm::SIRegisterInfo::getBoolRC
const TargetRegisterClass * getBoolRC() const
Definition: SIRegisterInfo.h:322
llvm::SIRegisterInfo::getRegSplitParts
ArrayRef< int16_t > getRegSplitParts(const TargetRegisterClass *RC, unsigned EltSize) const
Definition: SIRegisterInfo.cpp:2562
llvm::HasVGPR
@ HasVGPR
Definition: SIDefines.h:20
llvm::HasSGPR
@ HasSGPR
Definition: SIDefines.h:22
llvm::SIRegisterInfo::getAllAGPRRegMask
const uint32_t * getAllAGPRRegMask() const
Definition: SIRegisterInfo.cpp:493
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::SIRegisterInfo::isVSSuperClass
bool isVSSuperClass(const TargetRegisterClass *RC) const
Definition: SIRegisterInfo.h:201
llvm::SIRegisterInfo::getNoPreservedMask
const uint32_t * getNoPreservedMask() const override
Definition: SIRegisterInfo.cpp:405
llvm::SIRegisterInfo::get32BitRegister
MCPhysReg get32BitRegister(MCPhysReg Reg) const
Definition: SIRegisterInfo.cpp:2779
llvm::SIRegisterInfo::hasVectorRegisters
static bool hasVectorRegisters(const TargetRegisterClass *RC)
Definition: SIRegisterInfo.h:221
llvm::ArrayRef< int16_t >
llvm::SIRegisterInfo::isVectorSuperClass
bool isVectorSuperClass(const TargetRegisterClass *RC) const
Definition: SIRegisterInfo.h:196
llvm::SIRegisterInfo::getNumCoveredRegs
static unsigned getNumCoveredRegs(LaneBitmask LM)
Definition: SIRegisterInfo.h:352
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::HasAGPR
@ HasAGPR
Definition: SIDefines.h:21
llvm::SIRegisterInfo::isProperlyAlignedRC
bool isProperlyAlignedRC(const TargetRegisterClass &RC) const
Definition: SIRegisterInfo.cpp:2796
llvm::SIRegisterInfo::spillSGPRToVGPR
bool spillSGPRToVGPR() const
Definition: SIRegisterInfo.h:58
uint32_t
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::LaneBitmask::getAsInteger
constexpr Type getAsInteger() const
Definition: LaneBitmask.h:74
llvm::SIRegisterInfo::getCalleeSavedRegsViaCopy
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
Definition: SIRegisterInfo.cpp:383
llvm::SIRegisterInfo::resolveFrameIndex
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
Definition: SIRegisterInfo.cpp:825
llvm::SIRegisterInfo::buildSpillLoadStore
void buildSpillLoadStore(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned LoadStoreOp, int Index, Register ValueReg, bool ValueIsKill, MCRegister ScratchOffsetReg, int64_t InstrOffset, MachineMemOperand *MMO, RegScavenger *RS, LivePhysRegs *LiveRegs=nullptr) const
Definition: SIRegisterInfo.cpp:1173
llvm::SGPRSpillBuilder
Definition: SIRegisterInfo.cpp:70
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SIRegisterInfo::getRegPressureSetLimit
unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override
Definition: SIRegisterInfo.cpp:2638
llvm::SIRegisterInfo::getAllSGPR32
ArrayRef< MCPhysReg > getAllSGPR32(const MachineFunction &MF) const
Return all SGPR32 which satisfy the waves per execution unit requirement of the subtarget.
Definition: SIRegisterInfo.cpp:2837
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
uint16_t
llvm::SIRegisterInfo::eliminateSGPRToVGPRSpillFrameIndex
bool eliminateSGPRToVGPRSpillFrameIndex(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, LiveIntervals *LIS=nullptr) const
Special case of eliminateFrameIndex.
Definition: SIRegisterInfo.cpp:1735
SIDefines.h
AMDGPUGenRegisterInfo
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::SIRegisterInfo::spillSGPR
bool spillSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, LiveIntervals *LIS=nullptr, bool OnlyToVGPR=false) const
If OnlyToVGPR is true, this will only succeed if this.
Definition: SIRegisterInfo.cpp:1462
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::SIRegisterInfo::requiresRegisterScavenging
bool requiresRegisterScavenging(const MachineFunction &Fn) const override
Definition: SIRegisterInfo.cpp:706
llvm::SIRegisterInfo::getConstrainedRegClassForOperand
const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const override
Definition: SIRegisterInfo.cpp:2687
llvm::SIRegisterInfo::findUnusedRegister
MCRegister findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF, bool ReserveHighestVGPR=false) const
Returns a lowest register that is not used at any point in the function.
Definition: SIRegisterInfo.cpp:2546
llvm::SIRegisterInfo::getCompatibleSubRegClass
const TargetRegisterClass * getCompatibleSubRegClass(const TargetRegisterClass *SuperRC, const TargetRegisterClass *SubRC, unsigned SubIdx) const
Returns a register class which is compatible with SuperRC, such that a subregister exists with class ...
Definition: SIRegisterInfo.cpp:2494
llvm::SIRegisterInfo::getAGPRClassForBitWidth
const LLVM_READONLY TargetRegisterClass * getAGPRClassForBitWidth(unsigned BitWidth) const
Definition: SIRegisterInfo.cpp:2270
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::SIRegisterInfo::opCanUseInlineConstant
bool opCanUseInlineConstant(unsigned OpType) const
Definition: SIRegisterInfo.cpp:2503
llvm::SIRegisterInfo::shouldCoalesce
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
Definition: SIRegisterInfo.cpp:2598
llvm::SIRegisterInfo::isVectorRegister
bool isVectorRegister(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.h:275
llvm::SIRegisterInfo::spillEmergencySGPR
bool spillEmergencySGPR(MachineBasicBlock::iterator MI, MachineBasicBlock &RestoreMBB, Register SGPR, RegScavenger *RS) const
Definition: SIRegisterInfo.cpp:1663
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::SIRegisterInfo::getEquivalentSGPRClass
const TargetRegisterClass * getEquivalentSGPRClass(const TargetRegisterClass *VRC) const
Definition: SIRegisterInfo.cpp:2464
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::SIRegisterInfo::reservedPrivateSegmentBufferReg
MCRegister reservedPrivateSegmentBufferReg(const MachineFunction &MF) const
Return the end register initially reserved for the scratch buffer in case spilling is needed.
Definition: SIRegisterInfo.cpp:514
llvm::SIRegisterInfo::getPhysRegClass
const TargetRegisterClass * getPhysRegClass(MCRegister Reg) const
Return the 'base' register class for this register.
Definition: SIRegisterInfo.cpp:2369
llvm::SIRegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:521
llvm::SIRegisterInfo::getPointerRegClass
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
Definition: SIRegisterInfo.cpp:890
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:44
llvm::SIRegisterInfo::hasAGPRs
static bool hasAGPRs(const TargetRegisterClass *RC)
Definition: SIRegisterInfo.h:211
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::SIRegisterInfo::getSGPRClassForBitWidth
static const LLVM_READONLY TargetRegisterClass * getSGPRClassForBitWidth(unsigned BitWidth)
Definition: SIRegisterInfo.cpp:2339
llvm::LLT
Definition: LowLevelTypeImpl.h:39