LLVM  17.0.0git
SIRegisterInfo.h
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1 //===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Interface definition for SIRegisterInfo
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
16 
17 #define GET_REGINFO_HEADER
18 #include "AMDGPUGenRegisterInfo.inc"
19 
20 #include "SIDefines.h"
21 
22 namespace llvm {
23 
24 class GCNSubtarget;
25 class LiveIntervals;
26 class LivePhysRegs;
27 class RegisterBank;
28 struct SGPRSpillBuilder;
29 
30 class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
31 private:
32  const GCNSubtarget &ST;
33  bool SpillSGPRToVGPR;
34  bool isWave32;
35  BitVector RegPressureIgnoredUnits;
36 
37  /// Sub reg indexes for getRegSplitParts.
38  /// First index represents subreg size from 1 to 16 DWORDs.
39  /// The inner vector is sorted by bit offset.
40  /// Provided a register can be fully split with given subregs,
41  /// all elements of the inner vector combined give a full lane mask.
42  static std::array<std::vector<int16_t>, 16> RegSplitParts;
43 
44  // Table representing sub reg of given width and offset.
45  // First index is subreg size: 32, 64, 96, 128, 160, 192, 224, 256, 512.
46  // Second index is 32 different dword offsets.
47  static std::array<std::array<uint16_t, 32>, 9> SubRegFromChannelTable;
48 
49  void reserveRegisterTuples(BitVector &, MCRegister Reg) const;
50 
51 public:
52  SIRegisterInfo(const GCNSubtarget &ST);
53 
54  struct SpilledReg {
56  int Lane = -1;
57 
58  SpilledReg() = default;
59  SpilledReg(Register R, int L) : VGPR(R), Lane(L) {}
60 
61  bool hasLane() { return Lane != -1; }
62  bool hasReg() { return VGPR != 0; }
63  };
64 
65  /// \returns the sub reg enum value for the given \p Channel
66  /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)
67  static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs = 1);
68 
69  bool spillSGPRToVGPR() const {
70  return SpillSGPRToVGPR;
71  }
72 
73  /// Return the end register initially reserved for the scratch buffer in case
74  /// spilling is needed.
76 
77  BitVector getReservedRegs(const MachineFunction &MF) const override;
78  bool isAsmClobberable(const MachineFunction &MF,
79  MCRegister PhysReg) const override;
80 
81  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
82  const MCPhysReg *getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
84  CallingConv::ID) const override;
85  const uint32_t *getNoPreservedMask() const override;
86 
87  // Stack access is very expensive. CSRs are also the high registers, and we
88  // want to minimize the number of used registers.
89  unsigned getCSRFirstUseCost() const override {
90  return 100;
91  }
92 
93  const TargetRegisterClass *
95  const MachineFunction &MF) const override;
96 
97  Register getFrameRegister(const MachineFunction &MF) const override;
98 
99  bool hasBasePointer(const MachineFunction &MF) const;
100  Register getBaseRegister() const;
101 
102  bool shouldRealignStack(const MachineFunction &MF) const override;
103  bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
104 
105  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
107  const MachineFunction &MF) const override;
108  bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override;
109 
110  int64_t getScratchInstrOffset(const MachineInstr *MI) const;
111 
113  int Idx) const override;
114 
115  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
116 
118  int64_t Offset) const override;
119 
120  void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
121  int64_t Offset) const override;
122 
123  bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
124  int64_t Offset) const override;
125 
127  const MachineFunction &MF, unsigned Kind = 0) const override;
128 
129  /// Returns a legal register class to copy a register in the specified class
130  /// to or from. If it is possible to copy the register directly without using
131  /// a cross register class copy, return the specified RC. Returns NULL if it
132  /// is not possible to copy between two registers of the specified class.
133  const TargetRegisterClass *
134  getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
135 
137  bool IsLoad, bool IsKill = true) const;
138 
139  /// If \p OnlyToVGPR is true, this will only succeed if this
141  SlotIndexes *Indexes = nullptr, LiveIntervals *LIS = nullptr,
142  bool OnlyToVGPR = false) const;
143 
145  SlotIndexes *Indexes = nullptr, LiveIntervals *LIS = nullptr,
146  bool OnlyToVGPR = false) const;
147 
149  MachineBasicBlock &RestoreMBB, Register SGPR,
150  RegScavenger *RS) const;
151 
152  bool supportsBackwardScavenger() const override {
153  return true;
154  }
155 
157  unsigned FIOperandNum,
158  RegScavenger *RS) const override;
159 
161  int FI, RegScavenger *RS,
162  SlotIndexes *Indexes = nullptr,
163  LiveIntervals *LIS = nullptr) const;
164 
165  StringRef getRegAsmName(MCRegister Reg) const override;
166 
167  // Pseudo regs are not allowed
168  unsigned getHWRegIndex(MCRegister Reg) const {
169  return getEncodingValue(Reg) & 0xff;
170  }
171 
174 
177 
179  const TargetRegisterClass *
181 
183  static const TargetRegisterClass *getSGPRClassForBitWidth(unsigned BitWidth);
184 
185  /// \returns true if this class contains only SGPR registers
186  static bool isSGPRClass(const TargetRegisterClass *RC) {
187  return hasSGPRs(RC) && !hasVGPRs(RC) && !hasAGPRs(RC);
188  }
189 
190  /// \returns true if this class ID contains only SGPR registers
191  bool isSGPRClassID(unsigned RCID) const {
192  return isSGPRClass(getRegClass(RCID));
193  }
194 
195  bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const;
196 
197  /// \returns true if this class contains only VGPR registers
198  static bool isVGPRClass(const TargetRegisterClass *RC) {
199  return hasVGPRs(RC) && !hasAGPRs(RC) && !hasSGPRs(RC);
200  }
201 
202  /// \returns true if this class contains only AGPR registers
203  static bool isAGPRClass(const TargetRegisterClass *RC) {
204  return hasAGPRs(RC) && !hasVGPRs(RC) && !hasSGPRs(RC);
205  }
206 
207  /// \returns true only if this class contains both VGPR and AGPR registers
208  bool isVectorSuperClass(const TargetRegisterClass *RC) const {
209  return hasVGPRs(RC) && hasAGPRs(RC) && !hasSGPRs(RC);
210  }
211 
212  /// \returns true only if this class contains both VGPR and SGPR registers
213  bool isVSSuperClass(const TargetRegisterClass *RC) const {
214  return hasVGPRs(RC) && hasSGPRs(RC) && !hasAGPRs(RC);
215  }
216 
217  /// \returns true if this class contains VGPR registers.
218  static bool hasVGPRs(const TargetRegisterClass *RC) {
219  return RC->TSFlags & SIRCFlags::HasVGPR;
220  }
221 
222  /// \returns true if this class contains AGPR registers.
223  static bool hasAGPRs(const TargetRegisterClass *RC) {
224  return RC->TSFlags & SIRCFlags::HasAGPR;
225  }
226 
227  /// \returns true if this class contains SGPR registers.
228  static bool hasSGPRs(const TargetRegisterClass *RC) {
229  return RC->TSFlags & SIRCFlags::HasSGPR;
230  }
231 
232  /// \returns true if this class contains any vector registers.
233  static bool hasVectorRegisters(const TargetRegisterClass *RC) {
234  return hasVGPRs(RC) || hasAGPRs(RC);
235  }
236 
237  /// \returns A VGPR reg class with the same width as \p SRC
238  const TargetRegisterClass *
240 
241  /// \returns An AGPR reg class with the same width as \p SRC
242  const TargetRegisterClass *
244 
245  /// \returns A SGPR reg class with the same width as \p SRC
246  const TargetRegisterClass *
248 
249  /// Returns a register class which is compatible with \p SuperRC, such that a
250  /// subregister exists with class \p SubRC with subregister index \p
251  /// SubIdx. If this is impossible (e.g., an unaligned subregister index within
252  /// a register tuple), return null.
253  const TargetRegisterClass *
255  const TargetRegisterClass *SubRC,
256  unsigned SubIdx) const;
257 
258  bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
259  unsigned DefSubReg,
260  const TargetRegisterClass *SrcRC,
261  unsigned SrcSubReg) const override;
262 
263  /// \returns True if operands defined with this operand type can accept
264  /// a literal constant (i.e. any 32-bit immediate).
265  bool opCanUseLiteralConstant(unsigned OpType) const;
266 
267  /// \returns True if operands defined with this operand type can accept
268  /// an inline constant. i.e. An integer value in the range (-16, 64) or
269  /// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.
270  bool opCanUseInlineConstant(unsigned OpType) const;
271 
273  const TargetRegisterClass *RC,
274  const MachineFunction &MF,
275  bool ReserveHighestVGPR = false) const;
276 
278  Register Reg) const;
279  const TargetRegisterClass *
281  const MachineOperand &MO) const;
282 
283  bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const;
284  bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const;
286  return isVGPR(MRI, Reg) || isAGPR(MRI, Reg);
287  }
288 
289  bool isDivergentRegClass(const TargetRegisterClass *RC) const override {
290  return !isSGPRClass(RC);
291  }
292 
294  unsigned EltSize) const;
295 
297  const TargetRegisterClass *SrcRC,
298  unsigned SubReg,
299  const TargetRegisterClass *DstRC,
300  unsigned DstSubReg,
301  const TargetRegisterClass *NewRC,
302  LiveIntervals &LIS) const override;
303 
304  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
305  MachineFunction &MF) const override;
306 
307  unsigned getRegPressureSetLimit(const MachineFunction &MF,
308  unsigned Idx) const override;
309 
310  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
311 
313 
314  const TargetRegisterClass *
315  getRegClassForSizeOnBank(unsigned Size, const RegisterBank &Bank) const;
316 
317  const TargetRegisterClass *
318  getRegClassForTypeOnBank(LLT Ty, const RegisterBank &Bank) const {
319  return getRegClassForSizeOnBank(Ty.getSizeInBits(), Bank);
320  }
321 
322  const TargetRegisterClass *
324  const MachineRegisterInfo &MRI) const override;
325 
327  return isWave32 ? &AMDGPU::SReg_32RegClass
328  : &AMDGPU::SReg_64RegClass;
329  }
330 
332  return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass
333  : &AMDGPU::SReg_64_XEXECRegClass;
334  }
335 
336  // Return the appropriate register class to use for 64-bit VGPRs for the
337  // subtarget.
338  const TargetRegisterClass *getVGPR64Class() const;
339 
340  MCRegister getVCC() const;
341 
342  MCRegister getExec() const;
343 
344  const TargetRegisterClass *getRegClass(unsigned RCID) const;
345 
346  // Find reaching register definition
348  MachineInstr &Use,
350  LiveIntervals *LIS) const;
351 
352  const uint32_t *getAllVGPRRegMask() const;
353  const uint32_t *getAllAGPRRegMask() const;
354  const uint32_t *getAllVectorRegMask() const;
355  const uint32_t *getAllAllocatableSRegMask() const;
356 
357  // \returns number of 32 bit registers covered by a \p LM
358  static unsigned getNumCoveredRegs(LaneBitmask LM) {
359  // The assumption is that every lo16 subreg is an even bit and every hi16
360  // is an adjacent odd bit or vice versa.
361  uint64_t Mask = LM.getAsInteger();
362  uint64_t Even = Mask & 0xAAAAAAAAAAAAAAAAULL;
363  Mask = (Even >> 1) | Mask;
364  uint64_t Odd = Mask & 0x5555555555555555ULL;
365  return llvm::popcount(Odd);
366  }
367 
368  // \returns a DWORD offset of a \p SubReg
369  unsigned getChannelFromSubReg(unsigned SubReg) const {
370  return SubReg ? (getSubRegIdxOffset(SubReg) + 31) / 32 : 0;
371  }
372 
373  // \returns a DWORD size of a \p SubReg
374  unsigned getNumChannelsFromSubReg(unsigned SubReg) const {
375  return getNumCoveredRegs(getSubRegIndexLaneMask(SubReg));
376  }
377 
378  // For a given 16 bit \p Reg \returns a 32 bit register holding it.
379  // \returns \p Reg otherwise.
381 
382  // Returns true if a given register class is properly aligned for
383  // the subtarget.
384  bool isProperlyAlignedRC(const TargetRegisterClass &RC) const;
385 
386  // Given \p RC returns corresponding aligned register class if required
387  // by the subtarget.
388  const TargetRegisterClass *
389  getProperlyAlignedRC(const TargetRegisterClass *RC) const;
390 
391  /// Return all SGPR128 which satisfy the waves per execution unit requirement
392  /// of the subtarget.
394 
395  /// Return all SGPR64 which satisfy the waves per execution unit requirement
396  /// of the subtarget.
398 
399  /// Return all SGPR32 which satisfy the waves per execution unit requirement
400  /// of the subtarget.
402 
403  // Insert spill or restore instructions.
404  // When lowering spill pseudos, the RegScavenger should be set.
405  // For creating spill instructions during frame lowering, where no scavenger
406  // is available, LiveRegs can be used.
409  unsigned LoadStoreOp, int Index, Register ValueReg,
410  bool ValueIsKill, MCRegister ScratchOffsetReg,
411  int64_t InstrOffset, MachineMemOperand *MMO,
412  RegScavenger *RS,
413  LivePhysRegs *LiveRegs = nullptr) const;
414 };
415 
416 } // End namespace llvm
417 
418 #endif
llvm::LaneBitmask
Definition: LaneBitmask.h:40
llvm::SIRegisterInfo::getVGPRClassForBitWidth
const LLVM_READONLY TargetRegisterClass * getVGPRClassForBitWidth(unsigned BitWidth) const
Definition: SIRegisterInfo.cpp:2583
llvm::SIRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Definition: SIRegisterInfo.cpp:390
llvm::SIRegisterInfo::getEquivalentVGPRClass
const TargetRegisterClass * getEquivalentVGPRClass(const TargetRegisterClass *SRC) const
Definition: SIRegisterInfo.cpp:2790
llvm::SIRegisterInfo::isAGPRClass
static bool isAGPRClass(const TargetRegisterClass *RC)
Definition: SIRegisterInfo.h:203
LLVM_READONLY
#define LLVM_READONLY
Definition: Compiler.h:196
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::SIRegisterInfo::needsFrameBaseReg
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override
Definition: SIRegisterInfo.cpp:792
llvm::SIRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned RCID) const
Definition: SIRegisterInfo.cpp:3042
llvm::SIRegisterInfo::requiresVirtualBaseRegisters
bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override
Definition: SIRegisterInfo.cpp:764
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:51
llvm::SIRegisterInfo::getAllSGPR128
ArrayRef< MCPhysReg > getAllSGPR128(const MachineFunction &MF) const
Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget.
Definition: SIRegisterInfo.cpp:3163
llvm::SIRegisterInfo::getFrameIndexInstrOffset
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const override
Definition: SIRegisterInfo.cpp:778
llvm::SIRegisterInfo::getRegUnitPressureSets
const int * getRegUnitPressureSets(unsigned RegUnit) const override
Definition: SIRegisterInfo.cpp:2981
llvm::SIRegisterInfo::getScratchInstrOffset
int64_t getScratchInstrOffset(const MachineInstr *MI) const
Definition: SIRegisterInfo.cpp:770
llvm::SIRegisterInfo::getAllSGPR64
ArrayRef< MCPhysReg > getAllSGPR64(const MachineFunction &MF) const
Return all SGPR64 which satisfy the waves per execution unit requirement of the subtarget.
Definition: SIRegisterInfo.cpp:3168
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::SIRegisterInfo::hasSGPRs
static bool hasSGPRs(const TargetRegisterClass *RC)
Definition: SIRegisterInfo.h:228
llvm::SIRegisterInfo::SpilledReg
Definition: SIRegisterInfo.h:54
llvm::SIRegisterInfo::isSGPRClassID
bool isSGPRClassID(unsigned RCID) const
Definition: SIRegisterInfo.h:191
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:50
llvm::SIRegisterInfo::SIRegisterInfo
SIRegisterInfo(const GCNSubtarget &ST)
Definition: SIRegisterInfo.cpp:319
llvm::SIRegisterInfo::getVectorSuperClassForBitWidth
const LLVM_READONLY TargetRegisterClass * getVectorSuperClassForBitWidth(unsigned BitWidth) const
Definition: SIRegisterInfo.cpp:2733
llvm::SIRegisterInfo::getCSRFirstUseCost
unsigned getCSRFirstUseCost() const override
Definition: SIRegisterInfo.h:89
llvm::SIRegisterInfo::getWaveMaskRegClass
const TargetRegisterClass * getWaveMaskRegClass() const
Definition: SIRegisterInfo.h:331
llvm::SIRegisterInfo::getExec
MCRegister getExec() const
Definition: SIRegisterInfo.cpp:3031
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::SIRegisterInfo::getRegClassForSizeOnBank
const TargetRegisterClass * getRegClassForSizeOnBank(unsigned Size, const RegisterBank &Bank) const
Definition: SIRegisterInfo.cpp:2996
llvm::SIRegisterInfo::getEquivalentAGPRClass
const TargetRegisterClass * getEquivalentAGPRClass(const TargetRegisterClass *SRC) const
Definition: SIRegisterInfo.cpp:2798
llvm::SIRegisterInfo::materializeFrameBaseRegister
Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
Definition: SIRegisterInfo.cpp:806
llvm::SIRegisterInfo::spillSGPR
bool spillSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr, bool OnlyToVGPR=false) const
If OnlyToVGPR is true, this will only succeed if this.
Definition: SIRegisterInfo.cpp:1706
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::SIRegisterInfo::getAllAllocatableSRegMask
const uint32_t * getAllAllocatableSRegMask() const
Definition: SIRegisterInfo.cpp:525
llvm::SIRegisterInfo::isAsmClobberable
bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const override
Definition: SIRegisterInfo.cpp:720
llvm::SIRegisterInfo::getProperlyAlignedRC
const TargetRegisterClass * getProperlyAlignedRC(const TargetRegisterClass *RC) const
Definition: SIRegisterInfo.cpp:3144
llvm::SIRegisterInfo::requiresFrameIndexReplacementScavenging
bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:758
llvm::SIRegisterInfo::buildVGPRSpillLoadStore
void buildVGPRSpillLoadStore(SGPRSpillBuilder &SB, int Index, int Offset, bool IsLoad, bool IsKill=true) const
Definition: SIRegisterInfo.cpp:1673
llvm::SIRegisterInfo::findReachingDef
MachineInstr * findReachingDef(Register Reg, unsigned SubReg, MachineInstr &Use, MachineRegisterInfo &MRI, LiveIntervals *LIS) const
Definition: SIRegisterInfo.cpp:3057
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::SIRegisterInfo::getCrossCopyRegClass
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
Returns a legal register class to copy a register in the specified class to or from.
Definition: SIRegisterInfo.cpp:931
llvm::SIRegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:490
llvm::RegisterBank
This class implements the register bank concept.
Definition: RegisterBank.h:28
llvm::popcount
int popcount(T Value) noexcept
Count the number of set bits in a value.
Definition: bit.h:349
llvm::SIRegisterInfo::SpilledReg::hasReg
bool hasReg()
Definition: SIRegisterInfo.h:62
llvm::SIRegisterInfo::getLargestLegalSuperClass
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:436
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::SIRegisterInfo::getReturnAddressReg
MCRegister getReturnAddressReg(const MachineFunction &MF) const
Definition: SIRegisterInfo.cpp:2990
llvm::SIRegisterInfo::getRegClassForReg
const TargetRegisterClass * getRegClassForReg(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2900
llvm::SIRegisterInfo::isAGPR
bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2919
llvm::SIRegisterInfo::getHWRegIndex
unsigned getHWRegIndex(MCRegister Reg) const
Definition: SIRegisterInfo.h:168
llvm::SIRegisterInfo::getChannelFromSubReg
unsigned getChannelFromSubReg(unsigned SubReg) const
Definition: SIRegisterInfo.h:369
llvm::dwarf::Index
Index
Definition: Dwarf.h:550
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::SIRegisterInfo::getRegPressureLimit
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:2948
llvm::SIRegisterInfo::supportsBackwardScavenger
bool supportsBackwardScavenger() const override
Definition: SIRegisterInfo.h:152
llvm::SIRegisterInfo::SpilledReg::VGPR
Register VGPR
Definition: SIRegisterInfo.h:55
llvm::SIRegisterInfo::getNumChannelsFromSubReg
unsigned getNumChannelsFromSubReg(unsigned SubReg) const
Definition: SIRegisterInfo.h:374
llvm::SlotIndexes
SlotIndexes pass.
Definition: SlotIndexes.h:319
llvm::SIRegisterInfo::getSubRegFromChannel
static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs=1)
Definition: SIRegisterInfo.cpp:529
llvm::SIRegisterInfo::isSGPRClass
static bool isSGPRClass(const TargetRegisterClass *RC)
Definition: SIRegisterInfo.h:186
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:30
llvm::SIRegisterInfo::hasVGPRs
static bool hasVGPRs(const TargetRegisterClass *RC)
Definition: SIRegisterInfo.h:218
llvm::SIRegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Definition: SIRegisterInfo.cpp:415
llvm::SIRegisterInfo::getVCC
MCRegister getVCC() const
Definition: SIRegisterInfo.cpp:3027
llvm::BitVector
Definition: BitVector.h:75
llvm::SIRegisterInfo::getVGPR64Class
const TargetRegisterClass * getVGPR64Class() const
Definition: SIRegisterInfo.cpp:3035
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::LLT::getSizeInBits
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:159
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::SIRegisterInfo::eliminateSGPRToVGPRSpillFrameIndex
bool eliminateSGPRToVGPRSpillFrameIndex(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr) const
Special case of eliminateFrameIndex.
Definition: SIRegisterInfo.cpp:1975
llvm::SIRegisterInfo::isDivergentRegClass
bool isDivergentRegClass(const TargetRegisterClass *RC) const override
Definition: SIRegisterInfo.h:289
llvm::SIRegisterInfo::opCanUseLiteralConstant
bool opCanUseLiteralConstant(unsigned OpType) const
Definition: SIRegisterInfo.cpp:2858
llvm::SIRegisterInfo::isFrameOffsetLegal
bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
Definition: SIRegisterInfo.cpp:906
llvm::SIRegisterInfo::getBaseRegister
Register getBaseRegister() const
Definition: SIRegisterInfo.cpp:511
llvm::SIRegisterInfo::eliminateFrameIndex
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
Definition: SIRegisterInfo.cpp:2014
llvm::SIRegisterInfo::getAllVGPRRegMask
const uint32_t * getAllVGPRRegMask() const
Definition: SIRegisterInfo.cpp:513
llvm::SIRegisterInfo::SpilledReg::SpilledReg
SpilledReg()=default
llvm::SIRegisterInfo::shouldRewriteCopySrc
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
Definition: SIRegisterInfo.cpp:2834
llvm::SIRegisterInfo::shouldRealignStack
bool shouldRealignStack(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:725
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::SIRegisterInfo::getRegAsmName
StringRef getRegAsmName(MCRegister Reg) const override
Definition: SIRegisterInfo.cpp:2514
uint64_t
llvm::TargetRegisterClass::TSFlags
const uint8_t TSFlags
Configurable target specific flags.
Definition: TargetRegisterInfo.h:64
llvm::SIRegisterInfo::isVGPRClass
static bool isVGPRClass(const TargetRegisterClass *RC)
Definition: SIRegisterInfo.h:198
llvm::SIRegisterInfo::requiresFrameIndexScavenging
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:749
llvm::SIRegisterInfo::hasBasePointer
bool hasBasePointer(const MachineFunction &MF) const
Definition: SIRegisterInfo.cpp:504
llvm::SIRegisterInfo::getAllVectorRegMask
const uint32_t * getAllVectorRegMask() const
Definition: SIRegisterInfo.cpp:521
llvm::SIRegisterInfo::isSGPRReg
bool isSGPRReg(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2779
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::SIRegisterInfo::isVGPR
bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.cpp:2912
llvm::SIRegisterInfo::getBoolRC
const TargetRegisterClass * getBoolRC() const
Definition: SIRegisterInfo.h:326
llvm::SIRegisterInfo::getRegClassForOperandReg
const TargetRegisterClass * getRegClassForOperandReg(const MachineRegisterInfo &MRI, const MachineOperand &MO) const
Definition: SIRegisterInfo.cpp:2906
llvm::SIRegisterInfo::SpilledReg::Lane
int Lane
Definition: SIRegisterInfo.h:56
llvm::SIRegisterInfo::restoreSGPR
bool restoreSGPR(MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr, bool OnlyToVGPR=false) const
Definition: SIRegisterInfo.cpp:1826
llvm::SIRegisterInfo::getRegSplitParts
ArrayRef< int16_t > getRegSplitParts(const TargetRegisterClass *RC, unsigned EltSize) const
Definition: SIRegisterInfo.cpp:2884
llvm::HasVGPR
@ HasVGPR
Definition: SIDefines.h:20
llvm::HasSGPR
@ HasSGPR
Definition: SIDefines.h:22
llvm::SIRegisterInfo::getAllAGPRRegMask
const uint32_t * getAllAGPRRegMask() const
Definition: SIRegisterInfo.cpp:517
llvm::MachineFunction
Definition: MachineFunction.h:258
llvm::SIRegisterInfo::isVSSuperClass
bool isVSSuperClass(const TargetRegisterClass *RC) const
Definition: SIRegisterInfo.h:213
llvm::SIRegisterInfo::getNoPreservedMask
const uint32_t * getNoPreservedMask() const override
Definition: SIRegisterInfo.cpp:431
llvm::SIRegisterInfo::get32BitRegister
MCPhysReg get32BitRegister(MCPhysReg Reg) const
Definition: SIRegisterInfo.cpp:3111
llvm::SIRegisterInfo::hasVectorRegisters
static bool hasVectorRegisters(const TargetRegisterClass *RC)
Definition: SIRegisterInfo.h:233
llvm::ArrayRef< int16_t >
llvm::SIRegisterInfo::isVectorSuperClass
bool isVectorSuperClass(const TargetRegisterClass *RC) const
Definition: SIRegisterInfo.h:208
llvm::SIRegisterInfo::getNumCoveredRegs
static unsigned getNumCoveredRegs(LaneBitmask LM)
Definition: SIRegisterInfo.h:358
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::HasAGPR
@ HasAGPR
Definition: SIDefines.h:21
llvm::SIRegisterInfo::SpilledReg::hasLane
bool hasLane()
Definition: SIRegisterInfo.h:61
llvm::Offset
@ Offset
Definition: DWP.cpp:406
llvm::SIRegisterInfo::isProperlyAlignedRC
bool isProperlyAlignedRC(const TargetRegisterClass &RC) const
Definition: SIRegisterInfo.cpp:3128
llvm::SIRegisterInfo::spillSGPRToVGPR
bool spillSGPRToVGPR() const
Definition: SIRegisterInfo.h:69
uint32_t
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::LaneBitmask::getAsInteger
constexpr Type getAsInteger() const
Definition: LaneBitmask.h:74
llvm::SIRegisterInfo::getCalleeSavedRegsViaCopy
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
Definition: SIRegisterInfo.cpp:411
llvm::SIRegisterInfo::resolveFrameIndex
void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const override
Definition: SIRegisterInfo.cpp:857
llvm::SIRegisterInfo::SpilledReg::SpilledReg
SpilledReg(Register R, int L)
Definition: SIRegisterInfo.h:59
llvm::SIRegisterInfo::buildSpillLoadStore
void buildSpillLoadStore(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned LoadStoreOp, int Index, Register ValueReg, bool ValueIsKill, MCRegister ScratchOffsetReg, int64_t InstrOffset, MachineMemOperand *MMO, RegScavenger *RS, LivePhysRegs *LiveRegs=nullptr) const
Definition: SIRegisterInfo.cpp:1306
llvm::SGPRSpillBuilder
Definition: SIRegisterInfo.cpp:72
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SIRegisterInfo::getRegPressureSetLimit
unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override
Definition: SIRegisterInfo.cpp:2967
llvm::SIRegisterInfo::getAllSGPR32
ArrayRef< MCPhysReg > getAllSGPR32(const MachineFunction &MF) const
Return all SGPR32 which satisfy the waves per execution unit requirement of the subtarget.
Definition: SIRegisterInfo.cpp:3173
llvm::SIRegisterInfo::getRegClassForTypeOnBank
const TargetRegisterClass * getRegClassForTypeOnBank(LLT Ty, const RegisterBank &Bank) const
Definition: SIRegisterInfo.h:318
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
uint16_t
SIDefines.h
AMDGPUGenRegisterInfo
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::LiveIntervals
Definition: LiveIntervals.h:53
llvm::SIRegisterInfo::requiresRegisterScavenging
bool requiresRegisterScavenging(const MachineFunction &Fn) const override
Definition: SIRegisterInfo.cpp:738
llvm::SIRegisterInfo::getConstrainedRegClassForOperand
const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const override
Definition: SIRegisterInfo.cpp:3015
llvm::SIRegisterInfo::findUnusedRegister
MCRegister findUnusedRegister(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF, bool ReserveHighestVGPR=false) const
Returns a lowest register that is not used at any point in the function.
Definition: SIRegisterInfo.cpp:2868
llvm::SIRegisterInfo::getCompatibleSubRegClass
const TargetRegisterClass * getCompatibleSubRegClass(const TargetRegisterClass *SuperRC, const TargetRegisterClass *SubRC, unsigned SubIdx) const
Returns a register class which is compatible with SuperRC, such that a subregister exists with class ...
Definition: SIRegisterInfo.cpp:2816
llvm::SIRegisterInfo::getAGPRClassForBitWidth
const LLVM_READONLY TargetRegisterClass * getAGPRClassForBitWidth(unsigned BitWidth) const
Definition: SIRegisterInfo.cpp:2659
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::SIRegisterInfo::opCanUseInlineConstant
bool opCanUseInlineConstant(unsigned OpType) const
Definition: SIRegisterInfo.cpp:2825
llvm::SIRegisterInfo::shouldCoalesce
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
Definition: SIRegisterInfo.cpp:2927
llvm::SIRegisterInfo::isVectorRegister
bool isVectorRegister(const MachineRegisterInfo &MRI, Register Reg) const
Definition: SIRegisterInfo.h:285
llvm::SIRegisterInfo::spillEmergencySGPR
bool spillEmergencySGPR(MachineBasicBlock::iterator MI, MachineBasicBlock &RestoreMBB, Register SGPR, RegScavenger *RS) const
Definition: SIRegisterInfo.cpp:1903
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::SIRegisterInfo::getEquivalentSGPRClass
const TargetRegisterClass * getEquivalentSGPRClass(const TargetRegisterClass *VRC) const
Definition: SIRegisterInfo.cpp:2806
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::SIRegisterInfo::reservedPrivateSegmentBufferReg
MCRegister reservedPrivateSegmentBufferReg(const MachineFunction &MF) const
Return the end register initially reserved for the scratch buffer in case spilling is needed.
Definition: SIRegisterInfo.cpp:538
llvm::SIRegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
Definition: SIRegisterInfo.cpp:545
llvm::SIRegisterInfo::getPointerRegClass
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
Definition: SIRegisterInfo.cpp:922
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
llvm::SIRegisterInfo::hasAGPRs
static bool hasAGPRs(const TargetRegisterClass *RC)
Definition: SIRegisterInfo.h:223
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::SIRegisterInfo::getSGPRClassForBitWidth
static const LLVM_READONLY TargetRegisterClass * getSGPRClassForBitWidth(unsigned BitWidth)
Definition: SIRegisterInfo.cpp:2744
llvm::LLT
Definition: LowLevelTypeImpl.h:39