LLVM 19.0.0git
LiveRegUnits.h
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1//===- llvm/CodeGen/LiveRegUnits.h - Register Unit Set ----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// A set of register units. It is intended for register liveness tracking.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_LIVEREGUNITS_H
15#define LLVM_CODEGEN_LIVEREGUNITS_H
16
17#include "llvm/ADT/BitVector.h"
20#include "llvm/MC/LaneBitmask.h"
22#include <cstdint>
23
24namespace llvm {
25
26class MachineInstr;
27class MachineBasicBlock;
28
29/// A set of register units used to track register liveness.
31 const TargetRegisterInfo *TRI = nullptr;
32 BitVector Units;
33
34public:
35 /// Constructs a new empty LiveRegUnits set.
36 LiveRegUnits() = default;
37
38 /// Constructs and initialize an empty LiveRegUnits set.
40 init(TRI);
41 }
42
43 /// For a machine instruction \p MI, adds all register units used in
44 /// \p UsedRegUnits and defined or clobbered in \p ModifiedRegUnits. This is
45 /// useful when walking over a range of instructions to track registers
46 /// used or defined seperately.
48 LiveRegUnits &ModifiedRegUnits,
49 LiveRegUnits &UsedRegUnits,
50 const TargetRegisterInfo *TRI) {
51 for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
52 if (O->isRegMask())
53 ModifiedRegUnits.addRegsInMask(O->getRegMask());
54 if (!O->isReg())
55 continue;
56 Register Reg = O->getReg();
57 if (!Reg.isPhysical())
58 continue;
59 if (O->isDef()) {
60 // Some architectures (e.g. AArch64 XZR/WZR) have registers that are
61 // constant and may be used as destinations to indicate the generated
62 // value is discarded. No need to track such case as a def.
63 if (!TRI->isConstantPhysReg(Reg))
64 ModifiedRegUnits.addReg(Reg);
65 } else {
66 assert(O->isUse() && "Reg operand not a def and not a use");
67 UsedRegUnits.addReg(Reg);
68 }
69 }
70 }
71
72 /// Initialize and clear the set.
73 void init(const TargetRegisterInfo &TRI) {
74 this->TRI = &TRI;
75 Units.reset();
76 Units.resize(TRI.getNumRegUnits());
77 }
78
79 /// Clears the set.
80 void clear() { Units.reset(); }
81
82 /// Returns true if the set is empty.
83 bool empty() const { return Units.none(); }
84
85 /// Adds register units covered by physical register \p Reg.
87 for (MCRegUnit Unit : TRI->regunits(Reg))
88 Units.set(Unit);
89 }
90
91 /// Adds register units covered by physical register \p Reg that are
92 /// part of the lanemask \p Mask.
94 for (MCRegUnitMaskIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
95 LaneBitmask UnitMask = (*Unit).second;
96 if ((UnitMask & Mask).any())
97 Units.set((*Unit).first);
98 }
99 }
100
101 /// Removes all register units covered by physical register \p Reg.
103 for (MCRegUnit Unit : TRI->regunits(Reg))
104 Units.reset(Unit);
105 }
106
107 /// Removes register units not preserved by the regmask \p RegMask.
108 /// The regmask has the same format as the one in the RegMask machine operand.
109 void removeRegsNotPreserved(const uint32_t *RegMask);
110
111 /// Adds register units not preserved by the regmask \p RegMask.
112 /// The regmask has the same format as the one in the RegMask machine operand.
113 void addRegsInMask(const uint32_t *RegMask);
114
115 /// Returns true if no part of physical register \p Reg is live.
116 bool available(MCPhysReg Reg) const {
117 for (MCRegUnit Unit : TRI->regunits(Reg)) {
118 if (Units.test(Unit))
119 return false;
120 }
121 return true;
122 }
123
124 /// Updates liveness when stepping backwards over the instruction \p MI.
125 /// This removes all register units defined or clobbered in \p MI and then
126 /// adds the units used (as in use operands) in \p MI.
127 void stepBackward(const MachineInstr &MI);
128
129 /// Adds all register units used, defined or clobbered in \p MI.
130 /// This is useful when walking over a range of instruction to find registers
131 /// unused over the whole range.
132 void accumulate(const MachineInstr &MI);
133
134 /// Adds registers living out of block \p MBB.
135 /// Live out registers are the union of the live-in registers of the successor
136 /// blocks and pristine registers. Live out registers of the end block are the
137 /// callee saved registers.
138 void addLiveOuts(const MachineBasicBlock &MBB);
139
140 /// Adds registers living into block \p MBB.
141 void addLiveIns(const MachineBasicBlock &MBB);
142
143 /// Adds all register units marked in the bitvector \p RegUnits.
144 void addUnits(const BitVector &RegUnits) {
145 Units |= RegUnits;
146 }
147 /// Removes all register units marked in the bitvector \p RegUnits.
148 void removeUnits(const BitVector &RegUnits) {
149 Units.reset(RegUnits);
150 }
151 /// Return the internal bitvector representation of the set.
152 const BitVector &getBitVector() const {
153 return Units;
154 }
155
156private:
157 /// Adds pristine registers. Pristine registers are callee saved registers
158 /// that are unused in the function.
159 void addPristines(const MachineFunction &MF);
160};
161
162/// Returns an iterator range over all physical register and mask operands for
163/// \p MI and bundled instructions. This also skips any debug operands.
164inline iterator_range<
165 filter_iterator<ConstMIBundleOperands, bool (*)(const MachineOperand &)>>
167 auto Pred = [](const MachineOperand &MOP) {
168 return MOP.isRegMask() ||
169 (MOP.isReg() && !MOP.isDebug() && MOP.getReg().isPhysical());
170 };
172 static_cast<bool (*)(const MachineOperand &)>(Pred));
173}
174
175} // end namespace llvm
176
177#endif // LLVM_CODEGEN_LIVEREGUNITS_H
MachineBasicBlock & MBB
This file implements the BitVector class.
IRTranslator LLVM IR MI
A common definition of LaneBitmask for use in TableGen and CodeGen.
unsigned const TargetRegisterInfo * TRI
unsigned Reg
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool test(unsigned Idx) const
Definition: BitVector.h:461
BitVector & reset()
Definition: BitVector.h:392
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
Definition: BitVector.h:341
BitVector & set()
Definition: BitVector.h:351
bool none() const
none - Returns true if none of the bits are set.
Definition: BitVector.h:188
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
A set of register units used to track register liveness.
Definition: LiveRegUnits.h:30
static void accumulateUsedDefed(const MachineInstr &MI, LiveRegUnits &ModifiedRegUnits, LiveRegUnits &UsedRegUnits, const TargetRegisterInfo *TRI)
For a machine instruction MI, adds all register units used in UsedRegUnits and defined or clobbered i...
Definition: LiveRegUnits.h:47
LiveRegUnits(const TargetRegisterInfo &TRI)
Constructs and initialize an empty LiveRegUnits set.
Definition: LiveRegUnits.h:39
const BitVector & getBitVector() const
Return the internal bitvector representation of the set.
Definition: LiveRegUnits.h:152
void addRegMasked(MCPhysReg Reg, LaneBitmask Mask)
Adds register units covered by physical register Reg that are part of the lanemask Mask.
Definition: LiveRegUnits.h:93
bool available(MCPhysReg Reg) const
Returns true if no part of physical register Reg is live.
Definition: LiveRegUnits.h:116
void addRegsInMask(const uint32_t *RegMask)
Adds register units not preserved by the regmask RegMask.
void init(const TargetRegisterInfo &TRI)
Initialize and clear the set.
Definition: LiveRegUnits.h:73
LiveRegUnits()=default
Constructs a new empty LiveRegUnits set.
void stepBackward(const MachineInstr &MI)
Updates liveness when stepping backwards over the instruction MI.
void addReg(MCPhysReg Reg)
Adds register units covered by physical register Reg.
Definition: LiveRegUnits.h:86
void addLiveOuts(const MachineBasicBlock &MBB)
Adds registers living out of block MBB.
void addUnits(const BitVector &RegUnits)
Adds all register units marked in the bitvector RegUnits.
Definition: LiveRegUnits.h:144
bool empty() const
Returns true if the set is empty.
Definition: LiveRegUnits.h:83
void addLiveIns(const MachineBasicBlock &MBB)
Adds registers living into block MBB.
void removeUnits(const BitVector &RegUnits)
Removes all register units marked in the bitvector RegUnits.
Definition: LiveRegUnits.h:148
void removeRegsNotPreserved(const uint32_t *RegMask)
Removes register units not preserved by the regmask RegMask.
void removeReg(MCPhysReg Reg)
Removes all register units covered by physical register Reg.
Definition: LiveRegUnits.h:102
void clear()
Clears the set.
Definition: LiveRegUnits.h:80
void accumulate(const MachineInstr &MI)
Adds all register units used, defined or clobbered in MI.
MCRegUnitMaskIterator enumerates a list of register units and their associated lane masks for Reg.
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
iterator_range< filter_iterator< ConstMIBundleOperands, bool(*)(const MachineOperand &)> > phys_regs_and_masks(const MachineInstr &MI)
Returns an iterator range over all physical register and mask operands for MI and bundled instruction...
Definition: LiveRegUnits.h:166
iterator_range< filter_iterator< detail::IterOfRange< RangeT >, PredicateT > > make_filter_range(RangeT &&Range, PredicateT Pred)
Convenience function that takes a range of elements and a predicate, and return a new filter_iterator...
Definition: STLExtras.h:581
iterator_range< ConstMIBundleOperands > const_mi_bundle_ops(const MachineInstr &MI)
filter_iterator_impl< WrappedIteratorT, PredicateT, typename detail::fwd_or_bidi_tag< WrappedIteratorT >::type > filter_iterator
Defines filter_iterator to a suitable specialization of filter_iterator_impl, based on the underlying...
Definition: STLExtras.h:570