LLVM  14.0.0git
TargetRegisterInfo.h
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1 //==- CodeGen/TargetRegisterInfo.h - Target Register Information -*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes an abstract interface used to get information about a
10 // target machines register file. This information is used for a variety of
11 // purposed, especially register allocation.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_TARGETREGISTERINFO_H
16 #define LLVM_CODEGEN_TARGETREGISTERINFO_H
17 
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/StringRef.h"
23 #include "llvm/IR/CallingConv.h"
24 #include "llvm/MC/LaneBitmask.h"
25 #include "llvm/MC/MCRegisterInfo.h"
29 #include "llvm/Support/Printable.h"
30 #include <cassert>
31 #include <cstdint>
32 #include <functional>
33 
34 namespace llvm {
35 
36 class BitVector;
37 class DIExpression;
38 class LiveRegMatrix;
39 class MachineFunction;
40 class MachineInstr;
41 class RegScavenger;
42 class VirtRegMap;
43 class LiveIntervals;
44 class LiveInterval;
45 
47 public:
48  using iterator = const MCPhysReg *;
49  using const_iterator = const MCPhysReg *;
50  using sc_iterator = const TargetRegisterClass* const *;
51 
52  // Instance variables filled by tablegen, do not use!
57  /// Classes with a higher priority value are assigned first by register
58  /// allocators using a greedy heuristic. The value is in the range [0,63].
59  const uint8_t AllocationPriority;
60  /// Configurable target specific flags.
61  const uint8_t TSFlags;
62  /// Whether the class supports two (or more) disjunct subregister indices.
63  const bool HasDisjunctSubRegs;
64  /// Whether a combination of subregisters can cover every register in the
65  /// class. See also the CoveredBySubRegs description in Target.td.
66  const bool CoveredBySubRegs;
69 
70  /// Return the register class ID number.
71  unsigned getID() const { return MC->getID(); }
72 
73  /// begin/end - Return all of the registers in this class.
74  ///
75  iterator begin() const { return MC->begin(); }
76  iterator end() const { return MC->end(); }
77 
78  /// Return the number of registers in this class.
79  unsigned getNumRegs() const { return MC->getNumRegs(); }
80 
82  getRegisters() const {
83  return make_range(MC->begin(), MC->end());
84  }
85 
86  /// Return the specified register in the class.
87  MCRegister getRegister(unsigned i) const {
88  return MC->getRegister(i);
89  }
90 
91  /// Return true if the specified register is included in this register class.
92  /// This does not include virtual registers.
93  bool contains(Register Reg) const {
94  /// FIXME: Historically this function has returned false when given vregs
95  /// but it should probably only receive physical registers
96  if (!Reg.isPhysical())
97  return false;
98  return MC->contains(Reg.asMCReg());
99  }
100 
101  /// Return true if both registers are in this class.
102  bool contains(Register Reg1, Register Reg2) const {
103  /// FIXME: Historically this function has returned false when given a vregs
104  /// but it should probably only receive physical registers
105  if (!Reg1.isPhysical() || !Reg2.isPhysical())
106  return false;
107  return MC->contains(Reg1.asMCReg(), Reg2.asMCReg());
108  }
109 
110  /// Return the cost of copying a value between two registers in this class.
111  /// A negative number means the register class is very expensive
112  /// to copy e.g. status flag register classes.
113  int getCopyCost() const { return MC->getCopyCost(); }
114 
115  /// Return true if this register class may be used to create virtual
116  /// registers.
117  bool isAllocatable() const { return MC->isAllocatable(); }
118 
119  /// Return true if the specified TargetRegisterClass
120  /// is a proper sub-class of this TargetRegisterClass.
121  bool hasSubClass(const TargetRegisterClass *RC) const {
122  return RC != this && hasSubClassEq(RC);
123  }
124 
125  /// Returns true if RC is a sub-class of or equal to this class.
126  bool hasSubClassEq(const TargetRegisterClass *RC) const {
127  unsigned ID = RC->getID();
128  return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
129  }
130 
131  /// Return true if the specified TargetRegisterClass is a
132  /// proper super-class of this TargetRegisterClass.
133  bool hasSuperClass(const TargetRegisterClass *RC) const {
134  return RC->hasSubClass(this);
135  }
136 
137  /// Returns true if RC is a super-class of or equal to this class.
138  bool hasSuperClassEq(const TargetRegisterClass *RC) const {
139  return RC->hasSubClassEq(this);
140  }
141 
142  /// Returns a bit vector of subclasses, including this one.
143  /// The vector is indexed by class IDs.
144  ///
145  /// To use it, consider the returned array as a chunk of memory that
146  /// contains an array of bits of size NumRegClasses. Each 32-bit chunk
147  /// contains a bitset of the ID of the subclasses in big-endian style.
148 
149  /// I.e., the representation of the memory from left to right at the
150  /// bit level looks like:
151  /// [31 30 ... 1 0] [ 63 62 ... 33 32] ...
152  /// [ XXX NumRegClasses NumRegClasses - 1 ... ]
153  /// Where the number represents the class ID and XXX bits that
154  /// should be ignored.
155  ///
156  /// See the implementation of hasSubClassEq for an example of how it
157  /// can be used.
158  const uint32_t *getSubClassMask() const {
159  return SubClassMask;
160  }
161 
162  /// Returns a 0-terminated list of sub-register indices that project some
163  /// super-register class into this register class. The list has an entry for
164  /// each Idx such that:
165  ///
166  /// There exists SuperRC where:
167  /// For all Reg in SuperRC:
168  /// this->contains(Reg:Idx)
169  const uint16_t *getSuperRegIndices() const {
170  return SuperRegIndices;
171  }
172 
173  /// Returns a NULL-terminated list of super-classes. The
174  /// classes are ordered by ID which is also a topological ordering from large
175  /// to small classes. The list does NOT include the current class.
177  return SuperClasses;
178  }
179 
180  /// Return true if this TargetRegisterClass is a subset
181  /// class of at least one other TargetRegisterClass.
182  bool isASubClass() const {
183  return SuperClasses[0] != nullptr;
184  }
185 
186  /// Returns the preferred order for allocating registers from this register
187  /// class in MF. The raw order comes directly from the .td file and may
188  /// include reserved registers that are not allocatable.
189  /// Register allocators should also make sure to allocate
190  /// callee-saved registers only after all the volatiles are used. The
191  /// RegisterClassInfo class provides filtered allocation orders with
192  /// callee-saved registers moved to the end.
193  ///
194  /// The MachineFunction argument can be used to tune the allocatable
195  /// registers based on the characteristics of the function, subtarget, or
196  /// other criteria.
197  ///
198  /// By default, this method returns all registers in the class.
200  return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs());
201  }
202 
203  /// Returns the combination of all lane masks of register in this class.
204  /// The lane masks of the registers are the combination of all lane masks
205  /// of their subregisters. Returns 1 if there are no subregisters.
207  return LaneMask;
208  }
209 };
210 
211 /// Extra information, not in MCRegisterDesc, about registers.
212 /// These are used by codegen, not by MC.
214  const uint8_t *CostPerUse; // Extra cost of instructions using register.
215  unsigned NumCosts; // Number of cost values associated with each register.
216  const bool
217  *InAllocatableClass; // Register belongs to an allocatable regclass.
218 };
219 
220 /// Each TargetRegisterClass has a per register weight, and weight
221 /// limit which must be less than the limits of its pressure sets.
223  unsigned RegWeight;
224  unsigned WeightLimit;
225 };
226 
227 /// TargetRegisterInfo base class - We assume that the target defines a static
228 /// array of TargetRegisterDesc objects that represent all of the machine
229 /// registers that the target has. As such, we simply have to track a pointer
230 /// to this array so that we can turn register number into a register
231 /// descriptor.
232 ///
234 public:
235  using regclass_iterator = const TargetRegisterClass * const *;
237  struct RegClassInfo {
240  };
241 private:
242  const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
243  const char *const *SubRegIndexNames; // Names of subreg indexes.
244  // Pointer to array of lane masks, one per sub-reg index.
245  const LaneBitmask *SubRegIndexLaneMasks;
246 
247  regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
248  LaneBitmask CoveringLanes;
249  const RegClassInfo *const RCInfos;
250  unsigned HwMode;
251 
252 protected:
254  regclass_iterator RCB,
255  regclass_iterator RCE,
256  const char *const *SRINames,
257  const LaneBitmask *SRILaneMasks,
258  LaneBitmask CoveringLanes,
259  const RegClassInfo *const RCIs,
260  unsigned Mode = 0);
261  virtual ~TargetRegisterInfo();
262 
263 public:
264  // Register numbers can represent physical registers, virtual registers, and
265  // sometimes stack slots. The unsigned values are divided into these ranges:
266  //
267  // 0 Not a register, can be used as a sentinel.
268  // [1;2^30) Physical registers assigned by TableGen.
269  // [2^30;2^31) Stack slots. (Rarely used.)
270  // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
271  //
272  // Further sentinels can be allocated from the small negative integers.
273  // DenseMapInfo<unsigned> uses -1u and -2u.
274 
275  /// Return the size in bits of a register from class RC.
276  unsigned getRegSizeInBits(const TargetRegisterClass &RC) const {
277  return getRegClassInfo(RC).RegSize;
278  }
279 
280  /// Return the size in bytes of the stack slot allocated to hold a spilled
281  /// copy of a register from class RC.
282  unsigned getSpillSize(const TargetRegisterClass &RC) const {
283  return getRegClassInfo(RC).SpillSize / 8;
284  }
285 
286  /// Return the minimum required alignment in bytes for a spill slot for
287  /// a register of this class.
289  return Align(getRegClassInfo(RC).SpillAlignment / 8);
290  }
291 
292  /// Return true if the given TargetRegisterClass has the ValueType T.
293  bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const {
294  for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; ++I)
295  if (MVT(*I) == T)
296  return true;
297  return false;
298  }
299 
300  /// Return true if the given TargetRegisterClass is compatible with LLT T.
301  bool isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) const {
302  for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; ++I) {
303  MVT VT(*I);
304  if (VT == MVT::Untyped)
305  return true;
306 
307  if (LLT(VT) == T)
308  return true;
309  }
310  return false;
311  }
312 
313  /// Loop over all of the value types that can be represented by values
314  /// in the given register class.
316  return getRegClassInfo(RC).VTList;
317  }
318 
321  while (*I != MVT::Other)
322  ++I;
323  return I;
324  }
325 
326  /// Returns the Register Class of a physical register of the given type,
327  /// picking the most sub register class of the right type that contains this
328  /// physreg.
330  MVT VT = MVT::Other) const;
331 
332  /// Returns the Register Class of a physical register of the given type,
333  /// picking the most sub register class of the right type that contains this
334  /// physreg. If there is no register class compatible with the given type,
335  /// returns nullptr.
337  LLT Ty = LLT()) const;
338 
339  /// Return the maximal subclass of the given register class that is
340  /// allocatable or NULL.
341  const TargetRegisterClass *
342  getAllocatableClass(const TargetRegisterClass *RC) const;
343 
344  /// Returns a bitset indexed by register number indicating if a register is
345  /// allocatable or not. If a register class is specified, returns the subset
346  /// for the class.
348  const TargetRegisterClass *RC = nullptr) const;
349 
350  /// Get a list of cost values for all registers that correspond to the index
351  /// returned by RegisterCostTableIndex.
353  unsigned Idx = getRegisterCostTableIndex(MF);
354  unsigned NumRegs = getNumRegs();
355  assert(Idx < InfoDesc->NumCosts && "CostPerUse index out of bounds");
356 
357  return makeArrayRef(&InfoDesc->CostPerUse[Idx * NumRegs], NumRegs);
358  }
359 
360  /// Return true if the register is in the allocation of any register class.
361  bool isInAllocatableClass(MCRegister RegNo) const {
362  return InfoDesc->InAllocatableClass[RegNo];
363  }
364 
365  /// Return the human-readable symbolic target-specific
366  /// name for the specified SubRegIndex.
367  const char *getSubRegIndexName(unsigned SubIdx) const {
368  assert(SubIdx && SubIdx < getNumSubRegIndices() &&
369  "This is not a subregister index");
370  return SubRegIndexNames[SubIdx-1];
371  }
372 
373  /// Return a bitmask representing the parts of a register that are covered by
374  /// SubIdx \see LaneBitmask.
375  ///
376  /// SubIdx == 0 is allowed, it has the lane mask ~0u.
377  LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const {
378  assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index");
379  return SubRegIndexLaneMasks[SubIdx];
380  }
381 
382  /// Try to find one or more subregister indexes to cover \p LaneMask.
383  ///
384  /// If this is possible, returns true and appends the best matching set of
385  /// indexes to \p Indexes. If this is not possible, returns false.
387  const TargetRegisterClass *RC,
388  LaneBitmask LaneMask,
389  SmallVectorImpl<unsigned> &Indexes) const;
390 
391  /// The lane masks returned by getSubRegIndexLaneMask() above can only be
392  /// used to determine if sub-registers overlap - they can't be used to
393  /// determine if a set of sub-registers completely cover another
394  /// sub-register.
395  ///
396  /// The X86 general purpose registers have two lanes corresponding to the
397  /// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have
398  /// lane masks '3', but the sub_16bit sub-register doesn't fully cover the
399  /// sub_32bit sub-register.
400  ///
401  /// On the other hand, the ARM NEON lanes fully cover their registers: The
402  /// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes.
403  /// This is related to the CoveredBySubRegs property on register definitions.
404  ///
405  /// This function returns a bit mask of lanes that completely cover their
406  /// sub-registers. More precisely, given:
407  ///
408  /// Covering = getCoveringLanes();
409  /// MaskA = getSubRegIndexLaneMask(SubA);
410  /// MaskB = getSubRegIndexLaneMask(SubB);
411  ///
412  /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by
413  /// SubB.
414  LaneBitmask getCoveringLanes() const { return CoveringLanes; }
415 
416  /// Returns true if the two registers are equal or alias each other.
417  /// The registers may be virtual registers.
418  bool regsOverlap(Register regA, Register regB) const {
419  if (regA == regB) return true;
420  if (!regA.isPhysical() || !regB.isPhysical())
421  return false;
422 
423  // Regunits are numerically ordered. Find a common unit.
424  MCRegUnitIterator RUA(regA.asMCReg(), this);
425  MCRegUnitIterator RUB(regB.asMCReg(), this);
426  do {
427  if (*RUA == *RUB) return true;
428  if (*RUA < *RUB) ++RUA;
429  else ++RUB;
430  } while (RUA.isValid() && RUB.isValid());
431  return false;
432  }
433 
434  /// Returns true if Reg contains RegUnit.
435  bool hasRegUnit(MCRegister Reg, Register RegUnit) const {
436  for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units)
437  if (Register(*Units) == RegUnit)
438  return true;
439  return false;
440  }
441 
442  /// Returns the original SrcReg unless it is the target of a copy-like
443  /// operation, in which case we chain backwards through all such operations
444  /// to the ultimate source register. If a physical register is encountered,
445  /// we stop the search.
446  virtual Register lookThruCopyLike(Register SrcReg,
447  const MachineRegisterInfo *MRI) const;
448 
449  /// Find the original SrcReg unless it is the target of a copy-like operation,
450  /// in which case we chain backwards through all such operations to the
451  /// ultimate source register. If a physical register is encountered, we stop
452  /// the search.
453  /// Return the original SrcReg if all the definitions in the chain only have
454  /// one user and not a physical register.
455  virtual Register
457  const MachineRegisterInfo *MRI) const;
458 
459  /// Return a null-terminated list of all of the callee-saved registers on
460  /// this target. The register should be in the order of desired callee-save
461  /// stack frame offset. The first register is closest to the incoming stack
462  /// pointer if stack grows down, and vice versa.
463  /// Notice: This function does not take into account disabled CSRs.
464  /// In most cases you will want to use instead the function
465  /// getCalleeSavedRegs that is implemented in MachineRegisterInfo.
466  virtual const MCPhysReg*
467  getCalleeSavedRegs(const MachineFunction *MF) const = 0;
468 
469  /// Return a mask of call-preserved registers for the given calling convention
470  /// on the current function. The mask should include all call-preserved
471  /// aliases. This is used by the register allocator to determine which
472  /// registers can be live across a call.
473  ///
474  /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
475  /// A set bit indicates that all bits of the corresponding register are
476  /// preserved across the function call. The bit mask is expected to be
477  /// sub-register complete, i.e. if A is preserved, so are all its
478  /// sub-registers.
479  ///
480  /// Bits are numbered from the LSB, so the bit for physical register Reg can
481  /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
482  ///
483  /// A NULL pointer means that no register mask will be used, and call
484  /// instructions should use implicit-def operands to indicate call clobbered
485  /// registers.
486  ///
488  CallingConv::ID) const {
489  // The default mask clobbers everything. All targets should override.
490  return nullptr;
491  }
492 
493  /// Return a register mask for the registers preserved by the unwinder,
494  /// or nullptr if no custom mask is needed.
495  virtual const uint32_t *
497  return nullptr;
498  }
499 
500  /// Return a register mask that clobbers everything.
501  virtual const uint32_t *getNoPreservedMask() const {
502  llvm_unreachable("target does not provide no preserved mask");
503  }
504 
505  /// Return a list of all of the registers which are clobbered "inside" a call
506  /// to the given function. For example, these might be needed for PLT
507  /// sequences of long-branch veneers.
508  virtual ArrayRef<MCPhysReg>
510  return {};
511  }
512 
513  /// Return true if all bits that are set in mask \p mask0 are also set in
514  /// \p mask1.
515  bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const;
516 
517  /// Return all the call-preserved register masks defined for this target.
518  virtual ArrayRef<const uint32_t *> getRegMasks() const = 0;
519  virtual ArrayRef<const char *> getRegMaskNames() const = 0;
520 
521  /// Returns a bitset indexed by physical register number indicating if a
522  /// register is a special register that has particular uses and should be
523  /// considered unavailable at all times, e.g. stack pointer, return address.
524  /// A reserved register:
525  /// - is not allocatable
526  /// - is considered always live
527  /// - is ignored by liveness tracking
528  /// It is often necessary to reserve the super registers of a reserved
529  /// register as well, to avoid them getting allocated indirectly. You may use
530  /// markSuperRegs() and checkAllSuperRegsMarked() in this case.
531  virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
532 
533  /// Returns false if we can't guarantee that Physreg, specified as an IR asm
534  /// clobber constraint, will be preserved across the statement.
535  virtual bool isAsmClobberable(const MachineFunction &MF,
536  MCRegister PhysReg) const {
537  return true;
538  }
539 
540  /// Returns true if PhysReg cannot be written to in inline asm statements.
541  virtual bool isInlineAsmReadOnlyReg(const MachineFunction &MF,
542  unsigned PhysReg) const {
543  return false;
544  }
545 
546  /// Returns true if PhysReg is unallocatable and constant throughout the
547  /// function. Used by MachineRegisterInfo::isConstantPhysReg().
548  virtual bool isConstantPhysReg(MCRegister PhysReg) const { return false; }
549 
550  /// Returns true if the register class is considered divergent.
551  virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const {
552  return false;
553  }
554 
555  /// Physical registers that may be modified within a function but are
556  /// guaranteed to be restored before any uses. This is useful for targets that
557  /// have call sequences where a GOT register may be updated by the caller
558  /// prior to a call and is guaranteed to be restored (also by the caller)
559  /// after the call.
560  virtual bool isCallerPreservedPhysReg(MCRegister PhysReg,
561  const MachineFunction &MF) const {
562  return false;
563  }
564 
565  /// This is a wrapper around getCallPreservedMask().
566  /// Return true if the register is preserved after the call.
567  virtual bool isCalleeSavedPhysReg(MCRegister PhysReg,
568  const MachineFunction &MF) const;
569 
570  /// Prior to adding the live-out mask to a stackmap or patchpoint
571  /// instruction, provide the target the opportunity to adjust it (mainly to
572  /// remove pseudo-registers that should be ignored).
573  virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const {}
574 
575  /// Return a super-register of the specified register
576  /// Reg so its sub-register of index SubIdx is Reg.
578  const TargetRegisterClass *RC) const {
579  return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
580  }
581 
582  /// Return a subclass of the specified register
583  /// class A so that each register in it has a sub-register of the
584  /// specified sub-register index which is in the specified register class B.
585  ///
586  /// TableGen will synthesize missing A sub-classes.
587  virtual const TargetRegisterClass *
589  const TargetRegisterClass *B, unsigned Idx) const;
590 
591  // For a copy-like instruction that defines a register of class DefRC with
592  // subreg index DefSubReg, reading from another source with class SrcRC and
593  // subregister SrcSubReg return true if this is a preferable copy
594  // instruction or an earlier use should be used.
595  virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
596  unsigned DefSubReg,
597  const TargetRegisterClass *SrcRC,
598  unsigned SrcSubReg) const;
599 
600  /// Returns the largest legal sub-class of RC that
601  /// supports the sub-register index Idx.
602  /// If no such sub-class exists, return NULL.
603  /// If all registers in RC already have an Idx sub-register, return RC.
604  ///
605  /// TableGen generates a version of this function that is good enough in most
606  /// cases. Targets can override if they have constraints that TableGen
607  /// doesn't understand. For example, the x86 sub_8bit sub-register index is
608  /// supported by the full GR32 register class in 64-bit mode, but only by the
609  /// GR32_ABCD regiister class in 32-bit mode.
610  ///
611  /// TableGen will synthesize missing RC sub-classes.
612  virtual const TargetRegisterClass *
613  getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
614  assert(Idx == 0 && "Target has no sub-registers");
615  return RC;
616  }
617 
618  /// Return the subregister index you get from composing
619  /// two subregister indices.
620  ///
621  /// The special null sub-register index composes as the identity.
622  ///
623  /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
624  /// returns c. Note that composeSubRegIndices does not tell you about illegal
625  /// compositions. If R does not have a subreg a, or R:a does not have a subreg
626  /// b, composeSubRegIndices doesn't tell you.
627  ///
628  /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
629  /// ssub_0:S0 - ssub_3:S3 subregs.
630  /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
631  unsigned composeSubRegIndices(unsigned a, unsigned b) const {
632  if (!a) return b;
633  if (!b) return a;
634  return composeSubRegIndicesImpl(a, b);
635  }
636 
637  /// Transforms a LaneMask computed for one subregister to the lanemask that
638  /// would have been computed when composing the subsubregisters with IdxA
639  /// first. @sa composeSubRegIndices()
641  LaneBitmask Mask) const {
642  if (!IdxA)
643  return Mask;
644  return composeSubRegIndexLaneMaskImpl(IdxA, Mask);
645  }
646 
647  /// Transform a lanemask given for a virtual register to the corresponding
648  /// lanemask before using subregister with index \p IdxA.
649  /// This is the reverse of composeSubRegIndexLaneMask(), assuming Mask is a
650  /// valie lane mask (no invalid bits set) the following holds:
651  /// X0 = composeSubRegIndexLaneMask(Idx, Mask)
652  /// X1 = reverseComposeSubRegIndexLaneMask(Idx, X0)
653  /// => X1 == Mask
655  LaneBitmask LaneMask) const {
656  if (!IdxA)
657  return LaneMask;
658  return reverseComposeSubRegIndexLaneMaskImpl(IdxA, LaneMask);
659  }
660 
661  /// Debugging helper: dump register in human readable form to dbgs() stream.
662  static void dumpReg(Register Reg, unsigned SubRegIndex = 0,
663  const TargetRegisterInfo *TRI = nullptr);
664 
665 protected:
666  /// Overridden by TableGen in targets that have sub-registers.
667  virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const {
668  llvm_unreachable("Target has no sub-registers");
669  }
670 
671  /// Overridden by TableGen in targets that have sub-registers.
672  virtual LaneBitmask
674  llvm_unreachable("Target has no sub-registers");
675  }
676 
678  LaneBitmask) const {
679  llvm_unreachable("Target has no sub-registers");
680  }
681 
682  /// Return the register cost table index. This implementation is sufficient
683  /// for most architectures and can be overriden by targets in case there are
684  /// multiple cost values associated with each register.
685  virtual unsigned getRegisterCostTableIndex(const MachineFunction &MF) const {
686  return 0;
687  }
688 
689 public:
690  /// Find a common super-register class if it exists.
691  ///
692  /// Find a register class, SuperRC and two sub-register indices, PreA and
693  /// PreB, such that:
694  ///
695  /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
696  ///
697  /// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
698  ///
699  /// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).
700  ///
701  /// SuperRC will be chosen such that no super-class of SuperRC satisfies the
702  /// requirements, and there is no register class with a smaller spill size
703  /// that satisfies the requirements.
704  ///
705  /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
706  ///
707  /// Either of the PreA and PreB sub-register indices may be returned as 0. In
708  /// that case, the returned register class will be a sub-class of the
709  /// corresponding argument register class.
710  ///
711  /// The function returns NULL if no register class can be found.
712  const TargetRegisterClass*
713  getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
714  const TargetRegisterClass *RCB, unsigned SubB,
715  unsigned &PreA, unsigned &PreB) const;
716 
717  //===--------------------------------------------------------------------===//
718  // Register Class Information
719  //
720 protected:
722  return RCInfos[getNumRegClasses() * HwMode + RC.getID()];
723  }
724 
725 public:
726  /// Register class iterators
727  regclass_iterator regclass_begin() const { return RegClassBegin; }
728  regclass_iterator regclass_end() const { return RegClassEnd; }
731  }
732 
733  unsigned getNumRegClasses() const {
734  return (unsigned)(regclass_end()-regclass_begin());
735  }
736 
737  /// Returns the register class associated with the enumeration value.
738  /// See class MCOperandInfo.
739  const TargetRegisterClass *getRegClass(unsigned i) const {
740  assert(i < getNumRegClasses() && "Register Class ID out of range");
741  return RegClassBegin[i];
742  }
743 
744  /// Returns the name of the register class.
745  const char *getRegClassName(const TargetRegisterClass *Class) const {
746  return MCRegisterInfo::getRegClassName(Class->MC);
747  }
748 
749  /// Find the largest common subclass of A and B.
750  /// Return NULL if there is no common subclass.
751  const TargetRegisterClass *
753  const TargetRegisterClass *B) const;
754 
755  /// Returns a TargetRegisterClass used for pointer values.
756  /// If a target supports multiple different pointer register classes,
757  /// kind specifies which one is indicated.
758  virtual const TargetRegisterClass *
759  getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const {
760  llvm_unreachable("Target didn't implement getPointerRegClass!");
761  }
762 
763  /// Returns a legal register class to copy a register in the specified class
764  /// to or from. If it is possible to copy the register directly without using
765  /// a cross register class copy, return the specified RC. Returns NULL if it
766  /// is not possible to copy between two registers of the specified class.
767  virtual const TargetRegisterClass *
769  return RC;
770  }
771 
772  /// Returns the largest super class of RC that is legal to use in the current
773  /// sub-target and has the same spill size.
774  /// The returned register class can be used to create virtual registers which
775  /// means that all its registers can be copied and spilled.
776  virtual const TargetRegisterClass *
778  const MachineFunction &) const {
779  /// The default implementation is very conservative and doesn't allow the
780  /// register allocator to inflate register classes.
781  return RC;
782  }
783 
784  /// Return the register pressure "high water mark" for the specific register
785  /// class. The scheduler is in high register pressure mode (for the specific
786  /// register class) if it goes over the limit.
787  ///
788  /// Note: this is the old register pressure model that relies on a manually
789  /// specified representative register class per value type.
790  virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
791  MachineFunction &MF) const {
792  return 0;
793  }
794 
795  /// Return a heuristic for the machine scheduler to compare the profitability
796  /// of increasing one register pressure set versus another. The scheduler
797  /// will prefer increasing the register pressure of the set which returns
798  /// the largest value for this function.
799  virtual unsigned getRegPressureSetScore(const MachineFunction &MF,
800  unsigned PSetID) const {
801  return PSetID;
802  }
803 
804  /// Get the weight in units of pressure for this register class.
805  virtual const RegClassWeight &getRegClassWeight(
806  const TargetRegisterClass *RC) const = 0;
807 
808  /// Returns size in bits of a phys/virtual/generic register.
809  unsigned getRegSizeInBits(Register Reg, const MachineRegisterInfo &MRI) const;
810 
811  /// Get the weight in units of pressure for this register unit.
812  virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
813 
814  /// Get the number of dimensions of register pressure.
815  virtual unsigned getNumRegPressureSets() const = 0;
816 
817  /// Get the name of this register unit pressure set.
818  virtual const char *getRegPressureSetName(unsigned Idx) const = 0;
819 
820  /// Get the register unit pressure limit for this dimension.
821  /// This limit must be adjusted dynamically for reserved registers.
822  virtual unsigned getRegPressureSetLimit(const MachineFunction &MF,
823  unsigned Idx) const = 0;
824 
825  /// Get the dimensions of register pressure impacted by this register class.
826  /// Returns a -1 terminated array of pressure set IDs.
827  virtual const int *getRegClassPressureSets(
828  const TargetRegisterClass *RC) const = 0;
829 
830  /// Get the dimensions of register pressure impacted by this register unit.
831  /// Returns a -1 terminated array of pressure set IDs.
832  virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
833 
834  /// Get a list of 'hint' registers that the register allocator should try
835  /// first when allocating a physical register for the virtual register
836  /// VirtReg. These registers are effectively moved to the front of the
837  /// allocation order. If true is returned, regalloc will try to only use
838  /// hints to the greatest extent possible even if it means spilling.
839  ///
840  /// The Order argument is the allocation order for VirtReg's register class
841  /// as returned from RegisterClassInfo::getOrder(). The hint registers must
842  /// come from Order, and they must not be reserved.
843  ///
844  /// The default implementation of this function will only add target
845  /// independent register allocation hints. Targets that override this
846  /// function should typically call this default implementation as well and
847  /// expect to see generic copy hints added.
848  virtual bool
851  const MachineFunction &MF,
852  const VirtRegMap *VRM = nullptr,
853  const LiveRegMatrix *Matrix = nullptr) const;
854 
855  /// A callback to allow target a chance to update register allocation hints
856  /// when a register is "changed" (e.g. coalesced) to another register.
857  /// e.g. On ARM, some virtual registers should target register pairs,
858  /// if one of pair is coalesced to another register, the allocation hint of
859  /// the other half of the pair should be changed to point to the new register.
860  virtual void updateRegAllocHint(Register Reg, Register NewReg,
861  MachineFunction &MF) const {
862  // Do nothing.
863  }
864 
865  /// Allow the target to reverse allocation order of local live ranges. This
866  /// will generally allocate shorter local live ranges first. For targets with
867  /// many registers, this could reduce regalloc compile time by a large
868  /// factor. It is disabled by default for three reasons:
869  /// (1) Top-down allocation is simpler and easier to debug for targets that
870  /// don't benefit from reversing the order.
871  /// (2) Bottom-up allocation could result in poor evicition decisions on some
872  /// targets affecting the performance of compiled code.
873  /// (3) Bottom-up allocation is no longer guaranteed to optimally color.
874  virtual bool reverseLocalAssignment() const { return false; }
875 
876  /// Allow the target to override the cost of using a callee-saved register for
877  /// the first time. Default value of 0 means we will use a callee-saved
878  /// register if it is available.
879  virtual unsigned getCSRFirstUseCost() const { return 0; }
880 
881  /// Returns true if the target requires (and can make use of) the register
882  /// scavenger.
883  virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
884  return false;
885  }
886 
887  /// Returns true if the target wants to use frame pointer based accesses to
888  /// spill to the scavenger emergency spill slot.
889  virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
890  return true;
891  }
892 
893  /// Returns true if the target requires post PEI scavenging of registers for
894  /// materializing frame index constants.
895  virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
896  return false;
897  }
898 
899  /// Returns true if the target requires using the RegScavenger directly for
900  /// frame elimination despite using requiresFrameIndexScavenging.
902  const MachineFunction &MF) const {
903  return false;
904  }
905 
906  /// Returns true if the target wants the LocalStackAllocation pass to be run
907  /// and virtual base registers used for more efficient stack access.
908  virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
909  return false;
910  }
911 
912  /// Return true if target has reserved a spill slot in the stack frame of
913  /// the given function for the specified register. e.g. On x86, if the frame
914  /// register is required, the first fixed stack object is reserved as its
915  /// spill slot. This tells PEI not to create a new stack frame
916  /// object for the given register. It should be called only after
917  /// determineCalleeSaves().
919  int &FrameIdx) const {
920  return false;
921  }
922 
923  /// Returns true if the live-ins should be tracked after register allocation.
924  virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
925  return true;
926  }
927 
928  /// True if the stack can be realigned for the target.
929  virtual bool canRealignStack(const MachineFunction &MF) const;
930 
931  /// True if storage within the function requires the stack pointer to be
932  /// aligned more than the normal calling convention calls for.
933  virtual bool shouldRealignStack(const MachineFunction &MF) const;
934 
935  /// True if stack realignment is required and still possible.
936  bool hasStackRealignment(const MachineFunction &MF) const {
937  return shouldRealignStack(MF) && canRealignStack(MF);
938  }
939 
940  /// Get the offset from the referenced frame index in the instruction,
941  /// if there is one.
942  virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
943  int Idx) const {
944  return 0;
945  }
946 
947  /// Returns true if the instruction's frame index reference would be better
948  /// served by a base register other than FP or SP.
949  /// Used by LocalStackFrameAllocation to determine which frame index
950  /// references it should create new base registers for.
951  virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
952  return false;
953  }
954 
955  /// Insert defining instruction(s) for a pointer to FrameIdx before
956  /// insertion point I. Return materialized frame pointer.
958  int FrameIdx,
959  int64_t Offset) const {
960  llvm_unreachable("materializeFrameBaseRegister does not exist on this "
961  "target");
962  }
963 
964  /// Resolve a frame index operand of an instruction
965  /// to reference the indicated base register plus offset instead.
966  virtual void resolveFrameIndex(MachineInstr &MI, Register BaseReg,
967  int64_t Offset) const {
968  llvm_unreachable("resolveFrameIndex does not exist on this target");
969  }
970 
971  /// Determine whether a given base register plus offset immediate is
972  /// encodable to resolve a frame index.
973  virtual bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
974  int64_t Offset) const {
975  llvm_unreachable("isFrameOffsetLegal does not exist on this target");
976  }
977 
978  /// Gets the DWARF expression opcodes for \p Offset.
979  virtual void getOffsetOpcodes(const StackOffset &Offset,
980  SmallVectorImpl<uint64_t> &Ops) const;
981 
982  /// Prepends a DWARF expression for \p Offset to DIExpression \p Expr.
983  DIExpression *
984  prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags,
985  const StackOffset &Offset) const;
986 
987  /// Spill the register so it can be used by the register scavenger.
988  /// Return true if the register was spilled, false otherwise.
989  /// If this function does not spill the register, the scavenger
990  /// will instead spill it to the emergency spill slot.
994  const TargetRegisterClass *RC,
995  Register Reg) const {
996  return false;
997  }
998 
999  /// This method must be overriden to eliminate abstract frame indices from
1000  /// instructions which may use them. The instruction referenced by the
1001  /// iterator contains an MO_FrameIndex operand which must be eliminated by
1002  /// this method. This method may modify or replace the specified instruction,
1003  /// as long as it keeps the iterator pointing at the finished product.
1004  /// SPAdj is the SP adjustment due to call frame setup instruction.
1005  /// FIOperandNum is the FI operand number.
1007  int SPAdj, unsigned FIOperandNum,
1008  RegScavenger *RS = nullptr) const = 0;
1009 
1010  /// Return the assembly name for \p Reg.
1012  // FIXME: We are assuming that the assembly name is equal to the TableGen
1013  // name converted to lower case
1014  //
1015  // The TableGen name is the name of the definition for this register in the
1016  // target's tablegen files. For example, the TableGen name of
1017  // def EAX : Register <...>; is "EAX"
1018  return StringRef(getName(Reg));
1019  }
1020 
1021  //===--------------------------------------------------------------------===//
1022  /// Subtarget Hooks
1023 
1024  /// SrcRC and DstRC will be morphed into NewRC if this returns true.
1026  const TargetRegisterClass *SrcRC,
1027  unsigned SubReg,
1028  const TargetRegisterClass *DstRC,
1029  unsigned DstSubReg,
1030  const TargetRegisterClass *NewRC,
1031  LiveIntervals &LIS) const
1032  { return true; }
1033 
1034  /// Region split has a high compile time cost especially for large live range.
1035  /// This method is used to decide whether or not \p VirtReg should
1036  /// go through this expensive splitting heuristic.
1037  virtual bool shouldRegionSplitForVirtReg(const MachineFunction &MF,
1038  const LiveInterval &VirtReg) const;
1039 
1040  /// Last chance recoloring has a high compile time cost especially for
1041  /// targets with a lot of registers.
1042  /// This method is used to decide whether or not \p VirtReg should
1043  /// go through this expensive heuristic.
1044  /// When this target hook is hit, by returning false, there is a high
1045  /// chance that the register allocation will fail altogether (usually with
1046  /// "ran out of registers").
1047  /// That said, this error usually points to another problem in the
1048  /// optimization pipeline.
1049  virtual bool
1051  const LiveInterval &VirtReg) const {
1052  return true;
1053  }
1054 
1055  /// Deferred spilling delays the spill insertion of a virtual register
1056  /// after every other allocation. By deferring the spilling, it is
1057  /// sometimes possible to eliminate that spilling altogether because
1058  /// something else could have been eliminated, thus leaving some space
1059  /// for the virtual register.
1060  /// However, this comes with a compile time impact because it adds one
1061  /// more stage to the greedy register allocator.
1062  /// This method is used to decide whether \p VirtReg should use the deferred
1063  /// spilling stage instead of being spilled right away.
1064  virtual bool
1066  const LiveInterval &VirtReg) const {
1067  return false;
1068  }
1069 
1070  //===--------------------------------------------------------------------===//
1071  /// Debug information queries.
1072 
1073  /// getFrameRegister - This method should return the register used as a base
1074  /// for values allocated in the current stack frame.
1075  virtual Register getFrameRegister(const MachineFunction &MF) const = 0;
1076 
1077  /// Mark a register and all its aliases as reserved in the given set.
1079 
1080  /// Returns true if for every register in the set all super registers are part
1081  /// of the set as well.
1083  ArrayRef<MCPhysReg> Exceptions = ArrayRef<MCPhysReg>()) const;
1084 
1085  virtual const TargetRegisterClass *
1087  const MachineRegisterInfo &MRI) const {
1088  return nullptr;
1089  }
1090 
1091  /// Returns the physical register number of sub-register "Index"
1092  /// for physical register RegNo. Return zero if the sub-register does not
1093  /// exist.
1094  inline MCRegister getSubReg(MCRegister Reg, unsigned Idx) const {
1095  return static_cast<const MCRegisterInfo *>(this)->getSubReg(Reg, Idx);
1096  }
1097 };
1098 
1099 //===----------------------------------------------------------------------===//
1100 // SuperRegClassIterator
1101 //===----------------------------------------------------------------------===//
1102 //
1103 // Iterate over the possible super-registers for a given register class. The
1104 // iterator will visit a list of pairs (Idx, Mask) corresponding to the
1105 // possible classes of super-registers.
1106 //
1107 // Each bit mask will have at least one set bit, and each set bit in Mask
1108 // corresponds to a SuperRC such that:
1109 //
1110 // For all Reg in SuperRC: Reg:Idx is in RC.
1111 //
1112 // The iterator can include (O, RC->getSubClassMask()) as the first entry which
1113 // also satisfies the above requirement, assuming Reg:0 == Reg.
1114 //
1116  const unsigned RCMaskWords;
1117  unsigned SubReg = 0;
1118  const uint16_t *Idx;
1119  const uint32_t *Mask;
1120 
1121 public:
1122  /// Create a SuperRegClassIterator that visits all the super-register classes
1123  /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry.
1125  const TargetRegisterInfo *TRI,
1126  bool IncludeSelf = false)
1127  : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
1128  Idx(RC->getSuperRegIndices()), Mask(RC->getSubClassMask()) {
1129  if (!IncludeSelf)
1130  ++*this;
1131  }
1132 
1133  /// Returns true if this iterator is still pointing at a valid entry.
1134  bool isValid() const { return Idx; }
1135 
1136  /// Returns the current sub-register index.
1137  unsigned getSubReg() const { return SubReg; }
1138 
1139  /// Returns the bit mask of register classes that getSubReg() projects into
1140  /// RC.
1141  /// See TargetRegisterClass::getSubClassMask() for how to use it.
1142  const uint32_t *getMask() const { return Mask; }
1143 
1144  /// Advance iterator to the next entry.
1145  void operator++() {
1146  assert(isValid() && "Cannot move iterator past end.");
1147  Mask += RCMaskWords;
1148  SubReg = *Idx++;
1149  if (!SubReg)
1150  Idx = nullptr;
1151  }
1152 };
1153 
1154 //===----------------------------------------------------------------------===//
1155 // BitMaskClassIterator
1156 //===----------------------------------------------------------------------===//
1157 /// This class encapuslates the logic to iterate over bitmask returned by
1158 /// the various RegClass related APIs.
1159 /// E.g., this class can be used to iterate over the subclasses provided by
1160 /// TargetRegisterClass::getSubClassMask or SuperRegClassIterator::getMask.
1162  /// Total number of register classes.
1163  const unsigned NumRegClasses;
1164  /// Base index of CurrentChunk.
1165  /// In other words, the number of bit we read to get at the
1166  /// beginning of that chunck.
1167  unsigned Base = 0;
1168  /// Adjust base index of CurrentChunk.
1169  /// Base index + how many bit we read within CurrentChunk.
1170  unsigned Idx = 0;
1171  /// Current register class ID.
1172  unsigned ID = 0;
1173  /// Mask we are iterating over.
1174  const uint32_t *Mask;
1175  /// Current chunk of the Mask we are traversing.
1176  uint32_t CurrentChunk;
1177 
1178  /// Move ID to the next set bit.
1179  void moveToNextID() {
1180  // If the current chunk of memory is empty, move to the next one,
1181  // while making sure we do not go pass the number of register
1182  // classes.
1183  while (!CurrentChunk) {
1184  // Move to the next chunk.
1185  Base += 32;
1186  if (Base >= NumRegClasses) {
1187  ID = NumRegClasses;
1188  return;
1189  }
1190  CurrentChunk = *++Mask;
1191  Idx = Base;
1192  }
1193  // Otherwise look for the first bit set from the right
1194  // (representation of the class ID is big endian).
1195  // See getSubClassMask for more details on the representation.
1196  unsigned Offset = countTrailingZeros(CurrentChunk);
1197  // Add the Offset to the adjusted base number of this chunk: Idx.
1198  // This is the ID of the register class.
1199  ID = Idx + Offset;
1200 
1201  // Consume the zeros, if any, and the bit we just read
1202  // so that we are at the right spot for the next call.
1203  // Do not do Offset + 1 because Offset may be 31 and 32
1204  // will be UB for the shift, though in that case we could
1205  // have make the chunk being equal to 0, but that would
1206  // have introduced a if statement.
1207  moveNBits(Offset);
1208  moveNBits(1);
1209  }
1210 
1211  /// Move \p NumBits Bits forward in CurrentChunk.
1212  void moveNBits(unsigned NumBits) {
1213  assert(NumBits < 32 && "Undefined behavior spotted!");
1214  // Consume the bit we read for the next call.
1215  CurrentChunk >>= NumBits;
1216  // Adjust the base for the chunk.
1217  Idx += NumBits;
1218  }
1219 
1220 public:
1221  /// Create a BitMaskClassIterator that visits all the register classes
1222  /// represented by \p Mask.
1223  ///
1224  /// \pre \p Mask != nullptr
1226  : NumRegClasses(TRI.getNumRegClasses()), Mask(Mask), CurrentChunk(*Mask) {
1227  // Move to the first ID.
1228  moveToNextID();
1229  }
1230 
1231  /// Returns true if this iterator is still pointing at a valid entry.
1232  bool isValid() const { return getID() != NumRegClasses; }
1233 
1234  /// Returns the current register class ID.
1235  unsigned getID() const { return ID; }
1236 
1237  /// Advance iterator to the next entry.
1238  void operator++() {
1239  assert(isValid() && "Cannot move iterator past end.");
1240  moveToNextID();
1241  }
1242 };
1243 
1244 // This is useful when building IndexedMaps keyed on virtual registers
1247  unsigned operator()(Register Reg) const {
1248  return Register::virtReg2Index(Reg);
1249  }
1250 };
1251 
1252 /// Prints virtual and physical registers with or without a TRI instance.
1253 ///
1254 /// The format is:
1255 /// %noreg - NoRegister
1256 /// %5 - a virtual register.
1257 /// %5:sub_8bit - a virtual register with sub-register index (with TRI).
1258 /// %eax - a physical register
1259 /// %physreg17 - a physical register when no TRI instance given.
1260 ///
1261 /// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n';
1262 Printable printReg(Register Reg, const TargetRegisterInfo *TRI = nullptr,
1263  unsigned SubIdx = 0,
1264  const MachineRegisterInfo *MRI = nullptr);
1265 
1266 /// Create Printable object to print register units on a \ref raw_ostream.
1267 ///
1268 /// Register units are named after their root registers:
1269 ///
1270 /// al - Single root.
1271 /// fp0~st7 - Dual roots.
1272 ///
1273 /// Usage: OS << printRegUnit(Unit, TRI) << '\n';
1274 Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
1275 
1276 /// Create Printable object to print virtual registers and physical
1277 /// registers on a \ref raw_ostream.
1278 Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI);
1279 
1280 /// Create Printable object to print register classes or register banks
1281 /// on a \ref raw_ostream.
1282 Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo,
1283  const TargetRegisterInfo *TRI);
1284 
1285 } // end namespace llvm
1286 
1287 #endif // LLVM_CODEGEN_TARGETREGISTERINFO_H
llvm::TargetRegisterInfo::trackLivenessAfterRegAlloc
virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const
Returns true if the live-ins should be tracked after register allocation.
Definition: TargetRegisterInfo.h:924
llvm::LaneBitmask
Definition: LaneBitmask.h:40
llvm::TargetRegisterInfo::getRegAsmName
virtual StringRef getRegAsmName(MCRegister Reg) const
Return the assembly name for Reg.
Definition: TargetRegisterInfo.h:1011
i
i
Definition: README.txt:29
llvm::TargetRegisterInfoDesc::InAllocatableClass
const bool * InAllocatableClass
Definition: TargetRegisterInfo.h:217
llvm::TargetRegisterInfo::getSubClassWithSubReg
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
Definition: TargetRegisterInfo.h:613
llvm::TargetRegisterInfo::getLargestLegalSuperClass
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
Definition: TargetRegisterInfo.h:777
llvm::TargetRegisterInfo::getConstrainedRegClassForOperand
virtual const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand &MO, const MachineRegisterInfo &MRI) const
Definition: TargetRegisterInfo.h:1086
llvm::TargetRegisterInfo::shouldRegionSplitForVirtReg
virtual bool shouldRegionSplitForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Region split has a high compile time cost especially for large live range.
Definition: TargetRegisterInfo.cpp:68
llvm::TargetRegisterInfo::~TargetRegisterInfo
virtual ~TargetRegisterInfo()
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
MathExtras.h
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:71
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::TargetRegisterInfo::shouldUseLastChanceRecoloringForVirtReg
virtual bool shouldUseLastChanceRecoloringForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Last chance recoloring has a high compile time cost especially for targets with a lot of registers.
Definition: TargetRegisterInfo.h:1050
Reg
unsigned Reg
Definition: MachineSink.cpp:1558
llvm::SuperRegClassIterator::getSubReg
unsigned getSubReg() const
Returns the current sub-register index.
Definition: TargetRegisterInfo.h:1137
llvm::MCRegisterInfo::getName
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
Definition: MCRegisterInfo.h:485
llvm::TargetRegisterInfo::getCrossCopyRegClass
virtual const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const
Returns a legal register class to copy a register in the specified class to or from.
Definition: TargetRegisterInfo.h:768
llvm::TargetRegisterClass::isASubClass
bool isASubClass() const
Return true if this TargetRegisterClass is a subset class of at least one other TargetRegisterClass.
Definition: TargetRegisterInfo.h:182
llvm::TargetRegisterInfo::getIntraCallClobberedRegs
virtual ArrayRef< MCPhysReg > getIntraCallClobberedRegs(const MachineFunction *MF) const
Return a list of all of the registers which are clobbered "inside" a call to the given function.
Definition: TargetRegisterInfo.h:509
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:102
llvm::make_range
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Definition: iterator_range.h:53
llvm::TargetRegisterInfo::resolveFrameIndex
virtual void resolveFrameIndex(MachineInstr &MI, Register BaseReg, int64_t Offset) const
Resolve a frame index operand of an instruction to reference the indicated base register plus offset ...
Definition: TargetRegisterInfo.h:966
llvm::TargetRegisterClass::getLaneMask
LaneBitmask getLaneMask() const
Returns the combination of all lane masks of register in this class.
Definition: TargetRegisterInfo.h:206
llvm::printVRegOrUnit
Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
Definition: TargetRegisterInfo.cpp:164
llvm::MCRegisterClass::end
iterator end() const
Definition: MCRegisterInfo.h:53
llvm::TargetRegisterClass::isAllocatable
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
Definition: TargetRegisterInfo.h:117
llvm::VirtReg2IndexFunctor
Definition: TargetRegisterInfo.h:1245
llvm::MCRegisterClass::getNumRegs
unsigned getNumRegs() const
getNumRegs - Return the number of registers in this class.
Definition: MCRegisterInfo.h:57
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
Printable.h
StringRef.h
llvm::TargetRegisterInfo::dumpReg
static void dumpReg(Register Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)
Debugging helper: dump register in human readable form to dbgs() stream.
Definition: TargetRegisterInfo.cpp:669
llvm::MCRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: MCRegisterInfo.cpp:24
llvm::TargetRegisterInfo::getRegMaskNames
virtual ArrayRef< const char * > getRegMaskNames() const =0
llvm::TargetRegisterInfo::getRegisterCosts
ArrayRef< uint8_t > getRegisterCosts(const MachineFunction &MF) const
Get a list of cost values for all registers that correspond to the index returned by RegisterCostTabl...
Definition: TargetRegisterInfo.h:352
llvm::TargetRegisterInfo::getMinimalPhysRegClassLLT
const TargetRegisterClass * getMinimalPhysRegClassLLT(MCRegister Reg, LLT Ty=LLT()) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:229
llvm::TargetRegisterInfo::isInAllocatableClass
bool isInAllocatableClass(MCRegister RegNo) const
Return true if the register is in the allocation of any register class.
Definition: TargetRegisterInfo.h:361
llvm::SuperRegClassIterator::isValid
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Definition: TargetRegisterInfo.h:1134
llvm::TargetRegisterInfo::isConstantPhysReg
virtual bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
Definition: TargetRegisterInfo.h:548
ErrorHandling.h
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
llvm::TargetRegisterInfo::getReservedRegs
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
llvm::TargetRegisterInfo::getAllocatableSet
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not.
Definition: TargetRegisterInfo.cpp:255
llvm::TargetRegisterInfo::getOffsetOpcodes
virtual void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const
Gets the DWARF expression opcodes for Offset.
Definition: TargetRegisterInfo.cpp:642
llvm::TargetRegisterInfo::isAsmClobberable
virtual bool isAsmClobberable(const MachineFunction &MF, MCRegister PhysReg) const
Returns false if we can't guarantee that Physreg, specified as an IR asm clobber constraint,...
Definition: TargetRegisterInfo.h:535
llvm::TargetRegisterInfo::shouldRealignStack
virtual bool shouldRealignStack(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
Definition: TargetRegisterInfo.cpp:482
llvm::TargetRegisterInfo::updateRegAllocHint
virtual void updateRegAllocHint(Register Reg, Register NewReg, MachineFunction &MF) const
A callback to allow target a chance to update register allocation hints when a register is "changed" ...
Definition: TargetRegisterInfo.h:860
MachineBasicBlock.h
llvm::TargetRegisterInfoDesc::NumCosts
unsigned NumCosts
Definition: TargetRegisterInfo.h:215
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::TargetRegisterClass::getCopyCost
int getCopyCost() const
Return the cost of copying a value between two registers in this class.
Definition: TargetRegisterInfo.h:113
llvm::TargetRegisterInfo::markSuperRegs
void markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const
Mark a register and all its aliases as reserved in the given set.
Definition: TargetRegisterInfo.cpp:79
llvm::TargetRegisterInfo::getRegisterCostTableIndex
virtual unsigned getRegisterCostTableIndex(const MachineFunction &MF) const
Return the register cost table index.
Definition: TargetRegisterInfo.h:685
llvm::TargetRegisterInfo::regclass_begin
regclass_iterator regclass_begin() const
Register class iterators.
Definition: TargetRegisterInfo.h:727
llvm::TargetRegisterInfo::requiresFrameIndexScavenging
virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const
Returns true if the target requires post PEI scavenging of registers for materializing frame index co...
Definition: TargetRegisterInfo.h:895
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::MCRegisterClass::contains
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
Definition: MCRegisterInfo.h:68
llvm::TargetRegisterInfo::getCSRFirstUseCost
virtual unsigned getCSRFirstUseCost() const
Allow the target to override the cost of using a callee-saved register for the first time.
Definition: TargetRegisterInfo.h:879
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::TargetRegisterInfo::isCalleeSavedPhysReg
virtual bool isCalleeSavedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const
This is a wrapper around getCallPreservedMask().
Definition: TargetRegisterInfo.cpp:464
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2596
llvm::TargetRegisterInfo::getRegPressureSetLimit
virtual unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const =0
Get the register unit pressure limit for this dimension.
llvm::TargetRegisterInfo::RegClassInfo
Definition: TargetRegisterInfo.h:237
llvm::TargetRegisterInfo::getRegClassInfo
const RegClassInfo & getRegClassInfo(const TargetRegisterClass &RC) const
Definition: TargetRegisterInfo.h:721
RegisterSet
SmallSet< unsigned, 4 > RegisterSet
Definition: Thumb2ITBlockPass.cpp:39
llvm::TargetRegisterInfo::useFPForScavengingIndex
virtual bool useFPForScavengingIndex(const MachineFunction &MF) const
Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emerge...
Definition: TargetRegisterInfo.h:889
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
llvm::TargetRegisterClass::SubClassMask
const uint32_t * SubClassMask
Definition: TargetRegisterInfo.h:54
llvm::MCRegisterInfo::getNumSubRegIndices
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
Definition: MCRegisterInfo.h:498
llvm::TargetRegisterClass::getSubClassMask
const uint32_t * getSubClassMask() const
Returns a bit vector of subclasses, including this one.
Definition: TargetRegisterInfo.h:158
llvm::TargetRegisterInfo::legalclasstypes_end
vt_iterator legalclasstypes_end(const TargetRegisterClass &RC) const
Definition: TargetRegisterInfo.h:319
llvm::BitMaskClassIterator::isValid
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Definition: TargetRegisterInfo.h:1232
llvm::MCRegisterClass::getCopyCost
int getCopyCost() const
getCopyCost - Return the cost of copying a value between two registers in this class.
Definition: MCRegisterInfo.h:91
llvm::MCRegisterClass
MCRegisterClass - Base class of TargetRegisterClass.
Definition: MCRegisterInfo.h:31
a
=0.0 ? 0.0 :(a > 0.0 ? 1.0 :-1.0) a
Definition: README.txt:489
MachineValueType.h
llvm::MVT::SimpleValueType
SimpleValueType
Definition: MachineValueType.h:33
llvm::TargetRegisterInfo::getCalleeSavedRegs
virtual const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const =0
Return a null-terminated list of all of the callee-saved registers on this target.
llvm::TargetRegisterInfo::RegClassInfo::RegSize
unsigned RegSize
Definition: TargetRegisterInfo.h:238
llvm::Register::isPhysical
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
llvm::SuperRegClassIterator::SuperRegClassIterator
SuperRegClassIterator(const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, bool IncludeSelf=false)
Create a SuperRegClassIterator that visits all the super-register classes of RC.
Definition: TargetRegisterInfo.h:1124
llvm::TargetRegisterClass::contains
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
Definition: TargetRegisterInfo.h:93
llvm::TargetRegisterInfo::getRegUnitWeight
virtual unsigned getRegUnitWeight(unsigned RegUnit) const =0
Get the weight in units of pressure for this register unit.
llvm::TargetRegisterInfo::canRealignStack
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
Definition: TargetRegisterInfo.cpp:478
llvm::TargetRegisterInfoDesc::CostPerUse
const uint8_t * CostPerUse
Definition: TargetRegisterInfo.h:214
llvm::TargetRegisterInfo::getRegUnitPressureSets
virtual const int * getRegUnitPressureSets(unsigned RegUnit) const =0
Get the dimensions of register pressure impacted by this register unit.
llvm::TargetRegisterInfo::getSubRegIndexLaneMask
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
Definition: TargetRegisterInfo.h:377
llvm::TargetRegisterClass::SuperRegIndices
const uint16_t * SuperRegIndices
Definition: TargetRegisterInfo.h:55
llvm::TargetRegisterClass::CoveredBySubRegs
const bool CoveredBySubRegs
Whether a combination of subregisters can cover every register in the class.
Definition: TargetRegisterInfo.h:66
llvm::TargetRegisterClass::getRawAllocationOrder
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
Definition: TargetRegisterInfo.h:199
llvm::TargetRegisterInfo::isTypeLegalForClass
bool isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) const
Return true if the given TargetRegisterClass is compatible with LLT T.
Definition: TargetRegisterInfo.h:301
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::TargetRegisterInfo::hasRegUnit
bool hasRegUnit(MCRegister Reg, Register RegUnit) const
Returns true if Reg contains RegUnit.
Definition: TargetRegisterInfo.h:435
llvm::TargetRegisterInfo::getRegClassPressureSets
virtual const int * getRegClassPressureSets(const TargetRegisterClass *RC) const =0
Get the dimensions of register pressure impacted by this register class.
b
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical int b
Definition: README.txt:418
llvm::TargetRegisterClass::AllocationPriority
const uint8_t AllocationPriority
Classes with a higher priority value are assigned first by register allocators using a greedy heurist...
Definition: TargetRegisterInfo.h:59
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::TargetRegisterInfo::composeSubRegIndicesImpl
virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const
Overridden by TableGen in targets that have sub-registers.
Definition: TargetRegisterInfo.h:667
llvm::MCRegisterClass::getRegister
unsigned getRegister(unsigned i) const
getRegister - Return the specified register in the class.
Definition: MCRegisterInfo.h:61
llvm::TargetRegisterInfo::requiresVirtualBaseRegisters
virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const
Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers u...
Definition: TargetRegisterInfo.h:908
llvm::TargetRegisterClass::hasSuperClassEq
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
Definition: TargetRegisterInfo.h:138
llvm::TargetRegisterInfo::regsOverlap
bool regsOverlap(Register regA, Register regB) const
Returns true if the two registers are equal or alias each other.
Definition: TargetRegisterInfo.h:418
llvm::TargetRegisterInfo::getMatchingSuperRegClass
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
Definition: TargetRegisterInfo.cpp:302
llvm::BitVector
Definition: BitVector.h:74
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::TargetRegisterClass::hasSuperClass
bool hasSuperClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper super-class of this TargetRegisterClass.
Definition: TargetRegisterInfo.h:133
llvm::LiveInterval
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:680
llvm::TargetRegisterClass::OrderFunc
ArrayRef< MCPhysReg >(* OrderFunc)(const MachineFunction &)
Definition: TargetRegisterInfo.h:68
llvm::TargetRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl
virtual LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const
Definition: TargetRegisterInfo.h:677
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::SuperRegClassIterator
Definition: TargetRegisterInfo.h:1115
llvm::TargetRegisterInfo::isCallerPreservedPhysReg
virtual bool isCallerPreservedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const
Physical registers that may be modified within a function but are guaranteed to be restored before an...
Definition: TargetRegisterInfo.h:560
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::printRegUnit
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
Definition: TargetRegisterInfo.cpp:141
llvm::MCRegisterClass::begin
iterator begin() const
begin/end - Return all of the registers in this class.
Definition: MCRegisterInfo.h:52
llvm::TargetRegisterInfo::getPointerRegClass
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
Definition: TargetRegisterInfo.h:759
llvm::TargetRegisterInfo::regclasses
iterator_range< regclass_iterator > regclasses() const
Definition: TargetRegisterInfo.h:729
llvm::TargetRegisterInfo::regmaskSubsetEqual
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
Definition: TargetRegisterInfo.cpp:491
llvm::TargetRegisterInfo::getSpillAlign
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
Definition: TargetRegisterInfo.h:288
llvm::RegClassWeight
Each TargetRegisterClass has a per register weight, and weight limit which must be less than the limi...
Definition: TargetRegisterInfo.h:222
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:282
llvm::TargetRegisterClass::LaneMask
const LaneBitmask LaneMask
Definition: TargetRegisterInfo.h:56
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:739
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::TargetRegisterInfo::saveScavengerRegister
virtual bool saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, Register Reg) const
Spill the register so it can be used by the register scavenger.
Definition: TargetRegisterInfo.h:991
llvm::VirtReg2IndexFunctor::operator()
unsigned operator()(Register Reg) const
Definition: TargetRegisterInfo.h:1247
llvm::TargetRegisterClass::TSFlags
const uint8_t TSFlags
Configurable target specific flags.
Definition: TargetRegisterInfo.h:61
llvm::TargetRegisterInfo::getRegClassName
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Definition: TargetRegisterInfo.h:745
llvm::TargetRegisterInfo::getCommonSuperRegClass
const TargetRegisterClass * getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const
Find a common super-register class if it exists.
Definition: TargetRegisterInfo.cpp:318
llvm::SuperRegClassIterator::operator++
void operator++()
Advance iterator to the next entry.
Definition: TargetRegisterInfo.h:1145
llvm::TargetRegisterClass::SuperClasses
const sc_iterator SuperClasses
Definition: TargetRegisterInfo.h:67
llvm::TargetRegisterInfo::getFrameRegister
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
llvm::TargetRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: TargetRegisterInfo.h:577
llvm::TargetRegisterClass::HasDisjunctSubRegs
const bool HasDisjunctSubRegs
Whether the class supports two (or more) disjunct subregister indices.
Definition: TargetRegisterInfo.h:63
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetRegisterInfo::getNumRegPressureSets
virtual unsigned getNumRegPressureSets() const =0
Get the number of dimensions of register pressure.
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::TargetRegisterInfo::getRegAllocationHints
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
Definition: TargetRegisterInfo.cpp:421
llvm::TargetRegisterInfo::eliminateFrameIndex
virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const =0
This method must be overriden to eliminate abstract frame indices from instructions which may use the...
llvm::TargetRegisterInfo::reverseLocalAssignment
virtual bool reverseLocalAssignment() const
Allow the target to reverse allocation order of local live ranges.
Definition: TargetRegisterInfo.h:874
MCRegisterInfo.h
llvm::TargetRegisterInfo::regclass_end
regclass_iterator regclass_end() const
Definition: TargetRegisterInfo.h:728
ArrayRef.h
llvm::TargetRegisterInfo::getRegPressureSetName
virtual const char * getRegPressureSetName(unsigned Idx) const =0
Get the name of this register unit pressure set.
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetRegisterInfo::composeSubRegIndexLaneMaskImpl
virtual LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const
Overridden by TableGen in targets that have sub-registers.
Definition: TargetRegisterInfo.h:673
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::TargetRegisterInfo::getCommonSubClass
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
Definition: TargetRegisterInfo.cpp:288
iterator_range.h
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::Register::asMCReg
MCRegister asMCReg() const
Utility to check-convert this value to a MCRegister.
Definition: Register.h:120
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::TargetRegisterInfo::needsFrameBaseReg
virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const
Returns true if the instruction's frame index reference would be better served by a base register oth...
Definition: TargetRegisterInfo.h:951
llvm::RegClassWeight::RegWeight
unsigned RegWeight
Definition: TargetRegisterInfo.h:223
llvm::printRegClassOrBank
Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
Definition: TargetRegisterInfo.cpp:174
llvm::TargetRegisterInfo::TargetRegisterInfo
TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RCB, regclass_iterator RCE, const char *const *SRINames, const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes, const RegClassInfo *const RCIs, unsigned Mode=0)
Definition: TargetRegisterInfo.cpp:52
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::BitMaskClassIterator::BitMaskClassIterator
BitMaskClassIterator(const uint32_t *Mask, const TargetRegisterInfo &TRI)
Create a BitMaskClassIterator that visits all the register classes represented by Mask.
Definition: TargetRegisterInfo.h:1225
llvm::TargetRegisterInfo::shouldCoalesce
virtual bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const
Subtarget Hooks.
Definition: TargetRegisterInfo.h:1025
RegInfo
Definition: AMDGPUAsmParser.cpp:2384
llvm::countTrailingZeros
unsigned countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition: MathExtras.h:156
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::TargetRegisterInfo::composeSubRegIndices
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
Definition: TargetRegisterInfo.h:631
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::TargetRegisterInfo::getCoveringSubRegIndexes
bool getCoveringSubRegIndexes(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, LaneBitmask LaneMask, SmallVectorImpl< unsigned > &Indexes) const
Try to find one or more subregister indexes to cover LaneMask.
Definition: TargetRegisterInfo.cpp:523
llvm::MCRegisterClass::getID
unsigned getID() const
getID() - Return the register class ID number.
Definition: MCRegisterInfo.h:48
llvm::TargetRegisterInfo::isTypeLegalForClass
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
Definition: TargetRegisterInfo.h:293
uint32_t
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
llvm::RegClassWeight::WeightLimit
unsigned WeightLimit
Definition: TargetRegisterInfo.h:224
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::MCRegisterInfo::getRegClassName
const char * getRegClassName(const MCRegisterClass *Class) const
Definition: MCRegisterInfo.h:548
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::TargetRegisterInfo::isInlineAsmReadOnlyReg
virtual bool isInlineAsmReadOnlyReg(const MachineFunction &MF, unsigned PhysReg) const
Returns true if PhysReg cannot be written to in inline asm statements.
Definition: TargetRegisterInfo.h:541
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::TargetRegisterInfo::lookThruSingleUseCopyChain
virtual Register lookThruSingleUseCopyChain(Register SrcReg, const MachineRegisterInfo *MRI) const
Find the original SrcReg unless it is the target of a copy-like operation, in which case we chain bac...
Definition: TargetRegisterInfo.cpp:617
llvm::BitMaskClassIterator::operator++
void operator++()
Advance iterator to the next entry.
Definition: TargetRegisterInfo.h:1238
llvm::TargetRegisterInfo::shouldRewriteCopySrc
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
Definition: TargetRegisterInfo.cpp:412
llvm::TargetRegisterClass::getNumRegs
unsigned getNumRegs() const
Return the number of registers in this class.
Definition: TargetRegisterInfo.h:79
llvm::TargetRegisterInfo::shouldUseDeferredSpillingForVirtReg
virtual bool shouldUseDeferredSpillingForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Deferred spilling delays the spill insertion of a virtual register after every other allocation.
Definition: TargetRegisterInfo.h:1065
llvm::TargetRegisterClass::begin
iterator begin() const
begin/end - Return all of the registers in this class.
Definition: TargetRegisterInfo.h:75
llvm::TargetRegisterInfo::lookThruCopyLike
virtual Register lookThruCopyLike(Register SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
Definition: TargetRegisterInfo.cpp:595
llvm::TargetRegisterInfo::getRegSizeInBits
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Definition: TargetRegisterInfo.h:276
uint16_t
llvm::TargetRegisterClass::getRegister
MCRegister getRegister(unsigned i) const
Return the specified register in the class.
Definition: TargetRegisterInfo.h:87
llvm::TargetRegisterClass::getSuperClasses
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
Definition: TargetRegisterInfo.h:176
llvm::TargetRegisterInfo::getCustomEHPadPreservedMask
virtual const uint32_t * getCustomEHPadPreservedMask(const MachineFunction &MF) const
Return a register mask for the registers preserved by the unwinder, or nullptr if no custom mask is n...
Definition: TargetRegisterInfo.h:496
llvm::TargetRegisterInfo::isDivergentRegClass
virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const
Returns true if the register class is considered divergent.
Definition: TargetRegisterInfo.h:551
llvm::TargetRegisterInfo::composeSubRegIndexLaneMask
LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask Mask) const
Transforms a LaneMask computed for one subregister to the lanemask that would have been computed when...
Definition: TargetRegisterInfo.h:640
llvm::TargetRegisterClass::getSuperRegIndices
const uint16_t * getSuperRegIndices() const
Returns a 0-terminated list of sub-register indices that project some super-register class into this ...
Definition: TargetRegisterInfo.h:169
llvm::TargetRegisterInfo::getFrameIndexInstrOffset
virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const
Get the offset from the referenced frame index in the instruction, if there is one.
Definition: TargetRegisterInfo.h:942
llvm::TargetRegisterInfo::getRegPressureSetScore
virtual unsigned getRegPressureSetScore(const MachineFunction &MF, unsigned PSetID) const
Return a heuristic for the machine scheduler to compare the profitability of increasing one register ...
Definition: TargetRegisterInfo.h:799
llvm::TargetRegisterClass::sc_iterator
const TargetRegisterClass *const * sc_iterator
Definition: TargetRegisterInfo.h:50
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::TargetRegisterInfo::RegClassInfo::VTList
vt_iterator VTList
Definition: TargetRegisterInfo.h:239
llvm::TargetRegisterClass::contains
bool contains(Register Reg1, Register Reg2) const
Return true if both registers are in this class.
Definition: TargetRegisterInfo.h:102
llvm::TargetRegisterClass::MC
const MCRegisterClass * MC
Definition: TargetRegisterInfo.h:53
llvm::TargetRegisterInfo::getNumRegClasses
unsigned getNumRegClasses() const
Definition: TargetRegisterInfo.h:733
llvm::TargetRegisterInfo::getNoPreservedMask
virtual const uint32_t * getNoPreservedMask() const
Return a register mask that clobbers everything.
Definition: TargetRegisterInfo.h:501
llvm::TargetRegisterInfo::regclass_iterator
const TargetRegisterClass *const * regclass_iterator
Definition: TargetRegisterInfo.h:235
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:474
llvm::TargetRegisterInfo::hasStackRealignment
bool hasStackRealignment(const MachineFunction &MF) const
True if stack realignment is required and still possible.
Definition: TargetRegisterInfo.h:936
llvm::TargetRegisterInfo::materializeFrameBaseRegister
virtual Register materializeFrameBaseRegister(MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const
Insert defining instruction(s) for a pointer to FrameIdx before insertion point I.
Definition: TargetRegisterInfo.h:957
llvm::MCRegUnitIterator
Definition: MCRegisterInfo.h:677
llvm::TargetRegisterClass::hasSubClass
bool hasSubClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
Definition: TargetRegisterInfo.h:121
llvm::TargetRegisterInfo::requiresRegisterScavenging
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const
Returns true if the target requires (and can make use of) the register scavenger.
Definition: TargetRegisterInfo.h:883
SmallVector.h
llvm::TargetRegisterInfo::getCoveringLanes
LaneBitmask getCoveringLanes() const
The lane masks returned by getSubRegIndexLaneMask() above can only be used to determine if sub-regist...
Definition: TargetRegisterInfo.h:414
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::SuperRegClassIterator::getMask
const uint32_t * getMask() const
Returns the bit mask of register classes that getSubReg() projects into RC.
Definition: TargetRegisterInfo.h:1142
llvm::TargetRegisterInfo::getRegClassWeight
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
LaneBitmask.h
llvm::TargetRegisterInfoDesc
Extra information, not in MCRegisterDesc, about registers.
Definition: TargetRegisterInfo.h:213
llvm::TargetRegisterInfo::getAllocatableClass
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
Definition: TargetRegisterInfo.cpp:194
llvm::iterator_range
A range adaptor for a pair of iterators.
Definition: iterator_range.h:30
llvm::TargetRegisterInfo::RegClassInfo::SpillSize
unsigned SpillSize
Definition: TargetRegisterInfo.h:238
llvm::MVT::Untyped
@ Untyped
Definition: MachineValueType.h:266
llvm::SmallVectorImpl< unsigned >
llvm::MCRegisterClass::isAllocatable
bool isAllocatable() const
isAllocatable - Return true if this register class may be used to create virtual registers.
Definition: MCRegisterInfo.h:95
llvm::BitMaskClassIterator
This class encapuslates the logic to iterate over bitmask returned by the various RegClass related AP...
Definition: TargetRegisterInfo.h:1161
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1094
llvm::TargetRegisterInfo::checkAllSuperRegsMarked
bool checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const
Returns true if for every register in the set all super registers are part of the set as well.
Definition: TargetRegisterInfo.cpp:85
llvm::TargetRegisterClass::hasSubClassEq
bool hasSubClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a sub-class of or equal to this class.
Definition: TargetRegisterInfo.h:126
llvm::Register::virtReg2Index
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
Definition: Register.h:77
llvm::TargetRegisterInfo::isFrameOffsetLegal
virtual bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg, int64_t Offset) const
Determine whether a given base register plus offset immediate is encodable to resolve a frame index.
Definition: TargetRegisterInfo.h:973
llvm::TargetRegisterInfo::adjustStackMapLiveOutMask
virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const
Prior to adding the live-out mask to a stackmap or patchpoint instruction, provide the target the opp...
Definition: TargetRegisterInfo.h:573
llvm::TargetRegisterInfo::getMinimalPhysRegClass
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:211
llvm::TargetRegisterInfo::getSubRegIndexName
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
Definition: TargetRegisterInfo.h:367
llvm::TargetRegisterInfo::reverseComposeSubRegIndexLaneMask
LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask LaneMask) const
Transform a lanemask given for a virtual register to the corresponding lanemask before using subregis...
Definition: TargetRegisterInfo.h:654
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::TargetRegisterInfo::RegClassInfo::SpillAlignment
unsigned SpillAlignment
Definition: TargetRegisterInfo.h:238
llvm::TargetRegisterInfo::hasReservedSpillSlot
virtual bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const
Return true if target has reserved a spill slot in the stack frame of the given function for the spec...
Definition: TargetRegisterInfo.h:918
llvm::TargetRegisterClass::end
iterator end() const
Definition: TargetRegisterInfo.h:76
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:487
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::TargetRegisterClass::getRegisters
iterator_range< SmallVectorImpl< MCPhysReg >::const_iterator > getRegisters() const
Definition: TargetRegisterInfo.h:82
llvm::BitMaskClassIterator::getID
unsigned getID() const
Returns the current register class ID.
Definition: TargetRegisterInfo.h:1235
llvm::TargetRegisterInfo::prependOffsetExpression
DIExpression * prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags, const StackOffset &Offset) const
Prepends a DWARF expression for Offset to DIExpression Expr.
Definition: TargetRegisterInfo.cpp:649
llvm::TargetRegisterInfo::getRegMasks
virtual ArrayRef< const uint32_t * > getRegMasks() const =0
Return all the call-preserved register masks defined for this target.
llvm::TargetRegisterInfo::getRegPressureLimit
virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const
Return the register pressure "high water mark" for the specific register class.
Definition: TargetRegisterInfo.h:790
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::TargetRegisterInfo::legalclasstypes_begin
vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const
Loop over all of the value types that can be represented by values in the given register class.
Definition: TargetRegisterInfo.h:315
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::TargetRegisterInfo::requiresFrameIndexReplacementScavenging
virtual bool requiresFrameIndexReplacementScavenging(const MachineFunction &MF) const
Returns true if the target requires using the RegScavenger directly for frame elimination despite usi...
Definition: TargetRegisterInfo.h:901
llvm::LiveRegMatrix
Definition: LiveRegMatrix.h:40
llvm::LLT
Definition: LowLevelTypeImpl.h:40