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28 #include "llvm/Config/llvm-config.h"
43 #define DEBUG_TYPE "target-reg-info"
49 cl::desc(
"A threshold of live range size which may cause "
50 "high compile time cost in global splitting."),
55 const char *
const *SRINames,
60 : InfoDesc(
ID), SubRegIndexNames(SRINames),
61 SubRegIndexLaneMasks(SRILaneMasks),
62 RegClassBegin(RCB), RegClassEnd(RCE),
63 CoveringLanes(SRICoveringLanes),
64 RCInfos(RCIs), HwMode(
Mode) {
74 if (
MI &&
TII->isTriviallyReMaterializable(*
MI) &&
95 dbgs() <<
"Error: Super register " <<
printReg(*SR,
this)
97 <<
" is not reserved.\n";
126 OS <<
'$' <<
"physreg" <<
Reg;
127 else if (Reg < TRI->getNumRegs()) {
137 OS <<
":sub(" << SubIdx <<
')';
146 OS <<
"Unit~" << Unit;
152 OS <<
"BadUnit~" << Unit;
158 assert(Roots.isValid() &&
"Unit has no roots.");
160 for (++Roots; Roots.isValid(); ++Roots)
184 assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
185 "Generic registers must have a valid type");
214 "reg must be a physical register");
221 RC->contains(reg) && (!BestRC || BestRC->
hasSubClass(RC)))
225 assert(BestRC &&
"Couldn't find the register class");
232 "reg must be a physical register");
266 if (
C->isAllocatable())
273 Allocatable.
reset(Reserved);
283 if (
unsigned Common = *A++ & *
B++)
305 unsigned Idx)
const {
306 assert(A &&
B &&
"Missing register class");
307 assert(Idx &&
"Bad sub-register index");
311 if (RCI.getSubReg() == Idx)
321 unsigned &PreA,
unsigned &PreB)
const {
322 assert(RCA && SubA && RCB && SubB &&
"Invalid arguments");
337 unsigned *BestPreA = &PreA;
338 unsigned *BestPreB = &PreB;
360 if (FinalA != FinalB)
369 *BestPreA = IA.getSubReg();
370 *BestPreB = IB.getSubReg();
386 unsigned SrcSubReg) {
392 unsigned SrcIdx, DefIdx;
393 if (SrcSubReg && DefSubReg) {
395 SrcIdx, DefIdx) !=
nullptr;
416 unsigned SrcSubReg)
const {
427 const std::pair<Register, SmallVector<Register, 4>> &Hints_MRI =
432 bool Skip = (Hints_MRI.first != 0);
433 for (
auto Reg : Hints_MRI.second) {
446 if (!HintedRegs.
insert(Phys).second)
460 Hints.push_back(Phys);
469 const uint32_t *callerPreservedRegs =
471 if (callerPreservedRegs) {
473 "Expected physical register");
474 return (callerPreservedRegs[PhysReg / 32] >> PhysReg % 32) & 1;
487 return F.hasFnAttribute(
"stackrealign") ||
489 F.hasFnAttribute(Attribute::StackAlignment);
495 for (
unsigned I = 0;
I <
N; ++
I)
496 if ((mask0[
I] & mask1[
I]) != mask0[
I])
505 if (
Reg.isPhysical()) {
520 assert(RC &&
"Unable to deduce the register class");
528 unsigned BestIdx = 0;
529 unsigned BestCover = 0;
537 if (SubRegMask == LaneMask) {
543 if ((SubRegMask & ~LaneMask).
any())
547 PossibleIndexes.push_back(Idx);
548 if (PopCount > BestCover) {
549 BestCover = PopCount;
558 NeededIndexes.push_back(BestIdx);
563 while (LanesLeft.
any()) {
564 unsigned BestIdx = 0;
566 for (
unsigned Idx : PossibleIndexes) {
569 if (SubRegMask == LanesLeft) {
576 int Cover = (SubRegMask & LanesLeft).getNumLanes() -
577 (SubRegMask & ~LanesLeft).getNumLanes();
578 if (Cover > BestCover) {
587 NeededIndexes.push_back(BestIdx);
600 if (!
MI->isCopyLike())
605 CopySrcReg =
MI->getOperand(1).getReg();
607 assert(
MI->isSubregToReg() &&
"Bad opcode for lookThruCopyLike");
608 CopySrcReg =
MI->getOperand(2).getReg();
623 if (!
MI->isCopyLike())
628 CopySrcReg =
MI->getOperand(1).getReg();
630 assert(
MI->isSubregToReg() &&
"Bad opcode for lookThruCopyLike");
631 CopySrcReg =
MI->getOperand(2).getReg();
645 assert(!Offset.getScalable() &&
"Scalable offsets are not handled");
651 unsigned PrependFlags,
656 "Unsupported prepend flag");
659 OffsetExpr.push_back(dwarf::DW_OP_deref);
662 OffsetExpr.push_back(dwarf::DW_OP_deref);
668 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
virtual bool shouldRegionSplitForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Region split has a high compile time cost especially for large live range.
virtual ~TargetRegisterInfo()
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
This is an optimization pass for GlobalISel generic memory operations.
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
Information about stack frame layout on the target.
StringRef getVRegName(Register Reg) const
Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static void dumpReg(Register Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)
Debugging helper: dump register in human readable form to dbgs() stream.
virtual const TargetInstrInfo * getInstrInfo() const
const TargetRegisterClass * getMinimalPhysRegClassLLT(MCRegister Reg, LLT Ty=LLT()) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
unsigned getNumLanes() const
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Reg
All possible values of the reg field in the ModR/M byte.
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not.
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
virtual void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const
Gets the DWARF expression opcodes for Offset.
virtual bool shouldRealignStack(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
static int stackSlot2Index(Register Reg)
Compute the frame index from a register value representing a stack slot.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const
Mark a register and all its aliases as reserved in the given set.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
static void getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R)
getAllocatableSetForRC - Toggle the bits that represent allocatable registers for the specific regist...
virtual bool isCalleeSavedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const
This is a wrapper around getCallPreservedMask().
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
SmallSet< unsigned, 4 > RegisterSet
unsigned const TargetRegisterInfo * TRI
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
const uint32_t * getSubClassMask() const
Returns a bit vector of subclasses, including this one.
Predicate any(Predicate P0, Predicate P1)
True iff P0 or P1 are true.
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
TargetInstrInfo - Interface to description of machine instruction set.
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
static bool isStackSlot(unsigned Reg)
isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable th...
(vector float) vec_cmpeq(*A, *B) C
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const HexagonInstrInfo * TII
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
This class implements an extremely fast bulk output stream that can only output to a stream.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
LiveInterval - This class represents the liveness of a register, or stack slot.
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
iterator_range< regclass_iterator > regclasses() const
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Representation of each machine instruction.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
const TargetRegisterClass * getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const
Find a common super-register class if it exists.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
MCRegister getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
constexpr bool any() const
initializer< Ty > init(const Ty &Val)
LLVM_NODISCARD std::string lower() const
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
MCSuperRegIterator enumerates all super-registers of Reg.
Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RCB, regclass_iterator RCE, const char *const *SRINames, const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes, const RegClassInfo *const RCIs, unsigned Mode=0)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
unsigned countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1.
StringRef - Represent a constant reference to a string, i.e.
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool getCoveringSubRegIndexes(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, LaneBitmask LaneMask, SmallVectorImpl< unsigned > &Indexes) const
Try to find one or more subregister indexes to cover LaneMask.
if(llvm_vc STREQUAL "") set(fake_version_inc "$
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
const std::pair< Register, SmallVector< Register, 4 > > & getRegAllocationHints(Register VReg) const
getRegAllocationHints - Return a reference to the vector of all register allocation hints for VReg.
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
unsigned const MachineRegisterInfo * MRI
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Wrapper class representing virtual and physical registers.
virtual Register lookThruSingleUseCopyChain(Register SrcReg, const MachineRegisterInfo *MRI) const
Find the original SrcReg unless it is the target of a copy-like operation, in which case we chain bac...
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
static DIExpression * prependOpcodes(const DIExpression *Expr, SmallVectorImpl< uint64_t > &Ops, bool StackValue=false, bool EntryValue=false)
Prepend DIExpr with the given opcodes and optionally turn it into a stack value.
virtual Register lookThruCopyLike(Register SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
Function & getFunction()
Return the LLVM function that this machine code represents.
virtual const TargetFrameLowering * getFrameLowering() const
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
static const TargetRegisterClass * firstCommonClass(const uint32_t *A, const uint32_t *B, const TargetRegisterInfo *TRI)
const char * getName() const
Get a user friendly name of this register bank.
static bool shareSameRegisterFile(const TargetRegisterInfo &TRI, const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg)
Check if the registers defined by the pair (RegisterClass, SubReg) share the same register file.
const RegisterBank * getRegBankOrNull(Register Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
unsigned getNumRegClasses() const
const TargetRegisterClass *const * regclass_iterator
MCRegUnitRootIterator enumerates the root registers of a register unit.
bool hasSubClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Simple wrapper around std::function<void(raw_ostream&)>.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Extra information, not in MCRegisterDesc, about registers.
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
This class encapuslates the logic to iterate over bitmask returned by the various RegClass related AP...
static cl::opt< unsigned > HugeSizeForSplit("huge-size-for-split", cl::Hidden, cl::desc("A threshold of live range size which may cause " "high compile time cost in global splitting."), cl::init(5000))
bool checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const
Returns true if for every register in the set all super registers are part of the set as well.
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
DIExpression * prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags, const StackOffset &Offset) const
Prepends a DWARF expression for Offset to DIExpression Expr.
Wrapper class representing physical registers. Should be passed by value.