LLVM  10.0.0svn
TargetRegisterInfo.cpp
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1 //==- TargetRegisterInfo.cpp - Target Register Information Implementation --==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the TargetRegisterInfo interface.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/ArrayRef.h"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/ADT/SmallSet.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/Config/llvm-config.h"
26 #include "llvm/IR/Attributes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/MCRegisterInfo.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/Printable.h"
35 #include <cassert>
36 #include <utility>
37 
38 #define DEBUG_TYPE "target-reg-info"
39 
40 using namespace llvm;
41 
44  const char *const *SRINames,
45  const LaneBitmask *SRILaneMasks,
46  LaneBitmask SRICoveringLanes,
47  const RegClassInfo *const RCIs,
48  unsigned Mode)
49  : InfoDesc(ID), SubRegIndexNames(SRINames),
50  SubRegIndexLaneMasks(SRILaneMasks),
51  RegClassBegin(RCB), RegClassEnd(RCE),
52  CoveringLanes(SRICoveringLanes),
53  RCInfos(RCIs), HwMode(Mode) {
54 }
55 
57 
59  const {
60  for (MCSuperRegIterator AI(Reg, this, true); AI.isValid(); ++AI)
61  RegisterSet.set(*AI);
62 }
63 
65  ArrayRef<MCPhysReg> Exceptions) const {
66  // Check that all super registers of reserved regs are reserved as well.
67  BitVector Checked(getNumRegs());
68  for (unsigned Reg : RegisterSet.set_bits()) {
69  if (Checked[Reg])
70  continue;
71  for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) {
72  if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) {
73  dbgs() << "Error: Super register " << printReg(*SR, this)
74  << " of reserved register " << printReg(Reg, this)
75  << " is not reserved.\n";
76  return false;
77  }
78 
79  // We transitively check superregs. So we can remember this for later
80  // to avoid compiletime explosion in deep register hierarchies.
81  Checked.set(*SR);
82  }
83  }
84  return true;
85 }
86 
87 namespace llvm {
88 
90  unsigned SubIdx, const MachineRegisterInfo *MRI) {
91  return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) {
92  if (!Reg)
93  OS << "$noreg";
94  else if (Register::isStackSlot(Reg))
95  OS << "SS#" << Register::stackSlot2Index(Reg);
96  else if (Register::isVirtualRegister(Reg)) {
97  StringRef Name = MRI ? MRI->getVRegName(Reg) : "";
98  if (Name != "") {
99  OS << '%' << Name;
100  } else {
101  OS << '%' << Register::virtReg2Index(Reg);
102  }
103  } else if (!TRI)
104  OS << '$' << "physreg" << Reg;
105  else if (Reg < TRI->getNumRegs()) {
106  OS << '$';
107  printLowerCase(TRI->getName(Reg), OS);
108  } else
109  llvm_unreachable("Register kind is unsupported.");
110 
111  if (SubIdx) {
112  if (TRI)
113  OS << ':' << TRI->getSubRegIndexName(SubIdx);
114  else
115  OS << ":sub(" << SubIdx << ')';
116  }
117  });
118 }
119 
121  return Printable([Unit, TRI](raw_ostream &OS) {
122  // Generic printout when TRI is missing.
123  if (!TRI) {
124  OS << "Unit~" << Unit;
125  return;
126  }
127 
128  // Check for invalid register units.
129  if (Unit >= TRI->getNumRegUnits()) {
130  OS << "BadUnit~" << Unit;
131  return;
132  }
133 
134  // Normal units have at least one root.
135  MCRegUnitRootIterator Roots(Unit, TRI);
136  assert(Roots.isValid() && "Unit has no roots.");
137  OS << TRI->getName(*Roots);
138  for (++Roots; Roots.isValid(); ++Roots)
139  OS << '~' << TRI->getName(*Roots);
140  });
141 }
142 
144  return Printable([Unit, TRI](raw_ostream &OS) {
145  if (Register::isVirtualRegister(Unit)) {
146  OS << '%' << Register::virtReg2Index(Unit);
147  } else {
148  OS << printRegUnit(Unit, TRI);
149  }
150  });
151 }
152 
154  const TargetRegisterInfo *TRI) {
155  return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) {
156  if (RegInfo.getRegClassOrNull(Reg))
157  OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
158  else if (RegInfo.getRegBankOrNull(Reg))
159  OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
160  else {
161  OS << "_";
162  assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
163  "Generic registers must have a valid type");
164  }
165  });
166 }
167 
168 } // end namespace llvm
169 
170 /// getAllocatableClass - Return the maximal subclass of the given register
171 /// class that is alloctable, or NULL.
172 const TargetRegisterClass *
174  if (!RC || RC->isAllocatable())
175  return RC;
176 
177  for (BitMaskClassIterator It(RC->getSubClassMask(), *this); It.isValid();
178  ++It) {
179  const TargetRegisterClass *SubRC = getRegClass(It.getID());
180  if (SubRC->isAllocatable())
181  return SubRC;
182  }
183  return nullptr;
184 }
185 
186 /// getMinimalPhysRegClass - Returns the Register Class of a physical
187 /// register of the given type, picking the most sub register class of
188 /// the right type that contains this physreg.
189 const TargetRegisterClass *
192  "reg must be a physical register");
193 
194  // Pick the most sub register class of the right type that contains
195  // this physreg.
196  const TargetRegisterClass* BestRC = nullptr;
197  for (const TargetRegisterClass* RC : regclasses()) {
198  if ((VT == MVT::Other || isTypeLegalForClass(*RC, VT)) &&
199  RC->contains(reg) && (!BestRC || BestRC->hasSubClass(RC)))
200  BestRC = RC;
201  }
202 
203  assert(BestRC && "Couldn't find the register class");
204  return BestRC;
205 }
206 
207 /// getAllocatableSetForRC - Toggle the bits that represent allocatable
208 /// registers for the specific register class.
210  const TargetRegisterClass *RC, BitVector &R){
211  assert(RC->isAllocatable() && "invalid for nonallocatable sets");
213  for (unsigned i = 0; i != Order.size(); ++i)
214  R.set(Order[i]);
215 }
216 
218  const TargetRegisterClass *RC) const {
219  BitVector Allocatable(getNumRegs());
220  if (RC) {
221  // A register class with no allocatable subclass returns an empty set.
222  const TargetRegisterClass *SubClass = getAllocatableClass(RC);
223  if (SubClass)
224  getAllocatableSetForRC(MF, SubClass, Allocatable);
225  } else {
226  for (const TargetRegisterClass *C : regclasses())
227  if (C->isAllocatable())
228  getAllocatableSetForRC(MF, C, Allocatable);
229  }
230 
231  // Mask out the reserved registers
232  BitVector Reserved = getReservedRegs(MF);
233  Allocatable &= Reserved.flip();
234 
235  return Allocatable;
236 }
237 
238 static inline
240  const uint32_t *B,
241  const TargetRegisterInfo *TRI) {
242  for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32)
243  if (unsigned Common = *A++ & *B++)
244  return TRI->getRegClass(I + countTrailingZeros(Common));
245  return nullptr;
246 }
247 
248 const TargetRegisterClass *
250  const TargetRegisterClass *B) const {
251  // First take care of the trivial cases.
252  if (A == B)
253  return A;
254  if (!A || !B)
255  return nullptr;
256 
257  // Register classes are ordered topologically, so the largest common
258  // sub-class it the common sub-class with the smallest ID.
259  return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this);
260 }
261 
262 const TargetRegisterClass *
264  const TargetRegisterClass *B,
265  unsigned Idx) const {
266  assert(A && B && "Missing register class");
267  assert(Idx && "Bad sub-register index");
268 
269  // Find Idx in the list of super-register indices.
270  for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
271  if (RCI.getSubReg() == Idx)
272  // The bit mask contains all register classes that are projected into B
273  // by Idx. Find a class that is also a sub-class of A.
274  return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);
275  return nullptr;
276 }
277 
279 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
280  const TargetRegisterClass *RCB, unsigned SubB,
281  unsigned &PreA, unsigned &PreB) const {
282  assert(RCA && SubA && RCB && SubB && "Invalid arguments");
283 
284  // Search all pairs of sub-register indices that project into RCA and RCB
285  // respectively. This is quadratic, but usually the sets are very small. On
286  // most targets like X86, there will only be a single sub-register index
287  // (e.g., sub_16bit projecting into GR16).
288  //
289  // The worst case is a register class like DPR on ARM.
290  // We have indices dsub_0..dsub_7 projecting into that class.
291  //
292  // It is very common that one register class is a sub-register of the other.
293  // Arrange for RCA to be the larger register so the answer will be found in
294  // the first iteration. This makes the search linear for the most common
295  // case.
296  const TargetRegisterClass *BestRC = nullptr;
297  unsigned *BestPreA = &PreA;
298  unsigned *BestPreB = &PreB;
299  if (getRegSizeInBits(*RCA) < getRegSizeInBits(*RCB)) {
300  std::swap(RCA, RCB);
301  std::swap(SubA, SubB);
302  std::swap(BestPreA, BestPreB);
303  }
304 
305  // Also terminate the search one we have found a register class as small as
306  // RCA.
307  unsigned MinSize = getRegSizeInBits(*RCA);
308 
309  for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) {
310  unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
311  for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) {
312  // Check if a common super-register class exists for this index pair.
313  const TargetRegisterClass *RC =
314  firstCommonClass(IA.getMask(), IB.getMask(), this);
315  if (!RC || getRegSizeInBits(*RC) < MinSize)
316  continue;
317 
318  // The indexes must compose identically: PreA+SubA == PreB+SubB.
319  unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
320  if (FinalA != FinalB)
321  continue;
322 
323  // Is RC a better candidate than BestRC?
324  if (BestRC && getRegSizeInBits(*RC) >= getRegSizeInBits(*BestRC))
325  continue;
326 
327  // Yes, RC is the smallest super-register seen so far.
328  BestRC = RC;
329  *BestPreA = IA.getSubReg();
330  *BestPreB = IB.getSubReg();
331 
332  // Bail early if we reached MinSize. We won't find a better candidate.
333  if (getRegSizeInBits(*BestRC) == MinSize)
334  return BestRC;
335  }
336  }
337  return BestRC;
338 }
339 
340 /// Check if the registers defined by the pair (RegisterClass, SubReg)
341 /// share the same register file.
343  const TargetRegisterClass *DefRC,
344  unsigned DefSubReg,
345  const TargetRegisterClass *SrcRC,
346  unsigned SrcSubReg) {
347  // Same register class.
348  if (DefRC == SrcRC)
349  return true;
350 
351  // Both operands are sub registers. Check if they share a register class.
352  unsigned SrcIdx, DefIdx;
353  if (SrcSubReg && DefSubReg) {
354  return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
355  SrcIdx, DefIdx) != nullptr;
356  }
357 
358  // At most one of the register is a sub register, make it Src to avoid
359  // duplicating the test.
360  if (!SrcSubReg) {
361  std::swap(DefSubReg, SrcSubReg);
362  std::swap(DefRC, SrcRC);
363  }
364 
365  // One of the register is a sub register, check if we can get a superclass.
366  if (SrcSubReg)
367  return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
368 
369  // Plain copy.
370  return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
371 }
372 
374  unsigned DefSubReg,
375  const TargetRegisterClass *SrcRC,
376  unsigned SrcSubReg) const {
377  // If this source does not incur a cross register bank copy, use it.
378  return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg);
379 }
380 
381 // Compute target-independent register allocator hints to help eliminate copies.
382 bool
384  ArrayRef<MCPhysReg> Order,
386  const MachineFunction &MF,
387  const VirtRegMap *VRM,
388  const LiveRegMatrix *Matrix) const {
389  const MachineRegisterInfo &MRI = MF.getRegInfo();
390  const std::pair<unsigned, SmallVector<unsigned, 4>> &Hints_MRI =
391  MRI.getRegAllocationHints(VirtReg);
392 
393  SmallSet<unsigned, 32> HintedRegs;
394  // First hint may be a target hint.
395  bool Skip = (Hints_MRI.first != 0);
396  for (auto Reg : Hints_MRI.second) {
397  if (Skip) {
398  Skip = false;
399  continue;
400  }
401 
402  // Target-independent hints are either a physical or a virtual register.
403  unsigned Phys = Reg;
404  if (VRM && Register::isVirtualRegister(Phys))
405  Phys = VRM->getPhys(Phys);
406 
407  // Don't add the same reg twice (Hints_MRI may contain multiple virtual
408  // registers allocated to the same physreg).
409  if (!HintedRegs.insert(Phys).second)
410  continue;
411  // Check that Phys is a valid hint in VirtReg's register class.
412  if (!Register::isPhysicalRegister(Phys))
413  continue;
414  if (MRI.isReserved(Phys))
415  continue;
416  // Check that Phys is in the allocation order. We shouldn't heed hints
417  // from VirtReg's register class if they aren't in the allocation order. The
418  // target probably has a reason for removing the register.
419  if (!is_contained(Order, Phys))
420  continue;
421 
422  // All clear, tell the register allocator to prefer this register.
423  Hints.push_back(Phys);
424  }
425  return false;
426 }
427 
429  unsigned PhysReg, const MachineFunction &MF) const {
430  if (PhysReg == 0)
431  return false;
432  const uint32_t *callerPreservedRegs =
434  if (callerPreservedRegs) {
436  "Expected physical register");
437  return (callerPreservedRegs[PhysReg / 32] >> PhysReg % 32) & 1;
438  }
439  return false;
440 }
441 
443  return !MF.getFunction().hasFnAttribute("no-realign-stack");
444 }
445 
447  const MachineFunction &MF) const {
448  const MachineFrameInfo &MFI = MF.getFrameInfo();
450  const Function &F = MF.getFunction();
451  unsigned StackAlign = TFI->getStackAlignment();
452  bool requiresRealignment = ((MFI.getMaxAlignment() > StackAlign) ||
453  F.hasFnAttribute(Attribute::StackAlignment));
454  if (F.hasFnAttribute("stackrealign") || requiresRealignment) {
455  if (canRealignStack(MF))
456  return true;
457  LLVM_DEBUG(dbgs() << "Can't realign function's stack: " << F.getName()
458  << "\n");
459  }
460  return false;
461 }
462 
464  const uint32_t *mask1) const {
465  unsigned N = (getNumRegs()+31) / 32;
466  for (unsigned I = 0; I < N; ++I)
467  if ((mask0[I] & mask1[I]) != mask0[I])
468  return false;
469  return true;
470 }
471 
473  const MachineRegisterInfo &MRI) const {
474  const TargetRegisterClass *RC{};
475  if (Register::isPhysicalRegister(Reg)) {
476  // The size is not directly available for physical registers.
477  // Instead, we need to access a register class that contains Reg and
478  // get the size of that register class.
479  RC = getMinimalPhysRegClass(Reg);
480  } else {
481  LLT Ty = MRI.getType(Reg);
482  unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0;
483  // If Reg is not a generic register, query the register class to
484  // get its size.
485  if (RegSize)
486  return RegSize;
487  // Since Reg is not a generic register, it must have a register class.
488  RC = MRI.getRegClass(Reg);
489  }
490  assert(RC && "Unable to deduce the register class");
491  return getRegSizeInBits(*RC);
492 }
493 
494 unsigned
496  const MachineRegisterInfo *MRI) const {
497  while (true) {
498  const MachineInstr *MI = MRI->getVRegDef(SrcReg);
499  if (!MI->isCopyLike())
500  return SrcReg;
501 
502  unsigned CopySrcReg;
503  if (MI->isCopy())
504  CopySrcReg = MI->getOperand(1).getReg();
505  else {
506  assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");
507  CopySrcReg = MI->getOperand(2).getReg();
508  }
509 
510  if (!Register::isVirtualRegister(CopySrcReg))
511  return CopySrcReg;
512 
513  SrcReg = CopySrcReg;
514  }
515 }
516 
517 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
519 void TargetRegisterInfo::dumpReg(unsigned Reg, unsigned SubRegIndex,
520  const TargetRegisterInfo *TRI) {
521  dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n";
522 }
523 #endif
uint64_t CallInst * C
virtual bool getRegAllocationHints(unsigned VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of &#39;hint&#39; registers that the register allocator should try first when allocating a physica...
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not...
BitVector & set()
Definition: BitVector.h:397
bool isReserved(Register PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
static unsigned virtReg2Index(unsigned Reg)
Convert a virtual register number to a 0-based index.
Definition: Register.h:76
SI Whole Quad Mode
This class represents lattice values for constants.
Definition: AllocatorList.h:23
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds...
Definition: Compiler.h:476
virtual bool isCalleeSavedPhysReg(unsigned PhysReg, const MachineFunction &MF) const
This is a wrapper around getCallPreservedMask().
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
const char * getName() const
Get a user friendly name of this register bank.
Definition: RegisterBank.h:51
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
void push_back(const T &Elt)
Definition: SmallVector.h:211
bool isSubregToReg() const
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:63
static bool isStackSlot(unsigned Reg)
isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable th...
Definition: Register.h:45
unsigned Reg
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:323
unsigned const TargetRegisterInfo * TRI
F(f)
void markSuperRegs(BitVector &RegisterSet, unsigned Reg) const
Mark a register and all its aliases as reserved in the given set.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
bool isCopyLike() const
Return true if the instruction behaves like a copy.
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
bool checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const
Returns true if for every register in the set all super registers are part of the set as well...
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Live Register Matrix
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
unsigned countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:119
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
MCSuperRegIterator enumerates all super-registers of Reg.
This file contains the simple types necessary to represent the attributes associated with functions a...
iterator_range< regclass_iterator > regclasses() const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
unsigned getNumRegClasses() const
MachineInstr * getVRegDef(unsigned Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
const TargetRegisterClass * getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const
Find a common super-register class if it exists.
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
MCRegUnitRootIterator enumerates the root registers of a register unit.
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
SmallSet< unsigned, 4 > RegisterSet
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
This class encapuslates the logic to iterate over bitmask returned by the various RegClass related AP...
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function...
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
Machine Value Type.
const TargetRegisterClass *const * regclass_iterator
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static int stackSlot2Index(unsigned Reg)
Compute the frame index from a register value representing a stack slot.
Definition: Register.h:50
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
unsigned getMaxAlignment() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
bool isValid() const
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
bool def_empty(unsigned RegNo) const
def_empty - Return true if there are no instructions defining the specified register (it may be live-...
const RegisterBank * getRegBankOrNull(unsigned Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
bool hasSubClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:180
TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RCB, regclass_iterator RCE, const char *const *SRINames, const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes, const RegClassInfo *const RCIs, unsigned Mode=0)
Extra information, not in MCRegisterDesc, about registers.
bool isCopy() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static bool shareSameRegisterFile(const TargetRegisterInfo &TRI, const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg)
Check if the registers defined by the pair (RegisterClass, SubReg) share the same register file...
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
Information about stack frame layout on the target.
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
static void getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R)
getAllocatableSetForRC - Toggle the bits that represent allocatable registers for the specific regist...
BitVector & flip()
Definition: BitVector.h:477
const Function & getFunction() const
Return the LLVM function that this machine code represents.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:940
virtual BitVector getReservedRegs(const MachineFunction &MF) const =0
Returns a bitset indexed by physical register number indicating if a register is a special register t...
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register...
const uint32_t * getSubClassMask() const
Returns a bit vector of subclasses, including this one.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
Representation of each machine instruction.
Definition: MachineInstr.h:64
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Register getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:102
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
StringRef getName() const
Return a constant reference to the value&#39;s name.
Definition: Value.cpp:214
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
virtual const TargetFrameLowering * getFrameLowering() const
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
LLVM_NODISCARD std::string lower() const
Definition: StringRef.cpp:107
const TargetRegisterClass * getRegClassOrNull(unsigned Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void printLowerCase(StringRef String, raw_ostream &Out)
printLowerCase - Print each character as lowercase if it is uppercase.
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:129
bool needsStackRealignment(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
const std::pair< unsigned, SmallVector< unsigned, 4 > > & getRegAllocationHints(unsigned VReg) const
getRegAllocationHints - Return a reference to the vector of all register allocation hints for VReg...
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:69
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
IRTranslator LLVM IR MI
static const TargetRegisterClass * firstCommonClass(const uint32_t *A, const uint32_t *B, const TargetRegisterInfo *TRI)
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
bool isValid() const
Check if the iterator is at the end of the list.
Register getReg() const
getReg - Returns the register number.
Simple wrapper around std::function<void(raw_ostream&)>.
Definition: Printable.h:37
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
virtual unsigned lookThruCopyLike(unsigned SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
static void dumpReg(unsigned Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)
Debugging helper: dump register in human readable form to dbgs() stream.
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
StringRef getVRegName(unsigned Reg) const
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1224