LLVM 22.0.0git
TargetRegisterInfo.cpp
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1//==- TargetRegisterInfo.cpp - Target Register Information Implementation --==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the TargetRegisterInfo interface.
10//
11//===----------------------------------------------------------------------===//
12
14#include "llvm/ADT/ArrayRef.h"
15#include "llvm/ADT/BitVector.h"
16#include "llvm/ADT/STLExtras.h"
17#include "llvm/ADT/SmallSet.h"
29#include "llvm/Config/llvm-config.h"
30#include "llvm/IR/Attributes.h"
32#include "llvm/IR/Function.h"
36#include "llvm/Support/Debug.h"
39#include <cassert>
40#include <utility>
41
42#define DEBUG_TYPE "target-reg-info"
43
44using namespace llvm;
45
47 HugeSizeForSplit("huge-size-for-split", cl::Hidden,
48 cl::desc("A threshold of live range size which may cause "
49 "high compile time cost in global splitting."),
50 cl::init(5000));
51
54 regclass_iterator RCE, const char *const *SRINames,
55 const SubRegCoveredBits *SubIdxRanges, const LaneBitmask *SRILaneMasks,
56 LaneBitmask SRICoveringLanes, const RegClassInfo *const RCIs,
57 const MVT::SimpleValueType *const RCVTLists, unsigned Mode)
58 : InfoDesc(ID), SubRegIndexNames(SRINames), SubRegIdxRanges(SubIdxRanges),
59 SubRegIndexLaneMasks(SRILaneMasks), RegClassBegin(RCB), RegClassEnd(RCE),
60 CoveringLanes(SRICoveringLanes), RCInfos(RCIs), RCVTLists(RCVTLists),
61 HwMode(Mode) {}
62
64
66 const MachineFunction &MF, const LiveInterval &VirtReg) const {
69 MachineInstr *MI = MRI.getUniqueVRegDef(VirtReg.reg());
70 if (MI && TII->isTriviallyReMaterializable(*MI) &&
71 VirtReg.size() > HugeSizeForSplit)
72 return false;
73 return true;
74}
75
77 MCRegister Reg) const {
78 for (MCPhysReg SR : superregs_inclusive(Reg))
79 RegisterSet.set(SR);
80}
81
83 ArrayRef<MCPhysReg> Exceptions) const {
84 // Check that all super registers of reserved regs are reserved as well.
85 BitVector Checked(getNumRegs());
86 for (unsigned Reg : RegisterSet.set_bits()) {
87 if (Checked[Reg])
88 continue;
89 for (MCPhysReg SR : superregs(Reg)) {
90 if (!RegisterSet[SR] && !is_contained(Exceptions, Reg)) {
91 dbgs() << "Error: Super register " << printReg(SR, this)
92 << " of reserved register " << printReg(Reg, this)
93 << " is not reserved.\n";
94 return false;
95 }
96
97 // We transitively check superregs. So we can remember this for later
98 // to avoid compiletime explosion in deep register hierarchies.
99 Checked.set(SR);
100 }
101 }
102 return true;
103}
104
106 unsigned SubIdx, const MachineRegisterInfo *MRI) {
107 return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) {
108 if (!Reg)
109 OS << "$noreg";
110 else if (Reg.isStack())
111 OS << "SS#" << Reg.stackSlotIndex();
112 else if (Reg.isVirtual()) {
113 StringRef Name = MRI ? MRI->getVRegName(Reg) : "";
114 if (Name != "") {
115 OS << '%' << Name;
116 } else {
117 OS << '%' << Reg.virtRegIndex();
118 }
119 } else if (!TRI)
120 OS << '$' << "physreg" << Reg.id();
121 else if (Reg < TRI->getNumRegs()) {
122 OS << '$';
123 printLowerCase(TRI->getName(Reg), OS);
124 } else
125 llvm_unreachable("Register kind is unsupported.");
126
127 if (SubIdx) {
128 if (TRI)
129 OS << ':' << TRI->getSubRegIndexName(SubIdx);
130 else
131 OS << ":sub(" << SubIdx << ')';
132 }
133 });
134}
135
137 return Printable([Unit, TRI](raw_ostream &OS) {
138 // Generic printout when TRI is missing.
139 if (!TRI) {
140 OS << "Unit~" << Unit;
141 return;
142 }
143
144 // Check for invalid register units.
145 if (Unit >= TRI->getNumRegUnits()) {
146 OS << "BadUnit~" << Unit;
147 return;
148 }
149
150 // Normal units have at least one root.
151 MCRegUnitRootIterator Roots(Unit, TRI);
152 assert(Roots.isValid() && "Unit has no roots.");
153 OS << TRI->getName(*Roots);
154 for (++Roots; Roots.isValid(); ++Roots)
155 OS << '~' << TRI->getName(*Roots);
156 });
157}
158
160 return Printable([Unit, TRI](raw_ostream &OS) {
161 if (Register::isVirtualRegister(Unit)) {
162 OS << '%' << Register(Unit).virtRegIndex();
163 } else {
164 OS << printRegUnit(Unit, TRI);
165 }
166 });
167}
168
170 const MachineRegisterInfo &RegInfo,
171 const TargetRegisterInfo *TRI) {
172 return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) {
173 if (RegInfo.getRegClassOrNull(Reg))
174 OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
175 else if (RegInfo.getRegBankOrNull(Reg))
176 OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
177 else {
178 OS << "_";
179 assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
180 "Generic registers must have a valid type");
181 }
182 });
183}
184
185/// getAllocatableClass - Return the maximal subclass of the given register
186/// class that is alloctable, or NULL.
189 if (!RC || RC->isAllocatable())
190 return RC;
191
192 for (BitMaskClassIterator It(RC->getSubClassMask(), *this); It.isValid();
193 ++It) {
194 const TargetRegisterClass *SubRC = getRegClass(It.getID());
195 if (SubRC->isAllocatable())
196 return SubRC;
197 }
198 return nullptr;
199}
200
201template <typename TypeT>
202static const TargetRegisterClass *
204 TypeT Ty) {
205 static_assert(std::is_same_v<TypeT, MVT> || std::is_same_v<TypeT, LLT>);
206 assert(Reg.isPhysical() && "reg must be a physical register");
207
208 bool IsDefault = [&]() {
209 if constexpr (std::is_same_v<TypeT, MVT>)
210 return Ty == MVT::Other;
211 else
212 return !Ty.isValid();
213 }();
214
215 // Pick the most sub register class of the right type that contains
216 // this physreg.
217 const TargetRegisterClass *BestRC = nullptr;
218 for (const TargetRegisterClass *RC : TRI->regclasses()) {
219 if ((IsDefault || TRI->isTypeLegalForClass(*RC, Ty)) && RC->contains(Reg) &&
220 (!BestRC || BestRC->hasSubClass(RC)))
221 BestRC = RC;
222 }
223
224 if constexpr (std::is_same_v<TypeT, MVT>)
225 assert(BestRC && "Couldn't find the register class");
226 return BestRC;
227}
228
229template <typename TypeT>
230static const TargetRegisterClass *
232 MCRegister Reg2, TypeT Ty) {
233 static_assert(std::is_same_v<TypeT, MVT> || std::is_same_v<TypeT, LLT>);
234 assert(Reg1.isPhysical() && Reg2.isPhysical() &&
235 "Reg1/Reg2 must be a physical register");
236
237 bool IsDefault = [&]() {
238 if constexpr (std::is_same_v<TypeT, MVT>)
239 return Ty == MVT::Other;
240 else
241 return !Ty.isValid();
242 }();
243
244 // Pick the most sub register class of the right type that contains
245 // this physreg.
246 const TargetRegisterClass *BestRC = nullptr;
247 for (const TargetRegisterClass *RC : TRI->regclasses()) {
248 if ((IsDefault || TRI->isTypeLegalForClass(*RC, Ty)) &&
249 RC->contains(Reg1, Reg2) && (!BestRC || BestRC->hasSubClass(RC)))
250 BestRC = RC;
251 }
252
253 if constexpr (std::is_same_v<TypeT, MVT>)
254 assert(BestRC && "Couldn't find the register class");
255 return BestRC;
256}
257
260 return ::getMinimalPhysRegClass(this, Reg, VT);
261}
262
264 MCRegister Reg1, MCRegister Reg2, MVT VT) const {
265 return ::getCommonMinimalPhysRegClass(this, Reg1, Reg2, VT);
266}
267
270 return ::getMinimalPhysRegClass(this, Reg, Ty);
271}
272
274 MCRegister Reg1, MCRegister Reg2, LLT Ty) const {
275 return ::getCommonMinimalPhysRegClass(this, Reg1, Reg2, Ty);
276}
277
278/// getAllocatableSetForRC - Toggle the bits that represent allocatable
279/// registers for the specific register class.
281 const TargetRegisterClass *RC, BitVector &R){
282 assert(RC->isAllocatable() && "invalid for nonallocatable sets");
284 for (MCPhysReg PR : Order)
285 R.set(PR);
286}
287
289 const TargetRegisterClass *RC) const {
290 BitVector Allocatable(getNumRegs());
291 if (RC) {
292 // A register class with no allocatable subclass returns an empty set.
293 const TargetRegisterClass *SubClass = getAllocatableClass(RC);
294 if (SubClass)
295 getAllocatableSetForRC(MF, SubClass, Allocatable);
296 } else {
297 for (const TargetRegisterClass *C : regclasses())
298 if (C->isAllocatable())
299 getAllocatableSetForRC(MF, C, Allocatable);
300 }
301
302 // Mask out the reserved registers
303 const MachineRegisterInfo &MRI = MF.getRegInfo();
304 const BitVector &Reserved = MRI.getReservedRegs();
305 Allocatable.reset(Reserved);
306
307 return Allocatable;
308}
309
310static inline
312 const uint32_t *B,
313 const TargetRegisterInfo *TRI) {
314 for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32)
315 if (unsigned Common = *A++ & *B++)
316 return TRI->getRegClass(I + llvm::countr_zero(Common));
317 return nullptr;
318}
319
322 const TargetRegisterClass *B) const {
323 // First take care of the trivial cases.
324 if (A == B)
325 return A;
326 if (!A || !B)
327 return nullptr;
328
329 // Register classes are ordered topologically, so the largest common
330 // sub-class it the common sub-class with the smallest ID.
331 return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this);
332}
333
336 const TargetRegisterClass *B,
337 unsigned Idx) const {
338 assert(A && B && "Missing register class");
339 assert(Idx && "Bad sub-register index");
340
341 // Find Idx in the list of super-register indices.
342 for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
343 if (RCI.getSubReg() == Idx)
344 // The bit mask contains all register classes that are projected into B
345 // by Idx. Find a class that is also a sub-class of A.
346 return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);
347 return nullptr;
348}
349
351getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
352 const TargetRegisterClass *RCB, unsigned SubB,
353 unsigned &PreA, unsigned &PreB) const {
354 assert(RCA && SubA && RCB && SubB && "Invalid arguments");
355
356 // Search all pairs of sub-register indices that project into RCA and RCB
357 // respectively. This is quadratic, but usually the sets are very small. On
358 // most targets like X86, there will only be a single sub-register index
359 // (e.g., sub_16bit projecting into GR16).
360 //
361 // The worst case is a register class like DPR on ARM.
362 // We have indices dsub_0..dsub_7 projecting into that class.
363 //
364 // It is very common that one register class is a sub-register of the other.
365 // Arrange for RCA to be the larger register so the answer will be found in
366 // the first iteration. This makes the search linear for the most common
367 // case.
368 const TargetRegisterClass *BestRC = nullptr;
369 unsigned *BestPreA = &PreA;
370 unsigned *BestPreB = &PreB;
371 if (getRegSizeInBits(*RCA) < getRegSizeInBits(*RCB)) {
372 std::swap(RCA, RCB);
373 std::swap(SubA, SubB);
374 std::swap(BestPreA, BestPreB);
375 }
376
377 // Also terminate the search one we have found a register class as small as
378 // RCA.
379 unsigned MinSize = getRegSizeInBits(*RCA);
380
381 for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) {
382 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
383 for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) {
384 // Check if a common super-register class exists for this index pair.
385 const TargetRegisterClass *RC =
386 firstCommonClass(IA.getMask(), IB.getMask(), this);
387 if (!RC || getRegSizeInBits(*RC) < MinSize)
388 continue;
389
390 // The indexes must compose identically: PreA+SubA == PreB+SubB.
391 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
392 if (FinalA != FinalB)
393 continue;
394
395 // Is RC a better candidate than BestRC?
396 if (BestRC && getRegSizeInBits(*RC) >= getRegSizeInBits(*BestRC))
397 continue;
398
399 // Yes, RC is the smallest super-register seen so far.
400 BestRC = RC;
401 *BestPreA = IA.getSubReg();
402 *BestPreB = IB.getSubReg();
403
404 // Bail early if we reached MinSize. We won't find a better candidate.
405 if (getRegSizeInBits(*BestRC) == MinSize)
406 return BestRC;
407 }
408 }
409 return BestRC;
410}
411
413 const TargetRegisterClass *DefRC, unsigned DefSubReg,
414 const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const {
415 // Same register class.
416 //
417 // When processing uncoalescable copies / bitcasts, it is possible we reach
418 // here with the same register class, but mismatched subregister indices.
419 if (DefRC == SrcRC && DefSubReg == SrcSubReg)
420 return DefRC;
421
422 // Both operands are sub registers. Check if they share a register class.
423 unsigned SrcIdx, DefIdx;
424 if (SrcSubReg && DefSubReg) {
425 return getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, SrcIdx,
426 DefIdx);
427 }
428
429 // At most one of the register is a sub register, make it Src to avoid
430 // duplicating the test.
431 if (!SrcSubReg) {
432 std::swap(DefSubReg, SrcSubReg);
433 std::swap(DefRC, SrcRC);
434 }
435
436 // One of the register is a sub register, check if we can get a superclass.
437 if (SrcSubReg)
438 return getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg);
439
440 // Plain copy.
441 return getCommonSubClass(DefRC, SrcRC);
442}
443
445 const TargetRegisterClass *RC) const {
446 return 1.0;
447}
448
449// Compute target-independent register allocator hints to help eliminate copies.
451 Register VirtReg, ArrayRef<MCPhysReg> Order,
453 const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
454 const MachineRegisterInfo &MRI = MF.getRegInfo();
455 const std::pair<unsigned, SmallVector<Register, 4>> *Hints_MRI =
456 MRI.getRegAllocationHints(VirtReg);
457
458 if (!Hints_MRI)
459 return false;
460
461 SmallSet<Register, 32> HintedRegs;
462 // First hint may be a target hint.
463 bool Skip = (Hints_MRI->first != 0);
464 for (auto Reg : Hints_MRI->second) {
465 if (Skip) {
466 Skip = false;
467 continue;
468 }
469
470 // Target-independent hints are either a physical or a virtual register.
471 Register Phys = Reg;
472 if (VRM && Phys.isVirtual())
473 Phys = VRM->getPhys(Phys);
474
475 // Don't add the same reg twice (Hints_MRI may contain multiple virtual
476 // registers allocated to the same physreg).
477 if (!HintedRegs.insert(Phys).second)
478 continue;
479 // Check that Phys is a valid hint in VirtReg's register class.
480 if (!Phys.isPhysical())
481 continue;
482 if (MRI.isReserved(Phys))
483 continue;
484 // Check that Phys is in the allocation order. We shouldn't heed hints
485 // from VirtReg's register class if they aren't in the allocation order. The
486 // target probably has a reason for removing the register.
487 if (!is_contained(Order, Phys))
488 continue;
489
490 // All clear, tell the register allocator to prefer this register.
491 Hints.push_back(Phys.id());
492 }
493 return false;
494}
495
497 MCRegister PhysReg, const MachineFunction &MF) const {
498 if (!PhysReg)
499 return false;
500 const uint32_t *callerPreservedRegs =
502 if (callerPreservedRegs) {
503 assert(PhysReg.isPhysical() && "Expected physical register");
504 return (callerPreservedRegs[PhysReg.id() / 32] >> PhysReg.id() % 32) & 1;
505 }
506 return false;
507}
508
512
516
518 const uint32_t *mask1) const {
519 unsigned N = (getNumRegs()+31) / 32;
520 for (unsigned I = 0; I < N; ++I)
521 if ((mask0[I] & mask1[I]) != mask0[I])
522 return false;
523 return true;
524}
525
528 const MachineRegisterInfo &MRI) const {
529 const TargetRegisterClass *RC{};
530 if (Reg.isPhysical()) {
531 // The size is not directly available for physical registers.
532 // Instead, we need to access a register class that contains Reg and
533 // get the size of that register class.
534 RC = getMinimalPhysRegClass(Reg);
535 assert(RC && "Unable to deduce the register class");
536 return getRegSizeInBits(*RC);
537 }
538 LLT Ty = MRI.getType(Reg);
539 if (Ty.isValid())
540 return Ty.getSizeInBits();
541
542 // Since Reg is not a generic register, it may have a register class.
543 RC = MRI.getRegClass(Reg);
544 assert(RC && "Unable to deduce the register class");
545 return getRegSizeInBits(*RC);
546}
547
549 const TargetRegisterClass *RC, LaneBitmask LaneMask,
550 SmallVectorImpl<unsigned> &NeededIndexes) const {
551 SmallVector<unsigned, 8> PossibleIndexes;
552 unsigned BestIdx = 0;
553 unsigned BestCover = 0;
554
555 for (unsigned Idx = 1, E = getNumSubRegIndices(); Idx < E; ++Idx) {
556 // Is this index even compatible with the given class?
557 if (getSubClassWithSubReg(RC, Idx) != RC)
558 continue;
559 LaneBitmask SubRegMask = getSubRegIndexLaneMask(Idx);
560 // Early exit if we found a perfect match.
561 if (SubRegMask == LaneMask) {
562 BestIdx = Idx;
563 break;
564 }
565
566 // The index must not cover any lanes outside \p LaneMask.
567 if ((SubRegMask & ~LaneMask).any())
568 continue;
569
570 unsigned PopCount = SubRegMask.getNumLanes();
571 PossibleIndexes.push_back(Idx);
572 if (PopCount > BestCover) {
573 BestCover = PopCount;
574 BestIdx = Idx;
575 }
576 }
577
578 // Abort if we cannot possibly implement the COPY with the given indexes.
579 if (BestIdx == 0)
580 return false;
581
582 NeededIndexes.push_back(BestIdx);
583
584 // Greedy heuristic: Keep iterating keeping the best covering subreg index
585 // each time.
586 LaneBitmask LanesLeft = LaneMask & ~getSubRegIndexLaneMask(BestIdx);
587 while (LanesLeft.any()) {
588 unsigned BestIdx = 0;
589 int BestCover = std::numeric_limits<int>::min();
590 for (unsigned Idx : PossibleIndexes) {
591 LaneBitmask SubRegMask = getSubRegIndexLaneMask(Idx);
592 // Early exit if we found a perfect match.
593 if (SubRegMask == LanesLeft) {
594 BestIdx = Idx;
595 break;
596 }
597
598 // Do not cover already-covered lanes to avoid creating cycles
599 // in copy bundles (= bundle contains copies that write to the
600 // registers).
601 if ((SubRegMask & ~LanesLeft).any())
602 continue;
603
604 // Try to cover as many of the remaining lanes as possible.
605 const int Cover = (SubRegMask & LanesLeft).getNumLanes();
606 if (Cover > BestCover) {
607 BestCover = Cover;
608 BestIdx = Idx;
609 }
610 }
611
612 if (BestIdx == 0)
613 return false; // Impossible to handle
614
615 NeededIndexes.push_back(BestIdx);
616
617 LanesLeft &= ~getSubRegIndexLaneMask(BestIdx);
618 }
619
620 return BestIdx;
621}
622
623unsigned TargetRegisterInfo::getSubRegIdxSize(unsigned Idx) const {
624 assert(Idx && Idx < getNumSubRegIndices() &&
625 "This is not a subregister index");
626 return SubRegIdxRanges[HwMode * getNumSubRegIndices() + Idx].Size;
627}
628
629unsigned TargetRegisterInfo::getSubRegIdxOffset(unsigned Idx) const {
630 assert(Idx && Idx < getNumSubRegIndices() &&
631 "This is not a subregister index");
632 return SubRegIdxRanges[HwMode * getNumSubRegIndices() + Idx].Offset;
633}
634
637 const MachineRegisterInfo *MRI) const {
638 while (true) {
639 const MachineInstr *MI = MRI->getVRegDef(SrcReg);
640 if (!MI->isCopyLike())
641 return SrcReg;
642
643 Register CopySrcReg;
644 if (MI->isCopy())
645 CopySrcReg = MI->getOperand(1).getReg();
646 else {
647 assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");
648 CopySrcReg = MI->getOperand(2).getReg();
649 }
650
651 if (!CopySrcReg.isVirtual())
652 return CopySrcReg;
653
654 SrcReg = CopySrcReg;
655 }
656}
657
659 Register SrcReg, const MachineRegisterInfo *MRI) const {
660 while (true) {
661 const MachineInstr *MI = MRI->getVRegDef(SrcReg);
662 // Found the real definition, return it if it has a single use.
663 if (!MI->isCopyLike())
664 return MRI->hasOneNonDBGUse(SrcReg) ? SrcReg : Register();
665
666 Register CopySrcReg;
667 if (MI->isCopy())
668 CopySrcReg = MI->getOperand(1).getReg();
669 else {
670 assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");
671 CopySrcReg = MI->getOperand(2).getReg();
672 }
673
674 // Continue only if the next definition in the chain is for a virtual
675 // register that has a single use.
676 if (!CopySrcReg.isVirtual() || !MRI->hasOneNonDBGUse(CopySrcReg))
677 return Register();
678
679 SrcReg = CopySrcReg;
680 }
681}
682
685 assert(!Offset.getScalable() && "Scalable offsets are not handled");
687}
688
691 unsigned PrependFlags,
692 const StackOffset &Offset) const {
693 assert((PrependFlags &
696 "Unsupported prepend flag");
697 SmallVector<uint64_t, 16> OffsetExpr;
698 if (PrependFlags & DIExpression::DerefBefore)
699 OffsetExpr.push_back(dwarf::DW_OP_deref);
700 getOffsetOpcodes(Offset, OffsetExpr);
701 if (PrependFlags & DIExpression::DerefAfter)
702 OffsetExpr.push_back(dwarf::DW_OP_deref);
703 return DIExpression::prependOpcodes(Expr, OffsetExpr,
704 PrependFlags & DIExpression::StackValue,
705 PrependFlags & DIExpression::EntryValue);
706}
707
708#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
710void TargetRegisterInfo::dumpReg(Register Reg, unsigned SubRegIndex,
711 const TargetRegisterInfo *TRI) {
712 dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n";
713}
714#endif
unsigned const MachineRegisterInfo * MRI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
This file contains the simple types necessary to represent the attributes associated with functions a...
This file implements the BitVector class.
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition Compiler.h:638
This file contains constants used for implementing Dwarf debug support.
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]
Live Register Matrix
#define I(x, y, z)
Definition MD5.cpp:58
Register Reg
Register const TargetRegisterInfo * TRI
Promote Memory to Register
Definition Mem2Reg.cpp:110
This file contains some templates that are useful if you are working with the STL at all.
This file defines the SmallSet class.
This file contains some functions that are useful when dealing with strings.
static const TargetRegisterClass * getMinimalPhysRegClass(const TargetRegisterInfo *TRI, MCRegister Reg, TypeT Ty)
static void getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R)
getAllocatableSetForRC - Toggle the bits that represent allocatable registers for the specific regist...
static const TargetRegisterClass * firstCommonClass(const uint32_t *A, const uint32_t *B, const TargetRegisterInfo *TRI)
static const TargetRegisterClass * getCommonMinimalPhysRegClass(const TargetRegisterInfo *TRI, MCRegister Reg1, MCRegister Reg2, TypeT Ty)
static cl::opt< unsigned > HugeSizeForSplit("huge-size-for-split", cl::Hidden, cl::desc("A threshold of live range size which may cause " "high compile time cost in global splitting."), cl::init(5000))
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:41
This class encapuslates the logic to iterate over bitmask returned by the various RegClass related AP...
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
BitVector & reset()
Definition BitVector.h:411
BitVector & set()
Definition BitVector.h:370
DWARF expression.
static LLVM_ABI void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
static LLVM_ABI DIExpression * prependOpcodes(const DIExpression *Expr, SmallVectorImpl< uint64_t > &Ops, bool StackValue=false, bool EntryValue=false)
Prepend DIExpr with the given opcodes and optionally turn it into a stack value.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition Function.h:270
LiveInterval - This class represents the liveness of a register, or stack slot.
Register reg() const
size_t size() const
MCRegUnitRootIterator enumerates the root registers of a register unit.
bool isValid() const
Check if the iterator is at the end of the list.
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
iterator_range< MCSuperRegIterator > superregs(MCRegister Reg) const
Return an iterator range over all super-registers of Reg, excluding Reg.
iterator_range< MCSuperRegIterator > superregs_inclusive(MCRegister Reg) const
Return an iterator range over all super-registers of Reg, including Reg.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Wrapper class representing physical registers. Should be passed by value.
Definition MCRegister.h:33
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition MCRegister.h:64
constexpr unsigned id() const
Definition MCRegister.h:74
Machine Value Type.
bool shouldRealignStack() const
Return true if stack realignment is forced by function attributes or if the stack alignment.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Simple wrapper around std::function<void(raw_ostream&)>.
Definition Printable.h:38
Wrapper class representing virtual and physical registers.
Definition Register.h:19
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition Register.h:74
static constexpr bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition Register.h:61
constexpr unsigned id() const
Definition Register.h:95
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition Register.h:78
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition SmallSet.h:133
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition SmallSet.h:183
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StackOffset holds a fixed and a scalable offset in bytes.
Definition TypeSize.h:31
StringRef - Represent a constant reference to a string, i.e.
Definition StringRef.h:55
LLVM_ABI std::string lower() const
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
TargetInstrInfo - Interface to description of machine instruction set.
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF, bool Rev=false) const
Returns the preferred order for allocating registers from this register class in MF.
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
bool hasSubClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
const uint32_t * getSubClassMask() const
Returns a bit vector of subclasses, including this one.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const TargetRegisterClass *const * regclass_iterator
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
iterator_range< regclass_iterator > regclasses() const
virtual bool shouldRegionSplitForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Region split has a high compile time cost especially for large live range.
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
bool getCoveringSubRegIndexes(const TargetRegisterClass *RC, LaneBitmask LaneMask, SmallVectorImpl< unsigned > &Indexes) const
Try to find one or more subregister indexes to cover LaneMask.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
const TargetRegisterClass * getMinimalPhysRegClassLLT(MCRegister Reg, LLT Ty=LLT()) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
void markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const
Mark a register and all its aliases as reserved in the given set.
virtual float getSpillWeightScaleFactor(const TargetRegisterClass *RC) const
Get the scale factor of spill weight for this register class.
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
TypeSize getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
virtual Register lookThruSingleUseCopyChain(Register SrcReg, const MachineRegisterInfo *MRI) const
Find the original SrcReg unless it is the target of a copy-like operation, in which case we chain bac...
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
bool checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const
Returns true if for every register in the set all super registers are part of the set as well.
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
virtual Register lookThruCopyLike(Register SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
const TargetRegisterClass * getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const
Find a common super-register class if it exists.
unsigned getSubRegIdxSize(unsigned Idx) const
Get the size of the bit range covered by a sub-register index.
static void dumpReg(Register Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)
Debugging helper: dump register in human readable form to dbgs() stream.
virtual bool shouldRealignStack(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RCB, regclass_iterator RCE, const char *const *SRINames, const SubRegCoveredBits *SubIdxRanges, const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes, const RegClassInfo *const RCIs, const MVT::SimpleValueType *const RCVTLists, unsigned Mode=0)
DIExpression * prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags, const StackOffset &Offset) const
Prepends a DWARF expression for Offset to DIExpression Expr.
const TargetRegisterClass * findCommonRegClass(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
Find a common register class that can accomodate both the source and destination operands of a copy-l...
const TargetRegisterClass * getCommonMinimalPhysRegClass(MCRegister Reg1, MCRegister Reg2, MVT VT=MVT::Other) const
Returns the common Register Class of two physical registers of the given type, picking the most sub r...
virtual bool isCalleeSavedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const
This is a wrapper around getCallPreservedMask().
unsigned getSubRegIdxOffset(unsigned Idx) const
Get the offset of the bit range covered by a sub-register index.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
virtual void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const
Gets the DWARF expression opcodes for Offset.
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not.
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
const TargetRegisterClass * getCommonMinimalPhysRegClassLLT(MCRegister Reg1, MCRegister Reg2, LLT Ty=LLT()) const
Returns the common Register Class of two physical registers of the given type, picking the most sub r...
virtual const TargetInstrInfo * getInstrInfo() const
MCRegister getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
Definition VirtRegMap.h:91
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition raw_ostream.h:53
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition CallingConv.h:24
@ C
The default llvm calling convention, compatible with C.
Definition CallingConv.h:34
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
@ Offset
Definition DWP.cpp:477
LLVM_ABI void printLowerCase(StringRef String, raw_ostream &Out)
printLowerCase - Print each character as lowercase if it is uppercase.
LLVM_ABI Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition bit.h:202
LLVM_ABI Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition Debug.cpp:207
LLVM_ABI Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition MCRegister.h:21
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Definition STLExtras.h:1897
LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition BitVector.h:869
#define N
constexpr bool any() const
Definition LaneBitmask.h:53
unsigned getNumLanes() const
Definition LaneBitmask.h:76
Extra information, not in MCRegisterDesc, about registers.
SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg index, -1 in any being invalid...