LLVM  14.0.0git
TargetRegisterInfo.cpp
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1 //==- TargetRegisterInfo.cpp - Target Register Information Implementation --==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the TargetRegisterInfo interface.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/ArrayRef.h"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/Config/llvm-config.h"
28 #include "llvm/IR/Attributes.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/MC/MCRegisterInfo.h"
33 #include "llvm/Support/Compiler.h"
34 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/Printable.h"
39 #include <cassert>
40 #include <utility>
41 
42 #define DEBUG_TYPE "target-reg-info"
43 
44 using namespace llvm;
45 
46 static cl::opt<unsigned>
47  HugeSizeForSplit("huge-size-for-split", cl::Hidden,
48  cl::desc("A threshold of live range size which may cause "
49  "high compile time cost in global splitting."),
50  cl::init(5000));
51 
54  const char *const *SRINames,
55  const LaneBitmask *SRILaneMasks,
56  LaneBitmask SRICoveringLanes,
57  const RegClassInfo *const RCIs,
58  unsigned Mode)
59  : InfoDesc(ID), SubRegIndexNames(SRINames),
60  SubRegIndexLaneMasks(SRILaneMasks),
61  RegClassBegin(RCB), RegClassEnd(RCE),
62  CoveringLanes(SRICoveringLanes),
63  RCInfos(RCIs), HwMode(Mode) {
64 }
65 
67 
69  const MachineFunction &MF, const LiveInterval &VirtReg) const {
71  const MachineRegisterInfo &MRI = MF.getRegInfo();
72  MachineInstr *MI = MRI.getUniqueVRegDef(VirtReg.reg());
73  if (MI && TII->isTriviallyReMaterializable(*MI) &&
74  VirtReg.size() > HugeSizeForSplit)
75  return false;
76  return true;
77 }
78 
80  MCRegister Reg) const {
81  for (MCSuperRegIterator AI(Reg, this, true); AI.isValid(); ++AI)
82  RegisterSet.set(*AI);
83 }
84 
86  ArrayRef<MCPhysReg> Exceptions) const {
87  // Check that all super registers of reserved regs are reserved as well.
88  BitVector Checked(getNumRegs());
89  for (unsigned Reg : RegisterSet.set_bits()) {
90  if (Checked[Reg])
91  continue;
92  for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) {
93  if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) {
94  dbgs() << "Error: Super register " << printReg(*SR, this)
95  << " of reserved register " << printReg(Reg, this)
96  << " is not reserved.\n";
97  return false;
98  }
99 
100  // We transitively check superregs. So we can remember this for later
101  // to avoid compiletime explosion in deep register hierarchies.
102  Checked.set(*SR);
103  }
104  }
105  return true;
106 }
107 
108 namespace llvm {
109 
111  unsigned SubIdx, const MachineRegisterInfo *MRI) {
112  return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) {
113  if (!Reg)
114  OS << "$noreg";
115  else if (Register::isStackSlot(Reg))
116  OS << "SS#" << Register::stackSlot2Index(Reg);
117  else if (Register::isVirtualRegister(Reg)) {
118  StringRef Name = MRI ? MRI->getVRegName(Reg) : "";
119  if (Name != "") {
120  OS << '%' << Name;
121  } else {
122  OS << '%' << Register::virtReg2Index(Reg);
123  }
124  } else if (!TRI)
125  OS << '$' << "physreg" << Reg;
126  else if (Reg < TRI->getNumRegs()) {
127  OS << '$';
128  printLowerCase(TRI->getName(Reg), OS);
129  } else
130  llvm_unreachable("Register kind is unsupported.");
131 
132  if (SubIdx) {
133  if (TRI)
134  OS << ':' << TRI->getSubRegIndexName(SubIdx);
135  else
136  OS << ":sub(" << SubIdx << ')';
137  }
138  });
139 }
140 
142  return Printable([Unit, TRI](raw_ostream &OS) {
143  // Generic printout when TRI is missing.
144  if (!TRI) {
145  OS << "Unit~" << Unit;
146  return;
147  }
148 
149  // Check for invalid register units.
150  if (Unit >= TRI->getNumRegUnits()) {
151  OS << "BadUnit~" << Unit;
152  return;
153  }
154 
155  // Normal units have at least one root.
156  MCRegUnitRootIterator Roots(Unit, TRI);
157  assert(Roots.isValid() && "Unit has no roots.");
158  OS << TRI->getName(*Roots);
159  for (++Roots; Roots.isValid(); ++Roots)
160  OS << '~' << TRI->getName(*Roots);
161  });
162 }
163 
165  return Printable([Unit, TRI](raw_ostream &OS) {
166  if (Register::isVirtualRegister(Unit)) {
167  OS << '%' << Register::virtReg2Index(Unit);
168  } else {
169  OS << printRegUnit(Unit, TRI);
170  }
171  });
172 }
173 
175  const TargetRegisterInfo *TRI) {
176  return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) {
177  if (RegInfo.getRegClassOrNull(Reg))
178  OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
179  else if (RegInfo.getRegBankOrNull(Reg))
180  OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
181  else {
182  OS << "_";
183  assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
184  "Generic registers must have a valid type");
185  }
186  });
187 }
188 
189 } // end namespace llvm
190 
191 /// getAllocatableClass - Return the maximal subclass of the given register
192 /// class that is alloctable, or NULL.
193 const TargetRegisterClass *
195  if (!RC || RC->isAllocatable())
196  return RC;
197 
198  for (BitMaskClassIterator It(RC->getSubClassMask(), *this); It.isValid();
199  ++It) {
200  const TargetRegisterClass *SubRC = getRegClass(It.getID());
201  if (SubRC->isAllocatable())
202  return SubRC;
203  }
204  return nullptr;
205 }
206 
207 /// getMinimalPhysRegClass - Returns the Register Class of a physical
208 /// register of the given type, picking the most sub register class of
209 /// the right type that contains this physreg.
210 const TargetRegisterClass *
213  "reg must be a physical register");
214 
215  // Pick the most sub register class of the right type that contains
216  // this physreg.
217  const TargetRegisterClass* BestRC = nullptr;
218  for (const TargetRegisterClass* RC : regclasses()) {
219  if ((VT == MVT::Other || isTypeLegalForClass(*RC, VT)) &&
220  RC->contains(reg) && (!BestRC || BestRC->hasSubClass(RC)))
221  BestRC = RC;
222  }
223 
224  assert(BestRC && "Couldn't find the register class");
225  return BestRC;
226 }
227 
228 const TargetRegisterClass *
231  "reg must be a physical register");
232 
233  // Pick the most sub register class of the right type that contains
234  // this physreg.
235  const TargetRegisterClass *BestRC = nullptr;
236  for (const TargetRegisterClass *RC : regclasses()) {
237  if ((!Ty.isValid() || isTypeLegalForClass(*RC, Ty)) && RC->contains(reg) &&
238  (!BestRC || BestRC->hasSubClass(RC)))
239  BestRC = RC;
240  }
241 
242  return BestRC;
243 }
244 
245 /// getAllocatableSetForRC - Toggle the bits that represent allocatable
246 /// registers for the specific register class.
248  const TargetRegisterClass *RC, BitVector &R){
249  assert(RC->isAllocatable() && "invalid for nonallocatable sets");
251  for (unsigned i = 0; i != Order.size(); ++i)
252  R.set(Order[i]);
253 }
254 
256  const TargetRegisterClass *RC) const {
257  BitVector Allocatable(getNumRegs());
258  if (RC) {
259  // A register class with no allocatable subclass returns an empty set.
260  const TargetRegisterClass *SubClass = getAllocatableClass(RC);
261  if (SubClass)
262  getAllocatableSetForRC(MF, SubClass, Allocatable);
263  } else {
264  for (const TargetRegisterClass *C : regclasses())
265  if (C->isAllocatable())
266  getAllocatableSetForRC(MF, C, Allocatable);
267  }
268 
269  // Mask out the reserved registers
270  const MachineRegisterInfo &MRI = MF.getRegInfo();
271  const BitVector &Reserved = MRI.getReservedRegs();
272  Allocatable.reset(Reserved);
273 
274  return Allocatable;
275 }
276 
277 static inline
279  const uint32_t *B,
280  const TargetRegisterInfo *TRI) {
281  for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32)
282  if (unsigned Common = *A++ & *B++)
283  return TRI->getRegClass(I + countTrailingZeros(Common));
284  return nullptr;
285 }
286 
287 const TargetRegisterClass *
289  const TargetRegisterClass *B) const {
290  // First take care of the trivial cases.
291  if (A == B)
292  return A;
293  if (!A || !B)
294  return nullptr;
295 
296  // Register classes are ordered topologically, so the largest common
297  // sub-class it the common sub-class with the smallest ID.
298  return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this);
299 }
300 
301 const TargetRegisterClass *
303  const TargetRegisterClass *B,
304  unsigned Idx) const {
305  assert(A && B && "Missing register class");
306  assert(Idx && "Bad sub-register index");
307 
308  // Find Idx in the list of super-register indices.
309  for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
310  if (RCI.getSubReg() == Idx)
311  // The bit mask contains all register classes that are projected into B
312  // by Idx. Find a class that is also a sub-class of A.
313  return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);
314  return nullptr;
315 }
316 
318 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
319  const TargetRegisterClass *RCB, unsigned SubB,
320  unsigned &PreA, unsigned &PreB) const {
321  assert(RCA && SubA && RCB && SubB && "Invalid arguments");
322 
323  // Search all pairs of sub-register indices that project into RCA and RCB
324  // respectively. This is quadratic, but usually the sets are very small. On
325  // most targets like X86, there will only be a single sub-register index
326  // (e.g., sub_16bit projecting into GR16).
327  //
328  // The worst case is a register class like DPR on ARM.
329  // We have indices dsub_0..dsub_7 projecting into that class.
330  //
331  // It is very common that one register class is a sub-register of the other.
332  // Arrange for RCA to be the larger register so the answer will be found in
333  // the first iteration. This makes the search linear for the most common
334  // case.
335  const TargetRegisterClass *BestRC = nullptr;
336  unsigned *BestPreA = &PreA;
337  unsigned *BestPreB = &PreB;
338  if (getRegSizeInBits(*RCA) < getRegSizeInBits(*RCB)) {
339  std::swap(RCA, RCB);
340  std::swap(SubA, SubB);
341  std::swap(BestPreA, BestPreB);
342  }
343 
344  // Also terminate the search one we have found a register class as small as
345  // RCA.
346  unsigned MinSize = getRegSizeInBits(*RCA);
347 
348  for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) {
349  unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
350  for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) {
351  // Check if a common super-register class exists for this index pair.
352  const TargetRegisterClass *RC =
353  firstCommonClass(IA.getMask(), IB.getMask(), this);
354  if (!RC || getRegSizeInBits(*RC) < MinSize)
355  continue;
356 
357  // The indexes must compose identically: PreA+SubA == PreB+SubB.
358  unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
359  if (FinalA != FinalB)
360  continue;
361 
362  // Is RC a better candidate than BestRC?
363  if (BestRC && getRegSizeInBits(*RC) >= getRegSizeInBits(*BestRC))
364  continue;
365 
366  // Yes, RC is the smallest super-register seen so far.
367  BestRC = RC;
368  *BestPreA = IA.getSubReg();
369  *BestPreB = IB.getSubReg();
370 
371  // Bail early if we reached MinSize. We won't find a better candidate.
372  if (getRegSizeInBits(*BestRC) == MinSize)
373  return BestRC;
374  }
375  }
376  return BestRC;
377 }
378 
379 /// Check if the registers defined by the pair (RegisterClass, SubReg)
380 /// share the same register file.
382  const TargetRegisterClass *DefRC,
383  unsigned DefSubReg,
384  const TargetRegisterClass *SrcRC,
385  unsigned SrcSubReg) {
386  // Same register class.
387  if (DefRC == SrcRC)
388  return true;
389 
390  // Both operands are sub registers. Check if they share a register class.
391  unsigned SrcIdx, DefIdx;
392  if (SrcSubReg && DefSubReg) {
393  return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
394  SrcIdx, DefIdx) != nullptr;
395  }
396 
397  // At most one of the register is a sub register, make it Src to avoid
398  // duplicating the test.
399  if (!SrcSubReg) {
400  std::swap(DefSubReg, SrcSubReg);
401  std::swap(DefRC, SrcRC);
402  }
403 
404  // One of the register is a sub register, check if we can get a superclass.
405  if (SrcSubReg)
406  return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
407 
408  // Plain copy.
409  return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
410 }
411 
413  unsigned DefSubReg,
414  const TargetRegisterClass *SrcRC,
415  unsigned SrcSubReg) const {
416  // If this source does not incur a cross register bank copy, use it.
417  return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg);
418 }
419 
420 // Compute target-independent register allocator hints to help eliminate copies.
422  Register VirtReg, ArrayRef<MCPhysReg> Order,
424  const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
425  const MachineRegisterInfo &MRI = MF.getRegInfo();
426  const std::pair<Register, SmallVector<Register, 4>> &Hints_MRI =
427  MRI.getRegAllocationHints(VirtReg);
428 
429  SmallSet<Register, 32> HintedRegs;
430  // First hint may be a target hint.
431  bool Skip = (Hints_MRI.first != 0);
432  for (auto Reg : Hints_MRI.second) {
433  if (Skip) {
434  Skip = false;
435  continue;
436  }
437 
438  // Target-independent hints are either a physical or a virtual register.
439  Register Phys = Reg;
440  if (VRM && Phys.isVirtual())
441  Phys = VRM->getPhys(Phys);
442 
443  // Don't add the same reg twice (Hints_MRI may contain multiple virtual
444  // registers allocated to the same physreg).
445  if (!HintedRegs.insert(Phys).second)
446  continue;
447  // Check that Phys is a valid hint in VirtReg's register class.
448  if (!Phys.isPhysical())
449  continue;
450  if (MRI.isReserved(Phys))
451  continue;
452  // Check that Phys is in the allocation order. We shouldn't heed hints
453  // from VirtReg's register class if they aren't in the allocation order. The
454  // target probably has a reason for removing the register.
455  if (!is_contained(Order, Phys))
456  continue;
457 
458  // All clear, tell the register allocator to prefer this register.
459  Hints.push_back(Phys);
460  }
461  return false;
462 }
463 
465  MCRegister PhysReg, const MachineFunction &MF) const {
466  if (PhysReg == 0)
467  return false;
468  const uint32_t *callerPreservedRegs =
470  if (callerPreservedRegs) {
472  "Expected physical register");
473  return (callerPreservedRegs[PhysReg / 32] >> PhysReg % 32) & 1;
474  }
475  return false;
476 }
477 
479  return !MF.getFunction().hasFnAttribute("no-realign-stack");
480 }
481 
483  const MachineFrameInfo &MFI = MF.getFrameInfo();
485  const Function &F = MF.getFunction();
486  return F.hasFnAttribute("stackrealign") ||
487  (MFI.getMaxAlign() > TFI->getStackAlign()) ||
488  F.hasFnAttribute(Attribute::StackAlignment);
489 }
490 
492  const uint32_t *mask1) const {
493  unsigned N = (getNumRegs()+31) / 32;
494  for (unsigned I = 0; I < N; ++I)
495  if ((mask0[I] & mask1[I]) != mask0[I])
496  return false;
497  return true;
498 }
499 
500 unsigned
502  const MachineRegisterInfo &MRI) const {
503  const TargetRegisterClass *RC{};
504  if (Reg.isPhysical()) {
505  // The size is not directly available for physical registers.
506  // Instead, we need to access a register class that contains Reg and
507  // get the size of that register class.
509  } else {
510  LLT Ty = MRI.getType(Reg);
511  unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0;
512  // If Reg is not a generic register, query the register class to
513  // get its size.
514  if (RegSize)
515  return RegSize;
516  // Since Reg is not a generic register, it must have a register class.
517  RC = MRI.getRegClass(Reg);
518  }
519  assert(RC && "Unable to deduce the register class");
520  return getRegSizeInBits(*RC);
521 }
522 
524  const MachineRegisterInfo &MRI, const TargetRegisterClass *RC,
525  LaneBitmask LaneMask, SmallVectorImpl<unsigned> &NeededIndexes) const {
526  SmallVector<unsigned, 8> PossibleIndexes;
527  unsigned BestIdx = 0;
528  unsigned BestCover = 0;
529 
530  for (unsigned Idx = 1, E = getNumSubRegIndices(); Idx < E; ++Idx) {
531  // Is this index even compatible with the given class?
532  if (getSubClassWithSubReg(RC, Idx) != RC)
533  continue;
534  LaneBitmask SubRegMask = getSubRegIndexLaneMask(Idx);
535  // Early exit if we found a perfect match.
536  if (SubRegMask == LaneMask) {
537  BestIdx = Idx;
538  break;
539  }
540 
541  // The index must not cover any lanes outside \p LaneMask.
542  if ((SubRegMask & ~LaneMask).any())
543  continue;
544 
545  unsigned PopCount = SubRegMask.getNumLanes();
546  PossibleIndexes.push_back(Idx);
547  if (PopCount > BestCover) {
548  BestCover = PopCount;
549  BestIdx = Idx;
550  }
551  }
552 
553  // Abort if we cannot possibly implement the COPY with the given indexes.
554  if (BestIdx == 0)
555  return 0;
556 
557  NeededIndexes.push_back(BestIdx);
558 
559  // Greedy heuristic: Keep iterating keeping the best covering subreg index
560  // each time.
561  LaneBitmask LanesLeft = LaneMask & ~getSubRegIndexLaneMask(BestIdx);
562  while (LanesLeft.any()) {
563  unsigned BestIdx = 0;
564  int BestCover = std::numeric_limits<int>::min();
565  for (unsigned Idx : PossibleIndexes) {
566  LaneBitmask SubRegMask = getSubRegIndexLaneMask(Idx);
567  // Early exit if we found a perfect match.
568  if (SubRegMask == LanesLeft) {
569  BestIdx = Idx;
570  break;
571  }
572 
573  // Try to cover as much of the remaining lanes as possible but
574  // as few of the already covered lanes as possible.
575  int Cover = (SubRegMask & LanesLeft).getNumLanes() -
576  (SubRegMask & ~LanesLeft).getNumLanes();
577  if (Cover > BestCover) {
578  BestCover = Cover;
579  BestIdx = Idx;
580  }
581  }
582 
583  if (BestIdx == 0)
584  return 0; // Impossible to handle
585 
586  NeededIndexes.push_back(BestIdx);
587 
588  LanesLeft &= ~getSubRegIndexLaneMask(BestIdx);
589  }
590 
591  return BestIdx;
592 }
593 
594 Register
596  const MachineRegisterInfo *MRI) const {
597  while (true) {
598  const MachineInstr *MI = MRI->getVRegDef(SrcReg);
599  if (!MI->isCopyLike())
600  return SrcReg;
601 
602  Register CopySrcReg;
603  if (MI->isCopy())
604  CopySrcReg = MI->getOperand(1).getReg();
605  else {
606  assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");
607  CopySrcReg = MI->getOperand(2).getReg();
608  }
609 
610  if (!CopySrcReg.isVirtual())
611  return CopySrcReg;
612 
613  SrcReg = CopySrcReg;
614  }
615 }
616 
618  Register SrcReg, const MachineRegisterInfo *MRI) const {
619  while (true) {
620  const MachineInstr *MI = MRI->getVRegDef(SrcReg);
621  // Found the real definition, return it if it has a single use.
622  if (!MI->isCopyLike())
623  return MRI->hasOneNonDBGUse(SrcReg) ? SrcReg : Register();
624 
625  Register CopySrcReg;
626  if (MI->isCopy())
627  CopySrcReg = MI->getOperand(1).getReg();
628  else {
629  assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");
630  CopySrcReg = MI->getOperand(2).getReg();
631  }
632 
633  // Continue only if the next definition in the chain is for a virtual
634  // register that has a single use.
635  if (!CopySrcReg.isVirtual() || !MRI->hasOneNonDBGUse(CopySrcReg))
636  return Register();
637 
638  SrcReg = CopySrcReg;
639  }
640 }
641 
643  const StackOffset &Offset, SmallVectorImpl<uint64_t> &Ops) const {
644  assert(!Offset.getScalable() && "Scalable offsets are not handled");
645  DIExpression::appendOffset(Ops, Offset.getFixed());
646 }
647 
648 DIExpression *
650  unsigned PrependFlags,
651  const StackOffset &Offset) const {
652  assert((PrependFlags &
655  "Unsupported prepend flag");
656  SmallVector<uint64_t, 16> OffsetExpr;
657  if (PrependFlags & DIExpression::DerefBefore)
658  OffsetExpr.push_back(dwarf::DW_OP_deref);
659  getOffsetOpcodes(Offset, OffsetExpr);
660  if (PrependFlags & DIExpression::DerefAfter)
661  OffsetExpr.push_back(dwarf::DW_OP_deref);
662  return DIExpression::prependOpcodes(Expr, OffsetExpr,
663  PrependFlags & DIExpression::StackValue,
664  PrependFlags & DIExpression::EntryValue);
665 }
666 
667 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
669 void TargetRegisterInfo::dumpReg(Register Reg, unsigned SubRegIndex,
670  const TargetRegisterInfo *TRI) {
671  dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n";
672 }
673 #endif
llvm::LaneBitmask
Definition: LaneBitmask.h:40
i
i
Definition: README.txt:29
llvm::TargetRegisterInfo::getSubClassWithSubReg
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
Definition: TargetRegisterInfo.h:613
llvm::TargetRegisterInfo::shouldRegionSplitForVirtReg
virtual bool shouldRegionSplitForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Region split has a high compile time cost especially for large live range.
Definition: TargetRegisterInfo.cpp:68
llvm::TargetRegisterInfo::~TargetRegisterInfo
virtual ~TargetRegisterInfo()
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
LLVM_DUMP_METHOD
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:491
MathExtras.h
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MCRegisterInfo::getName
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
Definition: MCRegisterInfo.h:485
TargetFrameLowering.h
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:43
llvm::MachineRegisterInfo::getVRegName
StringRef getVRegName(Register Reg) const
Definition: MachineRegisterInfo.h:428
llvm::printVRegOrUnit
Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
Definition: TargetRegisterInfo.cpp:164
DebugInfoMetadata.h
llvm::TargetRegisterClass::isAllocatable
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
Definition: TargetRegisterInfo.h:117
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
Printable.h
llvm::Function
Definition: Function.h:61
llvm::TargetRegisterInfo::dumpReg
static void dumpReg(Register Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)
Debugging helper: dump register in human readable form to dbgs() stream.
Definition: TargetRegisterInfo.cpp:669
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:343
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
llvm::SmallVector< unsigned, 8 >
llvm::TargetRegisterInfo::getMinimalPhysRegClassLLT
const TargetRegisterClass * getMinimalPhysRegClassLLT(MCRegister Reg, LLT Ty=LLT()) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:229
llvm::SuperRegClassIterator::isValid
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Definition: TargetRegisterInfo.h:1134
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::LaneBitmask::getNumLanes
unsigned getNumLanes() const
Definition: LaneBitmask.h:76
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
llvm::TargetRegisterInfo::getAllocatableSet
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not.
Definition: TargetRegisterInfo.cpp:255
llvm::MachineRegisterInfo::getUniqueVRegDef
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
Definition: MachineRegisterInfo.cpp:411
llvm::TargetRegisterInfo::getOffsetOpcodes
virtual void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const
Gets the DWARF expression opcodes for Offset.
Definition: TargetRegisterInfo.cpp:642
llvm::TargetRegisterInfo::shouldRealignStack
virtual bool shouldRealignStack(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
Definition: TargetRegisterInfo.cpp:482
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::Register::stackSlot2Index
static int stackSlot2Index(Register Reg)
Compute the frame index from a register value representing a stack slot.
Definition: Register.h:52
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::TargetRegisterInfo::markSuperRegs
void markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const
Mark a register and all its aliases as reserved in the given set.
Definition: TargetRegisterInfo.cpp:79
TargetInstrInfo.h
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:117
getAllocatableSetForRC
static void getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R)
getAllocatableSetForRC - Toggle the bits that represent allocatable registers for the specific regist...
Definition: TargetRegisterInfo.cpp:247
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::TargetRegisterInfo::isCalleeSavedPhysReg
virtual bool isCalleeSavedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const
This is a wrapper around getCallPreservedMask().
Definition: TargetRegisterInfo.cpp:464
STLExtras.h
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2586
llvm::TargetRegisterInfo::RegClassInfo
Definition: TargetRegisterInfo.h:237
llvm::MCRegisterInfo::getNumRegUnits
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
Definition: MCRegisterInfo.h:505
RegisterSet
SmallSet< unsigned, 4 > RegisterSet
Definition: Thumb2ITBlockPass.cpp:39
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::MCRegisterInfo::getNumSubRegIndices
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
Definition: MCRegisterInfo.h:498
llvm::TargetRegisterClass::getSubClassMask
const uint32_t * getSubClassMask() const
Returns a bit vector of subclasses, including this one.
Definition: TargetRegisterInfo.h:158
llvm::LegalityPredicates::any
Predicate any(Predicate P0, Predicate P1)
True iff P0 or P1 are true.
Definition: LegalizerInfo.h:241
llvm::BitMaskClassIterator::isValid
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Definition: TargetRegisterInfo.h:1232
F
#define F(x, y, z)
Definition: MD5.cpp:56
MachineRegisterInfo.h
MachineValueType.h
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
CommandLine.h
llvm::Register::isPhysical
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
llvm::TargetRegisterInfo::canRealignStack
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
Definition: TargetRegisterInfo.cpp:478
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:636
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::TargetRegisterInfo::getSubRegIndexLaneMask
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
Definition: TargetRegisterInfo.h:377
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::TargetFrameLowering::getStackAlign
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:100
llvm::Register::isStackSlot
static bool isStackSlot(unsigned Reg)
isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable th...
Definition: Register.h:44
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:915
llvm::LLT::getSizeInBits
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:153
llvm::TargetRegisterClass::getRawAllocationOrder
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
Definition: TargetRegisterInfo.h:199
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
BitVector.h
llvm::LiveRange::size
size_t size() const
Definition: LiveInterval.h:297
llvm::TargetRegisterInfo::getMatchingSuperRegClass
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
Definition: TargetRegisterInfo.cpp:302
llvm::BitVector
Definition: BitVector.h:74
llvm::LiveInterval
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:680
llvm::SuperRegClassIterator
Definition: TargetRegisterInfo.h:1115
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:400
llvm::printRegUnit
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
Definition: TargetRegisterInfo.cpp:141
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::TargetRegisterInfo::regclasses
iterator_range< regclass_iterator > regclasses() const
Definition: TargetRegisterInfo.h:729
llvm::TargetRegisterInfo::regmaskSubsetEqual
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
Definition: TargetRegisterInfo.cpp:491
llvm::Register::isVirtual
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:626
llvm::cl::opt
Definition: CommandLine.h:1434
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:739
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:239
llvm::DIExpression::StackValue
@ StackValue
Definition: DebugInfoMetadata.h:2796
VirtRegMap.h
llvm::TargetRegisterInfo::getRegClassName
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Definition: TargetRegisterInfo.h:745
llvm::TargetRegisterInfo::getCommonSuperRegClass
const TargetRegisterClass * getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const
Find a common super-register class if it exists.
Definition: TargetRegisterInfo.cpp:318
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::VirtRegMap::getPhys
MCRegister getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:106
llvm::TargetRegisterInfo::getRegAllocationHints
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
Definition: TargetRegisterInfo.cpp:421
llvm::LaneBitmask::any
constexpr bool any() const
Definition: LaneBitmask.h:53
StringExtras.h
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
MCRegisterInfo.h
llvm::StringRef::lower
LLVM_NODISCARD std::string lower() const
Definition: StringRef.cpp:105
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1616
ArrayRef.h
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MachineRegisterInfo::getRegClassOrNull
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
Definition: MachineRegisterInfo.h:651
llvm::DIExpression::DerefBefore
@ DerefBefore
Definition: DebugInfoMetadata.h:2794
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:840
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:642
llvm::TargetRegisterInfo::getCommonSubClass
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
Definition: TargetRegisterInfo.cpp:288
llvm::MCSuperRegIterator
MCSuperRegIterator enumerates all super-registers of Reg.
Definition: MCRegisterInfo.h:641
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::printRegClassOrBank
Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
Definition: TargetRegisterInfo.cpp:174
llvm::TargetRegisterInfo::TargetRegisterInfo
TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RCB, regclass_iterator RCE, const char *const *SRINames, const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes, const RegClassInfo *const RCIs, unsigned Mode=0)
Definition: TargetRegisterInfo.cpp:52
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::countTrailingZeros
unsigned countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition: MathExtras.h:156
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MachineRegisterInfo::hasOneNonDBGUse
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
Definition: MachineRegisterInfo.cpp:419
llvm::TargetRegisterInfo::composeSubRegIndices
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
Definition: TargetRegisterInfo.h:631
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::TargetRegisterInfo::getCoveringSubRegIndexes
bool getCoveringSubRegIndexes(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, LaneBitmask LaneMask, SmallVectorImpl< unsigned > &Indexes) const
Try to find one or more subregister indexes to cover LaneMask.
Definition: TargetRegisterInfo.cpp:523
if
if(llvm_vc STREQUAL "") set(fake_version_inc "$
Definition: CMakeLists.txt:14
llvm::TargetRegisterInfo::isTypeLegalForClass
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
Definition: TargetRegisterInfo.h:293
uint32_t
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
Compiler.h
TargetSubtargetInfo.h
llvm::SmallSet::insert
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:180
llvm::MachineRegisterInfo::getRegAllocationHints
const std::pair< Register, SmallVector< Register, 4 > > & getRegAllocationHints(Register VReg) const
getRegAllocationHints - Return a reference to the vector of all register allocation hints for VReg.
Definition: MachineRegisterInfo.h:814
llvm::MachineRegisterInfo::getReservedRegs
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
Definition: MachineRegisterInfo.h:904
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MachineFrameInfo::getMaxAlign
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Definition: MachineFrameInfo.h:569
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::TargetRegisterInfo::lookThruSingleUseCopyChain
virtual Register lookThruSingleUseCopyChain(Register SrcReg, const MachineRegisterInfo *MRI) const
Find the original SrcReg unless it is the target of a copy-like operation, in which case we chain bac...
Definition: TargetRegisterInfo.cpp:617
Attributes.h
llvm::TargetRegisterInfo::shouldRewriteCopySrc
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
Definition: TargetRegisterInfo.cpp:412
llvm::DIExpression::appendOffset
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
Definition: DebugInfoMetadata.cpp:1228
llvm::DIExpression::prependOpcodes
static DIExpression * prependOpcodes(const DIExpression *Expr, SmallVectorImpl< uint64_t > &Ops, bool StackValue=false, bool EntryValue=false)
Prepend DIExpr with the given opcodes and optionally turn it into a stack value.
Definition: DebugInfoMetadata.cpp:1358
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::TargetRegisterInfo::lookThruCopyLike
virtual Register lookThruCopyLike(Register SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
Definition: TargetRegisterInfo.cpp:595
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:592
llvm::TargetSubtargetInfo::getFrameLowering
virtual const TargetFrameLowering * getFrameLowering() const
Definition: TargetSubtargetInfo.h:93
llvm::DIExpression::DerefAfter
@ DerefAfter
Definition: DebugInfoMetadata.h:2795
llvm::TargetRegisterInfo::getRegSizeInBits
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Definition: TargetRegisterInfo.h:276
MachineFrameInfo.h
firstCommonClass
static const TargetRegisterClass * firstCommonClass(const uint32_t *A, const uint32_t *B, const TargetRegisterInfo *TRI)
Definition: TargetRegisterInfo.cpp:278
llvm::RegisterBank::getName
const char * getName() const
Get a user friendly name of this register bank.
Definition: RegisterBank.h:51
shareSameRegisterFile
static bool shareSameRegisterFile(const TargetRegisterInfo &TRI, const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg)
Check if the registers defined by the pair (RegisterClass, SubReg) share the same register file.
Definition: TargetRegisterInfo.cpp:381
Function.h
llvm::MachineRegisterInfo::getRegBankOrNull
const RegisterBank * getRegBankOrNull(Register Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
Definition: MachineRegisterInfo.h:660
llvm::TargetRegisterInfo::getNumRegClasses
unsigned getNumRegClasses() const
Definition: TargetRegisterInfo.h:733
llvm::TargetRegisterInfo::regclass_iterator
const TargetRegisterClass *const * regclass_iterator
Definition: TargetRegisterInfo.h:235
llvm::BitVector::reset
BitVector & reset()
Definition: BitVector.h:384
LiveInterval.h
llvm::MCRegUnitRootIterator
MCRegUnitRootIterator enumerates the root registers of a register unit.
Definition: MCRegisterInfo.h:746
llvm::TargetRegisterClass::hasSubClass
bool hasSubClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
Definition: TargetRegisterInfo.h:121
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
llvm::Printable
Simple wrapper around std::function<void(raw_ostream&)>.
Definition: Printable.h:38
N
#define N
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::LiveInterval::reg
Register reg() const
Definition: LiveInterval.h:711
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
llvm::TargetRegisterInfoDesc
Extra information, not in MCRegisterDesc, about registers.
Definition: TargetRegisterInfo.h:213
llvm::TargetRegisterInfo::getAllocatableClass
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
Definition: TargetRegisterInfo.cpp:194
llvm::SmallVectorImpl< MCPhysReg >
llvm::BitMaskClassIterator
This class encapuslates the logic to iterate over bitmask returned by the various RegClass related AP...
Definition: TargetRegisterInfo.h:1161
HugeSizeForSplit
static cl::opt< unsigned > HugeSizeForSplit("huge-size-for-split", cl::Hidden, cl::desc("A threshold of live range size which may cause " "high compile time cost in global splitting."), cl::init(5000))
llvm::TargetRegisterInfo::checkAllSuperRegsMarked
bool checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const
Returns true if for every register in the set all super registers are part of the set as well.
Definition: TargetRegisterInfo.cpp:85
llvm::Register::virtReg2Index
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
Definition: Register.h:77
llvm::cl::desc
Definition: CommandLine.h:414
llvm::TargetRegisterInfo::getMinimalPhysRegClass
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:211
llvm::TargetRegisterInfo::getSubRegIndexName
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
Definition: TargetRegisterInfo.h:367
raw_ostream.h
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
TargetRegisterInfo.h
Debug.h
llvm::DIExpression::EntryValue
@ EntryValue
Definition: DebugInfoMetadata.h:2797
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:487
llvm::TargetRegisterInfo::prependOffsetExpression
DIExpression * prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags, const StackOffset &Offset) const
Prepends a DWARF expression for Offset to DIExpression Expr.
Definition: TargetRegisterInfo.cpp:649
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:23
SmallSet.h
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37
llvm::LiveRegMatrix
Definition: LiveRegMatrix.h:40
llvm::LLT
Definition: LowLevelTypeImpl.h:40