LLVM  15.0.0git
TargetRegisterInfo.cpp
Go to the documentation of this file.
1 //==- TargetRegisterInfo.cpp - Target Register Information Implementation --==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the TargetRegisterInfo interface.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/ArrayRef.h"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/ADT/StringExtras.h"
28 #include "llvm/Config/llvm-config.h"
29 #include "llvm/IR/Attributes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/MC/MCRegisterInfo.h"
34 #include "llvm/Support/Compiler.h"
35 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/Printable.h"
40 #include <cassert>
41 #include <utility>
42 
43 #define DEBUG_TYPE "target-reg-info"
44 
45 using namespace llvm;
46 
47 static cl::opt<unsigned>
48  HugeSizeForSplit("huge-size-for-split", cl::Hidden,
49  cl::desc("A threshold of live range size which may cause "
50  "high compile time cost in global splitting."),
51  cl::init(5000));
52 
55  const char *const *SRINames,
56  const LaneBitmask *SRILaneMasks,
57  LaneBitmask SRICoveringLanes,
58  const RegClassInfo *const RCIs,
59  unsigned Mode)
60  : InfoDesc(ID), SubRegIndexNames(SRINames),
61  SubRegIndexLaneMasks(SRILaneMasks),
62  RegClassBegin(RCB), RegClassEnd(RCE),
63  CoveringLanes(SRICoveringLanes),
64  RCInfos(RCIs), HwMode(Mode) {
65 }
66 
68 
70  const MachineFunction &MF, const LiveInterval &VirtReg) const {
72  const MachineRegisterInfo &MRI = MF.getRegInfo();
73  MachineInstr *MI = MRI.getUniqueVRegDef(VirtReg.reg());
74  if (MI && TII->isTriviallyReMaterializable(*MI) &&
75  VirtReg.size() > HugeSizeForSplit)
76  return false;
77  return true;
78 }
79 
81  MCRegister Reg) const {
82  for (MCSuperRegIterator AI(Reg, this, true); AI.isValid(); ++AI)
83  RegisterSet.set(*AI);
84 }
85 
87  ArrayRef<MCPhysReg> Exceptions) const {
88  // Check that all super registers of reserved regs are reserved as well.
89  BitVector Checked(getNumRegs());
90  for (unsigned Reg : RegisterSet.set_bits()) {
91  if (Checked[Reg])
92  continue;
93  for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) {
94  if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) {
95  dbgs() << "Error: Super register " << printReg(*SR, this)
96  << " of reserved register " << printReg(Reg, this)
97  << " is not reserved.\n";
98  return false;
99  }
100 
101  // We transitively check superregs. So we can remember this for later
102  // to avoid compiletime explosion in deep register hierarchies.
103  Checked.set(*SR);
104  }
105  }
106  return true;
107 }
108 
109 namespace llvm {
110 
112  unsigned SubIdx, const MachineRegisterInfo *MRI) {
113  return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) {
114  if (!Reg)
115  OS << "$noreg";
116  else if (Register::isStackSlot(Reg))
117  OS << "SS#" << Register::stackSlot2Index(Reg);
118  else if (Register::isVirtualRegister(Reg)) {
119  StringRef Name = MRI ? MRI->getVRegName(Reg) : "";
120  if (Name != "") {
121  OS << '%' << Name;
122  } else {
123  OS << '%' << Register::virtReg2Index(Reg);
124  }
125  } else if (!TRI)
126  OS << '$' << "physreg" << Reg;
127  else if (Reg < TRI->getNumRegs()) {
128  OS << '$';
129  printLowerCase(TRI->getName(Reg), OS);
130  } else
131  llvm_unreachable("Register kind is unsupported.");
132 
133  if (SubIdx) {
134  if (TRI)
135  OS << ':' << TRI->getSubRegIndexName(SubIdx);
136  else
137  OS << ":sub(" << SubIdx << ')';
138  }
139  });
140 }
141 
143  return Printable([Unit, TRI](raw_ostream &OS) {
144  // Generic printout when TRI is missing.
145  if (!TRI) {
146  OS << "Unit~" << Unit;
147  return;
148  }
149 
150  // Check for invalid register units.
151  if (Unit >= TRI->getNumRegUnits()) {
152  OS << "BadUnit~" << Unit;
153  return;
154  }
155 
156  // Normal units have at least one root.
157  MCRegUnitRootIterator Roots(Unit, TRI);
158  assert(Roots.isValid() && "Unit has no roots.");
159  OS << TRI->getName(*Roots);
160  for (++Roots; Roots.isValid(); ++Roots)
161  OS << '~' << TRI->getName(*Roots);
162  });
163 }
164 
166  return Printable([Unit, TRI](raw_ostream &OS) {
167  if (Register::isVirtualRegister(Unit)) {
168  OS << '%' << Register::virtReg2Index(Unit);
169  } else {
170  OS << printRegUnit(Unit, TRI);
171  }
172  });
173 }
174 
176  const TargetRegisterInfo *TRI) {
177  return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) {
178  if (RegInfo.getRegClassOrNull(Reg))
179  OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
180  else if (RegInfo.getRegBankOrNull(Reg))
181  OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower();
182  else {
183  OS << "_";
184  assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
185  "Generic registers must have a valid type");
186  }
187  });
188 }
189 
190 } // end namespace llvm
191 
192 /// getAllocatableClass - Return the maximal subclass of the given register
193 /// class that is alloctable, or NULL.
194 const TargetRegisterClass *
196  if (!RC || RC->isAllocatable())
197  return RC;
198 
199  for (BitMaskClassIterator It(RC->getSubClassMask(), *this); It.isValid();
200  ++It) {
201  const TargetRegisterClass *SubRC = getRegClass(It.getID());
202  if (SubRC->isAllocatable())
203  return SubRC;
204  }
205  return nullptr;
206 }
207 
208 /// getMinimalPhysRegClass - Returns the Register Class of a physical
209 /// register of the given type, picking the most sub register class of
210 /// the right type that contains this physreg.
211 const TargetRegisterClass *
214  "reg must be a physical register");
215 
216  // Pick the most sub register class of the right type that contains
217  // this physreg.
218  const TargetRegisterClass* BestRC = nullptr;
219  for (const TargetRegisterClass* RC : regclasses()) {
220  if ((VT == MVT::Other || isTypeLegalForClass(*RC, VT)) &&
221  RC->contains(reg) && (!BestRC || BestRC->hasSubClass(RC)))
222  BestRC = RC;
223  }
224 
225  assert(BestRC && "Couldn't find the register class");
226  return BestRC;
227 }
228 
229 const TargetRegisterClass *
232  "reg must be a physical register");
233 
234  // Pick the most sub register class of the right type that contains
235  // this physreg.
236  const TargetRegisterClass *BestRC = nullptr;
237  for (const TargetRegisterClass *RC : regclasses()) {
238  if ((!Ty.isValid() || isTypeLegalForClass(*RC, Ty)) && RC->contains(reg) &&
239  (!BestRC || BestRC->hasSubClass(RC)))
240  BestRC = RC;
241  }
242 
243  return BestRC;
244 }
245 
246 /// getAllocatableSetForRC - Toggle the bits that represent allocatable
247 /// registers for the specific register class.
249  const TargetRegisterClass *RC, BitVector &R){
250  assert(RC->isAllocatable() && "invalid for nonallocatable sets");
252  for (MCPhysReg PR : Order)
253  R.set(PR);
254 }
255 
257  const TargetRegisterClass *RC) const {
258  BitVector Allocatable(getNumRegs());
259  if (RC) {
260  // A register class with no allocatable subclass returns an empty set.
261  const TargetRegisterClass *SubClass = getAllocatableClass(RC);
262  if (SubClass)
263  getAllocatableSetForRC(MF, SubClass, Allocatable);
264  } else {
265  for (const TargetRegisterClass *C : regclasses())
266  if (C->isAllocatable())
267  getAllocatableSetForRC(MF, C, Allocatable);
268  }
269 
270  // Mask out the reserved registers
271  const MachineRegisterInfo &MRI = MF.getRegInfo();
272  const BitVector &Reserved = MRI.getReservedRegs();
273  Allocatable.reset(Reserved);
274 
275  return Allocatable;
276 }
277 
278 static inline
280  const uint32_t *B,
281  const TargetRegisterInfo *TRI) {
282  for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32)
283  if (unsigned Common = *A++ & *B++)
284  return TRI->getRegClass(I + countTrailingZeros(Common));
285  return nullptr;
286 }
287 
288 const TargetRegisterClass *
290  const TargetRegisterClass *B) const {
291  // First take care of the trivial cases.
292  if (A == B)
293  return A;
294  if (!A || !B)
295  return nullptr;
296 
297  // Register classes are ordered topologically, so the largest common
298  // sub-class it the common sub-class with the smallest ID.
299  return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this);
300 }
301 
302 const TargetRegisterClass *
304  const TargetRegisterClass *B,
305  unsigned Idx) const {
306  assert(A && B && "Missing register class");
307  assert(Idx && "Bad sub-register index");
308 
309  // Find Idx in the list of super-register indices.
310  for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
311  if (RCI.getSubReg() == Idx)
312  // The bit mask contains all register classes that are projected into B
313  // by Idx. Find a class that is also a sub-class of A.
314  return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);
315  return nullptr;
316 }
317 
319 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
320  const TargetRegisterClass *RCB, unsigned SubB,
321  unsigned &PreA, unsigned &PreB) const {
322  assert(RCA && SubA && RCB && SubB && "Invalid arguments");
323 
324  // Search all pairs of sub-register indices that project into RCA and RCB
325  // respectively. This is quadratic, but usually the sets are very small. On
326  // most targets like X86, there will only be a single sub-register index
327  // (e.g., sub_16bit projecting into GR16).
328  //
329  // The worst case is a register class like DPR on ARM.
330  // We have indices dsub_0..dsub_7 projecting into that class.
331  //
332  // It is very common that one register class is a sub-register of the other.
333  // Arrange for RCA to be the larger register so the answer will be found in
334  // the first iteration. This makes the search linear for the most common
335  // case.
336  const TargetRegisterClass *BestRC = nullptr;
337  unsigned *BestPreA = &PreA;
338  unsigned *BestPreB = &PreB;
339  if (getRegSizeInBits(*RCA) < getRegSizeInBits(*RCB)) {
340  std::swap(RCA, RCB);
341  std::swap(SubA, SubB);
342  std::swap(BestPreA, BestPreB);
343  }
344 
345  // Also terminate the search one we have found a register class as small as
346  // RCA.
347  unsigned MinSize = getRegSizeInBits(*RCA);
348 
349  for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) {
350  unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
351  for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) {
352  // Check if a common super-register class exists for this index pair.
353  const TargetRegisterClass *RC =
354  firstCommonClass(IA.getMask(), IB.getMask(), this);
355  if (!RC || getRegSizeInBits(*RC) < MinSize)
356  continue;
357 
358  // The indexes must compose identically: PreA+SubA == PreB+SubB.
359  unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
360  if (FinalA != FinalB)
361  continue;
362 
363  // Is RC a better candidate than BestRC?
364  if (BestRC && getRegSizeInBits(*RC) >= getRegSizeInBits(*BestRC))
365  continue;
366 
367  // Yes, RC is the smallest super-register seen so far.
368  BestRC = RC;
369  *BestPreA = IA.getSubReg();
370  *BestPreB = IB.getSubReg();
371 
372  // Bail early if we reached MinSize. We won't find a better candidate.
373  if (getRegSizeInBits(*BestRC) == MinSize)
374  return BestRC;
375  }
376  }
377  return BestRC;
378 }
379 
380 /// Check if the registers defined by the pair (RegisterClass, SubReg)
381 /// share the same register file.
383  const TargetRegisterClass *DefRC,
384  unsigned DefSubReg,
385  const TargetRegisterClass *SrcRC,
386  unsigned SrcSubReg) {
387  // Same register class.
388  if (DefRC == SrcRC)
389  return true;
390 
391  // Both operands are sub registers. Check if they share a register class.
392  unsigned SrcIdx, DefIdx;
393  if (SrcSubReg && DefSubReg) {
394  return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
395  SrcIdx, DefIdx) != nullptr;
396  }
397 
398  // At most one of the register is a sub register, make it Src to avoid
399  // duplicating the test.
400  if (!SrcSubReg) {
401  std::swap(DefSubReg, SrcSubReg);
402  std::swap(DefRC, SrcRC);
403  }
404 
405  // One of the register is a sub register, check if we can get a superclass.
406  if (SrcSubReg)
407  return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
408 
409  // Plain copy.
410  return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
411 }
412 
414  unsigned DefSubReg,
415  const TargetRegisterClass *SrcRC,
416  unsigned SrcSubReg) const {
417  // If this source does not incur a cross register bank copy, use it.
418  return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg);
419 }
420 
421 // Compute target-independent register allocator hints to help eliminate copies.
423  Register VirtReg, ArrayRef<MCPhysReg> Order,
425  const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
426  const MachineRegisterInfo &MRI = MF.getRegInfo();
427  const std::pair<Register, SmallVector<Register, 4>> &Hints_MRI =
428  MRI.getRegAllocationHints(VirtReg);
429 
430  SmallSet<Register, 32> HintedRegs;
431  // First hint may be a target hint.
432  bool Skip = (Hints_MRI.first != 0);
433  for (auto Reg : Hints_MRI.second) {
434  if (Skip) {
435  Skip = false;
436  continue;
437  }
438 
439  // Target-independent hints are either a physical or a virtual register.
440  Register Phys = Reg;
441  if (VRM && Phys.isVirtual())
442  Phys = VRM->getPhys(Phys);
443 
444  // Don't add the same reg twice (Hints_MRI may contain multiple virtual
445  // registers allocated to the same physreg).
446  if (!HintedRegs.insert(Phys).second)
447  continue;
448  // Check that Phys is a valid hint in VirtReg's register class.
449  if (!Phys.isPhysical())
450  continue;
451  if (MRI.isReserved(Phys))
452  continue;
453  // Check that Phys is in the allocation order. We shouldn't heed hints
454  // from VirtReg's register class if they aren't in the allocation order. The
455  // target probably has a reason for removing the register.
456  if (!is_contained(Order, Phys))
457  continue;
458 
459  // All clear, tell the register allocator to prefer this register.
460  Hints.push_back(Phys);
461  }
462  return false;
463 }
464 
466  MCRegister PhysReg, const MachineFunction &MF) const {
467  if (PhysReg == 0)
468  return false;
469  const uint32_t *callerPreservedRegs =
471  if (callerPreservedRegs) {
473  "Expected physical register");
474  return (callerPreservedRegs[PhysReg / 32] >> PhysReg % 32) & 1;
475  }
476  return false;
477 }
478 
480  return !MF.getFunction().hasFnAttribute("no-realign-stack");
481 }
482 
484  const MachineFrameInfo &MFI = MF.getFrameInfo();
486  const Function &F = MF.getFunction();
487  return F.hasFnAttribute("stackrealign") ||
488  (MFI.getMaxAlign() > TFI->getStackAlign()) ||
489  F.hasFnAttribute(Attribute::StackAlignment);
490 }
491 
493  const uint32_t *mask1) const {
494  unsigned N = (getNumRegs()+31) / 32;
495  for (unsigned I = 0; I < N; ++I)
496  if ((mask0[I] & mask1[I]) != mask0[I])
497  return false;
498  return true;
499 }
500 
501 unsigned
503  const MachineRegisterInfo &MRI) const {
504  const TargetRegisterClass *RC{};
505  if (Reg.isPhysical()) {
506  // The size is not directly available for physical registers.
507  // Instead, we need to access a register class that contains Reg and
508  // get the size of that register class.
510  } else {
511  LLT Ty = MRI.getType(Reg);
512  unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0;
513  // If Reg is not a generic register, query the register class to
514  // get its size.
515  if (RegSize)
516  return RegSize;
517  // Since Reg is not a generic register, it must have a register class.
518  RC = MRI.getRegClass(Reg);
519  }
520  assert(RC && "Unable to deduce the register class");
521  return getRegSizeInBits(*RC);
522 }
523 
525  const MachineRegisterInfo &MRI, const TargetRegisterClass *RC,
526  LaneBitmask LaneMask, SmallVectorImpl<unsigned> &NeededIndexes) const {
527  SmallVector<unsigned, 8> PossibleIndexes;
528  unsigned BestIdx = 0;
529  unsigned BestCover = 0;
530 
531  for (unsigned Idx = 1, E = getNumSubRegIndices(); Idx < E; ++Idx) {
532  // Is this index even compatible with the given class?
533  if (getSubClassWithSubReg(RC, Idx) != RC)
534  continue;
535  LaneBitmask SubRegMask = getSubRegIndexLaneMask(Idx);
536  // Early exit if we found a perfect match.
537  if (SubRegMask == LaneMask) {
538  BestIdx = Idx;
539  break;
540  }
541 
542  // The index must not cover any lanes outside \p LaneMask.
543  if ((SubRegMask & ~LaneMask).any())
544  continue;
545 
546  unsigned PopCount = SubRegMask.getNumLanes();
547  PossibleIndexes.push_back(Idx);
548  if (PopCount > BestCover) {
549  BestCover = PopCount;
550  BestIdx = Idx;
551  }
552  }
553 
554  // Abort if we cannot possibly implement the COPY with the given indexes.
555  if (BestIdx == 0)
556  return false;
557 
558  NeededIndexes.push_back(BestIdx);
559 
560  // Greedy heuristic: Keep iterating keeping the best covering subreg index
561  // each time.
562  LaneBitmask LanesLeft = LaneMask & ~getSubRegIndexLaneMask(BestIdx);
563  while (LanesLeft.any()) {
564  unsigned BestIdx = 0;
565  int BestCover = std::numeric_limits<int>::min();
566  for (unsigned Idx : PossibleIndexes) {
567  LaneBitmask SubRegMask = getSubRegIndexLaneMask(Idx);
568  // Early exit if we found a perfect match.
569  if (SubRegMask == LanesLeft) {
570  BestIdx = Idx;
571  break;
572  }
573 
574  // Try to cover as much of the remaining lanes as possible but
575  // as few of the already covered lanes as possible.
576  int Cover = (SubRegMask & LanesLeft).getNumLanes() -
577  (SubRegMask & ~LanesLeft).getNumLanes();
578  if (Cover > BestCover) {
579  BestCover = Cover;
580  BestIdx = Idx;
581  }
582  }
583 
584  if (BestIdx == 0)
585  return false; // Impossible to handle
586 
587  NeededIndexes.push_back(BestIdx);
588 
589  LanesLeft &= ~getSubRegIndexLaneMask(BestIdx);
590  }
591 
592  return BestIdx;
593 }
594 
595 Register
597  const MachineRegisterInfo *MRI) const {
598  while (true) {
599  const MachineInstr *MI = MRI->getVRegDef(SrcReg);
600  if (!MI->isCopyLike())
601  return SrcReg;
602 
603  Register CopySrcReg;
604  if (MI->isCopy())
605  CopySrcReg = MI->getOperand(1).getReg();
606  else {
607  assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");
608  CopySrcReg = MI->getOperand(2).getReg();
609  }
610 
611  if (!CopySrcReg.isVirtual())
612  return CopySrcReg;
613 
614  SrcReg = CopySrcReg;
615  }
616 }
617 
619  Register SrcReg, const MachineRegisterInfo *MRI) const {
620  while (true) {
621  const MachineInstr *MI = MRI->getVRegDef(SrcReg);
622  // Found the real definition, return it if it has a single use.
623  if (!MI->isCopyLike())
624  return MRI->hasOneNonDBGUse(SrcReg) ? SrcReg : Register();
625 
626  Register CopySrcReg;
627  if (MI->isCopy())
628  CopySrcReg = MI->getOperand(1).getReg();
629  else {
630  assert(MI->isSubregToReg() && "Bad opcode for lookThruCopyLike");
631  CopySrcReg = MI->getOperand(2).getReg();
632  }
633 
634  // Continue only if the next definition in the chain is for a virtual
635  // register that has a single use.
636  if (!CopySrcReg.isVirtual() || !MRI->hasOneNonDBGUse(CopySrcReg))
637  return Register();
638 
639  SrcReg = CopySrcReg;
640  }
641 }
642 
644  const StackOffset &Offset, SmallVectorImpl<uint64_t> &Ops) const {
645  assert(!Offset.getScalable() && "Scalable offsets are not handled");
646  DIExpression::appendOffset(Ops, Offset.getFixed());
647 }
648 
649 DIExpression *
651  unsigned PrependFlags,
652  const StackOffset &Offset) const {
653  assert((PrependFlags &
656  "Unsupported prepend flag");
657  SmallVector<uint64_t, 16> OffsetExpr;
658  if (PrependFlags & DIExpression::DerefBefore)
659  OffsetExpr.push_back(dwarf::DW_OP_deref);
660  getOffsetOpcodes(Offset, OffsetExpr);
661  if (PrependFlags & DIExpression::DerefAfter)
662  OffsetExpr.push_back(dwarf::DW_OP_deref);
663  return DIExpression::prependOpcodes(Expr, OffsetExpr,
664  PrependFlags & DIExpression::StackValue,
665  PrependFlags & DIExpression::EntryValue);
666 }
667 
668 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
670 void TargetRegisterInfo::dumpReg(Register Reg, unsigned SubRegIndex,
671  const TargetRegisterInfo *TRI) {
672  dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n";
673 }
674 #endif
llvm::LaneBitmask
Definition: LaneBitmask.h:40
llvm::TargetRegisterInfo::getSubClassWithSubReg
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
Definition: TargetRegisterInfo.h:624
llvm::TargetRegisterInfo::shouldRegionSplitForVirtReg
virtual bool shouldRegionSplitForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Region split has a high compile time cost especially for large live range.
Definition: TargetRegisterInfo.cpp:69
llvm::TargetRegisterInfo::~TargetRegisterInfo
virtual ~TargetRegisterInfo()
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
LLVM_DUMP_METHOD
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:494
MathExtras.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::MCRegisterInfo::getName
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
Definition: MCRegisterInfo.h:485
TargetFrameLowering.h
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:43
llvm::MachineRegisterInfo::getVRegName
StringRef getVRegName(Register Reg) const
Definition: MachineRegisterInfo.h:436
llvm::printVRegOrUnit
Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
Definition: TargetRegisterInfo.cpp:165
DebugInfoMetadata.h
llvm::TargetRegisterClass::isAllocatable
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
Definition: TargetRegisterInfo.h:118
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
Printable.h
RegSize
unsigned RegSize
Definition: AArch64MIPeepholeOpt.cpp:121
llvm::Function
Definition: Function.h:60
llvm::TargetRegisterInfo::dumpReg
static void dumpReg(Register Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)
Debugging helper: dump register in human readable form to dbgs() stream.
Definition: TargetRegisterInfo.cpp:670
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:344
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:93
llvm::SmallVector< unsigned, 8 >
llvm::TargetRegisterInfo::getMinimalPhysRegClassLLT
const TargetRegisterClass * getMinimalPhysRegClassLLT(MCRegister Reg, LLT Ty=LLT()) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:230
llvm::SuperRegClassIterator::isValid
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Definition: TargetRegisterInfo.h:1160
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::LaneBitmask::getNumLanes
unsigned getNumLanes() const
Definition: LaneBitmask.h:76
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::TargetRegisterInfo::getAllocatableSet
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not.
Definition: TargetRegisterInfo.cpp:256
llvm::MachineRegisterInfo::getUniqueVRegDef
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
Definition: MachineRegisterInfo.cpp:407
llvm::TargetRegisterInfo::getOffsetOpcodes
virtual void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const
Gets the DWARF expression opcodes for Offset.
Definition: TargetRegisterInfo.cpp:643
llvm::TargetRegisterInfo::shouldRealignStack
virtual bool shouldRealignStack(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
Definition: TargetRegisterInfo.cpp:483
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::Register::stackSlot2Index
static int stackSlot2Index(Register Reg)
Compute the frame index from a register value representing a stack slot.
Definition: Register.h:52
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::TargetRegisterInfo::markSuperRegs
void markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const
Mark a register and all its aliases as reserved in the given set.
Definition: TargetRegisterInfo.cpp:80
TargetInstrInfo.h
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:136
llvm::LLT::isValid
bool isValid() const
Definition: LowLevelTypeImpl.h:116
getAllocatableSetForRC
static void getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R)
getAllocatableSetForRC - Toggle the bits that represent allocatable registers for the specific regist...
Definition: TargetRegisterInfo.cpp:248
llvm::TargetRegisterInfo::isCalleeSavedPhysReg
virtual bool isCalleeSavedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const
This is a wrapper around getCallPreservedMask().
Definition: TargetRegisterInfo.cpp:465
STLExtras.h
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2558
llvm::TargetRegisterInfo::RegClassInfo
Definition: TargetRegisterInfo.h:238
llvm::MCRegisterInfo::getNumRegUnits
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
Definition: MCRegisterInfo.h:505
RegisterSet
SmallSet< unsigned, 4 > RegisterSet
Definition: Thumb2ITBlockPass.cpp:39
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::MCRegisterInfo::getNumSubRegIndices
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
Definition: MCRegisterInfo.h:498
llvm::TargetRegisterClass::getSubClassMask
const uint32_t * getSubClassMask() const
Returns a bit vector of subclasses, including this one.
Definition: TargetRegisterInfo.h:159
llvm::LegalityPredicates::any
Predicate any(Predicate P0, Predicate P1)
True iff P0 or P1 are true.
Definition: LegalizerInfo.h:241
llvm::BitMaskClassIterator::isValid
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Definition: TargetRegisterInfo.h:1258
F
#define F(x, y, z)
Definition: MD5.cpp:55
MachineRegisterInfo.h
MachineValueType.h
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
CommandLine.h
llvm::Register::isPhysical
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:97
llvm::TargetRegisterInfo::canRealignStack
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
Definition: TargetRegisterInfo.cpp:479
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::TargetRegisterInfo::getSubRegIndexLaneMask
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
Definition: TargetRegisterInfo.h:378
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::TargetFrameLowering::getStackAlign
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:100
llvm::Register::isStackSlot
static bool isStackSlot(unsigned Reg)
isStackSlot - Sometimes it is useful the be able to store a non-negative frame index in a variable th...
Definition: Register.h:44
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:925
llvm::LLT::getSizeInBits
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelTypeImpl.h:152
llvm::TargetRegisterClass::getRawAllocationOrder
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
Definition: TargetRegisterInfo.h:200
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:54
BitVector.h
llvm::LiveRange::size
size_t size() const
Definition: LiveInterval.h:305
llvm::TargetRegisterInfo::getMatchingSuperRegClass
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
Definition: TargetRegisterInfo.cpp:303
llvm::BitVector
Definition: BitVector.h:75
llvm::LiveInterval
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:686
llvm::SuperRegClassIterator
Definition: TargetRegisterInfo.h:1141
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:396
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::printRegUnit
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
Definition: TargetRegisterInfo.cpp:142
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:642
llvm::TargetRegisterInfo::regclasses
iterator_range< regclass_iterator > regclasses() const
Definition: TargetRegisterInfo.h:740
llvm::TargetRegisterInfo::regmaskSubsetEqual
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
Definition: TargetRegisterInfo.cpp:492
llvm::Register::isVirtual
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:625
llvm::cl::opt
Definition: CommandLine.h:1392
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:750
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:238
llvm::DIExpression::StackValue
@ StackValue
Definition: DebugInfoMetadata.h:2766
VirtRegMap.h
llvm::TargetRegisterInfo::getRegClassName
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Definition: TargetRegisterInfo.h:756
llvm::TargetRegisterInfo::getCommonSuperRegClass
const TargetRegisterClass * getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const
Find a common super-register class if it exists.
Definition: TargetRegisterInfo.cpp:319
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
llvm::VirtRegMap::getPhys
MCRegister getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
Definition: VirtRegMap.h:105
llvm::TargetRegisterInfo::getRegAllocationHints
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
Definition: TargetRegisterInfo.cpp:422
llvm::LaneBitmask::any
constexpr bool any() const
Definition: LaneBitmask.h:53
StringExtras.h
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
MCRegisterInfo.h
llvm::StringRef::lower
LLVM_NODISCARD std::string lower() const
Definition: StringRef.cpp:112
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1682
ArrayRef.h
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
llvm::MachineRegisterInfo::getRegClassOrNull
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
Definition: MachineRegisterInfo.h:659
llvm::DIExpression::DerefBefore
@ DerefBefore
Definition: DebugInfoMetadata.h:2764
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:853
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:672
llvm::TargetRegisterInfo::getCommonSubClass
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
Definition: TargetRegisterInfo.cpp:289
llvm::MCSuperRegIterator
MCSuperRegIterator enumerates all super-registers of Reg.
Definition: MCRegisterInfo.h:644
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::printRegClassOrBank
Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
Definition: TargetRegisterInfo.cpp:175
llvm::TargetRegisterInfo::TargetRegisterInfo
TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RCB, regclass_iterator RCE, const char *const *SRINames, const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes, const RegClassInfo *const RCIs, unsigned Mode=0)
Definition: TargetRegisterInfo.cpp:53
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::countTrailingZeros
unsigned countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition: MathExtras.h:156
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
Dwarf.h
llvm::MachineRegisterInfo::hasOneNonDBGUse
bool hasOneNonDBGUse(Register RegNo) const
hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.
Definition: MachineRegisterInfo.cpp:415
llvm::TargetRegisterInfo::composeSubRegIndices
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
Definition: TargetRegisterInfo.h:642
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::TargetRegisterInfo::getCoveringSubRegIndexes
bool getCoveringSubRegIndexes(const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, LaneBitmask LaneMask, SmallVectorImpl< unsigned > &Indexes) const
Try to find one or more subregister indexes to cover LaneMask.
Definition: TargetRegisterInfo.cpp:524
if
if(llvm_vc STREQUAL "") set(fake_version_inc "$
Definition: CMakeLists.txt:14
llvm::TargetRegisterInfo::isTypeLegalForClass
bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const
Return true if the given TargetRegisterClass has the ValueType T.
Definition: TargetRegisterInfo.h:294
uint32_t
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
Compiler.h
TargetSubtargetInfo.h
llvm::SmallSet::insert
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:182
llvm::MachineRegisterInfo::getRegAllocationHints
const std::pair< Register, SmallVector< Register, 4 > > & getRegAllocationHints(Register VReg) const
getRegAllocationHints - Return a reference to the vector of all register allocation hints for VReg.
Definition: MachineRegisterInfo.h:822
llvm::MachineRegisterInfo::getReservedRegs
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
Definition: MachineRegisterInfo.h:914
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MachineFrameInfo::getMaxAlign
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Definition: MachineFrameInfo.h:593
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::TargetRegisterInfo::lookThruSingleUseCopyChain
virtual Register lookThruSingleUseCopyChain(Register SrcReg, const MachineRegisterInfo *MRI) const
Find the original SrcReg unless it is the target of a copy-like operation, in which case we chain bac...
Definition: TargetRegisterInfo.cpp:618
Attributes.h
llvm::TargetRegisterInfo::shouldRewriteCopySrc
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
Definition: TargetRegisterInfo.cpp:413
llvm::DIExpression::appendOffset
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
Definition: DebugInfoMetadata.cpp:1383
llvm::DIExpression::prependOpcodes
static DIExpression * prependOpcodes(const DIExpression *Expr, SmallVectorImpl< uint64_t > &Ops, bool StackValue=false, bool EntryValue=false)
Prepend DIExpr with the given opcodes and optionally turn it into a stack value.
Definition: DebugInfoMetadata.cpp:1513
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
llvm::TargetRegisterInfo::lookThruCopyLike
virtual Register lookThruCopyLike(Register SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
Definition: TargetRegisterInfo.cpp:596
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:622
llvm::TargetSubtargetInfo::getFrameLowering
virtual const TargetFrameLowering * getFrameLowering() const
Definition: TargetSubtargetInfo.h:94
llvm::DIExpression::DerefAfter
@ DerefAfter
Definition: DebugInfoMetadata.h:2765
llvm::TargetRegisterInfo::getRegSizeInBits
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Definition: TargetRegisterInfo.h:277
MachineFrameInfo.h
firstCommonClass
static const TargetRegisterClass * firstCommonClass(const uint32_t *A, const uint32_t *B, const TargetRegisterInfo *TRI)
Definition: TargetRegisterInfo.cpp:279
llvm::RegisterBank::getName
const char * getName() const
Get a user friendly name of this register bank.
Definition: RegisterBank.h:51
shareSameRegisterFile
static bool shareSameRegisterFile(const TargetRegisterInfo &TRI, const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg)
Check if the registers defined by the pair (RegisterClass, SubReg) share the same register file.
Definition: TargetRegisterInfo.cpp:382
Function.h
llvm::MachineRegisterInfo::getRegBankOrNull
const RegisterBank * getRegBankOrNull(Register Reg) const
Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...
Definition: MachineRegisterInfo.h:668
llvm::TargetRegisterInfo::getNumRegClasses
unsigned getNumRegClasses() const
Definition: TargetRegisterInfo.h:744
llvm::TargetRegisterInfo::regclass_iterator
const TargetRegisterClass *const * regclass_iterator
Definition: TargetRegisterInfo.h:236
llvm::BitVector::reset
BitVector & reset()
Definition: BitVector.h:385
LiveInterval.h
llvm::MCRegUnitRootIterator
MCRegUnitRootIterator enumerates the root registers of a register unit.
Definition: MCRegisterInfo.h:754
llvm::TargetRegisterClass::hasSubClass
bool hasSubClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
Definition: TargetRegisterInfo.h:122
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:740
llvm::Printable
Simple wrapper around std::function<void(raw_ostream&)>.
Definition: Printable.h:38
N
#define N
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::LiveInterval::reg
Register reg() const
Definition: LiveInterval.h:717
llvm::TargetRegisterInfoDesc
Extra information, not in MCRegisterDesc, about registers.
Definition: TargetRegisterInfo.h:214
llvm::TargetRegisterInfo::getAllocatableClass
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
Definition: TargetRegisterInfo.cpp:195
llvm::SmallVectorImpl< MCPhysReg >
llvm::BitMaskClassIterator
This class encapuslates the logic to iterate over bitmask returned by the various RegClass related AP...
Definition: TargetRegisterInfo.h:1187
HugeSizeForSplit
static cl::opt< unsigned > HugeSizeForSplit("huge-size-for-split", cl::Hidden, cl::desc("A threshold of live range size which may cause " "high compile time cost in global splitting."), cl::init(5000))
llvm::TargetRegisterInfo::checkAllSuperRegsMarked
bool checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const
Returns true if for every register in the set all super registers are part of the set as well.
Definition: TargetRegisterInfo.cpp:86
llvm::Register::virtReg2Index
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
Definition: Register.h:77
llvm::cl::desc
Definition: CommandLine.h:405
llvm::TargetRegisterInfo::getMinimalPhysRegClass
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Definition: TargetRegisterInfo.cpp:212
llvm::TargetRegisterInfo::getSubRegIndexName
const char * getSubRegIndexName(unsigned SubIdx) const
Return the human-readable symbolic target-specific name for the specified SubRegIndex.
Definition: TargetRegisterInfo.h:368
raw_ostream.h
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:111
TargetRegisterInfo.h
Debug.h
llvm::DIExpression::EntryValue
@ EntryValue
Definition: DebugInfoMetadata.h:2767
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:480
llvm::TargetRegisterInfo::prependOffsetExpression
DIExpression * prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags, const StackOffset &Offset) const
Prepends a DWARF expression for Offset to DIExpression Expr.
Definition: TargetRegisterInfo.cpp:650
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
SmallSet.h
llvm::LiveRegMatrix
Definition: LiveRegMatrix.h:40
llvm::LLT
Definition: LowLevelTypeImpl.h:39