29#include "llvm/Config/llvm-config.h"
42#define DEBUG_TYPE "target-reg-info"
48 cl::desc(
"A threshold of live range size which may cause "
49 "high compile time cost in global splitting."),
58 : InfoDesc(
ID), SubRegIndexNames(SRINames), SubRegIdxRanges(SubIdxRanges),
59 SubRegIndexLaneMasks(SRILaneMasks), RegClassBegin(RCB), RegClassEnd(RCE),
60 CoveringLanes(SRICoveringLanes), RCInfos(RCIs), RCVTLists(RCVTLists),
70 if (
MI &&
TII->isTriviallyReMaterializable(*
MI) &&
86 for (
unsigned Reg : RegisterSet.set_bits()) {
90 if (!RegisterSet[SR] && !
is_contained(Exceptions, Reg)) {
92 <<
" of reserved register " <<
printReg(Reg,
this)
93 <<
" is not reserved.\n";
110 else if (Reg.isStack())
111 OS <<
"SS#" << Reg.stackSlotIndex();
112 else if (Reg.isVirtual()) {
117 OS <<
'%' << Reg.virtRegIndex();
120 OS <<
'$' <<
"physreg" << Reg.id();
129 OS <<
':' <<
TRI->getSubRegIndexName(SubIdx);
131 OS <<
":sub(" << SubIdx <<
')';
140 OS <<
"Unit~" << Unit;
145 if (Unit >=
TRI->getNumRegUnits()) {
146 OS <<
"BadUnit~" << Unit;
153 OS <<
TRI->getName(*Roots);
154 for (++Roots; Roots.
isValid(); ++Roots)
155 OS <<
'~' <<
TRI->getName(*Roots);
162 OS <<
'%' <<
Register(Unit).virtRegIndex();
173 if (RegInfo.getRegClassOrNull(Reg))
175 else if (RegInfo.getRegBankOrNull(Reg))
176 OS <<
StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).
lower();
179 assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) &&
180 "Generic registers must have a valid type");
201template <
typename TypeT>
205 static_assert(std::is_same_v<TypeT, MVT> || std::is_same_v<TypeT, LLT>);
206 assert(
Reg.isPhysical() &&
"reg must be a physical register");
208 bool IsDefault = [&]() {
209 if constexpr (std::is_same_v<TypeT, MVT>)
210 return Ty == MVT::Other;
212 return !Ty.isValid();
219 if ((IsDefault ||
TRI->isTypeLegalForClass(*RC, Ty)) && RC->contains(
Reg) &&
224 if constexpr (std::is_same_v<TypeT, MVT>)
225 assert(BestRC &&
"Couldn't find the register class");
229template <
typename TypeT>
233 static_assert(std::is_same_v<TypeT, MVT> || std::is_same_v<TypeT, LLT>);
235 "Reg1/Reg2 must be a physical register");
237 bool IsDefault = [&]() {
238 if constexpr (std::is_same_v<TypeT, MVT>)
239 return Ty == MVT::Other;
241 return !Ty.isValid();
248 if ((IsDefault ||
TRI->isTypeLegalForClass(*RC, Ty)) &&
249 RC->contains(Reg1, Reg2) && (!BestRC || BestRC->
hasSubClass(RC)))
253 if constexpr (std::is_same_v<TypeT, MVT>)
254 assert(BestRC &&
"Couldn't find the register class");
260 return ::getMinimalPhysRegClass(
this, Reg, VT);
265 return ::getCommonMinimalPhysRegClass(
this, Reg1, Reg2, VT);
270 return ::getMinimalPhysRegClass(
this, Reg, Ty);
275 return ::getCommonMinimalPhysRegClass(
this, Reg1, Reg2, Ty);
298 if (
C->isAllocatable())
314 for (
unsigned I = 0,
E =
TRI->getNumRegClasses();
I <
E;
I += 32)
315 if (
unsigned Common = *
A++ & *
B++)
337 unsigned Idx)
const {
338 assert(
A &&
B &&
"Missing register class");
339 assert(Idx &&
"Bad sub-register index");
343 if (RCI.getSubReg() == Idx)
353 unsigned &PreA,
unsigned &PreB)
const {
354 assert(RCA && SubA && RCB && SubB &&
"Invalid arguments");
369 unsigned *BestPreA = &PreA;
370 unsigned *BestPreB = &PreB;
392 if (FinalA != FinalB)
401 *BestPreA = IA.getSubReg();
402 *BestPreB = IB.getSubReg();
419 if (DefRC == SrcRC && DefSubReg == SrcSubReg)
423 unsigned SrcIdx, DefIdx;
424 if (SrcSubReg && DefSubReg) {
455 const std::pair<unsigned, SmallVector<Register, 4>> *Hints_MRI =
456 MRI.getRegAllocationHints(VirtReg);
463 bool Skip = (Hints_MRI->first != 0);
464 for (
auto Reg : Hints_MRI->second) {
477 if (!HintedRegs.
insert(Phys).second)
482 if (
MRI.isReserved(Phys))
500 const uint32_t *callerPreservedRegs =
502 if (callerPreservedRegs) {
504 return (callerPreservedRegs[PhysReg.
id() / 32] >> PhysReg.
id() % 32) & 1;
520 for (
unsigned I = 0;
I <
N; ++
I)
521 if ((mask0[
I] & mask1[
I]) != mask0[
I])
530 if (Reg.isPhysical()) {
535 assert(RC &&
"Unable to deduce the register class");
538 LLT Ty =
MRI.getType(Reg);
540 return Ty.getSizeInBits();
543 RC =
MRI.getRegClass(Reg);
544 assert(RC &&
"Unable to deduce the register class");
552 unsigned BestIdx = 0;
553 unsigned BestCover = 0;
561 if (SubRegMask == LaneMask) {
567 if ((SubRegMask & ~LaneMask).any())
572 if (PopCount > BestCover) {
573 BestCover = PopCount;
587 while (LanesLeft.
any()) {
588 unsigned BestIdx = 0;
589 int BestCover = std::numeric_limits<int>::min();
590 for (
unsigned Idx : PossibleIndexes) {
593 if (SubRegMask == LanesLeft) {
601 if ((SubRegMask & ~LanesLeft).any())
605 const int Cover = (SubRegMask & LanesLeft).getNumLanes();
606 if (Cover > BestCover) {
625 "This is not a subregister index");
631 "This is not a subregister index");
640 if (!
MI->isCopyLike())
645 CopySrcReg =
MI->getOperand(1).getReg();
647 assert(
MI->isSubregToReg() &&
"Bad opcode for lookThruCopyLike");
648 CopySrcReg =
MI->getOperand(2).getReg();
663 if (!
MI->isCopyLike())
664 return MRI->hasOneNonDBGUse(SrcReg) ? SrcReg :
Register();
668 CopySrcReg =
MI->getOperand(1).getReg();
670 assert(
MI->isSubregToReg() &&
"Bad opcode for lookThruCopyLike");
671 CopySrcReg =
MI->getOperand(2).getReg();
676 if (!CopySrcReg.
isVirtual() || !
MRI->hasOneNonDBGUse(CopySrcReg))
685 assert(!
Offset.getScalable() &&
"Scalable offsets are not handled");
691 unsigned PrependFlags,
696 "Unsupported prepend flag");
699 OffsetExpr.
push_back(dwarf::DW_OP_deref);
702 OffsetExpr.
push_back(dwarf::DW_OP_deref);
708#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
unsigned const MachineRegisterInfo * MRI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
This file contains the simple types necessary to represent the attributes associated with functions a...
This file implements the BitVector class.
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
This file contains constants used for implementing Dwarf debug support.
const HexagonInstrInfo * TII
const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]
Register const TargetRegisterInfo * TRI
Promote Memory to Register
This file defines the SmallSet class.
static const TargetRegisterClass * getMinimalPhysRegClass(const TargetRegisterInfo *TRI, MCRegister Reg, TypeT Ty)
static void getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R)
getAllocatableSetForRC - Toggle the bits that represent allocatable registers for the specific regist...
static const TargetRegisterClass * firstCommonClass(const uint32_t *A, const uint32_t *B, const TargetRegisterInfo *TRI)
static const TargetRegisterClass * getCommonMinimalPhysRegClass(const TargetRegisterInfo *TRI, MCRegister Reg1, MCRegister Reg2, TypeT Ty)
static cl::opt< unsigned > HugeSizeForSplit("huge-size-for-split", cl::Hidden, cl::desc("A threshold of live range size which may cause " "high compile time cost in global splitting."), cl::init(5000))
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
This class encapuslates the logic to iterate over bitmask returned by the various RegClass related AP...
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
static LLVM_ABI void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
static LLVM_ABI DIExpression * prependOpcodes(const DIExpression *Expr, SmallVectorImpl< uint64_t > &Ops, bool StackValue=false, bool EntryValue=false)
Prepend DIExpr with the given opcodes and optionally turn it into a stack value.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
LiveInterval - This class represents the liveness of a register, or stack slot.
MCRegUnitRootIterator enumerates the root registers of a register unit.
bool isValid() const
Check if the iterator is at the end of the list.
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
iterator_range< MCSuperRegIterator > superregs(MCRegister Reg) const
Return an iterator range over all super-registers of Reg, excluding Reg.
iterator_range< MCSuperRegIterator > superregs_inclusive(MCRegister Reg) const
Return an iterator range over all super-registers of Reg, including Reg.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Wrapper class representing physical registers. Should be passed by value.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
constexpr unsigned id() const
bool shouldRealignStack() const
Return true if stack realignment is forced by function attributes or if the stack alignment.
bool isStackRealignable() const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Simple wrapper around std::function<void(raw_ostream&)>.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
static constexpr bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
constexpr unsigned id() const
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StackOffset holds a fixed and a scalable offset in bytes.
StringRef - Represent a constant reference to a string, i.e.
LLVM_ABI std::string lower() const
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
TargetInstrInfo - Interface to description of machine instruction set.
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF, bool Rev=false) const
Returns the preferred order for allocating registers from this register class in MF.
bool isAllocatable() const
Return true if this register class may be used to create virtual registers.
bool hasSubClass(const TargetRegisterClass *RC) const
Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
const uint32_t * getSubClassMask() const
Returns a bit vector of subclasses, including this one.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const TargetRegisterClass *const * regclass_iterator
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
iterator_range< regclass_iterator > regclasses() const
virtual bool shouldRegionSplitForVirtReg(const MachineFunction &MF, const LiveInterval &VirtReg) const
Region split has a high compile time cost especially for large live range.
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const
Returns the largest legal sub-class of RC that supports the sub-register index Idx.
bool getCoveringSubRegIndexes(const TargetRegisterClass *RC, LaneBitmask LaneMask, SmallVectorImpl< unsigned > &Indexes) const
Try to find one or more subregister indexes to cover LaneMask.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
unsigned composeSubRegIndices(unsigned a, unsigned b) const
Return the subregister index you get from composing two subregister indices.
const TargetRegisterClass * getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B) const
Find the largest common subclass of A and B.
const TargetRegisterClass * getMinimalPhysRegClassLLT(MCRegister Reg, LLT Ty=LLT()) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
void markSuperRegs(BitVector &RegisterSet, MCRegister Reg) const
Mark a register and all its aliases as reserved in the given set.
virtual float getSpillWeightScaleFactor(const TargetRegisterClass *RC) const
Get the scale factor of spill weight for this register class.
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
TypeSize getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
virtual Register lookThruSingleUseCopyChain(Register SrcReg, const MachineRegisterInfo *MRI) const
Find the original SrcReg unless it is the target of a copy-like operation, in which case we chain bac...
virtual ~TargetRegisterInfo()
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
bool checkAllSuperRegsMarked(const BitVector &RegisterSet, ArrayRef< MCPhysReg > Exceptions=ArrayRef< MCPhysReg >()) const
Returns true if for every register in the set all super registers are part of the set as well.
const TargetRegisterClass * getAllocatableClass(const TargetRegisterClass *RC) const
Return the maximal subclass of the given register class that is allocatable or NULL.
virtual Register lookThruCopyLike(Register SrcReg, const MachineRegisterInfo *MRI) const
Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain ...
const TargetRegisterClass * getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, const TargetRegisterClass *RCB, unsigned SubB, unsigned &PreA, unsigned &PreB) const
Find a common super-register class if it exists.
unsigned getSubRegIdxSize(unsigned Idx) const
Get the size of the bit range covered by a sub-register index.
static void dumpReg(Register Reg, unsigned SubRegIndex=0, const TargetRegisterInfo *TRI=nullptr)
Debugging helper: dump register in human readable form to dbgs() stream.
virtual bool shouldRealignStack(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RCB, regclass_iterator RCE, const char *const *SRINames, const SubRegCoveredBits *SubIdxRanges, const LaneBitmask *SRILaneMasks, LaneBitmask CoveringLanes, const RegClassInfo *const RCIs, const MVT::SimpleValueType *const RCVTLists, unsigned Mode=0)
DIExpression * prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags, const StackOffset &Offset) const
Prepends a DWARF expression for Offset to DIExpression Expr.
const TargetRegisterClass * findCommonRegClass(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
Find a common register class that can accomodate both the source and destination operands of a copy-l...
const TargetRegisterClass * getCommonMinimalPhysRegClass(MCRegister Reg1, MCRegister Reg2, MVT VT=MVT::Other) const
Returns the common Register Class of two physical registers of the given type, picking the most sub r...
virtual bool isCalleeSavedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const
This is a wrapper around getCallPreservedMask().
unsigned getSubRegIdxOffset(unsigned Idx) const
Get the offset of the bit range covered by a sub-register index.
virtual const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const
Return a subclass of the specified register class A so that each register in it has a sub-register of...
virtual void getOffsetOpcodes(const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const
Gets the DWARF expression opcodes for Offset.
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not.
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
const TargetRegisterClass * getCommonMinimalPhysRegClassLLT(MCRegister Reg1, MCRegister Reg2, LLT Ty=LLT()) const
Returns the common Register Class of two physical registers of the given type, picking the most sub r...
virtual const TargetInstrInfo * getInstrInfo() const
MCRegister getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ C
The default llvm calling convention, compatible with C.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
LLVM_ABI void printLowerCase(StringRef String, raw_ostream &Out)
printLowerCase - Print each character as lowercase if it is uppercase.
LLVM_ABI Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
LLVM_ABI Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
LLVM_ABI Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI)
Create Printable object to print register classes or register banks on a raw_ostream.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
constexpr bool any() const
unsigned getNumLanes() const
Extra information, not in MCRegisterDesc, about registers.
SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg index, -1 in any being invalid...