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33 #define DEBUG_TYPE "regalloc"
35 STATISTIC(NumAssigned ,
"Number of registers assigned");
36 STATISTIC(NumUnassigned ,
"Number of registers unassigned");
40 "Live Register Matrix",
false,
false)
48 void LiveRegMatrix::getAnalysisUsage(
AnalysisUsage &AU)
const {
57 LIS = &getAnalysis<LiveIntervals>();
58 VRM = &getAnalysis<VirtRegMap>();
61 if (NumRegUnits != Matrix.
size())
63 Matrix.
init(LIUAlloc, NumRegUnits);
70 void LiveRegMatrix::releaseMemory() {
71 for (
unsigned i = 0,
e = Matrix.
size();
i !=
e; ++
i) {
79 template <
typename Callable>
85 unsigned Unit = (*Units).first;
88 if ((
S.LaneMask &
Mask).any()) {
97 if (Func(*Units, VRegInterval))
111 TRI, VirtReg, PhysReg, [&](
unsigned Unit,
const LiveRange &Range) {
113 Matrix[Unit].unify(VirtReg, Range);
124 <<
" from " <<
printReg(PhysReg, TRI) <<
':');
128 [&](
unsigned Unit,
const LiveRange &Range) {
130 Matrix[Unit].extract(VirtReg, Range);
140 if (!Matrix[*Unit].empty())
151 if (RegMaskVirtReg != VirtReg.
reg() || RegMaskTag != UserTag) {
152 RegMaskVirtReg = VirtReg.
reg();
153 RegMaskTag = UserTag;
154 RegMaskUsable.
clear();
161 return !RegMaskUsable.
empty() && (!PhysReg || !RegMaskUsable.
test(PhysReg));
170 bool Result =
foreachUnit(TRI, VirtReg, PhysReg, [&](
unsigned Unit,
181 Q.
init(UserTag, LR, Matrix[RegUnit]);
200 bool Interference =
foreachUnit(TRI, VirtReg, PhysReg,
233 Q.
reset(UserTag, LR, Matrix[*Units]);
243 if ((VRegInterval = Matrix[*Unit].
getOneVReg()))
244 return VRegInterval->
reg();
This is an optimization pass for GlobalISel generic memory operations.
SlotIndexes * getSlotIndexes() const
bool isValid() const
Returns true if this iterator is not yet at the end.
void invalidateVirtRegs()
Invalidate cached interference queries after modifying virtual register live ranges.
void clear()
clear - Removes all bits from the bitvector.
void reset(unsigned NewUserTag, const LiveRange &NewLR, const LiveIntervalUnion &NewLiveUnion)
void unassign(const LiveInterval &VirtReg)
Unassign VirtReg from its PhysReg.
This represents a simple continuous liveness interval for a value.
void assignVirt2Phys(Register virtReg, MCPhysReg physReg)
creates a mapping for the specified virtual register to the specified physical register
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void init(unsigned NewUserTag, const LiveRange &NewLR, const LiveIntervalUnion &NewLiveUnion)
static constexpr unsigned NoRegister
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
unsigned const TargetRegisterInfo * TRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Register getOneVReg(unsigned PhysReg) const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
INITIALIZE_PASS_BEGIN(LiveRegMatrix, "liveregmatrix", "Live Register Matrix", false, false) INITIALIZE_PASS_END(LiveRegMatrix
@ IK_RegUnit
Register unit interference.
@ IK_Free
No interference, go ahead and assign.
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
Represent the analysis usage information of a pass.
STATISTIC(NumFunctions, "Total number of functions")
bool isPhysRegUsed(MCRegister PhysReg) const
Returns true if the given PhysReg has any live intervals assigned.
LiveInterval - This class represents the liveness of a register, or stack slot.
SlotIndex - An opaque wrapper around machine indexes.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
bool empty() const
empty - Tests whether there are no bits in this bitvector.
bool hasPhys(Register virtReg) const
returns true if the specified virtual register is mapped to a physical register
LiveIntervalUnion::Query & query(const LiveRange &LR, MCRegister RegUnit)
Query a line of the assigned virtual register matrix directly.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
This class represents the liveness of a register, stack slot, etc.
bool checkRegMaskInterference(const LiveInterval &VirtReg, MCRegister PhysReg=MCRegister::NoRegister)
Check for regmask interference only.
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
MCRegUnitMaskIterator enumerates a list of register units and their associated lane masks for Reg.
MCRegister getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool checkRegUnitInterference(const LiveInterval &VirtReg, MCRegister PhysReg)
Check for regunit interference only.
bool checkRegMaskInterference(const LiveInterval &LI, BitVector &UsableRegs)
Test if LI is live across any register mask instructions, and compute a bit mask of physical register...
void init(LiveIntervalUnion::Allocator &, unsigned Size)
@ IK_VirtReg
Virtual register interference.
InterferenceKind checkInterference(const LiveInterval &VirtReg, MCRegister PhysReg)
Check for interference before assigning VirtReg to PhysReg.
A helper class for register coalescers.
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
A live range for subregisters.
Wrapper class representing virtual and physical registers.
bool test(unsigned Idx) const
void setPreservesAll()
Set by analyses that do not transform their input at all.
@ IK_RegMask
RegMask interference.
void clearVirt(Register virtReg)
clears the specified virtual register's, physical register mapping
VNInfo - Value Number Information.
static bool foreachUnit(const TargetRegisterInfo *TRI, const LiveInterval &VRegInterval, MCRegister PhysReg, Callable Func)
Query interferences between a single live virtual register and a live interval union.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
bool hasSubRanges() const
Returns true if subregister liveness information is available.
AnalysisUsage & addRequiredTransitive()
void assign(const LiveInterval &VirtReg, MCRegister PhysReg)
Assign VirtReg to PhysReg.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
LiveRange & getRegUnit(unsigned Unit)
Return the live range for register unit Unit.
Wrapper class representing physical registers. Should be passed by value.
iterator_range< subrange_iterator > subranges()