16#ifndef LLVM_CODEGEN_LIVEINTERVALUNION_H
17#define LLVM_CODEGEN_LIVEINTERVALUNION_H
29class TargetRegisterInfo;
33template <
unsigned Element>
class SparseBitVector;
76 bool empty()
const {
return Segments.empty(); }
118 bool CheckedFirstInterference =
false;
119 bool SeenAllInterferences =
false;
121 unsigned UserTag = 0;
125 unsigned collectInterferingVRegs(
unsigned MaxInterferingRegs);
128 bool isSeenInterference(
const LiveInterval *VirtReg)
const;
133 : LiveUnion(&LIU), LR(&LR) {}
139 LiveUnion = &NewLiveUnion;
141 InterferingVRegs.
clear();
142 CheckedFirstInterference =
false;
143 SeenAllInterferences =
false;
145 UserTag = NewUserTag;
150 if (UserTag == NewUserTag && LR == &NewLR && LiveUnion == &NewLiveUnion &&
155 reset(NewUserTag, NewLR, NewLiveUnion);
163 unsigned MaxInterferingRegs = std::numeric_limits<unsigned>::max()) {
164 if (!SeenAllInterferences || MaxInterferingRegs < InterferingVRegs.
size())
165 collectInterferingVRegs(MaxInterferingRegs);
166 return InterferingVRegs;
183 unsigned size()
const {
return Size; }
188 assert(idx < Size &&
"idx out of bounds");
193 assert(
Idx < Size &&
"Idx out of bounds");
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file implements a coalescing interval map for small objects.
unsigned const TargetRegisterInfo * TRI
ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
typename Sizer::Allocator Allocator
friend class const_iterator
void init(LiveIntervalUnion::Allocator &, unsigned Size)
LiveIntervalUnion & operator[](unsigned idx)
const LiveIntervalUnion & operator[](unsigned Idx) const
Query interferences between a single live virtual register and a live interval union.
Query & operator=(const Query &)=delete
Query(const LiveRange &LR, const LiveIntervalUnion &LIU)
void init(unsigned NewUserTag, const LiveRange &NewLR, const LiveIntervalUnion &NewLiveUnion)
const SmallVectorImpl< const LiveInterval * > & interferingVRegs(unsigned MaxInterferingRegs=std::numeric_limits< unsigned >::max())
void reset(unsigned NewUserTag, const LiveRange &NewLR, const LiveIntervalUnion &NewLiveUnion)
Query(const Query &)=delete
Union of live intervals that are strong candidates for coalescing into a single register (either phys...
SlotIndex startIndex() const
LiveSegments::const_iterator ConstSegmentIter
Const version of SegmentIter.
LiveIntervalUnion(Allocator &a)
SegmentIter find(SlotIndex x)
void unify(const LiveInterval &VirtReg, const LiveRange &Range)
ConstSegmentIter begin() const
const LiveInterval * getOneVReg() const
NDEBUG.
LiveSegments::iterator SegmentIter
unsigned getTag() const
getTag - Return an opaque tag representing the current state of the union.
ConstSegmentIter find(SlotIndex x) const
bool changedSince(unsigned tag) const
changedSince - Return true if the union change since getTag returned tag.
void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const
SlotIndex endIndex() const
const Map & getMap() const
LiveSegments::Allocator Allocator
ConstSegmentIter end() const
LiveInterval - This class represents the liveness of a register, or stack slot.
This class represents the liveness of a register, stack slot, etc.
SlotIndex - An opaque wrapper around machine indexes.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This class implements an extremely fast bulk output stream that can only output to a stream.
This is an optimization pass for GlobalISel generic memory operations.