LLVM 17.0.0git
PPCCTRLoopsVerify.cpp
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1//===-- PPCCTRLoops.cpp - Verify CTR loops -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This pass verifies that all bdnz/bdz instructions are dominated by a loop
10// mtctr before any other instructions that might clobber the ctr register.
11//
12//===----------------------------------------------------------------------===//
13
14// CTR loops are produced by the HardwareLoops pass and this pass is simply a
15// verification that no invalid CTR loops are produced. As such, it isn't
16// something that needs to be run (or even defined) for Release builds so the
17// entire file is guarded by NDEBUG.
18#ifndef NDEBUG
19#include <vector>
20
22#include "PPC.h"
23#include "llvm/ADT/SmallSet.h"
25#include "llvm/ADT/StringRef.h"
36#include "llvm/Pass.h"
37#include "llvm/PassRegistry.h"
39#include "llvm/Support/Debug.h"
44
45using namespace llvm;
46
47#define DEBUG_TYPE "ppc-ctrloops-verify"
48
49namespace {
50
51 struct PPCCTRLoopsVerify : public MachineFunctionPass {
52 public:
53 static char ID;
54
55 PPCCTRLoopsVerify() : MachineFunctionPass(ID) {
57 }
58
59 void getAnalysisUsage(AnalysisUsage &AU) const override {
62 }
63
64 bool runOnMachineFunction(MachineFunction &MF) override;
65
66 private:
68 };
69
70 char PPCCTRLoopsVerify::ID = 0;
71} // end anonymous namespace
72
73INITIALIZE_PASS_BEGIN(PPCCTRLoopsVerify, "ppc-ctr-loops-verify",
74 "PowerPC CTR Loops Verify", false, false)
76INITIALIZE_PASS_END(PPCCTRLoopsVerify, "ppc-ctr-loops-verify",
77 "PowerPC CTR Loops Verify", false, false)
78
80 return new PPCCTRLoopsVerify();
81}
82
83static bool clobbersCTR(const MachineInstr &MI) {
84 for (const MachineOperand &MO : MI.operands()) {
85 if (MO.isReg()) {
86 if (MO.isDef() && (MO.getReg() == PPC::CTR || MO.getReg() == PPC::CTR8))
87 return true;
88 } else if (MO.isRegMask()) {
89 if (MO.clobbersPhysReg(PPC::CTR) || MO.clobbersPhysReg(PPC::CTR8))
90 return true;
91 }
92 }
93
94 return false;
95}
96
102 bool CheckPreds;
103
104 if (I == MBB->begin()) {
105 Visited.insert(MBB);
106 goto queue_preds;
107 } else
108 --I;
109
110check_block:
111 Visited.insert(MBB);
112 if (I == MBB->end())
113 goto queue_preds;
114
115 CheckPreds = true;
116 for (MachineBasicBlock::iterator IE = MBB->begin();; --I) {
117 unsigned Opc = I->getOpcode();
118 if (Opc == PPC::MTCTRloop || Opc == PPC::MTCTR8loop) {
119 CheckPreds = false;
120 break;
121 }
122
123 if (I != BI && clobbersCTR(*I)) {
125 << ") instruction " << *I
126 << " clobbers CTR, invalidating "
127 << printMBBReference(*BI->getParent()) << " ("
128 << BI->getParent()->getFullName() << ") instruction "
129 << *BI << "\n");
130 return false;
131 }
132
133 if (I == IE)
134 break;
135 }
136
137 if (!CheckPreds && Preds.empty())
138 return true;
139
140 if (CheckPreds) {
141queue_preds:
143 LLVM_DEBUG(dbgs() << "Unable to find a MTCTR instruction for "
144 << printMBBReference(*BI->getParent()) << " ("
145 << BI->getParent()->getFullName() << ") instruction "
146 << *BI << "\n");
147 return false;
148 }
149
150 append_range(Preds, MBB->predecessors());
151 }
152
153 do {
154 MBB = Preds.pop_back_val();
155 if (!Visited.count(MBB)) {
157 goto check_block;
158 }
159 } while (!Preds.empty());
160
161 return true;
162}
163
164bool PPCCTRLoopsVerify::runOnMachineFunction(MachineFunction &MF) {
165 MDT = &getAnalysis<MachineDominatorTree>();
166
167 // Verify that all bdnz/bdz instructions are dominated by a loop mtctr before
168 // any other instructions that might clobber the ctr register.
169 for (MachineBasicBlock &MBB : MF) {
170 if (!MDT->isReachableFromEntry(&MBB))
171 continue;
172
174 MIIE = MBB.end(); MII != MIIE; ++MII) {
175 unsigned Opc = MII->getOpcode();
176 if (Opc == PPC::BDNZ8 || Opc == PPC::BDNZ ||
177 Opc == PPC::BDZ8 || Opc == PPC::BDZ)
178 if (!verifyCTRBranch(&MBB, MII))
179 llvm_unreachable("Invalid PPC CTR loop!");
180 }
181 }
182
183 return false;
184}
185#endif // NDEBUG
MachineBasicBlock & MBB
#define LLVM_DEBUG(X)
Definition: Debug.h:101
Generic dominator tree construction - this file provides routines to construct immediate dominator in...
Hexagon Hardware Loops
IRTranslator LLVM IR MI
loops
Definition: LoopInfo.cpp:1177
#define I(x, y, z)
Definition: MD5.cpp:58
static bool verifyCTRBranch(MachineBasicBlock *MBB, MachineBasicBlock::iterator I)
ppc ctr loops PowerPC CTR Loops Verify
ppc ctr loops verify
static bool clobbersCTR(const MachineInstr &MI)
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:55
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:59
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:52
This file defines the SmallSet class.
This file defines the SmallVector class.
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
std::string getFullName() const
Return a formatted string to identify this block and its parent function.
iterator_range< pred_iterator > predecessors()
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:135
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:164
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:177
bool empty() const
Definition: SmallVector.h:94
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void append_range(Container &C, Range &&R)
Wrapper function to append a range to a container.
Definition: STLExtras.h:2014
void initializePPCCTRLoopsVerifyPass(PassRegistry &)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
FunctionPass * createPPCCTRLoopsVerify()
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.