LLVM
15.0.0git
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#include "HexagonInstrInfo.h"
#include "HexagonSubtarget.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/InitializePasses.h"
#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include <cassert>
#include <cstdint>
#include <cstdlib>
#include <iterator>
#include <map>
#include <set>
#include <string>
#include <utility>
#include <vector>
Go to the source code of this file.
Namespaces | |
llvm | |
This is an optimization pass for GlobalISel generic memory operations. | |
Macros | |
#define | DEBUG_TYPE "hwloops" |
Functions | |
STATISTIC (NumHWLoops, "Number of loops converted to hardware loops") | |
FunctionPass * | llvm::createHexagonHardwareLoops () |
void | llvm::initializeHexagonHardwareLoopsPass (PassRegistry &) |
INITIALIZE_PASS_BEGIN (HexagonHardwareLoops, "hwloops", "Hexagon Hardware Loops", false, false) INITIALIZE_PASS_END(HexagonHardwareLoops | |
Variables | |
static cl::opt< int > | HWLoopLimit ("hexagon-max-hwloop", cl::Hidden, cl::init(-1)) |
static cl::opt< std::string > | PHFn ("hexagon-hwloop-phfn", cl::Hidden, cl::init("")) |
static cl::opt< bool > | HWCreatePreheader ("hexagon-hwloop-preheader", cl::Hidden, cl::init(true), cl::desc("Add a preheader to a hardware loop if one doesn't exist")) |
static cl::opt< bool > | SpecPreheader ("hwloop-spec-preheader", cl::Hidden, cl::desc("Allow speculation of preheader " "instructions")) |
hwloops | |
Hexagon Hardware | Loops |
Hexagon Hardware | false |
#define DEBUG_TYPE "hwloops" |
Definition at line 66 of file HexagonHardwareLoops.cpp.
INITIALIZE_PASS_BEGIN | ( | HexagonHardwareLoops | , |
"hwloops" | , | ||
"Hexagon Hardware Loops" | , | ||
false | , | ||
false | |||
) |
Hexagon Hardware false |
Definition at line 372 of file HexagonHardwareLoops.cpp.
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static |
hwloops |
Definition at line 371 of file HexagonHardwareLoops.cpp.
Hexagon Hardware Loops |
Definition at line 372 of file HexagonHardwareLoops.cpp.
Referenced by llvm::BlockFrequencyInfoImplBase::analyzeIrreducible(), llvm::appendLoopsToWorklist(), llvm::appendReversedLoopsToWorklist(), llvm::LoopNest::areAllLoopsRotatedForm(), llvm::LoopNest::areAllLoopsSimplifyForm(), llvm::CacheCost::CacheCost(), llvm::BlockFrequencyInfoImplBase::clear(), llvm::OpenMPIRBuilder::collapseLoops(), llvm::denormalizeForPostIncUse(), llvm::DependenceInfo::depends(), llvm::CacheCost::getCacheCost(), getInnerMostLoop(), llvm::LoopNest::getInnermostLoop(), llvm::LoopNest::getLoop(), llvm::LoopNest::getLoops(), llvm::LoopNest::getLoopsAtDepth(), llvm::LoopNest::getName(), llvm::LoopNest::getNestDepth(), llvm::LoopNest::getNumLoops(), llvm::LoopNest::getOutermostLoop(), llvm::LoopNest::getParent(), llvm::DependenceInfo::getSplitIteration(), INITIALIZE_PASS(), llvm::normalizeForPostIncUse(), runImpl(), llvm::RAGreedy::runOnMachineFunction(), llvm::OpenMPIRBuilder::tileLoops(), tryToUnrollAndJamLoop(), llvm::BlockFrequencyInfoImplBase::unwrapLoops(), llvm::LoopInfoBase< BasicBlock, Loop >::verify(), llvm::LoopBase< BasicBlock, Loop >::verifyLoopNest(), and llvm::VirtRegAuxInfo::VirtRegAuxInfo().
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