LLVM 17.0.0git
HexagonSubtarget.h
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1//===- HexagonSubtarget.h - Define Subtarget for the Hexagon ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the Hexagon specific subclass of TargetSubtarget.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
14#define LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
15
16#include "HexagonDepArch.h"
18#include "HexagonISelLowering.h"
19#include "HexagonInstrInfo.h"
20#include "HexagonRegisterInfo.h"
22#include "llvm/ADT/SmallSet.h"
23#include "llvm/ADT/StringRef.h"
28#include <memory>
29#include <string>
30#include <vector>
31
32#define GET_SUBTARGETINFO_HEADER
33#include "HexagonGenSubtargetInfo.inc"
34
35namespace llvm {
36
37class MachineInstr;
38class SDep;
39class SUnit;
40class TargetMachine;
41class Triple;
42
44 virtual void anchor();
45
46 bool UseHVX64BOps = false;
47 bool UseHVX128BOps = false;
48
49 bool UseAudioOps = false;
50 bool UseCompound = false;
51 bool UseLongCalls = false;
52 bool UseMemops = false;
53 bool UsePackets = false;
54 bool UseNewValueJumps = false;
55 bool UseNewValueStores = false;
56 bool UseSmallData = false;
57 bool UseUnsafeMath = false;
58 bool UseZRegOps = false;
59 bool UseHVXIEEEFPOps = false;
60 bool UseHVXQFloatOps = false;
61 bool UseHVXFloatingPoint = false;
62 bool UseCabac = false;
63
64 bool HasPreV65 = false;
65 bool HasMemNoShuf = false;
66 bool EnableDuplex = false;
67 bool ReservedR19 = false;
68 bool NoreturnStackElim = false;
69
70public:
74 /// True if the target should use Back-Skip-Back scheduling. This is the
75 /// default for V60.
77
79 void apply(ScheduleDAGInstrs *DAG) override;
80 };
82 void apply(ScheduleDAGInstrs *DAG) override;
83 };
85 void apply(ScheduleDAGInstrs *DAG) override;
86 private:
87 bool shouldTFRICallBind(const HexagonInstrInfo &HII,
88 const SUnit &Inst1, const SUnit &Inst2) const;
89 };
91 void apply(ScheduleDAGInstrs *DAG) override;
92 };
93
94private:
95 enum HexagonProcFamilyEnum { Others, TinyCore };
96
97 std::string CPUString;
98 HexagonProcFamilyEnum HexagonProcFamily = Others;
99 Triple TargetTriple;
100
101 // The following objects can use the TargetTriple, so they must be
102 // declared after it.
103 HexagonInstrInfo InstrInfo;
107 HexagonFrameLowering FrameLowering;
108 InstrItineraryData InstrItins;
109
110public:
111 HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
112 const TargetMachine &TM);
113
114 const Triple &getTargetTriple() const { return TargetTriple; }
115 bool isEnvironmentMusl() const {
116 return TargetTriple.getEnvironment() == Triple::Musl;
117 }
118
119 /// getInstrItins - Return the instruction itineraries based on subtarget
120 /// selection.
122 return &InstrItins;
123 }
124 const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; }
125 const HexagonRegisterInfo *getRegisterInfo() const override {
126 return &RegInfo;
127 }
128 const HexagonTargetLowering *getTargetLowering() const override {
129 return &TLInfo;
130 }
131 const HexagonFrameLowering *getFrameLowering() const override {
132 return &FrameLowering;
133 }
135 return &TSInfo;
136 }
137
139 StringRef FS);
140
141 /// ParseSubtargetFeatures - Parses features string setting specified
142 /// subtarget options. Definition of function is auto generated by tblgen.
144
145 bool isXRaySupported() const override { return true; }
146
147 bool hasV5Ops() const {
149 }
150 bool hasV5OpsOnly() const {
152 }
153 bool hasV55Ops() const {
155 }
156 bool hasV55OpsOnly() const {
158 }
159 bool hasV60Ops() const {
161 }
162 bool hasV60OpsOnly() const {
164 }
165 bool hasV62Ops() const {
167 }
168 bool hasV62OpsOnly() const {
170 }
171 bool hasV65Ops() const {
173 }
174 bool hasV65OpsOnly() const {
176 }
177 bool hasV66Ops() const {
179 }
180 bool hasV66OpsOnly() const {
182 }
183 bool hasV67Ops() const {
185 }
186 bool hasV67OpsOnly() const {
188 }
189 bool hasV68Ops() const {
191 }
192 bool hasV68OpsOnly() const {
194 }
195 bool hasV69Ops() const {
197 }
198 bool hasV69OpsOnly() const {
200 }
201 bool hasV71Ops() const {
203 }
204 bool hasV71OpsOnly() const {
206 }
207 bool hasV73Ops() const {
209 }
210 bool hasV73OpsOnly() const {
212 }
213
214 bool useAudioOps() const { return UseAudioOps; }
215 bool useCompound() const { return UseCompound; }
216 bool useLongCalls() const { return UseLongCalls; }
217 bool useMemops() const { return UseMemops; }
218 bool usePackets() const { return UsePackets; }
219 bool useNewValueJumps() const { return UseNewValueJumps; }
220 bool useNewValueStores() const { return UseNewValueStores; }
221 bool useSmallData() const { return UseSmallData; }
222 bool useUnsafeMath() const { return UseUnsafeMath; }
223 bool useZRegOps() const { return UseZRegOps; }
224 bool useCabac() const { return UseCabac; }
225
226 bool isTinyCore() const { return HexagonProcFamily == TinyCore; }
227 bool isTinyCoreWithDuplex() const { return isTinyCore() && EnableDuplex; }
228
229 bool useHVXIEEEFPOps() const { return UseHVXIEEEFPOps && useHVXOps(); }
230 bool useHVXQFloatOps() const {
231 return UseHVXQFloatOps && HexagonHVXVersion >= Hexagon::ArchEnum::V68;
232 }
233 bool useHVXFloatingPoint() const { return UseHVXFloatingPoint; }
234 bool useHVXOps() const {
236 }
237 bool useHVXV60Ops() const {
239 }
240 bool useHVXV62Ops() const {
242 }
243 bool useHVXV65Ops() const {
245 }
246 bool useHVXV66Ops() const {
248 }
249 bool useHVXV67Ops() const {
251 }
252 bool useHVXV68Ops() const {
254 }
255 bool useHVXV69Ops() const {
257 }
258 bool useHVXV71Ops() const {
260 }
261 bool useHVXV73Ops() const {
263 }
264 bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; }
265 bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; }
266
267 bool hasMemNoShuf() const { return HasMemNoShuf; }
268 bool hasReservedR19() const { return ReservedR19; }
269 bool usePredicatedCalls() const;
270
271 bool noreturnStackElim() const { return NoreturnStackElim; }
272
273 bool useBSBScheduling() const { return UseBSBScheduling; }
274 bool enableMachineScheduler() const override;
275
276 // Always use the TargetLowering default scheduler.
277 // FIXME: This will use the vliw scheduler which is probably just hurting
278 // compiler time and will be removed eventually anyway.
279 bool enableMachineSchedDefaultSched() const override { return false; }
280
281 // For use with PostRAScheduling: get the anti-dependence breaking that should
282 // be performed before post-RA scheduling.
283 AntiDepBreakMode getAntiDepBreakMode() const override { return ANTIDEP_ALL; }
284 /// True if the subtarget should run a scheduler after register
285 /// allocation.
286 bool enablePostRAScheduler() const override { return true; }
287
288 bool enableSubRegLiveness() const override;
289
290 const std::string &getCPUString () const { return CPUString; }
291
293 return HexagonArchVersion;
294 }
295
297 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
298 const override;
299
300 void getSMSMutations(
301 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
302 const override;
303
304 /// Enable use of alias analysis during code generation (during MI
305 /// scheduling, DAGCombine, etc.).
306 bool useAA() const override;
307
308 /// Perform target specific adjustments to the latency of a schedule
309 /// dependency.
310 void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx,
311 SDep &Dep) const override;
312
313 unsigned getVectorLength() const {
314 assert(useHVXOps());
315 if (useHVX64BOps())
316 return 64;
317 if (useHVX128BOps())
318 return 128;
319 llvm_unreachable("Invalid HVX vector length settings");
320 }
321
323 static MVT Types[] = {MVT::i8, MVT::i16, MVT::i32};
324 static MVT TypesV68[] = {MVT::i8, MVT::i16, MVT::i32, MVT::f16, MVT::f32};
325
327 return ArrayRef(TypesV68);
328 return ArrayRef(Types);
329 }
330
331 bool isHVXElementType(MVT Ty, bool IncludeBool = false) const;
332 bool isHVXVectorType(EVT VecTy, bool IncludeBool = false) const;
333 bool isTypeForHVX(Type *VecTy, bool IncludeBool = false) const;
334
336 if (isHVXVectorType(Ty, true))
337 return Align(getVectorLength());
338 return Align(std::max<unsigned>(1, Ty.getSizeInBits() / 8));
339 }
340
341 unsigned getL1CacheLineSize() const;
342 unsigned getL1PrefetchDistance() const;
343
344 Intrinsic::ID getIntrinsicId(unsigned Opc) const;
345
346private:
347 // Helper function responsible for increasing the latency only.
348 int updateLatency(MachineInstr &SrcInst, MachineInstr &DstInst,
349 bool IsArtificial, int Latency) const;
350 void restoreLatency(SUnit *Src, SUnit *Dst) const;
351 void changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat) const;
352 bool isBestZeroLatency(SUnit *Src, SUnit *Dst, const HexagonInstrInfo *TII,
353 SmallSet<SUnit*, 4> &ExclSrc, SmallSet<SUnit*, 4> &ExclDst) const;
354};
355
356} // end namespace llvm
357
358#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
const HexagonInstrInfo * TII
const char LLVMTargetMachineRef TM
return InstrInfo
unsigned UseOpIdx
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallSet class.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
bool isTinyCoreWithDuplex() const
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
Hexagon::ArchEnum HexagonArchVersion
bool enableMachineSchedDefaultSched() const override
const HexagonInstrInfo * getInstrInfo() const override
const HexagonFrameLowering * getFrameLowering() const override
Hexagon::ArchEnum HexagonHVXVersion
const HexagonRegisterInfo * getRegisterInfo() const override
const Hexagon::ArchEnum & getHexagonArchVersion() const
void getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const override
bool noreturnStackElim() const
bool isHVXVectorType(EVT VecTy, bool IncludeBool=false) const
const Triple & getTargetTriple() const
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const override
const HexagonTargetLowering * getTargetLowering() const override
void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep) const override
Perform target specific adjustments to the latency of a schedule dependency.
CodeGenOpt::Level OptLevel
bool useNewValueStores() const
bool UseBSBScheduling
True if the target should use Back-Skip-Back scheduling.
unsigned getL1PrefetchDistance() const
ArrayRef< MVT > getHVXElementTypes() const
bool useHVXFloatingPoint() const
bool enableSubRegLiveness() const override
Align getTypeAlignment(MVT Ty) const
unsigned getVectorLength() const
AntiDepBreakMode getAntiDepBreakMode() const override
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
unsigned getL1CacheLineSize() const
bool isTypeForHVX(Type *VecTy, bool IncludeBool=false) const
Intrinsic::ID getIntrinsicId(unsigned Opc) const
HexagonSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
const HexagonSelectionDAGInfo * getSelectionDAGInfo() const override
bool enableMachineScheduler() const override
bool enablePostRAScheduler() const override
True if the subtarget should run a scheduler after register allocation.
bool isEnvironmentMusl() const
bool isHVXElementType(MVT Ty, bool IncludeBool=false) const
const std::string & getCPUString() const
bool isXRaySupported() const override
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...
Itinerary data supplied by a subtarget to be used by a target.
Machine Value Type.
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Representation of each machine instruction.
Definition: MachineInstr.h:68
Scheduling dependency.
Definition: ScheduleDAG.h:49
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
A ScheduleDAG for scheduling lists of MachineInstr.
Mutate the DAG as a postpass after normal DAG building.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:135
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
Definition: Triple.h:372
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Level
Code generation optimization level.
Definition: CodeGen.h:57
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
void apply(ScheduleDAGInstrs *DAG) override
void apply(ScheduleDAGInstrs *DAG) override
void apply(ScheduleDAGInstrs *DAG) override
void apply(ScheduleDAGInstrs *DAG) override