LLVM  15.0.0git
HexagonSubtarget.h
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1 //===- HexagonSubtarget.h - Define Subtarget for the Hexagon ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the Hexagon specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
14 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
15 
16 #include "HexagonDepArch.h"
17 #include "HexagonFrameLowering.h"
18 #include "HexagonISelLowering.h"
19 #include "HexagonInstrInfo.h"
20 #include "HexagonRegisterInfo.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/StringRef.h"
27 #include "llvm/Support/Alignment.h"
28 #include <memory>
29 #include <string>
30 #include <vector>
31 
32 #define GET_SUBTARGETINFO_HEADER
33 #include "HexagonGenSubtargetInfo.inc"
34 
35 namespace llvm {
36 
37 class MachineInstr;
38 class SDep;
39 class SUnit;
40 class TargetMachine;
41 class Triple;
42 
44  virtual void anchor();
45 
46  bool UseHVX64BOps = false;
47  bool UseHVX128BOps = false;
48 
49  bool UseAudioOps = false;
50  bool UseCompound = false;
51  bool UseLongCalls = false;
52  bool UseMemops = false;
53  bool UsePackets = false;
54  bool UseNewValueJumps = false;
55  bool UseNewValueStores = false;
56  bool UseSmallData = false;
57  bool UseUnsafeMath = false;
58  bool UseZRegOps = false;
59  bool UseHVXIEEEFPOps = false;
60  bool UseHVXQFloatOps = false;
61  bool UseHVXFloatingPoint = false;
62  bool UseCabac = false;
63 
64  bool HasPreV65 = false;
65  bool HasMemNoShuf = false;
66  bool EnableDuplex = false;
67  bool ReservedR19 = false;
68  bool NoreturnStackElim = false;
69 
70 public:
74  /// True if the target should use Back-Skip-Back scheduling. This is the
75  /// default for V60.
77 
79  void apply(ScheduleDAGInstrs *DAG) override;
80  };
82  void apply(ScheduleDAGInstrs *DAG) override;
83  };
85  void apply(ScheduleDAGInstrs *DAG) override;
86  private:
87  bool shouldTFRICallBind(const HexagonInstrInfo &HII,
88  const SUnit &Inst1, const SUnit &Inst2) const;
89  };
91  void apply(ScheduleDAGInstrs *DAG) override;
92  };
93 
94 private:
95  enum HexagonProcFamilyEnum { Others, TinyCore };
96 
97  std::string CPUString;
98  Triple TargetTriple;
99 
100  // The following objects can use the TargetTriple, so they must be
101  // declared after it.
102  HexagonProcFamilyEnum HexagonProcFamily = Others;
103  HexagonInstrInfo InstrInfo;
105  HexagonTargetLowering TLInfo;
107  HexagonFrameLowering FrameLowering;
108  InstrItineraryData InstrItins;
109 
110 public:
111  HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
112  const TargetMachine &TM);
113 
114  const Triple &getTargetTriple() const { return TargetTriple; }
115  bool isEnvironmentMusl() const {
116  return TargetTriple.getEnvironment() == Triple::Musl;
117  }
118 
119  /// getInstrItins - Return the instruction itineraries based on subtarget
120  /// selection.
121  const InstrItineraryData *getInstrItineraryData() const override {
122  return &InstrItins;
123  }
124  const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; }
125  const HexagonRegisterInfo *getRegisterInfo() const override {
126  return &RegInfo;
127  }
128  const HexagonTargetLowering *getTargetLowering() const override {
129  return &TLInfo;
130  }
131  const HexagonFrameLowering *getFrameLowering() const override {
132  return &FrameLowering;
133  }
135  return &TSInfo;
136  }
137 
139  StringRef FS);
140 
141  /// ParseSubtargetFeatures - Parses features string setting specified
142  /// subtarget options. Definition of function is auto generated by tblgen.
144 
145  bool isXRaySupported() const override { return true; }
146 
147  bool hasV5Ops() const {
149  }
150  bool hasV5OpsOnly() const {
152  }
153  bool hasV55Ops() const {
155  }
156  bool hasV55OpsOnly() const {
158  }
159  bool hasV60Ops() const {
161  }
162  bool hasV60OpsOnly() const {
164  }
165  bool hasV62Ops() const {
167  }
168  bool hasV62OpsOnly() const {
170  }
171  bool hasV65Ops() const {
173  }
174  bool hasV65OpsOnly() const {
176  }
177  bool hasV66Ops() const {
179  }
180  bool hasV66OpsOnly() const {
182  }
183  bool hasV67Ops() const {
185  }
186  bool hasV67OpsOnly() const {
188  }
189  bool hasV68Ops() const {
191  }
192  bool hasV68OpsOnly() const {
194  }
195  bool hasV69Ops() const {
197  }
198  bool hasV69OpsOnly() const {
200  }
201 
202  bool useAudioOps() const { return UseAudioOps; }
203  bool useCompound() const { return UseCompound; }
204  bool useLongCalls() const { return UseLongCalls; }
205  bool useMemops() const { return UseMemops; }
206  bool usePackets() const { return UsePackets; }
207  bool useNewValueJumps() const { return UseNewValueJumps; }
208  bool useNewValueStores() const { return UseNewValueStores; }
209  bool useSmallData() const { return UseSmallData; }
210  bool useUnsafeMath() const { return UseUnsafeMath; }
211  bool useZRegOps() const { return UseZRegOps; }
212  bool useCabac() const { return UseCabac; }
213 
214  bool isTinyCore() const { return HexagonProcFamily == TinyCore; }
215  bool isTinyCoreWithDuplex() const { return isTinyCore() && EnableDuplex; }
216 
217  bool useHVXIEEEFPOps() const { return UseHVXIEEEFPOps && useHVXOps(); }
218  bool useHVXQFloatOps() const {
219  return UseHVXQFloatOps && HexagonHVXVersion >= Hexagon::ArchEnum::V68;
220  }
221  bool useHVXFloatingPoint() const { return UseHVXFloatingPoint; }
222  bool useHVXOps() const {
224  }
225  bool useHVXV60Ops() const {
227  }
228  bool useHVXV62Ops() const {
230  }
231  bool useHVXV65Ops() const {
233  }
234  bool useHVXV66Ops() const {
236  }
237  bool useHVXV67Ops() const {
239  }
240  bool useHVXV68Ops() const {
242  }
243  bool useHVXV69Ops() const {
245  }
246  bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; }
247  bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; }
248 
249  bool hasMemNoShuf() const { return HasMemNoShuf; }
250  bool hasReservedR19() const { return ReservedR19; }
251  bool usePredicatedCalls() const;
252 
253  bool noreturnStackElim() const { return NoreturnStackElim; }
254 
255  bool useBSBScheduling() const { return UseBSBScheduling; }
256  bool enableMachineScheduler() const override;
257 
258  // Always use the TargetLowering default scheduler.
259  // FIXME: This will use the vliw scheduler which is probably just hurting
260  // compiler time and will be removed eventually anyway.
261  bool enableMachineSchedDefaultSched() const override { return false; }
262 
263  // For use with PostRAScheduling: get the anti-dependence breaking that should
264  // be performed before post-RA scheduling.
265  AntiDepBreakMode getAntiDepBreakMode() const override { return ANTIDEP_ALL; }
266  /// True if the subtarget should run a scheduler after register
267  /// allocation.
268  bool enablePostRAScheduler() const override { return true; }
269 
270  bool enableSubRegLiveness() const override;
271 
272  const std::string &getCPUString () const { return CPUString; }
273 
275  return HexagonArchVersion;
276  }
277 
278  void getPostRAMutations(
279  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
280  const override;
281 
282  void getSMSMutations(
283  std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
284  const override;
285 
286  /// Enable use of alias analysis during code generation (during MI
287  /// scheduling, DAGCombine, etc.).
288  bool useAA() const override;
289 
290  /// Perform target specific adjustments to the latency of a schedule
291  /// dependency.
292  void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx,
293  SDep &Dep) const override;
294 
295  unsigned getVectorLength() const {
296  assert(useHVXOps());
297  if (useHVX64BOps())
298  return 64;
299  if (useHVX128BOps())
300  return 128;
301  llvm_unreachable("Invalid HVX vector length settings");
302  }
303 
305  static MVT Types[] = {MVT::i8, MVT::i16, MVT::i32};
306  static MVT TypesV68[] = {MVT::i8, MVT::i16, MVT::i32, MVT::f16, MVT::f32};
307 
309  return makeArrayRef(TypesV68);
310  return makeArrayRef(Types);
311  }
312 
313  bool isHVXElementType(MVT Ty, bool IncludeBool = false) const;
314  bool isHVXVectorType(MVT VecTy, bool IncludeBool = false) const;
315  bool isTypeForHVX(Type *VecTy, bool IncludeBool = false) const;
316 
318  if (isHVXVectorType(Ty, true))
319  return Align(getVectorLength());
320  return Align(std::max<unsigned>(1, Ty.getSizeInBits() / 8));
321  }
322 
323  unsigned getL1CacheLineSize() const;
324  unsigned getL1PrefetchDistance() const;
325 
326 private:
327  // Helper function responsible for increasing the latency only.
328  int updateLatency(MachineInstr &SrcInst, MachineInstr &DstInst,
329  bool IsArtificial, int Latency) const;
330  void restoreLatency(SUnit *Src, SUnit *Dst) const;
331  void changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat) const;
332  bool isBestZeroLatency(SUnit *Src, SUnit *Dst, const HexagonInstrInfo *TII,
333  SmallSet<SUnit*, 4> &ExclSrc, SmallSet<SUnit*, 4> &ExclDst) const;
334 };
335 
336 } // end namespace llvm
337 
338 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
llvm::HexagonSubtarget::useHVX64BOps
bool useHVX64BOps() const
Definition: HexagonSubtarget.h:247
llvm::HexagonSubtarget::hasV68Ops
bool hasV68Ops() const
Definition: HexagonSubtarget.h:189
llvm::HexagonSubtarget::getVectorLength
unsigned getVectorLength() const
Definition: HexagonSubtarget.h:295
llvm::HexagonSubtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
llvm::Hexagon::ArchEnum
ArchEnum
Definition: HexagonDepArch.h:19
llvm::HexagonSubtarget::useNewValueStores
bool useNewValueStores() const
Definition: HexagonSubtarget.h:208
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::HexagonSubtarget::useSmallData
bool useSmallData() const
Definition: HexagonSubtarget.h:209
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
llvm::Hexagon::ArchEnum::NoArch
@ NoArch
llvm::HexagonSubtarget::getFrameLowering
const HexagonFrameLowering * getFrameLowering() const override
Definition: HexagonSubtarget.h:131
llvm::Hexagon::ArchEnum::V65
@ V65
llvm::Latency
@ Latency
Definition: SIMachineScheduler.h:34
llvm::HexagonSubtarget::useHVXV60Ops
bool useHVXV60Ops() const
Definition: HexagonSubtarget.h:225
StringRef.h
llvm::HexagonSubtarget::HexagonSubtarget
HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM)
Definition: HexagonSubtarget.cpp:82
llvm::HexagonSubtarget::useHVXFloatingPoint
bool useHVXFloatingPoint() const
Definition: HexagonSubtarget.h:221
llvm::HexagonSubtarget::useHVXQFloatOps
bool useHVXQFloatOps() const
Definition: HexagonSubtarget.h:218
llvm::HexagonSubtarget::getHexagonArchVersion
const Hexagon::ArchEnum & getHexagonArchVersion() const
Definition: HexagonSubtarget.h:274
llvm::HexagonSubtarget::useCabac
bool useCabac() const
Definition: HexagonSubtarget.h:212
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::HexagonSelectionDAGInfo
Definition: HexagonSelectionDAGInfo.h:20
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::HexagonSubtarget::hasV69Ops
bool hasV69Ops() const
Definition: HexagonSubtarget.h:195
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:136
llvm::HexagonSubtarget::HexagonArchVersion
Hexagon::ArchEnum HexagonArchVersion
Definition: HexagonSubtarget.h:71
llvm::HexagonSubtarget::useAudioOps
bool useAudioOps() const
Definition: HexagonSubtarget.h:202
llvm::HexagonSubtarget::enableSubRegLiveness
bool enableSubRegLiveness() const override
Definition: HexagonSubtarget.cpp:739
llvm::Hexagon::ArchEnum::V5
@ V5
HexagonFrameLowering.h
llvm::HexagonSubtarget::useMemops
bool useMemops() const
Definition: HexagonSubtarget.h:205
llvm::HexagonSubtarget::isTypeForHVX
bool isTypeForHVX(Type *VecTy, bool IncludeBool=false) const
Definition: HexagonSubtarget.cpp:226
llvm::HexagonSubtarget::BankConflictMutation::apply
void apply(ScheduleDAGInstrs *DAG) override
Definition: HexagonSubtarget.cpp:394
llvm::HexagonSubtarget::useHVXV69Ops
bool useHVXV69Ops() const
Definition: HexagonSubtarget.h:243
llvm::Hexagon::ArchEnum::V66
@ V66
llvm::HexagonSubtarget::getHVXElementTypes
ArrayRef< MVT > getHVXElementTypes() const
Definition: HexagonSubtarget.h:304
llvm::HexagonSubtarget::hasReservedR19
bool hasReservedR19() const
Definition: HexagonSubtarget.h:250
llvm::HexagonSubtarget::getL1CacheLineSize
unsigned getL1CacheLineSize() const
Definition: HexagonSubtarget.cpp:731
llvm::HexagonSubtarget::isEnvironmentMusl
bool isEnvironmentMusl() const
Definition: HexagonSubtarget.h:115
llvm::HexagonSubtarget::getSMSMutations
void getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
Definition: HexagonSubtarget.cpp:535
llvm::HexagonSubtarget::UseBSBScheduling
bool UseBSBScheduling
True if the target should use Back-Skip-Back scheduling.
Definition: HexagonSubtarget.h:76
MCInstrItineraries.h
llvm::Triple::Musl
@ Musl
Definition: Triple.h:230
llvm::HexagonSubtarget::hasV55Ops
bool hasV55Ops() const
Definition: HexagonSubtarget.h:153
llvm::HexagonSubtarget::CallMutation
Definition: HexagonSubtarget.h:84
HexagonSelectionDAGInfo.h
llvm::HexagonSubtarget::OptLevel
CodeGenOpt::Level OptLevel
Definition: HexagonSubtarget.h:73
llvm::HexagonSubtarget::enableMachineSchedDefaultSched
bool enableMachineSchedDefaultSched() const override
Definition: HexagonSubtarget.h:261
llvm::HexagonSubtarget::useHVXV66Ops
bool useHVXV66Ops() const
Definition: HexagonSubtarget.h:234
llvm::HexagonSubtarget::enableMachineScheduler
bool enableMachineScheduler() const override
Definition: HexagonSubtarget.cpp:544
llvm::HexagonSubtarget::useNewValueJumps
bool useNewValueJumps() const
Definition: HexagonSubtarget.h:207
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
llvm::HexagonSubtarget::useHVXOps
bool useHVXOps() const
Definition: HexagonSubtarget.h:222
llvm::HexagonSubtarget::getCPUString
const std::string & getCPUString() const
Definition: HexagonSubtarget.h:272
llvm::HexagonSubtarget::hasV65Ops
bool hasV65Ops() const
Definition: HexagonSubtarget.h:171
llvm::Hexagon::ArchEnum::V62
@ V62
llvm::HexagonSubtarget::isTinyCore
bool isTinyCore() const
Definition: HexagonSubtarget.h:214
HexagonGenSubtargetInfo
llvm::HexagonSubtarget::enablePostRAScheduler
bool enablePostRAScheduler() const override
True if the subtarget should run a scheduler after register allocation.
Definition: HexagonSubtarget.h:268
HexagonInstrInfo.h
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::HexagonSubtarget::HVXMemLatencyMutation
Definition: HexagonSubtarget.h:81
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::HexagonSubtarget::isHVXVectorType
bool isHVXVectorType(MVT VecTy, bool IncludeBool=false) const
Definition: HexagonSubtarget.cpp:200
llvm::HexagonSubtarget::getL1PrefetchDistance
unsigned getL1PrefetchDistance() const
Definition: HexagonSubtarget.cpp:735
llvm::Hexagon::ArchEnum::V67
@ V67
llvm::HexagonSubtarget::isXRaySupported
bool isXRaySupported() const override
Definition: HexagonSubtarget.h:145
llvm::HexagonSubtarget::getInstrInfo
const HexagonInstrInfo * getInstrInfo() const override
Definition: HexagonSubtarget.h:124
llvm::HexagonSubtarget::getTargetTriple
const Triple & getTargetTriple() const
Definition: HexagonSubtarget.h:114
llvm::HexagonSubtarget::hasV62Ops
bool hasV62Ops() const
Definition: HexagonSubtarget.h:165
llvm::HexagonSubtarget::noreturnStackElim
bool noreturnStackElim() const
Definition: HexagonSubtarget.h:253
llvm::HexagonSubtarget::BankConflictMutation
Definition: HexagonSubtarget.h:90
llvm::HexagonSubtarget::useUnsafeMath
bool useUnsafeMath() const
Definition: HexagonSubtarget.h:210
llvm::HexagonSubtarget::usePackets
bool usePackets() const
Definition: HexagonSubtarget.h:206
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::HexagonSubtarget::useAA
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...
Definition: HexagonSubtarget.cpp:443
llvm::HexagonSubtarget::getTypeAlignment
Align getTypeAlignment(MVT Ty) const
Definition: HexagonSubtarget.h:317
llvm::HexagonSubtarget::hasV68OpsOnly
bool hasV68OpsOnly() const
Definition: HexagonSubtarget.h:192
llvm::HexagonSubtarget::CallMutation::apply
void apply(ScheduleDAGInstrs *DAG) override
Definition: HexagonSubtarget.cpp:325
llvm::HexagonSubtarget::hasMemNoShuf
bool hasMemNoShuf() const
Definition: HexagonSubtarget.h:249
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:44
HexagonRegisterInfo.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:864
llvm::Hexagon::ArchEnum::V55
@ V55
llvm::HexagonSubtarget::hasV69OpsOnly
bool hasV69OpsOnly() const
Definition: HexagonSubtarget.h:198
llvm::HexagonSubtarget::isTinyCoreWithDuplex
bool isTinyCoreWithDuplex() const
Definition: HexagonSubtarget.h:215
llvm::HexagonSubtarget::hasV55OpsOnly
bool hasV55OpsOnly() const
Definition: HexagonSubtarget.h:156
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
HexagonISelLowering.h
llvm::HexagonSubtarget::hasV60OpsOnly
bool hasV60OpsOnly() const
Definition: HexagonSubtarget.h:162
llvm::HexagonSubtarget::usePredicatedCalls
bool usePredicatedCalls() const
Definition: HexagonSubtarget.cpp:550
llvm::HexagonInstrInfo
Definition: HexagonInstrInfo.h:38
llvm::HexagonSubtarget::useHVXV68Ops
bool useHVXV68Ops() const
Definition: HexagonSubtarget.h:240
llvm::HexagonSubtarget::hasV66Ops
bool hasV66Ops() const
Definition: HexagonSubtarget.h:177
ScheduleDAGMutation.h
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
RegInfo
Definition: AMDGPUAsmParser.cpp:2500
llvm::HexagonSubtarget::useLongCalls
bool useLongCalls() const
Definition: HexagonSubtarget.h:204
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::HexagonSubtarget::isHVXElementType
bool isHVXElementType(MVT Ty, bool IncludeBool=false) const
Definition: HexagonSubtarget.cpp:189
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::HexagonTargetLowering
Definition: HexagonISelLowering.h:105
llvm::HexagonSubtarget::getPostRAMutations
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
Definition: HexagonSubtarget.cpp:528
TargetSubtargetInfo.h
llvm::HexagonSubtarget::useCompound
bool useCompound() const
Definition: HexagonSubtarget.h:203
llvm::HexagonSubtarget::UsrOverflowMutation
Definition: HexagonSubtarget.h:78
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::HexagonSubtarget::hasV5Ops
bool hasV5Ops() const
Definition: HexagonSubtarget.h:147
llvm::SDep
Scheduling dependency.
Definition: ScheduleDAG.h:49
llvm::HexagonSubtarget::hasV66OpsOnly
bool hasV66OpsOnly() const
Definition: HexagonSubtarget.h:180
llvm::HexagonSubtarget::UsrOverflowMutation::apply
void apply(ScheduleDAGInstrs *DAG) override
Definition: HexagonSubtarget.cpp:261
Alignment.h
llvm::HexagonSubtarget::getSelectionDAGInfo
const HexagonSelectionDAGInfo * getSelectionDAGInfo() const override
Definition: HexagonSubtarget.h:134
llvm::HexagonFrameLowering
Definition: HexagonFrameLowering.h:31
llvm::HexagonSubtarget::getRegisterInfo
const HexagonRegisterInfo * getRegisterInfo() const override
Definition: HexagonSubtarget.h:125
llvm::HexagonSubtarget::hasV65OpsOnly
bool hasV65OpsOnly() const
Definition: HexagonSubtarget.h:174
llvm::HexagonSubtarget::initializeSubtargetDependencies
HexagonSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
Definition: HexagonSubtarget.cpp:97
llvm::HexagonSubtarget::getTargetLowering
const HexagonTargetLowering * getTargetLowering() const override
Definition: HexagonSubtarget.h:128
llvm::HexagonSubtarget::hasV62OpsOnly
bool hasV62OpsOnly() const
Definition: HexagonSubtarget.h:168
llvm::Hexagon::ArchEnum::V69
@ V69
llvm::HexagonSubtarget::HexagonHVXVersion
Hexagon::ArchEnum HexagonHVXVersion
Definition: HexagonSubtarget.h:72
llvm::HexagonSubtarget::useBSBScheduling
bool useBSBScheduling() const
Definition: HexagonSubtarget.h:255
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::HexagonSubtarget::useHVXV67Ops
bool useHVXV67Ops() const
Definition: HexagonSubtarget.h:237
llvm::HexagonSubtarget::hasV67OpsOnly
bool hasV67OpsOnly() const
Definition: HexagonSubtarget.h:186
llvm::HexagonSubtarget::getAntiDepBreakMode
AntiDepBreakMode getAntiDepBreakMode() const override
Definition: HexagonSubtarget.h:265
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:475
HexagonDepArch.h
llvm::HexagonSubtarget::getInstrItineraryData
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
Definition: HexagonSubtarget.h:121
llvm::HexagonSubtarget::useHVXV65Ops
bool useHVXV65Ops() const
Definition: HexagonSubtarget.h:231
llvm::MVT::f16
@ f16
Definition: MachineValueType.h:54
llvm::HexagonSubtarget::hasV67Ops
bool hasV67Ops() const
Definition: HexagonSubtarget.h:183
llvm::Hexagon::ArchEnum::V68
@ V68
llvm::HexagonSubtarget
Definition: HexagonSubtarget.h:43
llvm::HexagonSubtarget::useHVXV62Ops
bool useHVXV62Ops() const
Definition: HexagonSubtarget.h:228
llvm::ScheduleDAGMutation
Mutate the DAG as a postpass after normal DAG building.
Definition: ScheduleDAGMutation.h:22
llvm::Triple::getEnvironment
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
Definition: Triple.h:354
llvm::HexagonSubtarget::useHVX128BOps
bool useHVX128BOps() const
Definition: HexagonSubtarget.h:246
llvm::Hexagon::ArchEnum::V60
@ V60
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:45
llvm::SUnit
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
llvm::HexagonRegisterInfo
Definition: HexagonRegisterInfo.h:29
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:119
llvm::HexagonSubtarget::hasV5OpsOnly
bool hasV5OpsOnly() const
Definition: HexagonSubtarget.h:150
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::HexagonSubtarget::useHVXIEEEFPOps
bool useHVXIEEEFPOps() const
Definition: HexagonSubtarget.h:217
llvm::MVT::f32
@ f32
Definition: MachineValueType.h:55
llvm::HexagonSubtarget::useZRegOps
bool useZRegOps() const
Definition: HexagonSubtarget.h:211
llvm::HexagonSubtarget::hasV60Ops
bool hasV60Ops() const
Definition: HexagonSubtarget.h:159
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::HexagonSubtarget::adjustSchedDependency
void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep) const override
Perform target specific adjustments to the latency of a schedule dependency.
Definition: HexagonSubtarget.cpp:451
llvm::HexagonSubtarget::HVXMemLatencyMutation::apply
void apply(ScheduleDAGInstrs *DAG) override
Definition: HexagonSubtarget.cpp:274
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
SmallSet.h