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13 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
14 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
32 #define GET_SUBTARGETINFO_HEADER
33 #include "HexagonGenSubtargetInfo.inc"
44 virtual void anchor();
46 bool UseHVX64BOps =
false;
47 bool UseHVX128BOps =
false;
49 bool UseAudioOps =
false;
50 bool UseCompound =
false;
51 bool UseLongCalls =
false;
52 bool UseMemops =
false;
53 bool UsePackets =
false;
54 bool UseNewValueJumps =
false;
55 bool UseNewValueStores =
false;
56 bool UseSmallData =
false;
57 bool UseUnsafeMath =
false;
58 bool UseZRegOps =
false;
59 bool UseHVXIEEEFPOps =
false;
60 bool UseHVXQFloatOps =
false;
61 bool UseHVXFloatingPoint =
false;
62 bool UseCabac =
false;
64 bool HasPreV65 =
false;
65 bool HasMemNoShuf =
false;
66 bool EnableDuplex =
false;
67 bool ReservedR19 =
false;
68 bool NoreturnStackElim =
false;
95 enum HexagonProcFamilyEnum { Others, TinyCore };
97 std::string CPUString;
102 HexagonProcFamilyEnum HexagonProcFamily = Others;
132 return &FrameLowering;
214 bool isTinyCore()
const {
return HexagonProcFamily == TinyCore; }
279 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
283 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
288 bool useAA()
const override;
293 SDep &Dep)
const override;
329 bool IsArtificial,
int Latency)
const;
330 void restoreLatency(
SUnit *Src,
SUnit *Dst)
const;
331 void changeLatency(
SUnit *Src,
SUnit *Dst,
unsigned Lat)
const;
338 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
bool useHVX64BOps() const
unsigned getVectorLength() const
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool useNewValueStores() const
This is an optimization pass for GlobalISel generic memory operations.
bool useSmallData() const
const HexagonFrameLowering * getFrameLowering() const override
bool useHVXV60Ops() const
HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM)
bool useHVXFloatingPoint() const
bool useHVXQFloatOps() const
const Hexagon::ArchEnum & getHexagonArchVersion() const
Triple - Helper class for working with autoconf configuration names.
The instances of the Type class are immutable: once they are created, they are never changed.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Hexagon::ArchEnum HexagonArchVersion
bool enableSubRegLiveness() const override
bool isTypeForHVX(Type *VecTy, bool IncludeBool=false) const
void apply(ScheduleDAGInstrs *DAG) override
bool useHVXV69Ops() const
ArrayRef< MVT > getHVXElementTypes() const
bool hasReservedR19() const
unsigned getL1CacheLineSize() const
bool isEnvironmentMusl() const
void getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
bool UseBSBScheduling
True if the target should use Back-Skip-Back scheduling.
CodeGenOpt::Level OptLevel
bool enableMachineSchedDefaultSched() const override
bool useHVXV66Ops() const
bool enableMachineScheduler() const override
bool useNewValueJumps() const
const HexagonInstrInfo * TII
const std::string & getCPUString() const
bool enablePostRAScheduler() const override
True if the subtarget should run a scheduler after register allocation.
This struct is a compact representation of a valid (non-zero power of two) alignment.
bool isHVXVectorType(MVT VecTy, bool IncludeBool=false) const
unsigned getL1PrefetchDistance() const
bool isXRaySupported() const override
const HexagonInstrInfo * getInstrInfo() const override
const Triple & getTargetTriple() const
bool noreturnStackElim() const
bool useUnsafeMath() const
Representation of each machine instruction.
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...
Align getTypeAlignment(MVT Ty) const
bool hasV68OpsOnly() const
void apply(ScheduleDAGInstrs *DAG) override
bool hasMemNoShuf() const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Primary interface to the complete machine description for the target machine.
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
bool hasV69OpsOnly() const
bool isTinyCoreWithDuplex() const
bool hasV55OpsOnly() const
bool hasV60OpsOnly() const
bool usePredicatedCalls() const
bool useHVXV68Ops() const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool useLongCalls() const
StringRef - Represent a constant reference to a string, i.e.
bool isHVXElementType(MVT Ty, bool IncludeBool=false) const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
bool hasV66OpsOnly() const
void apply(ScheduleDAGInstrs *DAG) override
const HexagonSelectionDAGInfo * getSelectionDAGInfo() const override
const HexagonRegisterInfo * getRegisterInfo() const override
bool hasV65OpsOnly() const
HexagonSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
const HexagonTargetLowering * getTargetLowering() const override
bool hasV62OpsOnly() const
Hexagon::ArchEnum HexagonHVXVersion
bool useBSBScheduling() const
bool useHVXV67Ops() const
bool hasV67OpsOnly() const
AntiDepBreakMode getAntiDepBreakMode() const override
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
bool useHVXV65Ops() const
bool useHVXV62Ops() const
Mutate the DAG as a postpass after normal DAG building.
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
bool useHVX128BOps() const
const char LLVMTargetMachineRef TM
Scheduling unit. This is a node in the scheduling DAG.
A ScheduleDAG for scheduling lists of MachineInstr.
bool hasV5OpsOnly() const
bool useHVXIEEEFPOps() const
Itinerary data supplied by a subtarget to be used by a target.
void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep) const override
Perform target specific adjustments to the latency of a schedule dependency.
void apply(ScheduleDAGInstrs *DAG) override
A Use represents the edge between a Value definition and its users.