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13 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
14 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
26 #define GET_INSTRINFO_HEADER
27 #include "HexagonGenInstrInfo.inc"
31 class HexagonSubtarget;
32 class MachineBranchProbabilityInfo;
33 class MachineFunction;
36 class TargetRegisterInfo;
41 enum BundleAttribute {
42 memShufDisabledMask = 0x4
45 virtual void anchor();
109 bool AllowModify)
const override;
115 int *BytesRemoved =
nullptr)
const override;
130 int *BytesAdded =
nullptr)
const override;
134 std::unique_ptr<PipelinerLoopInfo>
143 unsigned ExtraPredCycles,
153 unsigned NumTCycles,
unsigned ExtraTCycles,
155 unsigned NumFCycles,
unsigned ExtraFCycles,
177 bool KillSrc)
const override;
210 bool &OffsetIsScalable,
unsigned &
Width,
242 bool SkipDead)
const override;
274 int64_t &
Value)
const override;
281 unsigned *PredCost =
nullptr)
const override;
298 unsigned &OffsetPos)
const override;
314 unsigned UseIdx)
const override;
318 std::pair<unsigned, unsigned>
368 bool isExpr(
unsigned OpType)
const;
442 unsigned &AccessSize)
const;
471 unsigned &PredRegPos,
unsigned &PredRegFlags)
const;
500 bool ToBigInstrs)
const;
502 bool ToBigInstrs =
true)
const;
504 bool ToBigInstrs)
const;
540 #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
short changeAddrMode_io_abs(const MachineInstr &MI) const
bool isTailCall(const MachineInstr &MI) const override
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Test if the given instruction should be considered a scheduling boundary.
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
This is an optimization pass for GlobalISel generic memory operations.
unsigned nonDbgBBSize(const MachineBasicBlock *BB) const
getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Clas...
HexagonInstrInfo(HexagonSubtarget &ST)
MachineInstrBuilder & UseMI
bool isAbsoluteSet(const MachineInstr &MI) const
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
short changeAddrMode_io_rr(short Opc) const
InstrStage::FuncUnits getUnits(const MachineInstr &MI) const
HexagonII::CompoundGroup getCompoundCandidateGroup(const MachineInstr &MI) const
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Remove the branching code at the end of the specific MBB.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
bool isJumpR(const MachineInstr &MI) const
bool hasPseudoInstrPair(const MachineInstr &MI) const
bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const
bool isSpillPredRegOp(const MachineInstr &MI) const
This class is intended to be used as a base class for asm properties and features specific to the tar...
bool isZeroExtendingLoad(const MachineInstr &MI) const
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
int getNonDotCurOp(const MachineInstr &MI) const
short changeAddrMode_io_pi(short Opc) const
short getRegForm(const MachineInstr &MI) const
bool predOpcodeHasNot(ArrayRef< MachineOperand > Cond) const
bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const override
For instructions with a base and offset, return the position of the base register and offset operands...
MCInst getNop() const override
unsigned getAddrMode(const MachineInstr &MI) const
bool isTC2(const MachineInstr &MI) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
short changeAddrMode_abs_io(short Opc) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override
Return an array that contains the bitmask target flag values and their names.
bool isAddrModeWithOffset(const MachineInstr &MI) const
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert a noop into the instruction stream at the specified point.
bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const
bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has load from stack slots.
bool isHVXMemWithAIndirect(const MachineInstr &I, const MachineInstr &J) const
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
bool invertAndChangeJumpTarget(MachineInstr &MI, MachineBasicBlock *NewTarget) const
int getDotNewPredOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Return an array that contains the direct target flag values and their names.
short changeAddrMode_pi_io(short Opc) const
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
bool isNewValueStore(const MachineInstr &MI) const
bool isSolo(const MachineInstr &MI) const
bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
If the specified instruction defines any predicate or condition code register(s) used for predication...
Instances of this class represent a single low-level machine instruction.
bool isDependent(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
bool isPostIncrement(const MachineInstr &MI) const override
Return true for post-incremented instructions.
unsigned const TargetRegisterInfo * TRI
std::unique_ptr< PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...
bool isPredicable(const MachineInstr &MI) const override
Return true if the specified instruction can be predicated.
Instructions::const_iterator const_instr_iterator
bool isEarlySourceInstr(const MachineInstr &MI) const
bool isNewValueJump(const MachineInstr &MI) const
bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI, const MachineInstr &ESMI) const
bool isAsCheapAsAMove(const MachineInstr &MI) const override
bool hasEHLabel(const MachineBasicBlock *B) const
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
int getDotOldOp(const MachineInstr &MI) const
bool mayBeNewStore(const MachineInstr &MI) const
int getCondOpcode(int Opc, bool sense) const
bool isPureSlot0(const MachineInstr &MI) const
bool isVecUsableNextPacket(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
bool isTC2Early(const MachineInstr &MI) const
bool isEndLoopN(unsigned Opcode) const
bool doesNotReturn(const MachineInstr &CallMI) const
bool isLateSourceInstr(const MachineInstr &MI) const
bool hasUncondBranch(const MachineBasicBlock *B) const
short getEquivalentHWInstr(const MachineInstr &MI) const
short changeAddrMode_ur_rr(const MachineInstr &MI) const
int getDotNewOp(const MachineInstr &MI) const
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
into llvm powi allowing the code generator to produce balanced multiplication trees First
MachineOperand class - Representation of each machine instruction operand.
HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI) const
uint64_t getType(const MachineInstr &MI) const
int getMaxValue(const MachineInstr &MI) const
unsigned getCompoundOpcode(const MachineInstr &GA, const MachineInstr &GB) const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Insert branch code into the end of the specified MachineBasicBlock.
bool shouldSink(const MachineInstr &MI) const override
bool isVecALU(const MachineInstr &MI) const
bool isNewValue(const MachineInstr &MI) const
MachineInstr * findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp, MachineBasicBlock *TargetBB, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const
Find the hardware loop instruction used to set-up the specified loop.
MachineOperand * getBaseAndOffset(const MachineInstr &MI, int64_t &Offset, unsigned &AccessSize) const
short changeAddrMode_io_abs(short Opc) const
bool isIndirectL4Return(const MachineInstr &MI) const
bool PredOpcodeHasJMP_c(unsigned Opcode) const
bool isMemOp(const MachineInstr &MI) const
unsigned getSize(const MachineInstr &MI) const
unsigned createVR(MachineFunction *MF, MVT VT) const
HexagonInstrInfo specifics.
unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Compute the instruction latency of a given instruction.
bool reversePredSense(MachineInstr &MI) const
bool isLoopN(const MachineInstr &MI) const
bool isIndirectCall(const MachineInstr &MI) const
bool isDotNewInst(const MachineInstr &MI) const
Representation of each machine instruction.
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Return true if it's profitable for if-converter to duplicate instructions of specified accumulated in...
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
int getDotCurOp(const MachineInstr &MI) const
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index.
bool isBaseImmOffset(const MachineInstr &MI) const
SmallVector< MachineInstr *, 2 > getBranchingInstrs(MachineBasicBlock &MBB) const
void genAllInsnTimingClasses(MachineFunction &MF) const
short getPseudoInstrPair(const MachineInstr &MI) const
short changeAddrMode_abs_io(const MachineInstr &MI) const
int getMinValue(const MachineInstr &MI) const
bool isValidAutoIncImm(const EVT VT, const int Offset) const
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
unsigned getMemAccessSize(const MachineInstr &MI) const
bool isSignExtendingLoad(const MachineInstr &MI) const
bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const
Symmetrical. See if these two instructions are fit for duplex pair.
bool isFloat(const MachineInstr &MI) const
bool isHVXVec(const MachineInstr &MI) const
bool validateBranchCond(const ArrayRef< MachineOperand > &Cond) const
short changeAddrMode_io_rr(const MachineInstr &MI) const
void immediateExtend(MachineInstr &MI) const
immediateExtend - Changes the instruction in place to one using an immediate extender.
bool expandPostRAPseudo(MachineInstr &MI) const override
This function is called for all pseudo instructions that remain after register allocation.
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const override
Get the base register and byte offset of a load/store instr.
bool isNewValueInst(const MachineInstr &MI) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Decompose the machine operand's target flags into two values - the direct target flag value and any o...
SmallVector< MachineOperand, 4 > Cond
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index.
MachineBasicBlock MachineBasicBlock::iterator MBBI
unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI, const TargetSubtargetInfo *STI=nullptr) const override
Measure the specified inline asm to determine an approximation of its length.
bool isExtendable(const MachineInstr &MI) const
bool getBundleNoShuf(const MachineInstr &MIB) const
short changeAddrMode_ur_rr(short Opc) const
bool isRestrictNoSlot1Store(const MachineInstr &MI) const
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
short getNonExtOpcode(const MachineInstr &MI) const
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
TargetInstrInfo overrides.
short changeAddrMode_rr_ur(const MachineInstr &MI) const
unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const
bool isTC4x(const MachineInstr &MI) const
bool getInvertedPredSense(SmallVectorImpl< MachineOperand > &Cond) const
TargetSubtargetInfo - Generic base class for all target subtargets.
Wrapper class representing virtual and physical registers.
bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const
bool isComplex(const MachineInstr &MI) const
unsigned reversePrediction(unsigned Opcode) const
int getDuplexOpcode(const MachineInstr &MI, bool ForBigCore=true) const
bool isConstExtended(const MachineInstr &MI) const
int getDotNewPredJumpOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const
void translateInstrsForDup(MachineFunction &MF, bool ToBigInstrs=true) const
Instructions::iterator instr_iterator
MachineBasicBlock::instr_iterator expandVGatherPseudo(MachineInstr &MI) const
bool isValidOffset(unsigned Opcode, int Offset, const TargetRegisterInfo *TRI, bool Extend=true) const
bool isPredicatedNew(const MachineInstr &MI) const
void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const
short changeAddrMode_rr_io(short Opc) const
bool isPredicateLate(unsigned Opcode) const
unsigned getCExtOpNum(const MachineInstr &MI) const
bool isVecAcc(const MachineInstr &MI) const
bool isAccumulator(const MachineInstr &MI) const
bool isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const
short changeAddrMode_rr_ur(short Opc) const
unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData, const MachineInstr &MI) const
bool isPredicatedTrue(const MachineInstr &MI) const
bool isTC1(const MachineInstr &MI) const
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Reverses the branch condition of the specified condition list, returning false on success and true if...
bool getPredReg(ArrayRef< MachineOperand > Cond, unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const
bool addLatencyToSchedule(const MachineInstr &MI1, const MachineInstr &MI2) const
bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override
Returns true if the first specified predicate subsumes the second, e.g.
void changeDuplexOpcode(MachineBasicBlock::instr_iterator MII, bool ToBigInstrs) const
bool isExpr(unsigned OpType) const
MachineInstrBuilder MachineInstrBuilder & DefMI
bool isLateResultInstr(const MachineInstr &MI) const
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Return true if it's profitable to predicate instructions with accumulated instruction latency of "Num...
bool hasNonExtEquivalent(const MachineInstr &MI) const
bool isToBeScheduledASAP(const MachineInstr &MI1, const MachineInstr &MI2) const
bool canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const
Can these instructions execute at the same time in a bundle.
short changeAddrMode_rr_io(const MachineInstr &MI) const
int getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
getOperandLatency - Compute and return the use operand latency of a given pair of def and use.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool isPredictedTaken(unsigned Opcode) const
bool isDeallocRet(const MachineInstr &MI) const
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
bool isCompoundBranchInstr(const MachineInstr &MI) const
bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has store to stack slots.
bool isExtended(const MachineInstr &MI) const
bool getIncrementValue(const MachineInstr &MI, int &Value) const override
If the instruction is an increment of a constant value, return the amount.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
unsigned getInvertedPredicatedOpcode(const int Opc) const
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Cond) const override
Convert the instruction into a predicated instruction.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Emit instructions to copy a pair of physical registers.
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override
Create machine specific model for scheduling.
LLVM Value Representation.
Itinerary data supplied by a subtarget to be used by a target.
bool producesStall(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const
bool mayBeCurLoad(const MachineInstr &MI) const
bool isDotCurInst(const MachineInstr &MI) const
Wrapper class representing physical registers. Should be passed by value.