LLVM  16.0.0git
Macros | Functions | Variables
RISCVRedundantCopyElimination.cpp File Reference
#include "RISCV.h"
#include "RISCVInstrInfo.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Support/Debug.h"
Include dependency graph for RISCVRedundantCopyElimination.cpp:

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "riscv-copyelim"
 

Functions

 STATISTIC (NumCopiesRemoved, "Number of copies removed.")
 
 INITIALIZE_PASS (RISCVRedundantCopyElimination, "riscv-copyelim", "RISCV redundant copy elimination pass", false, false) static bool guaranteesZeroRegInBlock(MachineBasicBlock &MBB
 
 assert (TBB !=nullptr &&"Expected branch target basic block")
 
 if (CC==RISCVCC::COND_EQ &&Cond[2].getReg()==RISCV::X0 &&TBB==&MBB) return true
 

Variables

const SmallVectorImpl< MachineOperand > & Cond
 
const SmallVectorImpl< MachineOperand > MachineBasicBlockTBB
 
auto CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm())
 
return false
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "riscv-copyelim"

Definition at line 35 of file RISCVRedundantCopyElimination.cpp.

Function Documentation

◆ assert()

assert ( TBB = nullptr &&"Expected branch target basic block")

◆ if()

if ( CC  = =RISCVCC::COND_EQ &&Cond[2].getReg()==RISCV::X0 &&TBB==&MBB)

◆ INITIALIZE_PASS()

INITIALIZE_PASS ( RISCVRedundantCopyElimination  ,
"riscv-copyelim"  ,
"RISCV redundant copy elimination pass ,
false  ,
false   
) &

◆ STATISTIC()

STATISTIC ( NumCopiesRemoved  ,
"Number of copies removed."   
)

Variable Documentation

◆ CC

auto CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm())

Definition at line 79 of file RISCVRedundantCopyElimination.cpp.

Referenced by llvm::AMDGPUMachineFunction::AMDGPUMachineFunction(), llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), llvm::DwarfUnit::applySubprogramAttributes(), ARCCondCodeToString(), areCallingConvEligibleForTCO_64SVR4(), llvm::ARMCondCodeFromString(), llvm::ARMCondCodeToString(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::ARMVectorCondCodeFromString(), llvm::ARMVPTPredToString(), canGuaranteeTCO(), CanInvertMVEVCMP(), carryFlagToValue(), llvm::R600TargetLowering::CCAssignFnForCall(), llvm::AMDGPUCallLowering::CCAssignFnForCall(), llvm::AMDGPUTargetLowering::CCAssignFnForCall(), llvm::AArch64TargetLowering::CCAssignFnForCall(), llvm::ARMTargetLowering::CCAssignFnForCall(), llvm::PPCTargetLowering::ccAssignFnForCall(), llvm::AMDGPUCallLowering::CCAssignFnForReturn(), llvm::AMDGPUTargetLowering::CCAssignFnForReturn(), llvm::AArch64TargetLowering::CCAssignFnForReturn(), llvm::ARMTargetLowering::CCAssignFnForReturn(), CCMaskForCondCode(), changeFPCCToAArch64CC(), changeFPCCToANDAArch64CC(), changeFPCCToORAArch64CC(), changeIntCCToAArch64CC(), changeVectorFPCCToAArch64CC(), checkBoolTestSetCCCombine(), checkCCKill(), checkVSELConstraints(), classifySecond(), llvm::X86::classifySecondCondCodeInMacroFusion(), classifySecondInstInMacroFusion(), llvm::DISubroutineType::cloneWithCC(), combine_CC(), combineAddOrSubToADCOrSBB(), combineBrCond(), combineCMov(), combineExtSetcc(), llvm::AMDGPUTargetLowering::combineFMinMaxLegacy(), combineM68kBrCond(), combineM68kSetCC(), combineMinNumMaxNum(), combinePTESTCC(), llvm::VETargetLowering::combineSelect(), combineSelect(), llvm::VETargetLowering::combineSelectCC(), combineSelectOfTwoConstants(), combineSetCC(), combineSetCCAtomicArith(), combineSetCCCCR(), combineSetCCEFLAGS(), combineSetCCMOVMSK(), combineSubABS(), combineVectorSizedSetCCEquality(), combineVSelectWithAllOnesOrZeros(), combineX86SetCC(), llvm::ARMBaseInstrInfo::commuteInstructionImpl(), llvm::RISCVInstrInfo::commuteInstructionImpl(), llvm::X86InstrInfo::commuteInstructionImpl(), computeBytesPoppedByCalleeForSRet(), computeCalleeSaveRegisterPairs(), condCodeToFCC(), llvm::DwarfUnit::constructTypeDIE(), llvm::dwarf::ConventionString(), llvm::SystemZInstrInfo::copyPhysReg(), createCMovFP(), createFPCmp(), llvm::createLibcall(), llvm::ARMBaseInstrInfo::createMIROperandComment(), createPHIsForCMOVsInSinkBB(), llvm::DIBuilder::createSubroutineType(), llvm::CSKYTargetLowering::CSKYTargetLowering(), decideComp(), EmitAVX512Test(), EmitCMP(), emitComparison(), emitConditionalComparison(), emitConjunctionRec(), llvm::BPFTargetLowering::EmitInstrWithCustomInserter(), llvm::AVRTargetLowering::EmitInstrWithCustomInserter(), emitSelectPseudo(), EmitVectorComparison(), llvm::examineCFlagsUse(), llvm::SparcTargetLowering::expandSelectCC(), ExtendUsesToFormExtLoad(), foldADCToCINC(), foldAddSubBoolOfMaskedVal(), foldCSELOfCSEL(), foldCSELofCTTZ(), foldExtendedSignBitTest(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), foldOverflowCheck(), llvm::ConstantFolder::FoldSelect(), llvm::TargetFolder::FoldSelect(), foldSelectOfConstantsUsingSra(), foldVSelectToSignBitSplatMask(), FPCCToARMCC(), FPCondCCodeToFCC(), llvm::fpCondCode2Fcc(), generateComparison(), getAArch64Cmp(), getAArch64XALUOOp(), llvm::Constant::getAggregateElement(), getAssignFnsForCC(), getBitTestCondition(), llvm::RISCVInstrInfo::getBrCond(), llvm::AVRInstrInfo::getBrCond(), llvm::MipsABIInfo::GetCalleeAllocdArgSizeInBytes(), llvm::SIRegisterInfo::getCalleeSavedRegs(), llvm::X86RegisterInfo::getCalleeSavedRegs(), llvm::RISCVRegisterInfo::getCallPreservedMask(), llvm::VERegisterInfo::getCallPreservedMask(), llvm::AArch64RegisterInfo::getCallPreservedMask(), llvm::SIRegisterInfo::getCallPreservedMask(), llvm::PPCRegisterInfo::getCallPreservedMask(), llvm::X86RegisterInfo::getCallPreservedMask(), llvm::SystemZELFRegisters::getCallPreservedMask(), llvm::ARMBaseRegisterInfo::getCallPreservedMask(), llvm::SystemZRegisterInfo::getCallPreservedMask(), llvm::DISubroutineType::getCC(), getCCForBRcc(), getCmpToAddCondition(), llvm::M68k::GetCondBranchFromCond(), GetCondBranchFromCond(), llvm::TargetLoweringBase::getCondCodeAction(), getCopyFromParts(), getCRIdxForSetCC(), getCSETCondCode(), llvm::AArch64RegisterInfo::getDarwinCallPreservedMask(), llvm::AMDGPUSubtarget::getDefaultFlatWorkGroupSize(), llvm::AMDGPU::SIModeRegisterDefaults::getDefaultForCallingConv(), llvm::getFCmpCode(), llvm::getFCmpCodeWithoutNaN(), llvm::MDNodeKeyImpl< DISubroutineType >::getHashValue(), getIntrinsicCmp(), llvm::Mangler::getNameWithPrefix(), llvm::SITargetLowering::getNumRegistersForCallingConv(), llvm::RISCVTargetLowering::getNumRegistersForCallingConv(), llvm::X86TargetLowering::getNumRegistersForCallingConv(), llvm::RISCVCC::getOppositeBranchCondition(), llvm::M68k::GetOppositeBranchCondition(), llvm::X86::GetOppositeBranchCondition(), GetOppositeBranchCondition(), getOppositeBranchCondition(), llvm::ARMCC::getOppositeCondition(), llvm::AVRInstrInfo::getOppositeCondition(), getOppositeCondition(), llvm::SIProgramInfo::getPGMRSrc1(), getPredicateForSetCC(), getPTest(), getPTXCmpMode(), llvm::SITargetLowering::getRegisterTypeForCallingConv(), llvm::RISCVTargetLowering::getRegisterTypeForCallingConv(), llvm::X86TargetLowering::getRegisterTypeForCallingConv(), llvm::M68kRegisterInfo::getReservedRegs(), llvm::X86RegisterInfo::getReservedRegs(), llvm::GetReturnInfo(), llvm::RISCVDAGToDAGISel::getRISCVCCForIntCC(), getRsrc1Reg(), getScratchSizeKey(), getStageName(), llvm::ARMCC::getSwappedCondition(), getSwappedCondition(), llvm::AArch64RegisterInfo::getThisReturnPreservedMask(), llvm::ARMBaseRegisterInfo::getThisReturnPreservedMask(), getUsedNZCV(), getVCmpInst(), getVectorComparison(), getVectorComparisonOrInvert(), getVectorFCMP(), llvm::SITargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::MipsTargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::X86TargetLowering::getVectorTypeBreakdownForCallingConv(), llvm::X86::getVPCMPImmForCond(), llvm::X86::getX86ConditionCode(), getX86SSEConditionCode(), handleMaskRegisterForCallingConv(), hasByteCountSuffix(), hasChangeableCC(), INITIALIZE_PASS(), llvm::SparcInstrInfo::insertBranch(), llvm::RISCVInstrInfo::insertBranch(), llvm::AVRInstrInfo::insertBranch(), llvm::M68kInstrInfo::insertBranch(), llvm::X86InstrInfo::insertBranch(), llvm::AArch64InstrInfo::insertSelect(), llvm::GCNTTIImpl::instCombineIntrinsic(), IntCCToARMCC(), llvm::intCCToAVRCC(), IntCondCCodeToICC(), llvm::intCondCode2Icc(), invertFPCondCodeUser(), llvm::AMDGPU::isArgPassedInSGPR(), llvm::X86RegisterInfo::isArgumentRegister(), llvm::AArch64RegisterInfo::isArgumentRegister(), isCallingConvCCompatible(), llvm::AArch64Subtarget::isCallingConvWin64(), llvm::X86Subtarget::isCallingConvWin64(), isCMN(), IsCMPZCSINC(), llvm::TargetLoweringBase::isCondCodeLegal(), llvm::TargetLoweringBase::isCondCodeLegalOrCustom(), isConditionalZeroOrAllOnes(), llvm::AMDGPU::isEntryFunctionCC(), isEquivalentMaskless(), isGTorGE(), IsIntegerCC(), llvm::isIntVECondCode(), llvm::AMDGPU::isKernel(), llvm::MDNodeKeyImpl< DISubroutineType >::isKeyOf(), isLegalDSPCondCode(), isLowerSaturate(), isLowerSaturatingConditional(), isLTorLE(), llvm::AMDGPU::isModuleEntryFunctionCC(), isSaturatingMinMax(), isValidMVECond(), isValueTypeInRegForCC(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), llvm::LPCC::lanaiCondCodeToString(), llvm::TargetLowering::LegalizeSetCCCondCode(), LLVMSetFunctionCallConv(), LLVMSetInstructionCallConv(), LookThroughSetCC(), lower1BitShuffle(), LowerAndToBT(), LowerAndToBTST(), llvm::X86TargetLowering::LowerAsmOutputForConstraint(), llvm::LanaiTargetLowering::LowerBR_CC(), llvm::MSP430TargetLowering::LowerBR_CC(), LowerBR_CC(), LowerBRCOND(), llvm::TargetLowering::lowerCmpEqZeroToCtlzSrl(), llvm::AMDGPUCallLowering::lowerFormalArguments(), LowerINTRINSIC_W_CHAIN(), LowerIntVSETCC_AVX512(), llvm::RISCVTargetLowering::LowerOperation(), llvm::AArch64CallLowering::lowerReturn(), llvm::AMDGPUCallLowering::lowerReturn(), llvm::LanaiTargetLowering::LowerSELECT_CC(), llvm::MSP430TargetLowering::LowerSELECT_CC(), LowerSELECT_CC(), llvm::LanaiTargetLowering::LowerSETCC(), llvm::MSP430TargetLowering::LowerSETCC(), llvm::HexagonTargetLowering::LowerSETCC(), LowerTruncateToBTST(), LowerVectorAllZero(), lowerVectorFCMP(), LowerVSETCC(), LowerXALUO(), llvm::X86TargetLowering::markLibCallAttributes(), markRegisterParameterAttributes(), MatchVectorAllZeroTest(), mayTailCallThisCC(), mayUseCarryFlag(), mayUseP9Setb(), llvm::Mips::MipsFCCToString(), needCarryOrOverflowFlag(), NegateCC(), onlyZeroFlagUsed(), llvm::operator<<(), llvm::LanaiInstrInfo::optimizeCompareInstr(), llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::AArch64InstrInfo::optimizeCondBranch(), outputCallingConvention(), overflowFlagToValue(), parseCond(), parseCondBranch(), llvm::LLParser::parseMDField(), llvm::ARMTargetLowering::PerformBRCONDCombine(), performBRCONDCombine(), llvm::ARMTargetLowering::PerformCMOVCombine(), llvm::ARMTargetLowering::PerformCMOVToBFICombine(), performCONDCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::PPCTargetLowering::PerformDAGCombine(), PerformHWLoopCombine(), PerformMinMaxFpToSatCombine(), llvm::AMDGPUTargetLowering::performSelectCombine(), performSELECTCombine(), PerformSELECTCombine(), performSunpkloCombine(), PerformUMinFpToSatCombine(), PerformVSetCCToVCTPCombine(), PerformXORCombine(), llvm::SystemZInstrInfo::PredicateInstruction(), llvm::SystemZInstrInfo::prepareCompareSwapOperands(), llvm::LanaiInstPrinter::printCCOperand(), llvm::SparcInstPrinter::printCCOperand(), llvm::VEInstPrinter::printCCOperand(), llvm::AArch64InstPrinter::printCondCode(), llvm::AArch64InstPrinter::printInverseCondCode(), llvm::ARMInstPrinter::printMandatoryInvertedPredicateOperand(), llvm::ARMInstPrinter::printMandatoryPredicateOperand(), llvm::LanaiInstPrinter::printPredicateOperand(), llvm::ARMInstPrinter::printPredicateOperand(), llvm::ARMInstPrinter::printVPTPredicateOperand(), processSwitches(), llvm::RegsForValue::RegsForValue(), llvm::X86InstrInfo::replaceBranchWithTailCall(), llvm::Thumb2InstrInfo::ReplaceTailWithBranchTo(), llvm::MSP430InstrInfo::reverseBranchCondition(), llvm::VEInstrInfo::reverseBranchCondition(), llvm::SparcInstrInfo::reverseBranchCondition(), llvm::AVRInstrInfo::reverseBranchCondition(), llvm::RISCVInstrInfo::reverseBranchCondition(), llvm::ARMBaseInstrInfo::reverseBranchCondition(), llvm::AArch64InstrInfo::reverseBranchCondition(), llvm::X86InstrInfo::reverseBranchCondition(), llvm::LoopInterchangePass::run(), llvm::LoopCachePrinterPass::run(), safeWithoutCompWithNull(), SearchLoopIntrinsic(), llvm::FastISel::selectPatchpoint(), llvm::FastISel::selectStackmap(), llvm::FunctionLoweringInfo::set(), llvm::FastISel::CallLoweringInfo::setCallee(), llvm::TargetLowering::CallLoweringInfo::setCallee(), llvm::Function::setCallingConv(), llvm::CallBase::setCallingConv(), llvm::TargetLoweringBase::setCmpLibcallCC(), llvm::TargetLoweringBase::setCondCodeAction(), llvm::AMDGPUPALMetadata::setEntryPoint(), llvm::TargetLoweringBase::setLibcallCallingConv(), llvm::TargetLowering::CallLoweringInfo::setLibCallee(), llvm::AMDGPUPALMetadata::setNumUsedAgprs(), llvm::AMDGPUPALMetadata::setNumUsedSgprs(), llvm::AMDGPUPALMetadata::setNumUsedVgprs(), llvm::AMDGPUPALMetadata::setRsrc1(), llvm::AMDGPUPALMetadata::setRsrc2(), llvm::AMDGPUPALMetadata::setScratchSize(), llvm::AMDGPUPALMetadata::setWave32(), shouldConvertSelectOfConstantsToMath(), llvm::SelectionDAGBuilder::ShouldEmitAsBranches(), shouldGuaranteeTCO(), llvm::RISCVTargetLowering::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(), llvm::TargetLoweringBase::shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(), 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◆ Cond

Definition at line 75 of file RISCVRedundantCopyElimination.cpp.

◆ false

return false

Definition at line 84 of file RISCVRedundantCopyElimination.cpp.

◆ TBB

Initial value:
{
assert(Cond.size() == 3 && "Unexpected number of operands")

Definition at line 76 of file RISCVRedundantCopyElimination.cpp.

Referenced by llvm::SPIRVInstrInfo::analyzeBranch(), llvm::BPFInstrInfo::analyzeBranch(), llvm::XCoreInstrInfo::analyzeBranch(), llvm::LoongArchInstrInfo::analyzeBranch(), llvm::ARCInstrInfo::analyzeBranch(), llvm::WebAssemblyInstrInfo::analyzeBranch(), llvm::NVPTXInstrInfo::analyzeBranch(), llvm::MSP430InstrInfo::analyzeBranch(), llvm::MipsInstrInfo::analyzeBranch(), llvm::CSKYInstrInfo::analyzeBranch(), llvm::VEInstrInfo::analyzeBranch(), llvm::SparcInstrInfo::analyzeBranch(), llvm::RISCVInstrInfo::analyzeBranch(), llvm::AVRInstrInfo::analyzeBranch(), llvm::HexagonInstrInfo::analyzeBranch(), llvm::ARMBaseInstrInfo::analyzeBranch(), llvm::R600InstrInfo::analyzeBranch(), llvm::AArch64InstrInfo::analyzeBranch(), llvm::SystemZInstrInfo::analyzeBranch(), llvm::M68kInstrInfo::analyzeBranch(), llvm::SIInstrInfo::analyzeBranch(), llvm::X86InstrInfo::analyzeBranch(), llvm::PPCInstrInfo::analyzeBranch(), llvm::M68kInstrInfo::AnalyzeBranchImpl(), llvm::SIInstrInfo::analyzeBranchImpl(), llvm::MachineBasicBlock::canSplitCriticalEdge(), llvm::PeelingModuloScheduleExpander::CreateLCSSAExitingBlock(), llvm::SelectionDAGBuilder::EmitBranchForMergedCondition(), llvm::SelectionDAGBuilder::FindMergedConditions(), FixTail(), for(), getBBFallenThrough(), getBranchHint(), llvm::MachineBasicBlock::getFallThrough(), getFallThroughMBB(), INITIALIZE_PASS(), llvm::BPFInstrInfo::insertBranch(), llvm::XCoreInstrInfo::insertBranch(), llvm::ARCInstrInfo::insertBranch(), llvm::CSKYInstrInfo::insertBranch(), llvm::WebAssemblyInstrInfo::insertBranch(), llvm::NVPTXInstrInfo::insertBranch(), llvm::LoongArchInstrInfo::insertBranch(), llvm::MSP430InstrInfo::insertBranch(), llvm::MipsInstrInfo::insertBranch(), llvm::VEInstrInfo::insertBranch(), llvm::SparcInstrInfo::insertBranch(), llvm::RISCVInstrInfo::insertBranch(), llvm::AVRInstrInfo::insertBranch(), llvm::HexagonInstrInfo::insertBranch(), llvm::ARMBaseInstrInfo::insertBranch(), llvm::R600InstrInfo::insertBranch(), llvm::AArch64InstrInfo::insertBranch(), llvm::SystemZInstrInfo::insertBranch(), llvm::M68kInstrInfo::insertBranch(), llvm::SIInstrInfo::insertBranch(), llvm::X86InstrInfo::insertBranch(), llvm::PPCInstrInfo::insertBranch(), llvm::ARMBaseInstrInfo::isProfitableToIfCvt(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::PeelSingleBlockLoop(), and llvm::MachineBasicBlock::updateTerminator().

assert
assert(TBB !=nullptr &&"Expected branch target basic block")
Cond
const SmallVectorImpl< MachineOperand > & Cond
Definition: RISCVRedundantCopyElimination.cpp:75