LLVM  12.0.0git
X86RegisterInfo.cpp
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1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of the TargetRegisterInfo class.
10 // This file is responsible for the frame pointer elimination optimization
11 // on X86.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86RegisterInfo.h"
16 #include "X86FrameLowering.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/STLExtras.h"
27 #include "llvm/IR/Constants.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/Type.h"
34 
35 using namespace llvm;
36 
37 #define GET_REGINFO_TARGET_DESC
38 #include "X86GenRegisterInfo.inc"
39 
40 static cl::opt<bool>
41 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
42  cl::desc("Enable use of a base pointer for complex stack frames"));
43 
45  : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
46  X86_MC::getDwarfRegFlavour(TT, false),
47  X86_MC::getDwarfRegFlavour(TT, true),
48  (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
50 
51  // Cache some information.
52  Is64Bit = TT.isArch64Bit();
53  IsWin64 = Is64Bit && TT.isOSWindows();
54 
55  // Use a callee-saved register as the base pointer. These registers must
56  // not conflict with any ABI requirements. For example, in 32-bit mode PIC
57  // requires GOT in the EBX register before function calls via PLT GOT pointer.
58  if (Is64Bit) {
59  SlotSize = 8;
60  // This matches the simplified 32-bit pointer code in the data layout
61  // computation.
62  // FIXME: Should use the data layout?
63  bool Use64BitReg = TT.getEnvironment() != Triple::GNUX32;
64  StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
65  FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
66  BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
67  } else {
68  SlotSize = 4;
69  StackPtr = X86::ESP;
70  FramePtr = X86::EBP;
71  BasePtr = X86::ESI;
72  }
73 }
74 
75 int
76 X86RegisterInfo::getSEHRegNum(unsigned i) const {
77  return getEncodingValue(i);
78 }
79 
80 const TargetRegisterClass *
82  unsigned Idx) const {
83  // The sub_8bit sub-register index is more constrained in 32-bit mode.
84  // It behaves just like the sub_8bit_hi index.
85  if (!Is64Bit && Idx == X86::sub_8bit)
86  Idx = X86::sub_8bit_hi;
87 
88  // Forward to TableGen's default version.
89  return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
90 }
91 
92 const TargetRegisterClass *
94  const TargetRegisterClass *B,
95  unsigned SubIdx) const {
96  // The sub_8bit sub-register index is more constrained in 32-bit mode.
97  if (!Is64Bit && SubIdx == X86::sub_8bit) {
98  A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
99  if (!A)
100  return nullptr;
101  }
102  return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
103 }
104 
105 const TargetRegisterClass *
107  const MachineFunction &MF) const {
108  // Don't allow super-classes of GR8_NOREX. This class is only used after
109  // extracting sub_8bit_hi sub-registers. The H sub-registers cannot be copied
110  // to the full GR8 register class in 64-bit mode, so we cannot allow the
111  // reigster class inflation.
112  //
113  // The GR8_NOREX class is always used in a way that won't be constrained to a
114  // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
115  // full GR8 class.
116  if (RC == &X86::GR8_NOREXRegClass)
117  return RC;
118 
119  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
120 
121  const TargetRegisterClass *Super = RC;
123  do {
124  switch (Super->getID()) {
125  case X86::FR32RegClassID:
126  case X86::FR64RegClassID:
127  // If AVX-512 isn't supported we should only inflate to these classes.
128  if (!Subtarget.hasAVX512() &&
129  getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
130  return Super;
131  break;
132  case X86::VR128RegClassID:
133  case X86::VR256RegClassID:
134  // If VLX isn't supported we should only inflate to these classes.
135  if (!Subtarget.hasVLX() &&
136  getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
137  return Super;
138  break;
139  case X86::VR128XRegClassID:
140  case X86::VR256XRegClassID:
141  // If VLX isn't support we shouldn't inflate to these classes.
142  if (Subtarget.hasVLX() &&
143  getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
144  return Super;
145  break;
146  case X86::FR32XRegClassID:
147  case X86::FR64XRegClassID:
148  // If AVX-512 isn't support we shouldn't inflate to these classes.
149  if (Subtarget.hasAVX512() &&
150  getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
151  return Super;
152  break;
153  case X86::GR8RegClassID:
154  case X86::GR16RegClassID:
155  case X86::GR32RegClassID:
156  case X86::GR64RegClassID:
157  case X86::RFP32RegClassID:
158  case X86::RFP64RegClassID:
159  case X86::RFP80RegClassID:
160  case X86::VR512_0_15RegClassID:
161  case X86::VR512RegClassID:
162  // Don't return a super-class that would shrink the spill size.
163  // That can happen with the vector and float classes.
164  if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
165  return Super;
166  }
167  Super = *I++;
168  } while (Super);
169  return RC;
170 }
171 
172 const TargetRegisterClass *
174  unsigned Kind) const {
175  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
176  switch (Kind) {
177  default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
178  case 0: // Normal GPRs.
179  if (Subtarget.isTarget64BitLP64())
180  return &X86::GR64RegClass;
181  // If the target is 64bit but we have been told to use 32bit addresses,
182  // we can still use 64-bit register as long as we know the high bits
183  // are zeros.
184  // Reflect that in the returned register class.
185  if (Is64Bit) {
186  // When the target also allows 64-bit frame pointer and we do have a
187  // frame, this is fine to use it for the address accesses as well.
188  const X86FrameLowering *TFI = getFrameLowering(MF);
189  return TFI->hasFP(MF) && TFI->Uses64BitFramePtr
190  ? &X86::LOW32_ADDR_ACCESS_RBPRegClass
191  : &X86::LOW32_ADDR_ACCESSRegClass;
192  }
193  return &X86::GR32RegClass;
194  case 1: // Normal GPRs except the stack pointer (for encoding reasons).
195  if (Subtarget.isTarget64BitLP64())
196  return &X86::GR64_NOSPRegClass;
197  // NOSP does not contain RIP, so no special case here.
198  return &X86::GR32_NOSPRegClass;
199  case 2: // NOREX GPRs.
200  if (Subtarget.isTarget64BitLP64())
201  return &X86::GR64_NOREXRegClass;
202  return &X86::GR32_NOREXRegClass;
203  case 3: // NOREX GPRs except the stack pointer (for encoding reasons).
204  if (Subtarget.isTarget64BitLP64())
205  return &X86::GR64_NOREX_NOSPRegClass;
206  // NOSP does not contain RIP, so no special case here.
207  return &X86::GR32_NOREX_NOSPRegClass;
208  case 4: // Available for tailcall (not callee-saved GPRs).
209  return getGPRsForTailCall(MF);
210  }
211 }
212 
214  unsigned DefSubReg,
215  const TargetRegisterClass *SrcRC,
216  unsigned SrcSubReg) const {
217  // Prevent rewriting a copy where the destination size is larger than the
218  // input size. See PR41619.
219  // FIXME: Should this be factored into the base implementation somehow.
220  if (DefRC->hasSuperClassEq(&X86::GR64RegClass) && DefSubReg == 0 &&
221  SrcRC->hasSuperClassEq(&X86::GR64RegClass) && SrcSubReg == X86::sub_32bit)
222  return false;
223 
224  return TargetRegisterInfo::shouldRewriteCopySrc(DefRC, DefSubReg,
225  SrcRC, SrcSubReg);
226 }
227 
228 const TargetRegisterClass *
230  const Function &F = MF.getFunction();
231  if (IsWin64 || (F.getCallingConv() == CallingConv::Win64))
232  return &X86::GR64_TCW64RegClass;
233  else if (Is64Bit)
234  return &X86::GR64_TCRegClass;
235 
236  bool hasHipeCC = (F.getCallingConv() == CallingConv::HiPE);
237  if (hasHipeCC)
238  return &X86::GR32RegClass;
239  return &X86::GR32_TCRegClass;
240 }
241 
242 const TargetRegisterClass *
244  if (RC == &X86::CCRRegClass) {
245  if (Is64Bit)
246  return &X86::GR64RegClass;
247  else
248  return &X86::GR32RegClass;
249  }
250  return RC;
251 }
252 
253 unsigned
255  MachineFunction &MF) const {
256  const X86FrameLowering *TFI = getFrameLowering(MF);
257 
258  unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
259  switch (RC->getID()) {
260  default:
261  return 0;
262  case X86::GR32RegClassID:
263  return 4 - FPDiff;
264  case X86::GR64RegClassID:
265  return 12 - FPDiff;
266  case X86::VR128RegClassID:
267  return Is64Bit ? 10 : 4;
268  case X86::VR64RegClassID:
269  return 4;
270  }
271 }
272 
273 const MCPhysReg *
275  assert(MF && "MachineFunction required");
276 
277  const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>();
278  const Function &F = MF->getFunction();
279  bool HasSSE = Subtarget.hasSSE1();
280  bool HasAVX = Subtarget.hasAVX();
281  bool HasAVX512 = Subtarget.hasAVX512();
282  bool CallsEHReturn = MF->callsEHReturn();
283 
284  CallingConv::ID CC = F.getCallingConv();
285 
286  // If attribute NoCallerSavedRegisters exists then we set X86_INTR calling
287  // convention because it has the CSR list.
288  if (MF->getFunction().hasFnAttribute("no_caller_saved_registers"))
290 
291  switch (CC) {
292  case CallingConv::GHC:
293  case CallingConv::HiPE:
294  return CSR_NoRegs_SaveList;
295  case CallingConv::AnyReg:
296  if (HasAVX)
297  return CSR_64_AllRegs_AVX_SaveList;
298  return CSR_64_AllRegs_SaveList;
300  return CSR_64_RT_MostRegs_SaveList;
302  if (HasAVX)
303  return CSR_64_RT_AllRegs_AVX_SaveList;
304  return CSR_64_RT_AllRegs_SaveList;
306  if (Is64Bit)
307  return MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR() ?
308  CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList;
309  break;
311  if (HasAVX512 && IsWin64)
312  return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
313  if (HasAVX512 && Is64Bit)
314  return CSR_64_Intel_OCL_BI_AVX512_SaveList;
315  if (HasAVX && IsWin64)
316  return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
317  if (HasAVX && Is64Bit)
318  return CSR_64_Intel_OCL_BI_AVX_SaveList;
319  if (!HasAVX && !IsWin64 && Is64Bit)
320  return CSR_64_Intel_OCL_BI_SaveList;
321  break;
322  }
323  case CallingConv::HHVM:
324  return CSR_64_HHVM_SaveList;
326  if (Is64Bit) {
327  if (IsWin64) {
328  return (HasSSE ? CSR_Win64_RegCall_SaveList :
329  CSR_Win64_RegCall_NoSSE_SaveList);
330  } else {
331  return (HasSSE ? CSR_SysV64_RegCall_SaveList :
332  CSR_SysV64_RegCall_NoSSE_SaveList);
333  }
334  } else {
335  return (HasSSE ? CSR_32_RegCall_SaveList :
336  CSR_32_RegCall_NoSSE_SaveList);
337  }
339  assert(!Is64Bit && "CFGuard check mechanism only used on 32-bit X86");
340  return (HasSSE ? CSR_Win32_CFGuard_Check_SaveList
341  : CSR_Win32_CFGuard_Check_NoSSE_SaveList);
342  case CallingConv::Cold:
343  if (Is64Bit)
344  return CSR_64_MostRegs_SaveList;
345  break;
346  case CallingConv::Win64:
347  if (!HasSSE)
348  return CSR_Win64_NoSSE_SaveList;
349  return CSR_Win64_SaveList;
351  if (CallsEHReturn)
352  return CSR_64EHRet_SaveList;
353  return CSR_64_SaveList;
355  if (Is64Bit) {
356  if (HasAVX512)
357  return CSR_64_AllRegs_AVX512_SaveList;
358  if (HasAVX)
359  return CSR_64_AllRegs_AVX_SaveList;
360  if (HasSSE)
361  return CSR_64_AllRegs_SaveList;
362  return CSR_64_AllRegs_NoSSE_SaveList;
363  } else {
364  if (HasAVX512)
365  return CSR_32_AllRegs_AVX512_SaveList;
366  if (HasAVX)
367  return CSR_32_AllRegs_AVX_SaveList;
368  if (HasSSE)
369  return CSR_32_AllRegs_SSE_SaveList;
370  return CSR_32_AllRegs_SaveList;
371  }
372  default:
373  break;
374  }
375 
376  if (Is64Bit) {
377  bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() &&
378  F.getAttributes().hasAttrSomewhere(Attribute::SwiftError);
379  if (IsSwiftCC)
380  return IsWin64 ? CSR_Win64_SwiftError_SaveList
381  : CSR_64_SwiftError_SaveList;
382 
383  if (IsWin64)
384  return HasSSE ? CSR_Win64_SaveList : CSR_Win64_NoSSE_SaveList;
385  if (CallsEHReturn)
386  return CSR_64EHRet_SaveList;
387  return CSR_64_SaveList;
388  }
389 
390  return CallsEHReturn ? CSR_32EHRet_SaveList : CSR_32_SaveList;
391 }
392 
394  const MachineFunction *MF) const {
395  assert(MF && "Invalid MachineFunction pointer.");
397  MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR())
398  return CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList;
399  return nullptr;
400 }
401 
402 const uint32_t *
404  CallingConv::ID CC) const {
405  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
406  bool HasSSE = Subtarget.hasSSE1();
407  bool HasAVX = Subtarget.hasAVX();
408  bool HasAVX512 = Subtarget.hasAVX512();
409 
410  switch (CC) {
411  case CallingConv::GHC:
412  case CallingConv::HiPE:
413  return CSR_NoRegs_RegMask;
414  case CallingConv::AnyReg:
415  if (HasAVX)
416  return CSR_64_AllRegs_AVX_RegMask;
417  return CSR_64_AllRegs_RegMask;
419  return CSR_64_RT_MostRegs_RegMask;
421  if (HasAVX)
422  return CSR_64_RT_AllRegs_AVX_RegMask;
423  return CSR_64_RT_AllRegs_RegMask;
425  if (Is64Bit)
426  return CSR_64_TLS_Darwin_RegMask;
427  break;
429  if (HasAVX512 && IsWin64)
430  return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
431  if (HasAVX512 && Is64Bit)
432  return CSR_64_Intel_OCL_BI_AVX512_RegMask;
433  if (HasAVX && IsWin64)
434  return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
435  if (HasAVX && Is64Bit)
436  return CSR_64_Intel_OCL_BI_AVX_RegMask;
437  if (!HasAVX && !IsWin64 && Is64Bit)
438  return CSR_64_Intel_OCL_BI_RegMask;
439  break;
440  }
441  case CallingConv::HHVM:
442  return CSR_64_HHVM_RegMask;
444  if (Is64Bit) {
445  if (IsWin64) {
446  return (HasSSE ? CSR_Win64_RegCall_RegMask :
447  CSR_Win64_RegCall_NoSSE_RegMask);
448  } else {
449  return (HasSSE ? CSR_SysV64_RegCall_RegMask :
450  CSR_SysV64_RegCall_NoSSE_RegMask);
451  }
452  } else {
453  return (HasSSE ? CSR_32_RegCall_RegMask :
454  CSR_32_RegCall_NoSSE_RegMask);
455  }
457  assert(!Is64Bit && "CFGuard check mechanism only used on 32-bit X86");
458  return (HasSSE ? CSR_Win32_CFGuard_Check_RegMask
459  : CSR_Win32_CFGuard_Check_NoSSE_RegMask);
460  case CallingConv::Cold:
461  if (Is64Bit)
462  return CSR_64_MostRegs_RegMask;
463  break;
464  case CallingConv::Win64:
465  return CSR_Win64_RegMask;
467  return CSR_64_RegMask;
469  if (Is64Bit) {
470  if (HasAVX512)
471  return CSR_64_AllRegs_AVX512_RegMask;
472  if (HasAVX)
473  return CSR_64_AllRegs_AVX_RegMask;
474  if (HasSSE)
475  return CSR_64_AllRegs_RegMask;
476  return CSR_64_AllRegs_NoSSE_RegMask;
477  } else {
478  if (HasAVX512)
479  return CSR_32_AllRegs_AVX512_RegMask;
480  if (HasAVX)
481  return CSR_32_AllRegs_AVX_RegMask;
482  if (HasSSE)
483  return CSR_32_AllRegs_SSE_RegMask;
484  return CSR_32_AllRegs_RegMask;
485  }
486  default:
487  break;
488  }
489 
490  // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
491  // callsEHReturn().
492  if (Is64Bit) {
493  const Function &F = MF.getFunction();
494  bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() &&
495  F.getAttributes().hasAttrSomewhere(Attribute::SwiftError);
496  if (IsSwiftCC)
497  return IsWin64 ? CSR_Win64_SwiftError_RegMask : CSR_64_SwiftError_RegMask;
498  return IsWin64 ? CSR_Win64_RegMask : CSR_64_RegMask;
499  }
500 
501  return CSR_32_RegMask;
502 }
503 
504 const uint32_t*
506  return CSR_NoRegs_RegMask;
507 }
508 
510  return CSR_64_TLS_Darwin_RegMask;
511 }
512 
514  BitVector Reserved(getNumRegs());
515  const X86FrameLowering *TFI = getFrameLowering(MF);
516 
517  // Set the floating point control register as reserved.
518  Reserved.set(X86::FPCW);
519 
520  // Set the floating point status register as reserved.
521  Reserved.set(X86::FPSW);
522 
523  // Set the SIMD floating point control register as reserved.
524  Reserved.set(X86::MXCSR);
525 
526  // Set the stack-pointer register and its aliases as reserved.
527  for (const MCPhysReg &SubReg : subregs_inclusive(X86::RSP))
528  Reserved.set(SubReg);
529 
530  // Set the Shadow Stack Pointer as reserved.
531  Reserved.set(X86::SSP);
532 
533  // Set the instruction pointer register and its aliases as reserved.
534  for (const MCPhysReg &SubReg : subregs_inclusive(X86::RIP))
535  Reserved.set(SubReg);
536 
537  // Set the frame-pointer register and its aliases as reserved if needed.
538  if (TFI->hasFP(MF)) {
539  for (const MCPhysReg &SubReg : subregs_inclusive(X86::RBP))
540  Reserved.set(SubReg);
541  }
542 
543  // Set the base-pointer register and its aliases as reserved if needed.
544  if (hasBasePointer(MF)) {
546  const uint32_t *RegMask = getCallPreservedMask(MF, CC);
549  "Stack realignment in presence of dynamic allocas is not supported with"
550  "this calling convention.");
551 
553  for (const MCPhysReg &SubReg : subregs_inclusive(BasePtr))
554  Reserved.set(SubReg);
555  }
556 
557  // Mark the segment registers as reserved.
558  Reserved.set(X86::CS);
559  Reserved.set(X86::SS);
560  Reserved.set(X86::DS);
561  Reserved.set(X86::ES);
562  Reserved.set(X86::FS);
563  Reserved.set(X86::GS);
564 
565  // Mark the floating point stack registers as reserved.
566  for (unsigned n = 0; n != 8; ++n)
567  Reserved.set(X86::ST0 + n);
568 
569  // Reserve the registers that only exist in 64-bit mode.
570  if (!Is64Bit) {
571  // These 8-bit registers are part of the x86-64 extension even though their
572  // super-registers are old 32-bits.
573  Reserved.set(X86::SIL);
574  Reserved.set(X86::DIL);
575  Reserved.set(X86::BPL);
576  Reserved.set(X86::SPL);
577  Reserved.set(X86::SIH);
578  Reserved.set(X86::DIH);
579  Reserved.set(X86::BPH);
580  Reserved.set(X86::SPH);
581 
582  for (unsigned n = 0; n != 8; ++n) {
583  // R8, R9, ...
584  for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
585  Reserved.set(*AI);
586 
587  // XMM8, XMM9, ...
588  for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
589  Reserved.set(*AI);
590  }
591  }
592  if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) {
593  for (unsigned n = 16; n != 32; ++n) {
594  for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
595  Reserved.set(*AI);
596  }
597  }
598 
599  assert(checkAllSuperRegsMarked(Reserved,
600  {X86::SIL, X86::DIL, X86::BPL, X86::SPL,
601  X86::SIH, X86::DIH, X86::BPH, X86::SPH}));
602  return Reserved;
603 }
604 
606  // Check if the EFLAGS register is marked as live-out. This shouldn't happen,
607  // because the calling convention defines the EFLAGS register as NOT
608  // preserved.
609  //
610  // Unfortunatelly the EFLAGS show up as live-out after branch folding. Adding
611  // an assert to track this and clear the register afterwards to avoid
612  // unnecessary crashes during release builds.
613  assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
614  "EFLAGS are not live-out from a patchpoint.");
615 
616  // Also clean other registers that don't need preserving (IP).
617  for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
618  Mask[Reg / 32] &= ~(1U << (Reg % 32));
619 }
620 
621 //===----------------------------------------------------------------------===//
622 // Stack Frame Processing methods
623 //===----------------------------------------------------------------------===//
624 
625 static bool CantUseSP(const MachineFrameInfo &MFI) {
626  return MFI.hasVarSizedObjects() || MFI.hasOpaqueSPAdjustment();
627 }
628 
631  if (X86FI->hasPreallocatedCall())
632  return true;
633 
634  const MachineFrameInfo &MFI = MF.getFrameInfo();
635 
636  if (!EnableBasePointer)
637  return false;
638 
639  // When we need stack realignment, we can't address the stack from the frame
640  // pointer. When we have dynamic allocas or stack-adjusting inline asm, we
641  // can't address variables from the stack pointer. MS inline asm can
642  // reference locals while also adjusting the stack pointer. When we can't
643  // use both the SP and the FP, we need a separate base pointer register.
644  bool CantUseFP = needsStackRealignment(MF);
645  return CantUseFP && CantUseSP(MFI);
646 }
647 
650  return false;
651 
652  const MachineFrameInfo &MFI = MF.getFrameInfo();
653  const MachineRegisterInfo *MRI = &MF.getRegInfo();
654 
655  // Stack realignment requires a frame pointer. If we already started
656  // register allocation with frame pointer elimination, it is too late now.
657  if (!MRI->canReserveReg(FramePtr))
658  return false;
659 
660  // If a base pointer is necessary. Check that it isn't too late to reserve
661  // it.
662  if (CantUseSP(MFI))
663  return MRI->canReserveReg(BasePtr);
664  return true;
665 }
666 
668  Register Reg, int &FrameIdx) const {
669  // Since X86 defines assignCalleeSavedSpillSlots which always return true
670  // this function neither used nor tested.
671  llvm_unreachable("Unused function on X86. Otherwise need a test case.");
672 }
673 
674 // tryOptimizeLEAtoMOV - helper function that tries to replace a LEA instruction
675 // of the form 'lea (%esp), %ebx' --> 'mov %esp, %ebx'.
676 // TODO: In this case we should be really trying first to entirely eliminate
677 // this instruction which is a plain copy.
679  MachineInstr &MI = *II;
680  unsigned Opc = II->getOpcode();
681  // Check if this is a LEA of the form 'lea (%esp), %ebx'
682  if ((Opc != X86::LEA32r && Opc != X86::LEA64r && Opc != X86::LEA64_32r) ||
683  MI.getOperand(2).getImm() != 1 ||
684  MI.getOperand(3).getReg() != X86::NoRegister ||
685  MI.getOperand(4).getImm() != 0 ||
686  MI.getOperand(5).getReg() != X86::NoRegister)
687  return false;
688  Register BasePtr = MI.getOperand(1).getReg();
689  // In X32 mode, ensure the base-pointer is a 32-bit operand, so the LEA will
690  // be replaced with a 32-bit operand MOV which will zero extend the upper
691  // 32-bits of the super register.
692  if (Opc == X86::LEA64_32r)
693  BasePtr = getX86SubSuperRegister(BasePtr, 32);
694  Register NewDestReg = MI.getOperand(0).getReg();
695  const X86InstrInfo *TII =
696  MI.getParent()->getParent()->getSubtarget<X86Subtarget>().getInstrInfo();
697  TII->copyPhysReg(*MI.getParent(), II, MI.getDebugLoc(), NewDestReg, BasePtr,
698  MI.getOperand(1).isKill());
699  MI.eraseFromParent();
700  return true;
701 }
702 
704  switch (MI.getOpcode()) {
705  case X86::CATCHRET:
706  case X86::CLEANUPRET:
707  return true;
708  default:
709  return false;
710  }
711  llvm_unreachable("impossible");
712 }
713 
714 void
716  int SPAdj, unsigned FIOperandNum,
717  RegScavenger *RS) const {
718  MachineInstr &MI = *II;
720  MachineFunction &MF = *MBB.getParent();
722  bool IsEHFuncletEpilogue = MBBI == MBB.end() ? false
723  : isFuncletReturnInstr(*MBBI);
724  const X86FrameLowering *TFI = getFrameLowering(MF);
725  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
726 
727  // Determine base register and offset.
728  int FIOffset;
729  Register BasePtr;
730  if (MI.isReturn()) {
731  assert((!needsStackRealignment(MF) ||
732  MF.getFrameInfo().isFixedObjectIndex(FrameIndex)) &&
733  "Return instruction can only reference SP relative frame objects");
734  FIOffset = TFI->getFrameIndexReferenceSP(MF, FrameIndex, BasePtr, 0);
735  } else if (TFI->Is64Bit && (MBB.isEHFuncletEntry() || IsEHFuncletEpilogue)) {
736  FIOffset = TFI->getWin64EHFrameIndexRef(MF, FrameIndex, BasePtr);
737  } else {
738  FIOffset = TFI->getFrameIndexReference(MF, FrameIndex, BasePtr);
739  }
740 
741  // LOCAL_ESCAPE uses a single offset, with no register. It only works in the
742  // simple FP case, and doesn't work with stack realignment. On 32-bit, the
743  // offset is from the traditional base pointer location. On 64-bit, the
744  // offset is from the SP at the end of the prologue, not the FP location. This
745  // matches the behavior of llvm.frameaddress.
746  unsigned Opc = MI.getOpcode();
747  if (Opc == TargetOpcode::LOCAL_ESCAPE) {
748  MachineOperand &FI = MI.getOperand(FIOperandNum);
749  FI.ChangeToImmediate(FIOffset);
750  return;
751  }
752 
753  // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
754  // register as source operand, semantic is the same and destination is
755  // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
756  // Don't change BasePtr since it is used later for stack adjustment.
757  Register MachineBasePtr = BasePtr;
758  if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
759  MachineBasePtr = getX86SubSuperRegister(BasePtr, 64);
760 
761  // This must be part of a four operand memory reference. Replace the
762  // FrameIndex with base register. Add an offset to the offset.
763  MI.getOperand(FIOperandNum).ChangeToRegister(MachineBasePtr, false);
764 
765  if (BasePtr == StackPtr)
766  FIOffset += SPAdj;
767 
768  // The frame index format for stackmaps and patchpoints is different from the
769  // X86 format. It only has a FI and an offset.
770  if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
771  assert(BasePtr == FramePtr && "Expected the FP as base register");
772  int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
773  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
774  return;
775  }
776 
777  if (MI.getOperand(FIOperandNum+3).isImm()) {
778  // Offset is a 32-bit integer.
779  int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
780  int Offset = FIOffset + Imm;
781  assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
782  "Requesting 64-bit offset in 32-bit immediate!");
783  if (Offset != 0 || !tryOptimizeLEAtoMOV(II))
784  MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
785  } else {
786  // Offset is symbolic. This is extremely rare.
787  uint64_t Offset = FIOffset +
788  (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
789  MI.getOperand(FIOperandNum + 3).setOffset(Offset);
790  }
791 }
792 
794  const X86FrameLowering *TFI = getFrameLowering(MF);
795  return TFI->hasFP(MF) ? FramePtr : StackPtr;
796 }
797 
798 unsigned
800  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
801  Register FrameReg = getFrameRegister(MF);
802  if (Subtarget.isTarget64BitILP32())
803  FrameReg = getX86SubSuperRegister(FrameReg, 32);
804  return FrameReg;
805 }
806 
807 unsigned
809  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
810  Register StackReg = getStackRegister();
811  if (Subtarget.isTarget64BitILP32())
812  StackReg = getX86SubSuperRegister(StackReg, 32);
813  return StackReg;
814 }
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
bool hasAVX() const
Definition: X86Subtarget.h:618
int getFrameIndexReferenceSP(const MachineFunction &MF, int FI, Register &SPReg, int Adjustment) const
const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const override
getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register ...
bool hasBasePointer(const MachineFunction &MF) const
BitVector & set()
Definition: BitVector.h:398
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
static bool tryOptimizeLEAtoMOV(MachineBasicBlock::iterator II)
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:409
bool hasOpaqueSPAdjustment() const
Returns true if the function contains opaque dynamic stack adjustments.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
const TargetRegisterClass * getGPRsForTailCall(const MachineFunction &MF) const
getGPRsForTailCall - Returns a register class with registers that can be used in forming tail calls...
unsigned Reg
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:330
F(f)
unsigned getPtrSizedFrameRegister(const MachineFunction &MF) const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
unsigned getDwarfRegFlavour(const Triple &TT, bool isEH)
MCRegister getX86SubSuperRegister(MCRegister, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
return AArch64::GPR64RegClass contains(Reg)
Function & getFunction()
Return the LLVM function that this machine code represents.
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
MachineBasicBlock & MBB
int getWin64EHFrameIndexRef(const MachineFunction &MF, int FI, Register &SPReg) const
bool Uses64BitFramePtr
True if the 64-bit frame or stack pointer should be used.
X86RegisterInfo(const Triple &TT)
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Returns a TargetRegisterClass used for pointer values.
CLEANUPRET - Represents a return from a cleanup block funclet.
Definition: ISDOpcodes.h:894
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
const HexagonInstrInfo * TII
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
Definition: CallingConv.h:154
static bool isFuncletReturnInstr(MachineInstr &MI)
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Definition: X86Subtarget.h:598
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
unsigned SubReg
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:456
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
Special calling convention on Windows for calling the Control Guard Check ICall funtion.
Definition: CallingConv.h:87
const TargetRegisterClass *const * sc_iterator
unsigned getID() const
Return the register class ID number.
bool hasVLX() const
Definition: X86Subtarget.h:723
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register...
static cl::opt< bool > EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames"))
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:230
BitVector getReservedRegs(const MachineFunction &MF) const override
getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a ...
bool Is64Bit
Is64Bit implies that x86_64 instructions are available.
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
void ChangeToImmediate(int64_t ImmVal)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value...
unsigned getPtrSizedStackRegister(const MachineFunction &MF) const
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:750
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:532
const X86TargetLowering * getTargetLowering() const override
Definition: X86Subtarget.h:534
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value...
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:434
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Intel_OCL_BI - Calling conventions for Intel OpenCL built-ins.
Definition: CallingConv.h:150
unsigned const MachineRegisterInfo * MRI
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const uint32_t * getNoPreservedMask() const override
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg, int &FrameIdx) const override
Calling convention used by HipHop Virtual Machine (HHVM) to perform calls to and from translation cac...
Definition: CallingConv.h:174
This file contains the declarations for the subclasses of Constant, which represent the different fla...
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
MCRegAliasIterator enumerates all registers aliasing Reg.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
int getSEHRegNum(unsigned i) const
void setOffset(int64_t Offset)
Function Alias Analysis false
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
Register getFrameRegister(const MachineFunction &MF) const override
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:374
void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI)
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:219
MachineOperand class - Representation of each machine instruction operand.
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:318
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
getCalleeSavedRegs - Return a null-terminated list of all of the callee-save registers on this target...
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or...
int64_t getImm() const
bool canReserveReg(MCRegister PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
X86_INTR - x86 hardware interrupt context.
Definition: CallingConv.h:184
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
Definition: X86Subtarget.h:592
Register calling convention used for parameters transfer optimization.
Definition: CallingConv.h:214
bool callsEHReturn() const
const uint32_t * getDarwinTLSCallPreservedMask() const
CATCHRET - Represents a return from a catch block funclet.
Definition: ISDOpcodes.h:890
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:280
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:62
basic Basic Alias true
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1303
bool isEHFuncletEntry() const
Returns true if this is the entry block of an EH funclet.
int64_t getOffset() const
Return the offset from the symbol in this operand.
#define I(x, y, z)
Definition: MD5.cpp:59
void ChangeToRegister(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isDebug=false)
ChangeToRegister - Replace this operand with a new register operand of the specified value...
const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const override
bool canRealignStack(const MachineFunction &MF) const override
static bool CantUseSP(const MachineFrameInfo &MFI)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool hasSSE1() const
Definition: X86Subtarget.h:612
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:164
int getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
bool hasAVX512() const
Definition: X86Subtarget.h:620
IRTranslator LLVM IR MI
Register getReg() const
getReg - Returns the register number.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:466
Register getStackRegister() const
MachineBasicBlock MachineBasicBlock::iterator MBBI
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Register getBaseRegister() const