LLVM  13.0.0git
X86RegisterInfo.cpp
Go to the documentation of this file.
1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of the TargetRegisterInfo class.
10 // This file is responsible for the frame pointer elimination optimization
11 // on X86.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86RegisterInfo.h"
16 #include "X86FrameLowering.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/SmallSet.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/Type.h"
36 
37 using namespace llvm;
38 
39 #define GET_REGINFO_TARGET_DESC
40 #include "X86GenRegisterInfo.inc"
41 
42 static cl::opt<bool>
43 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
44  cl::desc("Enable use of a base pointer for complex stack frames"));
45 
47  : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
48  X86_MC::getDwarfRegFlavour(TT, false),
49  X86_MC::getDwarfRegFlavour(TT, true),
50  (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
52 
53  // Cache some information.
54  Is64Bit = TT.isArch64Bit();
55  IsWin64 = Is64Bit && TT.isOSWindows();
56 
57  // Use a callee-saved register as the base pointer. These registers must
58  // not conflict with any ABI requirements. For example, in 32-bit mode PIC
59  // requires GOT in the EBX register before function calls via PLT GOT pointer.
60  if (Is64Bit) {
61  SlotSize = 8;
62  // This matches the simplified 32-bit pointer code in the data layout
63  // computation.
64  // FIXME: Should use the data layout?
65  bool Use64BitReg = TT.getEnvironment() != Triple::GNUX32;
66  StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
67  FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
68  BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
69  } else {
70  SlotSize = 4;
71  StackPtr = X86::ESP;
72  FramePtr = X86::EBP;
73  BasePtr = X86::ESI;
74  }
75 }
76 
77 int
79  return getEncodingValue(i);
80 }
81 
82 const TargetRegisterClass *
84  unsigned Idx) const {
85  // The sub_8bit sub-register index is more constrained in 32-bit mode.
86  // It behaves just like the sub_8bit_hi index.
87  if (!Is64Bit && Idx == X86::sub_8bit)
88  Idx = X86::sub_8bit_hi;
89 
90  // Forward to TableGen's default version.
91  return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
92 }
93 
94 const TargetRegisterClass *
96  const TargetRegisterClass *B,
97  unsigned SubIdx) const {
98  // The sub_8bit sub-register index is more constrained in 32-bit mode.
99  if (!Is64Bit && SubIdx == X86::sub_8bit) {
100  A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
101  if (!A)
102  return nullptr;
103  }
104  return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
105 }
106 
107 const TargetRegisterClass *
109  const MachineFunction &MF) const {
110  // Don't allow super-classes of GR8_NOREX. This class is only used after
111  // extracting sub_8bit_hi sub-registers. The H sub-registers cannot be copied
112  // to the full GR8 register class in 64-bit mode, so we cannot allow the
113  // reigster class inflation.
114  //
115  // The GR8_NOREX class is always used in a way that won't be constrained to a
116  // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
117  // full GR8 class.
118  if (RC == &X86::GR8_NOREXRegClass)
119  return RC;
120 
121  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
122 
123  const TargetRegisterClass *Super = RC;
125  do {
126  switch (Super->getID()) {
127  case X86::FR32RegClassID:
128  case X86::FR64RegClassID:
129  // If AVX-512 isn't supported we should only inflate to these classes.
130  if (!Subtarget.hasAVX512() &&
131  getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
132  return Super;
133  break;
134  case X86::VR128RegClassID:
135  case X86::VR256RegClassID:
136  // If VLX isn't supported we should only inflate to these classes.
137  if (!Subtarget.hasVLX() &&
138  getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
139  return Super;
140  break;
141  case X86::VR128XRegClassID:
142  case X86::VR256XRegClassID:
143  // If VLX isn't support we shouldn't inflate to these classes.
144  if (Subtarget.hasVLX() &&
145  getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
146  return Super;
147  break;
148  case X86::FR32XRegClassID:
149  case X86::FR64XRegClassID:
150  // If AVX-512 isn't support we shouldn't inflate to these classes.
151  if (Subtarget.hasAVX512() &&
152  getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
153  return Super;
154  break;
155  case X86::GR8RegClassID:
156  case X86::GR16RegClassID:
157  case X86::GR32RegClassID:
158  case X86::GR64RegClassID:
159  case X86::RFP32RegClassID:
160  case X86::RFP64RegClassID:
161  case X86::RFP80RegClassID:
162  case X86::VR512_0_15RegClassID:
163  case X86::VR512RegClassID:
164  // Don't return a super-class that would shrink the spill size.
165  // That can happen with the vector and float classes.
166  if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
167  return Super;
168  }
169  Super = *I++;
170  } while (Super);
171  return RC;
172 }
173 
174 const TargetRegisterClass *
176  unsigned Kind) const {
177  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
178  switch (Kind) {
179  default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
180  case 0: // Normal GPRs.
181  if (Subtarget.isTarget64BitLP64())
182  return &X86::GR64RegClass;
183  // If the target is 64bit but we have been told to use 32bit addresses,
184  // we can still use 64-bit register as long as we know the high bits
185  // are zeros.
186  // Reflect that in the returned register class.
187  if (Is64Bit) {
188  // When the target also allows 64-bit frame pointer and we do have a
189  // frame, this is fine to use it for the address accesses as well.
190  const X86FrameLowering *TFI = getFrameLowering(MF);
191  return TFI->hasFP(MF) && TFI->Uses64BitFramePtr
192  ? &X86::LOW32_ADDR_ACCESS_RBPRegClass
193  : &X86::LOW32_ADDR_ACCESSRegClass;
194  }
195  return &X86::GR32RegClass;
196  case 1: // Normal GPRs except the stack pointer (for encoding reasons).
197  if (Subtarget.isTarget64BitLP64())
198  return &X86::GR64_NOSPRegClass;
199  // NOSP does not contain RIP, so no special case here.
200  return &X86::GR32_NOSPRegClass;
201  case 2: // NOREX GPRs.
202  if (Subtarget.isTarget64BitLP64())
203  return &X86::GR64_NOREXRegClass;
204  return &X86::GR32_NOREXRegClass;
205  case 3: // NOREX GPRs except the stack pointer (for encoding reasons).
206  if (Subtarget.isTarget64BitLP64())
207  return &X86::GR64_NOREX_NOSPRegClass;
208  // NOSP does not contain RIP, so no special case here.
209  return &X86::GR32_NOREX_NOSPRegClass;
210  case 4: // Available for tailcall (not callee-saved GPRs).
211  return getGPRsForTailCall(MF);
212  }
213 }
214 
216  unsigned DefSubReg,
217  const TargetRegisterClass *SrcRC,
218  unsigned SrcSubReg) const {
219  // Prevent rewriting a copy where the destination size is larger than the
220  // input size. See PR41619.
221  // FIXME: Should this be factored into the base implementation somehow.
222  if (DefRC->hasSuperClassEq(&X86::GR64RegClass) && DefSubReg == 0 &&
223  SrcRC->hasSuperClassEq(&X86::GR64RegClass) && SrcSubReg == X86::sub_32bit)
224  return false;
225 
226  return TargetRegisterInfo::shouldRewriteCopySrc(DefRC, DefSubReg,
227  SrcRC, SrcSubReg);
228 }
229 
230 const TargetRegisterClass *
232  const Function &F = MF.getFunction();
233  if (IsWin64 || (F.getCallingConv() == CallingConv::Win64))
234  return &X86::GR64_TCW64RegClass;
235  else if (Is64Bit)
236  return &X86::GR64_TCRegClass;
237 
238  bool hasHipeCC = (F.getCallingConv() == CallingConv::HiPE);
239  if (hasHipeCC)
240  return &X86::GR32RegClass;
241  return &X86::GR32_TCRegClass;
242 }
243 
244 const TargetRegisterClass *
246  if (RC == &X86::CCRRegClass) {
247  if (Is64Bit)
248  return &X86::GR64RegClass;
249  else
250  return &X86::GR32RegClass;
251  }
252  return RC;
253 }
254 
255 unsigned
257  MachineFunction &MF) const {
258  const X86FrameLowering *TFI = getFrameLowering(MF);
259 
260  unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
261  switch (RC->getID()) {
262  default:
263  return 0;
264  case X86::GR32RegClassID:
265  return 4 - FPDiff;
266  case X86::GR64RegClassID:
267  return 12 - FPDiff;
268  case X86::VR128RegClassID:
269  return Is64Bit ? 10 : 4;
270  case X86::VR64RegClassID:
271  return 4;
272  }
273 }
274 
275 const MCPhysReg *
277  assert(MF && "MachineFunction required");
278 
279  const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>();
280  const Function &F = MF->getFunction();
281  bool HasSSE = Subtarget.hasSSE1();
282  bool HasAVX = Subtarget.hasAVX();
283  bool HasAVX512 = Subtarget.hasAVX512();
284  bool CallsEHReturn = MF->callsEHReturn();
285 
286  CallingConv::ID CC = F.getCallingConv();
287 
288  // If attribute NoCallerSavedRegisters exists then we set X86_INTR calling
289  // convention because it has the CSR list.
290  if (MF->getFunction().hasFnAttribute("no_caller_saved_registers"))
292 
293  // If atribute specified, override the CSRs normally specified by the
294  // calling convention and use the empty set instead.
295  if (MF->getFunction().hasFnAttribute("no_callee_saved_registers"))
296  return CSR_NoRegs_SaveList;
297 
298  switch (CC) {
299  case CallingConv::GHC:
300  case CallingConv::HiPE:
301  return CSR_NoRegs_SaveList;
302  case CallingConv::AnyReg:
303  if (HasAVX)
304  return CSR_64_AllRegs_AVX_SaveList;
305  return CSR_64_AllRegs_SaveList;
307  return CSR_64_RT_MostRegs_SaveList;
309  if (HasAVX)
310  return CSR_64_RT_AllRegs_AVX_SaveList;
311  return CSR_64_RT_AllRegs_SaveList;
313  if (Is64Bit)
314  return MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR() ?
315  CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList;
316  break;
318  if (HasAVX512 && IsWin64)
319  return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
320  if (HasAVX512 && Is64Bit)
321  return CSR_64_Intel_OCL_BI_AVX512_SaveList;
322  if (HasAVX && IsWin64)
323  return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
324  if (HasAVX && Is64Bit)
325  return CSR_64_Intel_OCL_BI_AVX_SaveList;
326  if (!HasAVX && !IsWin64 && Is64Bit)
327  return CSR_64_Intel_OCL_BI_SaveList;
328  break;
329  }
330  case CallingConv::HHVM:
331  return CSR_64_HHVM_SaveList;
333  if (Is64Bit) {
334  if (IsWin64) {
335  return (HasSSE ? CSR_Win64_RegCall_SaveList :
336  CSR_Win64_RegCall_NoSSE_SaveList);
337  } else {
338  return (HasSSE ? CSR_SysV64_RegCall_SaveList :
339  CSR_SysV64_RegCall_NoSSE_SaveList);
340  }
341  } else {
342  return (HasSSE ? CSR_32_RegCall_SaveList :
343  CSR_32_RegCall_NoSSE_SaveList);
344  }
346  assert(!Is64Bit && "CFGuard check mechanism only used on 32-bit X86");
347  return (HasSSE ? CSR_Win32_CFGuard_Check_SaveList
348  : CSR_Win32_CFGuard_Check_NoSSE_SaveList);
349  case CallingConv::Cold:
350  if (Is64Bit)
351  return CSR_64_MostRegs_SaveList;
352  break;
353  case CallingConv::Win64:
354  if (!HasSSE)
355  return CSR_Win64_NoSSE_SaveList;
356  return CSR_Win64_SaveList;
358  if (CallsEHReturn)
359  return CSR_64EHRet_SaveList;
360  return CSR_64_SaveList;
362  if (Is64Bit) {
363  if (HasAVX512)
364  return CSR_64_AllRegs_AVX512_SaveList;
365  if (HasAVX)
366  return CSR_64_AllRegs_AVX_SaveList;
367  if (HasSSE)
368  return CSR_64_AllRegs_SaveList;
369  return CSR_64_AllRegs_NoSSE_SaveList;
370  } else {
371  if (HasAVX512)
372  return CSR_32_AllRegs_AVX512_SaveList;
373  if (HasAVX)
374  return CSR_32_AllRegs_AVX_SaveList;
375  if (HasSSE)
376  return CSR_32_AllRegs_SSE_SaveList;
377  return CSR_32_AllRegs_SaveList;
378  }
379  default:
380  break;
381  }
382 
383  if (Is64Bit) {
384  bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() &&
385  F.getAttributes().hasAttrSomewhere(Attribute::SwiftError);
386  if (IsSwiftCC)
387  return IsWin64 ? CSR_Win64_SwiftError_SaveList
388  : CSR_64_SwiftError_SaveList;
389 
390  if (IsWin64)
391  return HasSSE ? CSR_Win64_SaveList : CSR_Win64_NoSSE_SaveList;
392  if (CallsEHReturn)
393  return CSR_64EHRet_SaveList;
394  return CSR_64_SaveList;
395  }
396 
397  return CallsEHReturn ? CSR_32EHRet_SaveList : CSR_32_SaveList;
398 }
399 
401  const MachineFunction *MF) const {
402  assert(MF && "Invalid MachineFunction pointer.");
405  return CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList;
406  return nullptr;
407 }
408 
409 const uint32_t *
411  CallingConv::ID CC) const {
412  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
413  bool HasSSE = Subtarget.hasSSE1();
414  bool HasAVX = Subtarget.hasAVX();
415  bool HasAVX512 = Subtarget.hasAVX512();
416 
417  switch (CC) {
418  case CallingConv::GHC:
419  case CallingConv::HiPE:
420  return CSR_NoRegs_RegMask;
421  case CallingConv::AnyReg:
422  if (HasAVX)
423  return CSR_64_AllRegs_AVX_RegMask;
424  return CSR_64_AllRegs_RegMask;
426  return CSR_64_RT_MostRegs_RegMask;
428  if (HasAVX)
429  return CSR_64_RT_AllRegs_AVX_RegMask;
430  return CSR_64_RT_AllRegs_RegMask;
432  if (Is64Bit)
433  return CSR_64_TLS_Darwin_RegMask;
434  break;
436  if (HasAVX512 && IsWin64)
437  return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
438  if (HasAVX512 && Is64Bit)
439  return CSR_64_Intel_OCL_BI_AVX512_RegMask;
440  if (HasAVX && IsWin64)
441  return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
442  if (HasAVX && Is64Bit)
443  return CSR_64_Intel_OCL_BI_AVX_RegMask;
444  if (!HasAVX && !IsWin64 && Is64Bit)
445  return CSR_64_Intel_OCL_BI_RegMask;
446  break;
447  }
448  case CallingConv::HHVM:
449  return CSR_64_HHVM_RegMask;
451  if (Is64Bit) {
452  if (IsWin64) {
453  return (HasSSE ? CSR_Win64_RegCall_RegMask :
454  CSR_Win64_RegCall_NoSSE_RegMask);
455  } else {
456  return (HasSSE ? CSR_SysV64_RegCall_RegMask :
457  CSR_SysV64_RegCall_NoSSE_RegMask);
458  }
459  } else {
460  return (HasSSE ? CSR_32_RegCall_RegMask :
461  CSR_32_RegCall_NoSSE_RegMask);
462  }
464  assert(!Is64Bit && "CFGuard check mechanism only used on 32-bit X86");
465  return (HasSSE ? CSR_Win32_CFGuard_Check_RegMask
466  : CSR_Win32_CFGuard_Check_NoSSE_RegMask);
467  case CallingConv::Cold:
468  if (Is64Bit)
469  return CSR_64_MostRegs_RegMask;
470  break;
471  case CallingConv::Win64:
472  return CSR_Win64_RegMask;
474  return CSR_64_RegMask;
476  if (Is64Bit) {
477  if (HasAVX512)
478  return CSR_64_AllRegs_AVX512_RegMask;
479  if (HasAVX)
480  return CSR_64_AllRegs_AVX_RegMask;
481  if (HasSSE)
482  return CSR_64_AllRegs_RegMask;
483  return CSR_64_AllRegs_NoSSE_RegMask;
484  } else {
485  if (HasAVX512)
486  return CSR_32_AllRegs_AVX512_RegMask;
487  if (HasAVX)
488  return CSR_32_AllRegs_AVX_RegMask;
489  if (HasSSE)
490  return CSR_32_AllRegs_SSE_RegMask;
491  return CSR_32_AllRegs_RegMask;
492  }
493  default:
494  break;
495  }
496 
497  // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
498  // callsEHReturn().
499  if (Is64Bit) {
500  const Function &F = MF.getFunction();
501  bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() &&
502  F.getAttributes().hasAttrSomewhere(Attribute::SwiftError);
503  if (IsSwiftCC)
504  return IsWin64 ? CSR_Win64_SwiftError_RegMask : CSR_64_SwiftError_RegMask;
505  return IsWin64 ? CSR_Win64_RegMask : CSR_64_RegMask;
506  }
507 
508  return CSR_32_RegMask;
509 }
510 
511 const uint32_t*
513  return CSR_NoRegs_RegMask;
514 }
515 
517  return CSR_64_TLS_Darwin_RegMask;
518 }
519 
521  BitVector Reserved(getNumRegs());
522  const X86FrameLowering *TFI = getFrameLowering(MF);
523 
524  // Set the floating point control register as reserved.
525  Reserved.set(X86::FPCW);
526 
527  // Set the floating point status register as reserved.
528  Reserved.set(X86::FPSW);
529 
530  // Set the SIMD floating point control register as reserved.
531  Reserved.set(X86::MXCSR);
532 
533  // Set the stack-pointer register and its aliases as reserved.
534  for (const MCPhysReg &SubReg : subregs_inclusive(X86::RSP))
535  Reserved.set(SubReg);
536 
537  // Set the Shadow Stack Pointer as reserved.
538  Reserved.set(X86::SSP);
539 
540  // Set the instruction pointer register and its aliases as reserved.
541  for (const MCPhysReg &SubReg : subregs_inclusive(X86::RIP))
542  Reserved.set(SubReg);
543 
544  // Set the frame-pointer register and its aliases as reserved if needed.
545  if (TFI->hasFP(MF)) {
546  for (const MCPhysReg &SubReg : subregs_inclusive(X86::RBP))
547  Reserved.set(SubReg);
548  }
549 
550  // Set the base-pointer register and its aliases as reserved if needed.
551  if (hasBasePointer(MF)) {
553  const uint32_t *RegMask = getCallPreservedMask(MF, CC);
556  "Stack realignment in presence of dynamic allocas is not supported with"
557  "this calling convention.");
558 
560  for (const MCPhysReg &SubReg : subregs_inclusive(BasePtr))
561  Reserved.set(SubReg);
562  }
563 
564  // Mark the segment registers as reserved.
565  Reserved.set(X86::CS);
566  Reserved.set(X86::SS);
567  Reserved.set(X86::DS);
568  Reserved.set(X86::ES);
569  Reserved.set(X86::FS);
570  Reserved.set(X86::GS);
571 
572  // Mark the floating point stack registers as reserved.
573  for (unsigned n = 0; n != 8; ++n)
574  Reserved.set(X86::ST0 + n);
575 
576  // Reserve the registers that only exist in 64-bit mode.
577  if (!Is64Bit) {
578  // These 8-bit registers are part of the x86-64 extension even though their
579  // super-registers are old 32-bits.
580  Reserved.set(X86::SIL);
581  Reserved.set(X86::DIL);
582  Reserved.set(X86::BPL);
583  Reserved.set(X86::SPL);
584  Reserved.set(X86::SIH);
585  Reserved.set(X86::DIH);
586  Reserved.set(X86::BPH);
587  Reserved.set(X86::SPH);
588 
589  for (unsigned n = 0; n != 8; ++n) {
590  // R8, R9, ...
591  for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
592  Reserved.set(*AI);
593 
594  // XMM8, XMM9, ...
595  for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
596  Reserved.set(*AI);
597  }
598  }
599  if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) {
600  for (unsigned n = 16; n != 32; ++n) {
601  for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
602  Reserved.set(*AI);
603  }
604  }
605 
606  assert(checkAllSuperRegsMarked(Reserved,
607  {X86::SIL, X86::DIL, X86::BPL, X86::SPL,
608  X86::SIH, X86::DIH, X86::BPH, X86::SPH}));
609  return Reserved;
610 }
611 
613  // Check if the EFLAGS register is marked as live-out. This shouldn't happen,
614  // because the calling convention defines the EFLAGS register as NOT
615  // preserved.
616  //
617  // Unfortunatelly the EFLAGS show up as live-out after branch folding. Adding
618  // an assert to track this and clear the register afterwards to avoid
619  // unnecessary crashes during release builds.
620  assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
621  "EFLAGS are not live-out from a patchpoint.");
622 
623  // Also clean other registers that don't need preserving (IP).
624  for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
625  Mask[Reg / 32] &= ~(1U << (Reg % 32));
626 }
627 
628 //===----------------------------------------------------------------------===//
629 // Stack Frame Processing methods
630 //===----------------------------------------------------------------------===//
631 
632 static bool CantUseSP(const MachineFrameInfo &MFI) {
633  return MFI.hasVarSizedObjects() || MFI.hasOpaqueSPAdjustment();
634 }
635 
638  if (X86FI->hasPreallocatedCall())
639  return true;
640 
641  const MachineFrameInfo &MFI = MF.getFrameInfo();
642 
643  if (!EnableBasePointer)
644  return false;
645 
646  // When we need stack realignment, we can't address the stack from the frame
647  // pointer. When we have dynamic allocas or stack-adjusting inline asm, we
648  // can't address variables from the stack pointer. MS inline asm can
649  // reference locals while also adjusting the stack pointer. When we can't
650  // use both the SP and the FP, we need a separate base pointer register.
651  bool CantUseFP = needsStackRealignment(MF);
652  return CantUseFP && CantUseSP(MFI);
653 }
654 
657  return false;
658 
659  const MachineFrameInfo &MFI = MF.getFrameInfo();
660  const MachineRegisterInfo *MRI = &MF.getRegInfo();
661 
662  // Stack realignment requires a frame pointer. If we already started
663  // register allocation with frame pointer elimination, it is too late now.
664  if (!MRI->canReserveReg(FramePtr))
665  return false;
666 
667  // If a base pointer is necessary. Check that it isn't too late to reserve
668  // it.
669  if (CantUseSP(MFI))
670  return MRI->canReserveReg(BasePtr);
671  return true;
672 }
673 
674 // tryOptimizeLEAtoMOV - helper function that tries to replace a LEA instruction
675 // of the form 'lea (%esp), %ebx' --> 'mov %esp, %ebx'.
676 // TODO: In this case we should be really trying first to entirely eliminate
677 // this instruction which is a plain copy.
679  MachineInstr &MI = *II;
680  unsigned Opc = II->getOpcode();
681  // Check if this is a LEA of the form 'lea (%esp), %ebx'
682  if ((Opc != X86::LEA32r && Opc != X86::LEA64r && Opc != X86::LEA64_32r) ||
683  MI.getOperand(2).getImm() != 1 ||
684  MI.getOperand(3).getReg() != X86::NoRegister ||
685  MI.getOperand(4).getImm() != 0 ||
686  MI.getOperand(5).getReg() != X86::NoRegister)
687  return false;
688  Register BasePtr = MI.getOperand(1).getReg();
689  // In X32 mode, ensure the base-pointer is a 32-bit operand, so the LEA will
690  // be replaced with a 32-bit operand MOV which will zero extend the upper
691  // 32-bits of the super register.
692  if (Opc == X86::LEA64_32r)
693  BasePtr = getX86SubSuperRegister(BasePtr, 32);
694  Register NewDestReg = MI.getOperand(0).getReg();
695  const X86InstrInfo *TII =
696  MI.getParent()->getParent()->getSubtarget<X86Subtarget>().getInstrInfo();
697  TII->copyPhysReg(*MI.getParent(), II, MI.getDebugLoc(), NewDestReg, BasePtr,
698  MI.getOperand(1).isKill());
699  MI.eraseFromParent();
700  return true;
701 }
702 
704  switch (MI.getOpcode()) {
705  case X86::CATCHRET:
706  case X86::CLEANUPRET:
707  return true;
708  default:
709  return false;
710  }
711  llvm_unreachable("impossible");
712 }
713 
714 void
716  int SPAdj, unsigned FIOperandNum,
717  RegScavenger *RS) const {
718  MachineInstr &MI = *II;
719  MachineBasicBlock &MBB = *MI.getParent();
720  MachineFunction &MF = *MBB.getParent();
722  bool IsEHFuncletEpilogue = MBBI == MBB.end() ? false
724  const X86FrameLowering *TFI = getFrameLowering(MF);
725  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
726 
727  // Determine base register and offset.
728  int FIOffset;
729  Register BasePtr;
730  if (MI.isReturn()) {
731  assert((!needsStackRealignment(MF) ||
733  "Return instruction can only reference SP relative frame objects");
734  FIOffset =
735  TFI->getFrameIndexReferenceSP(MF, FrameIndex, BasePtr, 0).getFixed();
736  } else if (TFI->Is64Bit && (MBB.isEHFuncletEntry() || IsEHFuncletEpilogue)) {
737  FIOffset = TFI->getWin64EHFrameIndexRef(MF, FrameIndex, BasePtr);
738  } else {
739  FIOffset = TFI->getFrameIndexReference(MF, FrameIndex, BasePtr).getFixed();
740  }
741 
742  // LOCAL_ESCAPE uses a single offset, with no register. It only works in the
743  // simple FP case, and doesn't work with stack realignment. On 32-bit, the
744  // offset is from the traditional base pointer location. On 64-bit, the
745  // offset is from the SP at the end of the prologue, not the FP location. This
746  // matches the behavior of llvm.frameaddress.
747  unsigned Opc = MI.getOpcode();
748  if (Opc == TargetOpcode::LOCAL_ESCAPE) {
749  MachineOperand &FI = MI.getOperand(FIOperandNum);
750  FI.ChangeToImmediate(FIOffset);
751  return;
752  }
753 
754  // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
755  // register as source operand, semantic is the same and destination is
756  // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
757  // Don't change BasePtr since it is used later for stack adjustment.
758  Register MachineBasePtr = BasePtr;
759  if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
760  MachineBasePtr = getX86SubSuperRegister(BasePtr, 64);
761 
762  // This must be part of a four operand memory reference. Replace the
763  // FrameIndex with base register. Add an offset to the offset.
764  MI.getOperand(FIOperandNum).ChangeToRegister(MachineBasePtr, false);
765 
766  if (BasePtr == StackPtr)
767  FIOffset += SPAdj;
768 
769  // The frame index format for stackmaps and patchpoints is different from the
770  // X86 format. It only has a FI and an offset.
771  if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
772  assert(BasePtr == FramePtr && "Expected the FP as base register");
773  int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
774  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
775  return;
776  }
777 
778  if (MI.getOperand(FIOperandNum+3).isImm()) {
779  // Offset is a 32-bit integer.
780  int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
781  int Offset = FIOffset + Imm;
782  assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
783  "Requesting 64-bit offset in 32-bit immediate!");
784  if (Offset != 0 || !tryOptimizeLEAtoMOV(II))
785  MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
786  } else {
787  // Offset is symbolic. This is extremely rare.
788  uint64_t Offset = FIOffset +
789  (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
790  MI.getOperand(FIOperandNum + 3).setOffset(Offset);
791  }
792 }
793 
796  const MachineFunction *MF = MBB.getParent();
797  if (MF->callsEHReturn())
798  return 0;
799 
800  const TargetRegisterClass &AvailableRegs = *getGPRsForTailCall(*MF);
801 
802  if (MBBI == MBB.end())
803  return 0;
804 
805  switch (MBBI->getOpcode()) {
806  default:
807  return 0;
808  case TargetOpcode::PATCHABLE_RET:
809  case X86::RET:
810  case X86::RETL:
811  case X86::RETQ:
812  case X86::RETIL:
813  case X86::RETIQ:
814  case X86::TCRETURNdi:
815  case X86::TCRETURNri:
816  case X86::TCRETURNmi:
817  case X86::TCRETURNdi64:
818  case X86::TCRETURNri64:
819  case X86::TCRETURNmi64:
820  case X86::EH_RETURN:
821  case X86::EH_RETURN64: {
823  for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
824  MachineOperand &MO = MBBI->getOperand(I);
825  if (!MO.isReg() || MO.isDef())
826  continue;
827  Register Reg = MO.getReg();
828  if (!Reg)
829  continue;
830  for (MCRegAliasIterator AI(Reg, this, true); AI.isValid(); ++AI)
831  Uses.insert(*AI);
832  }
833 
834  for (auto CS : AvailableRegs)
835  if (!Uses.count(CS) && CS != X86::RIP && CS != X86::RSP && CS != X86::ESP)
836  return CS;
837  }
838  }
839 
840  return 0;
841 }
842 
844  const X86FrameLowering *TFI = getFrameLowering(MF);
845  return TFI->hasFP(MF) ? FramePtr : StackPtr;
846 }
847 
848 unsigned
850  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
851  Register FrameReg = getFrameRegister(MF);
852  if (Subtarget.isTarget64BitILP32())
853  FrameReg = getX86SubSuperRegister(FrameReg, 32);
854  return FrameReg;
855 }
856 
857 unsigned
859  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
860  Register StackReg = getStackRegister();
861  if (Subtarget.isTarget64BitILP32())
862  StackReg = getX86SubSuperRegister(StackReg, 32);
863  return StackReg;
864 }
865 
866 static ShapeT getTileShape(Register VirtReg, VirtRegMap *VRM,
867  const MachineRegisterInfo *MRI) {
868  if (VRM->hasShape(VirtReg))
869  return VRM->getShape(VirtReg);
870 
871  const MachineOperand &Def = *MRI->def_begin(VirtReg);
872  MachineInstr *MI = const_cast<MachineInstr *>(Def.getParent());
873  unsigned OpCode = MI->getOpcode();
874  switch (OpCode) {
875  default:
876  llvm_unreachable("Unexpected machine instruction on tile register!");
877  break;
878  case X86::COPY: {
879  Register SrcReg = MI->getOperand(1).getReg();
880  ShapeT Shape = getTileShape(SrcReg, VRM, MRI);
881  VRM->assignVirt2Shape(VirtReg, Shape);
882  return Shape;
883  }
884  // We only collect the tile shape that is defined.
885  case X86::PTILELOADDV:
886  case X86::PTDPBSSDV:
887  case X86::PTDPBSUDV:
888  case X86::PTDPBUSDV:
889  case X86::PTDPBUUDV:
890  case X86::PTILEZEROV:
891  case X86::PTDPBF16PSV:
892  MachineOperand &MO1 = MI->getOperand(1);
893  MachineOperand &MO2 = MI->getOperand(2);
894  ShapeT Shape(&MO1, &MO2, MRI);
895  VRM->assignVirt2Shape(VirtReg, Shape);
896  return Shape;
897  }
898 }
899 
901  ArrayRef<MCPhysReg> Order,
903  const MachineFunction &MF,
904  const VirtRegMap *VRM,
905  const LiveRegMatrix *Matrix) const {
906  const MachineRegisterInfo *MRI = &MF.getRegInfo();
907  const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
908  bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
909  VirtReg, Order, Hints, MF, VRM, Matrix);
910 
911  if (RC.getID() != X86::TILERegClassID)
912  return BaseImplRetVal;
913 
914  ShapeT VirtShape = getTileShape(VirtReg, const_cast<VirtRegMap *>(VRM), MRI);
915  auto AddHint = [&](MCPhysReg PhysReg) {
916  Register VReg = Matrix->getOneVReg(PhysReg);
917  if (VReg == MCRegister::NoRegister) { // Not allocated yet
918  Hints.push_back(PhysReg);
919  return;
920  }
921  ShapeT PhysShape = getTileShape(VReg, const_cast<VirtRegMap *>(VRM), MRI);
922  if (PhysShape == VirtShape)
923  Hints.push_back(PhysReg);
924  };
925 
926  SmallSet<MCPhysReg, 4> CopyHints;
927  CopyHints.insert(Hints.begin(), Hints.end());
928  Hints.clear();
929  for (auto Hint : CopyHints) {
930  if (RC.contains(Hint) && !MRI->isReserved(Hint))
931  AddHint(Hint);
932  }
933  for (MCPhysReg PhysReg : Order) {
934  if (!CopyHints.count(PhysReg) && RC.contains(PhysReg) &&
935  !MRI->isReserved(PhysReg))
936  AddHint(PhysReg);
937  }
938 
939 #define DEBUG_TYPE "tile-hint"
940  LLVM_DEBUG({
941  dbgs() << "Hints for virtual register " << format_hex(VirtReg, 8) << "\n";
942  for (auto Hint : Hints) {
943  dbgs() << "tmm" << Hint << ",";
944  }
945  dbgs() << "\n";
946  });
947 #undef DEBUG_TYPE
948 
949  return true;
950 }
i
i
Definition: README.txt:29
LiveRegMatrix.h
llvm::EngineKind::Kind
Kind
Definition: ExecutionEngine.h:524
llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:351
llvm::X86_MC::getDwarfRegFlavour
unsigned getDwarfRegFlavour(const Triple &TT, bool isEH)
Definition: X86MCTargetDesc.cpp:59
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm::MachineRegisterInfo::def_begin
def_iterator def_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:384
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:69
llvm
This class represents lattice values for constants.
Definition: AllocatorList.h:23
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
Reg
unsigned Reg
Definition: MachineSink.cpp:1540
llvm::CallingConv::X86_64_SysV
@ X86_64_SysV
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
Definition: CallingConv.h:154
llvm::CallingConv::HHVM
@ HHVM
Calling convention used by HipHop Virtual Machine (HHVM) to perform calls to and from translation cac...
Definition: CallingConv.h:174
TargetFrameLowering.h
X86Subtarget.h
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::Function
Definition: Function.h:61
llvm::X86FrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Definition: X86FrameLowering.cpp:93
llvm::MachineBasicBlock::isEHFuncletEntry
bool isEHFuncletEntry() const
Returns true if this is the entry block of an EH funclet.
Definition: MachineBasicBlock.h:461
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::X86Subtarget
Definition: X86Subtarget.h:52
ErrorHandling.h
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::X86RegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: X86RegisterInfo.cpp:843
llvm::X86Subtarget::isTarget64BitILP32
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
Definition: X86Subtarget.h:605
llvm::X86RegisterInfo::getRegPressureLimit
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
Definition: X86RegisterInfo.cpp:256
llvm::MachineRegisterInfo::canReserveReg
bool canReserveReg(MCRegister PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
Definition: MachineRegisterInfo.h:882
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::X86RegisterInfo::eliminateFrameIndex
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Definition: X86RegisterInfo.cpp:715
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:140
llvm::CallingConv::HiPE
@ HiPE
Definition: CallingConv.h:55
TargetInstrInfo.h
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
llvm::MCRegister::NoRegister
static constexpr unsigned NoRegister
Definition: MCRegister.h:41
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:345
llvm::CallingConv::Intel_OCL_BI
@ Intel_OCL_BI
Intel_OCL_BI - Calling conventions for Intel OpenCL built-ins.
Definition: CallingConv.h:150
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::ShapeT
Definition: TileShapeInfo.h:31
STLExtras.h
llvm::X86RegisterInfo::getCalleeSavedRegsViaCopy
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
Definition: X86RegisterInfo.cpp:400
llvm::X86AS::FS
@ FS
Definition: X86.h:182
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:122
F
#define F(x, y, z)
Definition: MD5.cpp:56
MachineRegisterInfo.h
Uses
SmallPtrSet< MachineInstr *, 2 > Uses
Definition: ARMLowOverheadLoops.cpp:583
llvm::X86RegisterInfo::getGPRsForTailCall
const TargetRegisterClass * getGPRsForTailCall(const MachineFunction &MF) const
getGPRsForTailCall - Returns a register class with registers that can be used in forming tail calls.
Definition: X86RegisterInfo.cpp:231
llvm::X86RegisterInfo::getDarwinTLSCallPreservedMask
const uint32_t * getDarwinTLSCallPreservedMask() const
Definition: X86RegisterInfo.cpp:516
X86FrameLowering.h
X86GenRegisterInfo
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
llvm::X86MachineFunctionInfo::hasPreallocatedCall
bool hasPreallocatedCall() const
Definition: X86MachineFunctionInfo.h:197
CommandLine.h
llvm::X86RegisterInfo::getLargestLegalSuperClass
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
Definition: X86RegisterInfo.cpp:108
llvm::N86::ESP
@ ESP
Definition: X86MCTargetDesc.h:51
X86MachineFunctionInfo.h
llvm::TargetRegisterClass::contains
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
Definition: TargetRegisterInfo.h:91
llvm::TargetRegisterInfo::canRealignStack
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
Definition: TargetRegisterInfo.cpp:460
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:565
llvm::CallingConv::PreserveAll
@ PreserveAll
Definition: CallingConv.h:70
TargetMachine.h
llvm::X86FrameLowering::getWin64EHFrameIndexRef
int getWin64EHFrameIndexRef(const MachineFunction &MF, int FI, Register &SPReg) const
Definition: X86FrameLowering.cpp:2200
Constants.h
llvm::X86FrameLowering::getFrameIndexReferenceSP
StackOffset getFrameIndexReferenceSP(const MachineFunction &MF, int FI, Register &SPReg, int Adjustment) const
Definition: X86FrameLowering.cpp:2216
llvm::X86RegisterInfo::getNoPreservedMask
const uint32_t * getNoPreservedMask() const override
Definition: X86RegisterInfo.cpp:512
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:653
llvm::ISD::CATCHRET
@ CATCHRET
CATCHRET - Represents a return from a catch block funclet.
Definition: ISDOpcodes.h:955
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:900
int
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
Definition: README.txt:536
CantUseSP
static bool CantUseSP(const MachineFrameInfo &MFI)
Definition: X86RegisterInfo.cpp:632
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::CallingConv::X86_INTR
@ X86_INTR
X86_INTR - x86 hardware interrupt context.
Definition: CallingConv.h:184
llvm::CallingConv::PreserveMost
@ PreserveMost
Definition: CallingConv.h:66
llvm::X86RegisterInfo::getBaseRegister
Register getBaseRegister() const
Definition: X86RegisterInfo.h:139
false
Definition: StackSlotColoring.cpp:142
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MachineOperand::ChangeToImmediate
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
Definition: MachineOperand.cpp:156
llvm::CallingConv::AnyReg
@ AnyReg
Definition: CallingConv.h:62
llvm::X86Subtarget::hasSSE1
bool hasSSE1() const
Definition: X86Subtarget.h:625
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::TargetRegisterClass::hasSuperClassEq
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
Definition: TargetRegisterInfo.h:136
llvm::X86RegisterInfo::shouldRewriteCopySrc
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
Definition: X86RegisterInfo.cpp:215
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
BitVector.h
llvm::BitVector
Definition: BitVector.h:74
llvm::MachineFrameInfo::isFixedObjectIndex
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Definition: MachineFrameInfo.h:677
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
Type.h
llvm::X86Subtarget::isTarget64BitLP64
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Definition: X86Subtarget.h:611
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::X86AS::GS
@ GS
Definition: X86.h:181
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:555
llvm::cl::opt< bool >
llvm::X86RegisterInfo::getRegAllocationHints
bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
Definition: X86RegisterInfo.cpp:900
llvm::MachineOperand::clobbersPhysReg
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Definition: MachineOperand.h:614
llvm::Triple::GNUX32
@ GNUX32
Definition: Triple.h:211
llvm::X86RegisterInfo::getSubClassWithSubReg
const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const override
Definition: X86RegisterInfo.cpp:83
llvm::isInt< 32 >
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:374
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:318
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:63
llvm::MachineFunction::callsEHReturn
bool callsEHReturn() const
Definition: MachineFunction.h:953
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:228
llvm::X86FrameLowering
Definition: X86FrameLowering.h:27
llvm::getX86SubSuperRegister
MCRegister getX86SubSuperRegister(MCRegister, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
Definition: X86MCTargetDesc.cpp:784
isFuncletReturnInstr
static bool isFuncletReturnInstr(MachineInstr &MI)
Definition: X86RegisterInfo.cpp:703
llvm::ISD::CLEANUPRET
@ CLEANUPRET
CLEANUPRET - Represents a return from a cleanup block funclet.
Definition: ISDOpcodes.h:959
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::X86RegisterInfo::getPtrSizedFrameRegister
unsigned getPtrSizedFrameRegister(const MachineFunction &MF) const
Definition: X86RegisterInfo.cpp:849
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::TargetRegisterInfo::getRegAllocationHints
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
Definition: TargetRegisterInfo.cpp:403
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:440
llvm::X86RegisterInfo::X86RegisterInfo
X86RegisterInfo(const Triple &TT)
Definition: X86RegisterInfo.cpp:46
llvm::CallingConv::CXX_FAST_TLS
@ CXX_FAST_TLS
Definition: CallingConv.h:76
MachineFunctionPass.h
llvm::CallingConv::GHC
@ GHC
Definition: CallingConv.h:51
llvm::X86_MC::initLLVMToSEHAndCVRegMapping
void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI)
Definition: X86MCTargetDesc.cpp:75
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::X86Subtarget::getTargetLowering
const X86TargetLowering * getTargetLowering() const override
Definition: X86Subtarget.h:542
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:571
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::VirtRegMap::hasShape
bool hasShape(Register virtReg) const
Definition: VirtRegMap.h:117
llvm::X86RegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Definition: X86RegisterInfo.cpp:410
llvm::X86MachineFunctionInfo
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
Definition: X86MachineFunctionInfo.h:25
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:357
EnableBasePointer
static cl::opt< bool > EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames"))
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::VirtRegMap::assignVirt2Shape
void assignVirt2Shape(Register virtReg, ShapeT shape)
Definition: VirtRegMap.h:126
llvm::X86InstrInfo
Definition: X86InstrInfo.h:130
TargetOptions.h
llvm::VirtRegMap::getShape
ShapeT getShape(Register virtReg) const
Definition: VirtRegMap.h:121
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:239
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
Matrix
Live Register Matrix
Definition: LiveRegMatrix.cpp:44
llvm::CallingConv::CFGuard_Check
@ CFGuard_Check
Special calling convention on Windows for calling the Control Guard Check ICall funtion.
Definition: CallingConv.h:87
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::X86RegisterInfo::adjustStackMapLiveOutMask
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
Definition: X86RegisterInfo.cpp:612
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
getTileShape
static ShapeT getTileShape(Register VirtReg, VirtRegMap *VRM, const MachineRegisterInfo *MRI)
Definition: X86RegisterInfo.cpp:866
uint32_t
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:372
llvm::X86RegisterInfo::getMatchingSuperRegClass
const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const override
getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register ...
Definition: X86RegisterInfo.cpp:95
llvm::X86RegisterInfo::canRealignStack
bool canRealignStack(const MachineFunction &MF) const override
Definition: X86RegisterInfo.cpp:655
llvm::SmallSet::insert
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:180
llvm::X86RegisterInfo::getSEHRegNum
int getSEHRegNum(unsigned i) const
Definition: X86RegisterInfo.cpp:78
llvm::StackOffset::getFixed
static StackOffset getFixed(ScalarTy Fixed)
Definition: TypeSize.h:139
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:73
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::TargetRegisterInfo::shouldRewriteCopySrc
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
Definition: TargetRegisterInfo.cpp:394
llvm::X86Subtarget::hasAVX512
bool hasAVX512() const
Definition: X86Subtarget.h:633
llvm::CallingConv::Win64
@ Win64
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:164
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:521
uint16_t
llvm::X86RegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
getCalleeSavedRegs - Return a null-terminated list of all of the callee-save registers on this target...
Definition: X86RegisterInfo.cpp:276
llvm::X86RegisterInfo::findDeadCallerSavedReg
unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI) const
findDeadCallerSavedReg - Return a caller-saved register that isn't live when it reaches the "return" ...
Definition: X86RegisterInfo.cpp:794
llvm::TargetRegisterClass::getSuperClasses
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
Definition: TargetRegisterInfo.h:174
llvm::N86::EBX
@ EBX
Definition: X86MCTargetDesc.h:51
MachineFrameInfo.h
llvm::ARCISD::RET
@ RET
Definition: ARCISelLowering.h:52
llvm::X86Subtarget::hasVLX
bool hasVLX() const
Definition: X86Subtarget.h:735
llvm::X86RegisterInfo::hasBasePointer
bool hasBasePointer(const MachineFunction &MF) const
Definition: X86RegisterInfo.cpp:636
Function.h
llvm::TargetRegisterClass::sc_iterator
const TargetRegisterClass *const * sc_iterator
Definition: TargetRegisterInfo.h:50
llvm::ISD::EH_RETURN
@ EH_RETURN
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin,...
Definition: ISDOpcodes.h:128
llvm::SmallVectorImpl::clear
void clear()
Definition: SmallVector.h:585
tryOptimizeLEAtoMOV
static bool tryOptimizeLEAtoMOV(MachineBasicBlock::iterator II)
Definition: X86RegisterInfo.cpp:678
llvm::X86Subtarget::hasAVX
bool hasAVX() const
Definition: X86Subtarget.h:631
X86RegisterInfo.h
false
Function Alias Analysis false
Definition: AliasAnalysis.cpp:847
llvm::X86RegisterInfo::getCrossCopyRegClass
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or...
Definition: X86RegisterInfo.cpp:245
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:798
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::X86FrameLowering::Is64Bit
bool Is64Bit
Is64Bit implies that x86_64 instructions are available.
Definition: X86FrameLowering.h:40
llvm::PseudoProbeAttributes::Reserved
@ Reserved
llvm::X86FrameLowering::Uses64BitFramePtr
bool Uses64BitFramePtr
True if the 64-bit frame or stack pointer should be used.
Definition: X86FrameLowering.h:47
llvm::SmallVectorImpl< MCPhysReg >
llvm::X86MachineFunctionInfo::isSplitCSR
bool isSplitCSR() const
Definition: X86MachineFunctionInfo.h:188
llvm::CallingConv::Cold
@ Cold
Definition: CallingConv.h:48
llvm::X86RegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a ...
Definition: X86RegisterInfo.cpp:520
llvm::X86RegisterInfo::getStackRegister
Register getStackRegister() const
Definition: X86RegisterInfo.h:138
llvm::MachineFrameInfo::hasOpaqueSPAdjustment
bool hasOpaqueSPAdjustment() const
Returns true if the function contains opaque dynamic stack adjustments.
Definition: MachineFrameInfo.h:606
llvm::CallingConv::X86_RegCall
@ X86_RegCall
Register calling convention used for parameters transfer optimization.
Definition: CallingConv.h:214
llvm::cl::desc
Definition: CommandLine.h:411
llvm::X86TargetLowering::supportSwiftError
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
Definition: X86ISelLowering.cpp:51629
llvm::N86::ESI
@ ESI
Definition: X86MCTargetDesc.h:51
llvm::SIInstrFlags::DS
@ DS
Definition: SIDefines.h:52
n
The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports that transformation probably isn t worthwhile The transformation can also easily be made to work with non zero equality for n
Definition: README.txt:685
MachineFunction.h
X86
Unrolling by would eliminate the &in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various including etc On X86
Definition: README.txt:568
llvm::MachineInstrBundleIterator< MachineInstr >
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1827
llvm::format_hex
FormattedNumber format_hex(uint64_t N, unsigned Width, bool Upper=false)
format_hex - Output N as a fixed width hexadecimal.
Definition: Format.h:186
llvm::HexagonInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Emit instructions to copy a pair of physical registers.
Definition: HexagonInstrInfo.cpp:812
llvm::X86FrameLowering::getFrameIndexReference
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
Definition: X86FrameLowering.cpp:2105
llvm::X86AS::SS
@ SS
Definition: X86.h:183
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::X86RegisterInfo::getPtrSizedStackRegister
unsigned getPtrSizedStackRegister(const MachineFunction &MF) const
Definition: X86RegisterInfo.cpp:858
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:773
llvm::X86RegisterInfo::getPointerRegClass
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Returns a TargetRegisterClass used for pointer values.
Definition: X86RegisterInfo.cpp:175
SmallSet.h
llvm::LiveRegMatrix
Definition: LiveRegMatrix.h:40