LLVM  15.0.0git
X86RegisterInfo.cpp
Go to the documentation of this file.
1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of the TargetRegisterInfo class.
10 // This file is responsible for the frame pointer elimination optimization
11 // on X86.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86RegisterInfo.h"
16 #include "X86FrameLowering.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/SmallSet.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/Type.h"
38 
39 using namespace llvm;
40 
41 #define GET_REGINFO_TARGET_DESC
42 #include "X86GenRegisterInfo.inc"
43 
44 static cl::opt<bool>
45 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
46  cl::desc("Enable use of a base pointer for complex stack frames"));
47 
49  : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
50  X86_MC::getDwarfRegFlavour(TT, false),
51  X86_MC::getDwarfRegFlavour(TT, true),
52  (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
54 
55  // Cache some information.
56  Is64Bit = TT.isArch64Bit();
57  IsWin64 = Is64Bit && TT.isOSWindows();
58 
59  // Use a callee-saved register as the base pointer. These registers must
60  // not conflict with any ABI requirements. For example, in 32-bit mode PIC
61  // requires GOT in the EBX register before function calls via PLT GOT pointer.
62  if (Is64Bit) {
63  SlotSize = 8;
64  // This matches the simplified 32-bit pointer code in the data layout
65  // computation.
66  // FIXME: Should use the data layout?
67  bool Use64BitReg = !TT.isX32();
68  StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
69  FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
70  BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
71  } else {
72  SlotSize = 4;
73  StackPtr = X86::ESP;
74  FramePtr = X86::EBP;
75  BasePtr = X86::ESI;
76  }
77 }
78 
79 int
81  return getEncodingValue(i);
82 }
83 
84 const TargetRegisterClass *
86  unsigned Idx) const {
87  // The sub_8bit sub-register index is more constrained in 32-bit mode.
88  // It behaves just like the sub_8bit_hi index.
89  if (!Is64Bit && Idx == X86::sub_8bit)
90  Idx = X86::sub_8bit_hi;
91 
92  // Forward to TableGen's default version.
93  return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
94 }
95 
96 const TargetRegisterClass *
98  const TargetRegisterClass *B,
99  unsigned SubIdx) const {
100  // The sub_8bit sub-register index is more constrained in 32-bit mode.
101  if (!Is64Bit && SubIdx == X86::sub_8bit) {
102  A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
103  if (!A)
104  return nullptr;
105  }
106  return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
107 }
108 
109 const TargetRegisterClass *
111  const MachineFunction &MF) const {
112  // Don't allow super-classes of GR8_NOREX. This class is only used after
113  // extracting sub_8bit_hi sub-registers. The H sub-registers cannot be copied
114  // to the full GR8 register class in 64-bit mode, so we cannot allow the
115  // reigster class inflation.
116  //
117  // The GR8_NOREX class is always used in a way that won't be constrained to a
118  // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
119  // full GR8 class.
120  if (RC == &X86::GR8_NOREXRegClass)
121  return RC;
122 
123  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
124 
125  const TargetRegisterClass *Super = RC;
127  do {
128  switch (Super->getID()) {
129  case X86::FR32RegClassID:
130  case X86::FR64RegClassID:
131  // If AVX-512 isn't supported we should only inflate to these classes.
132  if (!Subtarget.hasAVX512() &&
133  getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
134  return Super;
135  break;
136  case X86::VR128RegClassID:
137  case X86::VR256RegClassID:
138  // If VLX isn't supported we should only inflate to these classes.
139  if (!Subtarget.hasVLX() &&
140  getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
141  return Super;
142  break;
143  case X86::VR128XRegClassID:
144  case X86::VR256XRegClassID:
145  // If VLX isn't support we shouldn't inflate to these classes.
146  if (Subtarget.hasVLX() &&
147  getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
148  return Super;
149  break;
150  case X86::FR32XRegClassID:
151  case X86::FR64XRegClassID:
152  // If AVX-512 isn't support we shouldn't inflate to these classes.
153  if (Subtarget.hasAVX512() &&
154  getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
155  return Super;
156  break;
157  case X86::GR8RegClassID:
158  case X86::GR16RegClassID:
159  case X86::GR32RegClassID:
160  case X86::GR64RegClassID:
161  case X86::RFP32RegClassID:
162  case X86::RFP64RegClassID:
163  case X86::RFP80RegClassID:
164  case X86::VR512_0_15RegClassID:
165  case X86::VR512RegClassID:
166  // Don't return a super-class that would shrink the spill size.
167  // That can happen with the vector and float classes.
168  if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
169  return Super;
170  }
171  Super = *I++;
172  } while (Super);
173  return RC;
174 }
175 
176 const TargetRegisterClass *
178  unsigned Kind) const {
179  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
180  switch (Kind) {
181  default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
182  case 0: // Normal GPRs.
183  if (Subtarget.isTarget64BitLP64())
184  return &X86::GR64RegClass;
185  // If the target is 64bit but we have been told to use 32bit addresses,
186  // we can still use 64-bit register as long as we know the high bits
187  // are zeros.
188  // Reflect that in the returned register class.
189  if (Is64Bit) {
190  // When the target also allows 64-bit frame pointer and we do have a
191  // frame, this is fine to use it for the address accesses as well.
192  const X86FrameLowering *TFI = getFrameLowering(MF);
193  return TFI->hasFP(MF) && TFI->Uses64BitFramePtr
194  ? &X86::LOW32_ADDR_ACCESS_RBPRegClass
195  : &X86::LOW32_ADDR_ACCESSRegClass;
196  }
197  return &X86::GR32RegClass;
198  case 1: // Normal GPRs except the stack pointer (for encoding reasons).
199  if (Subtarget.isTarget64BitLP64())
200  return &X86::GR64_NOSPRegClass;
201  // NOSP does not contain RIP, so no special case here.
202  return &X86::GR32_NOSPRegClass;
203  case 2: // NOREX GPRs.
204  if (Subtarget.isTarget64BitLP64())
205  return &X86::GR64_NOREXRegClass;
206  return &X86::GR32_NOREXRegClass;
207  case 3: // NOREX GPRs except the stack pointer (for encoding reasons).
208  if (Subtarget.isTarget64BitLP64())
209  return &X86::GR64_NOREX_NOSPRegClass;
210  // NOSP does not contain RIP, so no special case here.
211  return &X86::GR32_NOREX_NOSPRegClass;
212  case 4: // Available for tailcall (not callee-saved GPRs).
213  return getGPRsForTailCall(MF);
214  }
215 }
216 
218  unsigned DefSubReg,
219  const TargetRegisterClass *SrcRC,
220  unsigned SrcSubReg) const {
221  // Prevent rewriting a copy where the destination size is larger than the
222  // input size. See PR41619.
223  // FIXME: Should this be factored into the base implementation somehow.
224  if (DefRC->hasSuperClassEq(&X86::GR64RegClass) && DefSubReg == 0 &&
225  SrcRC->hasSuperClassEq(&X86::GR64RegClass) && SrcSubReg == X86::sub_32bit)
226  return false;
227 
228  return TargetRegisterInfo::shouldRewriteCopySrc(DefRC, DefSubReg,
229  SrcRC, SrcSubReg);
230 }
231 
232 const TargetRegisterClass *
234  const Function &F = MF.getFunction();
235  if (IsWin64 || (F.getCallingConv() == CallingConv::Win64))
236  return &X86::GR64_TCW64RegClass;
237  else if (Is64Bit)
238  return &X86::GR64_TCRegClass;
239 
240  bool hasHipeCC = (F.getCallingConv() == CallingConv::HiPE);
241  if (hasHipeCC)
242  return &X86::GR32RegClass;
243  return &X86::GR32_TCRegClass;
244 }
245 
246 const TargetRegisterClass *
248  if (RC == &X86::CCRRegClass) {
249  if (Is64Bit)
250  return &X86::GR64RegClass;
251  else
252  return &X86::GR32RegClass;
253  }
254  return RC;
255 }
256 
257 unsigned
259  MachineFunction &MF) const {
260  const X86FrameLowering *TFI = getFrameLowering(MF);
261 
262  unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
263  switch (RC->getID()) {
264  default:
265  return 0;
266  case X86::GR32RegClassID:
267  return 4 - FPDiff;
268  case X86::GR64RegClassID:
269  return 12 - FPDiff;
270  case X86::VR128RegClassID:
271  return Is64Bit ? 10 : 4;
272  case X86::VR64RegClassID:
273  return 4;
274  }
275 }
276 
277 const MCPhysReg *
279  assert(MF && "MachineFunction required");
280 
281  const X86Subtarget &Subtarget = MF->getSubtarget<X86Subtarget>();
282  const Function &F = MF->getFunction();
283  bool HasSSE = Subtarget.hasSSE1();
284  bool HasAVX = Subtarget.hasAVX();
285  bool HasAVX512 = Subtarget.hasAVX512();
286  bool CallsEHReturn = MF->callsEHReturn();
287 
288  CallingConv::ID CC = F.getCallingConv();
289 
290  // If attribute NoCallerSavedRegisters exists then we set X86_INTR calling
291  // convention because it has the CSR list.
292  if (MF->getFunction().hasFnAttribute("no_caller_saved_registers"))
294 
295  // If atribute specified, override the CSRs normally specified by the
296  // calling convention and use the empty set instead.
297  if (MF->getFunction().hasFnAttribute("no_callee_saved_registers"))
298  return CSR_NoRegs_SaveList;
299 
300  switch (CC) {
301  case CallingConv::GHC:
302  case CallingConv::HiPE:
303  return CSR_NoRegs_SaveList;
304  case CallingConv::AnyReg:
305  if (HasAVX)
306  return CSR_64_AllRegs_AVX_SaveList;
307  return CSR_64_AllRegs_SaveList;
309  return CSR_64_RT_MostRegs_SaveList;
311  if (HasAVX)
312  return CSR_64_RT_AllRegs_AVX_SaveList;
313  return CSR_64_RT_AllRegs_SaveList;
315  if (Is64Bit)
316  return MF->getInfo<X86MachineFunctionInfo>()->isSplitCSR() ?
317  CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList;
318  break;
320  if (HasAVX512 && IsWin64)
321  return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
322  if (HasAVX512 && Is64Bit)
323  return CSR_64_Intel_OCL_BI_AVX512_SaveList;
324  if (HasAVX && IsWin64)
325  return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
326  if (HasAVX && Is64Bit)
327  return CSR_64_Intel_OCL_BI_AVX_SaveList;
328  if (!HasAVX && !IsWin64 && Is64Bit)
329  return CSR_64_Intel_OCL_BI_SaveList;
330  break;
331  }
332  case CallingConv::HHVM:
333  return CSR_64_HHVM_SaveList;
335  if (Is64Bit) {
336  if (IsWin64) {
337  return (HasSSE ? CSR_Win64_RegCall_SaveList :
338  CSR_Win64_RegCall_NoSSE_SaveList);
339  } else {
340  return (HasSSE ? CSR_SysV64_RegCall_SaveList :
341  CSR_SysV64_RegCall_NoSSE_SaveList);
342  }
343  } else {
344  return (HasSSE ? CSR_32_RegCall_SaveList :
345  CSR_32_RegCall_NoSSE_SaveList);
346  }
348  assert(!Is64Bit && "CFGuard check mechanism only used on 32-bit X86");
349  return (HasSSE ? CSR_Win32_CFGuard_Check_SaveList
350  : CSR_Win32_CFGuard_Check_NoSSE_SaveList);
351  case CallingConv::Cold:
352  if (Is64Bit)
353  return CSR_64_MostRegs_SaveList;
354  break;
355  case CallingConv::Win64:
356  if (!HasSSE)
357  return CSR_Win64_NoSSE_SaveList;
358  return CSR_Win64_SaveList;
360  if (!Is64Bit)
361  return CSR_32_SaveList;
362  return IsWin64 ? CSR_Win64_SwiftTail_SaveList : CSR_64_SwiftTail_SaveList;
364  if (CallsEHReturn)
365  return CSR_64EHRet_SaveList;
366  return CSR_64_SaveList;
368  if (Is64Bit) {
369  if (HasAVX512)
370  return CSR_64_AllRegs_AVX512_SaveList;
371  if (HasAVX)
372  return CSR_64_AllRegs_AVX_SaveList;
373  if (HasSSE)
374  return CSR_64_AllRegs_SaveList;
375  return CSR_64_AllRegs_NoSSE_SaveList;
376  } else {
377  if (HasAVX512)
378  return CSR_32_AllRegs_AVX512_SaveList;
379  if (HasAVX)
380  return CSR_32_AllRegs_AVX_SaveList;
381  if (HasSSE)
382  return CSR_32_AllRegs_SSE_SaveList;
383  return CSR_32_AllRegs_SaveList;
384  }
385  default:
386  break;
387  }
388 
389  if (Is64Bit) {
390  bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() &&
391  F.getAttributes().hasAttrSomewhere(Attribute::SwiftError);
392  if (IsSwiftCC)
393  return IsWin64 ? CSR_Win64_SwiftError_SaveList
394  : CSR_64_SwiftError_SaveList;
395 
396  if (IsWin64)
397  return HasSSE ? CSR_Win64_SaveList : CSR_Win64_NoSSE_SaveList;
398  if (CallsEHReturn)
399  return CSR_64EHRet_SaveList;
400  return CSR_64_SaveList;
401  }
402 
403  return CallsEHReturn ? CSR_32EHRet_SaveList : CSR_32_SaveList;
404 }
405 
407  const MachineFunction *MF) const {
408  assert(MF && "Invalid MachineFunction pointer.");
411  return CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList;
412  return nullptr;
413 }
414 
415 const uint32_t *
417  CallingConv::ID CC) const {
418  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
419  bool HasSSE = Subtarget.hasSSE1();
420  bool HasAVX = Subtarget.hasAVX();
421  bool HasAVX512 = Subtarget.hasAVX512();
422 
423  switch (CC) {
424  case CallingConv::GHC:
425  case CallingConv::HiPE:
426  return CSR_NoRegs_RegMask;
427  case CallingConv::AnyReg:
428  if (HasAVX)
429  return CSR_64_AllRegs_AVX_RegMask;
430  return CSR_64_AllRegs_RegMask;
432  return CSR_64_RT_MostRegs_RegMask;
434  if (HasAVX)
435  return CSR_64_RT_AllRegs_AVX_RegMask;
436  return CSR_64_RT_AllRegs_RegMask;
438  if (Is64Bit)
439  return CSR_64_TLS_Darwin_RegMask;
440  break;
442  if (HasAVX512 && IsWin64)
443  return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
444  if (HasAVX512 && Is64Bit)
445  return CSR_64_Intel_OCL_BI_AVX512_RegMask;
446  if (HasAVX && IsWin64)
447  return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
448  if (HasAVX && Is64Bit)
449  return CSR_64_Intel_OCL_BI_AVX_RegMask;
450  if (!HasAVX && !IsWin64 && Is64Bit)
451  return CSR_64_Intel_OCL_BI_RegMask;
452  break;
453  }
454  case CallingConv::HHVM:
455  return CSR_64_HHVM_RegMask;
457  if (Is64Bit) {
458  if (IsWin64) {
459  return (HasSSE ? CSR_Win64_RegCall_RegMask :
460  CSR_Win64_RegCall_NoSSE_RegMask);
461  } else {
462  return (HasSSE ? CSR_SysV64_RegCall_RegMask :
463  CSR_SysV64_RegCall_NoSSE_RegMask);
464  }
465  } else {
466  return (HasSSE ? CSR_32_RegCall_RegMask :
467  CSR_32_RegCall_NoSSE_RegMask);
468  }
470  assert(!Is64Bit && "CFGuard check mechanism only used on 32-bit X86");
471  return (HasSSE ? CSR_Win32_CFGuard_Check_RegMask
472  : CSR_Win32_CFGuard_Check_NoSSE_RegMask);
473  case CallingConv::Cold:
474  if (Is64Bit)
475  return CSR_64_MostRegs_RegMask;
476  break;
477  case CallingConv::Win64:
478  return CSR_Win64_RegMask;
480  if (!Is64Bit)
481  return CSR_32_RegMask;
482  return IsWin64 ? CSR_Win64_SwiftTail_RegMask : CSR_64_SwiftTail_RegMask;
484  return CSR_64_RegMask;
486  if (Is64Bit) {
487  if (HasAVX512)
488  return CSR_64_AllRegs_AVX512_RegMask;
489  if (HasAVX)
490  return CSR_64_AllRegs_AVX_RegMask;
491  if (HasSSE)
492  return CSR_64_AllRegs_RegMask;
493  return CSR_64_AllRegs_NoSSE_RegMask;
494  } else {
495  if (HasAVX512)
496  return CSR_32_AllRegs_AVX512_RegMask;
497  if (HasAVX)
498  return CSR_32_AllRegs_AVX_RegMask;
499  if (HasSSE)
500  return CSR_32_AllRegs_SSE_RegMask;
501  return CSR_32_AllRegs_RegMask;
502  }
503  default:
504  break;
505  }
506 
507  // Unlike getCalleeSavedRegs(), we don't have MMI so we can't check
508  // callsEHReturn().
509  if (Is64Bit) {
510  const Function &F = MF.getFunction();
511  bool IsSwiftCC = Subtarget.getTargetLowering()->supportSwiftError() &&
512  F.getAttributes().hasAttrSomewhere(Attribute::SwiftError);
513  if (IsSwiftCC)
514  return IsWin64 ? CSR_Win64_SwiftError_RegMask : CSR_64_SwiftError_RegMask;
515 
516  return IsWin64 ? CSR_Win64_RegMask : CSR_64_RegMask;
517  }
518 
519  return CSR_32_RegMask;
520 }
521 
522 const uint32_t*
524  return CSR_NoRegs_RegMask;
525 }
526 
528  return CSR_64_TLS_Darwin_RegMask;
529 }
530 
532  BitVector Reserved(getNumRegs());
533  const X86FrameLowering *TFI = getFrameLowering(MF);
534 
535  // Set the floating point control register as reserved.
536  Reserved.set(X86::FPCW);
537 
538  // Set the floating point status register as reserved.
539  Reserved.set(X86::FPSW);
540 
541  // Set the SIMD floating point control register as reserved.
542  Reserved.set(X86::MXCSR);
543 
544  // Set the stack-pointer register and its aliases as reserved.
545  for (const MCPhysReg &SubReg : subregs_inclusive(X86::RSP))
546  Reserved.set(SubReg);
547 
548  // Set the Shadow Stack Pointer as reserved.
549  Reserved.set(X86::SSP);
550 
551  // Set the instruction pointer register and its aliases as reserved.
552  for (const MCPhysReg &SubReg : subregs_inclusive(X86::RIP))
553  Reserved.set(SubReg);
554 
555  // Set the frame-pointer register and its aliases as reserved if needed.
556  if (TFI->hasFP(MF)) {
557  for (const MCPhysReg &SubReg : subregs_inclusive(X86::RBP))
558  Reserved.set(SubReg);
559  }
560 
561  // Set the base-pointer register and its aliases as reserved if needed.
562  if (hasBasePointer(MF)) {
564  const uint32_t *RegMask = getCallPreservedMask(MF, CC);
567  "Stack realignment in presence of dynamic allocas is not supported with"
568  "this calling convention.");
569 
571  for (const MCPhysReg &SubReg : subregs_inclusive(BasePtr))
572  Reserved.set(SubReg);
573  }
574 
575  // Mark the segment registers as reserved.
576  Reserved.set(X86::CS);
577  Reserved.set(X86::SS);
578  Reserved.set(X86::DS);
579  Reserved.set(X86::ES);
580  Reserved.set(X86::FS);
581  Reserved.set(X86::GS);
582 
583  // Mark the floating point stack registers as reserved.
584  for (unsigned n = 0; n != 8; ++n)
585  Reserved.set(X86::ST0 + n);
586 
587  // Reserve the registers that only exist in 64-bit mode.
588  if (!Is64Bit) {
589  // These 8-bit registers are part of the x86-64 extension even though their
590  // super-registers are old 32-bits.
591  Reserved.set(X86::SIL);
592  Reserved.set(X86::DIL);
593  Reserved.set(X86::BPL);
594  Reserved.set(X86::SPL);
595  Reserved.set(X86::SIH);
596  Reserved.set(X86::DIH);
597  Reserved.set(X86::BPH);
598  Reserved.set(X86::SPH);
599 
600  for (unsigned n = 0; n != 8; ++n) {
601  // R8, R9, ...
602  for (MCRegAliasIterator AI(X86::R8 + n, this, true); AI.isValid(); ++AI)
603  Reserved.set(*AI);
604 
605  // XMM8, XMM9, ...
606  for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
607  Reserved.set(*AI);
608  }
609  }
610  if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasAVX512()) {
611  for (unsigned n = 16; n != 32; ++n) {
612  for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
613  Reserved.set(*AI);
614  }
615  }
616 
617  assert(checkAllSuperRegsMarked(Reserved,
618  {X86::SIL, X86::DIL, X86::BPL, X86::SPL,
619  X86::SIH, X86::DIH, X86::BPH, X86::SPH}));
620  return Reserved;
621 }
622 
624  MCRegister Reg) const {
625  const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
626  const TargetRegisterInfo &TRI = *ST.getRegisterInfo();
627  auto IsSubReg = [&](MCRegister RegA, MCRegister RegB) {
628  return TRI.isSuperOrSubRegisterEq(RegA, RegB);
629  };
630 
631  if (!ST.is64Bit())
632  return llvm::any_of(
634  [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); }) ||
635  (ST.hasMMX() && X86::VR64RegClass.contains(Reg));
636 
638 
639  if (CC == CallingConv::X86_64_SysV && IsSubReg(X86::RAX, Reg))
640  return true;
641 
642  if (llvm::any_of(
643  SmallVector<MCRegister>{X86::RDX, X86::RCX, X86::R8, X86::R9},
644  [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); }))
645  return true;
646 
647  if (CC != CallingConv::Win64 &&
648  llvm::any_of(SmallVector<MCRegister>{X86::RDI, X86::RSI},
649  [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); }))
650  return true;
651 
652  if (ST.hasSSE1() &&
653  llvm::any_of(SmallVector<MCRegister>{X86::XMM0, X86::XMM1, X86::XMM2,
654  X86::XMM3, X86::XMM4, X86::XMM5,
655  X86::XMM6, X86::XMM7},
656  [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); }))
657  return true;
658 
659  return X86GenRegisterInfo::isArgumentRegister(MF, Reg);
660 }
661 
663  MCRegister PhysReg) const {
664  const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
665  const TargetRegisterInfo &TRI = *ST.getRegisterInfo();
666 
667  // Stack pointer.
668  if (TRI.isSuperOrSubRegisterEq(X86::RSP, PhysReg))
669  return true;
670 
671  // Don't use the frame pointer if it's being used.
672  const X86FrameLowering &TFI = *getFrameLowering(MF);
673  if (TFI.hasFP(MF) && TRI.isSuperOrSubRegisterEq(X86::RBP, PhysReg))
674  return true;
675 
676  return X86GenRegisterInfo::isFixedRegister(MF, PhysReg);
677 }
678 
680  // Check if the EFLAGS register is marked as live-out. This shouldn't happen,
681  // because the calling convention defines the EFLAGS register as NOT
682  // preserved.
683  //
684  // Unfortunatelly the EFLAGS show up as live-out after branch folding. Adding
685  // an assert to track this and clear the register afterwards to avoid
686  // unnecessary crashes during release builds.
687  assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
688  "EFLAGS are not live-out from a patchpoint.");
689 
690  // Also clean other registers that don't need preserving (IP).
691  for (auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
692  Mask[Reg / 32] &= ~(1U << (Reg % 32));
693 }
694 
695 //===----------------------------------------------------------------------===//
696 // Stack Frame Processing methods
697 //===----------------------------------------------------------------------===//
698 
699 static bool CantUseSP(const MachineFrameInfo &MFI) {
700  return MFI.hasVarSizedObjects() || MFI.hasOpaqueSPAdjustment();
701 }
702 
705  if (X86FI->hasPreallocatedCall())
706  return true;
707 
708  const MachineFrameInfo &MFI = MF.getFrameInfo();
709 
710  if (!EnableBasePointer)
711  return false;
712 
713  // When we need stack realignment, we can't address the stack from the frame
714  // pointer. When we have dynamic allocas or stack-adjusting inline asm, we
715  // can't address variables from the stack pointer. MS inline asm can
716  // reference locals while also adjusting the stack pointer. When we can't
717  // use both the SP and the FP, we need a separate base pointer register.
718  bool CantUseFP = hasStackRealignment(MF);
719  return CantUseFP && CantUseSP(MFI);
720 }
721 
724  return false;
725 
726  const MachineFrameInfo &MFI = MF.getFrameInfo();
727  const MachineRegisterInfo *MRI = &MF.getRegInfo();
728 
729  // Stack realignment requires a frame pointer. If we already started
730  // register allocation with frame pointer elimination, it is too late now.
731  if (!MRI->canReserveReg(FramePtr))
732  return false;
733 
734  // If a base pointer is necessary. Check that it isn't too late to reserve
735  // it.
736  if (CantUseSP(MFI))
737  return MRI->canReserveReg(BasePtr);
738  return true;
739 }
740 
741 // tryOptimizeLEAtoMOV - helper function that tries to replace a LEA instruction
742 // of the form 'lea (%esp), %ebx' --> 'mov %esp, %ebx'.
743 // TODO: In this case we should be really trying first to entirely eliminate
744 // this instruction which is a plain copy.
746  MachineInstr &MI = *II;
747  unsigned Opc = II->getOpcode();
748  // Check if this is a LEA of the form 'lea (%esp), %ebx'
749  if ((Opc != X86::LEA32r && Opc != X86::LEA64r && Opc != X86::LEA64_32r) ||
750  MI.getOperand(2).getImm() != 1 ||
751  MI.getOperand(3).getReg() != X86::NoRegister ||
752  MI.getOperand(4).getImm() != 0 ||
753  MI.getOperand(5).getReg() != X86::NoRegister)
754  return false;
755  Register BasePtr = MI.getOperand(1).getReg();
756  // In X32 mode, ensure the base-pointer is a 32-bit operand, so the LEA will
757  // be replaced with a 32-bit operand MOV which will zero extend the upper
758  // 32-bits of the super register.
759  if (Opc == X86::LEA64_32r)
760  BasePtr = getX86SubSuperRegister(BasePtr, 32);
761  Register NewDestReg = MI.getOperand(0).getReg();
762  const X86InstrInfo *TII =
763  MI.getParent()->getParent()->getSubtarget<X86Subtarget>().getInstrInfo();
764  TII->copyPhysReg(*MI.getParent(), II, MI.getDebugLoc(), NewDestReg, BasePtr,
765  MI.getOperand(1).isKill());
766  MI.eraseFromParent();
767  return true;
768 }
769 
771  switch (MI.getOpcode()) {
772  case X86::CATCHRET:
773  case X86::CLEANUPRET:
774  return true;
775  default:
776  return false;
777  }
778  llvm_unreachable("impossible");
779 }
780 
781 void
783  int SPAdj, unsigned FIOperandNum,
784  RegScavenger *RS) const {
785  MachineInstr &MI = *II;
786  MachineBasicBlock &MBB = *MI.getParent();
787  MachineFunction &MF = *MBB.getParent();
789  bool IsEHFuncletEpilogue = MBBI == MBB.end() ? false
791  const X86FrameLowering *TFI = getFrameLowering(MF);
792  int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
793 
794  // Determine base register and offset.
795  int FIOffset;
796  Register BasePtr;
797  if (MI.isReturn()) {
798  assert((!hasStackRealignment(MF) ||
800  "Return instruction can only reference SP relative frame objects");
801  FIOffset =
802  TFI->getFrameIndexReferenceSP(MF, FrameIndex, BasePtr, 0).getFixed();
803  } else if (TFI->Is64Bit && (MBB.isEHFuncletEntry() || IsEHFuncletEpilogue)) {
804  FIOffset = TFI->getWin64EHFrameIndexRef(MF, FrameIndex, BasePtr);
805  } else {
806  FIOffset = TFI->getFrameIndexReference(MF, FrameIndex, BasePtr).getFixed();
807  }
808 
809  // LOCAL_ESCAPE uses a single offset, with no register. It only works in the
810  // simple FP case, and doesn't work with stack realignment. On 32-bit, the
811  // offset is from the traditional base pointer location. On 64-bit, the
812  // offset is from the SP at the end of the prologue, not the FP location. This
813  // matches the behavior of llvm.frameaddress.
814  unsigned Opc = MI.getOpcode();
815  if (Opc == TargetOpcode::LOCAL_ESCAPE) {
816  MachineOperand &FI = MI.getOperand(FIOperandNum);
817  FI.ChangeToImmediate(FIOffset);
818  return;
819  }
820 
821  // For LEA64_32r when BasePtr is 32-bits (X32) we can use full-size 64-bit
822  // register as source operand, semantic is the same and destination is
823  // 32-bits. It saves one byte per lea in code since 0x67 prefix is avoided.
824  // Don't change BasePtr since it is used later for stack adjustment.
825  Register MachineBasePtr = BasePtr;
826  if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
827  MachineBasePtr = getX86SubSuperRegister(BasePtr, 64);
828 
829  // This must be part of a four operand memory reference. Replace the
830  // FrameIndex with base register. Add an offset to the offset.
831  MI.getOperand(FIOperandNum).ChangeToRegister(MachineBasePtr, false);
832 
833  if (BasePtr == StackPtr)
834  FIOffset += SPAdj;
835 
836  // The frame index format for stackmaps and patchpoints is different from the
837  // X86 format. It only has a FI and an offset.
838  if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
839  assert(BasePtr == FramePtr && "Expected the FP as base register");
840  int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
841  MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
842  return;
843  }
844 
845  if (MI.getOperand(FIOperandNum+3).isImm()) {
846  // Offset is a 32-bit integer.
847  int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
848  int Offset = FIOffset + Imm;
849  assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
850  "Requesting 64-bit offset in 32-bit immediate!");
851  if (Offset != 0 || !tryOptimizeLEAtoMOV(II))
852  MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
853  } else {
854  // Offset is symbolic. This is extremely rare.
855  uint64_t Offset = FIOffset +
856  (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
857  MI.getOperand(FIOperandNum + 3).setOffset(Offset);
858  }
859 }
860 
863  const MachineFunction *MF = MBB.getParent();
864  if (MF->callsEHReturn())
865  return 0;
866 
867  const TargetRegisterClass &AvailableRegs = *getGPRsForTailCall(*MF);
868 
869  if (MBBI == MBB.end())
870  return 0;
871 
872  switch (MBBI->getOpcode()) {
873  default:
874  return 0;
875  case TargetOpcode::PATCHABLE_RET:
876  case X86::RET:
877  case X86::RET32:
878  case X86::RET64:
879  case X86::RETI32:
880  case X86::RETI64:
881  case X86::TCRETURNdi:
882  case X86::TCRETURNri:
883  case X86::TCRETURNmi:
884  case X86::TCRETURNdi64:
885  case X86::TCRETURNri64:
886  case X86::TCRETURNmi64:
887  case X86::EH_RETURN:
888  case X86::EH_RETURN64: {
890  for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
891  MachineOperand &MO = MBBI->getOperand(I);
892  if (!MO.isReg() || MO.isDef())
893  continue;
894  Register Reg = MO.getReg();
895  if (!Reg)
896  continue;
897  for (MCRegAliasIterator AI(Reg, this, true); AI.isValid(); ++AI)
898  Uses.insert(*AI);
899  }
900 
901  for (auto CS : AvailableRegs)
902  if (!Uses.count(CS) && CS != X86::RIP && CS != X86::RSP && CS != X86::ESP)
903  return CS;
904  }
905  }
906 
907  return 0;
908 }
909 
911  const X86FrameLowering *TFI = getFrameLowering(MF);
912  return TFI->hasFP(MF) ? FramePtr : StackPtr;
913 }
914 
915 unsigned
917  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
918  Register FrameReg = getFrameRegister(MF);
919  if (Subtarget.isTarget64BitILP32())
920  FrameReg = getX86SubSuperRegister(FrameReg, 32);
921  return FrameReg;
922 }
923 
924 unsigned
926  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
927  Register StackReg = getStackRegister();
928  if (Subtarget.isTarget64BitILP32())
929  StackReg = getX86SubSuperRegister(StackReg, 32);
930  return StackReg;
931 }
932 
933 static ShapeT getTileShape(Register VirtReg, VirtRegMap *VRM,
934  const MachineRegisterInfo *MRI) {
935  if (VRM->hasShape(VirtReg))
936  return VRM->getShape(VirtReg);
937 
938  const MachineOperand &Def = *MRI->def_begin(VirtReg);
939  MachineInstr *MI = const_cast<MachineInstr *>(Def.getParent());
940  unsigned OpCode = MI->getOpcode();
941  switch (OpCode) {
942  default:
943  llvm_unreachable("Unexpected machine instruction on tile register!");
944  break;
945  case X86::COPY: {
946  Register SrcReg = MI->getOperand(1).getReg();
947  ShapeT Shape = getTileShape(SrcReg, VRM, MRI);
948  VRM->assignVirt2Shape(VirtReg, Shape);
949  return Shape;
950  }
951  // We only collect the tile shape that is defined.
952  case X86::PTILELOADDV:
953  case X86::PTILELOADDT1V:
954  case X86::PTDPBSSDV:
955  case X86::PTDPBSUDV:
956  case X86::PTDPBUSDV:
957  case X86::PTDPBUUDV:
958  case X86::PTILEZEROV:
959  case X86::PTDPBF16PSV:
960  MachineOperand &MO1 = MI->getOperand(1);
961  MachineOperand &MO2 = MI->getOperand(2);
962  ShapeT Shape(&MO1, &MO2, MRI);
963  VRM->assignVirt2Shape(VirtReg, Shape);
964  return Shape;
965  }
966 }
967 
969  ArrayRef<MCPhysReg> Order,
971  const MachineFunction &MF,
972  const VirtRegMap *VRM,
973  const LiveRegMatrix *Matrix) const {
974  const MachineRegisterInfo *MRI = &MF.getRegInfo();
975  const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
976  bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
977  VirtReg, Order, Hints, MF, VRM, Matrix);
978 
979  if (RC.getID() != X86::TILERegClassID)
980  return BaseImplRetVal;
981 
982  ShapeT VirtShape = getTileShape(VirtReg, const_cast<VirtRegMap *>(VRM), MRI);
983  auto AddHint = [&](MCPhysReg PhysReg) {
984  Register VReg = Matrix->getOneVReg(PhysReg);
985  if (VReg == MCRegister::NoRegister) { // Not allocated yet
986  Hints.push_back(PhysReg);
987  return;
988  }
989  ShapeT PhysShape = getTileShape(VReg, const_cast<VirtRegMap *>(VRM), MRI);
990  if (PhysShape == VirtShape)
991  Hints.push_back(PhysReg);
992  };
993 
994  SmallSet<MCPhysReg, 4> CopyHints;
995  CopyHints.insert(Hints.begin(), Hints.end());
996  Hints.clear();
997  for (auto Hint : CopyHints) {
998  if (RC.contains(Hint) && !MRI->isReserved(Hint))
999  AddHint(Hint);
1000  }
1001  for (MCPhysReg PhysReg : Order) {
1002  if (!CopyHints.count(PhysReg) && RC.contains(PhysReg) &&
1003  !MRI->isReserved(PhysReg))
1004  AddHint(PhysReg);
1005  }
1006 
1007 #define DEBUG_TYPE "tile-hint"
1008  LLVM_DEBUG({
1009  dbgs() << "Hints for virtual register " << format_hex(VirtReg, 8) << "\n";
1010  for (auto Hint : Hints) {
1011  dbgs() << "tmm" << Hint << ",";
1012  }
1013  dbgs() << "\n";
1014  });
1015 #undef DEBUG_TYPE
1016 
1017  return true;
1018 }
i
i
Definition: README.txt:29
LiveRegMatrix.h
llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:354
TileShapeInfo.h
llvm::X86_MC::getDwarfRegFlavour
unsigned getDwarfRegFlavour(const Triple &TT, bool isEH)
Definition: X86MCTargetDesc.cpp:59
llvm::N86::EBX
@ EBX
Definition: X86MCTargetDesc.h:51
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm::MachineRegisterInfo::def_begin
def_iterator def_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:392
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:72
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
TargetFrameLowering.h
X86Subtarget.h
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::Function
Definition: Function.h:60
llvm::X86FrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Definition: X86FrameLowering.cpp:95
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:344
llvm::MachineBasicBlock::isEHFuncletEntry
bool isEHFuncletEntry() const
Returns true if this is the entry block of an EH funclet.
Definition: MachineBasicBlock.h:575
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::X86Subtarget
Definition: X86Subtarget.h:52
llvm::X86RegisterInfo::isFixedRegister
bool isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const override
Returns true if PhysReg is a fixed register.
Definition: X86RegisterInfo.cpp:662
ErrorHandling.h
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::X86RegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: X86RegisterInfo.cpp:910
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::X86Subtarget::isTarget64BitILP32
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
Definition: X86Subtarget.h:179
llvm::X86RegisterInfo::getRegPressureLimit
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
Definition: X86RegisterInfo.cpp:258
llvm::MachineRegisterInfo::canReserveReg
bool canReserveReg(MCRegister PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
Definition: MachineRegisterInfo.h:907
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::X86RegisterInfo::eliminateFrameIndex
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Definition: X86RegisterInfo.cpp:782
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1886
TargetInstrInfo.h
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:136
llvm::MCRegister::NoRegister
static constexpr unsigned NoRegister
Definition: MCRegister.h:43
llvm::ShapeT
Definition: TileShapeInfo.h:30
STLExtras.h
llvm::X86RegisterInfo::getCalleeSavedRegsViaCopy
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
Definition: X86RegisterInfo.cpp:406
llvm::N86::ECX
@ ECX
Definition: X86MCTargetDesc.h:51
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::N86::EAX
@ EAX
Definition: X86MCTargetDesc.h:51
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
F
#define F(x, y, z)
Definition: MD5.cpp:55
MachineRegisterInfo.h
Uses
SmallPtrSet< MachineInstr *, 2 > Uses
Definition: ARMLowOverheadLoops.cpp:585
llvm::X86RegisterInfo::getGPRsForTailCall
const TargetRegisterClass * getGPRsForTailCall(const MachineFunction &MF) const
getGPRsForTailCall - Returns a register class with registers that can be used in forming tail calls.
Definition: X86RegisterInfo.cpp:233
llvm::X86RegisterInfo::getDarwinTLSCallPreservedMask
const uint32_t * getDarwinTLSCallPreservedMask() const
Definition: X86RegisterInfo.cpp:527
X86FrameLowering.h
X86GenRegisterInfo
llvm::CallingConv::Intel_OCL_BI
@ Intel_OCL_BI
Intel_OCL_BI - Calling conventions for Intel OpenCL built-ins.
Definition: CallingConv.h:155
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::X86MachineFunctionInfo::hasPreallocatedCall
bool hasPreallocatedCall() const
Definition: X86MachineFunctionInfo.h:216
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
CommandLine.h
llvm::X86RegisterInfo::getLargestLegalSuperClass
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
Definition: X86RegisterInfo.cpp:110
X86MachineFunctionInfo.h
llvm::TargetRegisterClass::contains
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
Definition: TargetRegisterInfo.h:94
llvm::TargetRegisterInfo::canRealignStack
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
Definition: TargetRegisterInfo.cpp:479
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
TargetMachine.h
llvm::X86FrameLowering::getWin64EHFrameIndexRef
int getWin64EHFrameIndexRef(const MachineFunction &MF, int FI, Register &SPReg) const
Definition: X86FrameLowering.cpp:2462
Constants.h
llvm::CallingConv::PreserveAll
@ PreserveAll
Definition: CallingConv.h:70
llvm::X86FrameLowering::getFrameIndexReferenceSP
StackOffset getFrameIndexReferenceSP(const MachineFunction &MF, int FI, Register &SPReg, int Adjustment) const
Definition: X86FrameLowering.cpp:2478
llvm::X86RegisterInfo::getNoPreservedMask
const uint32_t * getNoPreservedMask() const override
Definition: X86RegisterInfo.cpp:523
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:754
llvm::ISD::CATCHRET
@ CATCHRET
CATCHRET - Represents a return from a catch block funclet.
Definition: ISDOpcodes.h:1044
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:925
int
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
Definition: README.txt:536
CantUseSP
static bool CantUseSP(const MachineFrameInfo &MFI)
Definition: X86RegisterInfo.cpp:699
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::X86RegisterInfo::getBaseRegister
Register getBaseRegister() const
Definition: X86RegisterInfo.h:148
false
Definition: StackSlotColoring.cpp:141
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::MachineOperand::ChangeToImmediate
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
Definition: MachineOperand.cpp:154
llvm::X86Subtarget::hasSSE1
bool hasSSE1() const
Definition: X86Subtarget.h:199
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::TargetRegisterClass::hasSuperClassEq
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
Definition: TargetRegisterInfo.h:139
llvm::X86RegisterInfo::shouldRewriteCopySrc
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
Definition: X86RegisterInfo.cpp:217
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
BitVector.h
llvm::N86::EDX
@ EDX
Definition: X86MCTargetDesc.h:51
llvm::BitVector
Definition: BitVector.h:75
llvm::MachineFrameInfo::isFixedObjectIndex
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Definition: MachineFrameInfo.h:680
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
Type.h
llvm::CallingConv::CFGuard_Check
@ CFGuard_Check
Special calling convention on Windows for calling the Control Guard Check ICall funtion.
Definition: CallingConv.h:87
llvm::X86Subtarget::isTarget64BitLP64
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Definition: X86Subtarget.h:184
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:642
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::X86AS::SS
@ SS
Definition: X86.h:193
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:625
llvm::cl::opt< bool >
llvm::X86RegisterInfo::getRegAllocationHints
bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
Definition: X86RegisterInfo.cpp:968
llvm::MachineOperand::clobbersPhysReg
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Definition: MachineOperand.h:626
llvm::X86RegisterInfo::getSubClassWithSubReg
const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const override
Definition: X86RegisterInfo.cpp:85
llvm::isInt< 32 >
constexpr bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:373
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineFunction::callsEHReturn
bool callsEHReturn() const
Definition: MachineFunction.h:1086
uint64_t
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:238
llvm::X86FrameLowering
Definition: X86FrameLowering.h:28
VirtRegMap.h
llvm::getX86SubSuperRegister
MCRegister getX86SubSuperRegister(MCRegister, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
Definition: X86MCTargetDesc.cpp:913
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
isFuncletReturnInstr
static bool isFuncletReturnInstr(MachineInstr &MI)
Definition: X86RegisterInfo.cpp:770
llvm::ISD::CLEANUPRET
@ CLEANUPRET
CLEANUPRET - Represents a return from a cleanup block funclet.
Definition: ISDOpcodes.h:1048
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::X86RegisterInfo::getPtrSizedFrameRegister
unsigned getPtrSizedFrameRegister(const MachineFunction &MF) const
Definition: X86RegisterInfo.cpp:916
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::TargetRegisterInfo::getRegAllocationHints
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
Definition: TargetRegisterInfo.cpp:422
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
llvm::X86RegisterInfo::X86RegisterInfo
X86RegisterInfo(const Triple &TT)
Definition: X86RegisterInfo.cpp:48
MachineFunctionPass.h
llvm::X86_MC::initLLVMToSEHAndCVRegMapping
void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI)
Definition: X86MCTargetDesc.cpp:166
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::X86AS::FS
@ FS
Definition: X86.h:192
llvm::X86Subtarget::getTargetLowering
const X86TargetLowering * getTargetLowering() const override
Definition: X86Subtarget.h:124
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:672
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:234
llvm::X86RegisterInfo::isArgumentRegister
bool isArgumentRegister(const MachineFunction &MF, MCRegister Reg) const override
isArgumentReg - Returns true if Reg can be used as an argument to a function.
Definition: X86RegisterInfo.cpp:623
llvm::VirtRegMap::hasShape
bool hasShape(Register virtReg) const
Definition: VirtRegMap.h:116
llvm::X86RegisterInfo::getCallPreservedMask
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
Definition: X86RegisterInfo.cpp:416
llvm::X86MachineFunctionInfo
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
Definition: X86MachineFunctionInfo.h:25
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
EnableBasePointer
static cl::opt< bool > EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames"))
llvm::SIInstrFlags::DS
@ DS
Definition: SIDefines.h:60
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::VirtRegMap::assignVirt2Shape
void assignVirt2Shape(Register virtReg, ShapeT shape)
Definition: VirtRegMap.h:125
llvm::X86InstrInfo
Definition: X86InstrInfo.h:138
TargetOptions.h
llvm::VirtRegMap::getShape
ShapeT getShape(Register virtReg) const
Definition: VirtRegMap.h:120
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:238
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::N86::ESP
@ ESP
Definition: X86MCTargetDesc.h:51
Matrix
Live Register Matrix
Definition: LiveRegMatrix.cpp:44
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1624
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::X86RegisterInfo::adjustStackMapLiveOutMask
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
Definition: X86RegisterInfo.cpp:679
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
getTileShape
static ShapeT getTileShape(Register VirtReg, VirtRegMap *VRM, const MachineRegisterInfo *MRI)
Definition: X86RegisterInfo.cpp:933
llvm::CallingConv::X86_64_SysV
@ X86_64_SysV
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
Definition: CallingConv.h:159
llvm::CallingConv::PreserveMost
@ PreserveMost
Definition: CallingConv.h:66
uint32_t
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:374
llvm::X86RegisterInfo::getMatchingSuperRegClass
const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const override
getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register ...
Definition: X86RegisterInfo.cpp:97
llvm::X86RegisterInfo::canRealignStack
bool canRealignStack(const MachineFunction &MF) const override
Definition: X86RegisterInfo.cpp:722
llvm::SmallSet::insert
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:182
llvm::X86RegisterInfo::getSEHRegNum
int getSEHRegNum(unsigned i) const
Definition: X86RegisterInfo.cpp:80
llvm::StackOffset::getFixed
static StackOffset getFixed(ScalarTy Fixed)
Definition: TypeSize.h:143
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::TargetRegisterInfo::shouldRewriteCopySrc
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
Definition: TargetRegisterInfo.cpp:413
llvm::X86Subtarget::hasAVX512
bool hasAVX512() const
Definition: X86Subtarget.h:207
llvm::CallingConv::Win64
@ Win64
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:169
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:622
uint16_t
llvm::X86RegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
getCalleeSavedRegs - Return a null-terminated list of all of the callee-save registers on this target...
Definition: X86RegisterInfo.cpp:278
llvm::X86RegisterInfo::findDeadCallerSavedReg
unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI) const
findDeadCallerSavedReg - Return a caller-saved register that isn't live when it reaches the "return" ...
Definition: X86RegisterInfo.cpp:861
llvm::TargetRegisterClass::getSuperClasses
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
Definition: TargetRegisterInfo.h:177
MachineFrameInfo.h
llvm::X86AS::GS
@ GS
Definition: X86.h:191
llvm::ARCISD::RET
@ RET
Definition: ARCISelLowering.h:52
llvm::X86RegisterInfo::hasBasePointer
bool hasBasePointer(const MachineFunction &MF) const
Definition: X86RegisterInfo.cpp:703
Function.h
llvm::CallingConv::HiPE
@ HiPE
Definition: CallingConv.h:55
llvm::TargetRegisterClass::sc_iterator
const TargetRegisterClass *const * sc_iterator
Definition: TargetRegisterInfo.h:49
llvm::ISD::EH_RETURN
@ EH_RETURN
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin,...
Definition: ISDOpcodes.h:135
llvm::SmallVectorImpl::clear
void clear()
Definition: SmallVector.h:591
tryOptimizeLEAtoMOV
static bool tryOptimizeLEAtoMOV(MachineBasicBlock::iterator II)
Definition: X86RegisterInfo.cpp:745
llvm::X86Subtarget::hasAVX
bool hasAVX() const
Definition: X86Subtarget.h:205
llvm::CallingConv::X86_INTR
@ X86_INTR
X86_INTR - x86 hardware interrupt context.
Definition: CallingConv.h:189
X86RegisterInfo.h
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
false
Function Alias Analysis false
Definition: AliasAnalysis.cpp:848
llvm::X86RegisterInfo::getCrossCopyRegClass
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or...
Definition: X86RegisterInfo.cpp:247
llvm::MCRegAliasIterator::isValid
bool isValid() const
Definition: MCRegisterInfo.h:813
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
llvm::CallingConv::CXX_FAST_TLS
@ CXX_FAST_TLS
Definition: CallingConv.h:76
llvm::X86FrameLowering::Is64Bit
bool Is64Bit
Is64Bit implies that x86_64 instructions are available.
Definition: X86FrameLowering.h:41
llvm::X86FrameLowering::Uses64BitFramePtr
bool Uses64BitFramePtr
True if the 64-bit frame or stack pointer should be used.
Definition: X86FrameLowering.h:48
llvm::SmallVectorImpl< MCPhysReg >
llvm::X86MachineFunctionInfo::isSplitCSR
bool isSplitCSR() const
Definition: X86MachineFunctionInfo.h:207
llvm::X86RegisterInfo::getReservedRegs
BitVector getReservedRegs(const MachineFunction &MF) const override
getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a ...
Definition: X86RegisterInfo.cpp:531
llvm::X86RegisterInfo::getStackRegister
Register getStackRegister() const
Definition: X86RegisterInfo.h:147
llvm::MachineFrameInfo::hasOpaqueSPAdjustment
bool hasOpaqueSPAdjustment() const
Returns true if the function contains opaque dynamic stack adjustments.
Definition: MachineFrameInfo.h:609
llvm::MCRegisterInfo::isSuperOrSubRegisterEq
bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register or sub-register of RegA or if RegB == RegA.
Definition: MCRegisterInfo.h:580
llvm::cl::desc
Definition: CommandLine.h:405
llvm::X86TargetLowering::supportSwiftError
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
Definition: X86ISelLowering.cpp:56130
n
The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports that transformation probably isn t worthwhile The transformation can also easily be made to work with non zero equality for n
Definition: README.txt:685
MachineFunction.h
llvm::N86::ESI
@ ESI
Definition: X86MCTargetDesc.h:51
llvm::CallingConv::AnyReg
@ AnyReg
Definition: CallingConv.h:62
X86
Unrolling by would eliminate the &in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various including etc On X86
Definition: README.txt:568
llvm::CallingConv::GHC
@ GHC
Definition: CallingConv.h:51
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::format_hex
FormattedNumber format_hex(uint64_t N, unsigned Width, bool Upper=false)
format_hex - Output N as a fixed width hexadecimal.
Definition: Format.h:186
llvm::HexagonInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Emit instructions to copy a pair of physical registers.
Definition: HexagonInstrInfo.cpp:854
llvm::CallingConv::HHVM
@ HHVM
Calling convention used by HipHop Virtual Machine (HHVM) to perform calls to and from translation cac...
Definition: CallingConv.h:179
llvm::X86FrameLowering::getFrameIndexReference
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
Definition: X86FrameLowering.cpp:2380
llvm::CallingConv::X86_RegCall
@ X86_RegCall
Register calling convention used for parameters transfer optimization.
Definition: CallingConv.h:219
llvm::CallingConv::SwiftTail
@ SwiftTail
SwiftTail - This follows the Swift calling convention in how arguments are passed but guarantees tail...
Definition: CallingConv.h:92
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:280
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::X86RegisterInfo::getPtrSizedStackRegister
unsigned getPtrSizedStackRegister(const MachineFunction &MF) const
Definition: X86RegisterInfo.cpp:925
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:788
llvm::CallingConv::Cold
@ Cold
Definition: CallingConv.h:48
llvm::X86RegisterInfo::getPointerRegClass
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Returns a TargetRegisterClass used for pointer values.
Definition: X86RegisterInfo.cpp:177
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
SmallSet.h
llvm::LiveRegMatrix
Definition: LiveRegMatrix.h:40