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41 #define GET_REGINFO_TARGET_DESC
42 #include "X86GenRegisterInfo.inc"
46 cl::desc(
"Enable use of a base pointer for complex stack frames"));
52 (TT.isArch64Bit() ?
X86::RIP :
X86::EIP)) {
56 Is64Bit = TT.isArch64Bit();
57 IsWin64 = Is64Bit && TT.isOSWindows();
67 bool Use64BitReg = !TT.isX32();
68 StackPtr = Use64BitReg ? X86::RSP :
X86::ESP;
69 FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
70 BasePtr = Use64BitReg ? X86::RBX :
X86::EBX;
81 return getEncodingValue(
i);
89 if (!Is64Bit && Idx == X86::sub_8bit)
90 Idx = X86::sub_8bit_hi;
93 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
99 unsigned SubIdx)
const {
101 if (!Is64Bit && SubIdx == X86::sub_8bit) {
102 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
106 return X86GenRegisterInfo::getMatchingSuperRegClass(A,
B, SubIdx);
120 if (RC == &X86::GR8_NOREXRegClass)
128 switch (Super->getID()) {
129 case X86::FR32RegClassID:
130 case X86::FR64RegClassID:
133 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
136 case X86::VR128RegClassID:
137 case X86::VR256RegClassID:
139 if (!Subtarget.hasVLX() &&
140 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
143 case X86::VR128XRegClassID:
144 case X86::VR256XRegClassID:
146 if (Subtarget.hasVLX() &&
147 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
150 case X86::FR32XRegClassID:
151 case X86::FR64XRegClassID:
154 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
157 case X86::GR8RegClassID:
158 case X86::GR16RegClassID:
159 case X86::GR32RegClassID:
160 case X86::GR64RegClassID:
161 case X86::RFP32RegClassID:
162 case X86::RFP64RegClassID:
163 case X86::RFP80RegClassID:
164 case X86::VR512_0_15RegClassID:
165 case X86::VR512RegClassID:
168 if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
178 unsigned Kind)
const {
184 return &X86::GR64RegClass;
194 ? &X86::LOW32_ADDR_ACCESS_RBPRegClass
195 : &X86::LOW32_ADDR_ACCESSRegClass;
197 return &X86::GR32RegClass;
200 return &X86::GR64_NOSPRegClass;
202 return &X86::GR32_NOSPRegClass;
205 return &X86::GR64_NOREXRegClass;
206 return &X86::GR32_NOREXRegClass;
209 return &X86::GR64_NOREX_NOSPRegClass;
211 return &X86::GR32_NOREX_NOSPRegClass;
220 unsigned SrcSubReg)
const {
225 SrcRC->
hasSuperClassEq(&X86::GR64RegClass) && SrcSubReg == X86::sub_32bit)
236 return &X86::GR64_TCW64RegClass;
238 return &X86::GR64_TCRegClass;
242 return &X86::GR32RegClass;
243 return &X86::GR32_TCRegClass;
248 if (RC == &X86::CCRRegClass) {
250 return &X86::GR64RegClass;
252 return &X86::GR32RegClass;
262 unsigned FPDiff = TFI->
hasFP(MF) ? 1 : 0;
263 switch (RC->
getID()) {
266 case X86::GR32RegClassID:
268 case X86::GR64RegClassID:
270 case X86::VR128RegClassID:
271 return Is64Bit ? 10 : 4;
272 case X86::VR64RegClassID:
279 assert(MF &&
"MachineFunction required");
283 bool HasSSE = Subtarget.
hasSSE1();
284 bool HasAVX = Subtarget.
hasAVX();
298 return CSR_NoRegs_SaveList;
303 return CSR_NoRegs_SaveList;
306 return CSR_64_AllRegs_AVX_SaveList;
307 return CSR_64_AllRegs_SaveList;
309 return CSR_64_RT_MostRegs_SaveList;
312 return CSR_64_RT_AllRegs_AVX_SaveList;
313 return CSR_64_RT_AllRegs_SaveList;
317 CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList;
320 if (HasAVX512 && IsWin64)
321 return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
322 if (HasAVX512 && Is64Bit)
323 return CSR_64_Intel_OCL_BI_AVX512_SaveList;
324 if (HasAVX && IsWin64)
325 return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
326 if (HasAVX && Is64Bit)
327 return CSR_64_Intel_OCL_BI_AVX_SaveList;
328 if (!HasAVX && !IsWin64 && Is64Bit)
329 return CSR_64_Intel_OCL_BI_SaveList;
333 return CSR_64_HHVM_SaveList;
337 return (HasSSE ? CSR_Win64_RegCall_SaveList :
338 CSR_Win64_RegCall_NoSSE_SaveList);
340 return (HasSSE ? CSR_SysV64_RegCall_SaveList :
341 CSR_SysV64_RegCall_NoSSE_SaveList);
344 return (HasSSE ? CSR_32_RegCall_SaveList :
345 CSR_32_RegCall_NoSSE_SaveList);
348 assert(!Is64Bit &&
"CFGuard check mechanism only used on 32-bit X86");
349 return (HasSSE ? CSR_Win32_CFGuard_Check_SaveList
350 : CSR_Win32_CFGuard_Check_NoSSE_SaveList);
353 return CSR_64_MostRegs_SaveList;
357 return CSR_Win64_NoSSE_SaveList;
358 return CSR_Win64_SaveList;
361 return CSR_32_SaveList;
362 return IsWin64 ? CSR_Win64_SwiftTail_SaveList : CSR_64_SwiftTail_SaveList;
365 return CSR_64EHRet_SaveList;
366 return CSR_64_SaveList;
370 return CSR_64_AllRegs_AVX512_SaveList;
372 return CSR_64_AllRegs_AVX_SaveList;
374 return CSR_64_AllRegs_SaveList;
375 return CSR_64_AllRegs_NoSSE_SaveList;
378 return CSR_32_AllRegs_AVX512_SaveList;
380 return CSR_32_AllRegs_AVX_SaveList;
382 return CSR_32_AllRegs_SSE_SaveList;
383 return CSR_32_AllRegs_SaveList;
391 F.getAttributes().hasAttrSomewhere(Attribute::SwiftError);
393 return IsWin64 ? CSR_Win64_SwiftError_SaveList
394 : CSR_64_SwiftError_SaveList;
397 return HasSSE ? CSR_Win64_SaveList : CSR_Win64_NoSSE_SaveList;
399 return CSR_64EHRet_SaveList;
400 return CSR_64_SaveList;
403 return CallsEHReturn ? CSR_32EHRet_SaveList : CSR_32_SaveList;
408 assert(MF &&
"Invalid MachineFunction pointer.");
411 return CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList;
419 bool HasSSE = Subtarget.
hasSSE1();
420 bool HasAVX = Subtarget.
hasAVX();
426 return CSR_NoRegs_RegMask;
429 return CSR_64_AllRegs_AVX_RegMask;
430 return CSR_64_AllRegs_RegMask;
432 return CSR_64_RT_MostRegs_RegMask;
435 return CSR_64_RT_AllRegs_AVX_RegMask;
436 return CSR_64_RT_AllRegs_RegMask;
439 return CSR_64_TLS_Darwin_RegMask;
442 if (HasAVX512 && IsWin64)
443 return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
444 if (HasAVX512 && Is64Bit)
445 return CSR_64_Intel_OCL_BI_AVX512_RegMask;
446 if (HasAVX && IsWin64)
447 return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
448 if (HasAVX && Is64Bit)
449 return CSR_64_Intel_OCL_BI_AVX_RegMask;
450 if (!HasAVX && !IsWin64 && Is64Bit)
451 return CSR_64_Intel_OCL_BI_RegMask;
455 return CSR_64_HHVM_RegMask;
459 return (HasSSE ? CSR_Win64_RegCall_RegMask :
460 CSR_Win64_RegCall_NoSSE_RegMask);
462 return (HasSSE ? CSR_SysV64_RegCall_RegMask :
463 CSR_SysV64_RegCall_NoSSE_RegMask);
466 return (HasSSE ? CSR_32_RegCall_RegMask :
467 CSR_32_RegCall_NoSSE_RegMask);
470 assert(!Is64Bit &&
"CFGuard check mechanism only used on 32-bit X86");
471 return (HasSSE ? CSR_Win32_CFGuard_Check_RegMask
472 : CSR_Win32_CFGuard_Check_NoSSE_RegMask);
475 return CSR_64_MostRegs_RegMask;
478 return CSR_Win64_RegMask;
481 return CSR_32_RegMask;
482 return IsWin64 ? CSR_Win64_SwiftTail_RegMask : CSR_64_SwiftTail_RegMask;
484 return CSR_64_RegMask;
488 return CSR_64_AllRegs_AVX512_RegMask;
490 return CSR_64_AllRegs_AVX_RegMask;
492 return CSR_64_AllRegs_RegMask;
493 return CSR_64_AllRegs_NoSSE_RegMask;
496 return CSR_32_AllRegs_AVX512_RegMask;
498 return CSR_32_AllRegs_AVX_RegMask;
500 return CSR_32_AllRegs_SSE_RegMask;
501 return CSR_32_AllRegs_RegMask;
512 F.getAttributes().hasAttrSomewhere(Attribute::SwiftError);
514 return IsWin64 ? CSR_Win64_SwiftError_RegMask : CSR_64_SwiftError_RegMask;
516 return IsWin64 ? CSR_Win64_RegMask : CSR_64_RegMask;
519 return CSR_32_RegMask;
524 return CSR_NoRegs_RegMask;
528 return CSR_64_TLS_Darwin_RegMask;
536 Reserved.
set(X86::FPCW);
539 Reserved.
set(X86::FPSW);
542 Reserved.
set(X86::MXCSR);
549 Reserved.
set(X86::SSP);
556 if (TFI->
hasFP(MF)) {
567 "Stack realignment in presence of dynamic allocas is not supported with"
568 "this calling convention.");
576 Reserved.
set(X86::CS);
579 Reserved.
set(X86::ES);
584 for (
unsigned n = 0;
n != 8; ++
n)
585 Reserved.
set(X86::ST0 +
n);
591 Reserved.
set(X86::SIL);
592 Reserved.
set(X86::DIL);
593 Reserved.
set(X86::BPL);
594 Reserved.
set(X86::SPL);
595 Reserved.
set(X86::SIH);
596 Reserved.
set(X86::DIH);
597 Reserved.
set(X86::BPH);
598 Reserved.
set(X86::SPH);
600 for (
unsigned n = 0;
n != 8; ++
n) {
611 for (
unsigned n = 16;
n != 32; ++
n) {
617 assert(checkAllSuperRegsMarked(Reserved,
618 {X86::SIL, X86::DIL, X86::BPL, X86::SPL,
619 X86::SIH, X86::DIH, X86::BPH, X86::SPH}));
635 (
ST.hasMMX() && X86::VR64RegClass.contains(
Reg));
654 X86::XMM3, X86::XMM4, X86::XMM5,
655 X86::XMM6, X86::XMM7},
659 return X86GenRegisterInfo::isArgumentRegister(MF,
Reg);
676 return X86GenRegisterInfo::isFixedRegister(MF, PhysReg);
687 assert(!(
Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
688 "EFLAGS are not live-out from a patchpoint.");
691 for (
auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
718 bool CantUseFP = hasStackRealignment(MF);
747 unsigned Opc = II->getOpcode();
749 if ((Opc != X86::LEA32r && Opc != X86::LEA64r && Opc != X86::LEA64_32r) ||
750 MI.getOperand(2).getImm() != 1 ||
751 MI.getOperand(3).getReg() != X86::NoRegister ||
752 MI.getOperand(4).getImm() != 0 ||
753 MI.getOperand(5).getReg() != X86::NoRegister)
759 if (Opc == X86::LEA64_32r)
761 Register NewDestReg =
MI.getOperand(0).getReg();
763 MI.getParent()->getParent()->getSubtarget<
X86Subtarget>().getInstrInfo();
765 MI.getOperand(1).isKill());
766 MI.eraseFromParent();
771 switch (
MI.getOpcode()) {
783 int SPAdj,
unsigned FIOperandNum,
792 int FrameIndex =
MI.getOperand(FIOperandNum).getIndex();
798 assert((!hasStackRealignment(MF) ||
800 "Return instruction can only reference SP relative frame objects");
814 unsigned Opc =
MI.getOpcode();
815 if (Opc == TargetOpcode::LOCAL_ESCAPE) {
826 if (Opc == X86::LEA64_32r && X86::GR32RegClass.
contains(BasePtr))
831 MI.getOperand(FIOperandNum).ChangeToRegister(MachineBasePtr,
false);
833 if (BasePtr == StackPtr)
838 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
839 assert(BasePtr == FramePtr &&
"Expected the FP as base register");
840 int64_t Offset =
MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
841 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
845 if (
MI.getOperand(FIOperandNum+3).isImm()) {
847 int Imm = (
int)(
MI.getOperand(FIOperandNum + 3).getImm());
848 int Offset = FIOffset +
Imm;
850 "Requesting 64-bit offset in 32-bit immediate!");
852 MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
856 (
uint64_t)
MI.getOperand(FIOperandNum+3).getOffset();
857 MI.getOperand(FIOperandNum + 3).setOffset(Offset);
872 switch (
MBBI->getOpcode()) {
875 case TargetOpcode::PATCHABLE_RET:
881 case X86::TCRETURNdi:
882 case X86::TCRETURNri:
883 case X86::TCRETURNmi:
884 case X86::TCRETURNdi64:
885 case X86::TCRETURNri64:
886 case X86::TCRETURNmi64:
888 case X86::EH_RETURN64: {
890 for (
unsigned I = 0,
E =
MBBI->getNumOperands();
I !=
E; ++
I) {
901 for (
auto CS : AvailableRegs)
902 if (!
Uses.count(CS) && CS != X86::RIP && CS != X86::RSP && CS !=
X86::ESP)
912 return TFI->
hasFP(MF) ? FramePtr : StackPtr;
940 unsigned OpCode =
MI->getOpcode();
952 case X86::PTILELOADDV:
953 case X86::PTILELOADDT1V:
958 case X86::PTILEZEROV:
959 case X86::PTDPBF16PSV:
977 VirtReg, Order, Hints, MF, VRM,
Matrix);
979 if (RC.
getID() != X86::TILERegClassID)
980 return BaseImplRetVal;
986 Hints.push_back(PhysReg);
990 if (PhysShape == VirtShape)
991 Hints.push_back(PhysReg);
995 CopyHints.
insert(Hints.begin(), Hints.end());
997 for (
auto Hint : CopyHints) {
1002 if (!CopyHints.count(PhysReg) && RC.
contains(PhysReg) &&
1007 #define DEBUG_TYPE "tile-hint"
1009 dbgs() <<
"Hints for virtual register " <<
format_hex(VirtReg, 8) <<
"\n";
1010 for (
auto Hint : Hints) {
1011 dbgs() <<
"tmm" << Hint <<
",";
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getDwarfRegFlavour(const Triple &TT, bool isEH)
def_iterator def_begin(Register RegNo) const
unsigned getID() const
Return the register class ID number.
This is an optimization pass for GlobalISel generic memory operations.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
bool isEHFuncletEntry() const
Returns true if this is the entry block of an EH funclet.
return AArch64::GPR64RegClass contains(Reg)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
bool isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const override
Returns true if PhysReg is a fixed register.
Register getFrameRegister(const MachineFunction &MF) const override
Reg
All possible values of the reg field in the ModR/M byte.
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
bool canReserveReg(MCRegister PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
Triple - Helper class for working with autoconf configuration names.
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
static constexpr unsigned NoRegister
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
unsigned const TargetRegisterInfo * TRI
SmallPtrSet< MachineInstr *, 2 > Uses
const TargetRegisterClass * getGPRsForTailCall(const MachineFunction &MF) const
getGPRsForTailCall - Returns a register class with registers that can be used in forming tail calls.
const uint32_t * getDarwinTLSCallPreservedMask() const
@ Intel_OCL_BI
Intel_OCL_BI - Calling conventions for Intel OpenCL built-ins.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool hasPreallocatedCall() const
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
int getWin64EHFrameIndexRef(const MachineFunction &MF, int FI, Register &SPReg) const
StackOffset getFrameIndexReferenceSP(const MachineFunction &MF, int FI, Register &SPReg, int Adjustment) const
const uint32_t * getNoPreservedMask() const override
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
@ CATCHRET
CATCHRET - Represents a return from a catch block funclet.
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
static bool CantUseSP(const MachineFrameInfo &MFI)
Register getBaseRegister() const
const HexagonInstrInfo * TII
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
MachineOperand class - Representation of each machine instruction operand.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ CFGuard_Check
Special calling convention on Windows for calling the Control Guard Check ICall funtion.
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const override
constexpr bool isInt< 32 >(int64_t x)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
bool callsEHReturn() const
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
MCRegister getX86SubSuperRegister(MCRegister, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
static bool isFuncletReturnInstr(MachineInstr &MI)
@ CLEANUPRET
CLEANUPRET - Represents a return from a cleanup block funclet.
unsigned getPtrSizedFrameRegister(const MachineFunction &MF) const
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
initializer< Ty > init(const Ty &Val)
X86RegisterInfo(const Triple &TT)
void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const X86TargetLowering * getTargetLowering() const override
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool isArgumentRegister(const MachineFunction &MF, MCRegister Reg) const override
isArgumentReg - Returns true if Reg can be used as an argument to a function.
bool hasShape(Register virtReg) const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
Register getReg() const
getReg - Returns the register number.
static cl::opt< bool > EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames"))
void assignVirt2Shape(Register virtReg, ShapeT shape)
ShapeT getShape(Register virtReg) const
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
MachineBasicBlock MachineBasicBlock::iterator MBBI
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static ShapeT getTileShape(Register VirtReg, VirtRegMap *VRM, const MachineRegisterInfo *MRI)
@ X86_64_SysV
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const override
getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register ...
bool canRealignStack(const MachineFunction &MF) const override
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
int getSEHRegNum(unsigned i) const
static StackOffset getFixed(ScalarTy Fixed)
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
@ Win64
The C convention as implemented on Windows/x86-64 and AArch64.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
getCalleeSavedRegs - Return a null-terminated list of all of the callee-save registers on this target...
unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI) const
findDeadCallerSavedReg - Return a caller-saved register that isn't live when it reaches the "return" ...
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
bool hasBasePointer(const MachineFunction &MF) const
const TargetRegisterClass *const * sc_iterator
@ EH_RETURN
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin,...
static bool tryOptimizeLEAtoMOV(MachineBasicBlock::iterator II)
@ X86_INTR
X86_INTR - x86 hardware interrupt context.
Function Alias Analysis false
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool Is64Bit
Is64Bit implies that x86_64 instructions are available.
bool Uses64BitFramePtr
True if the 64-bit frame or stack pointer should be used.
BitVector getReservedRegs(const MachineFunction &MF) const override
getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a ...
Register getStackRegister() const
bool hasOpaqueSPAdjustment() const
Returns true if the function contains opaque dynamic stack adjustments.
bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register or sub-register of RegA or if RegB == RegA.
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports that transformation probably isn t worthwhile The transformation can also easily be made to work with non zero equality for n
Unrolling by would eliminate the &in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various including etc On X86
FormattedNumber format_hex(uint64_t N, unsigned Width, bool Upper=false)
format_hex - Output N as a fixed width hexadecimal.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Emit instructions to copy a pair of physical registers.
@ HHVM
Calling convention used by HipHop Virtual Machine (HHVM) to perform calls to and from translation cac...
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
@ X86_RegCall
Register calling convention used for parameters transfer optimization.
@ SwiftTail
SwiftTail - This follows the Swift calling convention in how arguments are passed but guarantees tail...
unsigned getPtrSizedStackRegister(const MachineFunction &MF) const
MCRegAliasIterator enumerates all registers aliasing Reg.
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Returns a TargetRegisterClass used for pointer values.
Wrapper class representing physical registers. Should be passed by value.