41#define GET_REGINFO_TARGET_DESC
42#include "X86GenRegisterInfo.inc"
46 cl::desc(
"Enable use of a base pointer for complex stack frames"));
51 cl::desc(
"Disable two address hints for register "
56 X86_MC::getDwarfRegFlavour(TT,
false),
57 X86_MC::getDwarfRegFlavour(TT,
true),
58 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
62 Is64Bit = TT.isArch64Bit();
63 IsWin64 = Is64Bit && TT.isOSWindows();
73 bool Use64BitReg = !TT.isX32();
74 StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
75 FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
76 BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
87 return getEncodingValue(i);
95 if (!Is64Bit &&
Idx == X86::sub_8bit)
96 Idx = X86::sub_8bit_hi;
99 return X86GenRegisterInfo::getSubClassWithSubReg(RC,
Idx);
105 unsigned SubIdx)
const {
107 if (!Is64Bit && SubIdx == X86::sub_8bit) {
108 A = X86GenRegisterInfo::getSubClassWithSubReg(
A, X86::sub_8bit_hi);
112 return X86GenRegisterInfo::getMatchingSuperRegClass(
A,
B, SubIdx);
126 if (RC == &X86::GR8_NOREXRegClass)
134 switch (Super->getID()) {
135 case X86::FR32RegClassID:
136 case X86::FR64RegClassID:
139 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
142 case X86::VR128RegClassID:
143 case X86::VR256RegClassID:
145 if (!Subtarget.hasVLX() &&
146 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
149 case X86::VR128XRegClassID:
150 case X86::VR256XRegClassID:
152 if (Subtarget.hasVLX() &&
153 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
156 case X86::FR32XRegClassID:
157 case X86::FR64XRegClassID:
160 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
163 case X86::GR8RegClassID:
164 case X86::GR16RegClassID:
165 case X86::GR32RegClassID:
166 case X86::GR64RegClassID:
167 case X86::GR8_NOREX2RegClassID:
168 case X86::GR16_NOREX2RegClassID:
169 case X86::GR32_NOREX2RegClassID:
170 case X86::GR64_NOREX2RegClassID:
171 case X86::RFP32RegClassID:
172 case X86::RFP64RegClassID:
173 case X86::RFP80RegClassID:
174 case X86::VR512_0_15RegClassID:
175 case X86::VR512RegClassID:
178 if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
188 unsigned Kind)
const {
194 return &X86::GR64RegClass;
204 ? &X86::LOW32_ADDR_ACCESS_RBPRegClass
205 : &X86::LOW32_ADDR_ACCESSRegClass;
207 return &X86::GR32RegClass;
210 return &X86::GR64_NOSPRegClass;
212 return &X86::GR32_NOSPRegClass;
215 return &X86::GR64_NOREXRegClass;
216 return &X86::GR32_NOREXRegClass;
219 return &X86::GR64_NOREX_NOSPRegClass;
221 return &X86::GR32_NOREX_NOSPRegClass;
230 unsigned SrcSubReg)
const {
235 SrcRC->
hasSuperClassEq(&X86::GR64RegClass) && SrcSubReg == X86::sub_32bit)
246 return &X86::GR64_TCW64RegClass;
248 return &X86::GR64_TCRegClass;
252 return &X86::GR32RegClass;
253 return &X86::GR32_TCRegClass;
258 if (RC == &X86::CCRRegClass) {
260 return &X86::GR64RegClass;
262 return &X86::GR32RegClass;
272 unsigned FPDiff = TFI->
hasFP(MF) ? 1 : 0;
273 switch (RC->
getID()) {
276 case X86::GR32RegClassID:
278 case X86::GR64RegClassID:
280 case X86::VR128RegClassID:
281 return Is64Bit ? 10 : 4;
282 case X86::VR64RegClassID:
289 assert(MF &&
"MachineFunction required");
293 bool HasSSE = Subtarget.
hasSSE1();
294 bool HasAVX = Subtarget.
hasAVX();
308 return CSR_NoRegs_SaveList;
313 return CSR_NoRegs_SaveList;
316 return CSR_64_AllRegs_AVX_SaveList;
317 return CSR_64_AllRegs_SaveList;
319 return IsWin64 ? CSR_Win64_RT_MostRegs_SaveList
320 : CSR_64_RT_MostRegs_SaveList;
323 return CSR_64_RT_AllRegs_AVX_SaveList;
324 return CSR_64_RT_AllRegs_SaveList;
326 return CSR_64_NoneRegs_SaveList;
330 CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList;
333 if (HasAVX512 && IsWin64)
334 return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
335 if (HasAVX512 && Is64Bit)
336 return CSR_64_Intel_OCL_BI_AVX512_SaveList;
337 if (HasAVX && IsWin64)
338 return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
339 if (HasAVX && Is64Bit)
340 return CSR_64_Intel_OCL_BI_AVX_SaveList;
341 if (!HasAVX && !IsWin64 && Is64Bit)
342 return CSR_64_Intel_OCL_BI_SaveList;
348 return (HasSSE ? CSR_Win64_RegCall_SaveList :
349 CSR_Win64_RegCall_NoSSE_SaveList);
351 return (HasSSE ? CSR_SysV64_RegCall_SaveList :
352 CSR_SysV64_RegCall_NoSSE_SaveList);
355 return (HasSSE ? CSR_32_RegCall_SaveList :
356 CSR_32_RegCall_NoSSE_SaveList);
359 assert(!Is64Bit &&
"CFGuard check mechanism only used on 32-bit X86");
360 return (HasSSE ? CSR_Win32_CFGuard_Check_SaveList
361 : CSR_Win32_CFGuard_Check_NoSSE_SaveList);
364 return CSR_64_MostRegs_SaveList;
368 return CSR_Win64_NoSSE_SaveList;
369 return CSR_Win64_SaveList;
372 return CSR_32_SaveList;
373 return IsWin64 ? CSR_Win64_SwiftTail_SaveList : CSR_64_SwiftTail_SaveList;
376 return CSR_64EHRet_SaveList;
377 return CSR_64_SaveList;
381 return CSR_64_AllRegs_AVX512_SaveList;
383 return CSR_64_AllRegs_AVX_SaveList;
385 return CSR_64_AllRegs_SaveList;
386 return CSR_64_AllRegs_NoSSE_SaveList;
389 return CSR_32_AllRegs_AVX512_SaveList;
391 return CSR_32_AllRegs_AVX_SaveList;
393 return CSR_32_AllRegs_SSE_SaveList;
394 return CSR_32_AllRegs_SaveList;
402 F.getAttributes().hasAttrSomewhere(Attribute::SwiftError);
404 return IsWin64 ? CSR_Win64_SwiftError_SaveList
405 : CSR_64_SwiftError_SaveList;
408 return HasSSE ? CSR_Win64_SaveList : CSR_Win64_NoSSE_SaveList;
410 return CSR_64EHRet_SaveList;
411 return CSR_64_SaveList;
414 return CallsEHReturn ? CSR_32EHRet_SaveList : CSR_32_SaveList;
419 assert(MF &&
"Invalid MachineFunction pointer.");
422 return CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList;
430 bool HasSSE = Subtarget.
hasSSE1();
431 bool HasAVX = Subtarget.
hasAVX();
437 return CSR_NoRegs_RegMask;
440 return CSR_64_AllRegs_AVX_RegMask;
441 return CSR_64_AllRegs_RegMask;
443 return IsWin64 ? CSR_Win64_RT_MostRegs_RegMask : CSR_64_RT_MostRegs_RegMask;
446 return CSR_64_RT_AllRegs_AVX_RegMask;
447 return CSR_64_RT_AllRegs_RegMask;
449 return CSR_64_NoneRegs_RegMask;
452 return CSR_64_TLS_Darwin_RegMask;
455 if (HasAVX512 && IsWin64)
456 return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
457 if (HasAVX512 && Is64Bit)
458 return CSR_64_Intel_OCL_BI_AVX512_RegMask;
459 if (HasAVX && IsWin64)
460 return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
461 if (HasAVX && Is64Bit)
462 return CSR_64_Intel_OCL_BI_AVX_RegMask;
463 if (!HasAVX && !IsWin64 && Is64Bit)
464 return CSR_64_Intel_OCL_BI_RegMask;
470 return (HasSSE ? CSR_Win64_RegCall_RegMask :
471 CSR_Win64_RegCall_NoSSE_RegMask);
473 return (HasSSE ? CSR_SysV64_RegCall_RegMask :
474 CSR_SysV64_RegCall_NoSSE_RegMask);
477 return (HasSSE ? CSR_32_RegCall_RegMask :
478 CSR_32_RegCall_NoSSE_RegMask);
481 assert(!Is64Bit &&
"CFGuard check mechanism only used on 32-bit X86");
482 return (HasSSE ? CSR_Win32_CFGuard_Check_RegMask
483 : CSR_Win32_CFGuard_Check_NoSSE_RegMask);
486 return CSR_64_MostRegs_RegMask;
489 return CSR_Win64_RegMask;
492 return CSR_32_RegMask;
493 return IsWin64 ? CSR_Win64_SwiftTail_RegMask : CSR_64_SwiftTail_RegMask;
495 return CSR_64_RegMask;
499 return CSR_64_AllRegs_AVX512_RegMask;
501 return CSR_64_AllRegs_AVX_RegMask;
503 return CSR_64_AllRegs_RegMask;
504 return CSR_64_AllRegs_NoSSE_RegMask;
507 return CSR_32_AllRegs_AVX512_RegMask;
509 return CSR_32_AllRegs_AVX_RegMask;
511 return CSR_32_AllRegs_SSE_RegMask;
512 return CSR_32_AllRegs_RegMask;
523 F.getAttributes().hasAttrSomewhere(Attribute::SwiftError);
525 return IsWin64 ? CSR_Win64_SwiftError_RegMask : CSR_64_SwiftError_RegMask;
527 return IsWin64 ? CSR_Win64_RegMask : CSR_64_RegMask;
530 return CSR_32_RegMask;
535 return CSR_NoRegs_RegMask;
539 return CSR_64_TLS_Darwin_RegMask;
567 if (TFI->
hasFP(MF)) {
578 "Stack realignment in presence of dynamic allocas is not supported with"
579 "this calling convention.");
595 for (
unsigned n = 0; n != 8; ++n)
611 for (
unsigned n = 0; n != 8; ++n) {
622 for (
unsigned n = 0; n != 16; ++n) {
631 Reserved.set(X86::R16, X86::R31WH + 1);
641 {X86::SIL, X86::DIL, X86::BPL, X86::SPL,
642 X86::SIH, X86::DIH, X86::BPH, X86::SPH}));
658 static_assert((X86::R15WH + 1 == X86::YMM0) && (X86::YMM15 + 1 == X86::K0) &&
659 (X86::K6_K7 + 1 == X86::TMMCFG) &&
660 (X86::TMM7 + 1 == X86::R16) &&
661 (X86::R31WH + 1 == X86::NUM_TARGET_REGS),
662 "Register number may be incorrect");
666 return X86::NUM_TARGET_REGS;
668 return X86::TMM7 + 1;
670 return X86::K6_K7 + 1;
672 return X86::YMM15 + 1;
673 return X86::R15WH + 1;
681 return TRI.isSuperOrSubRegisterEq(RegA, RegB);
687 [&](
MCRegister &RegA) {
return IsSubReg(RegA, Reg); }) ||
688 (ST.hasMMX() && X86::VR64RegClass.contains(Reg));
697 [&](
MCRegister &RegA) {
return IsSubReg(RegA, Reg); }))
702 [&](
MCRegister &RegA) {
return IsSubReg(RegA, Reg); }))
707 X86::XMM3, X86::XMM4, X86::XMM5,
708 X86::XMM6, X86::XMM7},
709 [&](
MCRegister &RegA) {
return IsSubReg(RegA, Reg); }))
712 return X86GenRegisterInfo::isArgumentRegister(MF, Reg);
721 if (
TRI.isSuperOrSubRegisterEq(X86::RSP, PhysReg))
726 if (TFI.
hasFP(MF) &&
TRI.isSuperOrSubRegisterEq(X86::RBP, PhysReg))
729 return X86GenRegisterInfo::isFixedRegister(MF, PhysReg);
733 return RC->
getID() == X86::TILERegClassID;
744 assert(!(Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
745 "EFLAGS are not live-out from a patchpoint.");
748 for (
auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
749 Mask[Reg / 32] &= ~(1U << (Reg % 32));
780 bool CantUseFP = hasStackRealignment(MF);
793 if (!
MRI->canReserveReg(FramePtr))
799 return MRI->canReserveReg(BasePtr);
816 unsigned Opc =
II->getOpcode();
818 if ((Opc != X86::LEA32r && Opc != X86::LEA64r && Opc != X86::LEA64_32r) ||
819 MI.getOperand(2).getImm() != 1 ||
820 MI.getOperand(3).getReg() != X86::NoRegister ||
821 MI.getOperand(4).getImm() != 0 ||
822 MI.getOperand(5).getReg() != X86::NoRegister)
828 if (Opc == X86::LEA64_32r)
830 Register NewDestReg =
MI.getOperand(0).getReg();
832 MI.getParent()->getParent()->getSubtarget<
X86Subtarget>().getInstrInfo();
834 MI.getOperand(1).isKill());
835 MI.eraseFromParent();
840 switch (
MI.getOpcode()) {
842 case X86::CLEANUPRET:
851 unsigned FIOperandNum,
853 int FIOffset)
const {
855 unsigned Opc =
MI.getOpcode();
856 if (Opc == TargetOpcode::LOCAL_ESCAPE) {
862 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg,
false);
866 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
867 assert(BasePtr == FramePtr &&
"Expected the FP as base register");
868 int64_t
Offset =
MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
869 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(
Offset);
873 if (
MI.getOperand(FIOperandNum + 3).isImm()) {
875 int Imm = (int)(
MI.getOperand(FIOperandNum + 3).getImm());
876 int Offset = FIOffset + Imm;
877 assert((!Is64Bit || isInt<32>((
long long)FIOffset + Imm)) &&
878 "Requesting 64-bit offset in 32-bit immediate!");
880 MI.getOperand(FIOperandNum + 3).ChangeToImmediate(
Offset);
884 FIOffset + (
uint64_t)
MI.getOperand(FIOperandNum + 3).getOffset();
885 MI.getOperand(FIOperandNum + 3).setOffset(
Offset);
891 int SPAdj,
unsigned FIOperandNum,
900 int FrameIndex =
MI.getOperand(FIOperandNum).getIndex();
906 assert((!hasStackRealignment(MF) ||
908 "Return instruction can only reference SP relative frame objects");
922 unsigned Opc =
MI.getOpcode();
923 if (Opc == TargetOpcode::LOCAL_ESCAPE) {
934 if (Opc == X86::LEA64_32r && X86::GR32RegClass.
contains(BasePtr))
939 MI.getOperand(FIOperandNum).ChangeToRegister(MachineBasePtr,
false);
941 if (BasePtr == StackPtr)
946 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
947 assert(BasePtr == FramePtr &&
"Expected the FP as base register");
948 int64_t
Offset =
MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
949 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(
Offset);
953 if (
MI.getOperand(FIOperandNum+3).isImm()) {
955 int Imm = (int)(
MI.getOperand(FIOperandNum + 3).getImm());
956 int Offset = FIOffset + Imm;
957 assert((!Is64Bit || isInt<32>((
long long)FIOffset + Imm)) &&
958 "Requesting 64-bit offset in 32-bit immediate!");
960 MI.getOperand(FIOperandNum + 3).ChangeToImmediate(
Offset);
964 (
uint64_t)
MI.getOperand(FIOperandNum+3).getOffset();
965 MI.getOperand(FIOperandNum + 3).setOffset(
Offset);
981 switch (
MBBI->getOpcode()) {
984 case TargetOpcode::PATCHABLE_RET:
990 case X86::TCRETURNdi:
991 case X86::TCRETURNri:
992 case X86::TCRETURNmi:
993 case X86::TCRETURNdi64:
994 case X86::TCRETURNri64:
995 case X86::TCRETURNmi64:
997 case X86::EH_RETURN64: {
1000 if (!MO.isReg() || MO.isDef())
1009 for (
auto CS : AvailableRegs)
1010 if (!
Uses.count(CS) && CS != X86::RIP && CS != X86::RSP && CS != X86::ESP)
1020 return TFI->
hasFP(MF) ? FramePtr : StackPtr;
1048 unsigned OpCode =
MI->getOpcode();
1054 Register SrcReg =
MI->getOperand(1).getReg();
1060 case X86::PTILELOADDV:
1061 case X86::PTILELOADDT1V:
1062 case X86::PTDPBSSDV:
1063 case X86::PTDPBSUDV:
1064 case X86::PTDPBUSDV:
1065 case X86::PTDPBUUDV:
1066 case X86::PTILEZEROV:
1067 case X86::PTDPBF16PSV:
1068 case X86::PTDPFP16PSV:
1069 case X86::PTCMMIMFP16PSV:
1070 case X86::PTCMMRLFP16PSV:
1088 VirtReg, Order, Hints, MF, VRM,
Matrix);
1095 return BaseImplRetVal;
1097 if (
ID != X86::TILERegClassID) {
1099 !
TRI.isGeneralPurposeRegisterClass(&RC))
1100 return BaseImplRetVal;
1109 if (PhysReg && !
MRI->isReserved(PhysReg) && !
is_contained(Hints, PhysReg))
1110 TwoAddrHints.
insert(PhysReg);
1115 for (
auto &MO :
MRI->reg_nodbg_operands(VirtReg)) {
1119 unsigned OpIdx =
MI.getOperandNo(&MO);
1122 TryAddNDDHint(
MI.getOperand(1));
1123 if (
MI.isCommutable()) {
1125 TryAddNDDHint(
MI.getOperand(2));
1127 }
else if (OpIdx == 1) {
1128 TryAddNDDHint(
MI.getOperand(0));
1129 }
else if (
MI.isCommutable() && OpIdx == 2) {
1130 TryAddNDDHint(
MI.getOperand(0));
1135 if (TwoAddrHints.
count(OrderReg))
1138 return BaseImplRetVal;
1149 if (PhysShape == VirtShape)
1156 for (
auto Hint : CopyHints) {
1162 !
MRI->isReserved(PhysReg))
1166#define DEBUG_TYPE "tile-hint"
1168 dbgs() <<
"Hints for virtual register " <<
format_hex(VirtReg, 8) <<
"\n";
1169 for (
auto Hint : Hints) {
1170 dbgs() <<
"tmm" << Hint <<
",";
unsigned const MachineRegisterInfo * MRI
static bool isFuncletReturnInstr(const MachineInstr &MI)
MachineBasicBlock MachineBasicBlock::iterator MBBI
This file implements the BitVector class.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
Rewrite Partial Register Uses
const HexagonInstrInfo * TII
static cl::opt< bool > EnableBasePointer("m68k-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames"))
static bool CantUseSP(const MachineFrameInfo &MFI)
unsigned const TargetRegisterInfo * TRI
uint64_t IntrinsicInst * II
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallSet class.
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
static cl::opt< bool > EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames"))
static bool tryOptimizeLEAtoMOV(MachineBasicBlock::iterator II)
static cl::opt< bool > DisableRegAllocNDDHints("x86-disable-regalloc-hints-for-ndd", cl::Hidden, cl::init(false), cl::desc("Disable two address hints for register " "allocation"))
static ShapeT getTileShape(Register VirtReg, VirtRegMap *VRM, const MachineRegisterInfo *MRI)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Emit instructions to copy a pair of physical registers.
MCRegAliasIterator enumerates all registers aliasing Reg.
Wrapper class representing physical registers. Should be passed by value.
static constexpr unsigned NoRegister
bool isEHFuncletEntry() const
Returns true if this is the entry block of an EH funclet.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
bool hasOpaqueSPAdjustment() const
Returns true if the function contains opaque dynamic stack adjustments.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool callsEHReturn() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
static constexpr bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
std::pair< const_iterator, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
static StackOffset getFixed(int64_t Fixed)
const TargetRegisterClass *const * sc_iterator
unsigned getID() const
Return the register class ID number.
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
virtual bool shouldRealignStack(const MachineFunction &MF) const
True if storage within the function requires the stack pointer to be aligned more than the normal cal...
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
Triple - Helper class for working with autoconf configuration names.
bool hasShape(Register virtReg) const
ShapeT getShape(Register virtReg) const
MCRegister getPhys(Register virtReg) const
returns the physical register mapped to the specified virtual register
void assignVirt2Shape(Register virtReg, ShapeT shape)
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
StackOffset getFrameIndexReferenceSP(const MachineFunction &MF, int FI, Register &SPReg, int Adjustment) const
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
bool Is64Bit
Is64Bit implies that x86_64 instructions are available.
bool Uses64BitFramePtr
True if the 64-bit frame or stack pointer should be used.
int getWin64EHFrameIndexRef(const MachineFunction &MF, int FI, Register &SPReg) const
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
bool hasPreallocatedCall() const
MachineInstr * getStackPtrSaveMI() const
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Returns a TargetRegisterClass used for pointer values.
unsigned getPtrSizedFrameRegister(const MachineFunction &MF) const
bool hasBasePointer(const MachineFunction &MF) const
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
const TargetRegisterClass * getGPRsForTailCall(const MachineFunction &MF) const
getGPRsForTailCall - Returns a register class with registers that can be used in forming tail calls.
bool canRealignStack(const MachineFunction &MF) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a ...
bool shouldRealignStack(const MachineFunction &MF) const override
unsigned getNumSupportedRegs(const MachineFunction &MF) const override
Return the number of registers for the function.
Register getFrameRegister(const MachineFunction &MF) const override
unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI) const
findDeadCallerSavedReg - Return a caller-saved register that isn't live when it reaches the "return" ...
const uint32_t * getDarwinTLSCallPreservedMask() const
bool isTileRegisterClass(const TargetRegisterClass *RC) const
Return true if it is tile register class.
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
bool isArgumentRegister(const MachineFunction &MF, MCRegister Reg) const override
isArgumentReg - Returns true if Reg can be used as an argument to a function.
Register getStackRegister() const
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const override
getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register ...
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
unsigned getPtrSizedStackRegister(const MachineFunction &MF) const
int getSEHRegNum(unsigned i) const
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or...
X86RegisterInfo(const Triple &TT)
Register getBaseRegister() const
bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
void eliminateFrameIndex(MachineBasicBlock::iterator II, unsigned FIOperandNum, Register BaseReg, int FIOffset) const
const uint32_t * getNoPreservedMask() const override
bool isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const override
Returns true if PhysReg is a fixed register.
const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const override
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
getCalleeSavedRegs - Return a null-terminated list of all of the callee-save registers on this target...
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
const X86TargetLowering * getTargetLowering() const override
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ X86_64_SysV
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
@ HiPE
Used by the High-Performance Erlang Compiler (HiPE).
@ CFGuard_Check
Special calling convention on Windows for calling the Control Guard Check ICall funtion.
@ PreserveMost
Used for runtime calls that preserves most registers.
@ AnyReg
OBSOLETED - Used for stack based JavaScript calls.
@ CXX_FAST_TLS
Used for access functions.
@ X86_INTR
x86 hardware interrupt context.
@ GHC
Used by the Glasgow Haskell Compiler (GHC).
@ Cold
Attempts to make code in the caller as efficient as possible under the assumption that the call is no...
@ PreserveAll
Used for runtime calls that preserves (almost) all registers.
@ Intel_OCL_BI
Used for Intel OpenCL built-ins.
@ PreserveNone
Used for runtime calls that preserves none general registers.
@ Win64
The C convention as implemented on Windows/x86-64 and AArch64.
@ SwiftTail
This follows the Swift calling convention in how arguments are passed but guarantees tail calls will ...
@ GRAAL
Used by GraalVM. Two additional registers are reserved.
@ X86_RegCall
Register calling convention used for parameters transfer optimization.
void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI)
unsigned getNonNDVariant(unsigned Opc)
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
MCRegister getX86SubSuperRegister(MCRegister Reg, unsigned Size, bool High=false)
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
FormattedNumber format_hex(uint64_t N, unsigned Width, bool Upper=false)
format_hex - Output N as a fixed width hexadecimal.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.