Go to the documentation of this file.
39 #define GET_REGINFO_TARGET_DESC
40 #include "X86GenRegisterInfo.inc"
44 cl::desc(
"Enable use of a base pointer for complex stack frames"));
50 (TT.isArch64Bit() ?
X86::RIP :
X86::EIP)) {
54 Is64Bit = TT.isArch64Bit();
55 IsWin64 = Is64Bit && TT.isOSWindows();
66 StackPtr = Use64BitReg ? X86::RSP :
X86::ESP;
67 FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
68 BasePtr = Use64BitReg ? X86::RBX :
X86::EBX;
79 return getEncodingValue(
i);
87 if (!Is64Bit && Idx == X86::sub_8bit)
88 Idx = X86::sub_8bit_hi;
91 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
97 unsigned SubIdx)
const {
99 if (!Is64Bit && SubIdx == X86::sub_8bit) {
100 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
104 return X86GenRegisterInfo::getMatchingSuperRegClass(A,
B, SubIdx);
118 if (RC == &X86::GR8_NOREXRegClass)
126 switch (Super->getID()) {
127 case X86::FR32RegClassID:
128 case X86::FR64RegClassID:
131 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
134 case X86::VR128RegClassID:
135 case X86::VR256RegClassID:
137 if (!Subtarget.
hasVLX() &&
138 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
141 case X86::VR128XRegClassID:
142 case X86::VR256XRegClassID:
145 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
148 case X86::FR32XRegClassID:
149 case X86::FR64XRegClassID:
152 getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
155 case X86::GR8RegClassID:
156 case X86::GR16RegClassID:
157 case X86::GR32RegClassID:
158 case X86::GR64RegClassID:
159 case X86::RFP32RegClassID:
160 case X86::RFP64RegClassID:
161 case X86::RFP80RegClassID:
162 case X86::VR512_0_15RegClassID:
163 case X86::VR512RegClassID:
166 if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
176 unsigned Kind)
const {
182 return &X86::GR64RegClass;
192 ? &X86::LOW32_ADDR_ACCESS_RBPRegClass
193 : &X86::LOW32_ADDR_ACCESSRegClass;
195 return &X86::GR32RegClass;
198 return &X86::GR64_NOSPRegClass;
200 return &X86::GR32_NOSPRegClass;
203 return &X86::GR64_NOREXRegClass;
204 return &X86::GR32_NOREXRegClass;
207 return &X86::GR64_NOREX_NOSPRegClass;
209 return &X86::GR32_NOREX_NOSPRegClass;
218 unsigned SrcSubReg)
const {
223 SrcRC->
hasSuperClassEq(&X86::GR64RegClass) && SrcSubReg == X86::sub_32bit)
234 return &X86::GR64_TCW64RegClass;
236 return &X86::GR64_TCRegClass;
240 return &X86::GR32RegClass;
241 return &X86::GR32_TCRegClass;
246 if (RC == &X86::CCRRegClass) {
248 return &X86::GR64RegClass;
250 return &X86::GR32RegClass;
260 unsigned FPDiff = TFI->
hasFP(MF) ? 1 : 0;
261 switch (RC->
getID()) {
264 case X86::GR32RegClassID:
266 case X86::GR64RegClassID:
268 case X86::VR128RegClassID:
269 return Is64Bit ? 10 : 4;
270 case X86::VR64RegClassID:
277 assert(MF &&
"MachineFunction required");
281 bool HasSSE = Subtarget.
hasSSE1();
282 bool HasAVX = Subtarget.
hasAVX();
296 return CSR_NoRegs_SaveList;
301 return CSR_NoRegs_SaveList;
304 return CSR_64_AllRegs_AVX_SaveList;
305 return CSR_64_AllRegs_SaveList;
307 return CSR_64_RT_MostRegs_SaveList;
310 return CSR_64_RT_AllRegs_AVX_SaveList;
311 return CSR_64_RT_AllRegs_SaveList;
315 CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList;
318 if (HasAVX512 && IsWin64)
319 return CSR_Win64_Intel_OCL_BI_AVX512_SaveList;
320 if (HasAVX512 && Is64Bit)
321 return CSR_64_Intel_OCL_BI_AVX512_SaveList;
322 if (HasAVX && IsWin64)
323 return CSR_Win64_Intel_OCL_BI_AVX_SaveList;
324 if (HasAVX && Is64Bit)
325 return CSR_64_Intel_OCL_BI_AVX_SaveList;
326 if (!HasAVX && !IsWin64 && Is64Bit)
327 return CSR_64_Intel_OCL_BI_SaveList;
331 return CSR_64_HHVM_SaveList;
335 return (HasSSE ? CSR_Win64_RegCall_SaveList :
336 CSR_Win64_RegCall_NoSSE_SaveList);
338 return (HasSSE ? CSR_SysV64_RegCall_SaveList :
339 CSR_SysV64_RegCall_NoSSE_SaveList);
342 return (HasSSE ? CSR_32_RegCall_SaveList :
343 CSR_32_RegCall_NoSSE_SaveList);
346 assert(!Is64Bit &&
"CFGuard check mechanism only used on 32-bit X86");
347 return (HasSSE ? CSR_Win32_CFGuard_Check_SaveList
348 : CSR_Win32_CFGuard_Check_NoSSE_SaveList);
351 return CSR_64_MostRegs_SaveList;
355 return CSR_Win64_NoSSE_SaveList;
356 return CSR_Win64_SaveList;
359 return CSR_64EHRet_SaveList;
360 return CSR_64_SaveList;
364 return CSR_64_AllRegs_AVX512_SaveList;
366 return CSR_64_AllRegs_AVX_SaveList;
368 return CSR_64_AllRegs_SaveList;
369 return CSR_64_AllRegs_NoSSE_SaveList;
372 return CSR_32_AllRegs_AVX512_SaveList;
374 return CSR_32_AllRegs_AVX_SaveList;
376 return CSR_32_AllRegs_SSE_SaveList;
377 return CSR_32_AllRegs_SaveList;
385 F.getAttributes().hasAttrSomewhere(Attribute::SwiftError);
387 return IsWin64 ? CSR_Win64_SwiftError_SaveList
388 : CSR_64_SwiftError_SaveList;
391 return HasSSE ? CSR_Win64_SaveList : CSR_Win64_NoSSE_SaveList;
393 return CSR_64EHRet_SaveList;
394 return CSR_64_SaveList;
397 return CallsEHReturn ? CSR_32EHRet_SaveList : CSR_32_SaveList;
402 assert(MF &&
"Invalid MachineFunction pointer.");
405 return CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList;
413 bool HasSSE = Subtarget.
hasSSE1();
414 bool HasAVX = Subtarget.
hasAVX();
420 return CSR_NoRegs_RegMask;
423 return CSR_64_AllRegs_AVX_RegMask;
424 return CSR_64_AllRegs_RegMask;
426 return CSR_64_RT_MostRegs_RegMask;
429 return CSR_64_RT_AllRegs_AVX_RegMask;
430 return CSR_64_RT_AllRegs_RegMask;
433 return CSR_64_TLS_Darwin_RegMask;
436 if (HasAVX512 && IsWin64)
437 return CSR_Win64_Intel_OCL_BI_AVX512_RegMask;
438 if (HasAVX512 && Is64Bit)
439 return CSR_64_Intel_OCL_BI_AVX512_RegMask;
440 if (HasAVX && IsWin64)
441 return CSR_Win64_Intel_OCL_BI_AVX_RegMask;
442 if (HasAVX && Is64Bit)
443 return CSR_64_Intel_OCL_BI_AVX_RegMask;
444 if (!HasAVX && !IsWin64 && Is64Bit)
445 return CSR_64_Intel_OCL_BI_RegMask;
449 return CSR_64_HHVM_RegMask;
453 return (HasSSE ? CSR_Win64_RegCall_RegMask :
454 CSR_Win64_RegCall_NoSSE_RegMask);
456 return (HasSSE ? CSR_SysV64_RegCall_RegMask :
457 CSR_SysV64_RegCall_NoSSE_RegMask);
460 return (HasSSE ? CSR_32_RegCall_RegMask :
461 CSR_32_RegCall_NoSSE_RegMask);
464 assert(!Is64Bit &&
"CFGuard check mechanism only used on 32-bit X86");
465 return (HasSSE ? CSR_Win32_CFGuard_Check_RegMask
466 : CSR_Win32_CFGuard_Check_NoSSE_RegMask);
469 return CSR_64_MostRegs_RegMask;
472 return CSR_Win64_RegMask;
474 return CSR_64_RegMask;
478 return CSR_64_AllRegs_AVX512_RegMask;
480 return CSR_64_AllRegs_AVX_RegMask;
482 return CSR_64_AllRegs_RegMask;
483 return CSR_64_AllRegs_NoSSE_RegMask;
486 return CSR_32_AllRegs_AVX512_RegMask;
488 return CSR_32_AllRegs_AVX_RegMask;
490 return CSR_32_AllRegs_SSE_RegMask;
491 return CSR_32_AllRegs_RegMask;
502 F.getAttributes().hasAttrSomewhere(Attribute::SwiftError);
504 return IsWin64 ? CSR_Win64_SwiftError_RegMask : CSR_64_SwiftError_RegMask;
505 return IsWin64 ? CSR_Win64_RegMask : CSR_64_RegMask;
508 return CSR_32_RegMask;
513 return CSR_NoRegs_RegMask;
517 return CSR_64_TLS_Darwin_RegMask;
545 if (TFI->
hasFP(MF)) {
556 "Stack realignment in presence of dynamic allocas is not supported with"
557 "this calling convention.");
573 for (
unsigned n = 0;
n != 8; ++
n)
589 for (
unsigned n = 0;
n != 8; ++
n) {
600 for (
unsigned n = 16;
n != 32; ++
n) {
607 {X86::SIL, X86::DIL, X86::BPL, X86::SPL,
608 X86::SIH, X86::DIH, X86::BPH, X86::SPH}));
620 assert(!(
Mask[X86::EFLAGS / 32] & (1U << (X86::EFLAGS % 32))) &&
621 "EFLAGS are not live-out from a patchpoint.");
624 for (
auto Reg : {X86::EFLAGS, X86::RIP, X86::EIP, X86::IP})
651 bool CantUseFP = needsStackRealignment(MF);
680 unsigned Opc = II->getOpcode();
682 if ((Opc != X86::LEA32r && Opc != X86::LEA64r && Opc != X86::LEA64_32r) ||
683 MI.getOperand(2).getImm() != 1 ||
684 MI.getOperand(3).getReg() != X86::NoRegister ||
685 MI.getOperand(4).getImm() != 0 ||
686 MI.getOperand(5).getReg() != X86::NoRegister)
692 if (Opc == X86::LEA64_32r)
694 Register NewDestReg =
MI.getOperand(0).getReg();
696 MI.getParent()->getParent()->getSubtarget<
X86Subtarget>().getInstrInfo();
698 MI.getOperand(1).isKill());
699 MI.eraseFromParent();
704 switch (
MI.getOpcode()) {
716 int SPAdj,
unsigned FIOperandNum,
725 int FrameIndex =
MI.getOperand(FIOperandNum).getIndex();
731 assert((!needsStackRealignment(MF) ||
733 "Return instruction can only reference SP relative frame objects");
747 unsigned Opc =
MI.getOpcode();
748 if (Opc == TargetOpcode::LOCAL_ESCAPE) {
759 if (Opc == X86::LEA64_32r && X86::GR32RegClass.
contains(BasePtr))
764 MI.getOperand(FIOperandNum).ChangeToRegister(MachineBasePtr,
false);
766 if (BasePtr == StackPtr)
771 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
772 assert(BasePtr == FramePtr &&
"Expected the FP as base register");
773 int64_t
Offset =
MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
774 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(
Offset);
778 if (
MI.getOperand(FIOperandNum+3).isImm()) {
780 int Imm = (
int)(
MI.getOperand(FIOperandNum + 3).getImm());
781 int Offset = FIOffset + Imm;
783 "Requesting 64-bit offset in 32-bit immediate!");
785 MI.getOperand(FIOperandNum + 3).ChangeToImmediate(
Offset);
788 uint64_t
Offset = FIOffset +
789 (uint64_t)
MI.getOperand(FIOperandNum+3).getOffset();
790 MI.getOperand(FIOperandNum + 3).setOffset(
Offset);
805 switch (
MBBI->getOpcode()) {
808 case TargetOpcode::PATCHABLE_RET:
814 case X86::TCRETURNdi:
815 case X86::TCRETURNri:
816 case X86::TCRETURNmi:
817 case X86::TCRETURNdi64:
818 case X86::TCRETURNri64:
819 case X86::TCRETURNmi64:
821 case X86::EH_RETURN64: {
823 for (
unsigned I = 0,
E =
MBBI->getNumOperands();
I !=
E; ++
I) {
834 for (
auto CS : AvailableRegs)
835 if (!
Uses.count(CS) && CS != X86::RIP && CS != X86::RSP && CS !=
X86::ESP)
845 return TFI->
hasFP(MF) ? FramePtr : StackPtr;
873 unsigned OpCode =
MI->getOpcode();
885 case X86::PTILELOADDV:
890 case X86::PTILEZEROV:
891 case X86::PTDPBF16PSV:
909 VirtReg, Order, Hints, MF, VRM,
Matrix);
911 if (RC.
getID() != X86::TILERegClassID)
912 return BaseImplRetVal;
918 Hints.push_back(PhysReg);
922 if (PhysShape == VirtShape)
923 Hints.push_back(PhysReg);
927 CopyHints.
insert(Hints.begin(), Hints.end());
929 for (
auto Hint : CopyHints) {
934 if (!CopyHints.count(PhysReg) && RC.
contains(PhysReg) &&
939 #define DEBUG_TYPE "tile-hint"
941 dbgs() <<
"Hints for virtual register " <<
format_hex(VirtReg, 8) <<
"\n";
942 for (
auto Hint : Hints) {
943 dbgs() <<
"tmm" << Hint <<
",";
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getDwarfRegFlavour(const Triple &TT, bool isEH)
def_iterator def_begin(Register RegNo) const
unsigned getID() const
Return the register class ID number.
This class represents lattice values for constants.
@ X86_64_SysV
The C convention as specified in the x86-64 supplement to the System V ABI, used on most non-Windows ...
@ HHVM
Calling convention used by HipHop Virtual Machine (HHVM) to perform calls to and from translation cac...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
bool isEHFuncletEntry() const
Returns true if this is the entry block of an EH funclet.
return AArch64::GPR64RegClass contains(Reg)
Register getFrameRegister(const MachineFunction &MF) const override
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override
bool canReserveReg(MCRegister PhysReg) const
canReserveReg - Returns true if PhysReg can be used as a reserved register.
Triple - Helper class for working with autoconf configuration names.
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
static constexpr unsigned NoRegister
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
@ Intel_OCL_BI
Intel_OCL_BI - Calling conventions for Intel OpenCL built-ins.
const MCPhysReg * getCalleeSavedRegsViaCopy(const MachineFunction *MF) const
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
SmallPtrSet< MachineInstr *, 2 > Uses
const TargetRegisterClass * getGPRsForTailCall(const MachineFunction &MF) const
getGPRsForTailCall - Returns a register class with registers that can be used in forming tail calls.
const uint32_t * getDarwinTLSCallPreservedMask() const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool hasPreallocatedCall() const
const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &MF) const override
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
virtual bool canRealignStack(const MachineFunction &MF) const
True if the stack can be realigned for the target.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
int getWin64EHFrameIndexRef(const MachineFunction &MF, int FI, Register &SPReg) const
StackOffset getFrameIndexReferenceSP(const MachineFunction &MF, int FI, Register &SPReg, int Adjustment) const
const uint32_t * getNoPreservedMask() const override
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
@ CATCHRET
CATCHRET - Represents a return from a catch block funclet.
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
static bool CantUseSP(const MachineFrameInfo &MFI)
@ X86_INTR
X86_INTR - x86 hardware interrupt context.
Register getBaseRegister() const
const HexagonInstrInfo * TII
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
MachineOperand class - Representation of each machine instruction operand.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const override
constexpr bool isInt< 32 >(int64_t x)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
bool callsEHReturn() const
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
MCRegister getX86SubSuperRegister(MCRegister, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
static bool isFuncletReturnInstr(MachineInstr &MI)
@ CLEANUPRET
CLEANUPRET - Represents a return from a cleanup block funclet.
unsigned getPtrSizedFrameRegister(const MachineFunction &MF) const
virtual bool getRegAllocationHints(Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM=nullptr, const LiveRegMatrix *Matrix=nullptr) const
Get a list of 'hint' registers that the register allocator should try first when allocating a physica...
initializer< Ty > init(const Ty &Val)
X86RegisterInfo(const Triple &TT)
void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const X86TargetLowering * getTargetLowering() const override
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
bool hasShape(Register virtReg) const
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
Register getReg() const
getReg - Returns the register number.
static cl::opt< bool > EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames"))
void assignVirt2Shape(Register virtReg, ShapeT shape)
ShapeT getShape(Register virtReg) const
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
@ CFGuard_Check
Special calling convention on Windows for calling the Control Guard Check ICall funtion.
MachineBasicBlock MachineBasicBlock::iterator MBBI
void adjustStackMapLiveOutMask(uint32_t *Mask) const override
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static ShapeT getTileShape(Register VirtReg, VirtRegMap *VRM, const MachineRegisterInfo *MRI)
const TargetRegisterClass * getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const override
getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register ...
bool canRealignStack(const MachineFunction &MF) const override
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
int getSEHRegNum(unsigned i) const
static StackOffset getFixed(ScalarTy Fixed)
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const
@ Win64
The C convention as implemented on Windows/x86-64 and AArch64.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
getCalleeSavedRegs - Return a null-terminated list of all of the callee-save registers on this target...
unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI) const
findDeadCallerSavedReg - Return a caller-saved register that isn't live when it reaches the "return" ...
sc_iterator getSuperClasses() const
Returns a NULL-terminated list of super-classes.
bool hasBasePointer(const MachineFunction &MF) const
const TargetRegisterClass *const * sc_iterator
@ EH_RETURN
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin,...
static bool tryOptimizeLEAtoMOV(MachineBasicBlock::iterator II)
Function Alias Analysis false
const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const override
getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool Is64Bit
Is64Bit implies that x86_64 instructions are available.
bool Uses64BitFramePtr
True if the 64-bit frame or stack pointer should be used.
BitVector getReservedRegs(const MachineFunction &MF) const override
getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a ...
Register getStackRegister() const
bool hasOpaqueSPAdjustment() const
Returns true if the function contains opaque dynamic stack adjustments.
@ X86_RegCall
Register calling convention used for parameters transfer optimization.
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports that transformation probably isn t worthwhile The transformation can also easily be made to work with non zero equality for n
Unrolling by would eliminate the &in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various including etc On X86
FormattedNumber format_hex(uint64_t N, unsigned Width, bool Upper=false)
format_hex - Output N as a fixed width hexadecimal.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Emit instructions to copy a pair of physical registers.
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
unsigned getPtrSizedStackRegister(const MachineFunction &MF) const
MCRegAliasIterator enumerates all registers aliasing Reg.
const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override
getPointerRegClass - Returns a TargetRegisterClass used for pointer values.