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HexagonCopyToCombine.cpp
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1 //===------- HexagonCopyToCombine.cpp - Hexagon Copy-To-Combine Pass ------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 // This pass replaces transfer instructions by combine instructions.
9 // We walk along a basic block and look for two combinable instructions and try
10 // to move them together. If we can move them next to each other we do so and
11 // replace them with a combine instruction.
12 //===----------------------------------------------------------------------===//
13 
14 #include "HexagonInstrInfo.h"
15 #include "HexagonSubtarget.h"
16 #include "llvm/ADT/DenseMap.h"
17 #include "llvm/ADT/DenseSet.h"
23 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/Pass.h"
26 #include "llvm/Support/CodeGen.h"
28 #include "llvm/Support/Debug.h"
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "hexagon-copy-combine"
35 
36 static
37 cl::opt<bool> IsCombinesDisabled("disable-merge-into-combines",
39  cl::init(false),
40  cl::desc("Disable merging into combines"));
41 static
42 cl::opt<bool> IsConst64Disabled("disable-const64",
44  cl::init(false),
45  cl::desc("Disable generation of const64"));
46 static
48 MaxNumOfInstsBetweenNewValueStoreAndTFR("max-num-inst-between-tfr-and-nv-store",
49  cl::Hidden, cl::init(4),
50  cl::desc("Maximum distance between a tfr feeding a store we "
51  "consider the store still to be newifiable"));
52 
53 namespace llvm {
56 }
57 
58 
59 namespace {
60 
61 class HexagonCopyToCombine : public MachineFunctionPass {
62  const HexagonInstrInfo *TII;
63  const TargetRegisterInfo *TRI;
64  const HexagonSubtarget *ST;
66 
67  DenseSet<MachineInstr *> PotentiallyNewifiableTFR;
69 
70 public:
71  static char ID;
72 
73  HexagonCopyToCombine() : MachineFunctionPass(ID) {
75  }
76 
77  void getAnalysisUsage(AnalysisUsage &AU) const override {
79  }
80 
81  StringRef getPassName() const override {
82  return "Hexagon Copy-To-Combine Pass";
83  }
84 
85  bool runOnMachineFunction(MachineFunction &Fn) override;
86 
87  MachineFunctionProperties getRequiredProperties() const override {
90  }
91 
92 private:
93  MachineInstr *findPairable(MachineInstr &I1, bool &DoInsertAtI1,
94  bool AllowC64);
95 
96  void findPotentialNewifiableTFRs(MachineBasicBlock &);
97 
98  void combine(MachineInstr &I1, MachineInstr &I2,
99  MachineBasicBlock::iterator &MI, bool DoInsertAtI1,
100  bool OptForSize);
101 
102  bool isSafeToMoveTogether(MachineInstr &I1, MachineInstr &I2,
103  unsigned I1DestReg, unsigned I2DestReg,
104  bool &DoInsertAtI1);
105 
106  void emitCombineRR(MachineBasicBlock::iterator &Before, unsigned DestReg,
107  MachineOperand &HiOperand, MachineOperand &LoOperand);
108 
109  void emitCombineRI(MachineBasicBlock::iterator &Before, unsigned DestReg,
110  MachineOperand &HiOperand, MachineOperand &LoOperand);
111 
112  void emitCombineIR(MachineBasicBlock::iterator &Before, unsigned DestReg,
113  MachineOperand &HiOperand, MachineOperand &LoOperand);
114 
115  void emitCombineII(MachineBasicBlock::iterator &Before, unsigned DestReg,
116  MachineOperand &HiOperand, MachineOperand &LoOperand);
117 
118  void emitConst64(MachineBasicBlock::iterator &Before, unsigned DestReg,
119  MachineOperand &HiOperand, MachineOperand &LoOperand);
120 };
121 
122 } // End anonymous namespace.
123 
124 char HexagonCopyToCombine::ID = 0;
125 
126 INITIALIZE_PASS(HexagonCopyToCombine, "hexagon-copy-combine",
127  "Hexagon Copy-To-Combine Pass", false, false)
128 
129 static bool isCombinableInstType(MachineInstr &MI, const HexagonInstrInfo *TII,
131  switch (MI.getOpcode()) {
132  case Hexagon::A2_tfr: {
133  // A COPY instruction can be combined if its arguments are IntRegs (32bit).
134  const MachineOperand &Op0 = MI.getOperand(0);
135  const MachineOperand &Op1 = MI.getOperand(1);
136  assert(Op0.isReg() && Op1.isReg());
137 
138  Register DestReg = Op0.getReg();
139  Register SrcReg = Op1.getReg();
140  return Hexagon::IntRegsRegClass.contains(DestReg) &&
141  Hexagon::IntRegsRegClass.contains(SrcReg);
142  }
143 
144  case Hexagon::A2_tfrsi: {
145  // A transfer-immediate can be combined if its argument is a signed 8bit
146  // value.
147  const MachineOperand &Op0 = MI.getOperand(0);
148  const MachineOperand &Op1 = MI.getOperand(1);
149  assert(Op0.isReg());
150 
151  Register DestReg = Op0.getReg();
152  // Ensure that TargetFlags are MO_NO_FLAG for a global. This is a
153  // workaround for an ABI bug that prevents GOT relocations on combine
154  // instructions
155  if (!Op1.isImm() && Op1.getTargetFlags() != HexagonII::MO_NO_FLAG)
156  return false;
157 
158  // Only combine constant extended A2_tfrsi if we are in aggressive mode.
159  bool NotExt = Op1.isImm() && isInt<8>(Op1.getImm());
160  return Hexagon::IntRegsRegClass.contains(DestReg) &&
161  (ShouldCombineAggressively || NotExt);
162  }
163 
164  case Hexagon::V6_vassign:
165  return true;
166 
167  default:
168  break;
169  }
170 
171  return false;
172 }
173 
174 template <unsigned N> static bool isGreaterThanNBitTFRI(const MachineInstr &I) {
175  if (I.getOpcode() == Hexagon::TFRI64_V4 ||
176  I.getOpcode() == Hexagon::A2_tfrsi) {
177  const MachineOperand &Op = I.getOperand(1);
178  return !Op.isImm() || !isInt<N>(Op.getImm());
179  }
180  return false;
181 }
182 
183 /// areCombinableOperations - Returns true if the two instruction can be merge
184 /// into a combine (ignoring register constraints).
186  MachineInstr &HighRegInst,
187  MachineInstr &LowRegInst, bool AllowC64) {
188  unsigned HiOpc = HighRegInst.getOpcode();
189  unsigned LoOpc = LowRegInst.getOpcode();
190 
191  auto verifyOpc = [](unsigned Opc) -> void {
192  switch (Opc) {
193  case Hexagon::A2_tfr:
194  case Hexagon::A2_tfrsi:
195  case Hexagon::V6_vassign:
196  break;
197  default:
198  llvm_unreachable("Unexpected opcode");
199  }
200  };
201  verifyOpc(HiOpc);
202  verifyOpc(LoOpc);
203 
204  if (HiOpc == Hexagon::V6_vassign || LoOpc == Hexagon::V6_vassign)
205  return HiOpc == LoOpc;
206 
207  if (!AllowC64) {
208  // There is no combine of two constant extended values.
209  if (isGreaterThanNBitTFRI<8>(HighRegInst) &&
210  isGreaterThanNBitTFRI<6>(LowRegInst))
211  return false;
212  }
213 
214  // There is a combine of two constant extended values into CONST64,
215  // provided both constants are true immediates.
216  if (isGreaterThanNBitTFRI<16>(HighRegInst) &&
217  isGreaterThanNBitTFRI<16>(LowRegInst) && !IsConst64Disabled)
218  return (HighRegInst.getOperand(1).isImm() &&
219  LowRegInst.getOperand(1).isImm());
220 
221  // There is no combine of two constant extended values, unless handled above
222  // Make both 8-bit size checks to allow both combine (#,##) and combine(##,#)
223  if (isGreaterThanNBitTFRI<8>(HighRegInst) &&
224  isGreaterThanNBitTFRI<8>(LowRegInst))
225  return false;
226 
227  return true;
228 }
229 
230 static bool isEvenReg(unsigned Reg) {
232  if (Hexagon::IntRegsRegClass.contains(Reg))
233  return (Reg - Hexagon::R0) % 2 == 0;
234  if (Hexagon::HvxVRRegClass.contains(Reg))
235  return (Reg - Hexagon::V0) % 2 == 0;
236  llvm_unreachable("Invalid register");
237 }
238 
239 static void removeKillInfo(MachineInstr &MI, unsigned RegNotKilled) {
240  for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
241  MachineOperand &Op = MI.getOperand(I);
242  if (!Op.isReg() || Op.getReg() != RegNotKilled || !Op.isKill())
243  continue;
244  Op.setIsKill(false);
245  }
246 }
247 
248 /// Returns true if it is unsafe to move a copy instruction from \p UseReg to
249 /// \p DestReg over the instruction \p MI.
251  unsigned DestReg,
252  const TargetRegisterInfo *TRI) {
253  return (UseReg && (MI.modifiesRegister(UseReg, TRI))) ||
254  MI.modifiesRegister(DestReg, TRI) || MI.readsRegister(DestReg, TRI) ||
255  MI.hasUnmodeledSideEffects() || MI.isInlineAsm() ||
256  MI.isMetaInstruction();
257 }
258 
259 static Register UseReg(const MachineOperand& MO) {
260  return MO.isReg() ? MO.getReg() : Register();
261 }
262 
263 /// isSafeToMoveTogether - Returns true if it is safe to move I1 next to I2 such
264 /// that the two instructions can be paired in a combine.
265 bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr &I1,
266  MachineInstr &I2,
267  unsigned I1DestReg,
268  unsigned I2DestReg,
269  bool &DoInsertAtI1) {
270  Register I2UseReg = UseReg(I2.getOperand(1));
271 
272  // It is not safe to move I1 and I2 into one combine if I2 has a true
273  // dependence on I1.
274  if (I2UseReg && I1.modifiesRegister(I2UseReg, TRI))
275  return false;
276 
277  bool isSafe = true;
278 
279  // First try to move I2 towards I1.
280  {
281  // A reverse_iterator instantiated like below starts before I2, and I1
282  // respectively.
283  // Look at instructions I in between I2 and (excluding) I1.
286  // At 03 we got better results (dhrystone!) by being more conservative.
288  End = ++I1.getIterator().getReverse();
289  // If I2 kills its operand and we move I2 over an instruction that also
290  // uses I2's use reg we need to modify that (first) instruction to now kill
291  // this reg.
292  unsigned KilledOperand = 0;
293  if (I2.killsRegister(I2UseReg))
294  KilledOperand = I2UseReg;
295  MachineInstr *KillingInstr = nullptr;
296 
297  for (; I != End; ++I) {
298  // If the intervening instruction I:
299  // * modifies I2's use reg
300  // * modifies I2's def reg
301  // * reads I2's def reg
302  // * or has unmodelled side effects
303  // we can't move I2 across it.
304  if (I->isDebugInstr())
305  continue;
306 
307  if (isUnsafeToMoveAcross(*I, I2UseReg, I2DestReg, TRI)) {
308  isSafe = false;
309  break;
310  }
311 
312  // Update first use of the killed operand.
313  if (!KillingInstr && KilledOperand &&
314  I->readsRegister(KilledOperand, TRI))
315  KillingInstr = &*I;
316  }
317  if (isSafe) {
318  // Update the intermediate instruction to with the kill flag.
319  if (KillingInstr) {
320  bool Added = KillingInstr->addRegisterKilled(KilledOperand, TRI, true);
321  (void)Added; // suppress compiler warning
322  assert(Added && "Must successfully update kill flag");
323  removeKillInfo(I2, KilledOperand);
324  }
325  DoInsertAtI1 = true;
326  return true;
327  }
328  }
329 
330  // Try to move I1 towards I2.
331  {
332  // Look at instructions I in between I1 and (excluding) I2.
333  MachineBasicBlock::iterator I(I1), End(I2);
334  // At O3 we got better results (dhrystone) by being more conservative here.
336  End = std::next(MachineBasicBlock::iterator(I2));
337  Register I1UseReg = UseReg(I1.getOperand(1));
338  // Track killed operands. If we move across an instruction that kills our
339  // operand, we need to update the kill information on the moved I1. It kills
340  // the operand now.
341  MachineInstr *KillingInstr = nullptr;
342  unsigned KilledOperand = 0;
343 
344  while(++I != End) {
345  MachineInstr &MI = *I;
346  // If the intervening instruction MI:
347  // * modifies I1's use reg
348  // * modifies I1's def reg
349  // * reads I1's def reg
350  // * or has unmodelled side effects
351  // We introduce this special case because llvm has no api to remove a
352  // kill flag for a register (a removeRegisterKilled() analogous to
353  // addRegisterKilled) that handles aliased register correctly.
354  // * or has a killed aliased register use of I1's use reg
355  // %d4 = A2_tfrpi 16
356  // %r6 = A2_tfr %r9
357  // %r8 = KILL %r8, implicit killed %d4
358  // If we want to move R6 = across the KILL instruction we would have
359  // to remove the implicit killed %d4 operand. For now, we are
360  // conservative and disallow the move.
361  // we can't move I1 across it.
362  if (MI.isDebugInstr()) {
363  if (MI.readsRegister(I1DestReg, TRI)) // Move this instruction after I2.
364  DbgMItoMove.push_back(&MI);
365  continue;
366  }
367 
368  if (isUnsafeToMoveAcross(MI, I1UseReg, I1DestReg, TRI) ||
369  // Check for an aliased register kill. Bail out if we see one.
370  (!MI.killsRegister(I1UseReg) && MI.killsRegister(I1UseReg, TRI)))
371  return false;
372 
373  // Check for an exact kill (registers match).
374  if (I1UseReg && MI.killsRegister(I1UseReg)) {
375  assert(!KillingInstr && "Should only see one killing instruction");
376  KilledOperand = I1UseReg;
377  KillingInstr = &MI;
378  }
379  }
380  if (KillingInstr) {
381  removeKillInfo(*KillingInstr, KilledOperand);
382  // Update I1 to set the kill flag. This flag will later be picked up by
383  // the new COMBINE instruction.
384  bool Added = I1.addRegisterKilled(KilledOperand, TRI);
385  (void)Added; // suppress compiler warning
386  assert(Added && "Must successfully update kill flag");
387  }
388  DoInsertAtI1 = false;
389  }
390 
391  return true;
392 }
393 
394 /// findPotentialNewifiableTFRs - Finds tranfers that feed stores that could be
395 /// newified. (A use of a 64 bit register define can not be newified)
396 void
397 HexagonCopyToCombine::findPotentialNewifiableTFRs(MachineBasicBlock &BB) {
399  for (MachineInstr &MI : BB) {
400  if (MI.isDebugInstr())
401  continue;
402 
403  // Mark TFRs that feed a potential new value store as such.
404  if (TII->mayBeNewStore(MI)) {
405  // Look for uses of TFR instructions.
406  for (unsigned OpdIdx = 0, OpdE = MI.getNumOperands(); OpdIdx != OpdE;
407  ++OpdIdx) {
408  MachineOperand &Op = MI.getOperand(OpdIdx);
409 
410  // Skip over anything except register uses.
411  if (!Op.isReg() || !Op.isUse() || !Op.getReg())
412  continue;
413 
414  // Look for the defining instruction.
415  Register Reg = Op.getReg();
416  MachineInstr *DefInst = LastDef[Reg];
417  if (!DefInst)
418  continue;
419  if (!isCombinableInstType(*DefInst, TII, ShouldCombineAggressively))
420  continue;
421 
422  // Only close newifiable stores should influence the decision.
423  // Ignore the debug instructions in between.
424  MachineBasicBlock::iterator It(DefInst);
425  unsigned NumInstsToDef = 0;
426  while (&*It != &MI) {
427  if (!It->isDebugInstr())
428  ++NumInstsToDef;
429  ++It;
430  }
431 
432  if (NumInstsToDef > MaxNumOfInstsBetweenNewValueStoreAndTFR)
433  continue;
434 
435  PotentiallyNewifiableTFR.insert(DefInst);
436  }
437  // Skip to next instruction.
438  continue;
439  }
440 
441  // Put instructions that last defined integer or double registers into the
442  // map.
443  for (MachineOperand &Op : MI.operands()) {
444  if (Op.isReg()) {
445  if (!Op.isDef() || !Op.getReg())
446  continue;
447  Register Reg = Op.getReg();
448  if (Hexagon::DoubleRegsRegClass.contains(Reg)) {
449  for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
450  LastDef[*SubRegs] = &MI;
451  } else if (Hexagon::IntRegsRegClass.contains(Reg))
452  LastDef[Reg] = &MI;
453  } else if (Op.isRegMask()) {
454  for (unsigned Reg : Hexagon::IntRegsRegClass)
455  if (Op.clobbersPhysReg(Reg))
456  LastDef[Reg] = &MI;
457  }
458  }
459  }
460 }
461 
462 bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) {
463  if (skipFunction(MF.getFunction()))
464  return false;
465 
466  if (IsCombinesDisabled) return false;
467 
468  bool HasChanged = false;
469 
470  // Get target info.
472  TRI = ST->getRegisterInfo();
473  TII = ST->getInstrInfo();
474 
475  const Function &F = MF.getFunction();
476  bool OptForSize = F.hasFnAttribute(Attribute::OptimizeForSize);
477 
478  // Combine aggressively (for code size)
481 
482  // Disable CONST64 for tiny core since it takes a LD resource.
483  if (!OptForSize && ST->isTinyCore())
484  IsConst64Disabled = true;
485 
486  // Traverse basic blocks.
487  for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); BI != BE;
488  ++BI) {
489  PotentiallyNewifiableTFR.clear();
490  findPotentialNewifiableTFRs(*BI);
491 
492  // Traverse instructions in basic block.
493  for(MachineBasicBlock::iterator MI = BI->begin(), End = BI->end();
494  MI != End;) {
495  MachineInstr &I1 = *MI++;
496 
497  if (I1.isDebugInstr())
498  continue;
499 
500  // Don't combine a TFR whose user could be newified (instructions that
501  // define double registers can not be newified - Programmer's Ref Manual
502  // 5.4.2 New-value stores).
503  if (ShouldCombineAggressively && PotentiallyNewifiableTFR.count(&I1))
504  continue;
505 
506  // Ignore instructions that are not combinable.
507  if (!isCombinableInstType(I1, TII, ShouldCombineAggressively))
508  continue;
509 
510  // Find a second instruction that can be merged into a combine
511  // instruction. In addition, also find all the debug instructions that
512  // need to be moved along with it.
513  bool DoInsertAtI1 = false;
514  DbgMItoMove.clear();
515  MachineInstr *I2 = findPairable(I1, DoInsertAtI1, OptForSize);
516  if (I2) {
517  HasChanged = true;
518  combine(I1, *I2, MI, DoInsertAtI1, OptForSize);
519  }
520  }
521  }
522 
523  return HasChanged;
524 }
525 
526 /// findPairable - Returns an instruction that can be merged with \p I1 into a
527 /// COMBINE instruction or 0 if no such instruction can be found. Returns true
528 /// in \p DoInsertAtI1 if the combine must be inserted at instruction \p I1
529 /// false if the combine must be inserted at the returned instruction.
530 MachineInstr *HexagonCopyToCombine::findPairable(MachineInstr &I1,
531  bool &DoInsertAtI1,
532  bool AllowC64) {
534  while (I2 != I1.getParent()->end() && I2->isDebugInstr())
535  ++I2;
536 
537  Register I1DestReg = I1.getOperand(0).getReg();
538 
539  for (MachineBasicBlock::iterator End = I1.getParent()->end(); I2 != End;
540  ++I2) {
541  // Bail out early if we see a second definition of I1DestReg.
542  if (I2->modifiesRegister(I1DestReg, TRI))
543  break;
544 
545  // Ignore non-combinable instructions.
546  if (!isCombinableInstType(*I2, TII, ShouldCombineAggressively))
547  continue;
548 
549  // Don't combine a TFR whose user could be newified.
550  if (ShouldCombineAggressively && PotentiallyNewifiableTFR.count(&*I2))
551  continue;
552 
553  Register I2DestReg = I2->getOperand(0).getReg();
554 
555  // Check that registers are adjacent and that the first destination register
556  // is even.
557  bool IsI1LowReg = (I2DestReg - I1DestReg) == 1;
558  bool IsI2LowReg = (I1DestReg - I2DestReg) == 1;
559  unsigned FirstRegIndex = IsI1LowReg ? I1DestReg : I2DestReg;
560  if ((!IsI1LowReg && !IsI2LowReg) || !isEvenReg(FirstRegIndex))
561  continue;
562 
563  // Check that the two instructions are combinable.
564  // The order matters because in a A2_tfrsi we might can encode a int8 as
565  // the hi reg operand but only a uint6 as the low reg operand.
566  if ((IsI2LowReg && !areCombinableOperations(TRI, I1, *I2, AllowC64)) ||
567  (IsI1LowReg && !areCombinableOperations(TRI, *I2, I1, AllowC64)))
568  break;
569 
570  if (isSafeToMoveTogether(I1, *I2, I1DestReg, I2DestReg, DoInsertAtI1))
571  return &*I2;
572 
573  // Not safe. Stop searching.
574  break;
575  }
576  return nullptr;
577 }
578 
581  bool DoInsertAtI1, bool OptForSize) {
582  // We are going to delete I2. If MI points to I2 advance it to the next
583  // instruction.
584  if (MI == I2.getIterator())
585  ++MI;
586 
587  // Figure out whether I1 or I2 goes into the lowreg part.
588  Register I1DestReg = I1.getOperand(0).getReg();
589  Register I2DestReg = I2.getOperand(0).getReg();
590  bool IsI1Loreg = (I2DestReg - I1DestReg) == 1;
591  unsigned LoRegDef = IsI1Loreg ? I1DestReg : I2DestReg;
592  unsigned SubLo;
593 
594  const TargetRegisterClass *SuperRC = nullptr;
595  if (Hexagon::IntRegsRegClass.contains(LoRegDef)) {
596  SuperRC = &Hexagon::DoubleRegsRegClass;
597  SubLo = Hexagon::isub_lo;
598  } else if (Hexagon::HvxVRRegClass.contains(LoRegDef)) {
599  assert(ST->useHVXOps());
600  SuperRC = &Hexagon::HvxWRRegClass;
601  SubLo = Hexagon::vsub_lo;
602  } else
603  llvm_unreachable("Unexpected register class");
604 
605  // Get the double word register.
606  unsigned DoubleRegDest = TRI->getMatchingSuperReg(LoRegDef, SubLo, SuperRC);
607  assert(DoubleRegDest != 0 && "Expect a valid register");
608 
609  // Setup source operands.
610  MachineOperand &LoOperand = IsI1Loreg ? I1.getOperand(1) : I2.getOperand(1);
611  MachineOperand &HiOperand = IsI1Loreg ? I2.getOperand(1) : I1.getOperand(1);
612 
613  // Figure out which source is a register and which a constant.
614  bool IsHiReg = HiOperand.isReg();
615  bool IsLoReg = LoOperand.isReg();
616 
617  // There is a combine of two constant extended values into CONST64.
618  bool IsC64 = OptForSize && LoOperand.isImm() && HiOperand.isImm() &&
619  isGreaterThanNBitTFRI<16>(I1) && isGreaterThanNBitTFRI<16>(I2);
620 
621  MachineBasicBlock::iterator InsertPt(DoInsertAtI1 ? I1 : I2);
622  // Emit combine.
623  if (IsHiReg && IsLoReg)
624  emitCombineRR(InsertPt, DoubleRegDest, HiOperand, LoOperand);
625  else if (IsHiReg)
626  emitCombineRI(InsertPt, DoubleRegDest, HiOperand, LoOperand);
627  else if (IsLoReg)
628  emitCombineIR(InsertPt, DoubleRegDest, HiOperand, LoOperand);
629  else if (IsC64 && !IsConst64Disabled)
630  emitConst64(InsertPt, DoubleRegDest, HiOperand, LoOperand);
631  else
632  emitCombineII(InsertPt, DoubleRegDest, HiOperand, LoOperand);
633 
634  // Move debug instructions along with I1 if it's being
635  // moved towards I2.
636  if (!DoInsertAtI1 && DbgMItoMove.size() != 0) {
637  // Insert debug instructions at the new location before I2.
638  MachineBasicBlock *BB = InsertPt->getParent();
639  for (auto NewMI : DbgMItoMove) {
640  // If iterator MI is pointing to DEBUG_VAL, make sure
641  // MI now points to next relevant instruction.
642  if (NewMI == MI)
643  ++MI;
644  BB->splice(InsertPt, BB, NewMI);
645  }
646  }
647 
648  I1.eraseFromParent();
649  I2.eraseFromParent();
650 }
651 
652 void HexagonCopyToCombine::emitConst64(MachineBasicBlock::iterator &InsertPt,
653  unsigned DoubleDestReg,
654  MachineOperand &HiOperand,
655  MachineOperand &LoOperand) {
656  LLVM_DEBUG(dbgs() << "Found a CONST64\n");
657 
658  DebugLoc DL = InsertPt->getDebugLoc();
659  MachineBasicBlock *BB = InsertPt->getParent();
660  assert(LoOperand.isImm() && HiOperand.isImm() &&
661  "Both operands must be immediate");
662 
663  int64_t V = HiOperand.getImm();
664  V = (V << 32) | (0x0ffffffffLL & LoOperand.getImm());
665  BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::CONST64), DoubleDestReg)
666  .addImm(V);
667 }
668 
669 void HexagonCopyToCombine::emitCombineII(MachineBasicBlock::iterator &InsertPt,
670  unsigned DoubleDestReg,
671  MachineOperand &HiOperand,
672  MachineOperand &LoOperand) {
673  DebugLoc DL = InsertPt->getDebugLoc();
674  MachineBasicBlock *BB = InsertPt->getParent();
675 
676  // Handle globals.
677  if (HiOperand.isGlobal()) {
678  BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
679  .addGlobalAddress(HiOperand.getGlobal(), HiOperand.getOffset(),
680  HiOperand.getTargetFlags())
681  .addImm(LoOperand.getImm());
682  return;
683  }
684  if (LoOperand.isGlobal()) {
685  BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
686  .addImm(HiOperand.getImm())
687  .addGlobalAddress(LoOperand.getGlobal(), LoOperand.getOffset(),
688  LoOperand.getTargetFlags());
689  return;
690  }
691 
692  // Handle block addresses.
693  if (HiOperand.isBlockAddress()) {
694  BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
695  .addBlockAddress(HiOperand.getBlockAddress(), HiOperand.getOffset(),
696  HiOperand.getTargetFlags())
697  .addImm(LoOperand.getImm());
698  return;
699  }
700  if (LoOperand.isBlockAddress()) {
701  BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
702  .addImm(HiOperand.getImm())
703  .addBlockAddress(LoOperand.getBlockAddress(), LoOperand.getOffset(),
704  LoOperand.getTargetFlags());
705  return;
706  }
707 
708  // Handle jump tables.
709  if (HiOperand.isJTI()) {
710  BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
711  .addJumpTableIndex(HiOperand.getIndex(), HiOperand.getTargetFlags())
712  .addImm(LoOperand.getImm());
713  return;
714  }
715  if (LoOperand.isJTI()) {
716  BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
717  .addImm(HiOperand.getImm())
718  .addJumpTableIndex(LoOperand.getIndex(), LoOperand.getTargetFlags());
719  return;
720  }
721 
722  // Handle constant pools.
723  if (HiOperand.isCPI()) {
724  BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
725  .addConstantPoolIndex(HiOperand.getIndex(), HiOperand.getOffset(),
726  HiOperand.getTargetFlags())
727  .addImm(LoOperand.getImm());
728  return;
729  }
730  if (LoOperand.isCPI()) {
731  BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
732  .addImm(HiOperand.getImm())
733  .addConstantPoolIndex(LoOperand.getIndex(), LoOperand.getOffset(),
734  LoOperand.getTargetFlags());
735  return;
736  }
737 
738  // First preference should be given to Hexagon::A2_combineii instruction
739  // as it can include U6 (in Hexagon::A4_combineii) as well.
740  // In this instruction, HiOperand is const extended, if required.
741  if (isInt<8>(LoOperand.getImm())) {
742  BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
743  .addImm(HiOperand.getImm())
744  .addImm(LoOperand.getImm());
745  return;
746  }
747 
748  // In this instruction, LoOperand is const extended, if required.
749  if (isInt<8>(HiOperand.getImm())) {
750  BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
751  .addImm(HiOperand.getImm())
752  .addImm(LoOperand.getImm());
753  return;
754  }
755 
756  // Insert new combine instruction.
757  // DoubleRegDest = combine #HiImm, #LoImm
758  BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
759  .addImm(HiOperand.getImm())
760  .addImm(LoOperand.getImm());
761 }
762 
763 void HexagonCopyToCombine::emitCombineIR(MachineBasicBlock::iterator &InsertPt,
764  unsigned DoubleDestReg,
765  MachineOperand &HiOperand,
766  MachineOperand &LoOperand) {
767  Register LoReg = LoOperand.getReg();
768  unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
769 
770  DebugLoc DL = InsertPt->getDebugLoc();
771  MachineBasicBlock *BB = InsertPt->getParent();
772 
773  // Handle globals.
774  if (HiOperand.isGlobal()) {
775  BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
776  .addGlobalAddress(HiOperand.getGlobal(), HiOperand.getOffset(),
777  HiOperand.getTargetFlags())
778  .addReg(LoReg, LoRegKillFlag);
779  return;
780  }
781  // Handle block addresses.
782  if (HiOperand.isBlockAddress()) {
783  BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
784  .addBlockAddress(HiOperand.getBlockAddress(), HiOperand.getOffset(),
785  HiOperand.getTargetFlags())
786  .addReg(LoReg, LoRegKillFlag);
787  return;
788  }
789  // Handle jump tables.
790  if (HiOperand.isJTI()) {
791  BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
792  .addJumpTableIndex(HiOperand.getIndex(), HiOperand.getTargetFlags())
793  .addReg(LoReg, LoRegKillFlag);
794  return;
795  }
796  // Handle constant pools.
797  if (HiOperand.isCPI()) {
798  BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
799  .addConstantPoolIndex(HiOperand.getIndex(), HiOperand.getOffset(),
800  HiOperand.getTargetFlags())
801  .addReg(LoReg, LoRegKillFlag);
802  return;
803  }
804  // Insert new combine instruction.
805  // DoubleRegDest = combine #HiImm, LoReg
806  BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
807  .addImm(HiOperand.getImm())
808  .addReg(LoReg, LoRegKillFlag);
809 }
810 
811 void HexagonCopyToCombine::emitCombineRI(MachineBasicBlock::iterator &InsertPt,
812  unsigned DoubleDestReg,
813  MachineOperand &HiOperand,
814  MachineOperand &LoOperand) {
815  unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
816  Register HiReg = HiOperand.getReg();
817 
818  DebugLoc DL = InsertPt->getDebugLoc();
819  MachineBasicBlock *BB = InsertPt->getParent();
820 
821  // Handle global.
822  if (LoOperand.isGlobal()) {
823  BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
824  .addReg(HiReg, HiRegKillFlag)
825  .addGlobalAddress(LoOperand.getGlobal(), LoOperand.getOffset(),
826  LoOperand.getTargetFlags());
827  return;
828  }
829  // Handle block addresses.
830  if (LoOperand.isBlockAddress()) {
831  BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
832  .addReg(HiReg, HiRegKillFlag)
833  .addBlockAddress(LoOperand.getBlockAddress(), LoOperand.getOffset(),
834  LoOperand.getTargetFlags());
835  return;
836  }
837  // Handle jump tables.
838  if (LoOperand.isJTI()) {
839  BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
840  .addReg(HiOperand.getReg(), HiRegKillFlag)
841  .addJumpTableIndex(LoOperand.getIndex(), LoOperand.getTargetFlags());
842  return;
843  }
844  // Handle constant pools.
845  if (LoOperand.isCPI()) {
846  BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
847  .addReg(HiOperand.getReg(), HiRegKillFlag)
848  .addConstantPoolIndex(LoOperand.getIndex(), LoOperand.getOffset(),
849  LoOperand.getTargetFlags());
850  return;
851  }
852 
853  // Insert new combine instruction.
854  // DoubleRegDest = combine HiReg, #LoImm
855  BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
856  .addReg(HiReg, HiRegKillFlag)
857  .addImm(LoOperand.getImm());
858 }
859 
860 void HexagonCopyToCombine::emitCombineRR(MachineBasicBlock::iterator &InsertPt,
861  unsigned DoubleDestReg,
862  MachineOperand &HiOperand,
863  MachineOperand &LoOperand) {
864  unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
865  unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
866  Register LoReg = LoOperand.getReg();
867  Register HiReg = HiOperand.getReg();
868 
869  DebugLoc DL = InsertPt->getDebugLoc();
870  MachineBasicBlock *BB = InsertPt->getParent();
871 
872  // Insert new combine instruction.
873  // DoubleRegDest = combine HiReg, LoReg
874  unsigned NewOpc;
875  if (Hexagon::DoubleRegsRegClass.contains(DoubleDestReg)) {
876  NewOpc = Hexagon::A2_combinew;
877  } else if (Hexagon::HvxWRRegClass.contains(DoubleDestReg)) {
878  assert(ST->useHVXOps());
879  NewOpc = Hexagon::V6_vcombine;
880  } else
881  llvm_unreachable("Unexpected register");
882 
883  BuildMI(*BB, InsertPt, DL, TII->get(NewOpc), DoubleDestReg)
884  .addReg(HiReg, HiRegKillFlag)
885  .addReg(LoReg, LoRegKillFlag);
886 }
887 
889  return new HexagonCopyToCombine();
890 }
llvm::TargetMachine::getOptLevel
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:185
IsConst64Disabled
static cl::opt< bool > IsConst64Disabled("disable-const64", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable generation of const64"))
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
MachineInstr.h
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const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MachineOperand::isBlockAddress
bool isBlockAddress() const
isBlockAddress - Tests if this is a MO_BlockAddress operand.
Definition: MachineOperand.h:343
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:563
llvm::Function
Definition: Function.h:61
Pass.h
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return AArch64::GPR64RegClass contains(Reg)
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This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
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iterator end()
Definition: MachineFunction.h:810
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const BlockAddress * getBlockAddress() const
Definition: MachineOperand.h:568
HexagonSubtarget.h
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MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
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@ Hidden
Definition: CommandLine.h:143
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
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bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
Definition: MachineOperand.h:337
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Properties which a MachineFunction may have at a given point in time.
Definition: MachineFunction.h:111
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std::pair< iterator, bool > insert(const ValueT &V)
Definition: DenseSet.h:206
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static bool isGreaterThanNBitTFRI(const MachineInstr &I)
Definition: HexagonCopyToCombine.cpp:174
llvm::MachineOperand::getOffset
int64_t getOffset() const
Return the offset from the symbol in this operand.
Definition: MachineOperand.h:600
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size_type count(const_arg_type_t< ValueT > V) const
Return 1 if the specified key is in the set, 0 otherwise.
Definition: DenseSet.h:97
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
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void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
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#define LLVM_DEBUG(X)
Definition: Debug.h:101
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
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bool isKill() const
Definition: MachineOperand.h:390
CommandLine.h
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bool mayBeNewStore(const MachineInstr &MI) const
Definition: HexagonInstrInfo.cpp:3084
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static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
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int64_t getImm() const
Definition: MachineOperand.h:537
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const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
INITIALIZE_PASS
INITIALIZE_PASS(HexagonCopyToCombine, "hexagon-copy-combine", "Hexagon Copy-To-Combine Pass", false, false) static bool isCombinableInstType(MachineInstr &MI
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
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bool isDebugInstr() const
Definition: MachineInstr.h:1222
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bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
Definition: MachineInstr.cpp:1878
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
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MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineFunctionProperties::set
MachineFunctionProperties & set(Property P)
Definition: MachineFunction.h:169
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
areCombinableOperations
static bool areCombinableOperations(const TargetRegisterInfo *TRI, MachineInstr &HighRegInst, MachineInstr &LowRegInst, bool AllowC64)
areCombinableOperations - Returns true if the two instruction can be merge into a combine (ignoring r...
Definition: HexagonCopyToCombine.cpp:185
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iterator begin()
Definition: MachineFunction.h:808
IsCombinesDisabled
static cl::opt< bool > IsCombinesDisabled("disable-merge-into-combines", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable merging into combines"))
HexagonInstrInfo.h
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bool killsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
Definition: MachineInstr.h:1389
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Definition: MachineBasicBlock.h:95
isEvenReg
static bool isEvenReg(unsigned Reg)
Definition: HexagonCopyToCombine.cpp:230
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@ NoVRegs
llvm::cl::ZeroOrMore
@ ZeroOrMore
Definition: CommandLine.h:120
Passes.h
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constexpr bool isInt< 8 >(int64_t x)
Definition: MathExtras.h:367
llvm::DenseSet
Implements a dense probed hash-table based set.
Definition: DenseSet.h:268
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
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llvm::CodeGenOpt::Default
@ Default
Definition: CodeGen.h:55
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition: MachineOperand.h:221
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bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
const
aarch64 promote const
Definition: AArch64PromoteConstant.cpp:232
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@ ST
Definition: ARMBaseInfo.h:73
UseReg
static Register UseReg(const MachineOperand &MO)
Definition: HexagonCopyToCombine.cpp:259
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@ MO_NO_FLAG
Definition: HexagonBaseInfo.h:177
ShouldCombineAggressively
const HexagonInstrInfo bool ShouldCombineAggressively
Definition: HexagonCopyToCombine.cpp:130
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Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: TargetRegisterInfo.h:577
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Definition: DenseMap.h:714
I
#define I(x, y, z)
Definition: MD5.cpp:59
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initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
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bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
Definition: MachineOperand.h:333
MachineFunctionPass.h
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FunctionPass * createHexagonCopyToCombine()
Definition: HexagonCopyToCombine.cpp:888
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
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Returns true if it is unsafe to move a copy instruction from UseReg to DestReg over the instruction M...
Definition: HexagonCopyToCombine.cpp:250
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const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::detail::DenseSetImpl< ValueT, DenseMap< ValueT, detail::DenseSetEmpty, DenseMapInfo< ValueT >, detail::DenseSetPair< ValueT > >, DenseMapInfo< ValueT > >::clear
void clear()
Definition: DenseSet.h:92
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Definition: HexagonInstrInfo.h:38
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
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unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:489
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const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:171
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#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:81
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
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const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:190
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:286
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineInstr::modifiesRegister
bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr modifies (fully define or partially define) the specified register.
Definition: MachineInstr.h:1406
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void initializeHexagonCopyToCombinePass(PassRegistry &)
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:592
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:622
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:321
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
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int getIndex() const
Definition: MachineOperand.h:557
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const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:158
llvm::SmallVectorImpl::clear
void clear()
Definition: SmallVector.h:585
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bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:323
MaxNumOfInstsBetweenNewValueStoreAndTFR
static cl::opt< unsigned > MaxNumOfInstsBetweenNewValueStoreAndTFR("max-num-inst-between-tfr-and-nv-store", cl::Hidden, cl::init(4), cl::desc("Maximum distance between a tfr feeding a store we " "consider the store still to be newifiable"))
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const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:177
CodeGen.h
llvm::MCSubRegIterator
MCSubRegIterator enumerates all sub-registers of Reg.
Definition: MCRegisterInfo.h:594
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
llvm::ilist_iterator::getReverse
ilist_iterator< OptionsT, !IsReverse, IsConst > getReverse() const
Get a reverse iterator to the same node.
Definition: ilist_iterator.h:121
MachineInstrBuilder.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::HexagonSubtarget
Definition: HexagonSubtarget.h:43
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::cl::desc
Definition: CommandLine.h:414
raw_ostream.h
MachineFunction.h
combine
vector combine
Definition: VectorCombine.cpp:1137
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:677
llvm::MachineInstrBundleIterator< MachineInstr >
TargetRegisterInfo.h
Debug.h
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
removeKillInfo
static void removeKillInfo(MachineInstr &MI, unsigned RegNotKilled)
Definition: HexagonCopyToCombine.cpp:239
llvm::MachineOperand::isGlobal
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Definition: MachineOperand.h:339
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37