LLVM  9.0.0svn
IRTranslator.cpp
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1 //===- llvm/CodeGen/GlobalISel/IRTranslator.cpp - IRTranslator ---*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the IRTranslator class.
10 //===----------------------------------------------------------------------===//
11 
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/ScopeExit.h"
16 #include "llvm/ADT/SmallSet.h"
17 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/Analysis.h"
37 #include "llvm/IR/BasicBlock.h"
38 #include "llvm/IR/CFG.h"
39 #include "llvm/IR/Constant.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/InstrTypes.h"
48 #include "llvm/IR/Instructions.h"
49 #include "llvm/IR/IntrinsicInst.h"
50 #include "llvm/IR/Intrinsics.h"
51 #include "llvm/IR/LLVMContext.h"
52 #include "llvm/IR/Metadata.h"
53 #include "llvm/IR/Type.h"
54 #include "llvm/IR/User.h"
55 #include "llvm/IR/Value.h"
56 #include "llvm/MC/MCContext.h"
57 #include "llvm/Pass.h"
58 #include "llvm/Support/Casting.h"
59 #include "llvm/Support/CodeGen.h"
60 #include "llvm/Support/Debug.h"
67 #include <algorithm>
68 #include <cassert>
69 #include <cstdint>
70 #include <iterator>
71 #include <string>
72 #include <utility>
73 #include <vector>
74 
75 #define DEBUG_TYPE "irtranslator"
76 
77 using namespace llvm;
78 
79 static cl::opt<bool>
80  EnableCSEInIRTranslator("enable-cse-in-irtranslator",
81  cl::desc("Should enable CSE in irtranslator"),
82  cl::Optional, cl::init(false));
83 char IRTranslator::ID = 0;
84 
85 INITIALIZE_PASS_BEGIN(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI",
86  false, false)
89 INITIALIZE_PASS_END(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI",
90  false, false)
91 
97 
98  // Print the function name explicitly if we don't have a debug location (which
99  // makes the diagnostic less useful) or if we're going to emit a raw error.
100  if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled())
101  R << (" (in function: " + MF.getName() + ")").str();
102 
103  if (TPC.isGlobalISelAbortEnabled())
104  report_fatal_error(R.getMsg());
105  else
106  ORE.emit(R);
107 }
108 
110 
111 #ifndef NDEBUG
112 namespace {
113 /// Verify that every instruction created has the same DILocation as the
114 /// instruction being translated.
115 class DILocationVerifier : public GISelChangeObserver {
116  const Instruction *CurrInst = nullptr;
117 
118 public:
119  DILocationVerifier() = default;
120  ~DILocationVerifier() = default;
121 
122  const Instruction *getCurrentInst() const { return CurrInst; }
123  void setCurrentInst(const Instruction *Inst) { CurrInst = Inst; }
124 
125  void erasingInstr(MachineInstr &MI) override {}
126  void changingInstr(MachineInstr &MI) override {}
127  void changedInstr(MachineInstr &MI) override {}
128 
129  void createdInstr(MachineInstr &MI) override {
130  assert(getCurrentInst() && "Inserted instruction without a current MI");
131 
132  // Only print the check message if we're actually checking it.
133 #ifndef NDEBUG
134  LLVM_DEBUG(dbgs() << "Checking DILocation from " << *CurrInst
135  << " was copied to " << MI);
136 #endif
137  // We allow insts in the entry block to have a debug loc line of 0 because
138  // they could have originated from constants, and we don't want a jumpy
139  // debug experience.
140  assert((CurrInst->getDebugLoc() == MI.getDebugLoc() ||
141  MI.getDebugLoc().getLine() == 0) &&
142  "Line info was not transferred to all instructions");
143  }
144 };
145 } // namespace
146 #endif // ifndef NDEBUG
147 
148 
155 }
156 
158 IRTranslator::allocateVRegs(const Value &Val) {
159  assert(!VMap.contains(Val) && "Value already allocated in VMap");
160  auto *Regs = VMap.getVRegs(Val);
161  auto *Offsets = VMap.getOffsets(Val);
162  SmallVector<LLT, 4> SplitTys;
163  computeValueLLTs(*DL, *Val.getType(), SplitTys,
164  Offsets->empty() ? Offsets : nullptr);
165  for (unsigned i = 0; i < SplitTys.size(); ++i)
166  Regs->push_back(0);
167  return *Regs;
168 }
169 
170 ArrayRef<unsigned> IRTranslator::getOrCreateVRegs(const Value &Val) {
171  auto VRegsIt = VMap.findVRegs(Val);
172  if (VRegsIt != VMap.vregs_end())
173  return *VRegsIt->second;
174 
175  if (Val.getType()->isVoidTy())
176  return *VMap.getVRegs(Val);
177 
178  // Create entry for this type.
179  auto *VRegs = VMap.getVRegs(Val);
180  auto *Offsets = VMap.getOffsets(Val);
181 
182  assert(Val.getType()->isSized() &&
183  "Don't know how to create an empty vreg");
184 
185  SmallVector<LLT, 4> SplitTys;
186  computeValueLLTs(*DL, *Val.getType(), SplitTys,
187  Offsets->empty() ? Offsets : nullptr);
188 
189  if (!isa<Constant>(Val)) {
190  for (auto Ty : SplitTys)
191  VRegs->push_back(MRI->createGenericVirtualRegister(Ty));
192  return *VRegs;
193  }
194 
195  if (Val.getType()->isAggregateType()) {
196  // UndefValue, ConstantAggregateZero
197  auto &C = cast<Constant>(Val);
198  unsigned Idx = 0;
199  while (auto Elt = C.getAggregateElement(Idx++)) {
200  auto EltRegs = getOrCreateVRegs(*Elt);
201  llvm::copy(EltRegs, std::back_inserter(*VRegs));
202  }
203  } else {
204  assert(SplitTys.size() == 1 && "unexpectedly split LLT");
205  VRegs->push_back(MRI->createGenericVirtualRegister(SplitTys[0]));
206  bool Success = translate(cast<Constant>(Val), VRegs->front());
207  if (!Success) {
208  OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
209  MF->getFunction().getSubprogram(),
210  &MF->getFunction().getEntryBlock());
211  R << "unable to translate constant: " << ore::NV("Type", Val.getType());
212  reportTranslationError(*MF, *TPC, *ORE, R);
213  return *VRegs;
214  }
215  }
216 
217  return *VRegs;
218 }
219 
220 int IRTranslator::getOrCreateFrameIndex(const AllocaInst &AI) {
221  if (FrameIndices.find(&AI) != FrameIndices.end())
222  return FrameIndices[&AI];
223 
224  unsigned ElementSize = DL->getTypeAllocSize(AI.getAllocatedType());
225  unsigned Size =
226  ElementSize * cast<ConstantInt>(AI.getArraySize())->getZExtValue();
227 
228  // Always allocate at least one byte.
229  Size = std::max(Size, 1u);
230 
231  unsigned Alignment = AI.getAlignment();
232  if (!Alignment)
233  Alignment = DL->getABITypeAlignment(AI.getAllocatedType());
234 
235  int &FI = FrameIndices[&AI];
236  FI = MF->getFrameInfo().CreateStackObject(Size, Alignment, false, &AI);
237  return FI;
238 }
239 
240 unsigned IRTranslator::getMemOpAlignment(const Instruction &I) {
241  unsigned Alignment = 0;
242  Type *ValTy = nullptr;
243  if (const StoreInst *SI = dyn_cast<StoreInst>(&I)) {
244  Alignment = SI->getAlignment();
245  ValTy = SI->getValueOperand()->getType();
246  } else if (const LoadInst *LI = dyn_cast<LoadInst>(&I)) {
247  Alignment = LI->getAlignment();
248  ValTy = LI->getType();
249  } else if (const AtomicCmpXchgInst *AI = dyn_cast<AtomicCmpXchgInst>(&I)) {
250  // TODO(PR27168): This instruction has no alignment attribute, but unlike
251  // the default alignment for load/store, the default here is to assume
252  // it has NATURAL alignment, not DataLayout-specified alignment.
253  const DataLayout &DL = AI->getModule()->getDataLayout();
254  Alignment = DL.getTypeStoreSize(AI->getCompareOperand()->getType());
255  ValTy = AI->getCompareOperand()->getType();
256  } else if (const AtomicRMWInst *AI = dyn_cast<AtomicRMWInst>(&I)) {
257  // TODO(PR27168): This instruction has no alignment attribute, but unlike
258  // the default alignment for load/store, the default here is to assume
259  // it has NATURAL alignment, not DataLayout-specified alignment.
260  const DataLayout &DL = AI->getModule()->getDataLayout();
261  Alignment = DL.getTypeStoreSize(AI->getValOperand()->getType());
262  ValTy = AI->getType();
263  } else {
264  OptimizationRemarkMissed R("gisel-irtranslator", "", &I);
265  R << "unable to translate memop: " << ore::NV("Opcode", &I);
266  reportTranslationError(*MF, *TPC, *ORE, R);
267  return 1;
268  }
269 
270  return Alignment ? Alignment : DL->getABITypeAlignment(ValTy);
271 }
272 
273 MachineBasicBlock &IRTranslator::getMBB(const BasicBlock &BB) {
274  MachineBasicBlock *&MBB = BBToMBB[&BB];
275  assert(MBB && "BasicBlock was not encountered before");
276  return *MBB;
277 }
278 
279 void IRTranslator::addMachineCFGPred(CFGEdge Edge, MachineBasicBlock *NewPred) {
280  assert(NewPred && "new predecessor must be a real MachineBasicBlock");
281  MachinePreds[Edge].push_back(NewPred);
282 }
283 
284 bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U,
285  MachineIRBuilder &MIRBuilder) {
286  // Get or create a virtual register for each value.
287  // Unless the value is a Constant => loadimm cst?
288  // or inline constant each time?
289  // Creation of a virtual register needs to have a size.
290  unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
291  unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
292  unsigned Res = getOrCreateVReg(U);
293  uint16_t Flags = 0;
294  if (isa<Instruction>(U)) {
295  const Instruction &I = cast<Instruction>(U);
297  }
298 
299  MIRBuilder.buildInstr(Opcode, {Res}, {Op0, Op1}, Flags);
300  return true;
301 }
302 
303 bool IRTranslator::translateFSub(const User &U, MachineIRBuilder &MIRBuilder) {
304  // -0.0 - X --> G_FNEG
305  if (isa<Constant>(U.getOperand(0)) &&
307  unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
308  unsigned Res = getOrCreateVReg(U);
309  uint16_t Flags = 0;
310  if (isa<Instruction>(U)) {
311  const Instruction &I = cast<Instruction>(U);
313  }
314  // Negate the last operand of the FSUB
315  MIRBuilder.buildInstr(TargetOpcode::G_FNEG, {Res}, {Op1}, Flags);
316  return true;
317  }
318  return translateBinaryOp(TargetOpcode::G_FSUB, U, MIRBuilder);
319 }
320 
321 bool IRTranslator::translateFNeg(const User &U, MachineIRBuilder &MIRBuilder) {
322  unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
323  unsigned Res = getOrCreateVReg(U);
324  uint16_t Flags = 0;
325  if (isa<Instruction>(U)) {
326  const Instruction &I = cast<Instruction>(U);
328  }
329  MIRBuilder.buildInstr(TargetOpcode::G_FNEG, {Res}, {Op0}, Flags);
330  return true;
331 }
332 
333 bool IRTranslator::translateCompare(const User &U,
334  MachineIRBuilder &MIRBuilder) {
335  const CmpInst *CI = dyn_cast<CmpInst>(&U);
336  unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
337  unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
338  unsigned Res = getOrCreateVReg(U);
339  CmpInst::Predicate Pred =
340  CI ? CI->getPredicate() : static_cast<CmpInst::Predicate>(
341  cast<ConstantExpr>(U).getPredicate());
342  if (CmpInst::isIntPredicate(Pred))
343  MIRBuilder.buildICmp(Pred, Res, Op0, Op1);
344  else if (Pred == CmpInst::FCMP_FALSE)
345  MIRBuilder.buildCopy(
346  Res, getOrCreateVReg(*Constant::getNullValue(CI->getType())));
347  else if (Pred == CmpInst::FCMP_TRUE)
348  MIRBuilder.buildCopy(
349  Res, getOrCreateVReg(*Constant::getAllOnesValue(CI->getType())));
350  else {
351  MIRBuilder.buildInstr(TargetOpcode::G_FCMP, {Res}, {Pred, Op0, Op1},
353  }
354 
355  return true;
356 }
357 
358 bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) {
359  const ReturnInst &RI = cast<ReturnInst>(U);
360  const Value *Ret = RI.getReturnValue();
361  if (Ret && DL->getTypeStoreSize(Ret->getType()) == 0)
362  Ret = nullptr;
363 
364  ArrayRef<unsigned> VRegs;
365  if (Ret)
366  VRegs = getOrCreateVRegs(*Ret);
367 
368  unsigned SwiftErrorVReg = 0;
369  if (CLI->supportSwiftError() && SwiftError.getFunctionArg()) {
370  SwiftErrorVReg = SwiftError.getOrCreateVRegUseAt(
371  &RI, &MIRBuilder.getMBB(), SwiftError.getFunctionArg());
372  }
373 
374  // The target may mess up with the insertion point, but
375  // this is not important as a return is the last instruction
376  // of the block anyway.
377  return CLI->lowerReturn(MIRBuilder, Ret, VRegs, SwiftErrorVReg);
378 }
379 
380 bool IRTranslator::translateBr(const User &U, MachineIRBuilder &MIRBuilder) {
381  const BranchInst &BrInst = cast<BranchInst>(U);
382  unsigned Succ = 0;
383  if (!BrInst.isUnconditional()) {
384  // We want a G_BRCOND to the true BB followed by an unconditional branch.
385  unsigned Tst = getOrCreateVReg(*BrInst.getCondition());
386  const BasicBlock &TrueTgt = *cast<BasicBlock>(BrInst.getSuccessor(Succ++));
387  MachineBasicBlock &TrueBB = getMBB(TrueTgt);
388  MIRBuilder.buildBrCond(Tst, TrueBB);
389  }
390 
391  const BasicBlock &BrTgt = *cast<BasicBlock>(BrInst.getSuccessor(Succ));
392  MachineBasicBlock &TgtBB = getMBB(BrTgt);
393  MachineBasicBlock &CurBB = MIRBuilder.getMBB();
394 
395  // If the unconditional target is the layout successor, fallthrough.
396  if (!CurBB.isLayoutSuccessor(&TgtBB))
397  MIRBuilder.buildBr(TgtBB);
398 
399  // Link successors.
400  for (const BasicBlock *Succ : successors(&BrInst))
401  CurBB.addSuccessor(&getMBB(*Succ));
402  return true;
403 }
404 
405 bool IRTranslator::translateSwitch(const User &U,
406  MachineIRBuilder &MIRBuilder) {
407  // For now, just translate as a chain of conditional branches.
408  // FIXME: could we share most of the logic/code in
409  // SelectionDAGBuilder::visitSwitch between SelectionDAG and GlobalISel?
410  // At first sight, it seems most of the logic in there is independent of
411  // SelectionDAG-specifics and a lot of work went in to optimize switch
412  // lowering in there.
413 
414  const SwitchInst &SwInst = cast<SwitchInst>(U);
415  const unsigned SwCondValue = getOrCreateVReg(*SwInst.getCondition());
416  const BasicBlock *OrigBB = SwInst.getParent();
417 
418  LLT LLTi1 = getLLTForType(*Type::getInt1Ty(U.getContext()), *DL);
419  for (auto &CaseIt : SwInst.cases()) {
420  const unsigned CaseValueReg = getOrCreateVReg(*CaseIt.getCaseValue());
421  const unsigned Tst = MRI->createGenericVirtualRegister(LLTi1);
422  MIRBuilder.buildICmp(CmpInst::ICMP_EQ, Tst, CaseValueReg, SwCondValue);
423  MachineBasicBlock &CurMBB = MIRBuilder.getMBB();
424  const BasicBlock *TrueBB = CaseIt.getCaseSuccessor();
425  MachineBasicBlock &TrueMBB = getMBB(*TrueBB);
426 
427  MIRBuilder.buildBrCond(Tst, TrueMBB);
428  CurMBB.addSuccessor(&TrueMBB);
429  addMachineCFGPred({OrigBB, TrueBB}, &CurMBB);
430 
431  MachineBasicBlock *FalseMBB =
432  MF->CreateMachineBasicBlock(SwInst.getParent());
433  // Insert the comparison blocks one after the other.
434  MF->insert(std::next(CurMBB.getIterator()), FalseMBB);
435  MIRBuilder.buildBr(*FalseMBB);
436  CurMBB.addSuccessor(FalseMBB);
437 
438  MIRBuilder.setMBB(*FalseMBB);
439  }
440  // handle default case
441  const BasicBlock *DefaultBB = SwInst.getDefaultDest();
442  MachineBasicBlock &DefaultMBB = getMBB(*DefaultBB);
443  MIRBuilder.buildBr(DefaultMBB);
444  MachineBasicBlock &CurMBB = MIRBuilder.getMBB();
445  CurMBB.addSuccessor(&DefaultMBB);
446  addMachineCFGPred({OrigBB, DefaultBB}, &CurMBB);
447 
448  return true;
449 }
450 
451 bool IRTranslator::translateIndirectBr(const User &U,
452  MachineIRBuilder &MIRBuilder) {
453  const IndirectBrInst &BrInst = cast<IndirectBrInst>(U);
454 
455  const unsigned Tgt = getOrCreateVReg(*BrInst.getAddress());
456  MIRBuilder.buildBrIndirect(Tgt);
457 
458  // Link successors.
459  MachineBasicBlock &CurBB = MIRBuilder.getMBB();
460  for (const BasicBlock *Succ : successors(&BrInst))
461  CurBB.addSuccessor(&getMBB(*Succ));
462 
463  return true;
464 }
465 
466 static bool isSwiftError(const Value *V) {
467  if (auto Arg = dyn_cast<Argument>(V))
468  return Arg->hasSwiftErrorAttr();
469  if (auto AI = dyn_cast<AllocaInst>(V))
470  return AI->isSwiftError();
471  return false;
472 }
473 
474 bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
475  const LoadInst &LI = cast<LoadInst>(U);
476 
477  auto Flags = LI.isVolatile() ? MachineMemOperand::MOVolatile
479  Flags |= MachineMemOperand::MOLoad;
480 
481  if (DL->getTypeStoreSize(LI.getType()) == 0)
482  return true;
483 
484  ArrayRef<unsigned> Regs = getOrCreateVRegs(LI);
485  ArrayRef<uint64_t> Offsets = *VMap.getOffsets(LI);
486  unsigned Base = getOrCreateVReg(*LI.getPointerOperand());
487 
488  Type *OffsetIRTy = DL->getIntPtrType(LI.getPointerOperandType());
489  LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
490 
491  if (CLI->supportSwiftError() && isSwiftError(LI.getPointerOperand())) {
492  assert(Regs.size() == 1 && "swifterror should be single pointer");
493  unsigned VReg = SwiftError.getOrCreateVRegUseAt(&LI, &MIRBuilder.getMBB(),
494  LI.getPointerOperand());
495  MIRBuilder.buildCopy(Regs[0], VReg);
496  return true;
497  }
498 
499 
500  for (unsigned i = 0; i < Regs.size(); ++i) {
501  unsigned Addr = 0;
502  MIRBuilder.materializeGEP(Addr, Base, OffsetTy, Offsets[i] / 8);
503 
504  MachinePointerInfo Ptr(LI.getPointerOperand(), Offsets[i] / 8);
505  unsigned BaseAlign = getMemOpAlignment(LI);
506  auto MMO = MF->getMachineMemOperand(
507  Ptr, Flags, (MRI->getType(Regs[i]).getSizeInBits() + 7) / 8,
508  MinAlign(BaseAlign, Offsets[i] / 8), AAMDNodes(), nullptr,
509  LI.getSyncScopeID(), LI.getOrdering());
510  MIRBuilder.buildLoad(Regs[i], Addr, *MMO);
511  }
512 
513  return true;
514 }
515 
516 bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
517  const StoreInst &SI = cast<StoreInst>(U);
518  auto Flags = SI.isVolatile() ? MachineMemOperand::MOVolatile
521 
522  if (DL->getTypeStoreSize(SI.getValueOperand()->getType()) == 0)
523  return true;
524 
525  ArrayRef<unsigned> Vals = getOrCreateVRegs(*SI.getValueOperand());
526  ArrayRef<uint64_t> Offsets = *VMap.getOffsets(*SI.getValueOperand());
527  unsigned Base = getOrCreateVReg(*SI.getPointerOperand());
528 
529  Type *OffsetIRTy = DL->getIntPtrType(SI.getPointerOperandType());
530  LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
531 
532  if (CLI->supportSwiftError() && isSwiftError(SI.getPointerOperand())) {
533  assert(Vals.size() == 1 && "swifterror should be single pointer");
534 
535  unsigned VReg = SwiftError.getOrCreateVRegDefAt(&SI, &MIRBuilder.getMBB(),
536  SI.getPointerOperand());
537  MIRBuilder.buildCopy(VReg, Vals[0]);
538  return true;
539  }
540 
541  for (unsigned i = 0; i < Vals.size(); ++i) {
542  unsigned Addr = 0;
543  MIRBuilder.materializeGEP(Addr, Base, OffsetTy, Offsets[i] / 8);
544 
545  MachinePointerInfo Ptr(SI.getPointerOperand(), Offsets[i] / 8);
546  unsigned BaseAlign = getMemOpAlignment(SI);
547  auto MMO = MF->getMachineMemOperand(
548  Ptr, Flags, (MRI->getType(Vals[i]).getSizeInBits() + 7) / 8,
549  MinAlign(BaseAlign, Offsets[i] / 8), AAMDNodes(), nullptr,
550  SI.getSyncScopeID(), SI.getOrdering());
551  MIRBuilder.buildStore(Vals[i], Addr, *MMO);
552  }
553  return true;
554 }
555 
556 static uint64_t getOffsetFromIndices(const User &U, const DataLayout &DL) {
557  const Value *Src = U.getOperand(0);
559 
560  // getIndexedOffsetInType is designed for GEPs, so the first index is the
561  // usual array element rather than looking into the actual aggregate.
562  SmallVector<Value *, 1> Indices;
563  Indices.push_back(ConstantInt::get(Int32Ty, 0));
564 
565  if (const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(&U)) {
566  for (auto Idx : EVI->indices())
567  Indices.push_back(ConstantInt::get(Int32Ty, Idx));
568  } else if (const InsertValueInst *IVI = dyn_cast<InsertValueInst>(&U)) {
569  for (auto Idx : IVI->indices())
570  Indices.push_back(ConstantInt::get(Int32Ty, Idx));
571  } else {
572  for (unsigned i = 1; i < U.getNumOperands(); ++i)
573  Indices.push_back(U.getOperand(i));
574  }
575 
576  return 8 * static_cast<uint64_t>(
577  DL.getIndexedOffsetInType(Src->getType(), Indices));
578 }
579 
580 bool IRTranslator::translateExtractValue(const User &U,
581  MachineIRBuilder &MIRBuilder) {
582  const Value *Src = U.getOperand(0);
583  uint64_t Offset = getOffsetFromIndices(U, *DL);
584  ArrayRef<unsigned> SrcRegs = getOrCreateVRegs(*Src);
585  ArrayRef<uint64_t> Offsets = *VMap.getOffsets(*Src);
586  unsigned Idx = llvm::lower_bound(Offsets, Offset) - Offsets.begin();
587  auto &DstRegs = allocateVRegs(U);
588 
589  for (unsigned i = 0; i < DstRegs.size(); ++i)
590  DstRegs[i] = SrcRegs[Idx++];
591 
592  return true;
593 }
594 
595 bool IRTranslator::translateInsertValue(const User &U,
596  MachineIRBuilder &MIRBuilder) {
597  const Value *Src = U.getOperand(0);
598  uint64_t Offset = getOffsetFromIndices(U, *DL);
599  auto &DstRegs = allocateVRegs(U);
600  ArrayRef<uint64_t> DstOffsets = *VMap.getOffsets(U);
601  ArrayRef<unsigned> SrcRegs = getOrCreateVRegs(*Src);
602  ArrayRef<unsigned> InsertedRegs = getOrCreateVRegs(*U.getOperand(1));
603  auto InsertedIt = InsertedRegs.begin();
604 
605  for (unsigned i = 0; i < DstRegs.size(); ++i) {
606  if (DstOffsets[i] >= Offset && InsertedIt != InsertedRegs.end())
607  DstRegs[i] = *InsertedIt++;
608  else
609  DstRegs[i] = SrcRegs[i];
610  }
611 
612  return true;
613 }
614 
615 bool IRTranslator::translateSelect(const User &U,
616  MachineIRBuilder &MIRBuilder) {
617  unsigned Tst = getOrCreateVReg(*U.getOperand(0));
618  ArrayRef<unsigned> ResRegs = getOrCreateVRegs(U);
619  ArrayRef<unsigned> Op0Regs = getOrCreateVRegs(*U.getOperand(1));
620  ArrayRef<unsigned> Op1Regs = getOrCreateVRegs(*U.getOperand(2));
621 
622  const SelectInst &SI = cast<SelectInst>(U);
623  uint16_t Flags = 0;
624  if (const CmpInst *Cmp = dyn_cast<CmpInst>(SI.getCondition()))
626 
627  for (unsigned i = 0; i < ResRegs.size(); ++i) {
628  MIRBuilder.buildInstr(TargetOpcode::G_SELECT, {ResRegs[i]},
629  {Tst, Op0Regs[i], Op1Regs[i]}, Flags);
630  }
631 
632  return true;
633 }
634 
635 bool IRTranslator::translateBitCast(const User &U,
636  MachineIRBuilder &MIRBuilder) {
637  // If we're bitcasting to the source type, we can reuse the source vreg.
638  if (getLLTForType(*U.getOperand(0)->getType(), *DL) ==
639  getLLTForType(*U.getType(), *DL)) {
640  unsigned SrcReg = getOrCreateVReg(*U.getOperand(0));
641  auto &Regs = *VMap.getVRegs(U);
642  // If we already assigned a vreg for this bitcast, we can't change that.
643  // Emit a copy to satisfy the users we already emitted.
644  if (!Regs.empty())
645  MIRBuilder.buildCopy(Regs[0], SrcReg);
646  else {
647  Regs.push_back(SrcReg);
648  VMap.getOffsets(U)->push_back(0);
649  }
650  return true;
651  }
652  return translateCast(TargetOpcode::G_BITCAST, U, MIRBuilder);
653 }
654 
655 bool IRTranslator::translateCast(unsigned Opcode, const User &U,
656  MachineIRBuilder &MIRBuilder) {
657  unsigned Op = getOrCreateVReg(*U.getOperand(0));
658  unsigned Res = getOrCreateVReg(U);
659  MIRBuilder.buildInstr(Opcode, {Res}, {Op});
660  return true;
661 }
662 
663 bool IRTranslator::translateGetElementPtr(const User &U,
664  MachineIRBuilder &MIRBuilder) {
665  // FIXME: support vector GEPs.
666  if (U.getType()->isVectorTy())
667  return false;
668 
669  Value &Op0 = *U.getOperand(0);
670  unsigned BaseReg = getOrCreateVReg(Op0);
671  Type *PtrIRTy = Op0.getType();
672  LLT PtrTy = getLLTForType(*PtrIRTy, *DL);
673  Type *OffsetIRTy = DL->getIntPtrType(PtrIRTy);
674  LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
675 
676  int64_t Offset = 0;
677  for (gep_type_iterator GTI = gep_type_begin(&U), E = gep_type_end(&U);
678  GTI != E; ++GTI) {
679  const Value *Idx = GTI.getOperand();
680  if (StructType *StTy = GTI.getStructTypeOrNull()) {
681  unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
682  Offset += DL->getStructLayout(StTy)->getElementOffset(Field);
683  continue;
684  } else {
685  uint64_t ElementSize = DL->getTypeAllocSize(GTI.getIndexedType());
686 
687  // If this is a scalar constant or a splat vector of constants,
688  // handle it quickly.
689  if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
690  Offset += ElementSize * CI->getSExtValue();
691  continue;
692  }
693 
694  if (Offset != 0) {
695  unsigned NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
696  LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
697  auto OffsetMIB = MIRBuilder.buildConstant({OffsetTy}, Offset);
698  MIRBuilder.buildGEP(NewBaseReg, BaseReg, OffsetMIB.getReg(0));
699 
700  BaseReg = NewBaseReg;
701  Offset = 0;
702  }
703 
704  unsigned IdxReg = getOrCreateVReg(*Idx);
705  if (MRI->getType(IdxReg) != OffsetTy) {
706  unsigned NewIdxReg = MRI->createGenericVirtualRegister(OffsetTy);
707  MIRBuilder.buildSExtOrTrunc(NewIdxReg, IdxReg);
708  IdxReg = NewIdxReg;
709  }
710 
711  // N = N + Idx * ElementSize;
712  // Avoid doing it for ElementSize of 1.
713  unsigned GepOffsetReg;
714  if (ElementSize != 1) {
715  GepOffsetReg = MRI->createGenericVirtualRegister(OffsetTy);
716  auto ElementSizeMIB = MIRBuilder.buildConstant(
717  getLLTForType(*OffsetIRTy, *DL), ElementSize);
718  MIRBuilder.buildMul(GepOffsetReg, ElementSizeMIB.getReg(0), IdxReg);
719  } else
720  GepOffsetReg = IdxReg;
721 
722  unsigned NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
723  MIRBuilder.buildGEP(NewBaseReg, BaseReg, GepOffsetReg);
724  BaseReg = NewBaseReg;
725  }
726  }
727 
728  if (Offset != 0) {
729  auto OffsetMIB =
730  MIRBuilder.buildConstant(getLLTForType(*OffsetIRTy, *DL), Offset);
731  MIRBuilder.buildGEP(getOrCreateVReg(U), BaseReg, OffsetMIB.getReg(0));
732  return true;
733  }
734 
735  MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg);
736  return true;
737 }
738 
739 bool IRTranslator::translateMemfunc(const CallInst &CI,
740  MachineIRBuilder &MIRBuilder,
741  unsigned ID) {
742 
743  // If the source is undef, then just emit a nop.
744  if (isa<UndefValue>(CI.getArgOperand(1))) {
745  switch (ID) {
746  case Intrinsic::memmove:
747  case Intrinsic::memcpy:
748  case Intrinsic::memset:
749  return true;
750  default:
751  break;
752  }
753  }
754 
755  LLT SizeTy = getLLTForType(*CI.getArgOperand(2)->getType(), *DL);
756  Type *DstTy = CI.getArgOperand(0)->getType();
757  if (cast<PointerType>(DstTy)->getAddressSpace() != 0 ||
758  SizeTy.getSizeInBits() != DL->getPointerSizeInBits(0))
759  return false;
760 
762  for (int i = 0; i < 3; ++i) {
763  const auto &Arg = CI.getArgOperand(i);
764  Args.emplace_back(getOrCreateVReg(*Arg), Arg->getType());
765  }
766 
767  const char *Callee;
768  switch (ID) {
769  case Intrinsic::memmove:
770  case Intrinsic::memcpy: {
771  Type *SrcTy = CI.getArgOperand(1)->getType();
772  if(cast<PointerType>(SrcTy)->getAddressSpace() != 0)
773  return false;
774  Callee = ID == Intrinsic::memcpy ? "memcpy" : "memmove";
775  break;
776  }
777  case Intrinsic::memset:
778  Callee = "memset";
779  break;
780  default:
781  return false;
782  }
783 
784  return CLI->lowerCall(MIRBuilder, CI.getCallingConv(),
785  MachineOperand::CreateES(Callee),
786  CallLowering::ArgInfo(0, CI.getType()), Args);
787 }
788 
789 void IRTranslator::getStackGuard(unsigned DstReg,
790  MachineIRBuilder &MIRBuilder) {
791  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
792  MRI->setRegClass(DstReg, TRI->getPointerRegClass(*MF));
793  auto MIB = MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD);
794  MIB.addDef(DstReg);
795 
796  auto &TLI = *MF->getSubtarget().getTargetLowering();
797  Value *Global = TLI.getSDagStackGuard(*MF->getFunction().getParent());
798  if (!Global)
799  return;
800 
801  MachinePointerInfo MPInfo(Global);
805  MF->getMachineMemOperand(MPInfo, Flags, DL->getPointerSizeInBits() / 8,
806  DL->getPointerABIAlignment(0));
807  MIB.setMemRefs({MemRef});
808 }
809 
810 bool IRTranslator::translateOverflowIntrinsic(const CallInst &CI, unsigned Op,
811  MachineIRBuilder &MIRBuilder) {
812  ArrayRef<unsigned> ResRegs = getOrCreateVRegs(CI);
813  MIRBuilder.buildInstr(Op)
814  .addDef(ResRegs[0])
815  .addDef(ResRegs[1])
816  .addUse(getOrCreateVReg(*CI.getOperand(0)))
817  .addUse(getOrCreateVReg(*CI.getOperand(1)));
818 
819  return true;
820 }
821 
822 unsigned IRTranslator::getSimpleIntrinsicOpcode(Intrinsic::ID ID) {
823  switch (ID) {
824  default:
825  break;
826  case Intrinsic::bswap:
827  return TargetOpcode::G_BSWAP;
828  case Intrinsic::ceil:
829  return TargetOpcode::G_FCEIL;
830  case Intrinsic::cos:
831  return TargetOpcode::G_FCOS;
832  case Intrinsic::ctpop:
833  return TargetOpcode::G_CTPOP;
834  case Intrinsic::exp:
835  return TargetOpcode::G_FEXP;
836  case Intrinsic::exp2:
837  return TargetOpcode::G_FEXP2;
838  case Intrinsic::fabs:
839  return TargetOpcode::G_FABS;
840  case Intrinsic::copysign:
841  return TargetOpcode::G_FCOPYSIGN;
842  case Intrinsic::canonicalize:
843  return TargetOpcode::G_FCANONICALIZE;
844  case Intrinsic::floor:
845  return TargetOpcode::G_FFLOOR;
846  case Intrinsic::fma:
847  return TargetOpcode::G_FMA;
848  case Intrinsic::log:
849  return TargetOpcode::G_FLOG;
850  case Intrinsic::log2:
851  return TargetOpcode::G_FLOG2;
852  case Intrinsic::log10:
853  return TargetOpcode::G_FLOG10;
854  case Intrinsic::nearbyint:
855  return TargetOpcode::G_FNEARBYINT;
856  case Intrinsic::pow:
857  return TargetOpcode::G_FPOW;
858  case Intrinsic::rint:
859  return TargetOpcode::G_FRINT;
860  case Intrinsic::round:
861  return TargetOpcode::G_INTRINSIC_ROUND;
862  case Intrinsic::sin:
863  return TargetOpcode::G_FSIN;
864  case Intrinsic::sqrt:
865  return TargetOpcode::G_FSQRT;
866  case Intrinsic::trunc:
867  return TargetOpcode::G_INTRINSIC_TRUNC;
868  }
870 }
871 
872 bool IRTranslator::translateSimpleIntrinsic(const CallInst &CI,
873  Intrinsic::ID ID,
874  MachineIRBuilder &MIRBuilder) {
875 
876  unsigned Op = getSimpleIntrinsicOpcode(ID);
877 
878  // Is this a simple intrinsic?
879  if (Op == Intrinsic::not_intrinsic)
880  return false;
881 
882  // Yes. Let's translate it.
884  for (auto &Arg : CI.arg_operands())
885  VRegs.push_back(getOrCreateVReg(*Arg));
886 
887  MIRBuilder.buildInstr(Op, {getOrCreateVReg(CI)}, VRegs,
889  return true;
890 }
891 
892 bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
893  MachineIRBuilder &MIRBuilder) {
894 
895  // If this is a simple intrinsic (that is, we just need to add a def of
896  // a vreg, and uses for each arg operand, then translate it.
897  if (translateSimpleIntrinsic(CI, ID, MIRBuilder))
898  return true;
899 
900  switch (ID) {
901  default:
902  break;
903  case Intrinsic::lifetime_start:
904  case Intrinsic::lifetime_end: {
905  // No stack colouring in O0, discard region information.
906  if (MF->getTarget().getOptLevel() == CodeGenOpt::None)
907  return true;
908 
909  unsigned Op = ID == Intrinsic::lifetime_start ? TargetOpcode::LIFETIME_START
911 
912  // Get the underlying objects for the location passed on the lifetime
913  // marker.
915  GetUnderlyingObjects(CI.getArgOperand(1), Allocas, *DL);
916 
917  // Iterate over each underlying object, creating lifetime markers for each
918  // static alloca. Quit if we find a non-static alloca.
919  for (const Value *V : Allocas) {
920  const AllocaInst *AI = dyn_cast<AllocaInst>(V);
921  if (!AI)
922  continue;
923 
924  if (!AI->isStaticAlloca())
925  return true;
926 
927  MIRBuilder.buildInstr(Op).addFrameIndex(getOrCreateFrameIndex(*AI));
928  }
929  return true;
930  }
931  case Intrinsic::dbg_declare: {
932  const DbgDeclareInst &DI = cast<DbgDeclareInst>(CI);
933  assert(DI.getVariable() && "Missing variable");
934 
935  const Value *Address = DI.getAddress();
936  if (!Address || isa<UndefValue>(Address)) {
937  LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
938  return true;
939  }
940 
942  MIRBuilder.getDebugLoc()) &&
943  "Expected inlined-at fields to agree");
944  auto AI = dyn_cast<AllocaInst>(Address);
945  if (AI && AI->isStaticAlloca()) {
946  // Static allocas are tracked at the MF level, no need for DBG_VALUE
947  // instructions (in fact, they get ignored if they *do* exist).
948  MF->setVariableDbgInfo(DI.getVariable(), DI.getExpression(),
949  getOrCreateFrameIndex(*AI), DI.getDebugLoc());
950  } else {
951  // A dbg.declare describes the address of a source variable, so lower it
952  // into an indirect DBG_VALUE.
953  MIRBuilder.buildIndirectDbgValue(getOrCreateVReg(*Address),
954  DI.getVariable(), DI.getExpression());
955  }
956  return true;
957  }
958  case Intrinsic::dbg_label: {
959  const DbgLabelInst &DI = cast<DbgLabelInst>(CI);
960  assert(DI.getLabel() && "Missing label");
961 
963  MIRBuilder.getDebugLoc()) &&
964  "Expected inlined-at fields to agree");
965 
966  MIRBuilder.buildDbgLabel(DI.getLabel());
967  return true;
968  }
969  case Intrinsic::vaend:
970  // No target I know of cares about va_end. Certainly no in-tree target
971  // does. Simplest intrinsic ever!
972  return true;
973  case Intrinsic::vastart: {
974  auto &TLI = *MF->getSubtarget().getTargetLowering();
975  Value *Ptr = CI.getArgOperand(0);
976  unsigned ListSize = TLI.getVaListSizeInBits(*DL) / 8;
977 
978  // FIXME: Get alignment
979  MIRBuilder.buildInstr(TargetOpcode::G_VASTART)
980  .addUse(getOrCreateVReg(*Ptr))
981  .addMemOperand(MF->getMachineMemOperand(
982  MachinePointerInfo(Ptr), MachineMemOperand::MOStore, ListSize, 1));
983  return true;
984  }
985  case Intrinsic::dbg_value: {
986  // This form of DBG_VALUE is target-independent.
987  const DbgValueInst &DI = cast<DbgValueInst>(CI);
988  const Value *V = DI.getValue();
990  MIRBuilder.getDebugLoc()) &&
991  "Expected inlined-at fields to agree");
992  if (!V) {
993  // Currently the optimizer can produce this; insert an undef to
994  // help debugging. Probably the optimizer should not do this.
995  MIRBuilder.buildIndirectDbgValue(0, DI.getVariable(), DI.getExpression());
996  } else if (const auto *CI = dyn_cast<Constant>(V)) {
997  MIRBuilder.buildConstDbgValue(*CI, DI.getVariable(), DI.getExpression());
998  } else {
999  unsigned Reg = getOrCreateVReg(*V);
1000  // FIXME: This does not handle register-indirect values at offset 0. The
1001  // direct/indirect thing shouldn't really be handled by something as
1002  // implicit as reg+noreg vs reg+imm in the first palce, but it seems
1003  // pretty baked in right now.
1004  MIRBuilder.buildDirectDbgValue(Reg, DI.getVariable(), DI.getExpression());
1005  }
1006  return true;
1007  }
1008  case Intrinsic::uadd_with_overflow:
1009  return translateOverflowIntrinsic(CI, TargetOpcode::G_UADDO, MIRBuilder);
1010  case Intrinsic::sadd_with_overflow:
1011  return translateOverflowIntrinsic(CI, TargetOpcode::G_SADDO, MIRBuilder);
1012  case Intrinsic::usub_with_overflow:
1013  return translateOverflowIntrinsic(CI, TargetOpcode::G_USUBO, MIRBuilder);
1014  case Intrinsic::ssub_with_overflow:
1015  return translateOverflowIntrinsic(CI, TargetOpcode::G_SSUBO, MIRBuilder);
1016  case Intrinsic::umul_with_overflow:
1017  return translateOverflowIntrinsic(CI, TargetOpcode::G_UMULO, MIRBuilder);
1018  case Intrinsic::smul_with_overflow:
1019  return translateOverflowIntrinsic(CI, TargetOpcode::G_SMULO, MIRBuilder);
1020  case Intrinsic::fmuladd: {
1021  const TargetMachine &TM = MF->getTarget();
1022  const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
1023  unsigned Dst = getOrCreateVReg(CI);
1024  unsigned Op0 = getOrCreateVReg(*CI.getArgOperand(0));
1025  unsigned Op1 = getOrCreateVReg(*CI.getArgOperand(1));
1026  unsigned Op2 = getOrCreateVReg(*CI.getArgOperand(2));
1028  TLI.isFMAFasterThanFMulAndFAdd(TLI.getValueType(*DL, CI.getType()))) {
1029  // TODO: Revisit this to see if we should move this part of the
1030  // lowering to the combiner.
1031  MIRBuilder.buildInstr(TargetOpcode::G_FMA, {Dst}, {Op0, Op1, Op2},
1033  } else {
1034  LLT Ty = getLLTForType(*CI.getType(), *DL);
1035  auto FMul = MIRBuilder.buildInstr(TargetOpcode::G_FMUL, {Ty}, {Op0, Op1},
1037  MIRBuilder.buildInstr(TargetOpcode::G_FADD, {Dst}, {FMul, Op2},
1039  }
1040  return true;
1041  }
1042  case Intrinsic::memcpy:
1043  case Intrinsic::memmove:
1044  case Intrinsic::memset:
1045  return translateMemfunc(CI, MIRBuilder, ID);
1046  case Intrinsic::eh_typeid_for: {
1048  unsigned Reg = getOrCreateVReg(CI);
1049  unsigned TypeID = MF->getTypeIDFor(GV);
1050  MIRBuilder.buildConstant(Reg, TypeID);
1051  return true;
1052  }
1053  case Intrinsic::objectsize: {
1054  // If we don't know by now, we're never going to know.
1055  const ConstantInt *Min = cast<ConstantInt>(CI.getArgOperand(1));
1056 
1057  MIRBuilder.buildConstant(getOrCreateVReg(CI), Min->isZero() ? -1ULL : 0);
1058  return true;
1059  }
1060  case Intrinsic::is_constant:
1061  // If this wasn't constant-folded away by now, then it's not a
1062  // constant.
1063  MIRBuilder.buildConstant(getOrCreateVReg(CI), 0);
1064  return true;
1065  case Intrinsic::stackguard:
1066  getStackGuard(getOrCreateVReg(CI), MIRBuilder);
1067  return true;
1068  case Intrinsic::stackprotector: {
1069  LLT PtrTy = getLLTForType(*CI.getArgOperand(0)->getType(), *DL);
1070  unsigned GuardVal = MRI->createGenericVirtualRegister(PtrTy);
1071  getStackGuard(GuardVal, MIRBuilder);
1072 
1073  AllocaInst *Slot = cast<AllocaInst>(CI.getArgOperand(1));
1074  int FI = getOrCreateFrameIndex(*Slot);
1075  MF->getFrameInfo().setStackProtectorIndex(FI);
1076 
1077  MIRBuilder.buildStore(
1078  GuardVal, getOrCreateVReg(*Slot),
1079  *MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(*MF, FI),
1082  PtrTy.getSizeInBits() / 8, 8));
1083  return true;
1084  }
1085  case Intrinsic::stacksave: {
1086  // Save the stack pointer to the location provided by the intrinsic.
1087  unsigned Reg = getOrCreateVReg(CI);
1088  unsigned StackPtr = MF->getSubtarget()
1089  .getTargetLowering()
1090  ->getStackPointerRegisterToSaveRestore();
1091 
1092  // If the target doesn't specify a stack pointer, then fall back.
1093  if (!StackPtr)
1094  return false;
1095 
1096  MIRBuilder.buildCopy(Reg, StackPtr);
1097  return true;
1098  }
1099  case Intrinsic::stackrestore: {
1100  // Restore the stack pointer from the location provided by the intrinsic.
1101  unsigned Reg = getOrCreateVReg(*CI.getArgOperand(0));
1102  unsigned StackPtr = MF->getSubtarget()
1103  .getTargetLowering()
1104  ->getStackPointerRegisterToSaveRestore();
1105 
1106  // If the target doesn't specify a stack pointer, then fall back.
1107  if (!StackPtr)
1108  return false;
1109 
1110  MIRBuilder.buildCopy(StackPtr, Reg);
1111  return true;
1112  }
1113  case Intrinsic::cttz:
1114  case Intrinsic::ctlz: {
1115  ConstantInt *Cst = cast<ConstantInt>(CI.getArgOperand(1));
1116  bool isTrailing = ID == Intrinsic::cttz;
1117  unsigned Opcode = isTrailing
1118  ? Cst->isZero() ? TargetOpcode::G_CTTZ
1119  : TargetOpcode::G_CTTZ_ZERO_UNDEF
1120  : Cst->isZero() ? TargetOpcode::G_CTLZ
1121  : TargetOpcode::G_CTLZ_ZERO_UNDEF;
1122  MIRBuilder.buildInstr(Opcode)
1123  .addDef(getOrCreateVReg(CI))
1124  .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
1125  return true;
1126  }
1127  case Intrinsic::invariant_start: {
1128  LLT PtrTy = getLLTForType(*CI.getArgOperand(0)->getType(), *DL);
1129  unsigned Undef = MRI->createGenericVirtualRegister(PtrTy);
1130  MIRBuilder.buildUndef(Undef);
1131  return true;
1132  }
1133  case Intrinsic::invariant_end:
1134  return true;
1135  case Intrinsic::assume:
1136  case Intrinsic::var_annotation:
1137  case Intrinsic::sideeffect:
1138  // Discard annotate attributes, assumptions, and artificial side-effects.
1139  return true;
1140  }
1141  return false;
1142 }
1143 
1144 bool IRTranslator::translateInlineAsm(const CallInst &CI,
1145  MachineIRBuilder &MIRBuilder) {
1146  const InlineAsm &IA = cast<InlineAsm>(*CI.getCalledValue());
1147  if (!IA.getConstraintString().empty())
1148  return false;
1149 
1150  unsigned ExtraInfo = 0;
1151  if (IA.hasSideEffects())
1152  ExtraInfo |= InlineAsm::Extra_HasSideEffects;
1153  if (IA.getDialect() == InlineAsm::AD_Intel)
1154  ExtraInfo |= InlineAsm::Extra_AsmDialect;
1155 
1157  .addExternalSymbol(IA.getAsmString().c_str())
1158  .addImm(ExtraInfo);
1159 
1160  return true;
1161 }
1162 
1163 unsigned IRTranslator::packRegs(const Value &V,
1164  MachineIRBuilder &MIRBuilder) {
1165  ArrayRef<unsigned> Regs = getOrCreateVRegs(V);
1166  ArrayRef<uint64_t> Offsets = *VMap.getOffsets(V);
1167  LLT BigTy = getLLTForType(*V.getType(), *DL);
1168 
1169  if (Regs.size() == 1)
1170  return Regs[0];
1171 
1172  unsigned Dst = MRI->createGenericVirtualRegister(BigTy);
1173  MIRBuilder.buildUndef(Dst);
1174  for (unsigned i = 0; i < Regs.size(); ++i) {
1175  unsigned NewDst = MRI->createGenericVirtualRegister(BigTy);
1176  MIRBuilder.buildInsert(NewDst, Dst, Regs[i], Offsets[i]);
1177  Dst = NewDst;
1178  }
1179  return Dst;
1180 }
1181 
1182 void IRTranslator::unpackRegs(const Value &V, unsigned Src,
1183  MachineIRBuilder &MIRBuilder) {
1184  ArrayRef<unsigned> Regs = getOrCreateVRegs(V);
1185  ArrayRef<uint64_t> Offsets = *VMap.getOffsets(V);
1186 
1187  for (unsigned i = 0; i < Regs.size(); ++i)
1188  MIRBuilder.buildExtract(Regs[i], Src, Offsets[i]);
1189 }
1190 
1191 bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
1192  const CallInst &CI = cast<CallInst>(U);
1193  auto TII = MF->getTarget().getIntrinsicInfo();
1194  const Function *F = CI.getCalledFunction();
1195 
1196  // FIXME: support Windows dllimport function calls.
1197  if (F && F->hasDLLImportStorageClass())
1198  return false;
1199 
1200  if (CI.isInlineAsm())
1201  return translateInlineAsm(CI, MIRBuilder);
1202 
1204  if (F && F->isIntrinsic()) {
1205  ID = F->getIntrinsicID();
1206  if (TII && ID == Intrinsic::not_intrinsic)
1207  ID = static_cast<Intrinsic::ID>(TII->getIntrinsicID(F));
1208  }
1209 
1210  if (!F || !F->isIntrinsic() || ID == Intrinsic::not_intrinsic) {
1211  bool IsSplitType = valueIsSplit(CI);
1212  unsigned Res = IsSplitType ? MRI->createGenericVirtualRegister(
1213  getLLTForType(*CI.getType(), *DL))
1214  : getOrCreateVReg(CI);
1215 
1217  unsigned SwiftErrorVReg = 0;
1218  for (auto &Arg: CI.arg_operands()) {
1219  if (CLI->supportSwiftError() && isSwiftError(Arg)) {
1220  LLT Ty = getLLTForType(*Arg->getType(), *DL);
1221  unsigned InVReg = MRI->createGenericVirtualRegister(Ty);
1222  MIRBuilder.buildCopy(InVReg, SwiftError.getOrCreateVRegUseAt(
1223  &CI, &MIRBuilder.getMBB(), Arg));
1224  Args.push_back(InVReg);
1225  SwiftErrorVReg =
1226  SwiftError.getOrCreateVRegDefAt(&CI, &MIRBuilder.getMBB(), Arg);
1227  continue;
1228  }
1229  Args.push_back(packRegs(*Arg, MIRBuilder));
1230  }
1231 
1232  MF->getFrameInfo().setHasCalls(true);
1233  bool Success =
1234  CLI->lowerCall(MIRBuilder, &CI, Res, Args, SwiftErrorVReg,
1235  [&]() { return getOrCreateVReg(*CI.getCalledValue()); });
1236 
1237  if (IsSplitType)
1238  unpackRegs(CI, Res, MIRBuilder);
1239 
1240  return Success;
1241  }
1242 
1243  assert(ID != Intrinsic::not_intrinsic && "unknown intrinsic");
1244 
1245  if (translateKnownIntrinsic(CI, ID, MIRBuilder))
1246  return true;
1247 
1248  ArrayRef<unsigned> ResultRegs;
1249  if (!CI.getType()->isVoidTy())
1250  ResultRegs = getOrCreateVRegs(CI);
1251 
1252  // Ignore the callsite attributes. Backend code is most likely not expecting
1253  // an intrinsic to sometimes have side effects and sometimes not.
1254  MachineInstrBuilder MIB =
1255  MIRBuilder.buildIntrinsic(ID, ResultRegs, !F->doesNotAccessMemory());
1256  if (isa<FPMathOperator>(CI))
1257  MIB->copyIRFlags(CI);
1258 
1259  for (auto &Arg : CI.arg_operands()) {
1260  // Some intrinsics take metadata parameters. Reject them.
1261  if (isa<MetadataAsValue>(Arg))
1262  return false;
1263  MIB.addUse(packRegs(*Arg, MIRBuilder));
1264  }
1265 
1266  // Add a MachineMemOperand if it is a target mem intrinsic.
1267  const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
1268  TargetLowering::IntrinsicInfo Info;
1269  // TODO: Add a GlobalISel version of getTgtMemIntrinsic.
1270  if (TLI.getTgtMemIntrinsic(Info, CI, *MF, ID)) {
1271  unsigned Align = Info.align;
1272  if (Align == 0)
1273  Align = DL->getABITypeAlignment(Info.memVT.getTypeForEVT(F->getContext()));
1274 
1275  uint64_t Size = Info.memVT.getStoreSize();
1276  MIB.addMemOperand(MF->getMachineMemOperand(MachinePointerInfo(Info.ptrVal),
1277  Info.flags, Size, Align));
1278  }
1279 
1280  return true;
1281 }
1282 
1283 bool IRTranslator::translateInvoke(const User &U,
1284  MachineIRBuilder &MIRBuilder) {
1285  const InvokeInst &I = cast<InvokeInst>(U);
1286  MCContext &Context = MF->getContext();
1287 
1288  const BasicBlock *ReturnBB = I.getSuccessor(0);
1289  const BasicBlock *EHPadBB = I.getSuccessor(1);
1290 
1291  const Value *Callee = I.getCalledValue();
1292  const Function *Fn = dyn_cast<Function>(Callee);
1293  if (isa<InlineAsm>(Callee))
1294  return false;
1295 
1296  // FIXME: support invoking patchpoint and statepoint intrinsics.
1297  if (Fn && Fn->isIntrinsic())
1298  return false;
1299 
1300  // FIXME: support whatever these are.
1302  return false;
1303 
1304  // FIXME: support Windows exception handling.
1305  if (!isa<LandingPadInst>(EHPadBB->front()))
1306  return false;
1307 
1308  // Emit the actual call, bracketed by EH_LABELs so that the MF knows about
1309  // the region covered by the try.
1310  MCSymbol *BeginSymbol = Context.createTempSymbol();
1311  MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(BeginSymbol);
1312 
1313  unsigned Res = 0;
1314  if (!I.getType()->isVoidTy())
1315  Res = MRI->createGenericVirtualRegister(getLLTForType(*I.getType(), *DL));
1317  unsigned SwiftErrorVReg = 0;
1318  for (auto &Arg : I.arg_operands()) {
1319  if (CLI->supportSwiftError() && isSwiftError(Arg)) {
1320  LLT Ty = getLLTForType(*Arg->getType(), *DL);
1321  unsigned InVReg = MRI->createGenericVirtualRegister(Ty);
1322  MIRBuilder.buildCopy(InVReg, SwiftError.getOrCreateVRegUseAt(
1323  &I, &MIRBuilder.getMBB(), Arg));
1324  Args.push_back(InVReg);
1325  SwiftErrorVReg =
1326  SwiftError.getOrCreateVRegDefAt(&I, &MIRBuilder.getMBB(), Arg);
1327  continue;
1328  }
1329 
1330  Args.push_back(packRegs(*Arg, MIRBuilder));
1331  }
1332 
1333  if (!CLI->lowerCall(MIRBuilder, &I, Res, Args, SwiftErrorVReg,
1334  [&]() { return getOrCreateVReg(*I.getCalledValue()); }))
1335  return false;
1336 
1337  unpackRegs(I, Res, MIRBuilder);
1338 
1339  MCSymbol *EndSymbol = Context.createTempSymbol();
1340  MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(EndSymbol);
1341 
1342  // FIXME: track probabilities.
1343  MachineBasicBlock &EHPadMBB = getMBB(*EHPadBB),
1344  &ReturnMBB = getMBB(*ReturnBB);
1345  MF->addInvoke(&EHPadMBB, BeginSymbol, EndSymbol);
1346  MIRBuilder.getMBB().addSuccessor(&ReturnMBB);
1347  MIRBuilder.getMBB().addSuccessor(&EHPadMBB);
1348  MIRBuilder.buildBr(ReturnMBB);
1349 
1350  return true;
1351 }
1352 
1353 bool IRTranslator::translateCallBr(const User &U,
1354  MachineIRBuilder &MIRBuilder) {
1355  // FIXME: Implement this.
1356  return false;
1357 }
1358 
1359 bool IRTranslator::translateLandingPad(const User &U,
1360  MachineIRBuilder &MIRBuilder) {
1361  const LandingPadInst &LP = cast<LandingPadInst>(U);
1362 
1363  MachineBasicBlock &MBB = MIRBuilder.getMBB();
1364 
1365  MBB.setIsEHPad();
1366 
1367  // If there aren't registers to copy the values into (e.g., during SjLj
1368  // exceptions), then don't bother.
1369  auto &TLI = *MF->getSubtarget().getTargetLowering();
1370  const Constant *PersonalityFn = MF->getFunction().getPersonalityFn();
1371  if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 &&
1372  TLI.getExceptionSelectorRegister(PersonalityFn) == 0)
1373  return true;
1374 
1375  // If landingpad's return type is token type, we don't create DAG nodes
1376  // for its exception pointer and selector value. The extraction of exception
1377  // pointer or selector value from token type landingpads is not currently
1378  // supported.
1379  if (LP.getType()->isTokenTy())
1380  return true;
1381 
1382  // Add a label to mark the beginning of the landing pad. Deletion of the
1383  // landing pad can thus be detected via the MachineModuleInfo.
1385  .addSym(MF->addLandingPad(&MBB));
1386 
1387  LLT Ty = getLLTForType(*LP.getType(), *DL);
1388  unsigned Undef = MRI->createGenericVirtualRegister(Ty);
1389  MIRBuilder.buildUndef(Undef);
1390 
1391  SmallVector<LLT, 2> Tys;
1392  for (Type *Ty : cast<StructType>(LP.getType())->elements())
1393  Tys.push_back(getLLTForType(*Ty, *DL));
1394  assert(Tys.size() == 2 && "Only two-valued landingpads are supported");
1395 
1396  // Mark exception register as live in.
1397  unsigned ExceptionReg = TLI.getExceptionPointerRegister(PersonalityFn);
1398  if (!ExceptionReg)
1399  return false;
1400 
1401  MBB.addLiveIn(ExceptionReg);
1402  ArrayRef<unsigned> ResRegs = getOrCreateVRegs(LP);
1403  MIRBuilder.buildCopy(ResRegs[0], ExceptionReg);
1404 
1405  unsigned SelectorReg = TLI.getExceptionSelectorRegister(PersonalityFn);
1406  if (!SelectorReg)
1407  return false;
1408 
1409  MBB.addLiveIn(SelectorReg);
1410  unsigned PtrVReg = MRI->createGenericVirtualRegister(Tys[0]);
1411  MIRBuilder.buildCopy(PtrVReg, SelectorReg);
1412  MIRBuilder.buildCast(ResRegs[1], PtrVReg);
1413 
1414  return true;
1415 }
1416 
1417 bool IRTranslator::translateAlloca(const User &U,
1418  MachineIRBuilder &MIRBuilder) {
1419  auto &AI = cast<AllocaInst>(U);
1420 
1421  if (AI.isSwiftError())
1422  return true;
1423 
1424  if (AI.isStaticAlloca()) {
1425  unsigned Res = getOrCreateVReg(AI);
1426  int FI = getOrCreateFrameIndex(AI);
1427  MIRBuilder.buildFrameIndex(Res, FI);
1428  return true;
1429  }
1430 
1431  // FIXME: support stack probing for Windows.
1432  if (MF->getTarget().getTargetTriple().isOSWindows())
1433  return false;
1434 
1435  // Now we're in the harder dynamic case.
1436  Type *Ty = AI.getAllocatedType();
1437  unsigned Align =
1438  std::max((unsigned)DL->getPrefTypeAlignment(Ty), AI.getAlignment());
1439 
1440  unsigned NumElts = getOrCreateVReg(*AI.getArraySize());
1441 
1442  Type *IntPtrIRTy = DL->getIntPtrType(AI.getType());
1443  LLT IntPtrTy = getLLTForType(*IntPtrIRTy, *DL);
1444  if (MRI->getType(NumElts) != IntPtrTy) {
1445  unsigned ExtElts = MRI->createGenericVirtualRegister(IntPtrTy);
1446  MIRBuilder.buildZExtOrTrunc(ExtElts, NumElts);
1447  NumElts = ExtElts;
1448  }
1449 
1450  unsigned AllocSize = MRI->createGenericVirtualRegister(IntPtrTy);
1451  unsigned TySize =
1452  getOrCreateVReg(*ConstantInt::get(IntPtrIRTy, -DL->getTypeAllocSize(Ty)));
1453  MIRBuilder.buildMul(AllocSize, NumElts, TySize);
1454 
1455  LLT PtrTy = getLLTForType(*AI.getType(), *DL);
1456  auto &TLI = *MF->getSubtarget().getTargetLowering();
1457  unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1458 
1459  unsigned SPTmp = MRI->createGenericVirtualRegister(PtrTy);
1460  MIRBuilder.buildCopy(SPTmp, SPReg);
1461 
1462  unsigned AllocTmp = MRI->createGenericVirtualRegister(PtrTy);
1463  MIRBuilder.buildGEP(AllocTmp, SPTmp, AllocSize);
1464 
1465  // Handle alignment. We have to realign if the allocation granule was smaller
1466  // than stack alignment, or the specific alloca requires more than stack
1467  // alignment.
1468  unsigned StackAlign =
1469  MF->getSubtarget().getFrameLowering()->getStackAlignment();
1470  Align = std::max(Align, StackAlign);
1471  if (Align > StackAlign || DL->getTypeAllocSize(Ty) % StackAlign != 0) {
1472  // Round the size of the allocation up to the stack alignment size
1473  // by add SA-1 to the size. This doesn't overflow because we're computing
1474  // an address inside an alloca.
1475  unsigned AlignedAlloc = MRI->createGenericVirtualRegister(PtrTy);
1476  MIRBuilder.buildPtrMask(AlignedAlloc, AllocTmp, Log2_32(Align));
1477  AllocTmp = AlignedAlloc;
1478  }
1479 
1480  MIRBuilder.buildCopy(SPReg, AllocTmp);
1481  MIRBuilder.buildCopy(getOrCreateVReg(AI), AllocTmp);
1482 
1483  MF->getFrameInfo().CreateVariableSizedObject(Align ? Align : 1, &AI);
1484  assert(MF->getFrameInfo().hasVarSizedObjects());
1485  return true;
1486 }
1487 
1488 bool IRTranslator::translateVAArg(const User &U, MachineIRBuilder &MIRBuilder) {
1489  // FIXME: We may need more info about the type. Because of how LLT works,
1490  // we're completely discarding the i64/double distinction here (amongst
1491  // others). Fortunately the ABIs I know of where that matters don't use va_arg
1492  // anyway but that's not guaranteed.
1493  MIRBuilder.buildInstr(TargetOpcode::G_VAARG)
1494  .addDef(getOrCreateVReg(U))
1495  .addUse(getOrCreateVReg(*U.getOperand(0)))
1496  .addImm(DL->getABITypeAlignment(U.getType()));
1497  return true;
1498 }
1499 
1500 bool IRTranslator::translateInsertElement(const User &U,
1501  MachineIRBuilder &MIRBuilder) {
1502  // If it is a <1 x Ty> vector, use the scalar as it is
1503  // not a legal vector type in LLT.
1504  if (U.getType()->getVectorNumElements() == 1) {
1505  unsigned Elt = getOrCreateVReg(*U.getOperand(1));
1506  auto &Regs = *VMap.getVRegs(U);
1507  if (Regs.empty()) {
1508  Regs.push_back(Elt);
1509  VMap.getOffsets(U)->push_back(0);
1510  } else {
1511  MIRBuilder.buildCopy(Regs[0], Elt);
1512  }
1513  return true;
1514  }
1515 
1516  unsigned Res = getOrCreateVReg(U);
1517  unsigned Val = getOrCreateVReg(*U.getOperand(0));
1518  unsigned Elt = getOrCreateVReg(*U.getOperand(1));
1519  unsigned Idx = getOrCreateVReg(*U.getOperand(2));
1520  MIRBuilder.buildInsertVectorElement(Res, Val, Elt, Idx);
1521  return true;
1522 }
1523 
1524 bool IRTranslator::translateExtractElement(const User &U,
1525  MachineIRBuilder &MIRBuilder) {
1526  // If it is a <1 x Ty> vector, use the scalar as it is
1527  // not a legal vector type in LLT.
1528  if (U.getOperand(0)->getType()->getVectorNumElements() == 1) {
1529  unsigned Elt = getOrCreateVReg(*U.getOperand(0));
1530  auto &Regs = *VMap.getVRegs(U);
1531  if (Regs.empty()) {
1532  Regs.push_back(Elt);
1533  VMap.getOffsets(U)->push_back(0);
1534  } else {
1535  MIRBuilder.buildCopy(Regs[0], Elt);
1536  }
1537  return true;
1538  }
1539  unsigned Res = getOrCreateVReg(U);
1540  unsigned Val = getOrCreateVReg(*U.getOperand(0));
1541  const auto &TLI = *MF->getSubtarget().getTargetLowering();
1542  unsigned PreferredVecIdxWidth = TLI.getVectorIdxTy(*DL).getSizeInBits();
1543  unsigned Idx = 0;
1544  if (auto *CI = dyn_cast<ConstantInt>(U.getOperand(1))) {
1545  if (CI->getBitWidth() != PreferredVecIdxWidth) {
1546  APInt NewIdx = CI->getValue().sextOrTrunc(PreferredVecIdxWidth);
1547  auto *NewIdxCI = ConstantInt::get(CI->getContext(), NewIdx);
1548  Idx = getOrCreateVReg(*NewIdxCI);
1549  }
1550  }
1551  if (!Idx)
1552  Idx = getOrCreateVReg(*U.getOperand(1));
1553  if (MRI->getType(Idx).getSizeInBits() != PreferredVecIdxWidth) {
1554  const LLT &VecIdxTy = LLT::scalar(PreferredVecIdxWidth);
1555  Idx = MIRBuilder.buildSExtOrTrunc(VecIdxTy, Idx)->getOperand(0).getReg();
1556  }
1557  MIRBuilder.buildExtractVectorElement(Res, Val, Idx);
1558  return true;
1559 }
1560 
1561 bool IRTranslator::translateShuffleVector(const User &U,
1562  MachineIRBuilder &MIRBuilder) {
1563  MIRBuilder.buildInstr(TargetOpcode::G_SHUFFLE_VECTOR)
1564  .addDef(getOrCreateVReg(U))
1565  .addUse(getOrCreateVReg(*U.getOperand(0)))
1566  .addUse(getOrCreateVReg(*U.getOperand(1)))
1567  .addUse(getOrCreateVReg(*U.getOperand(2)));
1568  return true;
1569 }
1570 
1571 bool IRTranslator::translatePHI(const User &U, MachineIRBuilder &MIRBuilder) {
1572  const PHINode &PI = cast<PHINode>(U);
1573 
1575  for (auto Reg : getOrCreateVRegs(PI)) {
1576  auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI, {Reg}, {});
1577  Insts.push_back(MIB.getInstr());
1578  }
1579 
1580  PendingPHIs.emplace_back(&PI, std::move(Insts));
1581  return true;
1582 }
1583 
1584 bool IRTranslator::translateAtomicCmpXchg(const User &U,
1585  MachineIRBuilder &MIRBuilder) {
1586  const AtomicCmpXchgInst &I = cast<AtomicCmpXchgInst>(U);
1587 
1588  if (I.isWeak())
1589  return false;
1590 
1591  auto Flags = I.isVolatile() ? MachineMemOperand::MOVolatile
1594 
1595  Type *ResType = I.getType();
1596  Type *ValType = ResType->Type::getStructElementType(0);
1597 
1598  auto Res = getOrCreateVRegs(I);
1599  unsigned OldValRes = Res[0];
1600  unsigned SuccessRes = Res[1];
1601  unsigned Addr = getOrCreateVReg(*I.getPointerOperand());
1602  unsigned Cmp = getOrCreateVReg(*I.getCompareOperand());
1603  unsigned NewVal = getOrCreateVReg(*I.getNewValOperand());
1604 
1605  MIRBuilder.buildAtomicCmpXchgWithSuccess(
1606  OldValRes, SuccessRes, Addr, Cmp, NewVal,
1607  *MF->getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
1608  Flags, DL->getTypeStoreSize(ValType),
1609  getMemOpAlignment(I), AAMDNodes(), nullptr,
1611  I.getFailureOrdering()));
1612  return true;
1613 }
1614 
1615 bool IRTranslator::translateAtomicRMW(const User &U,
1616  MachineIRBuilder &MIRBuilder) {
1617  const AtomicRMWInst &I = cast<AtomicRMWInst>(U);
1618 
1619  auto Flags = I.isVolatile() ? MachineMemOperand::MOVolatile
1622 
1623  Type *ResType = I.getType();
1624 
1625  unsigned Res = getOrCreateVReg(I);
1626  unsigned Addr = getOrCreateVReg(*I.getPointerOperand());
1627  unsigned Val = getOrCreateVReg(*I.getValOperand());
1628 
1629  unsigned Opcode = 0;
1630  switch (I.getOperation()) {
1631  default:
1632  llvm_unreachable("Unknown atomicrmw op");
1633  return false;
1634  case AtomicRMWInst::Xchg:
1635  Opcode = TargetOpcode::G_ATOMICRMW_XCHG;
1636  break;
1637  case AtomicRMWInst::Add:
1638  Opcode = TargetOpcode::G_ATOMICRMW_ADD;
1639  break;
1640  case AtomicRMWInst::Sub:
1641  Opcode = TargetOpcode::G_ATOMICRMW_SUB;
1642  break;
1643  case AtomicRMWInst::And:
1644  Opcode = TargetOpcode::G_ATOMICRMW_AND;
1645  break;
1646  case AtomicRMWInst::Nand:
1647  Opcode = TargetOpcode::G_ATOMICRMW_NAND;
1648  break;
1649  case AtomicRMWInst::Or:
1650  Opcode = TargetOpcode::G_ATOMICRMW_OR;
1651  break;
1652  case AtomicRMWInst::Xor:
1653  Opcode = TargetOpcode::G_ATOMICRMW_XOR;
1654  break;
1655  case AtomicRMWInst::Max:
1656  Opcode = TargetOpcode::G_ATOMICRMW_MAX;
1657  break;
1658  case AtomicRMWInst::Min:
1659  Opcode = TargetOpcode::G_ATOMICRMW_MIN;
1660  break;
1661  case AtomicRMWInst::UMax:
1662  Opcode = TargetOpcode::G_ATOMICRMW_UMAX;
1663  break;
1664  case AtomicRMWInst::UMin:
1665  Opcode = TargetOpcode::G_ATOMICRMW_UMIN;
1666  break;
1667  }
1668 
1669  MIRBuilder.buildAtomicRMW(
1670  Opcode, Res, Addr, Val,
1671  *MF->getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
1672  Flags, DL->getTypeStoreSize(ResType),
1673  getMemOpAlignment(I), AAMDNodes(), nullptr,
1674  I.getSyncScopeID(), I.getOrdering()));
1675  return true;
1676 }
1677 
1678 void IRTranslator::finishPendingPhis() {
1679 #ifndef NDEBUG
1680  DILocationVerifier Verifier;
1681  GISelObserverWrapper WrapperObserver(&Verifier);
1682  RAIIDelegateInstaller DelInstall(*MF, &WrapperObserver);
1683 #endif // ifndef NDEBUG
1684  for (auto &Phi : PendingPHIs) {
1685  const PHINode *PI = Phi.first;
1686  ArrayRef<MachineInstr *> ComponentPHIs = Phi.second;
1687  EntryBuilder->setDebugLoc(PI->getDebugLoc());
1688 #ifndef NDEBUG
1689  Verifier.setCurrentInst(PI);
1690 #endif // ifndef NDEBUG
1691 
1692  // All MachineBasicBlocks exist, add them to the PHI. We assume IRTranslator
1693  // won't create extra control flow here, otherwise we need to find the
1694  // dominating predecessor here (or perhaps force the weirder IRTranslators
1695  // to provide a simple boundary).
1696  SmallSet<const BasicBlock *, 4> HandledPreds;
1697 
1698  for (unsigned i = 0; i < PI->getNumIncomingValues(); ++i) {
1699  auto IRPred = PI->getIncomingBlock(i);
1700  if (HandledPreds.count(IRPred))
1701  continue;
1702 
1703  HandledPreds.insert(IRPred);
1704  ArrayRef<unsigned> ValRegs = getOrCreateVRegs(*PI->getIncomingValue(i));
1705  for (auto Pred : getMachinePredBBs({IRPred, PI->getParent()})) {
1706  assert(Pred->isSuccessor(ComponentPHIs[0]->getParent()) &&
1707  "incorrect CFG at MachineBasicBlock level");
1708  for (unsigned j = 0; j < ValRegs.size(); ++j) {
1709  MachineInstrBuilder MIB(*MF, ComponentPHIs[j]);
1710  MIB.addUse(ValRegs[j]);
1711  MIB.addMBB(Pred);
1712  }
1713  }
1714  }
1715  }
1716 }
1717 
1718 bool IRTranslator::valueIsSplit(const Value &V,
1720  SmallVector<LLT, 4> SplitTys;
1721  if (Offsets && !Offsets->empty())
1722  Offsets->clear();
1723  computeValueLLTs(*DL, *V.getType(), SplitTys, Offsets);
1724  return SplitTys.size() > 1;
1725 }
1726 
1727 bool IRTranslator::translate(const Instruction &Inst) {
1728  CurBuilder->setDebugLoc(Inst.getDebugLoc());
1729  // We only emit constants into the entry block from here. To prevent jumpy
1730  // debug behaviour set the line to 0.
1731  if (const DebugLoc &DL = Inst.getDebugLoc())
1732  EntryBuilder->setDebugLoc(
1733  DebugLoc::get(0, 0, DL.getScope(), DL.getInlinedAt()));
1734  else
1735  EntryBuilder->setDebugLoc(DebugLoc());
1736 
1737  switch (Inst.getOpcode()) {
1738 #define HANDLE_INST(NUM, OPCODE, CLASS) \
1739  case Instruction::OPCODE: \
1740  return translate##OPCODE(Inst, *CurBuilder.get());
1741 #include "llvm/IR/Instruction.def"
1742  default:
1743  return false;
1744  }
1745 }
1746 
1747 bool IRTranslator::translate(const Constant &C, unsigned Reg) {
1748  if (auto CI = dyn_cast<ConstantInt>(&C))
1749  EntryBuilder->buildConstant(Reg, *CI);
1750  else if (auto CF = dyn_cast<ConstantFP>(&C))
1751  EntryBuilder->buildFConstant(Reg, *CF);
1752  else if (isa<UndefValue>(C))
1753  EntryBuilder->buildUndef(Reg);
1754  else if (isa<ConstantPointerNull>(C)) {
1755  // As we are trying to build a constant val of 0 into a pointer,
1756  // insert a cast to make them correct with respect to types.
1757  unsigned NullSize = DL->getTypeSizeInBits(C.getType());
1758  auto *ZeroTy = Type::getIntNTy(C.getContext(), NullSize);
1759  auto *ZeroVal = ConstantInt::get(ZeroTy, 0);
1760  unsigned ZeroReg = getOrCreateVReg(*ZeroVal);
1761  EntryBuilder->buildCast(Reg, ZeroReg);
1762  } else if (auto GV = dyn_cast<GlobalValue>(&C))
1763  EntryBuilder->buildGlobalValue(Reg, GV);
1764  else if (auto CAZ = dyn_cast<ConstantAggregateZero>(&C)) {
1765  if (!CAZ->getType()->isVectorTy())
1766  return false;
1767  // Return the scalar if it is a <1 x Ty> vector.
1768  if (CAZ->getNumElements() == 1)
1769  return translate(*CAZ->getElementValue(0u), Reg);
1771  for (unsigned i = 0; i < CAZ->getNumElements(); ++i) {
1772  Constant &Elt = *CAZ->getElementValue(i);
1773  Ops.push_back(getOrCreateVReg(Elt));
1774  }
1775  EntryBuilder->buildBuildVector(Reg, Ops);
1776  } else if (auto CV = dyn_cast<ConstantDataVector>(&C)) {
1777  // Return the scalar if it is a <1 x Ty> vector.
1778  if (CV->getNumElements() == 1)
1779  return translate(*CV->getElementAsConstant(0), Reg);
1781  for (unsigned i = 0; i < CV->getNumElements(); ++i) {
1782  Constant &Elt = *CV->getElementAsConstant(i);
1783  Ops.push_back(getOrCreateVReg(Elt));
1784  }
1785  EntryBuilder->buildBuildVector(Reg, Ops);
1786  } else if (auto CE = dyn_cast<ConstantExpr>(&C)) {
1787  switch(CE->getOpcode()) {
1788 #define HANDLE_INST(NUM, OPCODE, CLASS) \
1789  case Instruction::OPCODE: \
1790  return translate##OPCODE(*CE, *EntryBuilder.get());
1791 #include "llvm/IR/Instruction.def"
1792  default:
1793  return false;
1794  }
1795  } else if (auto CV = dyn_cast<ConstantVector>(&C)) {
1796  if (CV->getNumOperands() == 1)
1797  return translate(*CV->getOperand(0), Reg);
1799  for (unsigned i = 0; i < CV->getNumOperands(); ++i) {
1800  Ops.push_back(getOrCreateVReg(*CV->getOperand(i)));
1801  }
1802  EntryBuilder->buildBuildVector(Reg, Ops);
1803  } else if (auto *BA = dyn_cast<BlockAddress>(&C)) {
1804  EntryBuilder->buildBlockAddress(Reg, BA);
1805  } else
1806  return false;
1807 
1808  return true;
1809 }
1810 
1811 void IRTranslator::finalizeFunction() {
1812  // Release the memory used by the different maps we
1813  // needed during the translation.
1814  PendingPHIs.clear();
1815  VMap.reset();
1816  FrameIndices.clear();
1817  MachinePreds.clear();
1818  // MachineIRBuilder::DebugLoc can outlive the DILocation it holds. Clear it
1819  // to avoid accessing free’d memory (in runOnMachineFunction) and to avoid
1820  // destroying it twice (in ~IRTranslator() and ~LLVMContext())
1821  EntryBuilder.reset();
1822  CurBuilder.reset();
1823 }
1824 
1826  MF = &CurMF;
1827  const Function &F = MF->getFunction();
1828  if (F.empty())
1829  return false;
1831  getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
1832  // Set the CSEConfig and run the analysis.
1833  GISelCSEInfo *CSEInfo = nullptr;
1834  TPC = &getAnalysis<TargetPassConfig>();
1835  bool EnableCSE = EnableCSEInIRTranslator.getNumOccurrences()
1837  : TPC->isGISelCSEEnabled();
1838 
1839  if (EnableCSE) {
1840  EntryBuilder = make_unique<CSEMIRBuilder>(CurMF);
1841  CSEInfo = &Wrapper.get(TPC->getCSEConfig());
1842  EntryBuilder->setCSEInfo(CSEInfo);
1843  CurBuilder = make_unique<CSEMIRBuilder>(CurMF);
1844  CurBuilder->setCSEInfo(CSEInfo);
1845  } else {
1846  EntryBuilder = make_unique<MachineIRBuilder>();
1847  CurBuilder = make_unique<MachineIRBuilder>();
1848  }
1849  CLI = MF->getSubtarget().getCallLowering();
1850  CurBuilder->setMF(*MF);
1851  EntryBuilder->setMF(*MF);
1852  MRI = &MF->getRegInfo();
1853  DL = &F.getParent()->getDataLayout();
1854  ORE = llvm::make_unique<OptimizationRemarkEmitter>(&F);
1855 
1856  assert(PendingPHIs.empty() && "stale PHIs");
1857 
1858  if (!DL->isLittleEndian()) {
1859  // Currently we don't properly handle big endian code.
1860  OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
1861  F.getSubprogram(), &F.getEntryBlock());
1862  R << "unable to translate in big endian mode";
1863  reportTranslationError(*MF, *TPC, *ORE, R);
1864  }
1865 
1866  // Release the per-function state when we return, whether we succeeded or not.
1867  auto FinalizeOnReturn = make_scope_exit([this]() { finalizeFunction(); });
1868 
1869  // Setup a separate basic-block for the arguments and constants
1870  MachineBasicBlock *EntryBB = MF->CreateMachineBasicBlock();
1871  MF->push_back(EntryBB);
1872  EntryBuilder->setMBB(*EntryBB);
1873 
1875  SwiftError.setFunction(CurMF);
1876  SwiftError.createEntriesInEntryBlock(DbgLoc);
1877 
1878  // Create all blocks, in IR order, to preserve the layout.
1879  for (const BasicBlock &BB: F) {
1880  auto *&MBB = BBToMBB[&BB];
1881 
1882  MBB = MF->CreateMachineBasicBlock(&BB);
1883  MF->push_back(MBB);
1884 
1885  if (BB.hasAddressTaken())
1886  MBB->setHasAddressTaken();
1887  }
1888 
1889  // Make our arguments/constants entry block fallthrough to the IR entry block.
1890  EntryBB->addSuccessor(&getMBB(F.front()));
1891 
1892  // Lower the actual args into this basic block.
1893  SmallVector<unsigned, 8> VRegArgs;
1894  for (const Argument &Arg: F.args()) {
1895  if (DL->getTypeStoreSize(Arg.getType()) == 0)
1896  continue; // Don't handle zero sized types.
1897  VRegArgs.push_back(
1898  MRI->createGenericVirtualRegister(getLLTForType(*Arg.getType(), *DL)));
1899 
1900  if (Arg.hasSwiftErrorAttr())
1901  SwiftError.setCurrentVReg(EntryBB, SwiftError.getFunctionArg(),
1902  VRegArgs.back());
1903  }
1904 
1905  // We don't currently support translating swifterror or swiftself functions.
1906  for (auto &Arg : F.args()) {
1907  if (Arg.hasSwiftSelfAttr()) {
1908  OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
1909  F.getSubprogram(), &F.getEntryBlock());
1910  R << "unable to lower arguments due to swiftself: "
1911  << ore::NV("Prototype", F.getType());
1912  reportTranslationError(*MF, *TPC, *ORE, R);
1913  return false;
1914  }
1915  }
1916 
1917  if (!CLI->lowerFormalArguments(*EntryBuilder.get(), F, VRegArgs)) {
1918  OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
1919  F.getSubprogram(), &F.getEntryBlock());
1920  R << "unable to lower arguments: " << ore::NV("Prototype", F.getType());
1921  reportTranslationError(*MF, *TPC, *ORE, R);
1922  return false;
1923  }
1924 
1925  auto ArgIt = F.arg_begin();
1926  for (auto &VArg : VRegArgs) {
1927  // If the argument is an unsplit scalar then don't use unpackRegs to avoid
1928  // creating redundant copies.
1929  if (!valueIsSplit(*ArgIt, VMap.getOffsets(*ArgIt))) {
1930  auto &VRegs = *VMap.getVRegs(cast<Value>(*ArgIt));
1931  assert(VRegs.empty() && "VRegs already populated?");
1932  VRegs.push_back(VArg);
1933  } else {
1934  unpackRegs(*ArgIt, VArg, *EntryBuilder.get());
1935  }
1936  ArgIt++;
1937  }
1938 
1939  // Need to visit defs before uses when translating instructions.
1940  GISelObserverWrapper WrapperObserver;
1941  if (EnableCSE && CSEInfo)
1942  WrapperObserver.addObserver(CSEInfo);
1943  {
1945 #ifndef NDEBUG
1946  DILocationVerifier Verifier;
1947  WrapperObserver.addObserver(&Verifier);
1948 #endif // ifndef NDEBUG
1949  RAIIDelegateInstaller DelInstall(*MF, &WrapperObserver);
1950  for (const BasicBlock *BB : RPOT) {
1951  MachineBasicBlock &MBB = getMBB(*BB);
1952  // Set the insertion point of all the following translations to
1953  // the end of this basic block.
1954  CurBuilder->setMBB(MBB);
1955 
1956  for (const Instruction &Inst : *BB) {
1957 #ifndef NDEBUG
1958  Verifier.setCurrentInst(&Inst);
1959 #endif // ifndef NDEBUG
1960  if (translate(Inst))
1961  continue;
1962 
1963  OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
1964  Inst.getDebugLoc(), BB);
1965  R << "unable to translate instruction: " << ore::NV("Opcode", &Inst);
1966 
1967  if (ORE->allowExtraAnalysis("gisel-irtranslator")) {
1968  std::string InstStrStorage;
1969  raw_string_ostream InstStr(InstStrStorage);
1970  InstStr << Inst;
1971 
1972  R << ": '" << InstStr.str() << "'";
1973  }
1974 
1975  reportTranslationError(*MF, *TPC, *ORE, R);
1976  return false;
1977  }
1978  }
1979 #ifndef NDEBUG
1980  WrapperObserver.removeObserver(&Verifier);
1981 #endif
1982  }
1983 
1984  finishPendingPhis();
1985 
1986  SwiftError.propagateVRegs();
1987 
1988  // Merge the argument lowering and constants block with its single
1989  // successor, the LLVM-IR entry block. We want the basic block to
1990  // be maximal.
1991  assert(EntryBB->succ_size() == 1 &&
1992  "Custom BB used for lowering should have only one successor");
1993  // Get the successor of the current entry block.
1994  MachineBasicBlock &NewEntryBB = **EntryBB->succ_begin();
1995  assert(NewEntryBB.pred_size() == 1 &&
1996  "LLVM-IR entry block has a predecessor!?");
1997  // Move all the instruction from the current entry block to the
1998  // new entry block.
1999  NewEntryBB.splice(NewEntryBB.begin(), EntryBB, EntryBB->begin(),
2000  EntryBB->end());
2001 
2002  // Update the live-in information for the new entry block.
2003  for (const MachineBasicBlock::RegisterMaskPair &LiveIn : EntryBB->liveins())
2004  NewEntryBB.addLiveIn(LiveIn);
2005  NewEntryBB.sortUniqueLiveIns();
2006 
2007  // Get rid of the now empty basic block.
2008  EntryBB->removeSuccessor(&NewEntryBB);
2009  MF->remove(EntryBB);
2010  MF->DeleteMachineBasicBlock(EntryBB);
2011 
2012  assert(&MF->front() == &NewEntryBB &&
2013  "New entry wasn't next in the list of basic block!");
2014 
2015  // Initialize stack protector information.
2016  StackProtector &SP = getAnalysis<StackProtector>();
2017  SP.copyToMachineFrameInfo(MF->getFrameInfo());
2018 
2019  return false;
2020 }
auto lower_bound(R &&Range, T &&Value) -> decltype(adl_begin(Range))
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1288
uint64_t CallInst * C
Return a value (possibly void), from a function.
Value * getValueOperand()
Definition: Instructions.h:409
bool isIntrinsic() const
isIntrinsic - Returns true if the function&#39;s name starts with "llvm.".
Definition: Function.h:198
A simple RAII based CSEInfo installer.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:641
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:722
bool empty() const
Definition: Function.h:678
static IntegerType * getInt1Ty(LLVMContext &C)
Definition: Type.cpp:172
The CSE Analysis object.
Definition: CSEInfo.h:71
Diagnostic information for missed-optimization remarks.
DILocation * get() const
Get the underlying DILocation.
Definition: DebugLoc.cpp:21
This instruction extracts a struct member or array element value from an aggregate value...
MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
*p = old <signed v ? old : v
Definition: Instructions.h:721
iterator_range< CaseIt > cases()
Iteration adapter for range-for loops.
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
LLVMContext & Context
MachineInstrBuilder buildGEP(unsigned Res, unsigned Op0, unsigned Op1)
Build and insert Res = G_GEP Op0, Op1.
DiagnosticInfoOptimizationBase::Argument NV
This represents the llvm.dbg.label instruction.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
MachineInstrBuilder buildIndirectDbgValue(unsigned Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:364
MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
bool isSized(SmallPtrSetImpl< Type *> *Visited=nullptr) const
Return true if it makes sense to take the size of this type.
Definition: Type.h:264
iterator begin() const
Definition: ArrayRef.h:136
void setIsEHPad(bool V=true)
Indicates the block is a landing pad.
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:528
void push_back(const T &Elt)
Definition: SmallVector.h:211
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< unsigned > Res, bool HasSideEffects)
Build and insert either a G_INTRINSIC (if HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS inst...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:384
unsigned getReg() const
getReg - Returns the register number.
MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src)
Build and insert an appropriate cast between two registers of equal size.
IRTranslator LLVM IR static false void reportTranslationError(MachineFunction &MF, const TargetPassConfig &TPC, OptimizationRemarkEmitter &ORE, OptimizationRemarkMissed &R)
This class represents a function call, abstracting a target machine&#39;s calling convention.
unsigned Reg
This file contains the declarations for metadata subclasses.
Value * getCondition() const
static uint64_t round(uint64_t Acc, uint64_t Input)
Definition: xxhash.cpp:57
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID of this store instruction.
Definition: Instructions.h:384
gep_type_iterator gep_type_end(const User *GEP)
const std::string & getAsmString() const
Definition: InlineAsm.h:80
*p = old <unsigned v ? old : v
Definition: Instructions.h:725
bool isSwiftError() const
Return true if this alloca is used as a swifterror argument to a call.
Definition: Instructions.h:135
AtomicOrdering getOrdering() const
Returns the ordering constraint of this load instruction.
Definition: Instructions.h:247
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1047
*p = old >unsigned v ? old : v
Definition: Instructions.h:723
LLVM_NODISCARD detail::scope_exit< typename std::decay< Callable >::type > make_scope_exit(Callable &&F)
Definition: ScopeExit.h:58
LLVMContext & getContext() const
All values hold a context through their type.
Definition: Value.cpp:720
Type * getPointerOperandType() const
Definition: Instructions.h:415
unsigned getLine() const
Definition: DebugLoc.cpp:25
bool hasDLLImportStorageClass() const
Definition: GlobalValue.h:265
BasicBlock * getSuccessor(unsigned i) const
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
F(f)
The actual analysis pass wrapper.
Definition: CSEInfo.h:218
An instruction for reading from memory.
Definition: Instructions.h:167
void setMF(MachineFunction &MF)
Definition: CSEInfo.cpp:77
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:691
Value * getCondition() const
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:229
GlobalValue * ExtractTypeInfo(Value *V)
ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
Definition: Analysis.cpp:158
*p = old >signed v ? old : v
Definition: Instructions.h:719
virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
static Constant * getNullValue(Type *Ty)
Constructor to create a &#39;0&#39; constant of arbitrary type.
Definition: Constants.cpp:274
AtomicOrdering getFailureOrdering() const
Returns the failure ordering constraint of this cmpxchg instruction.
Definition: Instructions.h:595
MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)
Build and insert `Res0, ...
bool hasSideEffects() const
Definition: InlineAsm.h:66
Value * getArgOperand(unsigned i) const
Definition: InstrTypes.h:1241
MachineInstrBuilder buildStore(unsigned Val, unsigned Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
AnalysisUsage & addRequired()
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:50
bool isVolatile() const
Return true if this is a load from a volatile memory location.
Definition: Instructions.h:231
A description of a memory reference used in the backend.
amdgpu aa AMDGPU Address space based Alias Analysis Wrapper
unsigned countOperandBundlesOfType(StringRef Name) const
Return the number of operand bundles with the tag Name attached to this instruction.
Definition: InstrTypes.h:1784
This class represents the LLVM &#39;select&#39; instruction.
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:369
#define DEBUG_TYPE
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
unsigned getAlignment() const
Return the alignment of the memory that is being allocated by the instruction.
Definition: Instructions.h:112
PointerType * getType() const
Overload to return most specific pointer type.
Definition: Instructions.h:96
Class to represent struct types.
Definition: DerivedTypes.h:232
DILabel * getLabel() const
BinOp getOperation() const
Definition: Instructions.h:750
const MachineInstrBuilder & addUse(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
bool isWeak() const
Return true if this cmpxchg may spuriously fail.
Definition: Instructions.h:569
TypeID
Definitions of all of the base types for the Type system.
Definition: Type.h:54
The memory access is dereferenceable (i.e., doesn&#39;t trap).
bool isVolatile() const
Return true if this is a cmpxchg from a volatile memory location.
Definition: Instructions.h:557
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Target-Independent Code Generator Pass Configuration Options.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:695
Context object for machine code objects.
Definition: MCContext.h:62
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:244
Definition: Lint.cpp:83
AtomicOrdering getSuccessOrdering() const
Returns the success ordering constraint of this cmpxchg instruction.
Definition: Instructions.h:582
MachineInstrBuilder buildAtomicRMW(unsigned Opcode, unsigned OldValRes, unsigned Addr, unsigned Val, MachineMemOperand &MMO)
Build and insert OldValRes<def> = G_ATOMICRMW_<Opcode> Addr, Val, MMO.
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:125
iterator_range< User::op_iterator > arg_operands()
Definition: InstrTypes.h:1233
An instruction for storing to memory.
Definition: Instructions.h:320
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
Value * getOperand(unsigned i) const
Definition: User.h:169
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
This corresponds to the llvm.lifetime.
Definition: ISDOpcodes.h:877
bool doesNotAccessMemory() const
Determine if the function does not access memory.
Definition: Function.h:473
MachineInstrBuilder buildDbgLabel(const MDNode *Label)
Build and insert a DBG_LABEL instructions specifying that Label is given.
bool isVoidTy() const
Return true if this is &#39;void&#39;.
Definition: Type.h:140
The memory access is volatile.
bool isValidLocationForIntrinsic(const DILocation *DL) const
Check that a location is valid for this label.
const BasicBlock & getEntryBlock() const
Definition: Function.h:656
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
Definition: MathExtras.h:609
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
Abstract class that contains various methods for clients to notify about changes. ...
FPOpFusion::FPOpFusionMode AllowFPOpFusion
AllowFPOpFusion - This flag is set by the -fuse-fp-ops=xxx option.
The landingpad instruction holds all of the information necessary to generate correct exception handl...
const Instruction * getFirstNonPHI() const
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
Definition: BasicBlock.cpp:189
void GetUnderlyingObjects(const Value *V, SmallVectorImpl< const Value *> &Objects, const DataLayout &DL, LoopInfo *LI=nullptr, unsigned MaxLookup=6)
This method is similar to GetUnderlyingObject except that it can look through phi and select instruct...
* if(!EatIfPresent(lltok::kw_thread_local)) return false
ParseOptionalThreadLocal := /*empty.
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID of this rmw instruction.
Definition: Instructions.h:802
unsigned const MachineRegisterInfo * MRI
Value * getCalledValue() const
Definition: InstrTypes.h:1280
LLVM Basic Block Representation.
Definition: BasicBlock.h:57
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
DISubprogram * getSubprogram() const
Get the attached subprogram.
Definition: Metadata.cpp:1504
Conditional or Unconditional Branch instruction.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Value * getAddress() const
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This is an important base class in LLVM.
Definition: Constant.h:41
bool isInlineAsm() const
Check if this call is an inline asm statement.
Definition: InstrTypes.h:1356
Value * getValue() const
MachineInstrBuilder buildPtrMask(unsigned Res, unsigned Op0, uint32_t NumBits)
Build and insert Res = G_PTR_MASK Op0, NumBits.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const Instruction & front() const
Definition: BasicBlock.h:280
void computeValueLLTs(const DataLayout &DL, Type &Ty, SmallVectorImpl< LLT > &ValueTys, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
computeValueLLTs - Given an LLVM IR type, compute a sequence of LLTs that represent all the individua...
Definition: Analysis.cpp:127
Indirect Branch Instruction.
Helper class to build MachineInstr.
BasicBlock * getDefaultDest() const
DIExpression * getExpression() const
bool isValidLocationForIntrinsic(const DILocation *DL) const
Check that a location is valid for this variable.
Represent the analysis usage information of a pass.
GISelCSEInfo & get(std::unique_ptr< CSEConfigBase > CSEOpt, bool ReCompute=false)
Takes a CSEConfigBase object that defines what opcodes get CSEd.
Definition: CSEInfo.cpp:363
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:732
MachineInstrBuilder buildInsert(unsigned Res, unsigned Src, unsigned Op, unsigned Index)
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Value * getPointerOperand()
Definition: Instructions.h:284
self_iterator getIterator()
Definition: ilist_node.h:81
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn&#39;t already there.
Definition: SmallSet.h:180
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
static double log2(double V)
static Constant * getAllOnesValue(Type *Ty)
Definition: Constants.cpp:328
1 1 1 1 Always true (always folded)
Definition: InstrTypes.h:749
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:205
MachineInstrBuilder buildBrIndirect(unsigned Tgt)
Build and insert G_BRINDIRECT Tgt.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID of this cmpxchg instruction.
Definition: Instructions.h:608
BasicBlock * getSuccessor(unsigned i) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const Value * getArraySize() const
Get the number of elements allocated.
Definition: Instructions.h:92
size_t size() const
Definition: SmallVector.h:52
Value * getIncomingValue(unsigned i) const
Return incoming value number x.
static uint16_t copyFlagsFromInstruction(const Instruction &I)
AtomicOrdering getOrdering() const
Returns the ordering constraint of this rmw instruction.
Definition: Instructions.h:789
Simple wrapper that does the following.
Definition: CSEInfo.h:200
This class contains a discriminated union of information about pointers in memory operands...
std::string & str()
Flushes the stream contents to the target string and returns the string&#39;s reference.
Definition: raw_ostream.h:498
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
const std::string & getConstraintString() const
Definition: InlineAsm.h:81
Type * getAllocatedType() const
Return the type that is being allocated by the instruction.
Definition: Instructions.h:105
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
Definition: ISDOpcodes.h:703
MachineInstrBuilder buildFrameIndex(unsigned Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
LLT getLLTForType(Type &Ty, const DataLayout &DL)
Construct a low-level type based on an LLVM type.
The memory access writes data.
MachineInstrBuilder buildBr(MachineBasicBlock &Dest)
Build and insert G_BR Dest.
bool hasAddressTaken() const
Returns true if there are any uses of this basic block other than direct branches, switches, etc.
Definition: BasicBlock.h:391
MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...
Value * getValOperand()
Definition: Instructions.h:815
Predicate getPredicate(unsigned Condition, unsigned Hint)
Return predicate consisting of specified condition and hint bits.
Definition: PPCPredicates.h:87
unsigned getNumOperands() const
Definition: User.h:191
MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_MUL Op0, Op1.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
iterator end() const
Definition: ArrayRef.h:137
bool isAggregateType() const
Return true if the type is an aggregate type.
Definition: Type.h:257
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
static uint64_t getOffsetFromIndices(const User &U, const DataLayout &DL)
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:643
MachineInstrBuilder buildBrCond(unsigned Tst, MachineBasicBlock &Dest)
Build and insert G_BRCOND Tst, Dest.
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
Definition: Type.cpp:179
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:631
DebugLoc getDebugLoc()
Get the current instruction&#39;s debug location.
unsigned getNumIncomingValues() const
Return the number of incoming edges.
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
Intrinsic::ID getIntrinsicID() const LLVM_READONLY
getIntrinsicID - This method returns the ID number of the specified function, or Intrinsic::not_intri...
Definition: Function.h:193
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:538
MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
unsigned getVectorNumElements() const
Definition: DerivedTypes.h:493
bool isIntPredicate() const
Definition: InstrTypes.h:825
const Module * getModule() const
Return the module owning the function this instruction belongs to or nullptr it the function does not...
Definition: Instruction.cpp:55
Class for arbitrary precision integers.
Definition: APInt.h:69
amdgpu Simplify well known AMD library false FunctionCallee Callee
MachineInstrBuilder buildAtomicCmpXchgWithSuccess(unsigned OldValRes, unsigned SuccessRes, unsigned Addr, unsigned CmpVal, unsigned NewVal, MachineMemOperand &MMO)
Build and insert OldValRes<def>, SuccessRes<def> = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO.
static MachineOperand CreateES(const char *SymName, unsigned char TargetFlags=0)
static char ID
Definition: IRTranslator.h:61
virtual bool isFMAFasterThanFMulAndFAdd(EVT) const
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
The memory access reads data.
#define Success
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Representation of each machine instruction.
Definition: MachineInstr.h:63
Predicate getPredicate() const
Return the predicate for this instruction.
Definition: InstrTypes.h:807
This file provides various utilities for inspecting and working with the control flow graph in LLVM I...
void addObserver(GISelChangeObserver *O)
bool isVolatile() const
Return true if this is a store to a volatile memory location.
Definition: Instructions.h:353
MachineInstrBuilder buildDirectDbgValue(unsigned Reg, const MDNode *Variable, const MDNode *Expr)
Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...
const DebugLoc & getDebugLoc() const
Return the debug location for this node as a DebugLoc.
Definition: Instruction.h:321
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Type * getPointerOperandType() const
Definition: Instructions.h:287
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:175
void removeObserver(GISelChangeObserver *O)
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
AtomicOrdering getOrdering() const
Returns the ordering constraint of this store instruction.
Definition: Instructions.h:372
This represents the llvm.dbg.value instruction.
bool isTokenTy() const
Return true if this is &#39;token&#39;.
Definition: Type.h:193
CallingConv::ID getCallingConv() const
Definition: InstrTypes.h:1344
verify safepoint Safepoint IR Verifier
Value * getPointerOperand()
Definition: Instructions.h:811
TargetOptions Options
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
BasicBlock * getIncomingBlock(unsigned i) const
Return incoming basic block number i.
Function * getCalledFunction() const
Returns the function called, or null if this is an indirect function invocation.
Definition: InstrTypes.h:1287
static cl::opt< bool > EnableCSEInIRTranslator("enable-cse-in-irtranslator", cl::desc("Should enable CSE in irtranslator"), cl::Optional, cl::init(false))
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID of this load instruction.
Definition: Instructions.h:259
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned char TargetFlags=0) const
void push_back(MachineInstr *MI)
#define I(x, y, z)
Definition: MD5.cpp:58
static Constant * getZeroValueForNegation(Type *Ty)
Floating point negation must be implemented with f(x) = -0.0 - x.
Definition: Constants.cpp:780
Pair of physical register and lane mask.
The memory access always returns the same value (or traps).
bool isZero() const
This is just a convenience method to make client code smaller for a common code.
Definition: Constants.h:192
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
uint32_t Size
Definition: Profile.cpp:46
DILocalVariable * getVariable() const
Value * getReturnValue() const
Convenience accessor. Returns null if there is no return value.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
bool isUnconditional() const
Optional< MachineInstrBuilder > materializeGEP(unsigned &Res, unsigned Op0, const LLT &ValueTy, uint64_t Value)
Materialize and insert Res = G_GEP Op0, (G_CONSTANT Value)
AsmDialect getDialect() const
Definition: InlineAsm.h:68
Multiway switch.
This file declares the IRTranslator pass.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:482
aarch64 promote const
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:575
LLVM Value Representation.
Definition: Value.h:72
static bool isSwiftError(const Value *V)
uint64_t getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type...
Definition: DataLayout.h:444
succ_range successors(Instruction *I)
Definition: CFG.h:259
This file describes how to lower LLVM calls to machine code calls.
MachineInstrBuilder buildLoad(unsigned Res, unsigned Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
INITIALIZE_PASS_BEGIN(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI", false, false) INITIALIZE_PASS_END(IRTranslator
Invoke instruction.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
IRTranslator LLVM IR MI
const MachineInstrBuilder & addDef(unsigned RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
Simple wrapper observer that takes several observers, and calls each one for each event...
bool isStaticAlloca() const
Return true if this alloca is in the entry block of the function and is a constant size...
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:415
OutputIt copy(R &&Range, OutputIt Out)
Definition: STLExtras.h:1244
This represents the llvm.dbg.declare instruction.
Value * getPointerOperand()
Definition: Instructions.h:412
The optimization diagnostic interface.
Statically lint checks LLVM IR
Definition: Lint.cpp:192
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
int64_t getIndexedOffsetInType(Type *ElemTy, ArrayRef< Value *> Indices) const
Returns the offset from the beginning of the type for the specified indices.
Definition: DataLayout.cpp:806
bool isVolatile() const
Return true if this is a RMW on a volatile memory location.
Definition: Instructions.h:774
0 0 0 0 Always false (always folded)
Definition: InstrTypes.h:734
IntegerType * Int32Ty
This file describes how to lower LLVM code to machine code.
const BasicBlock * getParent() const
Definition: Instruction.h:66
virtual const TargetRegisterClass * getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const
Returns a TargetRegisterClass used for pointer values.
an instruction to allocate memory on the stack
Definition: Instructions.h:59
This instruction inserts a struct field of array element value into an aggregate value.
gep_type_iterator gep_type_begin(const User *GEP)
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:164