14#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
15#define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
125class HexagonSubtarget;
128 int VarArgsFrameOffset;
147 unsigned Intrinsic)
const override;
169 unsigned DefinedValues)
const override;
171 unsigned Index)
const override;
230 unsigned ReturnReg,
unsigned char OperandGlues)
const;
286 EVT VT)
const override {
300 std::pair<unsigned, const TargetRegisterClass *>
313 Type *Ty,
unsigned AS,
320 bool ForCodeSize)
const override;
332 unsigned AddrSpace,
Align Alignment,
334 unsigned *
Fast)
const override;
339 unsigned *
Fast)
const override;
346 EVT NewVT)
const override;
367 void initializeHVXLowering();
368 unsigned getPreferredHvxVectorAction(
MVT VecTy)
const;
369 unsigned getCustomHvxOperationAction(
SDNode &
Op)
const;
375 std::pair<SDValue,int> getBaseAndOffset(
SDValue Addr)
const;
403 if (
Op.isMachineOpcode())
404 return Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF;
407 SDValue getInstr(
unsigned MachineOpc,
const SDLoc &dl, MVT Ty,
408 ArrayRef<SDValue> Ops, SelectionDAG &DAG)
const {
409 SDNode *
N = DAG.getMachineNode(MachineOpc, dl, Ty, Ops);
410 return SDValue(
N, 0);
412 SDValue getZero(
const SDLoc &dl, MVT Ty, SelectionDAG &DAG)
const;
414 using VectorPair = std::pair<SDValue, SDValue>;
415 using TypePair = std::pair<MVT, MVT>;
417 SDValue getInt(
unsigned IntId, MVT ResTy, ArrayRef<SDValue> Ops,
418 const SDLoc &dl, SelectionDAG &DAG)
const;
420 MVT ty(SDValue
Op)
const {
421 return Op.getValueType().getSimpleVT();
423 TypePair ty(
const VectorPair &Ops)
const {
424 return { Ops.first.getValueType().getSimpleVT(),
425 Ops.second.getValueType().getSimpleVT() };
427 MVT tyScalar(MVT Ty)
const {
432 MVT tyVector(MVT Ty, MVT ElemTy)
const {
433 if (Ty.isVector() && Ty.getVectorElementType() == ElemTy)
435 unsigned TyWidth = Ty.getSizeInBits();
436 unsigned ElemWidth = ElemTy.getSizeInBits();
437 assert((TyWidth % ElemWidth) == 0);
441 MVT typeJoin(
const TypePair &Tys)
const;
442 TypePair typeSplit(MVT Ty)
const;
443 MVT typeExtElem(MVT VecTy,
unsigned Factor)
const;
444 MVT typeTruncElem(MVT VecTy,
unsigned Factor)
const;
445 TypePair typeExtendToWider(MVT Ty0, MVT Ty1)
const;
446 TypePair typeWidenToWider(MVT Ty0, MVT Ty1)
const;
447 MVT typeLegalize(MVT Ty, SelectionDAG &DAG)
const;
448 MVT typeWidenToHvx(MVT Ty)
const;
450 SDValue opJoin(
const VectorPair &Ops,
const SDLoc &dl,
451 SelectionDAG &DAG)
const;
452 VectorPair opSplit(SDValue Vec,
const SDLoc &dl, SelectionDAG &DAG)
const;
453 SDValue opCastElem(SDValue Vec, MVT ElemTy, SelectionDAG &DAG)
const;
455 SDValue LoHalf(SDValue V, SelectionDAG &DAG)
const {
458 if (!Ty.isVector()) {
459 assert(Ty.getSizeInBits() == 64);
460 return DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, V);
462 MVT HalfTy = typeSplit(Ty).first;
463 SDValue
Idx = getZero(dl, MVT::i32, DAG);
466 SDValue HiHalf(SDValue V, SelectionDAG &DAG)
const {
469 if (!Ty.isVector()) {
470 assert(Ty.getSizeInBits() == 64);
471 return DAG.getTargetExtractSubreg(Hexagon::isub_hi, dl, MVT::i32, V);
473 MVT HalfTy = typeSplit(Ty).first;
474 SDValue
Idx = DAG.getConstant(HalfTy.getVectorNumElements(), dl, MVT::i32);
479 unsigned *
Fast)
const;
480 bool allowsHvxMisalignedMemoryAccesses(MVT VecTy,
482 unsigned *
Fast)
const;
483 void AdjustHvxInstrPostInstrSelection(MachineInstr &
MI, SDNode *
Node)
const;
485 bool isHvxSingleTy(MVT Ty)
const;
486 bool isHvxPairTy(MVT Ty)
const;
487 bool isHvxBoolTy(MVT Ty)
const;
488 SDValue convertToByteIndex(SDValue ElemIdx, MVT ElemTy,
489 SelectionDAG &DAG)
const;
490 SDValue getIndexInWord32(SDValue
Idx, MVT ElemTy, SelectionDAG &DAG)
const;
491 SDValue getByteShuffle(
const SDLoc &dl, SDValue Op0, SDValue Op1,
492 ArrayRef<int> Mask, SelectionDAG &DAG)
const;
494 SDValue buildHvxVectorReg(ArrayRef<SDValue> Values,
const SDLoc &dl,
495 MVT VecTy, SelectionDAG &DAG)
const;
496 SDValue buildHvxVectorPred(ArrayRef<SDValue> Values,
const SDLoc &dl,
497 MVT VecTy, SelectionDAG &DAG)
const;
498 SDValue createHvxPrefixPred(SDValue PredV,
const SDLoc &dl,
499 unsigned BitBytes,
bool ZeroFill,
500 SelectionDAG &DAG)
const;
501 SDValue extractHvxElementReg(SDValue VecV, SDValue IdxV,
const SDLoc &dl,
502 MVT ResTy, SelectionDAG &DAG)
const;
503 SDValue extractHvxElementPred(SDValue VecV, SDValue IdxV,
const SDLoc &dl,
504 MVT ResTy, SelectionDAG &DAG)
const;
505 SDValue insertHvxElementReg(SDValue VecV, SDValue IdxV, SDValue ValV,
506 const SDLoc &dl, SelectionDAG &DAG)
const;
507 SDValue insertHvxElementPred(SDValue VecV, SDValue IdxV, SDValue ValV,
508 const SDLoc &dl, SelectionDAG &DAG)
const;
509 SDValue extractHvxSubvectorReg(SDValue OrigOp, SDValue VecV, SDValue IdxV,
510 const SDLoc &dl, MVT ResTy, SelectionDAG &DAG)
512 SDValue extractHvxSubvectorPred(SDValue VecV, SDValue IdxV,
const SDLoc &dl,
513 MVT ResTy, SelectionDAG &DAG)
const;
514 SDValue insertHvxSubvectorReg(SDValue VecV, SDValue SubV, SDValue IdxV,
515 const SDLoc &dl, SelectionDAG &DAG)
const;
516 SDValue insertHvxSubvectorPred(SDValue VecV, SDValue SubV, SDValue IdxV,
517 const SDLoc &dl, SelectionDAG &DAG)
const;
518 SDValue extendHvxVectorPred(SDValue VecV,
const SDLoc &dl, MVT ResTy,
519 bool ZeroExt, SelectionDAG &DAG)
const;
520 SDValue compressHvxPred(SDValue VecQ,
const SDLoc &dl, MVT ResTy,
521 SelectionDAG &DAG)
const;
522 SDValue resizeToWidth(SDValue VecV, MVT ResTy,
bool Signed,
const SDLoc &dl,
523 SelectionDAG &DAG)
const;
524 SDValue extractSubvector(SDValue Vec, MVT SubTy,
unsigned SubIdx,
525 SelectionDAG &DAG)
const;
526 VectorPair emitHvxAddWithOverflow(SDValue
A, SDValue
B,
const SDLoc &dl,
527 bool Signed, SelectionDAG &DAG)
const;
528 VectorPair emitHvxShiftRightRnd(SDValue Val,
unsigned Amt,
bool Signed,
529 SelectionDAG &DAG)
const;
530 SDValue emitHvxMulHsV60(SDValue
A, SDValue
B,
const SDLoc &dl,
531 SelectionDAG &DAG)
const;
532 SDValue emitHvxMulLoHiV60(SDValue
A,
bool SignedA, SDValue
B,
bool SignedB,
533 const SDLoc &dl, SelectionDAG &DAG)
const;
534 SDValue emitHvxMulLoHiV62(SDValue
A,
bool SignedA, SDValue
B,
bool SignedB,
535 const SDLoc &dl, SelectionDAG &DAG)
const;
537 SDValue LowerHvxBuildVector(SDValue
Op, SelectionDAG &DAG)
const;
538 SDValue LowerHvxSplatVector(SDValue
Op, SelectionDAG &DAG)
const;
539 SDValue LowerHvxConcatVectors(SDValue
Op, SelectionDAG &DAG)
const;
540 SDValue LowerHvxExtractElement(SDValue
Op, SelectionDAG &DAG)
const;
541 SDValue LowerHvxInsertElement(SDValue
Op, SelectionDAG &DAG)
const;
542 SDValue LowerHvxExtractSubvector(SDValue
Op, SelectionDAG &DAG)
const;
543 SDValue LowerHvxInsertSubvector(SDValue
Op, SelectionDAG &DAG)
const;
544 SDValue LowerHvxBitcast(SDValue
Op, SelectionDAG &DAG)
const;
545 SDValue LowerHvxAnyExt(SDValue
Op, SelectionDAG &DAG)
const;
546 SDValue LowerHvxSignExt(SDValue
Op, SelectionDAG &DAG)
const;
547 SDValue LowerHvxZeroExt(SDValue
Op, SelectionDAG &DAG)
const;
548 SDValue LowerHvxCttz(SDValue
Op, SelectionDAG &DAG)
const;
549 SDValue LowerHvxMulh(SDValue
Op, SelectionDAG &DAG)
const;
550 SDValue LowerHvxMulLoHi(SDValue
Op, SelectionDAG &DAG)
const;
551 SDValue LowerHvxExtend(SDValue
Op, SelectionDAG &DAG)
const;
552 SDValue LowerHvxSelect(SDValue
Op, SelectionDAG &DAG)
const;
553 SDValue LowerHvxShift(SDValue
Op, SelectionDAG &DAG)
const;
554 SDValue LowerHvxFunnelShift(SDValue
Op, SelectionDAG &DAG)
const;
555 SDValue LowerHvxIntrinsic(SDValue
Op, SelectionDAG &DAG)
const;
556 SDValue LowerHvxMaskedOp(SDValue
Op, SelectionDAG &DAG)
const;
557 SDValue LowerHvxFpExtend(SDValue
Op, SelectionDAG &DAG)
const;
558 SDValue LowerHvxFpToInt(SDValue
Op, SelectionDAG &DAG)
const;
559 SDValue LowerHvxIntToFp(SDValue
Op, SelectionDAG &DAG)
const;
560 SDValue ExpandHvxFpToInt(SDValue
Op, SelectionDAG &DAG)
const;
561 SDValue ExpandHvxIntToFp(SDValue
Op, SelectionDAG &DAG)
const;
563 VectorPair SplitVectorOp(SDValue
Op, SelectionDAG &DAG)
const;
565 SDValue SplitHvxMemOp(SDValue
Op, SelectionDAG &DAG)
const;
566 SDValue WidenHvxLoad(SDValue
Op, SelectionDAG &DAG)
const;
567 SDValue WidenHvxStore(SDValue
Op, SelectionDAG &DAG)
const;
568 SDValue WidenHvxSetCC(SDValue
Op, SelectionDAG &DAG)
const;
569 SDValue LegalizeHvxResize(SDValue
Op, SelectionDAG &DAG)
const;
570 SDValue ExpandHvxResizeIntoSteps(SDValue
Op, SelectionDAG &DAG)
const;
571 SDValue EqualizeFpIntConversion(SDValue
Op, SelectionDAG &DAG)
const;
573 SDValue CreateTLWrapper(SDValue
Op, SelectionDAG &DAG)
const;
574 SDValue RemoveTLWrapper(SDValue
Op, SelectionDAG &DAG)
const;
576 std::pair<const TargetRegisterClass*, uint8_t>
577 findRepresentativeClass(
const TargetRegisterInfo *
TRI, MVT VT)
580 bool shouldSplitToHvx(MVT Ty, SelectionDAG &DAG)
const;
581 bool shouldWidenToHvx(MVT Ty, SelectionDAG &DAG)
const;
582 bool isHvxOperation(SDNode *
N, SelectionDAG &DAG)
const;
583 SDValue LowerHvxOperation(SDValue
Op, SelectionDAG &DAG)
const;
584 void LowerHvxOperationWrapper(SDNode *
N, SmallVectorImpl<SDValue> &
Results,
585 SelectionDAG &DAG)
const;
586 void ReplaceHvxNodeResults(SDNode *
N, SmallVectorImpl<SDValue> &
Results,
587 SelectionDAG &DAG)
const;
589 SDValue combineTruncateBeforeLegal(SDValue
Op, DAGCombinerInfo &DCI)
const;
590 SDValue combineConcatVectorsBeforeLegal(SDValue
Op, DAGCombinerInfo & DCI)
592 SDValue combineVectorShuffleBeforeLegal(SDValue
Op, DAGCombinerInfo & DCI)
595 SDValue PerformHvxDAGCombine(SDNode *
N, DAGCombinerInfo & DCI)
const;
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Analysis containing CSE Info
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file describes how to lower LLVM code to machine code.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
An instruction that atomically checks whether a specified value is in a memory location,...
an instruction that atomically reads a memory location, combines it with another value,...
This class represents a function call, abstracting a target machine's calling convention.
This is an important base class in LLVM.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const
SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
bool isCtlzFast() const override
Return true if ctlz instruction is fast.
SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
bool isTargetCanonicalConstantNode(SDValue Op) const override
Returns true if the given Opc is considered a canonical constant for the target, which should not be ...
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const
SDValue LowerUAddSubO(SDValue Op, SelectionDAG &DAG) const
SDValue LowerANY_EXTEND(SDValue Op, SelectionDAG &DAG) const
Value * emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate,...
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const
AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.
SDValue GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, SDValue InGlue, EVT PtrVT, unsigned ReturnReg, unsigned char OperandGlues) const
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
SDValue LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const
SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const
SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const
bool isCheapToSpeculateCtlz(Type *) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively.
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
bool isCheapToSpeculateCttz(Type *) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
SDValue LowerCallResult(SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, const SmallVectorImpl< SDValue > &OutVals, SDValue Callee) const
LowerCallResult - Lower the result values of an ISD::CALL into the appropriate copies out of appropri...
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
SDValue LowerToTLSInitialExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const override
Return true if the target supports a memory access of this type for the given address space and align...
SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
SDValue LowerLoad(SDValue Op, SelectionDAG &DAG) const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
bool isShuffleMaskLegal(ArrayRef< int > Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations,...
LegalizeAction getCustomOperationAction(SDNode &Op) const override
How to legalize this custom operation?
SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
SDValue LowerUAddSubOCarry(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
LowerCall - Functions arguments are copied from virtual regs to (physical regs)/(stack frame),...
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const override
Determine if the target supports unaligned memory accesses.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
SDValue LowerStore(SDValue Op, SelectionDAG &DAG) const
SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const
SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
EVT getSetCCResultType(const DataLayout &, LLVMContext &C, EVT VT) const override
Return the ValueType of the result of SETCC operations.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Value * emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization.
SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const
void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const
SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &, EVT) const override
Return true if an FMA operation is faster than a pair of mul and add instructions.
SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const
LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override
Return true if it is profitable to reduce a load to a smaller type.
SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const
SDValue LowerREADSTEADYCOUNTER(SDValue Op, SelectionDAG &DAG) const
Common base class shared among various IRBuilders.
This is an important class for using LLVM in a threaded context.
An instruction for reading from memory.
static MVT getVectorVT(MVT VT, unsigned NumElements)
static MVT getIntegerVT(unsigned BitWidth)
Representation of each machine instruction.
Flags
Flags values. These may be or'd together.
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
An instruction for storing to memory.
StringRef - Represent a constant reference to a string, i.e.
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
LLVM Value Representation.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ C
The default llvm calling convention, compatible with C.
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
@ UNDEF
UNDEF - An undefined node.
@ EXTRACT_SUBVECTOR
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
This is an optimization pass for GlobalISel generic memory operations.
AtomicOrdering
Atomic ordering for LLVM's memory model.
DWARFExpression::Operation Op
This struct is a compact representation of a valid (non-zero power of two) alignment.
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
bool isVector() const
Return true if this is a vector value type.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
This structure contains all information that is necessary for lowering calls.