LLVM 18.0.0git
HexagonISelLowering.h
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1//===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that Hexagon uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
15#define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
16
17#include "Hexagon.h"
19#include "llvm/ADT/StringRef.h"
25#include "llvm/IR/CallingConv.h"
26#include "llvm/IR/InlineAsm.h"
27#include <cstdint>
28#include <utility>
29
30namespace llvm {
31
32namespace HexagonISD {
33
34enum NodeType : unsigned {
36
38 CONST32_GP, // For marking data present in GP.
39 ADDC, // Add with carry: (X, Y, Cin) -> (X+Y, Cout).
40 SUBC, // Sub with carry: (X, Y, Cin) -> (X+~Y+Cin, Cout).
42
43 AT_GOT, // Index in GOT.
44 AT_PCREL, // Offset relative to PC.
45
46 CALL, // Function call.
47 CALLnr, // Function call that does not return.
49
50 RET_GLUE, // Return with a glue operand.
51 BARRIER, // Memory barrier.
52 JT, // Jump table.
53 CP, // Constant pool.
54
56 VASL, // Vector shifts by a scalar value
59 MFSHL, // Funnel shifts with the shift amount guaranteed to be
60 MFSHR, // within the range of the bit width of the element.
61
62 SSAT, // Signed saturate.
63 USAT, // Unsigned saturate.
64 SMUL_LOHI, // Same as ISD::SMUL_LOHI, but opaque to the combiner.
65 UMUL_LOHI, // Same as ISD::UMUL_LOHI, but opaque to the combiner.
66 // We want to legalize MULH[SU] to [SU]MUL_LOHI, but the
67 // combiner will keep rewriting it back to MULH[SU].
68 USMUL_LOHI, // Like SMUL_LOHI, but unsigned*signed.
69
82 D2P, // Convert 8-byte value to 8-bit predicate register. [*]
83 P2D, // Convert 8-bit predicate register to 8-byte value. [*]
84 V2Q, // Convert HVX vector to a vector predicate reg. [*]
85 Q2V, // Convert vector predicate to an HVX vector. [*]
86 // [*] The equivalence is defined as "Q <=> (V != 0)",
87 // where the != operation compares bytes.
88 // Note: V != 0 is implemented as V >u 0.
92
93 TL_EXTEND, // Wrappers for ISD::*_EXTEND and ISD::TRUNCATE to prevent DAG
94 TL_TRUNCATE, // from auto-folding operations, e.g.
95 // (i32 ext (i16 ext i8)) would be folded to (i32 ext i8).
96 // To simplify the type legalization, we want to keep these
97 // single steps separate during type legalization.
98 // TL_[EXTEND|TRUNCATE] Inp, i128 _, i32 Opc
99 // * Inp is the original input to extend/truncate,
100 // * _ is a dummy operand with an illegal type (can be undef),
101 // * Opc is the original opcode.
102 // The legalization process (in Hexagon lowering code) will
103 // first deal with the "real" types (i.e. Inp and the result),
104 // and once all of them are processed, the wrapper node will
105 // be replaced with the original ISD node. The dummy illegal
106 // operand is there to make sure that the legalization hooks
107 // are called again after everything else is legal, giving
108 // us the opportunity to undo the wrapping.
109
110 TYPECAST, // No-op that's used to convert between different legal
111 // types in a register.
112 VALIGN, // Align two vectors (in Op0, Op1) to one that would have
113 // been loaded from address in Op2.
114 VALIGNADDR, // Align vector address: Op0 & -Op1, except when it is
115 // an address in a vector load, then it's a no-op.
116 ISEL, // Marker for nodes that were created during ISel, and
117 // which need explicit selection (would have been left
118 // unselected otherwise).
119 OP_END
121
122} // end namespace HexagonISD
123
124class HexagonSubtarget;
125
127 int VarArgsFrameOffset; // Frame offset to start of varargs area.
128 const HexagonTargetMachine &HTM;
129 const HexagonSubtarget &Subtarget;
130
131public:
132 explicit HexagonTargetLowering(const TargetMachine &TM,
133 const HexagonSubtarget &ST);
134
135 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
136 /// for tail call optimization. Targets which want to do tail call
137 /// optimization should implement this function.
139 CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet,
140 bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs,
141 const SmallVectorImpl<SDValue> &OutVals,
142 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const;
143
145 MachineFunction &MF,
146 unsigned Intrinsic) const override;
147
148 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
149 bool isTruncateFree(EVT VT1, EVT VT2) const override;
150
151 bool isCheapToSpeculateCttz(Type *) const override { return true; }
152 bool isCheapToSpeculateCtlz(Type *) const override { return true; }
153 bool isCtlzFast() const override { return true; }
154
155 bool hasBitTest(SDValue X, SDValue Y) const override;
156
157 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
158
159 /// Return true if an FMA operation is faster than a pair of mul and add
160 /// instructions. fmuladd intrinsics will be expanded to FMAs when this
161 /// method returns true (and FMAs are legal), otherwise fmuladd is
162 /// expanded to mul + add.
164 EVT) const override;
165
166 // Should we expand the build vector with shuffles?
168 unsigned DefinedValues) const override;
169 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
170 unsigned Index) const override;
171
172 bool isTargetCanonicalConstantNode(SDValue Op) const override;
173
174 bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
177
178 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
180 SelectionDAG &DAG) const override;
182 SelectionDAG &DAG) const override;
183
184 const char *getTargetNodeName(unsigned Opcode) const override;
185
204
211 SDValue
212 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
214 const SDLoc &dl, SelectionDAG &DAG,
215 SmallVectorImpl<SDValue> &InVals) const override;
220 SelectionDAG &DAG) const;
222 SelectionDAG &DAG) const;
224 SelectionDAG &DAG) const;
226 GlobalAddressSDNode *GA, SDValue InGlue, EVT PtrVT,
227 unsigned ReturnReg, unsigned char OperandGlues) const;
229
231 SmallVectorImpl<SDValue> &InVals) const override;
233 CallingConv::ID CallConv, bool isVarArg,
235 const SDLoc &dl, SelectionDAG &DAG,
237 const SmallVectorImpl<SDValue> &OutVals,
238 SDValue Callee) const;
239
245
246 bool CanLowerReturn(CallingConv::ID CallConv,
247 MachineFunction &MF, bool isVarArg,
249 LLVMContext &Context) const override;
250
251 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
253 const SmallVectorImpl<SDValue> &OutVals,
254 const SDLoc &dl, SelectionDAG &DAG) const override;
255
256 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
257
258 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
259
260 Register getRegisterByName(const char* RegName, LLT VT,
261 const MachineFunction &MF) const override;
262
263 /// If a physical register, this returns the register that receives the
264 /// exception address on entry to an EH pad.
266 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
267 return Hexagon::R0;
268 }
269
270 /// If a physical register, this returns the register that receives the
271 /// exception typeid on entry to a landing pad.
273 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
274 return Hexagon::R1;
275 }
276
281
283 EVT VT) const override {
284 if (!VT.isVector())
285 return MVT::i1;
286 else
287 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
288 }
289
293 SelectionDAG &DAG) const override;
294
295 ConstraintType getConstraintType(StringRef Constraint) const override;
296
297 std::pair<unsigned, const TargetRegisterClass *>
299 StringRef Constraint, MVT VT) const override;
300
301 // Intrinsics
304 /// isLegalAddressingMode - Return true if the addressing mode represented
305 /// by AM is legal for this target, for a load/store of the specified type.
306 /// The type may be VoidTy, in which case only return true if the addressing
307 /// mode is legal for a load/store of any legal type.
308 /// TODO: Handle pre/postinc as well.
309 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
310 Type *Ty, unsigned AS,
311 Instruction *I = nullptr) const override;
312 /// Return true if folding a constant offset with the given GlobalAddress
313 /// is legal. It is frequently not legal in PIC relocation models.
314 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
315
316 bool isFPImmLegal(const APFloat &Imm, EVT VT,
317 bool ForCodeSize) const override;
318
319 /// isLegalICmpImmediate - Return true if the specified immediate is legal
320 /// icmp immediate, that is the target has icmp instructions which can
321 /// compare a register against the immediate without having to materialize
322 /// the immediate into a register.
323 bool isLegalICmpImmediate(int64_t Imm) const override;
324
326 const AttributeList &FuncAttributes) const override;
327
328 bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
329 unsigned AddrSpace, Align Alignment,
331 unsigned *Fast) const override;
332
333 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
334 Align Alignment,
336 unsigned *Fast) const override;
337
338 /// Returns relocation base for the given PIC jumptable.
340 const override;
341
343 EVT NewVT) const override;
344
346 SDNode *Node) const override;
347
348 // Handling of atomic RMW instructions.
349 Value *emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr,
350 AtomicOrdering Ord) const override;
352 AtomicOrdering Ord) const override;
357
361 }
362
363private:
364 void initializeHVXLowering();
365 unsigned getPreferredHvxVectorAction(MVT VecTy) const;
366 unsigned getCustomHvxOperationAction(SDNode &Op) const;
367
368 bool validateConstPtrAlignment(SDValue Ptr, Align NeedAlign, const SDLoc &dl,
369 SelectionDAG &DAG) const;
370 SDValue replaceMemWithUndef(SDValue Op, SelectionDAG &DAG) const;
371
372 std::pair<SDValue,int> getBaseAndOffset(SDValue Addr) const;
373
374 bool getBuildVectorConstInts(ArrayRef<SDValue> Values, MVT VecTy,
375 SelectionDAG &DAG,
376 MutableArrayRef<ConstantInt*> Consts) const;
377 SDValue buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy,
378 SelectionDAG &DAG) const;
379 SDValue buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy,
380 SelectionDAG &DAG) const;
381 SDValue extractVector(SDValue VecV, SDValue IdxV, const SDLoc &dl,
382 MVT ValTy, MVT ResTy, SelectionDAG &DAG) const;
383 SDValue extractVectorPred(SDValue VecV, SDValue IdxV, const SDLoc &dl,
384 MVT ValTy, MVT ResTy, SelectionDAG &DAG) const;
385 SDValue insertVector(SDValue VecV, SDValue ValV, SDValue IdxV,
386 const SDLoc &dl, MVT ValTy, SelectionDAG &DAG) const;
387 SDValue insertVectorPred(SDValue VecV, SDValue ValV, SDValue IdxV,
388 const SDLoc &dl, MVT ValTy, SelectionDAG &DAG) const;
389 SDValue expandPredicate(SDValue Vec32, const SDLoc &dl,
390 SelectionDAG &DAG) const;
391 SDValue contractPredicate(SDValue Vec64, const SDLoc &dl,
392 SelectionDAG &DAG) const;
393 SDValue getSplatValue(SDValue Op, SelectionDAG &DAG) const;
394 SDValue getVectorShiftByInt(SDValue Op, SelectionDAG &DAG) const;
395 SDValue appendUndef(SDValue Val, MVT ResTy, SelectionDAG &DAG) const;
396 SDValue getCombine(SDValue Hi, SDValue Lo, const SDLoc &dl, MVT ResTy,
397 SelectionDAG &DAG) const;
398
399 bool isUndef(SDValue Op) const {
400 if (Op.isMachineOpcode())
401 return Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF;
402 return Op.getOpcode() == ISD::UNDEF;
403 }
404 SDValue getInstr(unsigned MachineOpc, const SDLoc &dl, MVT Ty,
405 ArrayRef<SDValue> Ops, SelectionDAG &DAG) const {
406 SDNode *N = DAG.getMachineNode(MachineOpc, dl, Ty, Ops);
407 return SDValue(N, 0);
408 }
409 SDValue getZero(const SDLoc &dl, MVT Ty, SelectionDAG &DAG) const;
410
411 using VectorPair = std::pair<SDValue, SDValue>;
412 using TypePair = std::pair<MVT, MVT>;
413
414 SDValue getInt(unsigned IntId, MVT ResTy, ArrayRef<SDValue> Ops,
415 const SDLoc &dl, SelectionDAG &DAG) const;
416
417 MVT ty(SDValue Op) const {
418 return Op.getValueType().getSimpleVT();
419 }
420 TypePair ty(const VectorPair &Ops) const {
421 return { Ops.first.getValueType().getSimpleVT(),
422 Ops.second.getValueType().getSimpleVT() };
423 }
424 MVT tyScalar(MVT Ty) const {
425 if (!Ty.isVector())
426 return Ty;
427 return MVT::getIntegerVT(Ty.getSizeInBits());
428 }
429 MVT tyVector(MVT Ty, MVT ElemTy) const {
430 if (Ty.isVector() && Ty.getVectorElementType() == ElemTy)
431 return Ty;
432 unsigned TyWidth = Ty.getSizeInBits();
433 unsigned ElemWidth = ElemTy.getSizeInBits();
434 assert((TyWidth % ElemWidth) == 0);
435 return MVT::getVectorVT(ElemTy, TyWidth/ElemWidth);
436 }
437
438 MVT typeJoin(const TypePair &Tys) const;
439 TypePair typeSplit(MVT Ty) const;
440 MVT typeExtElem(MVT VecTy, unsigned Factor) const;
441 MVT typeTruncElem(MVT VecTy, unsigned Factor) const;
442 TypePair typeExtendToWider(MVT Ty0, MVT Ty1) const;
443 TypePair typeWidenToWider(MVT Ty0, MVT Ty1) const;
444 MVT typeLegalize(MVT Ty, SelectionDAG &DAG) const;
445 MVT typeWidenToHvx(MVT Ty) const;
446
447 SDValue opJoin(const VectorPair &Ops, const SDLoc &dl,
448 SelectionDAG &DAG) const;
449 VectorPair opSplit(SDValue Vec, const SDLoc &dl, SelectionDAG &DAG) const;
450 SDValue opCastElem(SDValue Vec, MVT ElemTy, SelectionDAG &DAG) const;
451
452 SDValue LoHalf(SDValue V, SelectionDAG &DAG) const {
453 MVT Ty = ty(V);
454 const SDLoc &dl(V);
455 if (!Ty.isVector()) {
456 assert(Ty.getSizeInBits() == 64);
457 return DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, V);
458 }
459 MVT HalfTy = typeSplit(Ty).first;
460 SDValue Idx = getZero(dl, MVT::i32, DAG);
461 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfTy, V, Idx);
462 }
463 SDValue HiHalf(SDValue V, SelectionDAG &DAG) const {
464 MVT Ty = ty(V);
465 const SDLoc &dl(V);
466 if (!Ty.isVector()) {
467 assert(Ty.getSizeInBits() == 64);
468 return DAG.getTargetExtractSubreg(Hexagon::isub_hi, dl, MVT::i32, V);
469 }
470 MVT HalfTy = typeSplit(Ty).first;
471 SDValue Idx = DAG.getConstant(HalfTy.getVectorNumElements(), dl, MVT::i32);
472 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfTy, V, Idx);
473 }
474
475 bool allowsHvxMemoryAccess(MVT VecTy, MachineMemOperand::Flags Flags,
476 unsigned *Fast) const;
477 bool allowsHvxMisalignedMemoryAccesses(MVT VecTy,
479 unsigned *Fast) const;
480 void AdjustHvxInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const;
481
482 bool isHvxSingleTy(MVT Ty) const;
483 bool isHvxPairTy(MVT Ty) const;
484 bool isHvxBoolTy(MVT Ty) const;
485 SDValue convertToByteIndex(SDValue ElemIdx, MVT ElemTy,
486 SelectionDAG &DAG) const;
487 SDValue getIndexInWord32(SDValue Idx, MVT ElemTy, SelectionDAG &DAG) const;
488 SDValue getByteShuffle(const SDLoc &dl, SDValue Op0, SDValue Op1,
489 ArrayRef<int> Mask, SelectionDAG &DAG) const;
490
491 SDValue buildHvxVectorReg(ArrayRef<SDValue> Values, const SDLoc &dl,
492 MVT VecTy, SelectionDAG &DAG) const;
493 SDValue buildHvxVectorPred(ArrayRef<SDValue> Values, const SDLoc &dl,
494 MVT VecTy, SelectionDAG &DAG) const;
495 SDValue createHvxPrefixPred(SDValue PredV, const SDLoc &dl,
496 unsigned BitBytes, bool ZeroFill,
497 SelectionDAG &DAG) const;
498 SDValue extractHvxElementReg(SDValue VecV, SDValue IdxV, const SDLoc &dl,
499 MVT ResTy, SelectionDAG &DAG) const;
500 SDValue extractHvxElementPred(SDValue VecV, SDValue IdxV, const SDLoc &dl,
501 MVT ResTy, SelectionDAG &DAG) const;
502 SDValue insertHvxElementReg(SDValue VecV, SDValue IdxV, SDValue ValV,
503 const SDLoc &dl, SelectionDAG &DAG) const;
504 SDValue insertHvxElementPred(SDValue VecV, SDValue IdxV, SDValue ValV,
505 const SDLoc &dl, SelectionDAG &DAG) const;
506 SDValue extractHvxSubvectorReg(SDValue OrigOp, SDValue VecV, SDValue IdxV,
507 const SDLoc &dl, MVT ResTy, SelectionDAG &DAG)
508 const;
509 SDValue extractHvxSubvectorPred(SDValue VecV, SDValue IdxV, const SDLoc &dl,
510 MVT ResTy, SelectionDAG &DAG) const;
511 SDValue insertHvxSubvectorReg(SDValue VecV, SDValue SubV, SDValue IdxV,
512 const SDLoc &dl, SelectionDAG &DAG) const;
513 SDValue insertHvxSubvectorPred(SDValue VecV, SDValue SubV, SDValue IdxV,
514 const SDLoc &dl, SelectionDAG &DAG) const;
515 SDValue extendHvxVectorPred(SDValue VecV, const SDLoc &dl, MVT ResTy,
516 bool ZeroExt, SelectionDAG &DAG) const;
517 SDValue compressHvxPred(SDValue VecQ, const SDLoc &dl, MVT ResTy,
518 SelectionDAG &DAG) const;
519 SDValue resizeToWidth(SDValue VecV, MVT ResTy, bool Signed, const SDLoc &dl,
520 SelectionDAG &DAG) const;
521 SDValue extractSubvector(SDValue Vec, MVT SubTy, unsigned SubIdx,
522 SelectionDAG &DAG) const;
523 VectorPair emitHvxAddWithOverflow(SDValue A, SDValue B, const SDLoc &dl,
524 bool Signed, SelectionDAG &DAG) const;
525 VectorPair emitHvxShiftRightRnd(SDValue Val, unsigned Amt, bool Signed,
526 SelectionDAG &DAG) const;
527 SDValue emitHvxMulHsV60(SDValue A, SDValue B, const SDLoc &dl,
528 SelectionDAG &DAG) const;
529 SDValue emitHvxMulLoHiV60(SDValue A, bool SignedA, SDValue B, bool SignedB,
530 const SDLoc &dl, SelectionDAG &DAG) const;
531 SDValue emitHvxMulLoHiV62(SDValue A, bool SignedA, SDValue B, bool SignedB,
532 const SDLoc &dl, SelectionDAG &DAG) const;
533
534 SDValue LowerHvxBuildVector(SDValue Op, SelectionDAG &DAG) const;
535 SDValue LowerHvxSplatVector(SDValue Op, SelectionDAG &DAG) const;
536 SDValue LowerHvxConcatVectors(SDValue Op, SelectionDAG &DAG) const;
537 SDValue LowerHvxExtractElement(SDValue Op, SelectionDAG &DAG) const;
538 SDValue LowerHvxInsertElement(SDValue Op, SelectionDAG &DAG) const;
539 SDValue LowerHvxExtractSubvector(SDValue Op, SelectionDAG &DAG) const;
540 SDValue LowerHvxInsertSubvector(SDValue Op, SelectionDAG &DAG) const;
541 SDValue LowerHvxBitcast(SDValue Op, SelectionDAG &DAG) const;
542 SDValue LowerHvxAnyExt(SDValue Op, SelectionDAG &DAG) const;
543 SDValue LowerHvxSignExt(SDValue Op, SelectionDAG &DAG) const;
544 SDValue LowerHvxZeroExt(SDValue Op, SelectionDAG &DAG) const;
545 SDValue LowerHvxCttz(SDValue Op, SelectionDAG &DAG) const;
546 SDValue LowerHvxMulh(SDValue Op, SelectionDAG &DAG) const;
547 SDValue LowerHvxMulLoHi(SDValue Op, SelectionDAG &DAG) const;
548 SDValue LowerHvxExtend(SDValue Op, SelectionDAG &DAG) const;
549 SDValue LowerHvxSelect(SDValue Op, SelectionDAG &DAG) const;
550 SDValue LowerHvxShift(SDValue Op, SelectionDAG &DAG) const;
551 SDValue LowerHvxFunnelShift(SDValue Op, SelectionDAG &DAG) const;
552 SDValue LowerHvxIntrinsic(SDValue Op, SelectionDAG &DAG) const;
553 SDValue LowerHvxMaskedOp(SDValue Op, SelectionDAG &DAG) const;
554 SDValue LowerHvxFpExtend(SDValue Op, SelectionDAG &DAG) const;
555 SDValue LowerHvxFpToInt(SDValue Op, SelectionDAG &DAG) const;
556 SDValue LowerHvxIntToFp(SDValue Op, SelectionDAG &DAG) const;
557 SDValue ExpandHvxFpToInt(SDValue Op, SelectionDAG &DAG) const;
558 SDValue ExpandHvxIntToFp(SDValue Op, SelectionDAG &DAG) const;
559
560 VectorPair SplitVectorOp(SDValue Op, SelectionDAG &DAG) const;
561
562 SDValue SplitHvxMemOp(SDValue Op, SelectionDAG &DAG) const;
563 SDValue WidenHvxLoad(SDValue Op, SelectionDAG &DAG) const;
564 SDValue WidenHvxStore(SDValue Op, SelectionDAG &DAG) const;
565 SDValue WidenHvxSetCC(SDValue Op, SelectionDAG &DAG) const;
566 SDValue LegalizeHvxResize(SDValue Op, SelectionDAG &DAG) const;
567 SDValue ExpandHvxResizeIntoSteps(SDValue Op, SelectionDAG &DAG) const;
568 SDValue EqualizeFpIntConversion(SDValue Op, SelectionDAG &DAG) const;
569
570 SDValue CreateTLWrapper(SDValue Op, SelectionDAG &DAG) const;
571 SDValue RemoveTLWrapper(SDValue Op, SelectionDAG &DAG) const;
572
573 std::pair<const TargetRegisterClass*, uint8_t>
574 findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT)
575 const override;
576
577 bool shouldSplitToHvx(MVT Ty, SelectionDAG &DAG) const;
578 bool shouldWidenToHvx(MVT Ty, SelectionDAG &DAG) const;
579 bool isHvxOperation(SDNode *N, SelectionDAG &DAG) const;
580 SDValue LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const;
581 void LowerHvxOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,
582 SelectionDAG &DAG) const;
583 void ReplaceHvxNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
584 SelectionDAG &DAG) const;
585
586 SDValue combineTruncateBeforeLegal(SDValue Op, DAGCombinerInfo &DCI) const;
587 SDValue combineConcatVectorsBeforeLegal(SDValue Op, DAGCombinerInfo & DCI)
588 const;
589 SDValue combineVectorShuffleBeforeLegal(SDValue Op, DAGCombinerInfo & DCI)
590 const;
591
592 SDValue PerformHvxDAGCombine(SDNode * N, DAGCombinerInfo & DCI) const;
593};
594
595} // end namespace llvm
596
597#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
uint64_t Addr
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
IRTranslator LLVM IR MI
#define RegName(no)
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file describes how to lower LLVM code to machine code.
static constexpr uint32_t Opcode
Definition: aarch32.h:200
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:521
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:726
This class represents a function call, abstracting a target machine's calling convention.
This is an important base class in LLVM.
Definition: Constant.h:41
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const
SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
bool isCtlzFast() const override
Return true if ctlz instruction is fast.
SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
bool isTargetCanonicalConstantNode(SDValue Op) const override
Returns true if the given Opc is considered a canonical constant for the target, which should not be ...
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const
SDValue LowerUAddSubO(SDValue Op, SelectionDAG &DAG) const
SDValue LowerANY_EXTEND(SDValue Op, SelectionDAG &DAG) const
Value * emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate,...
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const
AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.
SDValue GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, SDValue InGlue, EVT PtrVT, unsigned ReturnReg, unsigned char OperandGlues) const
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
SDValue LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG) const
SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const
SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const
bool isCheapToSpeculateCtlz(Type *) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively.
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
bool isCheapToSpeculateCttz(Type *) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
SDValue LowerCallResult(SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, const SmallVectorImpl< SDValue > &OutVals, SDValue Callee) const
LowerCallResult - Lower the result values of an ISD::CALL into the appropriate copies out of appropri...
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
SDValue LowerToTLSInitialExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const override
Return true if the target supports a memory access of this type for the given address space and align...
SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
SDValue LowerLoad(SDValue Op, SelectionDAG &DAG) const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
bool isShuffleMaskLegal(ArrayRef< int > Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations,...
LegalizeAction getCustomOperationAction(SDNode &Op) const override
How to legalize this custom operation?
SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
SDValue LowerUAddSubOCarry(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
LowerCall - Functions arguments are copied from virtual regs to (physical regs)/(stack frame),...
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const override
Determine if the target supports unaligned memory accesses.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
SDValue LowerStore(SDValue Op, SelectionDAG &DAG) const
SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const
SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
EVT getSetCCResultType(const DataLayout &, LLVMContext &C, EVT VT) const override
Return the ValueType of the result of SETCC operations.
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Value * emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization.
SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const
void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const
SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &, EVT) const override
Return true if an FMA operation is faster than a pair of mul and add instructions.
SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const
LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT) const override
Return true if it is profitable to reduce a load to a smaller type.
SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:94
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
An instruction for reading from memory.
Definition: Instructions.h:177
Machine Value Type.
static MVT getVectorVT(MVT VT, unsigned NumElements)
static MVT getIntegerVT(unsigned BitWidth)
Representation of each machine instruction.
Definition: MachineInstr.h:68
Flags
Flags values. These may be or'd together.
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:307
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
An instruction for storing to memory.
Definition: Instructions.h:301
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1383
@ UNDEF
UNDEF - An undefined node.
Definition: ISDOpcodes.h:211
@ EXTRACT_SUBVECTOR
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
Definition: ISDOpcodes.h:573
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1455
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:1486
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
AtomicOrdering
Atomic ordering for LLVM's memory model.
DWARFExpression::Operation Op
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
Definition: ValueTypes.h:73
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:160
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:319
This structure contains all information that is necessary for lowering calls.