18 using namespace dwarf;
22 typedef std::vector<DWARFExpression::Operation::Description>
DescVector;
27 typedef Op::Description Desc;
29 Descriptions.resize(0xff);
30 Descriptions[DW_OP_addr] = Desc(Op::Dwarf2, Op::SizeAddr);
31 Descriptions[DW_OP_deref] = Desc(Op::Dwarf2);
32 Descriptions[DW_OP_const1u] = Desc(Op::Dwarf2, Op::Size1);
33 Descriptions[DW_OP_const1s] = Desc(Op::Dwarf2, Op::SignedSize1);
34 Descriptions[DW_OP_const2u] = Desc(Op::Dwarf2, Op::Size2);
35 Descriptions[DW_OP_const2s] = Desc(Op::Dwarf2, Op::SignedSize2);
36 Descriptions[DW_OP_const4u] = Desc(Op::Dwarf2, Op::Size4);
37 Descriptions[DW_OP_const4s] = Desc(Op::Dwarf2, Op::SignedSize4);
38 Descriptions[DW_OP_const8u] = Desc(Op::Dwarf2, Op::Size8);
39 Descriptions[DW_OP_const8s] = Desc(Op::Dwarf2, Op::SignedSize8);
40 Descriptions[DW_OP_constu] = Desc(Op::Dwarf2, Op::SizeLEB);
41 Descriptions[DW_OP_consts] = Desc(Op::Dwarf2, Op::SignedSizeLEB);
42 Descriptions[DW_OP_dup] = Desc(Op::Dwarf2);
43 Descriptions[DW_OP_drop] = Desc(Op::Dwarf2);
44 Descriptions[DW_OP_over] = Desc(Op::Dwarf2);
45 Descriptions[DW_OP_pick] = Desc(Op::Dwarf2, Op::Size1);
46 Descriptions[DW_OP_swap] = Desc(Op::Dwarf2);
47 Descriptions[DW_OP_rot] = Desc(Op::Dwarf2);
48 Descriptions[DW_OP_xderef] = Desc(Op::Dwarf2);
49 Descriptions[DW_OP_abs] = Desc(Op::Dwarf2);
50 Descriptions[DW_OP_and] = Desc(Op::Dwarf2);
51 Descriptions[DW_OP_div] = Desc(Op::Dwarf2);
52 Descriptions[DW_OP_minus] = Desc(Op::Dwarf2);
53 Descriptions[DW_OP_mod] = Desc(Op::Dwarf2);
54 Descriptions[DW_OP_mul] = Desc(Op::Dwarf2);
55 Descriptions[DW_OP_neg] = Desc(Op::Dwarf2);
56 Descriptions[DW_OP_not] = Desc(Op::Dwarf2);
57 Descriptions[DW_OP_or] = Desc(Op::Dwarf2);
58 Descriptions[DW_OP_plus] = Desc(Op::Dwarf2);
59 Descriptions[DW_OP_plus_uconst] = Desc(Op::Dwarf2, Op::SizeLEB);
60 Descriptions[DW_OP_shl] = Desc(Op::Dwarf2);
61 Descriptions[DW_OP_shr] = Desc(Op::Dwarf2);
62 Descriptions[DW_OP_shra] = Desc(Op::Dwarf2);
63 Descriptions[DW_OP_xor] = Desc(Op::Dwarf2);
64 Descriptions[DW_OP_skip] = Desc(Op::Dwarf2, Op::SignedSize2);
65 Descriptions[DW_OP_bra] = Desc(Op::Dwarf2, Op::SignedSize2);
66 Descriptions[DW_OP_eq] = Desc(Op::Dwarf2);
67 Descriptions[DW_OP_ge] = Desc(Op::Dwarf2);
68 Descriptions[DW_OP_gt] = Desc(Op::Dwarf2);
69 Descriptions[DW_OP_le] = Desc(Op::Dwarf2);
70 Descriptions[DW_OP_lt] = Desc(Op::Dwarf2);
71 Descriptions[DW_OP_ne] = Desc(Op::Dwarf2);
73 Descriptions[
LA] = Desc(Op::Dwarf2);
75 Descriptions[
LA] = Desc(Op::Dwarf2);
77 Descriptions[
LA] = Desc(Op::Dwarf2, Op::SignedSizeLEB);
78 Descriptions[DW_OP_regx] = Desc(Op::Dwarf2, Op::SizeLEB);
79 Descriptions[DW_OP_fbreg] = Desc(Op::Dwarf2, Op::SignedSizeLEB);
80 Descriptions[DW_OP_bregx] = Desc(Op::Dwarf2, Op::SizeLEB, Op::SignedSizeLEB);
81 Descriptions[DW_OP_piece] = Desc(Op::Dwarf2, Op::SizeLEB);
82 Descriptions[DW_OP_deref_size] = Desc(Op::Dwarf2, Op::Size1);
83 Descriptions[DW_OP_xderef_size] = Desc(Op::Dwarf2, Op::Size1);
84 Descriptions[DW_OP_nop] = Desc(Op::Dwarf2);
85 Descriptions[DW_OP_push_object_address] = Desc(Op::Dwarf3);
86 Descriptions[DW_OP_call2] = Desc(Op::Dwarf3, Op::Size2);
87 Descriptions[DW_OP_call4] = Desc(Op::Dwarf3, Op::Size4);
88 Descriptions[DW_OP_call_ref] = Desc(Op::Dwarf3, Op::SizeRefAddr);
89 Descriptions[DW_OP_form_tls_address] = Desc(Op::Dwarf3);
90 Descriptions[DW_OP_call_frame_cfa] = Desc(Op::Dwarf3);
91 Descriptions[DW_OP_bit_piece] = Desc(Op::Dwarf3, Op::SizeLEB, Op::SizeLEB);
92 Descriptions[DW_OP_implicit_value] =
93 Desc(Op::Dwarf3, Op::SizeLEB, Op::SizeBlock);
94 Descriptions[DW_OP_stack_value] = Desc(Op::Dwarf3);
95 Descriptions[DW_OP_WASM_location] =
96 Desc(Op::Dwarf4, Op::SizeLEB, Op::WasmLocationArg);
97 Descriptions[DW_OP_GNU_push_tls_address] = Desc(Op::Dwarf3);
98 Descriptions[DW_OP_addrx] = Desc(Op::Dwarf4, Op::SizeLEB);
99 Descriptions[DW_OP_GNU_addr_index] = Desc(Op::Dwarf4, Op::SizeLEB);
100 Descriptions[DW_OP_GNU_const_index] = Desc(Op::Dwarf4, Op::SizeLEB);
101 Descriptions[DW_OP_GNU_entry_value] = Desc(Op::Dwarf4, Op::SizeLEB);
103 Descriptions[DW_OP_convert] = Desc(Op::Dwarf5, Op::BaseTypeRef);
104 Descriptions[DW_OP_entry_value] = Desc(Op::Dwarf5, Op::SizeLEB);
105 Descriptions[DW_OP_regval_type] =
106 Desc(Op::Dwarf5, Op::SizeLEB, Op::BaseTypeRef);
115 if (OpCode >= Descriptions.size())
117 return Descriptions[OpCode];
121 uint8_t AddressSize,
uint64_t Offset,
124 Opcode =
Data.getU8(&Offset);
127 if (Desc.Version == Operation::DwarfNA)
130 for (
unsigned Operand = 0; Operand < 2; ++Operand) {
131 unsigned Size = Desc.Op[Operand];
132 unsigned Signed = Size & Operation::SignBit;
134 if (Size == Operation::SizeNA)
137 switch (Size & ~Operation::SignBit) {
138 case Operation::Size1:
143 case Operation::Size2:
148 case Operation::Size4:
153 case Operation::Size8:
156 case Operation::SizeAddr:
157 Operands[Operand] =
Data.getUnsigned(&Offset, AddressSize);
159 case Operation::SizeRefAddr:
165 case Operation::SizeLEB:
171 case Operation::BaseTypeRef:
174 case Operation::WasmLocationArg:
190 case Operation::SizeBlock:
202 OperandEndOffsets[Operand] =
Offset;
213 assert(Operand < 2 &&
"operand out of bounds");
215 if (Die && Die.getTag() == dwarf::DW_TAG_base_type) {
221 OS <<
" \"" << *
Name <<
"\"";
223 OS <<
format(
" <invalid base_type ref: 0x%" PRIx64
">",
238 if (Opcode == DW_OP_bregx || Opcode == DW_OP_regx ||
239 Opcode == DW_OP_regval_type)
241 else if (Opcode >= DW_OP_breg0 && Opcode < DW_OP_bregx)
242 DwarfRegNum = Opcode - DW_OP_breg0;
244 DwarfRegNum = Opcode - DW_OP_reg0;
247 if (
const char *
RegName =
MRI->getName(*LLVMRegNum)) {
248 if ((Opcode >= DW_OP_breg0 && Opcode <= DW_OP_breg31) ||
249 Opcode == DW_OP_bregx)
254 if (Opcode == DW_OP_regval_type)
268 OS <<
"<decoding error>";
273 assert(!
Name.empty() &&
"DW_OP has no name!");
276 if ((Opcode >= DW_OP_breg0 && Opcode <= DW_OP_breg31) ||
277 (Opcode >= DW_OP_reg0 && Opcode <= DW_OP_reg31) ||
278 Opcode == DW_OP_bregx || Opcode == DW_OP_regx ||
279 Opcode == DW_OP_regval_type)
283 for (
unsigned Operand = 0; Operand < 2; ++Operand) {
284 unsigned Size = Desc.Op[Operand];
285 unsigned Signed = Size & Operation::SignBit;
287 if (Size == Operation::SizeNA)
290 if (Size == Operation::BaseTypeRef && U) {
294 if (Opcode == DW_OP_convert &&
Operands[Operand] == 0)
298 }
else if (Size == Operation::WasmLocationArg) {
310 }
else if (Size == Operation::SizeBlock) {
312 for (
unsigned i = 0;
i <
Operands[Operand - 1]; ++
i)
313 OS <<
format(
" 0x%02x", Expr->Data.
getU8(&Offset));
317 else if (Opcode != DW_OP_entry_value &&
318 Opcode != DW_OP_GNU_entry_value)
330 if (
Data.getData().empty())
333 for (
auto &
Op : *
this) {
334 if (!
Op.print(OS, DumpOpts,
this, RegInfo, U, IsEH)) {
336 while (FailOffset <
Data.getData().size())
337 OS <<
format(
" %02x",
Data.getU8(&FailOffset));
341 if (
Op.getCode() == DW_OP_entry_value ||
342 Op.getCode() == DW_OP_GNU_entry_value) {
344 EntryValExprSize =
Op.getRawOperand(0);
345 EntryValStartOffset =
Op.getEndOffset();
349 if (EntryValExprSize) {
350 EntryValExprSize -=
Op.getEndOffset() - EntryValStartOffset;
351 if (EntryValExprSize == 0)
355 if (
Op.getEndOffset() <
Data.getData().size())
361 for (
unsigned Operand = 0; Operand < 2; ++Operand) {
362 unsigned Size =
Op.Desc.Op[Operand];
364 if (Size == Operation::SizeNA)
367 if (Size == Operation::BaseTypeRef) {
372 if (
Op.Opcode == DW_OP_convert &&
Op.Operands[Operand] == 0)
375 if (!Die || Die.getTag() != dwarf::DW_TAG_base_type)
384 for (
auto &
Op : *
this)
412 uint8_t Opcode =
Op.getCode();
414 case dwarf::DW_OP_regx: {
420 OS <<
"<unknown register " << DwarfRegNum <<
">";
424 S <<
MRI.getName(*LLVMRegNum);
427 case dwarf::DW_OP_bregx: {
428 int DwarfRegNum =
Op.getRawOperand(0);
429 int64_t Offset =
Op.getRawOperand(1);
432 OS <<
"<unknown register " << DwarfRegNum <<
">";
436 S <<
MRI.getName(*LLVMRegNum);
438 S <<
format(
"%+" PRId64, Offset);
441 case dwarf::DW_OP_entry_value:
442 case dwarf::DW_OP_GNU_entry_value: {
455 case dwarf::DW_OP_stack_value: {
463 if (Opcode >= dwarf::DW_OP_reg0 && Opcode <= dwarf::DW_OP_reg31) {
466 uint64_t DwarfRegNum = Opcode - dwarf::DW_OP_reg0;
469 OS <<
"<unknown register " << DwarfRegNum <<
">";
473 S <<
MRI.getName(*LLVMRegNum);
474 }
else if (Opcode >= dwarf::DW_OP_breg0 &&
475 Opcode <= dwarf::DW_OP_breg31) {
476 int DwarfRegNum = Opcode - dwarf::DW_OP_breg0;
477 int64_t Offset =
Op.getRawOperand(0);
480 OS <<
"<unknown register " << DwarfRegNum <<
">";
484 S <<
MRI.getName(*LLVMRegNum);
486 S <<
format(
"%+" PRId64, Offset);
491 << (
int)Opcode <<
")>";
499 assert(Stack.size() == 1 &&
"expected one value on stack");
502 OS <<
"[" << Stack.front().String <<
"]";
504 OS << Stack.front().String;
514 if (AddressSize !=
RHS.AddressSize || Format !=
RHS.Format)
516 return Data.getData() ==
RHS.Data.getData();