LLVM 22.0.0git
ISDOpcodes.h
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1//===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares codegen opcodes and related utilities.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_ISDOPCODES_H
14#define LLVM_CODEGEN_ISDOPCODES_H
15
18
19namespace llvm {
20
21/// ISD namespace - This namespace contains an enum which represents all of the
22/// SelectionDAG node types and value types.
23///
24namespace ISD {
25
26//===--------------------------------------------------------------------===//
27/// ISD::NodeType enum - This enum defines the target-independent operators
28/// for a SelectionDAG.
29///
30/// Targets may also define target-dependent operator codes for SDNodes. For
31/// example, on x86, these are the enum values in the X86ISD namespace.
32/// Targets should aim to use target-independent operators to model their
33/// instruction sets as much as possible, and only use target-dependent
34/// operators when they have special requirements.
35///
36/// Finally, during and after selection proper, SNodes may use special
37/// operator codes that correspond directly with MachineInstr opcodes. These
38/// are used to represent selected instructions. See the isMachineOpcode()
39/// and getMachineOpcode() member functions of SDNode.
40///
42
43 /// DELETED_NODE - This is an illegal value that is used to catch
44 /// errors. This opcode is not a legal opcode for any node.
46
47 /// EntryToken - This is the marker used to indicate the start of a region.
49
50 /// TokenFactor - This node takes multiple tokens as input and produces a
51 /// single token result. This is used to represent the fact that the operand
52 /// operators are independent of each other.
54
55 /// AssertSext, AssertZext - These nodes record if a register contains a
56 /// value that has already been zero or sign extended from a narrower type.
57 /// These nodes take two operands. The first is the node that has already
58 /// been extended, and the second is a value type node indicating the width
59 /// of the extension.
60 /// NOTE: In case of the source value (or any vector element value) is
61 /// poisoned the assertion will not be true for that value.
64
65 /// AssertAlign - These nodes record if a register contains a value that
66 /// has a known alignment and the trailing bits are known to be zero.
67 /// NOTE: In case of the source value (or any vector element value) is
68 /// poisoned the assertion will not be true for that value.
70
71 /// AssertNoFPClass - These nodes record if a register contains a float
72 /// value that is known to be not some type.
73 /// This node takes two operands. The first is the node that is known
74 /// never to be some float types; the second is a constant value with
75 /// the value of FPClassTest (casted to uint32_t).
76 /// NOTE: In case of the source value (or any vector element value) is
77 /// poisoned the assertion will not be true for that value.
79
80 /// Various leaf nodes.
95
96 /// A ptrauth constant.
97 /// ptr, key, addr-disc, disc
98 /// Note that the addr-disc can be a non-constant value, to allow representing
99 /// a constant global address signed using address-diversification, in code.
101
102 /// The address of the GOT
104
105 /// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and
106 /// llvm.returnaddress on the DAG. These nodes take one operand, the index
107 /// of the frame or return address to return. An index of zero corresponds
108 /// to the current function's frame or return address, an index of one to
109 /// the parent's frame or return address, and so on.
112
113 /// ADDROFRETURNADDR - Represents the llvm.addressofreturnaddress intrinsic.
114 /// This node takes no operand, returns a target-specific pointer to the
115 /// place in the stack frame where the return address of the current
116 /// function is stored.
118
119 /// SPONENTRY - Represents the llvm.sponentry intrinsic. Takes no argument
120 /// and returns the stack pointer value at the entry of the current
121 /// function calling this intrinsic.
123
124 /// LOCAL_RECOVER - Represents the llvm.localrecover intrinsic.
125 /// Materializes the offset from the local object pointer of another
126 /// function to a particular local object passed to llvm.localescape. The
127 /// operand is the MCSymbol label used to represent this offset, since
128 /// typically the offset is not known until after code generation of the
129 /// parent.
131
132 /// READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on
133 /// the DAG, which implements the named register global variables extension.
136
137 /// FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to
138 /// first (possible) on-stack argument. This is needed for correct stack
139 /// adjustment during unwind.
141
142 /// EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical
143 /// Frame Address (CFA), generally the value of the stack pointer at the
144 /// call site in the previous frame.
146
147 /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents
148 /// 'eh_return' gcc dwarf builtin, which is used to return from
149 /// exception. The general meaning is: adjust stack by OFFSET and pass
150 /// execution to HANDLER. Many platform-related details also :)
152
153 /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer)
154 /// This corresponds to the eh.sjlj.setjmp intrinsic.
155 /// It takes an input chain and a pointer to the jump buffer as inputs
156 /// and returns an outchain.
158
159 /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer)
160 /// This corresponds to the eh.sjlj.longjmp intrinsic.
161 /// It takes an input chain and a pointer to the jump buffer as inputs
162 /// and returns an outchain.
164
165 /// OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN)
166 /// The target initializes the dispatch table here.
168
169 /// TargetConstant* - Like Constant*, but the DAG does not do any folding,
170 /// simplification, or lowering of the constant. They are used for constants
171 /// which are known to fit in the immediate fields of their users, or for
172 /// carrying magic numbers which are not values which need to be
173 /// materialized in registers.
176
177 /// TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or
178 /// anything else with this node, and this is valid in the target-specific
179 /// dag, turning into a GlobalAddress operand.
187
189
190 /// TargetIndex - Like a constant pool entry, but with completely
191 /// target-dependent semantics. Holds target flags, a 32-bit index, and a
192 /// 64-bit index. Targets can use this however they like.
194
195 /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...)
196 /// This node represents a target intrinsic function with no side effects.
197 /// The first operand is the ID number of the intrinsic from the
198 /// llvm::Intrinsic namespace. The operands to the intrinsic follow. The
199 /// node returns the result of the intrinsic.
201
202 /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...)
203 /// This node represents a target intrinsic function with side effects that
204 /// returns a result. The first operand is a chain pointer. The second is
205 /// the ID number of the intrinsic from the llvm::Intrinsic namespace. The
206 /// operands to the intrinsic follow. The node has two results, the result
207 /// of the intrinsic and an output chain.
209
210 /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...)
211 /// This node represents a target intrinsic function with side effects that
212 /// does not return a result. The first operand is a chain pointer. The
213 /// second is the ID number of the intrinsic from the llvm::Intrinsic
214 /// namespace. The operands to the intrinsic follow.
216
217 /// CopyToReg - This node has three operands: a chain, a register number to
218 /// set to this value, and a value.
220
221 /// CopyFromReg - This node indicates that the input value is a virtual or
222 /// physical register that is defined outside of the scope of this
223 /// SelectionDAG. The register is available from the RegisterSDNode object.
224 /// Note that CopyFromReg is considered as also freezing the value.
226
227 /// UNDEF - An undefined node.
229
230 /// POISON - A poison node.
232
233 /// FREEZE - FREEZE(VAL) returns an arbitrary value if VAL is UNDEF (or
234 /// is evaluated to UNDEF), or returns VAL otherwise. Note that each
235 /// read of UNDEF can yield different value, but FREEZE(UNDEF) cannot.
237
238 /// EXTRACT_ELEMENT - This is used to get the lower or upper (determined by
239 /// a Constant, which is required to be operand #1) half of the integer or
240 /// float value specified as operand #0. This is only for use before
241 /// legalization, for values that will be broken into multiple registers.
243
244 /// BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
245 /// Given two values of the same integer value type, this produces a value
246 /// twice as big. Like EXTRACT_ELEMENT, this can only be used before
247 /// legalization. The lower part of the composite value should be in
248 /// element 0 and the upper part should be in element 1.
250
251 /// MERGE_VALUES - This node takes multiple discrete operands and returns
252 /// them all as its individual results. This nodes has exactly the same
253 /// number of inputs and outputs. This node is useful for some pieces of the
254 /// code generator that want to think about a single node with multiple
255 /// results, not multiple nodes.
257
258 /// Simple integer binary arithmetic operators.
266
267 /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing
268 /// a signed/unsigned value of type i[2*N], and return the full value as
269 /// two results, each of type iN.
272
273 /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and
274 /// remainder result.
277
278 /// CARRY_FALSE - This node is used when folding other nodes,
279 /// like ADDC/SUBC, which indicate the carry result is always false.
281
282 /// Carry-setting nodes for multiple precision addition and subtraction.
283 /// These nodes take two operands of the same value type, and produce two
284 /// results. The first result is the normal add or sub result, the second
285 /// result is the carry flag result.
286 /// FIXME: These nodes are deprecated in favor of UADDO_CARRY and USUBO_CARRY.
287 /// They are kept around for now to provide a smooth transition path
288 /// toward the use of UADDO_CARRY/USUBO_CARRY and will eventually be removed.
291
292 /// Carry-using nodes for multiple precision addition and subtraction. These
293 /// nodes take three operands: The first two are the normal lhs and rhs to
294 /// the add or sub, and the third is the input carry flag. These nodes
295 /// produce two results; the normal result of the add or sub, and the output
296 /// carry flag. These nodes both read and write a carry flag to allow them
297 /// to them to be chained together for add and sub of arbitrarily large
298 /// values.
301
302 /// Carry-using nodes for multiple precision addition and subtraction.
303 /// These nodes take three operands: The first two are the normal lhs and
304 /// rhs to the add or sub, and the third is a boolean value that is 1 if and
305 /// only if there is an incoming carry/borrow. These nodes produce two
306 /// results: the normal result of the add or sub, and a boolean value that is
307 /// 1 if and only if there is an outgoing carry/borrow.
308 ///
309 /// Care must be taken if these opcodes are lowered to hardware instructions
310 /// that use the inverse logic -- 0 if and only if there is an
311 /// incoming/outgoing carry/borrow. In such cases, you must preserve the
312 /// semantics of these opcodes by inverting the incoming carry/borrow, feeding
313 /// it to the add/sub hardware instruction, and then inverting the outgoing
314 /// carry/borrow.
315 ///
316 /// The use of these opcodes is preferable to ADDE/SUBE if the target supports
317 /// it, as the carry is a regular value rather than a glue, which allows
318 /// further optimisation.
319 ///
320 /// These opcodes are different from [US]{ADD,SUB}O in that
321 /// U{ADD,SUB}O_CARRY consume and produce a carry/borrow, whereas
322 /// [US]{ADD,SUB}O produce an overflow.
325
326 /// Carry-using overflow-aware nodes for multiple precision addition and
327 /// subtraction. These nodes take three operands: The first two are normal lhs
328 /// and rhs to the add or sub, and the third is a boolean indicating if there
329 /// is an incoming carry. They produce two results: the normal result of the
330 /// add or sub, and a boolean that indicates if an overflow occurred (*not*
331 /// flag, because it may be a store to memory, etc.). If the type of the
332 /// boolean is not i1 then the high bits conform to getBooleanContents.
335
336 /// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
337 /// These nodes take two operands: the normal LHS and RHS to the add. They
338 /// produce two results: the normal result of the add, and a boolean that
339 /// indicates if an overflow occurred (*not* a flag, because it may be store
340 /// to memory, etc.). If the type of the boolean is not i1 then the high
341 /// bits conform to getBooleanContents.
342 /// These nodes are generated from llvm.[su]add.with.overflow intrinsics.
345
346 /// Same for subtraction.
349
350 /// Same for multiplication.
353
354 /// RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2
355 /// integers with the same bit width (W). If the true value of LHS + RHS
356 /// exceeds the largest value that can be represented by W bits, the
357 /// resulting value is this maximum value. Otherwise, if this value is less
358 /// than the smallest value that can be represented by W bits, the
359 /// resulting value is this minimum value.
362
363 /// RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2
364 /// integers with the same bit width (W). If the true value of LHS - RHS
365 /// exceeds the largest value that can be represented by W bits, the
366 /// resulting value is this maximum value. Otherwise, if this value is less
367 /// than the smallest value that can be represented by W bits, the
368 /// resulting value is this minimum value.
371
372 /// RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift. The first
373 /// operand is the value to be shifted, and the second argument is the amount
374 /// to shift by. Both must be integers of the same bit width (W). If the true
375 /// value of LHS << RHS exceeds the largest value that can be represented by
376 /// W bits, the resulting value is this maximum value, Otherwise, if this
377 /// value is less than the smallest value that can be represented by W bits,
378 /// the resulting value is this minimum value.
381
382 /// RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication
383 /// on 2 integers with the same width and scale. SCALE represents the scale
384 /// of both operands as fixed point numbers. This SCALE parameter must be a
385 /// constant integer. A scale of zero is effectively performing
386 /// multiplication on 2 integers.
389
390 /// Same as the corresponding unsaturated fixed point instructions, but the
391 /// result is clamped between the min and max values representable by the
392 /// bits of the first 2 operands.
395
396 /// RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on
397 /// 2 integers with the same width and scale. SCALE represents the scale
398 /// of both operands as fixed point numbers. This SCALE parameter must be a
399 /// constant integer.
402
403 /// Same as the corresponding unsaturated fixed point instructions, but the
404 /// result is clamped between the min and max values representable by the
405 /// bits of the first 2 operands.
408
409 /// Simple binary floating point operators.
415
416 /// Constrained versions of the binary floating point operators.
417 /// These will be lowered to the simple operators before final selection.
418 /// They are used to limit optimizations while the DAG is being
419 /// optimized.
426
427 /// Constrained versions of libm-equivalent floating point intrinsics.
428 /// These will be lowered to the equivalent non-constrained pseudo-op
429 /// (or expanded to the equivalent library call) before final selection.
430 /// They are used to limit optimizations while the DAG is being optimized.
465
466 /// STRICT_FP_TO_[US]INT - Convert a floating point value to a signed or
467 /// unsigned integer. These have the same semantics as fptosi and fptoui
468 /// in IR.
469 /// They are used to limit optimizations while the DAG is being optimized.
472
473 /// STRICT_[US]INT_TO_FP - Convert a signed or unsigned integer to
474 /// a floating point value. These have the same semantics as sitofp and
475 /// uitofp in IR.
476 /// They are used to limit optimizations while the DAG is being optimized.
479
480 /// X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating
481 /// point type down to the precision of the destination VT. TRUNC is a
482 /// flag, which is always an integer that is zero or one. If TRUNC is 0,
483 /// this is a normal rounding, if it is 1, this FP_ROUND is known to not
484 /// change the value of Y.
485 ///
486 /// The TRUNC = 1 case is used in cases where we know that the value will
487 /// not be modified by the node, because Y is not using any of the extra
488 /// precision of source type. This allows certain transformations like
489 /// STRICT_FP_EXTEND(STRICT_FP_ROUND(X,1)) -> X which are not safe for
490 /// STRICT_FP_EXTEND(STRICT_FP_ROUND(X,0)) because the extra bits aren't
491 /// removed.
492 /// It is used to limit optimizations while the DAG is being optimized.
494
495 /// X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP
496 /// type.
497 /// It is used to limit optimizations while the DAG is being optimized.
499
500 /// STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used
501 /// for floating-point operands only. STRICT_FSETCC performs a quiet
502 /// comparison operation, while STRICT_FSETCCS performs a signaling
503 /// comparison operation.
506
507 /// FPTRUNC_ROUND - This corresponds to the fptrunc_round intrinsic.
509
510 /// FMA - Perform a * b + c with no intermediate rounding step.
512
513 /// FMAD - Perform a * b + c, while getting the same result as the
514 /// separately rounded operations.
516
517 /// FMULADD - Performs a * b + c, with, or without, intermediate rounding.
518 /// It is expected that this will be illegal for most targets, as it usually
519 /// makes sense to split this or use an FMA. But some targets, such as
520 /// WebAssembly, can directly support these semantics.
522
523 /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This
524 /// DAG node does not require that X and Y have the same type, just that
525 /// they are both floating point. X and the result must have the same type.
526 /// FCOPYSIGN(f32, f64) is allowed.
528
529 /// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point
530 /// value as an integer 0/1 value.
532
533 /// Returns platform specific canonical encoding of a floating point number.
535
536 /// Performs a check of floating point class property, defined by IEEE-754.
537 /// The first operand is the floating point value to check. The second operand
538 /// specifies the checked property and is a TargetConstant which specifies
539 /// test in the same way as intrinsic 'is_fpclass'.
540 /// Returns boolean value.
542
543 /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector
544 /// with the specified, possibly variable, elements. The types of the
545 /// operands must match the vector element type, except that integer types
546 /// are allowed to be larger than the element type, in which case the
547 /// operands are implicitly truncated. The types of the operands must all
548 /// be the same.
550
551 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element
552 /// at IDX replaced with VAL. If the type of VAL is larger than the vector
553 /// element type then VAL is truncated before replacement.
554 ///
555 /// If VECTOR is a scalable vector, then IDX may be larger than the minimum
556 /// vector width. IDX is not first scaled by the runtime scaling factor of
557 /// VECTOR.
559
560 /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR
561 /// identified by the (potentially variable) element number IDX. If the return
562 /// type is an integer type larger than the element type of the vector, the
563 /// result is extended to the width of the return type. In that case, the high
564 /// bits are undefined.
565 ///
566 /// If VECTOR is a scalable vector, then IDX may be larger than the minimum
567 /// vector width. IDX is not first scaled by the runtime scaling factor of
568 /// VECTOR.
570
571 /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of
572 /// vector type with the same length and element type, this produces a
573 /// concatenated vector result value, with length equal to the sum of the
574 /// lengths of the input vectors. If VECTOR0 is a fixed-width vector, then
575 /// VECTOR1..VECTORN must all be fixed-width vectors. Similarly, if VECTOR0
576 /// is a scalable vector, then VECTOR1..VECTORN must all be scalable vectors.
578
579 /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2
580 /// inserted into VECTOR1. IDX represents the starting element number at which
581 /// VECTOR2 will be inserted. IDX must be a constant multiple of T's known
582 /// minimum vector length. Let the type of VECTOR2 be T, then if T is a
583 /// scalable vector, IDX is first scaled by the runtime scaling factor of T.
584 /// The elements of VECTOR1 starting at IDX are overwritten with VECTOR2.
585 /// Elements IDX through (IDX + num_elements(T) - 1) must be valid VECTOR1
586 /// indices. If this condition cannot be determined statically but is false at
587 /// runtime, then the result vector is undefined. The IDX parameter must be a
588 /// vector index constant type, which for most targets will be an integer
589 /// pointer type.
590 ///
591 /// This operation supports inserting a fixed-width vector into a scalable
592 /// vector, but not the other way around.
594
595 /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
596 /// Let the result type be T, then IDX represents the starting element number
597 /// from which a subvector of type T is extracted. IDX must be a constant
598 /// multiple of T's known minimum vector length. If T is a scalable vector,
599 /// IDX is first scaled by the runtime scaling factor of T. Elements IDX
600 /// through (IDX + num_elements(T) - 1) must be valid VECTOR indices. If this
601 /// condition cannot be determined statically but is false at runtime, then
602 /// the result vector is undefined. The IDX parameter must be a vector index
603 /// constant type, which for most targets will be an integer pointer type.
604 ///
605 /// This operation supports extracting a fixed-width vector from a scalable
606 /// vector, but not the other way around.
608
609 /// VECTOR_DEINTERLEAVE(VEC1, VEC2, ...) - Returns N vectors from N input
610 /// vectors, where N is the factor to deinterleave. All input and output
611 /// vectors must have the same type.
612 ///
613 /// Each output contains the deinterleaved indices for a specific field from
614 /// CONCAT_VECTORS(VEC1, VEC2, ...):
615 ///
616 /// Result[I][J] = CONCAT_VECTORS(...)[I + N * J]
618
619 /// VECTOR_INTERLEAVE(VEC1, VEC2, ...) - Returns N vectors from N input
620 /// vectors, where N is the factor to interleave. All input and
621 /// output vectors must have the same type.
622 ///
623 /// All input vectors are interleaved into one wide vector, which is then
624 /// chunked into equal sized parts:
625 ///
626 /// Interleaved[I] = VEC(I % N)[I / N]
627 /// Result[J] = EXTRACT_SUBVECTOR(Interleaved, J * getVectorMinNumElements())
629
630 /// VECTOR_REVERSE(VECTOR) - Returns a vector, of the same type as VECTOR,
631 /// whose elements are shuffled using the following algorithm:
632 /// RESULT[i] = VECTOR[VECTOR.ElementCount - 1 - i]
634
635 /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as
636 /// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int
637 /// values that indicate which value (or undef) each result element will
638 /// get. These constant ints are accessible through the
639 /// ShuffleVectorSDNode class. This is quite similar to the Altivec
640 /// 'vperm' instruction, except that the indices must be constants and are
641 /// in terms of the element size of VEC1/VEC2, not in terms of bytes.
643
644 /// VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as
645 /// VEC1/VEC2 from CONCAT_VECTORS(VEC1, VEC2), based on the IMM in two ways.
646 /// Let the result type be T, if IMM is positive it represents the starting
647 /// element number (an index) from which a subvector of type T is extracted
648 /// from CONCAT_VECTORS(VEC1, VEC2). If IMM is negative it represents a count
649 /// specifying the number of trailing elements to extract from VEC1, where the
650 /// elements of T are selected using the following algorithm:
651 /// RESULT[i] = CONCAT_VECTORS(VEC1,VEC2)[VEC1.ElementCount - ABS(IMM) + i]
652 /// If IMM is not in the range [-VL, VL-1] the result vector is undefined. IMM
653 /// is a constant integer.
655
656 /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a
657 /// scalar value into element 0 of the resultant vector type. The top
658 /// elements 1 to N-1 of the N-element vector are undefined. The type
659 /// of the operand must match the vector element type, except when they
660 /// are integer types. In this case the operand is allowed to be wider
661 /// than the vector element type, and is implicitly truncated to it.
663
664 /// SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL
665 /// duplicated in all lanes. The type of the operand must match the vector
666 /// element type, except when they are integer types. In this case the
667 /// operand is allowed to be wider than the vector element type, and is
668 /// implicitly truncated to it.
670
671 /// SPLAT_VECTOR_PARTS(SCALAR1, SCALAR2, ...) - Returns a vector with the
672 /// scalar values joined together and then duplicated in all lanes. This
673 /// represents a SPLAT_VECTOR that has had its scalar operand expanded. This
674 /// allows representing a 64-bit splat on a target with 32-bit integers. The
675 /// total width of the scalars must cover the element width. SCALAR1 contains
676 /// the least significant bits of the value regardless of endianness and all
677 /// scalars should have the same type.
679
680 /// STEP_VECTOR(IMM) - Returns a scalable vector whose lanes are comprised
681 /// of a linear sequence of unsigned values starting from 0 with a step of
682 /// IMM, where IMM must be a TargetConstant with type equal to the vector
683 /// element type. The arithmetic is performed modulo the bitwidth of the
684 /// element.
685 ///
686 /// The operation does not support returning fixed-width vectors or
687 /// non-constant operands.
689
690 /// VECTOR_COMPRESS(Vec, Mask, Passthru)
691 /// consecutively place vector elements based on mask
692 /// e.g., vec = {A, B, C, D} and mask = {1, 0, 1, 0}
693 /// --> {A, C, ?, ?} where ? is undefined
694 /// If passthru is defined, ?s are replaced with elements from passthru.
695 /// If passthru is undef, ?s remain undefined.
697
698 /// MULHU/MULHS - Multiply high - Multiply two integers of type iN,
699 /// producing an unsigned/signed value of type i[2*N], then return the top
700 /// part.
703
704 /// AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of
705 /// type i[N+1], halving the result by shifting it one bit right.
706 /// shr(add(ext(X), ext(Y)), 1)
709 /// AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an
710 /// integer of type i[N+2], add 1 and halve the result by shifting it one bit
711 /// right. shr(add(ext(X), ext(Y), 1), 1)
714
715 /// ABDS/ABDU - Absolute difference - Return the absolute difference between
716 /// two numbers interpreted as signed/unsigned.
717 /// i.e trunc(abs(sext(Op0) - sext(Op1))) becomes abds(Op0, Op1)
718 /// or trunc(abs(zext(Op0) - zext(Op1))) becomes abdu(Op0, Op1)
721
722 /// [US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned
723 /// integers.
728
729 /// [US]CMP - 3-way comparison of signed or unsigned integers. Returns -1, 0,
730 /// or 1 depending on whether Op0 <, ==, or > Op1. The operands can have type
731 /// different to the result.
734
735 /// Bitwise operators - logical and, logical or, logical xor.
739
740 /// ABS - Determine the unsigned absolute value of a signed integer value of
741 /// the same bitwidth.
742 /// Note: A value of INT_MIN will return INT_MIN, no saturation or overflow
743 /// is performed.
745
746 /// Shift and rotation operations. After legalization, the type of the
747 /// shift amount is known to be TLI.getShiftAmountTy(). Before legalization
748 /// the shift amount can be any type, but care must be taken to ensure it is
749 /// large enough. TLI.getShiftAmountTy() is i8 on some targets, but before
750 /// legalization, types like i1024 can occur and i8 doesn't have enough bits
751 /// to represent the shift amount.
752 /// When the 1st operand is a vector, the shift amount must be in the same
753 /// type. (TLI.getShiftAmountTy() will return the same type when the input
754 /// type is a vector.)
755 /// For rotates and funnel shifts, the shift amount is treated as an unsigned
756 /// amount modulo the element size of the first operand.
757 ///
758 /// Funnel 'double' shifts take 3 operands, 2 inputs and the shift amount.
759 ///
760 /// fshl(X,Y,Z): (X << (Z % BW)) | (Y >> (BW - (Z % BW)))
761 /// fshr(X,Y,Z): (X << (BW - (Z % BW))) | (Y >> (Z % BW))
769
770 /// Byte Swap and Counting operators.
777
778 /// Bit counting operators with an undefined result for zero inputs.
781
782 /// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not
783 /// i1 then the high bits must conform to getBooleanContents.
785
786 /// Select with a vector condition (op #0) and two vector operands (ops #1
787 /// and #2), returning a vector result. All vectors have the same length.
788 /// Much like the scalar select and setcc, each bit in the condition selects
789 /// whether the corresponding result element is taken from op #1 or op #2.
790 /// At first, the VSELECT condition is of vXi1 type. Later, targets may
791 /// change the condition type in order to match the VSELECT node using a
792 /// pattern. The condition follows the BooleanContent format of the target.
794
795 /// Select with condition operator - This selects between a true value and
796 /// a false value (ops #2 and #3) based on the boolean result of comparing
797 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
798 /// condition code in op #4, a CondCodeSDNode.
800
801 /// SetCC operator - This evaluates to a true value iff the condition is
802 /// true. If the result value type is not i1 then the high bits conform
803 /// to getBooleanContents. The operands to this are the left and right
804 /// operands to compare (ops #0, and #1) and the condition code to compare
805 /// them with (op #2) as a CondCodeSDNode. If the operands are vector types
806 /// then the result type must also be a vector type.
808
809 /// Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but
810 /// op #2 is a boolean indicating if there is an incoming carry. This
811 /// operator checks the result of "LHS - RHS - Carry", and can be used to
812 /// compare two wide integers:
813 /// (setcccarry lhshi rhshi (usubo_carry lhslo rhslo) cc).
814 /// Only valid for integers.
816
817 /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded
818 /// integer shift operations. The operation ordering is:
819 ///
820 /// [Lo,Hi] = op [LoLHS,HiLHS], Amt
824
825 /// Conversion operators. These are all single input single output
826 /// operations. For all of these, the result type must be strictly
827 /// wider or narrower (depending on the operation) than the source
828 /// type.
829
830 /// SIGN_EXTEND - Used for integer types, replicating the sign bit
831 /// into new bits.
833
834 /// ZERO_EXTEND - Used for integer types, zeroing the new bits. Can carry
835 /// the NonNeg SDNodeFlag to indicate that the input is known to be
836 /// non-negative. If the flag is present and the input is negative, the result
837 /// is poison.
839
840 /// ANY_EXTEND - Used for integer types. The high bits are undefined.
842
843 /// TRUNCATE - Completely drop the high bits.
845 /// TRUNCATE_[SU]SAT_[SU] - Truncate for saturated operand
846 /// [SU] located in middle, prefix for `SAT` means indicates whether
847 /// existing truncate target was a signed operation. For examples,
848 /// If `truncate(smin(smax(x, C), C))` was saturated then become `S`.
849 /// If `truncate(umin(x, C))` was saturated then become `U`.
850 /// [SU] located in last indicates whether range of truncated values is
851 /// sign-saturated. For example, if `truncate(smin(smax(x, C), C))` is a
852 /// truncation to `i8`, then if value of C ranges from `-128 to 127`, it will
853 /// be saturated against signed values, resulting in `S`, which will combine
854 /// to `TRUNCATE_SSAT_S`. If the value of C ranges from `0 to 255`, it will
855 /// be saturated against unsigned values, resulting in `U`, which will
856 /// combine to `TRUNCATE_SSAT_U`. Similarly, in `truncate(umin(x, C))`, if
857 /// value of C ranges from `0 to 255`, it becomes `U` because it is saturated
858 /// for unsigned values. As a result, it combines to `TRUNCATE_USAT_U`.
859 TRUNCATE_SSAT_S, // saturate signed input to signed result -
860 // truncate(smin(smax(x, C), C))
861 TRUNCATE_SSAT_U, // saturate signed input to unsigned result -
862 // truncate(smin(smax(x, 0), C))
863 TRUNCATE_USAT_U, // saturate unsigned input to unsigned result -
864 // truncate(umin(x, C))
865
866 /// [SU]INT_TO_FP - These operators convert integers (whose interpreted sign
867 /// depends on the first letter) to floating point.
870
871 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
872 /// sign extend a small value in a large integer register (e.g. sign
873 /// extending the low 8 bits of a 32-bit register to fill the top 24 bits
874 /// with the 7th bit). The size of the smaller type is indicated by the 1th
875 /// operand, a ValueType node.
877
878 /// ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an
879 /// in-register any-extension of the low lanes of an integer vector. The
880 /// result type must have fewer elements than the operand type, and those
881 /// elements must be larger integer types such that the total size of the
882 /// operand type is less than or equal to the size of the result type. Each
883 /// of the low operand elements is any-extended into the corresponding,
884 /// wider result elements with the high bits becoming undef.
885 /// NOTE: The type legalizer prefers to make the operand and result size
886 /// the same to allow expansion to shuffle vector during op legalization.
888
889 /// SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an
890 /// in-register sign-extension of the low lanes of an integer vector. The
891 /// result type must have fewer elements than the operand type, and those
892 /// elements must be larger integer types such that the total size of the
893 /// operand type is less than or equal to the size of the result type. Each
894 /// of the low operand elements is sign-extended into the corresponding,
895 /// wider result elements.
896 /// NOTE: The type legalizer prefers to make the operand and result size
897 /// the same to allow expansion to shuffle vector during op legalization.
899
900 /// ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an
901 /// in-register zero-extension of the low lanes of an integer vector. The
902 /// result type must have fewer elements than the operand type, and those
903 /// elements must be larger integer types such that the total size of the
904 /// operand type is less than or equal to the size of the result type. Each
905 /// of the low operand elements is zero-extended into the corresponding,
906 /// wider result elements.
907 /// NOTE: The type legalizer prefers to make the operand and result size
908 /// the same to allow expansion to shuffle vector during op legalization.
910
911 /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned
912 /// integer. These have the same semantics as fptosi and fptoui in IR. If
913 /// the FP value cannot fit in the integer type, the results are undefined.
916
917 /// FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a
918 /// signed or unsigned scalar integer type given in operand 1 with the
919 /// following semantics:
920 ///
921 /// * If the value is NaN, zero is returned.
922 /// * If the value is larger/smaller than the largest/smallest integer,
923 /// the largest/smallest integer is returned (saturation).
924 /// * Otherwise the result of rounding the value towards zero is returned.
925 ///
926 /// The scalar width of the type given in operand 1 must be equal to, or
927 /// smaller than, the scalar result type width. It may end up being smaller
928 /// than the result width as a result of integer type legalization.
929 ///
930 /// After converting to the scalar integer type in operand 1, the value is
931 /// extended to the result VT. FP_TO_SINT_SAT sign extends and FP_TO_UINT_SAT
932 /// zero extends.
935
936 /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type
937 /// down to the precision of the destination VT. TRUNC is a flag, which is
938 /// always an integer that is zero or one. If TRUNC is 0, this is a
939 /// normal rounding, if it is 1, this FP_ROUND is known to not change the
940 /// value of Y.
941 ///
942 /// The TRUNC = 1 case is used in cases where we know that the value will
943 /// not be modified by the node, because Y is not using any of the extra
944 /// precision of source type. This allows certain transformations like
945 /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for
946 /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed.
948
949 /// Returns current rounding mode:
950 /// -1 Undefined
951 /// 0 Round to 0
952 /// 1 Round to nearest, ties to even
953 /// 2 Round to +inf
954 /// 3 Round to -inf
955 /// 4 Round to nearest, ties to zero
956 /// Other values are target dependent.
957 /// Result is rounding mode and chain. Input is a chain.
959
960 /// Set rounding mode.
961 /// The first operand is a chain pointer. The second specifies the required
962 /// rounding mode, encoded in the same way as used in '``GET_ROUNDING``'.
963 SET_ROUNDING,
964
965 /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
966 FP_EXTEND,
967
968 /// BITCAST - This operator converts between integer, vector and FP
969 /// values, as if the value was stored to memory with one type and loaded
970 /// from the same address with the other type (or equivalently for vector
971 /// format conversions, etc). The source and result are required to have
972 /// the same bit size (e.g. f32 <-> i32). This can also be used for
973 /// int-to-int or fp-to-fp conversions, but that is a noop, deleted by
974 /// getNode().
975 ///
976 /// This operator is subtly different from the bitcast instruction from
977 /// LLVM-IR since this node may change the bits in the register. For
978 /// example, this occurs on big-endian NEON and big-endian MSA where the
979 /// layout of the bits in the register depends on the vector type and this
980 /// operator acts as a shuffle operation for some vector type combinations.
981 BITCAST,
982
983 /// ADDRSPACECAST - This operator converts between pointers of different
984 /// address spaces.
985 ADDRSPACECAST,
986
987 /// FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions
988 /// and truncation for half-precision (16 bit) floating numbers. These nodes
989 /// form a semi-softened interface for dealing with f16 (as an i16), which
990 /// is often a storage-only type but has native conversions.
991 FP16_TO_FP,
992 FP_TO_FP16,
993 STRICT_FP16_TO_FP,
994 STRICT_FP_TO_FP16,
995
996 /// BF16_TO_FP, FP_TO_BF16 - These operators are used to perform promotions
997 /// and truncation for bfloat16. These nodes form a semi-softened interface
998 /// for dealing with bf16 (as an i16), which is often a storage-only type but
999 /// has native conversions.
1000 BF16_TO_FP,
1001 FP_TO_BF16,
1002 STRICT_BF16_TO_FP,
1003 STRICT_FP_TO_BF16,
1004
1005 /// Perform various unary floating-point operations inspired by libm. For
1006 /// FPOWI, the result is undefined if the integer operand doesn't fit into
1007 /// sizeof(int).
1008 FNEG,
1009 FABS,
1010 FSQRT,
1011 FCBRT,
1012 FSIN,
1013 FCOS,
1014 FTAN,
1015 FASIN,
1016 FACOS,
1017 FATAN,
1018 FSINH,
1019 FCOSH,
1020 FTANH,
1021 FPOW,
1022 FPOWI,
1023 /// FLDEXP - ldexp, inspired by libm (op0 * 2**op1).
1024 FLDEXP,
1025 /// FATAN2 - atan2, inspired by libm.
1026 FATAN2,
1027
1028 /// FFREXP - frexp, extract fractional and exponent component of a
1029 /// floating-point value. Returns the two components as separate return
1030 /// values.
1031 FFREXP,
1032
1033 FLOG,
1034 FLOG2,
1035 FLOG10,
1036 FEXP,
1037 FEXP2,
1038 FEXP10,
1039 FCEIL,
1040 FTRUNC,
1041 FRINT,
1042 FNEARBYINT,
1043 FROUND,
1044 FROUNDEVEN,
1045 FFLOOR,
1046 LROUND,
1047 LLROUND,
1048 LRINT,
1049 LLRINT,
1050
1051 /// FMINNUM/FMAXNUM - Perform floating-point minimum maximum on two values,
1052 /// following IEEE-754 definitions except for signed zero behavior.
1053 ///
1054 /// If one input is a signaling NaN, returns a quiet NaN. This matches
1055 /// IEEE-754 2008's minNum/maxNum behavior for signaling NaNs (which differs
1056 /// from 2019).
1057 ///
1058 /// These treat -0 as ordered less than +0, matching the behavior of IEEE-754
1059 /// 2019's minimumNumber/maximumNumber.
1060 ///
1061 /// Note that that arithmetic on an sNaN doesn't consistently produce a qNaN,
1062 /// so arithmetic feeding into a minnum/maxnum can produce inconsistent
1063 /// results. FMAXIMUN/FMINIMUM or FMAXIMUMNUM/FMINIMUMNUM may be better choice
1064 /// for non-distinction of sNaN/qNaN handling.
1065 FMINNUM,
1066 FMAXNUM,
1067
1068 /// FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimumNumber or
1069 /// maximumNumber on two values, following IEEE-754 definitions. This differs
1070 /// from FMINNUM/FMAXNUM in the handling of signaling NaNs, and signed zero.
1071 ///
1072 /// If one input is a signaling NaN, returns a quiet NaN. This matches
1073 /// IEEE-754 2008's minnum/maxnum behavior for signaling NaNs (which differs
1074 /// from 2019).
1075 ///
1076 /// These treat -0 as ordered less than +0, matching the behavior of IEEE-754
1077 /// 2019's minimumNumber/maximumNumber.
1078 ///
1079 /// Deprecated, and will be removed soon, as FMINNUM/FMAXNUM have the same
1080 /// semantics now.
1081 FMINNUM_IEEE,
1082 FMAXNUM_IEEE,
1083
1084 /// FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0
1085 /// as less than 0.0. While FMINNUM_IEEE/FMAXNUM_IEEE follow IEEE 754-2008
1086 /// semantics, FMINIMUM/FMAXIMUM follow IEEE 754-2019 semantics.
1087 FMINIMUM,
1088 FMAXIMUM,
1089
1090 /// FMINIMUMNUM/FMAXIMUMNUM - minimumnum/maximumnum that is same with
1091 /// FMINNUM_IEEE and FMAXNUM_IEEE besides if either operand is sNaN.
1092 FMINIMUMNUM,
1093 FMAXIMUMNUM,
1094
1095 /// FSINCOS - Compute both fsin and fcos as a single operation.
1096 FSINCOS,
1097
1098 /// FSINCOSPI - Compute both the sine and cosine times pi more accurately
1099 /// than FSINCOS(pi*x), especially for large x.
1100 FSINCOSPI,
1101
1102 /// FMODF - Decomposes the operand into integral and fractional parts, each
1103 /// having the same type and sign as the operand.
1104 FMODF,
1105
1106 /// Gets the current floating-point environment. The first operand is a token
1107 /// chain. The results are FP environment, represented by an integer value,
1108 /// and a token chain.
1109 GET_FPENV,
1110
1111 /// Sets the current floating-point environment. The first operand is a token
1112 /// chain, the second is FP environment, represented by an integer value. The
1113 /// result is a token chain.
1114 SET_FPENV,
1115
1116 /// Set floating-point environment to default state. The first operand and the
1117 /// result are token chains.
1118 RESET_FPENV,
1119
1120 /// Gets the current floating-point environment. The first operand is a token
1121 /// chain, the second is a pointer to memory, where FP environment is stored
1122 /// to. The result is a token chain.
1123 GET_FPENV_MEM,
1124
1125 /// Sets the current floating point environment. The first operand is a token
1126 /// chain, the second is a pointer to memory, where FP environment is loaded
1127 /// from. The result is a token chain.
1128 SET_FPENV_MEM,
1129
1130 /// Reads the current dynamic floating-point control modes. The operand is
1131 /// a token chain.
1132 GET_FPMODE,
1133
1134 /// Sets the current dynamic floating-point control modes. The first operand
1135 /// is a token chain, the second is control modes set represented as integer
1136 /// value.
1137 SET_FPMODE,
1138
1139 /// Sets default dynamic floating-point control modes. The operand is a
1140 /// token chain.
1141 RESET_FPMODE,
1142
1143 /// LOAD and STORE have token chains as their first operand, then the same
1144 /// operands as an LLVM load/store instruction, then an offset node that
1145 /// is added / subtracted from the base pointer to form the address (for
1146 /// indexed memory ops).
1147 LOAD,
1148 STORE,
1149
1150 /// DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned
1151 /// to a specified boundary. This node always has two return values: a new
1152 /// stack pointer value and a chain. The first operand is the token chain,
1153 /// the second is the number of bytes to allocate, and the third is the
1154 /// alignment boundary. The size is guaranteed to be a multiple of the
1155 /// stack alignment, and the alignment is guaranteed to be bigger than the
1156 /// stack alignment (if required) or 0 to get standard stack alignment.
1157 DYNAMIC_STACKALLOC,
1158
1159 /// Control flow instructions. These all have token chains.
1160
1161 /// BR - Unconditional branch. The first operand is the chain
1162 /// operand, the second is the MBB to branch to.
1163 BR,
1164
1165 /// BRIND - Indirect branch. The first operand is the chain, the second
1166 /// is the value to branch to, which must be of the same type as the
1167 /// target's pointer type.
1168 BRIND,
1169
1170 /// BR_JT - Jumptable branch. The first operand is the chain, the second
1171 /// is the jumptable index, the last one is the jumptable entry index.
1172 BR_JT,
1173
1174 /// JUMP_TABLE_DEBUG_INFO - Jumptable debug info. The first operand is the
1175 /// chain, the second is the jumptable index.
1176 JUMP_TABLE_DEBUG_INFO,
1177
1178 /// BRCOND - Conditional branch. The first operand is the chain, the
1179 /// second is the condition, the third is the block to branch to if the
1180 /// condition is true. If the type of the condition is not i1, then the
1181 /// high bits must conform to getBooleanContents. If the condition is undef,
1182 /// it nondeterministically jumps to the block.
1183 /// TODO: Its semantics w.r.t undef requires further discussion; we need to
1184 /// make it sure that it is consistent with optimizations in MIR & the
1185 /// meaning of IMPLICIT_DEF. See https://reviews.llvm.org/D92015
1186 BRCOND,
1187
1188 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in
1189 /// that the condition is represented as condition code, and two nodes to
1190 /// compare, rather than as a combined SetCC node. The operands in order
1191 /// are chain, cc, lhs, rhs, block to branch to if condition is true. If
1192 /// condition is undef, it nondeterministically jumps to the block.
1193 BR_CC,
1194
1195 /// INLINEASM - Represents an inline asm block. This node always has two
1196 /// return values: a chain and a flag result. The inputs are as follows:
1197 /// Operand #0 : Input chain.
1198 /// Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string.
1199 /// Operand #2 : a MDNodeSDNode with the !srcloc metadata.
1200 /// Operand #3 : HasSideEffect, IsAlignStack bits.
1201 /// After this, it is followed by a list of operands with this format:
1202 /// ConstantSDNode: Flags that encode whether it is a mem or not, the
1203 /// of operands that follow, etc. See InlineAsm.h.
1204 /// ... however many operands ...
1205 /// Operand #last: Optional, an incoming flag.
1206 ///
1207 /// The variable width operands are required to represent target addressing
1208 /// modes as a single "operand", even though they may have multiple
1209 /// SDOperands.
1210 INLINEASM,
1211
1212 /// INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
1213 INLINEASM_BR,
1214
1215 /// EH_LABEL - Represents a label in mid basic block used to track
1216 /// locations needed for debug and exception handling tables. These nodes
1217 /// take a chain as input and return a chain.
1218 EH_LABEL,
1219
1220 /// ANNOTATION_LABEL - Represents a mid basic block label used by
1221 /// annotations. This should remain within the basic block and be ordered
1222 /// with respect to other call instructions, but loads and stores may float
1223 /// past it.
1224 ANNOTATION_LABEL,
1225
1226 /// CATCHRET - Represents a return from a catch block funclet. Used for
1227 /// MSVC compatible exception handling. Takes a chain operand and a
1228 /// destination basic block operand.
1229 CATCHRET,
1230
1231 /// CLEANUPRET - Represents a return from a cleanup block funclet. Used for
1232 /// MSVC compatible exception handling. Takes only a chain operand.
1233 CLEANUPRET,
1234
1235 /// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a
1236 /// value, the same type as the pointer type for the system, and an output
1237 /// chain.
1238 STACKSAVE,
1239
1240 /// STACKRESTORE has two operands, an input chain and a pointer to restore
1241 /// to it returns an output chain.
1242 STACKRESTORE,
1243
1244 /// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end
1245 /// of a call sequence, and carry arbitrary information that target might
1246 /// want to know. The first operand is a chain, the rest are specified by
1247 /// the target and not touched by the DAG optimizers.
1248 /// Targets that may use stack to pass call arguments define additional
1249 /// operands:
1250 /// - size of the call frame part that must be set up within the
1251 /// CALLSEQ_START..CALLSEQ_END pair,
1252 /// - part of the call frame prepared prior to CALLSEQ_START.
1253 /// Both these parameters must be constants, their sum is the total call
1254 /// frame size.
1255 /// CALLSEQ_START..CALLSEQ_END pairs may not be nested.
1256 CALLSEQ_START, // Beginning of a call sequence
1257 CALLSEQ_END, // End of a call sequence
1258
1259 /// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE,
1260 /// and the alignment. It returns a pair of values: the vaarg value and a
1261 /// new chain.
1262 VAARG,
1263
1264 /// VACOPY - VACOPY has 5 operands: an input chain, a destination pointer,
1265 /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the
1266 /// source.
1267 VACOPY,
1268
1269 /// VAEND, VASTART - VAEND and VASTART have three operands: an input chain,
1270 /// pointer, and a SRCVALUE.
1271 VAEND,
1272 VASTART,
1273
1274 /// PREALLOCATED_SETUP - This has 2 operands: an input chain and a SRCVALUE
1275 /// with the preallocated call Value.
1276 PREALLOCATED_SETUP,
1277 /// PREALLOCATED_ARG - This has 3 operands: an input chain, a SRCVALUE
1278 /// with the preallocated call Value, and a constant int.
1279 PREALLOCATED_ARG,
1280
1281 /// SRCVALUE - This is a node type that holds a Value* that is used to
1282 /// make reference to a value in the LLVM IR.
1283 SRCVALUE,
1284
1285 /// MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to
1286 /// reference metadata in the IR.
1287 MDNODE_SDNODE,
1288
1289 /// PCMARKER - This corresponds to the pcmarker intrinsic.
1290 PCMARKER,
1291
1292 /// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
1293 /// It produces a chain and one i64 value. The only operand is a chain.
1294 /// If i64 is not legal, the result will be expanded into smaller values.
1295 /// Still, it returns an i64, so targets should set legality for i64.
1296 /// The result is the content of the architecture-specific cycle
1297 /// counter-like register (or other high accuracy low latency clock source).
1298 READCYCLECOUNTER,
1299
1300 /// READSTEADYCOUNTER - This corresponds to the readfixedcounter intrinsic.
1301 /// It has the same semantics as the READCYCLECOUNTER implementation except
1302 /// that the result is the content of the architecture-specific fixed
1303 /// frequency counter suitable for measuring elapsed time.
1304 READSTEADYCOUNTER,
1305
1306 /// HANDLENODE node - Used as a handle for various purposes.
1307 HANDLENODE,
1308
1309 /// INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic. It
1310 /// takes as input a token chain, the pointer to the trampoline, the pointer
1311 /// to the nested function, the pointer to pass for the 'nest' parameter, a
1312 /// SRCVALUE for the trampoline and another for the nested function
1313 /// (allowing targets to access the original Function*).
1314 /// It produces a token chain as output.
1315 INIT_TRAMPOLINE,
1316
1317 /// ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
1318 /// It takes a pointer to the trampoline and produces a (possibly) new
1319 /// pointer to the same trampoline with platform-specific adjustments
1320 /// applied. The pointer it returns points to an executable block of code.
1321 ADJUST_TRAMPOLINE,
1322
1323 /// TRAP - Trapping instruction
1324 TRAP,
1325
1326 /// DEBUGTRAP - Trap intended to get the attention of a debugger.
1327 DEBUGTRAP,
1328
1329 /// UBSANTRAP - Trap with an immediate describing the kind of sanitizer
1330 /// failure.
1331 UBSANTRAP,
1332
1333 /// PREFETCH - This corresponds to a prefetch intrinsic. The first operand
1334 /// is the chain. The other operands are the address to prefetch,
1335 /// read / write specifier, locality specifier and instruction / data cache
1336 /// specifier.
1337 PREFETCH,
1338
1339 /// ARITH_FENCE - This corresponds to a arithmetic fence intrinsic. Both its
1340 /// operand and output are the same floating type.
1341 ARITH_FENCE,
1342
1343 /// MEMBARRIER - Compiler barrier only; generate a no-op.
1344 MEMBARRIER,
1345
1346 /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope)
1347 /// This corresponds to the fence instruction. It takes an input chain, and
1348 /// two integer constants: an AtomicOrdering and a SynchronizationScope.
1349 ATOMIC_FENCE,
1350
1351 /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr)
1352 /// This corresponds to "load atomic" instruction.
1354
1355 /// OUTCHAIN = ATOMIC_STORE(INCHAIN, val, ptr)
1356 /// This corresponds to "store atomic" instruction.
1358
1359 /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
1360 /// For double-word atomic operations:
1361 /// ValLo, ValHi, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmpLo, cmpHi,
1362 /// swapLo, swapHi)
1363 /// This corresponds to the cmpxchg instruction.
1364 ATOMIC_CMP_SWAP,
1365
1366 /// Val, Success, OUTCHAIN
1367 /// = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap)
1368 /// N.b. this is still a strong cmpxchg operation, so
1369 /// Success == "Val == cmp".
1370 ATOMIC_CMP_SWAP_WITH_SUCCESS,
1371
1372 /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt)
1373 /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt)
1374 /// For double-word atomic operations:
1375 /// ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi)
1376 /// ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi)
1377 /// These correspond to the atomicrmw instruction.
1378 ATOMIC_SWAP,
1379 ATOMIC_LOAD_ADD,
1380 ATOMIC_LOAD_SUB,
1381 ATOMIC_LOAD_AND,
1382 ATOMIC_LOAD_CLR,
1383 ATOMIC_LOAD_OR,
1384 ATOMIC_LOAD_XOR,
1385 ATOMIC_LOAD_NAND,
1386 ATOMIC_LOAD_MIN,
1387 ATOMIC_LOAD_MAX,
1388 ATOMIC_LOAD_UMIN,
1389 ATOMIC_LOAD_UMAX,
1390 ATOMIC_LOAD_FADD,
1391 ATOMIC_LOAD_FSUB,
1392 ATOMIC_LOAD_FMAX,
1393 ATOMIC_LOAD_FMIN,
1394 ATOMIC_LOAD_FMAXIMUM,
1395 ATOMIC_LOAD_FMINIMUM,
1396 ATOMIC_LOAD_UINC_WRAP,
1397 ATOMIC_LOAD_UDEC_WRAP,
1398 ATOMIC_LOAD_USUB_COND,
1399 ATOMIC_LOAD_USUB_SAT,
1400
1401 /// Masked load and store - consecutive vector load and store operations
1402 /// with additional mask operand that prevents memory accesses to the
1403 /// masked-off lanes.
1404 ///
1405 /// Val, OutChain = MLOAD(BasePtr, Mask, PassThru)
1406 /// OutChain = MSTORE(Value, BasePtr, Mask)
1407 MLOAD,
1408 MSTORE,
1409
1410 /// Masked gather and scatter - load and store operations for a vector of
1411 /// random addresses with additional mask operand that prevents memory
1412 /// accesses to the masked-off lanes.
1413 ///
1414 /// Val, OutChain = GATHER(InChain, PassThru, Mask, BasePtr, Index, Scale)
1415 /// OutChain = SCATTER(InChain, Value, Mask, BasePtr, Index, Scale)
1416 ///
1417 /// The Index operand can have more vector elements than the other operands
1418 /// due to type legalization. The extra elements are ignored.
1419 MGATHER,
1420 MSCATTER,
1421
1422 /// This corresponds to the llvm.lifetime.* intrinsics. The first operand
1423 /// is the chain and the second operand is the alloca pointer.
1424 LIFETIME_START,
1425 LIFETIME_END,
1426
1427 /// FAKE_USE represents a use of the operand but does not do anything.
1428 /// Its purpose is the extension of the operand's lifetime mainly for
1429 /// debugging purposes.
1430 FAKE_USE,
1431
1432 /// GC_TRANSITION_START/GC_TRANSITION_END - These operators mark the
1433 /// beginning and end of GC transition sequence, and carry arbitrary
1434 /// information that target might need for lowering. The first operand is
1435 /// a chain, the rest are specified by the target and not touched by the DAG
1436 /// optimizers. GC_TRANSITION_START..GC_TRANSITION_END pairs may not be
1437 /// nested.
1438 GC_TRANSITION_START,
1439 GC_TRANSITION_END,
1440
1441 /// GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of
1442 /// the most recent dynamic alloca. For most targets that would be 0, but
1443 /// for some others (e.g. PowerPC, PowerPC64) that would be compile-time
1444 /// known nonzero constant. The only operand here is the chain.
1445 GET_DYNAMIC_AREA_OFFSET,
1446
1447 /// Pseudo probe for AutoFDO, as a place holder in a basic block to improve
1448 /// the sample counts quality.
1449 PSEUDO_PROBE,
1450
1451 /// VSCALE(IMM) - Returns the runtime scaling factor used to calculate the
1452 /// number of elements within a scalable vector. IMM is a constant integer
1453 /// multiplier that is applied to the runtime value.
1454 VSCALE,
1455
1456 /// Generic reduction nodes. These nodes represent horizontal vector
1457 /// reduction operations, producing a scalar result.
1458 /// The SEQ variants perform reductions in sequential order. The first
1459 /// operand is an initial scalar accumulator value, and the second operand
1460 /// is the vector to reduce.
1461 /// E.g. RES = VECREDUCE_SEQ_FADD f32 ACC, <4 x f32> SRC_VEC
1462 /// ... is equivalent to
1463 /// RES = (((ACC + SRC_VEC[0]) + SRC_VEC[1]) + SRC_VEC[2]) + SRC_VEC[3]
1464 VECREDUCE_SEQ_FADD,
1465 VECREDUCE_SEQ_FMUL,
1466
1467 /// These reductions have relaxed evaluation order semantics, and have a
1468 /// single vector operand. The order of evaluation is unspecified. For
1469 /// pow-of-2 vectors, one valid legalizer expansion is to use a tree
1470 /// reduction, i.e.:
1471 /// For RES = VECREDUCE_FADD <8 x f16> SRC_VEC
1472 ///
1473 /// PART_RDX = FADD SRC_VEC[0:3], SRC_VEC[4:7]
1474 /// PART_RDX2 = FADD PART_RDX[0:1], PART_RDX[2:3]
1475 /// RES = FADD PART_RDX2[0], PART_RDX2[1]
1476 ///
1477 /// For non-pow-2 vectors, this can be computed by extracting each element
1478 /// and performing the operation as if it were scalarized.
1479 VECREDUCE_FADD,
1480 VECREDUCE_FMUL,
1481 /// FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
1482 VECREDUCE_FMAX,
1483 VECREDUCE_FMIN,
1484 /// FMINIMUM/FMAXIMUM nodes propatate NaNs and signed zeroes using the
1485 /// llvm.minimum and llvm.maximum semantics.
1486 VECREDUCE_FMAXIMUM,
1487 VECREDUCE_FMINIMUM,
1488 /// Integer reductions may have a result type larger than the vector element
1489 /// type. However, the reduction is performed using the vector element type
1490 /// and the value in the top bits is unspecified.
1491 VECREDUCE_ADD,
1492 VECREDUCE_MUL,
1493 VECREDUCE_AND,
1494 VECREDUCE_OR,
1495 VECREDUCE_XOR,
1496 VECREDUCE_SMAX,
1497 VECREDUCE_SMIN,
1498 VECREDUCE_UMAX,
1499 VECREDUCE_UMIN,
1500
1501 // PARTIAL_REDUCE_[U|S]MLA(Accumulator, Input1, Input2)
1502 // The partial reduction nodes sign or zero extend Input1 and Input2
1503 // (with the extension kind noted below) to the element type of
1504 // Accumulator before multiplying their results.
1505 // This result is concatenated to the Accumulator, and this is then reduced,
1506 // using addition, to the result type.
1507 // The output is only expected to either be given to another partial reduction
1508 // operation or an equivalent vector reduce operation, so the order in which
1509 // the elements are reduced is deliberately not specified.
1510 // Input1 and Input2 must be the same type. Accumulator and the output must be
1511 // the same type.
1512 // The number of elements in Input1 and Input2 must be a positive integer
1513 // multiple of the number of elements in the Accumulator / output type.
1514 // Input1 and Input2 must have an element type which is the same as or smaller
1515 // than the element type of the Accumulator and output.
1516 PARTIAL_REDUCE_SMLA, // sext, sext
1517 PARTIAL_REDUCE_UMLA, // zext, zext
1518 PARTIAL_REDUCE_SUMLA, // sext, zext
1519
1520 // The `llvm.experimental.stackmap` intrinsic.
1521 // Operands: input chain, glue, <id>, <numShadowBytes>, [live0[, live1...]]
1522 // Outputs: output chain, glue
1523 STACKMAP,
1524
1525 // The `llvm.experimental.patchpoint.*` intrinsic.
1526 // Operands: input chain, [glue], reg-mask, <id>, <numShadowBytes>, callee,
1527 // <numArgs>, cc, ...
1528 // Outputs: [rv], output chain, glue
1529 PATCHPOINT,
1530
1531 // PTRADD represents pointer arithmetic semantics, for targets that opt in
1532 // using shouldPreservePtrArith().
1533 // ptr = PTRADD ptr, offset
1534 PTRADD,
1535
1536// Vector Predication
1537#define BEGIN_REGISTER_VP_SDNODE(VPSDID, ...) VPSDID,
1538#include "llvm/IR/VPIntrinsics.def"
1539
1540 // The `llvm.experimental.convergence.*` intrinsics.
1541 CONVERGENCECTRL_ANCHOR,
1542 CONVERGENCECTRL_ENTRY,
1543 CONVERGENCECTRL_LOOP,
1544 // This does not correspond to any convergence control intrinsic. It is used
1545 // to glue a convergence control token to a convergent operation in the DAG,
1546 // which is later translated to an implicit use in the MIR.
1547 CONVERGENCECTRL_GLUE,
1548
1549 // Experimental vector histogram intrinsic
1550 // Operands: Input Chain, Inc, Mask, Base, Index, Scale, ID
1551 // Output: Output Chain
1552 EXPERIMENTAL_VECTOR_HISTOGRAM,
1553
1554 // Finds the index of the last active mask element
1555 // Operands: Mask
1556 VECTOR_FIND_LAST_ACTIVE,
1557
1558 // GET_ACTIVE_LANE_MASK - this corrosponds to the llvm.get.active.lane.mask
1559 // intrinsic. It creates a mask representing active and inactive vector
1560 // lanes, active while Base + index < Trip Count. As with the intrinsic,
1561 // the operands Base and Trip Count have the same scalar integer type and
1562 // the internal addition of Base + index cannot overflow. However, the ISD
1563 // node supports result types which are wider than i1, where the high
1564 // bits conform to getBooleanContents similar to the SETCC operator.
1565 GET_ACTIVE_LANE_MASK,
1566
1567 // The `llvm.loop.dependence.{war, raw}.mask` intrinsics
1568 // Operands: Load pointer, Store pointer, Element size
1569 // Output: Mask
1572
1573 // llvm.clear_cache intrinsic
1574 // Operands: Input Chain, Start Addres, End Address
1575 // Outputs: Output Chain
1577
1578 /// BUILTIN_OP_END - This must be the last enum value in this list.
1579 /// The target-specific pre-isel opcode values start here.
1581};
1582
1583/// Whether this is bitwise logic opcode.
1584inline bool isBitwiseLogicOp(unsigned Opcode) {
1585 return Opcode == ISD::AND || Opcode == ISD::OR || Opcode == ISD::XOR;
1586}
1587
1588/// Given a \p MinMaxOpc of ISD::(U|S)MIN or ISD::(U|S)MAX, returns
1589/// ISD::(U|S)MAX and ISD::(U|S)MIN, respectively.
1590LLVM_ABI NodeType getInverseMinMaxOpcode(unsigned MinMaxOpc);
1591
1592/// Get underlying scalar opcode for VECREDUCE opcode.
1593/// For example ISD::AND for ISD::VECREDUCE_AND.
1594LLVM_ABI NodeType getVecReduceBaseOpcode(unsigned VecReduceOpcode);
1595
1596/// Whether this is a vector-predicated Opcode.
1597LLVM_ABI bool isVPOpcode(unsigned Opcode);
1598
1599/// Whether this is a vector-predicated binary operation opcode.
1600LLVM_ABI bool isVPBinaryOp(unsigned Opcode);
1601
1602/// Whether this is a vector-predicated reduction opcode.
1603LLVM_ABI bool isVPReduction(unsigned Opcode);
1604
1605/// The operand position of the vector mask.
1606LLVM_ABI std::optional<unsigned> getVPMaskIdx(unsigned Opcode);
1607
1608/// The operand position of the explicit vector length parameter.
1609LLVM_ABI std::optional<unsigned> getVPExplicitVectorLengthIdx(unsigned Opcode);
1610
1611/// Translate this VP Opcode to its corresponding non-VP Opcode.
1612LLVM_ABI std::optional<unsigned> getBaseOpcodeForVP(unsigned Opcode,
1613 bool hasFPExcept);
1614
1615/// Translate this non-VP Opcode to its corresponding VP Opcode.
1616LLVM_ABI std::optional<unsigned> getVPForBaseOpcode(unsigned Opcode);
1617
1618//===--------------------------------------------------------------------===//
1619/// MemIndexedMode enum - This enum defines the load / store indexed
1620/// addressing modes.
1621///
1622/// UNINDEXED "Normal" load / store. The effective address is already
1623/// computed and is available in the base pointer. The offset
1624/// operand is always undefined. In addition to producing a
1625/// chain, an unindexed load produces one value (result of the
1626/// load); an unindexed store does not produce a value.
1627///
1628/// PRE_INC Similar to the unindexed mode where the effective address is
1629/// PRE_DEC the value of the base pointer add / subtract the offset.
1630/// It considers the computation as being folded into the load /
1631/// store operation (i.e. the load / store does the address
1632/// computation as well as performing the memory transaction).
1633/// The base operand is always undefined. In addition to
1634/// producing a chain, pre-indexed load produces two values
1635/// (result of the load and the result of the address
1636/// computation); a pre-indexed store produces one value (result
1637/// of the address computation).
1638///
1639/// POST_INC The effective address is the value of the base pointer. The
1640/// POST_DEC value of the offset operand is then added to / subtracted
1641/// from the base after memory transaction. In addition to
1642/// producing a chain, post-indexed load produces two values
1643/// (the result of the load and the result of the base +/- offset
1644/// computation); a post-indexed store produces one value (the
1645/// the result of the base +/- offset computation).
1647
1648static const int LAST_INDEXED_MODE = POST_DEC + 1;
1649
1650//===--------------------------------------------------------------------===//
1651/// MemIndexType enum - This enum defines how to interpret MGATHER/SCATTER's
1652/// index parameter when calculating addresses.
1653///
1654/// SIGNED_SCALED Addr = Base + ((signed)Index * Scale)
1655/// UNSIGNED_SCALED Addr = Base + ((unsigned)Index * Scale)
1656///
1657/// NOTE: The value of Scale is typically only known to the node owning the
1658/// IndexType, with a value of 1 the equivalent of being unscaled.
1660
1662
1663inline bool isIndexTypeSigned(MemIndexType IndexType) {
1664 return IndexType == SIGNED_SCALED;
1665}
1666
1667//===--------------------------------------------------------------------===//
1668/// LoadExtType enum - This enum defines the three variants of LOADEXT
1669/// (load with extension).
1670///
1671/// SEXTLOAD loads the integer operand and sign extends it to a larger
1672/// integer result type.
1673/// ZEXTLOAD loads the integer operand and zero extends it to a larger
1674/// integer result type.
1675/// EXTLOAD is used for two things: floating point extending loads and
1676/// integer extending loads [the top bits are undefined].
1678
1679static const int LAST_LOADEXT_TYPE = ZEXTLOAD + 1;
1680
1682
1683//===--------------------------------------------------------------------===//
1684/// ISD::CondCode enum - These are ordered carefully to make the bitfields
1685/// below work out, when considering SETFALSE (something that never exists
1686/// dynamically) as 0. "U" -> Unsigned (for integer operands) or Unordered
1687/// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal
1688/// to. If the "N" column is 1, the result of the comparison is undefined if
1689/// the input is a NAN.
1690///
1691/// All of these (except for the 'always folded ops') should be handled for
1692/// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT,
1693/// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used.
1694///
1695/// Note that these are laid out in a specific order to allow bit-twiddling
1696/// to transform conditions.
1698 // Opcode N U L G E Intuitive operation
1699 SETFALSE, // 0 0 0 0 Always false (always folded)
1700 SETOEQ, // 0 0 0 1 True if ordered and equal
1701 SETOGT, // 0 0 1 0 True if ordered and greater than
1702 SETOGE, // 0 0 1 1 True if ordered and greater than or equal
1703 SETOLT, // 0 1 0 0 True if ordered and less than
1704 SETOLE, // 0 1 0 1 True if ordered and less than or equal
1705 SETONE, // 0 1 1 0 True if ordered and operands are unequal
1706 SETO, // 0 1 1 1 True if ordered (no nans)
1707 SETUO, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
1708 SETUEQ, // 1 0 0 1 True if unordered or equal
1709 SETUGT, // 1 0 1 0 True if unordered or greater than
1710 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal
1711 SETULT, // 1 1 0 0 True if unordered or less than
1712 SETULE, // 1 1 0 1 True if unordered, less than, or equal
1713 SETUNE, // 1 1 1 0 True if unordered or not equal
1714 SETTRUE, // 1 1 1 1 Always true (always folded)
1715 // Don't care operations: undefined if the input is a nan.
1716 SETFALSE2, // 1 X 0 0 0 Always false (always folded)
1717 SETEQ, // 1 X 0 0 1 True if equal
1718 SETGT, // 1 X 0 1 0 True if greater than
1719 SETGE, // 1 X 0 1 1 True if greater than or equal
1720 SETLT, // 1 X 1 0 0 True if less than
1721 SETLE, // 1 X 1 0 1 True if less than or equal
1722 SETNE, // 1 X 1 1 0 True if not equal
1723 SETTRUE2, // 1 X 1 1 1 Always true (always folded)
1724
1725 SETCC_INVALID // Marker value.
1726};
1727
1728/// Return true if this is a setcc instruction that performs a signed
1729/// comparison when used with integer operands.
1730inline bool isSignedIntSetCC(CondCode Code) {
1731 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE;
1732}
1733
1734/// Return true if this is a setcc instruction that performs an unsigned
1735/// comparison when used with integer operands.
1736inline bool isUnsignedIntSetCC(CondCode Code) {
1737 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE;
1738}
1739
1740/// Return true if this is a setcc instruction that performs an equality
1741/// comparison when used with integer operands.
1742inline bool isIntEqualitySetCC(CondCode Code) {
1743 return Code == SETEQ || Code == SETNE;
1744}
1745
1746/// Return true if this is a setcc instruction that performs an equality
1747/// comparison when used with floating point operands.
1748inline bool isFPEqualitySetCC(CondCode Code) {
1749 return Code == SETOEQ || Code == SETONE || Code == SETUEQ || Code == SETUNE;
1750}
1751
1752/// Return true if the specified condition returns true if the two operands to
1753/// the condition are equal. Note that if one of the two operands is a NaN,
1754/// this value is meaningless.
1755inline bool isTrueWhenEqual(CondCode Cond) { return ((int)Cond & 1) != 0; }
1756
1757/// This function returns 0 if the condition is always false if an operand is
1758/// a NaN, 1 if the condition is always true if the operand is a NaN, and 2 if
1759/// the condition is undefined if the operand is a NaN.
1761 return ((int)Cond >> 3) & 3;
1762}
1763
1764/// Return the operation corresponding to !(X op Y), where 'op' is a valid
1765/// SetCC operation.
1766LLVM_ABI CondCode getSetCCInverse(CondCode Operation, EVT Type);
1767
1768inline bool isExtOpcode(unsigned Opcode) {
1769 return Opcode == ISD::ANY_EXTEND || Opcode == ISD::ZERO_EXTEND ||
1770 Opcode == ISD::SIGN_EXTEND;
1771}
1772
1773inline bool isExtVecInRegOpcode(unsigned Opcode) {
1774 return Opcode == ISD::ANY_EXTEND_VECTOR_INREG ||
1777}
1778
1779namespace GlobalISel {
1780/// Return the operation corresponding to !(X op Y), where 'op' is a valid
1781/// SetCC operation. The U bit of the condition code has different meanings
1782/// between floating point and integer comparisons and LLT's don't provide
1783/// this distinction. As such we need to be told whether the comparison is
1784/// floating point or integer-like. Pointers should use integer-like
1785/// comparisons.
1787} // end namespace GlobalISel
1788
1789/// Return the operation corresponding to (Y op X) when given the operation
1790/// for (X op Y).
1792
1793/// Return the result of a logical OR between different comparisons of
1794/// identical values: ((X op1 Y) | (X op2 Y)). This function returns
1795/// SETCC_INVALID if it is not possible to represent the resultant comparison.
1797
1798/// Return the result of a logical AND between different comparisons of
1799/// identical values: ((X op1 Y) & (X op2 Y)). This function returns
1800/// SETCC_INVALID if it is not possible to represent the resultant comparison.
1802
1803} // namespace ISD
1804
1805} // namespace llvm
1806
1807#endif
#define LLVM_ABI
Definition Compiler.h:213
PowerPC Reduce CR logical Operation
const SmallVectorImpl< MachineOperand > & Cond
#define ATOMIC_STORE(x, y)
#define ATOMIC_LOAD(x)
The instances of the Type class are immutable: once they are created, they are never changed.
Definition Type.h:45
LLVM_ABI CondCode getSetCCInverse(CondCode Operation, bool isIntegerLike)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
ISD namespace - This namespace contains an enum which represents all of the SelectionDAG node types a...
Definition ISDOpcodes.h:24
LLVM_ABI CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, EVT Type)
Return the result of a logical AND between different comparisons of identical values: ((X op1 Y) & (X...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition ISDOpcodes.h:41
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition ISDOpcodes.h:807
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition ISDOpcodes.h:256
@ CTLZ_ZERO_UNDEF
Definition ISDOpcodes.h:780
@ TargetConstantPool
Definition ISDOpcodes.h:184
@ STRICT_FSETCC
STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used for floating-point operands only.
Definition ISDOpcodes.h:504
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
Definition ISDOpcodes.h:45
@ POISON
POISON - A poison node.
Definition ISDOpcodes.h:231
@ LOOP_DEPENDENCE_RAW_MASK
@ EH_SJLJ_LONGJMP
OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.longjmp intrinsic.
Definition ISDOpcodes.h:163
@ FGETSIGN
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
Definition ISDOpcodes.h:531
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
Definition ISDOpcodes.h:270
@ INSERT_SUBVECTOR
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1.
Definition ISDOpcodes.h:593
@ BSWAP
Byte Swap and Counting operators.
Definition ISDOpcodes.h:771
@ SMULFIX
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition ISDOpcodes.h:387
@ TargetBlockAddress
Definition ISDOpcodes.h:186
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
Definition ISDOpcodes.h:289
@ FRAME_TO_ARGS_OFFSET
FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to first (possible) on-stack ar...
Definition ISDOpcodes.h:140
@ FMAD
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.
Definition ISDOpcodes.h:515
@ ADD
Simple integer binary arithmetic operators.
Definition ISDOpcodes.h:259
@ SMULFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition ISDOpcodes.h:393
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition ISDOpcodes.h:841
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
Definition ISDOpcodes.h:511
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
Definition ISDOpcodes.h:215
@ EH_SJLJ_SETUP_DISPATCH
OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) The target initializes the dispatch table here.
Definition ISDOpcodes.h:167
@ GlobalAddress
Definition ISDOpcodes.h:88
@ STRICT_FMINIMUM
Definition ISDOpcodes.h:464
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition ISDOpcodes.h:868
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
Definition ISDOpcodes.h:577
@ FADD
Simple binary floating point operators.
Definition ISDOpcodes.h:410
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
Definition ISDOpcodes.h:744
@ SIGN_EXTEND_VECTOR_INREG
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
Definition ISDOpcodes.h:898
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition ISDOpcodes.h:275
@ FMULADD
FMULADD - Performs a * b + c, with, or without, intermediate rounding.
Definition ISDOpcodes.h:521
@ FPTRUNC_ROUND
FPTRUNC_ROUND - This corresponds to the fptrunc_round intrinsic.
Definition ISDOpcodes.h:508
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition ISDOpcodes.h:249
@ SDIVFIX
RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on 2 integers with the same width...
Definition ISDOpcodes.h:400
@ STRICT_FSQRT
Constrained versions of libm-equivalent floating point intrinsics.
Definition ISDOpcodes.h:431
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
@ GlobalTLSAddress
Definition ISDOpcodes.h:89
@ EH_RETURN
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin,...
Definition ISDOpcodes.h:151
@ SIGN_EXTEND
Conversion operators.
Definition ISDOpcodes.h:832
@ AVGCEILS
AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an integer of type i[N+2],...
Definition ISDOpcodes.h:712
@ STRICT_UINT_TO_FP
Definition ISDOpcodes.h:478
@ SCALAR_TO_VECTOR
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
Definition ISDOpcodes.h:662
@ ADDROFRETURNADDR
ADDROFRETURNADDR - Represents the llvm.addressofreturnaddress intrinsic.
Definition ISDOpcodes.h:117
@ TargetExternalSymbol
Definition ISDOpcodes.h:185
@ CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
Definition ISDOpcodes.h:779
@ TargetJumpTable
Definition ISDOpcodes.h:183
@ TargetIndex
TargetIndex - Like a constant pool entry, but with completely target-dependent semantics.
Definition ISDOpcodes.h:193
@ TRUNCATE_SSAT_U
Definition ISDOpcodes.h:861
@ SETCCCARRY
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
Definition ISDOpcodes.h:815
@ SSUBO
Same for subtraction.
Definition ISDOpcodes.h:347
@ VECTOR_INTERLEAVE
VECTOR_INTERLEAVE(VEC1, VEC2, ...) - Returns N vectors from N input vectors, where N is the factor to...
Definition ISDOpcodes.h:628
@ STEP_VECTOR
STEP_VECTOR(IMM) - Returns a scalable vector whose lanes are comprised of a linear sequence of unsign...
Definition ISDOpcodes.h:688
@ FCANONICALIZE
Returns platform specific canonical encoding of a floating point number.
Definition ISDOpcodes.h:534
@ IS_FPCLASS
Performs a check of floating point class property, defined by IEEE-754.
Definition ISDOpcodes.h:541
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
Definition ISDOpcodes.h:369
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition ISDOpcodes.h:784
@ UNDEF
UNDEF - An undefined node.
Definition ISDOpcodes.h:228
@ EXTRACT_ELEMENT
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...
Definition ISDOpcodes.h:242
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
Definition ISDOpcodes.h:669
@ AssertAlign
AssertAlign - These nodes record if a register contains a value that has a known alignment and the tr...
Definition ISDOpcodes.h:69
@ BasicBlock
Various leaf nodes.
Definition ISDOpcodes.h:81
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition ISDOpcodes.h:225
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition ISDOpcodes.h:343
@ TargetGlobalAddress
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
Definition ISDOpcodes.h:180
@ GET_ROUNDING
Returns current rounding mode: -1 Undefined 0 Round to 0 1 Round to nearest, ties to even 2 Round to ...
Definition ISDOpcodes.h:958
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
Definition ISDOpcodes.h:701
@ SHL
Shift and rotation operations.
Definition ISDOpcodes.h:762
@ AssertNoFPClass
AssertNoFPClass - These nodes record if a register contains a float value that is known to be not som...
Definition ISDOpcodes.h:78
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition ISDOpcodes.h:642
@ PtrAuthGlobalAddress
A ptrauth constant.
Definition ISDOpcodes.h:100
@ EXTRACT_SUBVECTOR
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
Definition ISDOpcodes.h:607
@ STRICT_FMAXIMUM
Definition ISDOpcodes.h:463
@ EntryToken
EntryToken - This is the marker used to indicate the start of a region.
Definition ISDOpcodes.h:48
@ READ_REGISTER
READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on the DAG, which implements the n...
Definition ISDOpcodes.h:134
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition ISDOpcodes.h:569
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
Definition ISDOpcodes.h:219
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition ISDOpcodes.h:838
@ TargetConstantFP
Definition ISDOpcodes.h:175
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition ISDOpcodes.h:799
@ LOCAL_RECOVER
LOCAL_RECOVER - Represents the llvm.localrecover intrinsic.
Definition ISDOpcodes.h:130
@ SSHLSAT
RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.
Definition ISDOpcodes.h:379
@ SMULO
Same for multiplication.
Definition ISDOpcodes.h:351
@ TargetFrameIndex
Definition ISDOpcodes.h:182
@ ANY_EXTEND_VECTOR_INREG
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
Definition ISDOpcodes.h:887
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition ISDOpcodes.h:876
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
Definition ISDOpcodes.h:724
@ VECTOR_REVERSE
VECTOR_REVERSE(VECTOR) - Returns a vector, of the same type as VECTOR, whose elements are shuffled us...
Definition ISDOpcodes.h:633
@ SDIVFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition ISDOpcodes.h:406
@ GLOBAL_OFFSET_TABLE
The address of the GOT.
Definition ISDOpcodes.h:103
@ VSELECT
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
Definition ISDOpcodes.h:793
@ UADDO_CARRY
Carry-using nodes for multiple precision addition and subtraction.
Definition ISDOpcodes.h:323
@ STRICT_SINT_TO_FP
STRICT_[US]INT_TO_FP - Convert a signed or unsigned integer to a floating point value.
Definition ISDOpcodes.h:477
@ STRICT_FROUNDEVEN
Definition ISDOpcodes.h:457
@ EH_DWARF_CFA
EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical Frame Address (CFA),...
Definition ISDOpcodes.h:145
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
Definition ISDOpcodes.h:110
@ STRICT_FP_TO_UINT
Definition ISDOpcodes.h:471
@ STRICT_FP_ROUND
X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision ...
Definition ISDOpcodes.h:493
@ STRICT_FP_TO_SINT
STRICT_FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition ISDOpcodes.h:470
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition ISDOpcodes.h:914
@ TargetConstant
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification,...
Definition ISDOpcodes.h:174
@ STRICT_FP_EXTEND
X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition ISDOpcodes.h:498
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition ISDOpcodes.h:736
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition ISDOpcodes.h:200
@ SCMP
[US]CMP - 3-way comparison of signed or unsigned integers.
Definition ISDOpcodes.h:732
@ CARRY_FALSE
CARRY_FALSE - This node is used when folding other nodes, like ADDC/SUBC, which indicate the carry re...
Definition ISDOpcodes.h:280
@ AVGFLOORS
AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of type i[N+1],...
Definition ISDOpcodes.h:707
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
Definition ISDOpcodes.h:299
@ STRICT_FADD
Constrained versions of the binary floating point operators.
Definition ISDOpcodes.h:420
@ SPLAT_VECTOR_PARTS
SPLAT_VECTOR_PARTS(SCALAR1, SCALAR2, ...) - Returns a vector with the scalar values joined together a...
Definition ISDOpcodes.h:678
@ FREEZE
FREEZE - FREEZE(VAL) returns an arbitrary value if VAL is UNDEF (or is evaluated to UNDEF),...
Definition ISDOpcodes.h:236
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
Definition ISDOpcodes.h:558
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition ISDOpcodes.h:53
@ VECTOR_SPLICE
VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...
Definition ISDOpcodes.h:654
@ ExternalSymbol
Definition ISDOpcodes.h:93
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
Definition ISDOpcodes.h:947
@ VECTOR_COMPRESS
VECTOR_COMPRESS(Vec, Mask, Passthru) consecutively place vector elements based on mask e....
Definition ISDOpcodes.h:696
@ SPONENTRY
SPONENTRY - Represents the llvm.sponentry intrinsic.
Definition ISDOpcodes.h:122
@ ZERO_EXTEND_VECTOR_INREG
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
Definition ISDOpcodes.h:909
@ STRICT_FNEARBYINT
Definition ISDOpcodes.h:451
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...
Definition ISDOpcodes.h:933
@ EH_SJLJ_SETJMP
RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) This corresponds to the eh.sjlj....
Definition ISDOpcodes.h:157
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition ISDOpcodes.h:844
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
Definition ISDOpcodes.h:821
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
Definition ISDOpcodes.h:62
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition ISDOpcodes.h:527
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
Definition ISDOpcodes.h:360
@ VECTOR_DEINTERLEAVE
VECTOR_DEINTERLEAVE(VEC1, VEC2, ...) - Returns N vectors from N input vectors, where N is the factor ...
Definition ISDOpcodes.h:617
@ TRUNCATE_SSAT_S
TRUNCATE_[SU]SAT_[SU] - Truncate for saturated operand [SU] located in middle, prefix for SAT means i...
Definition ISDOpcodes.h:859
@ ABDS
ABDS/ABDU - Absolute difference - Return the absolute difference between two numbers interpreted as s...
Definition ISDOpcodes.h:719
@ TRUNCATE_USAT_U
Definition ISDOpcodes.h:863
@ SADDO_CARRY
Carry-using overflow-aware nodes for multiple precision addition and subtraction.
Definition ISDOpcodes.h:333
@ INTRINSIC_W_CHAIN
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition ISDOpcodes.h:208
@ TargetGlobalTLSAddress
Definition ISDOpcodes.h:181
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
Definition ISDOpcodes.h:549
@ LOOP_DEPENDENCE_WAR_MASK
Set rounding mode.
bool isIndexTypeSigned(MemIndexType IndexType)
bool isExtVecInRegOpcode(unsigned Opcode)
LLVM_ABI NodeType getExtForLoadExtType(bool IsFP, LoadExtType)
bool isFPEqualitySetCC(CondCode Code)
Return true if this is a setcc instruction that performs an equality comparison when used with floati...
bool isExtOpcode(unsigned Opcode)
static const int LAST_LOADEXT_TYPE
LLVM_ABI bool isVPBinaryOp(unsigned Opcode)
Whether this is a vector-predicated binary operation opcode.
LLVM_ABI CondCode getSetCCInverse(CondCode Operation, EVT Type)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
LLVM_ABI std::optional< unsigned > getBaseOpcodeForVP(unsigned Opcode, bool hasFPExcept)
Translate this VP Opcode to its corresponding non-VP Opcode.
bool isBitwiseLogicOp(unsigned Opcode)
Whether this is bitwise logic opcode.
bool isTrueWhenEqual(CondCode Cond)
Return true if the specified condition returns true if the two operands to the condition are equal.
LLVM_ABI std::optional< unsigned > getVPMaskIdx(unsigned Opcode)
The operand position of the vector mask.
static const int LAST_MEM_INDEX_TYPE
unsigned getUnorderedFlavor(CondCode Cond)
This function returns 0 if the condition is always false if an operand is a NaN, 1 if the condition i...
LLVM_ABI std::optional< unsigned > getVPExplicitVectorLengthIdx(unsigned Opcode)
The operand position of the explicit vector length parameter.
LLVM_ABI CondCode getSetCCSwappedOperands(CondCode Operation)
Return the operation corresponding to (Y op X) when given the operation for (X op Y).
LLVM_ABI std::optional< unsigned > getVPForBaseOpcode(unsigned Opcode)
Translate this non-VP Opcode to its corresponding VP Opcode.
MemIndexType
MemIndexType enum - This enum defines how to interpret MGATHER/SCATTER's index parameter when calcula...
bool isSignedIntSetCC(CondCode Code)
Return true if this is a setcc instruction that performs a signed comparison when used with integer o...
LLVM_ABI NodeType getInverseMinMaxOpcode(unsigned MinMaxOpc)
Given a MinMaxOpc of ISD::(U|S)MIN or ISD::(U|S)MAX, returns ISD::(U|S)MAX and ISD::(U|S)MIN,...
LLVM_ABI bool isVPReduction(unsigned Opcode)
Whether this is a vector-predicated reduction opcode.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
LLVM_ABI NodeType getVecReduceBaseOpcode(unsigned VecReduceOpcode)
Get underlying scalar opcode for VECREDUCE opcode.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
bool isUnsignedIntSetCC(CondCode Code)
Return true if this is a setcc instruction that performs an unsigned comparison when used with intege...
static const int LAST_INDEXED_MODE
LLVM_ABI bool isVPOpcode(unsigned Opcode)
Whether this is a vector-predicated Opcode.
LLVM_ABI CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, EVT Type)
Return the result of a logical OR between different comparisons of identical values: ((X op1 Y) | (X ...
bool isIntEqualitySetCC(CondCode Code)
Return true if this is a setcc instruction that performs an equality comparison when used with intege...
This is an optimization pass for GlobalISel generic memory operations.
Extended Value Type.
Definition ValueTypes.h:35