98void SelectionDAG::DAGNodeDeletedListener::anchor() {}
99void SelectionDAG::DAGNodeInsertedListener::anchor() {}
101#define DEBUG_TYPE "selectiondag"
105 cl::desc(
"Gang up loads and stores generated by inlining of memcpy"));
108 cl::desc(
"Number limit for gluing ld/st of memcpy."),
124 return getValueAPF().bitwiseIsEqual(V);
147 N->getValueType(0).getVectorElementType().getSizeInBits();
148 if (
auto *Op0 = dyn_cast<ConstantSDNode>(
N->getOperand(0))) {
149 SplatVal = Op0->getAPIntValue().
trunc(EltSize);
152 if (
auto *Op0 = dyn_cast<ConstantFPSDNode>(
N->getOperand(0))) {
153 SplatVal = Op0->getValueAPF().bitcastToAPInt().
trunc(EltSize);
158 auto *BV = dyn_cast<BuildVectorSDNode>(
N);
163 unsigned SplatBitSize;
165 unsigned EltSize =
N->getValueType(0).getVectorElementType().getSizeInBits();
170 const bool IsBigEndian =
false;
171 return BV->isConstantSplat(SplatVal, SplatUndef, SplatBitSize, HasUndefs,
172 EltSize, IsBigEndian) &&
173 EltSize == SplatBitSize;
182 N =
N->getOperand(0).getNode();
191 unsigned i = 0, e =
N->getNumOperands();
194 while (i != e &&
N->getOperand(i).isUndef())
198 if (i == e)
return false;
209 unsigned EltSize =
N->getValueType(0).getScalarSizeInBits();
211 if (CN->getAPIntValue().countr_one() < EltSize)
214 if (CFPN->getValueAPF().bitcastToAPInt().countr_one() < EltSize)
222 for (++i; i != e; ++i)
223 if (
N->getOperand(i) != NotZero && !
N->getOperand(i).isUndef())
231 N =
N->getOperand(0).getNode();
240 bool IsAllUndef =
true;
253 unsigned EltSize =
N->getValueType(0).getScalarSizeInBits();
255 if (CN->getAPIntValue().countr_zero() < EltSize)
258 if (CFPN->getValueAPF().bitcastToAPInt().countr_zero() < EltSize)
285 if (!isa<ConstantSDNode>(
Op))
298 if (!isa<ConstantFPSDNode>(
Op))
306 assert(
N->getValueType(0).isVector() &&
"Expected a vector!");
308 unsigned EltSize =
N->getValueType(0).getScalarSizeInBits();
309 if (EltSize <= NewEltSize)
313 return (
N->getOperand(0).getValueType().getScalarSizeInBits() <=
318 return (
N->getOperand(0).getValueType().getScalarSizeInBits() <=
328 if (!isa<ConstantSDNode>(
Op))
331 APInt C =
Op->getAsAPIntVal().trunc(EltSize);
332 if (
Signed &&
C.trunc(NewEltSize).sext(EltSize) !=
C)
334 if (!
Signed &&
C.trunc(NewEltSize).zext(EltSize) !=
C)
345 if (
N->getNumOperands() == 0)
351 return N->getOpcode() ==
ISD::FREEZE &&
N->getOperand(0).isUndef();
354template <
typename ConstNodeType>
356 std::function<
bool(ConstNodeType *)>
Match,
359 if (
auto *
C = dyn_cast<ConstNodeType>(
Op))
367 EVT SVT =
Op.getValueType().getScalarType();
369 if (AllowUndefs &&
Op.getOperand(i).isUndef()) {
375 auto *Cst = dyn_cast<ConstNodeType>(
Op.getOperand(i));
376 if (!Cst || Cst->getValueType(0) != SVT || !
Match(Cst))
382template bool ISD::matchUnaryPredicateImpl<ConstantSDNode>(
384template bool ISD::matchUnaryPredicateImpl<ConstantFPSDNode>(
390 bool AllowUndefs,
bool AllowTypeMismatch) {
391 if (!AllowTypeMismatch &&
LHS.getValueType() !=
RHS.getValueType())
395 if (
auto *LHSCst = dyn_cast<ConstantSDNode>(
LHS))
396 if (
auto *RHSCst = dyn_cast<ConstantSDNode>(
RHS))
397 return Match(LHSCst, RHSCst);
400 if (
LHS.getOpcode() !=
RHS.getOpcode() ||
405 EVT SVT =
LHS.getValueType().getScalarType();
406 for (
unsigned i = 0, e =
LHS.getNumOperands(); i != e; ++i) {
409 bool LHSUndef = AllowUndefs && LHSOp.
isUndef();
410 bool RHSUndef = AllowUndefs && RHSOp.
isUndef();
411 auto *LHSCst = dyn_cast<ConstantSDNode>(LHSOp);
412 auto *RHSCst = dyn_cast<ConstantSDNode>(RHSOp);
413 if ((!LHSCst && !LHSUndef) || (!RHSCst && !RHSUndef))
415 if (!AllowTypeMismatch && (LHSOp.
getValueType() != SVT ||
418 if (!
Match(LHSCst, RHSCst))
425 switch (VecReduceOpcode) {
430 case ISD::VP_REDUCE_FADD:
431 case ISD::VP_REDUCE_SEQ_FADD:
435 case ISD::VP_REDUCE_FMUL:
436 case ISD::VP_REDUCE_SEQ_FMUL:
439 case ISD::VP_REDUCE_ADD:
442 case ISD::VP_REDUCE_MUL:
445 case ISD::VP_REDUCE_AND:
448 case ISD::VP_REDUCE_OR:
451 case ISD::VP_REDUCE_XOR:
454 case ISD::VP_REDUCE_SMAX:
457 case ISD::VP_REDUCE_SMIN:
460 case ISD::VP_REDUCE_UMAX:
463 case ISD::VP_REDUCE_UMIN:
466 case ISD::VP_REDUCE_FMAX:
469 case ISD::VP_REDUCE_FMIN:
472 case ISD::VP_REDUCE_FMAXIMUM:
475 case ISD::VP_REDUCE_FMINIMUM:
484#define BEGIN_REGISTER_VP_SDNODE(VPSD, ...) \
487#include "llvm/IR/VPIntrinsics.def"
495#define BEGIN_REGISTER_VP_SDNODE(VPSD, ...) case ISD::VPSD:
496#define VP_PROPERTY_BINARYOP return true;
497#define END_REGISTER_VP_SDNODE(VPSD) break;
498#include "llvm/IR/VPIntrinsics.def"
507#define BEGIN_REGISTER_VP_SDNODE(VPSD, ...) case ISD::VPSD:
508#define VP_PROPERTY_REDUCTION(STARTPOS, ...) return true;
509#define END_REGISTER_VP_SDNODE(VPSD) break;
510#include "llvm/IR/VPIntrinsics.def"
520#define BEGIN_REGISTER_VP_SDNODE(VPSD, LEGALPOS, TDNAME, MASKPOS, ...) \
523#include "llvm/IR/VPIntrinsics.def"
532#define BEGIN_REGISTER_VP_SDNODE(VPSD, LEGALPOS, TDNAME, MASKPOS, EVLPOS) \
535#include "llvm/IR/VPIntrinsics.def"
545#define BEGIN_REGISTER_VP_SDNODE(VPOPC, ...) case ISD::VPOPC:
546#define VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) return ISD::SDOPC;
547#define END_REGISTER_VP_SDNODE(VPOPC) break;
548#include "llvm/IR/VPIntrinsics.def"
557#define BEGIN_REGISTER_VP_SDNODE(VPOPC, ...) break;
558#define VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) case ISD::SDOPC:
559#define END_REGISTER_VP_SDNODE(VPOPC) return ISD::VPOPC;
560#include "llvm/IR/VPIntrinsics.def"
607 bool isIntegerLike) {
632 bool IsInteger =
Type.isInteger();
637 unsigned Op = Op1 | Op2;
653 bool IsInteger =
Type.isInteger();
688 ID.AddPointer(VTList.
VTs);
694 for (
const auto &
Op : Ops) {
695 ID.AddPointer(
Op.getNode());
696 ID.AddInteger(
Op.getResNo());
703 for (
const auto &
Op : Ops) {
704 ID.AddPointer(
Op.getNode());
705 ID.AddInteger(
Op.getResNo());
718 switch (
N->getOpcode()) {
727 ID.AddPointer(
C->getConstantIntValue());
728 ID.AddBoolean(
C->isOpaque());
733 ID.AddPointer(cast<ConstantFPSDNode>(
N)->getConstantFPValue());
749 ID.AddInteger(cast<RegisterSDNode>(
N)->
getReg());
752 ID.AddPointer(cast<RegisterMaskSDNode>(
N)->getRegMask());
755 ID.AddPointer(cast<SrcValueSDNode>(
N)->getValue());
759 ID.AddInteger(cast<FrameIndexSDNode>(
N)->getIndex());
763 if (cast<LifetimeSDNode>(
N)->hasOffset()) {
764 ID.AddInteger(cast<LifetimeSDNode>(
N)->
getSize());
769 ID.AddInteger(cast<PseudoProbeSDNode>(
N)->getGuid());
770 ID.AddInteger(cast<PseudoProbeSDNode>(
N)->getIndex());
771 ID.AddInteger(cast<PseudoProbeSDNode>(
N)->getAttributes());
775 ID.AddInteger(cast<JumpTableSDNode>(
N)->getIndex());
776 ID.AddInteger(cast<JumpTableSDNode>(
N)->getTargetFlags());
781 ID.AddInteger(CP->getAlign().value());
782 ID.AddInteger(CP->getOffset());
783 if (CP->isMachineConstantPoolEntry())
784 CP->getMachineCPVal()->addSelectionDAGCSEId(
ID);
786 ID.AddPointer(CP->getConstVal());
787 ID.AddInteger(CP->getTargetFlags());
799 ID.AddInteger(LD->getMemoryVT().getRawBits());
800 ID.AddInteger(LD->getRawSubclassData());
801 ID.AddInteger(LD->getPointerInfo().getAddrSpace());
802 ID.AddInteger(LD->getMemOperand()->getFlags());
807 ID.AddInteger(ST->getMemoryVT().getRawBits());
808 ID.AddInteger(ST->getRawSubclassData());
809 ID.AddInteger(ST->getPointerInfo().getAddrSpace());
810 ID.AddInteger(ST->getMemOperand()->getFlags());
821 case ISD::VP_STORE: {
829 case ISD::EXPERIMENTAL_VP_STRIDED_LOAD: {
836 case ISD::EXPERIMENTAL_VP_STRIDED_STORE: {
843 case ISD::VP_GATHER: {
851 case ISD::VP_SCATTER: {
940 if (
auto *MN = dyn_cast<MemIntrinsicSDNode>(
N)) {
941 ID.AddInteger(MN->getRawSubclassData());
942 ID.AddInteger(MN->getPointerInfo().getAddrSpace());
943 ID.AddInteger(MN->getMemOperand()->getFlags());
944 ID.AddInteger(MN->getMemoryVT().getRawBits());
967 if (
N->getValueType(0) == MVT::Glue)
970 switch (
N->getOpcode()) {
978 for (
unsigned i = 1, e =
N->getNumValues(); i != e; ++i)
979 if (
N->getValueType(i) == MVT::Glue)
996 if (Node.use_empty())
1011 while (!DeadNodes.
empty()) {
1020 DUL->NodeDeleted(
N,
nullptr);
1023 RemoveNodeFromCSEMaps(
N);
1054 RemoveNodeFromCSEMaps(
N);
1058 DeleteNodeNotInCSEMaps(
N);
1061void SelectionDAG::DeleteNodeNotInCSEMaps(
SDNode *
N) {
1062 assert(
N->getIterator() != AllNodes.begin() &&
1063 "Cannot delete the entry node!");
1064 assert(
N->use_empty() &&
"Cannot delete a node that is not dead!");
1073 assert(!(V->isVariadic() && isParameter));
1075 ByvalParmDbgValues.push_back(V);
1077 DbgValues.push_back(V);
1078 for (
const SDNode *Node : V->getSDNodes())
1080 DbgValMap[Node].push_back(V);
1085 if (
I == DbgValMap.end())
1087 for (
auto &Val:
I->second)
1088 Val->setIsInvalidated();
1092void SelectionDAG::DeallocateNode(
SDNode *
N) {
1116 switch (
N->getOpcode()) {
1122 EVT VT =
N->getValueType(0);
1123 assert(
N->getNumValues() == 1 &&
"Too many results!");
1125 "Wrong return type!");
1126 assert(
N->getNumOperands() == 2 &&
"Wrong number of operands!");
1127 assert(
N->getOperand(0).getValueType() ==
N->getOperand(1).getValueType() &&
1128 "Mismatched operand types!");
1130 "Wrong operand type!");
1132 "Wrong return type size");
1136 assert(
N->getNumValues() == 1 &&
"Too many results!");
1137 assert(
N->getValueType(0).isVector() &&
"Wrong return type!");
1138 assert(
N->getNumOperands() ==
N->getValueType(0).getVectorNumElements() &&
1139 "Wrong number of operands!");
1140 EVT EltVT =
N->getValueType(0).getVectorElementType();
1142 assert((
Op.getValueType() == EltVT ||
1143 (EltVT.
isInteger() &&
Op.getValueType().isInteger() &&
1144 EltVT.
bitsLE(
Op.getValueType()))) &&
1145 "Wrong operand type!");
1146 assert(
Op.getValueType() ==
N->getOperand(0).getValueType() &&
1147 "Operands must all have the same type");
1159void SelectionDAG::InsertNode(
SDNode *
N) {
1160 AllNodes.push_back(
N);
1162 N->PersistentId = NextPersistentId++;
1165 for (DAGUpdateListener *DUL = UpdateListeners; DUL; DUL = DUL->Next)
1166 DUL->NodeInserted(
N);
1173bool SelectionDAG::RemoveNodeFromCSEMaps(
SDNode *
N) {
1174 bool Erased =
false;
1175 switch (
N->getOpcode()) {
1178 assert(CondCodeNodes[cast<CondCodeSDNode>(
N)->
get()] &&
1179 "Cond code doesn't exist!");
1180 Erased = CondCodeNodes[cast<CondCodeSDNode>(
N)->get()] !=
nullptr;
1181 CondCodeNodes[cast<CondCodeSDNode>(
N)->get()] =
nullptr;
1184 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(
N)->getSymbol());
1188 Erased = TargetExternalSymbols.erase(std::pair<std::string, unsigned>(
1193 auto *MCSN = cast<MCSymbolSDNode>(
N);
1194 Erased = MCSymbols.erase(MCSN->getMCSymbol());
1198 EVT VT = cast<VTSDNode>(
N)->getVT();
1200 Erased = ExtendedValueTypeNodes.erase(VT);
1211 Erased = CSEMap.RemoveNode(
N);
1218 if (!Erased &&
N->getValueType(
N->getNumValues()-1) != MVT::Glue &&
1233SelectionDAG::AddModifiedNodeToCSEMaps(
SDNode *
N) {
1237 SDNode *Existing = CSEMap.GetOrInsertNode(
N);
1238 if (Existing !=
N) {
1245 for (DAGUpdateListener *DUL = UpdateListeners; DUL; DUL = DUL->Next)
1246 DUL->NodeDeleted(
N, Existing);
1247 DeleteNodeNotInCSEMaps(
N);
1253 for (DAGUpdateListener *DUL = UpdateListeners; DUL; DUL = DUL->Next)
1254 DUL->NodeUpdated(
N);
1272 Node->intersectFlagsWith(
N->getFlags());
1292 Node->intersectFlagsWith(
N->getFlags());
1310 Node->intersectFlagsWith(
N->getFlags());
1323 : TM(tm), OptLevel(OL), EntryNode(ISD::EntryToken, 0,
DebugLoc(),
1326 InsertNode(&EntryNode);
1337 SDAGISelPass = PassPtr;
1341 LibInfo = LibraryInfo;
1346 FnVarLocs = VarLocs;
1350 assert(!UpdateListeners &&
"Dangling registered DAGUpdateListeners");
1352 OperandRecycler.clear(OperandAllocator);
1361void SelectionDAG::allnodes_clear() {
1362 assert(&*AllNodes.begin() == &EntryNode);
1363 AllNodes.remove(AllNodes.begin());
1364 while (!AllNodes.empty())
1365 DeallocateNode(&AllNodes.front());
1367 NextPersistentId = 0;
1373 SDNode *
N = CSEMap.FindNodeOrInsertPos(
ID, InsertPos);
1375 switch (
N->getOpcode()) {
1380 "debug location. Use another overload.");
1387 const SDLoc &
DL,
void *&InsertPos) {
1388 SDNode *
N = CSEMap.FindNodeOrInsertPos(
ID, InsertPos);
1390 switch (
N->getOpcode()) {
1396 if (
N->getDebugLoc() !=
DL.getDebugLoc())
1403 if (
DL.getIROrder() &&
DL.getIROrder() <
N->getIROrder())
1404 N->setDebugLoc(
DL.getDebugLoc());
1413 OperandRecycler.clear(OperandAllocator);
1414 OperandAllocator.
Reset();
1417 ExtendedValueTypeNodes.clear();
1418 ExternalSymbols.clear();
1419 TargetExternalSymbols.clear();
1422 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(),
nullptr);
1423 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(),
nullptr);
1425 EntryNode.UseList =
nullptr;
1426 InsertNode(&EntryNode);
1432 return VT.
bitsGT(
Op.getValueType())
1438std::pair<SDValue, SDValue>
1442 "Strict no-op FP extend/round not allowed.");
1449 return std::pair<SDValue, SDValue>(Res,
SDValue(Res.
getNode(), 1));
1453 return VT.
bitsGT(
Op.getValueType()) ?
1459 return VT.
bitsGT(
Op.getValueType()) ?
1465 return VT.
bitsGT(
Op.getValueType()) ?
1473 auto Type =
Op.getValueType();
1477 auto Size =
Op.getValueSizeInBits();
1488 auto Type =
Op.getValueType();
1492 auto Size =
Op.getValueSizeInBits();
1503 auto Type =
Op.getValueType();
1507 auto Size =
Op.getValueSizeInBits();
1525 EVT OpVT =
Op.getValueType();
1527 "Cannot getZeroExtendInReg FP types");
1529 "getZeroExtendInReg type should be vector iff the operand "
1533 "Vector element counts must match in getZeroExtendInReg");
1545 EVT OpVT =
Op.getValueType();
1547 "Cannot getVPZeroExtendInReg FP types");
1549 "getVPZeroExtendInReg type and operand type should be vector!");
1551 "Vector element counts must match in getZeroExtendInReg");
1590 return getNode(ISD::VP_XOR,
DL, VT, Val, TrueValue, Mask, EVL);
1601 return getNode(ISD::VP_ZERO_EXTEND,
DL, VT,
Op, Mask, EVL);
1603 return getNode(ISD::VP_TRUNCATE,
DL, VT,
Op, Mask, EVL);
1623 bool isT,
bool isO) {
1627 "getConstant with a uint64_t value that doesn't fit in the type!");
1632 bool isT,
bool isO) {
1633 return getConstant(*ConstantInt::get(*Context, Val),
DL, VT, isT, isO);
1637 EVT VT,
bool isT,
bool isO) {
1655 Elt = ConstantInt::get(*
getContext(), NewVal);
1674 "Can only handle an even split!");
1678 for (
unsigned i = 0; i != Parts; ++i)
1680 NewVal.
extractBits(ViaEltSizeInBits, i * ViaEltSizeInBits),
DL,
1681 ViaEltVT, isT, isO));
1686 unsigned ViaVecNumElts = VT.
getSizeInBits() / ViaEltSizeInBits;
1697 NewVal.
extractBits(ViaEltSizeInBits, i * ViaEltSizeInBits),
DL,
1698 ViaEltVT, isT, isO));
1703 std::reverse(EltParts.
begin(), EltParts.
end());
1722 "APInt size does not match type size!");
1731 if ((
N = FindNodeOrInsertPos(
ID,
DL, IP)))
1736 N = newSDNode<ConstantSDNode>(isT, isO, Elt, VTs);
1737 CSEMap.InsertNode(
N, IP);
1754 const SDLoc &
DL,
bool LegalTypes) {
1761 const SDLoc &
DL,
bool LegalTypes) {
1777 EVT VT,
bool isTarget) {
1792 if ((
N = FindNodeOrInsertPos(
ID,
DL, IP)))
1797 N = newSDNode<ConstantFPSDNode>(isTarget, &V, VTs);
1798 CSEMap.InsertNode(
N, IP);
1812 if (EltVT == MVT::f32)
1814 if (EltVT == MVT::f64)
1816 if (EltVT == MVT::f80 || EltVT == MVT::f128 || EltVT == MVT::ppcf128 ||
1817 EltVT == MVT::f16 || EltVT == MVT::bf16) {
1828 EVT VT, int64_t
Offset,
bool isTargetGA,
1829 unsigned TargetFlags) {
1830 assert((TargetFlags == 0 || isTargetGA) &&
1831 "Cannot set target flags on target-independent globals");
1849 ID.AddInteger(TargetFlags);
1851 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP))
1854 auto *
N = newSDNode<GlobalAddressSDNode>(
1855 Opc,
DL.getIROrder(),
DL.getDebugLoc(), GV, VTs,
Offset, TargetFlags);
1856 CSEMap.InsertNode(
N, IP);
1868 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
1871 auto *
N = newSDNode<FrameIndexSDNode>(FI, VTs, isTarget);
1872 CSEMap.InsertNode(
N, IP);
1878 unsigned TargetFlags) {
1879 assert((TargetFlags == 0 || isTarget) &&
1880 "Cannot set target flags on target-independent jump tables");
1886 ID.AddInteger(TargetFlags);
1888 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
1891 auto *
N = newSDNode<JumpTableSDNode>(JTI, VTs, isTarget, TargetFlags);
1892 CSEMap.InsertNode(
N, IP);
1906 bool isTarget,
unsigned TargetFlags) {
1907 assert((TargetFlags == 0 || isTarget) &&
1908 "Cannot set target flags on target-independent globals");
1917 ID.AddInteger(Alignment->value());
1920 ID.AddInteger(TargetFlags);
1922 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
1925 auto *
N = newSDNode<ConstantPoolSDNode>(isTarget,
C, VTs,
Offset, *Alignment,
1927 CSEMap.InsertNode(
N, IP);
1936 bool isTarget,
unsigned TargetFlags) {
1937 assert((TargetFlags == 0 || isTarget) &&
1938 "Cannot set target flags on target-independent globals");
1945 ID.AddInteger(Alignment->value());
1947 C->addSelectionDAGCSEId(
ID);
1948 ID.AddInteger(TargetFlags);
1950 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
1953 auto *
N = newSDNode<ConstantPoolSDNode>(isTarget,
C, VTs,
Offset, *Alignment,
1955 CSEMap.InsertNode(
N, IP);
1965 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
1968 auto *
N = newSDNode<BasicBlockSDNode>(
MBB);
1969 CSEMap.InsertNode(
N, IP);
1976 ValueTypeNodes.size())
1983 N = newSDNode<VTSDNode>(VT);
1991 N = newSDNode<ExternalSymbolSDNode>(
false,
Sym, 0,
getVTList(VT));
2006 unsigned TargetFlags) {
2008 TargetExternalSymbols[std::pair<std::string, unsigned>(
Sym, TargetFlags)];
2010 N = newSDNode<ExternalSymbolSDNode>(
true,
Sym, TargetFlags,
getVTList(VT));
2016 if ((
unsigned)
Cond >= CondCodeNodes.size())
2017 CondCodeNodes.resize(
Cond+1);
2019 if (!CondCodeNodes[
Cond]) {
2020 auto *
N = newSDNode<CondCodeSDNode>(
Cond);
2021 CondCodeNodes[
Cond] =
N;
2031 "APInt size does not match type size!");
2049 if (EC.isScalable())
2062 const APInt &StepVal) {
2086 "Must have the same number of vector elements as mask elements!");
2088 "Invalid VECTOR_SHUFFLE");
2096 int NElts = Mask.size();
2098 [&](
int M) {
return M < (NElts * 2) && M >= -1; }) &&
2099 "Index out of range");
2107 for (
int i = 0; i != NElts; ++i)
2108 if (MaskVec[i] >= NElts) MaskVec[i] -= NElts;
2124 for (
int i = 0; i < NElts; ++i) {
2125 if (MaskVec[i] <
Offset || MaskVec[i] >= (
Offset + NElts))
2129 if (UndefElements[MaskVec[i] -
Offset]) {
2135 if (!UndefElements[i])
2139 if (
auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
2140 BlendSplat(N1BV, 0);
2141 if (
auto *N2BV = dyn_cast<BuildVectorSDNode>(N2))
2142 BlendSplat(N2BV, NElts);
2147 bool AllLHS =
true, AllRHS =
true;
2149 for (
int i = 0; i != NElts; ++i) {
2150 if (MaskVec[i] >= NElts) {
2155 }
else if (MaskVec[i] >= 0) {
2159 if (AllLHS && AllRHS)
2161 if (AllLHS && !N2Undef)
2174 bool Identity =
true, AllSame =
true;
2175 for (
int i = 0; i != NElts; ++i) {
2176 if (MaskVec[i] >= 0 && MaskVec[i] != i) Identity =
false;
2177 if (MaskVec[i] != MaskVec[0]) AllSame =
false;
2179 if (Identity && NElts)
2189 V = V->getOperand(0);
2192 if (
auto *BV = dyn_cast<BuildVectorSDNode>(V)) {
2212 if (AllSame && SameNumElts) {
2213 EVT BuildVT = BV->getValueType(0);
2230 for (
int i = 0; i != NElts; ++i)
2231 ID.AddInteger(MaskVec[i]);
2234 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
2240 int *MaskAlloc = OperandAllocator.
Allocate<
int>(NElts);
2243 auto *
N = newSDNode<ShuffleVectorSDNode>(VTs, dl.
getIROrder(),
2245 createOperands(
N, Ops);
2247 CSEMap.InsertNode(
N, IP);
2268 ID.AddInteger(RegNo);
2270 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2273 auto *
N = newSDNode<RegisterSDNode>(RegNo, VTs);
2275 CSEMap.InsertNode(
N, IP);
2283 ID.AddPointer(RegMask);
2285 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2288 auto *
N = newSDNode<RegisterMaskSDNode>(RegMask);
2289 CSEMap.InsertNode(
N, IP);
2304 ID.AddPointer(Label);
2306 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2311 createOperands(
N, Ops);
2313 CSEMap.InsertNode(
N, IP);
2319 int64_t
Offset,
bool isTarget,
2320 unsigned TargetFlags) {
2328 ID.AddInteger(TargetFlags);
2330 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2333 auto *
N = newSDNode<BlockAddressSDNode>(Opc, VTs, BA,
Offset, TargetFlags);
2334 CSEMap.InsertNode(
N, IP);
2345 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2348 auto *
N = newSDNode<SrcValueSDNode>(V);
2349 CSEMap.InsertNode(
N, IP);
2360 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2363 auto *
N = newSDNode<MDNodeSDNode>(MD);
2364 CSEMap.InsertNode(
N, IP);
2370 if (VT == V.getValueType())
2377 unsigned SrcAS,
unsigned DestAS) {
2382 ID.AddInteger(SrcAS);
2383 ID.AddInteger(DestAS);
2386 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
2390 VTs, SrcAS, DestAS);
2391 createOperands(
N, Ops);
2393 CSEMap.InsertNode(
N, IP);
2405 EVT OpTy =
Op.getValueType();
2407 if (OpTy == ShTy || OpTy.
isVector())
return Op;
2415 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2416 EVT VT = Node->getValueType(0);
2417 SDValue Tmp1 = Node->getOperand(0);
2418 SDValue Tmp2 = Node->getOperand(1);
2419 const MaybeAlign MA(Node->getConstantOperandVal(3));
2451 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2452 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2463 Align RedAlign = UseABI ?
DL.getABITypeAlign(Ty) :
DL.getPrefTypeAlign(Ty);
2473 if (RedAlign > StackAlign) {
2476 unsigned NumIntermediates;
2478 NumIntermediates, RegisterVT);
2480 Align RedAlign2 = UseABI ?
DL.getABITypeAlign(Ty) :
DL.getPrefTypeAlign(Ty);
2481 if (RedAlign2 < RedAlign)
2482 RedAlign = RedAlign2;
2497 false,
nullptr, StackID);
2512 "Don't know how to choose the maximum size when creating a stack "
2521 Align Align = std::max(
DL.getPrefTypeAlign(Ty1),
DL.getPrefTypeAlign(Ty2));
2529 auto GetUndefBooleanConstant = [&]() {
2568 return GetUndefBooleanConstant();
2573 return GetUndefBooleanConstant();
2582 const APInt &C2 = N2C->getAPIntValue();
2584 const APInt &C1 = N1C->getAPIntValue();
2591 auto *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2592 auto *N2CFP = dyn_cast<ConstantFPSDNode>(N2);
2594 if (N1CFP && N2CFP) {
2599 return GetUndefBooleanConstant();
2604 return GetUndefBooleanConstant();
2610 return GetUndefBooleanConstant();
2615 return GetUndefBooleanConstant();
2620 return GetUndefBooleanConstant();
2626 return GetUndefBooleanConstant();
2655 return getSetCC(dl, VT, N2, N1, SwappedCond);
2656 }
else if ((N2CFP && N2CFP->getValueAPF().isNaN()) ||
2671 return GetUndefBooleanConstant();
2682 unsigned BitWidth =
Op.getScalarValueSizeInBits();
2690 unsigned Depth)
const {
2698 const APInt &DemandedElts,
2699 unsigned Depth)
const {
2706 unsigned Depth )
const {
2712 unsigned Depth)
const {
2717 const APInt &DemandedElts,
2718 unsigned Depth)
const {
2719 EVT VT =
Op.getValueType();
2726 for (
unsigned EltIdx = 0; EltIdx != NumElts; ++EltIdx) {
2727 if (!DemandedElts[EltIdx])
2731 KnownZeroElements.
setBit(EltIdx);
2733 return KnownZeroElements;
2743 unsigned Opcode = V.getOpcode();
2744 EVT VT = V.getValueType();
2747 "scalable demanded bits are ignored");
2759 UndefElts = V.getOperand(0).isUndef()
2768 APInt UndefLHS, UndefRHS;
2773 UndefElts = UndefLHS | UndefRHS;
2803 for (
unsigned i = 0; i != NumElts; ++i) {
2809 if (!DemandedElts[i])
2811 if (Scl && Scl !=
Op)
2821 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(V)->getMask();
2822 for (
int i = 0; i != (int)NumElts; ++i) {
2828 if (!DemandedElts[i])
2830 if (M < (
int)NumElts)
2833 DemandedRHS.
setBit(M - NumElts);
2845 auto CheckSplatSrc = [&](
SDValue Src,
const APInt &SrcElts) {
2847 return (SrcElts.popcount() == 1) ||
2849 (SrcElts & SrcUndefs).
isZero());
2851 if (!DemandedLHS.
isZero())
2852 return CheckSplatSrc(V.getOperand(0), DemandedLHS);
2853 return CheckSplatSrc(V.getOperand(1), DemandedRHS);
2857 SDValue Src = V.getOperand(0);
2859 if (Src.getValueType().isScalableVector())
2862 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
2875 SDValue Src = V.getOperand(0);
2877 if (Src.getValueType().isScalableVector())
2879 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
2881 APInt DemandedSrcElts = DemandedElts.
zext(NumSrcElts);
2883 UndefElts = UndefSrcElts.
trunc(NumElts);
2889 SDValue Src = V.getOperand(0);
2890 EVT SrcVT = Src.getValueType();
2900 if ((
BitWidth % SrcBitWidth) == 0) {
2902 unsigned Scale =
BitWidth / SrcBitWidth;
2904 APInt ScaledDemandedElts =
2906 for (
unsigned I = 0;
I != Scale; ++
I) {
2910 SubDemandedElts &= ScaledDemandedElts;
2914 if (!SubUndefElts.
isZero())
2928 EVT VT = V.getValueType();
2938 (AllowUndefs || !UndefElts);
2944 EVT VT = V.getValueType();
2945 unsigned Opcode = V.getOpcode();
2966 SplatIdx = (UndefElts & DemandedElts).
countr_one();
2980 auto *SVN = cast<ShuffleVectorSDNode>(V);
2981 if (!SVN->isSplat())
2983 int Idx = SVN->getSplatIndex();
2984 int NumElts = V.getValueType().getVectorNumElements();
2985 SplatIdx =
Idx % NumElts;
2986 return V.getOperand(
Idx / NumElts);
3002 if (LegalSVT.
bitsLT(SVT))
3011std::optional<ConstantRange>
3013 unsigned Depth)
const {
3016 "Unknown shift node");
3018 unsigned BitWidth = V.getScalarValueSizeInBits();
3020 if (
auto *Cst = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
3021 const APInt &ShAmt = Cst->getAPIntValue();
3023 return std::nullopt;
3027 if (
auto *BV = dyn_cast<BuildVectorSDNode>(V.getOperand(1))) {
3028 const APInt *MinAmt =
nullptr, *MaxAmt =
nullptr;
3029 for (
unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3030 if (!DemandedElts[i])
3032 auto *SA = dyn_cast<ConstantSDNode>(BV->getOperand(i));
3034 MinAmt = MaxAmt =
nullptr;
3037 const APInt &ShAmt = SA->getAPIntValue();
3039 return std::nullopt;
3040 if (!MinAmt || MinAmt->
ugt(ShAmt))
3042 if (!MaxAmt || MaxAmt->ult(ShAmt))
3045 assert(((!MinAmt && !MaxAmt) || (MinAmt && MaxAmt)) &&
3046 "Failed to find matching min/max shift amounts");
3047 if (MinAmt && MaxAmt)
3057 return std::nullopt;
3060std::optional<uint64_t>
3062 unsigned Depth)
const {
3065 "Unknown shift node");
3066 if (std::optional<ConstantRange> AmtRange =
3068 if (
const APInt *ShAmt = AmtRange->getSingleElement())
3069 return ShAmt->getZExtValue();
3070 return std::nullopt;
3073std::optional<uint64_t>
3075 EVT VT = V.getValueType();
3082std::optional<uint64_t>
3084 unsigned Depth)
const {
3087 "Unknown shift node");
3088 if (std::optional<ConstantRange> AmtRange =
3090 return AmtRange->getUnsignedMin().getZExtValue();
3091 return std::nullopt;
3094std::optional<uint64_t>
3096 EVT VT = V.getValueType();
3103std::optional<uint64_t>
3105 unsigned Depth)
const {
3108 "Unknown shift node");
3109 if (std::optional<ConstantRange> AmtRange =
3111 return AmtRange->getUnsignedMax().getZExtValue();
3112 return std::nullopt;
3115std::optional<uint64_t>
3117 EVT VT = V.getValueType();
3128 EVT VT =
Op.getValueType();
3143 unsigned Depth)
const {
3144 unsigned BitWidth =
Op.getScalarValueSizeInBits();
3148 if (
auto *
C = dyn_cast<ConstantSDNode>(
Op)) {
3152 if (
auto *
C = dyn_cast<ConstantFPSDNode>(
Op)) {
3162 assert((!
Op.getValueType().isFixedLengthVector() ||
3163 NumElts ==
Op.getValueType().getVectorNumElements()) &&
3164 "Unexpected vector size");
3169 unsigned Opcode =
Op.getOpcode();
3177 "Expected SPLAT_VECTOR implicit truncation");
3184 unsigned ScalarSize =
Op.getOperand(0).getScalarValueSizeInBits();
3186 "Expected SPLAT_VECTOR_PARTS scalars to cover element width");
3193 const APInt &Step =
Op.getConstantOperandAPInt(0);
3202 const APInt MinNumElts =
3208 .
umul_ov(MinNumElts, Overflow);
3212 const APInt MaxValue = (MaxNumElts - 1).
umul_ov(Step, Overflow);
3220 assert(!
Op.getValueType().isScalableVector());
3224 if (!DemandedElts[i])
3233 "Expected BUILD_VECTOR implicit truncation");
3246 assert(!
Op.getValueType().isScalableVector());
3249 APInt DemandedLHS, DemandedRHS;
3253 DemandedLHS, DemandedRHS))
3258 if (!!DemandedLHS) {
3266 if (!!DemandedRHS) {
3275 const APInt &Multiplier =
Op.getConstantOperandAPInt(0);
3280 if (
Op.getValueType().isScalableVector())
3284 EVT SubVectorVT =
Op.getOperand(0).getValueType();
3287 for (
unsigned i = 0; i != NumSubVectors; ++i) {
3289 DemandedElts.
extractBits(NumSubVectorElts, i * NumSubVectorElts);
3290 if (!!DemandedSub) {
3302 if (
Op.getValueType().isScalableVector())
3311 APInt DemandedSrcElts = DemandedElts;
3316 if (!!DemandedSubElts) {
3321 if (!!DemandedSrcElts) {
3331 if (
Op.getValueType().isScalableVector() || Src.getValueType().isScalableVector())
3334 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
3340 if (
Op.getValueType().isScalableVector())
3344 if (DemandedElts != 1)
3355 if (
Op.getValueType().isScalableVector())
3375 if ((
BitWidth % SubBitWidth) == 0) {
3382 unsigned SubScale =
BitWidth / SubBitWidth;
3383 APInt SubDemandedElts(NumElts * SubScale, 0);
3384 for (
unsigned i = 0; i != NumElts; ++i)
3385 if (DemandedElts[i])
3386 SubDemandedElts.
setBit(i * SubScale);
3388 for (
unsigned i = 0; i != SubScale; ++i) {
3391 unsigned Shifts = IsLE ? i : SubScale - 1 - i;
3392 Known.
insertBits(Known2, SubBitWidth * Shifts);
3397 if ((SubBitWidth %
BitWidth) == 0) {
3398 assert(
Op.getValueType().isVector() &&
"Expected bitcast to vector");
3403 unsigned SubScale = SubBitWidth /
BitWidth;
3404 APInt SubDemandedElts =
3409 for (
unsigned i = 0; i != NumElts; ++i)
3410 if (DemandedElts[i]) {
3411 unsigned Shifts = IsLE ? i : NumElts - 1 - i;
3442 bool SelfMultiply =
Op.getOperand(0) ==
Op.getOperand(1);
3446 Op.getOperand(0), DemandedElts,
false,
Depth + 1);
3452 if (
Op->getFlags().hasNoSignedWrap() &&
3453 Op.getOperand(0) ==
Op.getOperand(1) &&
3480 unsigned SignBits1 =
3484 unsigned SignBits0 =
3490 assert((
Op.getResNo() == 0 ||
Op.getResNo() == 1) &&
"Unknown result");
3493 bool SelfMultiply =
Op.getOperand(0) ==
Op.getOperand(1);
3494 if (
Op.getResNo() == 0)
3501 assert((
Op.getResNo() == 0 ||
Op.getResNo() == 1) &&
"Unknown result");
3504 bool SelfMultiply =
Op.getOperand(0) ==
Op.getOperand(1);
3505 if (
Op.getResNo() == 0)
3558 if (
Op.getResNo() != 1)
3573 unsigned OpNo =
Op->isStrictFPOpcode() ? 1 : 0;
3585 bool NUW =
Op->getFlags().hasNoUnsignedWrap();
3586 bool NSW =
Op->getFlags().hasNoSignedWrap();
3593 if (std::optional<uint64_t> ShMinAmt =
3602 Op->getFlags().hasExact());
3605 if (std::optional<uint64_t> ShMinAmt =
3613 Op->getFlags().hasExact());
3618 unsigned Amt =
C->getAPIntValue().urem(
BitWidth);
3624 DemandedElts,
Depth + 1);
3649 assert((
Op.getResNo() == 0 ||
Op.getResNo() == 1) &&
"Unknown result");
3652 unsigned LoBits =
Op.getOperand(0).getScalarValueSizeInBits();
3653 unsigned HiBits =
Op.getOperand(1).getScalarValueSizeInBits();
3656 Known = Known2.
concat(Known);
3670 if (
Op.getResNo() == 0)
3678 EVT EVT = cast<VTSDNode>(
Op.getOperand(1))->getVT();
3719 !
Op.getValueType().isScalableVector()) {
3733 for (
unsigned i = 0; i != NumElts; ++i) {
3734 if (!DemandedElts[i])
3737 if (
auto *CInt = dyn_cast<ConstantInt>(Elt)) {
3743 if (
auto *CFP = dyn_cast<ConstantFP>(Elt)) {
3744 APInt Value = CFP->getValueAPF().bitcastToAPInt();
3755 if (
auto *CInt = dyn_cast<ConstantInt>(Cst)) {
3757 }
else if (
auto *CFP = dyn_cast<ConstantFP>(Cst)) {
3763 }
else if (
Op.getResNo() == 0) {
3764 KnownBits Known0(!LD->getMemoryVT().isScalableVT()
3765 ? LD->getMemoryVT().getFixedSizeInBits()
3767 EVT VT =
Op.getValueType();
3774 if (
const MDNode *MD = LD->getRanges()) {
3785 if (LD->getMemoryVT().isVector())
3786 Known0 = Known0.
trunc(LD->getMemoryVT().getScalarSizeInBits());
3803 if (
Op.getValueType().isScalableVector())
3805 EVT InVT =
Op.getOperand(0).getValueType();
3817 if (
Op.getValueType().isScalableVector())
3819 EVT InVT =
Op.getOperand(0).getValueType();
3835 if (
Op.getValueType().isScalableVector())
3837 EVT InVT =
Op.getOperand(0).getValueType();
3854 EVT VT = cast<VTSDNode>(
Op.getOperand(1))->getVT();
3857 Known.
Zero |= (~InMask);
3858 Known.
One &= (~Known.Zero);
3862 unsigned LogOfAlign =
Log2(cast<AssertAlignSDNode>(
Op)->
getAlign());
3882 Op.getOpcode() ==
ISD::ADD, Flags.hasNoSignedWrap(),
3883 Flags.hasNoUnsignedWrap(), Known, Known2);
3890 if (
Op.getResNo() == 1) {
3901 "We only compute knownbits for the difference here.");
3908 Borrow = Borrow.
trunc(1);
3922 if (
Op.getResNo() == 1) {
3933 assert(
Op.getResNo() == 0 &&
"We only compute knownbits for the sum here.");
3943 Carry = Carry.
trunc(1);
3979 const unsigned Index =
Op.getConstantOperandVal(1);
3980 const unsigned EltBitWidth =
Op.getValueSizeInBits();
3987 Known = Known.
trunc(EltBitWidth);
4003 Known = Known.
trunc(EltBitWidth);
4008 auto *ConstEltNo = dyn_cast<ConstantSDNode>(EltNo);
4009 if (ConstEltNo && ConstEltNo->getAPIntValue().ult(NumSrcElts))
4019 if (
Op.getValueType().isScalableVector())
4028 bool DemandedVal =
true;
4029 APInt DemandedVecElts = DemandedElts;
4030 auto *CEltNo = dyn_cast<ConstantSDNode>(EltNo);
4031 if (CEltNo && CEltNo->getAPIntValue().ult(NumElts)) {
4032 unsigned EltIdx = CEltNo->getZExtValue();
4033 DemandedVal = !!DemandedElts[EltIdx];
4042 if (!!DemandedVecElts) {
4060 Known = Known2.
abs();
4093 if (CstLow && CstHigh) {
4098 const APInt &ValueHigh = CstHigh->getAPIntValue();
4099 if (ValueLow.
sle(ValueHigh)) {
4102 unsigned MinSignBits = std::min(LowSignBits, HighSignBits);
4125 if (IsMax && CstLow) {
4149 EVT VT = cast<VTSDNode>(
Op.getOperand(1))->getVT();
4154 if (
Op.getResNo() == 1) {
4181 cast<AtomicSDNode>(
Op)->getMemoryVT().getScalarSizeInBits();
4183 if (
Op.getResNo() == 0) {
4207 if (
Op.getValueType().isScalableVector())
4353 return C->getAPIntValue().zextOrTrunc(
BitWidth).isPowerOf2();
4361 if (
C &&
C->getAPIntValue() == 1)
4371 if (
C &&
C->getAPIntValue().isSignMask())
4383 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(E))
4384 return C->getAPIntValue().zextOrTrunc(BitWidth).isPowerOf2();
4392 if (
C->getAPIntValue().zextOrTrunc(
BitWidth).isPowerOf2())
4430 return C1->getValueAPF().getExactLog2Abs() >= 0;
4439 EVT VT =
Op.getValueType();
4451 unsigned Depth)
const {
4452 EVT VT =
Op.getValueType();
4457 unsigned FirstAnswer = 1;
4459 if (
auto *
C = dyn_cast<ConstantSDNode>(
Op)) {
4460 const APInt &Val =
C->getAPIntValue();
4470 unsigned Opcode =
Op.getOpcode();
4474 Tmp = cast<VTSDNode>(
Op.getOperand(1))->getVT().getSizeInBits();
4475 return VTBits-Tmp+1;
4477 Tmp = cast<VTSDNode>(
Op.getOperand(1))->getVT().getSizeInBits();
4484 unsigned NumSrcBits =
Op.getOperand(0).getValueSizeInBits();
4486 if (NumSrcSignBits > (NumSrcBits - VTBits))
4487 return NumSrcSignBits - (NumSrcBits - VTBits);
4494 if (!DemandedElts[i])
4501 APInt T =
C->getAPIntValue().trunc(VTBits);
4502 Tmp2 =
T.getNumSignBits();
4506 if (
SrcOp.getValueSizeInBits() != VTBits) {
4508 "Expected BUILD_VECTOR implicit truncation");
4509 unsigned ExtraBits =
SrcOp.getValueSizeInBits() - VTBits;
4510 Tmp2 = (Tmp2 > ExtraBits ? Tmp2 - ExtraBits : 1);
4513 Tmp = std::min(Tmp, Tmp2);
4520 APInt DemandedLHS, DemandedRHS;
4524 DemandedLHS, DemandedRHS))
4527 Tmp = std::numeric_limits<unsigned>::max();
4530 if (!!DemandedRHS) {
4532 Tmp = std::min(Tmp, Tmp2);
4537 assert(Tmp <= VTBits &&
"Failed to determine minimum sign bits");
4553 if (VTBits == SrcBits)
4559 if ((SrcBits % VTBits) == 0) {
4562 unsigned Scale = SrcBits / VTBits;
4563 APInt SrcDemandedElts =
4573 for (
unsigned i = 0; i != NumElts; ++i)
4574 if (DemandedElts[i]) {
4575 unsigned SubOffset = i % Scale;
4576 SubOffset = (IsLE ? ((Scale - 1) - SubOffset) : SubOffset);
4577 SubOffset = SubOffset * VTBits;
4578 if (Tmp <= SubOffset)
4580 Tmp2 = std::min(Tmp2, Tmp - SubOffset);
4589 Tmp = cast<VTSDNode>(
Op.getOperand(1))->getVT().getScalarSizeInBits();
4590 return VTBits - Tmp + 1;
4592 Tmp = VTBits -
Op.getOperand(0).getScalarValueSizeInBits();
4596 Tmp = cast<VTSDNode>(
Op.getOperand(1))->getVT().getScalarSizeInBits();
4599 return std::max(Tmp, Tmp2);
4604 EVT SrcVT = Src.getValueType();
4612 if (std::optional<uint64_t> ShAmt =
4614 Tmp = std::min<uint64_t>(Tmp + *ShAmt, VTBits);
4617 if (std::optional<uint64_t> ShAmt =
4622 return Tmp - *ShAmt;
4632 FirstAnswer = std::min(Tmp, Tmp2);
4642 if (Tmp == 1)
return 1;
4644 return std::min(Tmp, Tmp2);
4647 if (Tmp == 1)
return 1;
4649 return std::min(Tmp, Tmp2);
4661 if (CstLow && CstHigh) {
4666 Tmp2 = CstHigh->getAPIntValue().getNumSignBits();
4667 return std::min(Tmp, Tmp2);
4676 return std::min(Tmp, Tmp2);
4684 return std::min(Tmp, Tmp2);
4695 if (
Op.getResNo() != 1)
4709 unsigned OpNo =
Op->isStrictFPOpcode() ? 1 : 0;
4726 unsigned RotAmt =
C->getAPIntValue().urem(VTBits);
4730 RotAmt = (VTBits - RotAmt) % VTBits;
4734 if (Tmp > (RotAmt + 1))
return (Tmp - RotAmt);
4742 if (Tmp == 1)
return 1;
4747 if (CRHS->isAllOnes()) {
4753 if ((Known.
Zero | 1).isAllOnes())
4763 if (Tmp2 == 1)
return 1;
4764 return std::min(Tmp, Tmp2) - 1;
4767 if (Tmp2 == 1)
return 1;
4772 if (CLHS->isZero()) {
4777 if ((Known.
Zero | 1).isAllOnes())
4791 if (Tmp == 1)
return 1;
4792 return std::min(Tmp, Tmp2) - 1;
4796 if (SignBitsOp0 == 1)
4799 if (SignBitsOp1 == 1)
4801 unsigned OutValidBits =
4802 (VTBits - SignBitsOp0 + 1) + (VTBits - SignBitsOp1 + 1);
4803 return OutValidBits > VTBits ? 1 : VTBits - OutValidBits + 1;
4811 return std::min(Tmp, Tmp2);
4820 unsigned NumSrcBits =
Op.getOperand(0).getScalarValueSizeInBits();
4822 if (NumSrcSignBits > (NumSrcBits - VTBits))
4823 return NumSrcSignBits - (NumSrcBits - VTBits);
4830 const int BitWidth =
Op.getValueSizeInBits();
4831 const int Items =
Op.getOperand(0).getValueSizeInBits() /
BitWidth;
4835 const int rIndex = Items - 1 -
Op.getConstantOperandVal(1);
4850 bool DemandedVal =
true;
4851 APInt DemandedVecElts = DemandedElts;
4852 auto *CEltNo = dyn_cast<ConstantSDNode>(EltNo);
4853 if (CEltNo && CEltNo->getAPIntValue().ult(NumElts)) {
4854 unsigned EltIdx = CEltNo->getZExtValue();
4855 DemandedVal = !!DemandedElts[EltIdx];
4858 Tmp = std::numeric_limits<unsigned>::max();
4864 Tmp = std::min(Tmp, Tmp2);
4866 if (!!DemandedVecElts) {
4868 Tmp = std::min(Tmp, Tmp2);
4870 assert(Tmp <= VTBits &&
"Failed to determine minimum sign bits");
4881 const unsigned BitWidth =
Op.getValueSizeInBits();
4882 const unsigned EltBitWidth =
Op.getOperand(0).getScalarValueSizeInBits();
4894 auto *ConstEltNo = dyn_cast<ConstantSDNode>(EltNo);
4895 if (ConstEltNo && ConstEltNo->getAPIntValue().ult(NumSrcElts))
4905 if (Src.getValueType().isScalableVector())
4908 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
4917 Tmp = std::numeric_limits<unsigned>::max();
4918 EVT SubVectorVT =
Op.getOperand(0).getValueType();
4921 for (
unsigned i = 0; (i < NumSubVectors) && (Tmp > 1); ++i) {
4923 DemandedElts.
extractBits(NumSubVectorElts, i * NumSubVectorElts);
4927 Tmp = std::min(Tmp, Tmp2);
4929 assert(Tmp <= VTBits &&
"Failed to determine minimum sign bits");
4942 APInt DemandedSrcElts = DemandedElts;
4945 Tmp = std::numeric_limits<unsigned>::max();
4946 if (!!DemandedSubElts) {
4951 if (!!DemandedSrcElts) {
4953 Tmp = std::min(Tmp, Tmp2);
4955 assert(Tmp <= VTBits &&
"Failed to determine minimum sign bits");
4960 if (
const MDNode *Ranges = LD->getRanges()) {
4961 if (DemandedElts != 1)
4966 switch (LD->getExtensionType()) {
5001 Tmp = cast<AtomicSDNode>(
Op)->getMemoryVT().getScalarSizeInBits();
5003 if (
Op.getResNo() == 0) {
5007 return VTBits - Tmp + 1;
5009 return VTBits - Tmp;
5013 return VTBits - Tmp + 1;
5015 return VTBits - Tmp;
5023 if (
Op.getResNo() == 0) {
5026 unsigned ExtType = LD->getExtensionType();
5030 Tmp = LD->getMemoryVT().getScalarSizeInBits();
5031 return VTBits - Tmp + 1;
5033 Tmp = LD->getMemoryVT().getScalarSizeInBits();
5034 return VTBits - Tmp;
5039 Type *CstTy = Cst->getType();
5044 for (
unsigned i = 0; i != NumElts; ++i) {
5045 if (!DemandedElts[i])
5048 if (
auto *CInt = dyn_cast<ConstantInt>(Elt)) {
5050 Tmp = std::min(Tmp,
Value.getNumSignBits());
5053 if (
auto *CFP = dyn_cast<ConstantFP>(Elt)) {
5054 APInt Value = CFP->getValueAPF().bitcastToAPInt();
5055 Tmp = std::min(Tmp,
Value.getNumSignBits());
5081 FirstAnswer = std::max(FirstAnswer, NumBits);
5092 unsigned Depth)
const {
5094 return Op.getScalarValueSizeInBits() - SignBits + 1;
5098 const APInt &DemandedElts,
5099 unsigned Depth)
const {
5101 return Op.getScalarValueSizeInBits() - SignBits + 1;
5105 unsigned Depth)
const {
5111 EVT VT =
Op.getValueType();
5122 const APInt &DemandedElts,
5124 unsigned Depth)
const {
5125 unsigned Opcode =
Op.getOpcode();
5152 if (!DemandedElts[i])
5161 APInt DemandedLHS, DemandedRHS;
5162 auto *SVN = cast<ShuffleVectorSDNode>(
Op);
5164 DemandedElts, DemandedLHS, DemandedRHS,
5167 if (!DemandedLHS.
isZero() &&
5171 if (!DemandedRHS.
isZero() &&
5199 return isGuaranteedNotToBeUndefOrPoison(V, PoisonOnly, Depth + 1);
5205 unsigned Depth)
const {
5207 EVT VT =
Op.getValueType();
5220 unsigned Depth)
const {
5222 EVT VT =
Op.getValueType();
5226 if (ConsiderFlags &&
Op->hasPoisonGeneratingFlags())
5229 unsigned Opcode =
Op.getOpcode();
5267 if (
Op.getOperand(0).getValueType().isInteger())
5274 unsigned CCOp = Opcode ==
ISD::SETCC ? 2 : 4;
5275 ISD::CondCode CCCode = cast<CondCodeSDNode>(
Op.getOperand(CCOp))->get();
5276 if (((
unsigned)CCCode & 0x10U))
5307 EVT VecVT =
Op.getOperand(0).getValueType();
5319 auto *SVN = cast<ShuffleVectorSDNode>(
Op);
5321 if (Elt < 0 && DemandedElts[
Idx])
5340 unsigned Opcode =
Op.getOpcode();
5342 return Op->getFlags().hasDisjoint() ||
5364 return !
C->getValueAPF().isNaN() ||
5365 (SNaN && !
C->getValueAPF().isSignaling());
5368 unsigned Opcode =
Op.getOpcode();
5477 assert(
Op.getValueType().isFloatingPoint() &&
5478 "Floating point type expected");
5489 assert(!
Op.getValueType().isFloatingPoint() &&
5490 "Floating point types unsupported - use isKnownNeverZeroFloat");
5499 switch (
Op.getOpcode()) {
5513 if (
Op->getFlags().hasNoSignedWrap() ||
Op->getFlags().hasNoUnsignedWrap())
5517 if (ValKnown.
One[0])
5577 if (
Op->getFlags().hasExact())
5593 if (
Op->getFlags().hasExact())
5598 if (
Op->getFlags().hasNoUnsignedWrap())
5609 std::optional<bool> ne =
5616 if (
Op->getFlags().hasNoSignedWrap() ||
Op->getFlags().hasNoUnsignedWrap())
5632 return !C1->isNegative();
5639 if (
A ==
B)
return true;
5644 if (CA->isZero() && CB->isZero())
return true;
5653 return V.getOperand(0);
5660 SDValue ExtArg = V.getOperand(0);
5679 NotOperand = NotOperand->getOperand(0);
5681 if (
Other == NotOperand)
5684 return NotOperand ==
Other->getOperand(0) ||
5685 NotOperand ==
Other->getOperand(1);
5691 A =
A->getOperand(0);
5694 B =
B->getOperand(0);
5697 return MatchNoCommonBitsPattern(
A->getOperand(0),
A->getOperand(1),
B) ||
5698 MatchNoCommonBitsPattern(
A->getOperand(1),
A->getOperand(0),
B);
5704 assert(
A.getValueType() ==
B.getValueType() &&
5705 "Values must have the same type");
5715 if (cast<ConstantSDNode>(Step)->
isZero())
5724 int NumOps = Ops.
size();
5725 assert(NumOps != 0 &&
"Can't build an empty vector!");
5727 "BUILD_VECTOR cannot be used with scalable types");
5729 "Incorrect element count in BUILD_VECTOR!");
5737 bool IsIdentity =
true;
5738 for (
int i = 0; i != NumOps; ++i) {
5740 Ops[i].getOperand(0).getValueType() != VT ||
5741 (IdentitySrc && Ops[i].getOperand(0) != IdentitySrc) ||
5742 !isa<ConstantSDNode>(Ops[i].getOperand(1)) ||
5743 Ops[i].getConstantOperandAPInt(1) != i) {
5747 IdentitySrc = Ops[i].getOperand(0);
5760 assert(!Ops.
empty() &&
"Can't concatenate an empty list of vectors!");
5763 return Ops[0].getValueType() ==
Op.getValueType();
5765 "Concatenation of vectors with inconsistent value types!");
5766 assert((Ops[0].getValueType().getVectorElementCount() * Ops.
size()) ==
5768 "Incorrect element count in vector concatenation!");
5770 if (Ops.
size() == 1)
5781 bool IsIdentity =
true;
5782 for (
unsigned i = 0, e = Ops.
size(); i != e; ++i) {
5784 unsigned IdentityIndex = i *
Op.getValueType().getVectorMinNumElements();
5786 Op.getOperand(0).getValueType() != VT ||
5787 (IdentitySrc &&
Op.getOperand(0) != IdentitySrc) ||
5788 Op.getConstantOperandVal(1) != IdentityIndex) {
5792 assert((!IdentitySrc || IdentitySrc ==
Op.getOperand(0)) &&
5793 "Unexpected identity source vector for concat of extracts");
5794 IdentitySrc =
Op.getOperand(0);
5797 assert(IdentitySrc &&
"Failed to set source vector of extracts");
5812 EVT OpVT =
Op.getValueType();
5824 SVT = (SVT.
bitsLT(
Op.getValueType()) ?
Op.getValueType() : SVT);
5848 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP))
5851 auto *
N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
5852 CSEMap.InsertNode(
N, IP);
5865 return getNode(Opcode,
DL, VT, N1, Flags);
5916 "STEP_VECTOR can only be used with scalable types");
5919 "Unexpected step operand");
5941 "Invalid FP cast!");
5945 "Vector element count mismatch!");
5963 "Invalid SIGN_EXTEND!");
5965 "SIGN_EXTEND result type type should be vector iff the operand "
5970 "Vector element count mismatch!");
5984 "Invalid ZERO_EXTEND!");
5986 "ZERO_EXTEND result type type should be vector iff the operand "
5991 "Vector element count mismatch!");
6022 "Invalid ANY_EXTEND!");
6024 "ANY_EXTEND result type type should be vector iff the operand "
6029 "Vector element count mismatch!");
6054 "Invalid TRUNCATE!");
6056 "TRUNCATE result type type should be vector iff the operand "
6061 "Vector element count mismatch!");
6084 assert(VT.
isVector() &&
"This DAG node is restricted to vector types.");
6086 "The input must be the same size or smaller than the result.");
6089 "The destination vector type must have fewer lanes than the input.");
6099 "BSWAP types must be a multiple of 16 bits!");
6113 "Cannot BITCAST between types of different sizes!");
6126 "Illegal SCALAR_TO_VECTOR node!");
6183 "Wrong operand type!");
6190 if (VT != MVT::Glue) {
6194 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
6195 E->intersectFlagsWith(Flags);
6199 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
6201 createOperands(
N, Ops);
6202 CSEMap.InsertNode(
N, IP);
6204 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
6205 createOperands(
N, Ops);
6239 if (!C2.getBoolValue())
6243 if (!C2.getBoolValue())
6247 if (!C2.getBoolValue())
6251 if (!C2.getBoolValue())
6271 return std::nullopt;
6276 bool IsUndef1,
const APInt &C2,
6278 if (!(IsUndef1 || IsUndef2))
6286 return std::nullopt;
6296 auto *C2 = dyn_cast<ConstantSDNode>(N2);
6299 int64_t
Offset = C2->getSExtValue();
6317 assert(Ops.
size() == 2 &&
"Div/rem should have 2 operands");
6324 [](
SDValue V) { return V.isUndef() ||
6325 isNullConstant(V); });
6346 unsigned NumOps = Ops.
size();
6362 if (
auto *
C = dyn_cast<ConstantSDNode>(N1)) {
6363 const APInt &Val =
C->getAPIntValue();
6367 C->isTargetOpcode(),
C->isOpaque());
6374 C->isTargetOpcode(),
C->isOpaque());
6379 C->isTargetOpcode(),
C->isOpaque());
6381 C->isTargetOpcode(),
C->isOpaque());
6428 if (VT == MVT::f16 &&
C->getValueType(0) == MVT::i16)
6430 if (VT == MVT::f32 &&
C->getValueType(0) == MVT::i32)
6432 if (VT == MVT::f64 &&
C->getValueType(0) == MVT::i64)
6434 if (VT == MVT::f128 &&
C->getValueType(0) == MVT::i128)
6441 if (
auto *
C = dyn_cast<ConstantFPSDNode>(N1)) {
6495 return getConstant(V.bitcastToAPInt().getZExtValue(),
DL, VT);
6498 if (VT == MVT::i16 &&
C->getValueType(0) == MVT::f16)
6501 if (VT == MVT::i16 &&
C->getValueType(0) == MVT::bf16)
6504 if (VT == MVT::i32 &&
C->getValueType(0) == MVT::f32)
6507 if (VT == MVT::i64 &&
C->getValueType(0) == MVT::f64)
6508 return getConstant(V.bitcastToAPInt().getZExtValue(),
DL, VT);
6523 if (
auto *C1 = dyn_cast<ConstantSDNode>(Ops[0])) {
6524 if (
auto *C2 = dyn_cast<ConstantSDNode>(Ops[1])) {
6525 if (C1->isOpaque() || C2->isOpaque())
6528 std::optional<APInt> FoldAttempt =
6529 FoldValue(Opcode, C1->getAPIntValue(), C2->getAPIntValue());
6535 "Can't fold vectors ops with scalar operands");
6556 Ops[0].getValueType() == VT && Ops[1].getValueType() == VT &&
6561 auto *BV1 = dyn_cast<BuildVectorSDNode>(N1);
6562 auto *BV2 = dyn_cast<BuildVectorSDNode>(N2);
6569 if (BV1->getConstantRawBits(IsLE, EltBits, RawBits1, UndefElts1) &&
6570 BV2->getConstantRawBits(IsLE, EltBits, RawBits2, UndefElts2)) {
6574 Opcode, RawBits1[
I], UndefElts1[
I], RawBits2[
I], UndefElts2[
I]);
6585 BVEltVT = BV1->getOperand(0).getValueType();
6588 BVEltVT = BV2->getOperand(0).getValueType();
6594 DstBits, RawBits, DstUndefs,
6597 for (
unsigned I = 0, E = DstBits.
size();
I != E; ++
I) {
6615 ? Ops[0].getConstantOperandAPInt(0) * RHSVal
6616 : Ops[0].getConstantOperandAPInt(0) << RHSVal;
6621 auto IsScalarOrSameVectorSize = [NumElts](
const SDValue &
Op) {
6622 return !
Op.getValueType().isVector() ||
6623 Op.getValueType().getVectorElementCount() == NumElts;
6626 auto IsBuildVectorSplatVectorOrUndef = [](
const SDValue &
Op) {
6635 if (!
llvm::all_of(Ops, IsBuildVectorSplatVectorOrUndef) ||
6664 for (
unsigned I = 0;
I != NumVectorElts;
I++) {
6667 EVT InSVT =
Op.getValueType().getScalarType();
6689 !isa<ConstantSDNode>(ScalarOp) &&
6703 if (LegalSVT != SVT)
6704 ScalarResult =
getNode(ExtendCode,
DL, LegalSVT, ScalarResult);
6722 if (Ops.
size() != 2)
6733 if (N1CFP && N2CFP) {
6780 if (N1C && N1C->getValueAPF().isNegZero() && N2.
isUndef())
6809 ID.AddInteger(
A.value());
6812 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP))
6816 newSDNode<AssertAlignSDNode>(
DL.getIROrder(),
DL.getDebugLoc(), VTs,
A);
6817 createOperands(
N, {Val});
6819 CSEMap.InsertNode(
N, IP);
6832 return getNode(Opcode,
DL, VT, N1, N2, Flags);
6846 if ((N1C && !N2C) || (N1CFP && !N2CFP))
6860 "Operand is DELETED_NODE!");
6864 auto *N1C = dyn_cast<ConstantSDNode>(N1);
6865 auto *N2C = dyn_cast<ConstantSDNode>(N2);
6876 N2.
getValueType() == MVT::Other &&
"Invalid token factor!");
6880 if (N1 == N2)
return N1;
6896 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6898 N1.
getValueType() == VT &&
"Binary operator types must match!");
6901 if (N2CV && N2CV->
isZero())
6910 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6912 N1.
getValueType() == VT &&
"Binary operator types must match!");
6915 if (N2CV && N2CV->
isZero())
6922 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6924 N1.
getValueType() == VT &&
"Binary operator types must match!");
6929 const APInt &N2CImm = N2C->getAPIntValue();
6943 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6945 N1.
getValueType() == VT &&
"Binary operator types must match!");
6959 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6961 N1.
getValueType() == VT &&
"Binary operator types must match!");
6965 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6967 N1.
getValueType() == VT &&
"Binary operator types must match!");
6971 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6973 N1.
getValueType() == VT &&
"Binary operator types must match!");
6979 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6981 N1.
getValueType() == VT &&
"Binary operator types must match!");
6992 N1.
getValueType() == VT &&
"Binary operator types must match!");
7000 "Invalid FCOPYSIGN!");
7005 const APInt &ShiftImm = N2C->getAPIntValue();
7017 "Shift operators return type must be the same as their first arg");
7019 "Shifts only work on integers");
7021 "Vector shift amounts must be in the same as their first arg");
7028 "Invalid use of small shift amount with oversized value!");
7035 if (N2CV && N2CV->
isZero())
7042 N2C && (N2C->getZExtValue() == 0 || N2C->getZExtValue() == 1) &&
7043 "Invalid FP_ROUND!");
7048 EVT EVT = cast<VTSDNode>(N2)->getVT();
7051 "Cannot *_EXTEND_INREG FP types");
7053 "AssertSExt/AssertZExt type should be the vector element type "
7054 "rather than the vector type!");
7060 EVT EVT = cast<VTSDNode>(N2)->getVT();
7063 "Cannot *_EXTEND_INREG FP types");
7065 "SIGN_EXTEND_INREG type should be vector iff the operand "
7069 "Vector element counts must match in SIGN_EXTEND_INREG");
7071 if (
EVT == VT)
return N1;
7081 const APInt &Val = N1C->getAPIntValue();
7082 return SignExtendInReg(Val, VT);
7095 APInt Val =
C->getAPIntValue();
7096 Ops.
push_back(SignExtendInReg(Val, OpVT));
7114 "FP_TO_*INT_SAT type should be vector iff the operand type is "
7118 "Vector element counts must match in FP_TO_*INT_SAT");
7119 assert(!cast<VTSDNode>(N2)->getVT().isVector() &&
7120 "Type to saturate to must be a scalar.");
7127 "The result of EXTRACT_VECTOR_ELT must be at least as wide as the \
7128 element type of the vector.");
7160 "BUILD_VECTOR used for scalable vectors");
7183 if (N1Op2C && N2C) {
7213 assert(N2C && (
unsigned)N2C->getZExtValue() < 2 &&
"Bad EXTRACT_ELEMENT!");
7217 "Wrong types for EXTRACT_ELEMENT!");
7228 unsigned Shift = ElementSize * N2C->getZExtValue();
7229 const APInt &Val = N1C->getAPIntValue();
7236 "Extract subvector VTs must be vectors!");
7238 "Extract subvector VTs must have the same element type!");
7240 "Cannot extract a scalable vector from a fixed length vector!");
7243 "Extract subvector must be from larger vector to smaller vector!");
7244 assert(N2C &&
"Extract subvector index must be a constant");
7248 "Extract subvector overflow!");
7249 assert(N2C->getAPIntValue().getBitWidth() ==
7251 "Constant index for EXTRACT_SUBVECTOR has an invalid size");
7266 return N1.
getOperand(N2C->getZExtValue() / Factor);
7334 if (VT != MVT::Glue) {
7338 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
7339 E->intersectFlagsWith(Flags);
7343 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
7345 createOperands(
N, Ops);
7346 CSEMap.InsertNode(
N, IP);
7348 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
7349 createOperands(
N, Ops);
7363 return getNode(Opcode,
DL, VT, N1, N2, N3, Flags);
7372 "Operand is DELETED_NODE!");
7383 if (N1CFP && N2CFP && N3CFP) {
7412 "SETCC operands must have the same type!");
7414 "SETCC type should be vector iff the operand type is vector!");
7417 "SETCC vector element counts must match!");
7437 if (cast<ConstantSDNode>(N3)->
isZero())
7467 "Dest and insert subvector source types must match!");
7469 "Insert subvector VTs must be vectors!");
7471 "Insert subvector VTs must have the same element type!");
7473 "Cannot insert a scalable vector into a fixed length vector!");
7476 "Insert subvector must be from smaller vector to larger vector!");
7477 assert(isa<ConstantSDNode>(N3) &&
7478 "Insert subvector index must be constant");
7482 "Insert subvector overflow!");
7485 "Constant index for INSERT_SUBVECTOR has an invalid size");
7503 case ISD::VP_TRUNCATE:
7504 case ISD::VP_SIGN_EXTEND:
7505 case ISD::VP_ZERO_EXTEND:
7516 if (VT != MVT::Glue) {
7520 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
7521 E->intersectFlagsWith(Flags);
7525 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
7527 createOperands(
N, Ops);
7528 CSEMap.InsertNode(
N, IP);
7530 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
7531 createOperands(
N, Ops);
7542 SDValue Ops[] = { N1, N2, N3, N4 };
7549 SDValue Ops[] = { N1, N2, N3, N4, N5 };
7567 if (FI->getIndex() < 0)
7582 assert(
C->getAPIntValue().getBitWidth() == 8);
7587 return DAG.
getConstant(Val, dl, VT,
false, IsOpaque);
7593 assert(
Value.getValueType() == MVT::i8 &&
"memset with non-byte fill value?");
7609 if (VT !=
Value.getValueType())
7622 if (Slice.
Array ==
nullptr) {
7625 if (VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
7640 unsigned NumVTBytes = NumVTBits / 8;
7641 unsigned NumBytes = std::min(NumVTBytes,
unsigned(Slice.
Length));
7643 APInt Val(NumVTBits, 0);
7645 for (
unsigned i = 0; i != NumBytes; ++i)
7648 for (
unsigned i = 0; i != NumBytes; ++i)
7649 Val |= (
uint64_t)(
unsigned char)Slice[i] << (NumVTBytes-i-1)*8;
7668 APInt(
Base.getValueSizeInBits().getFixedValue(),
7669 Offset.getKnownMinValue()));
7680 EVT BasePtrVT =
Ptr.getValueType();
7689 G = cast<GlobalAddressSDNode>(Src);
7690 else if (Src.getOpcode() ==
ISD::ADD &&
7693 G = cast<GlobalAddressSDNode>(Src.getOperand(0));
7694 SrcDelta = Src.getConstantOperandVal(1);
7700 SrcDelta +
G->getOffset());
7716 assert(OutLoadChains.
size() &&
"Missing loads in memcpy inlining");
7717 assert(OutStoreChains.
size() &&
"Missing stores in memcpy inlining");
7719 for (
unsigned i =
From; i < To; ++i) {
7721 GluedLoadChains.
push_back(OutLoadChains[i]);
7728 for (
unsigned i =
From; i < To; ++i) {
7729 StoreSDNode *ST = dyn_cast<StoreSDNode>(OutStoreChains[i]);
7731 ST->getBasePtr(), ST->getMemoryVT(),
7732 ST->getMemOperand());
7740 bool isVol,
bool AlwaysInline,
7756 std::vector<EVT> MemOps;
7757 bool DstAlignCanChange =
false;
7763 DstAlignCanChange =
true;
7765 if (!SrcAlign || Alignment > *SrcAlign)
7766 SrcAlign = Alignment;
7767 assert(SrcAlign &&
"SrcAlign must be set");
7771 bool isZeroConstant = CopyFromConstant && Slice.
Array ==
nullptr;
7773 const MemOp Op = isZeroConstant
7777 *SrcAlign, isVol, CopyFromConstant);
7783 if (DstAlignCanChange) {
7784 Type *Ty = MemOps[0].getTypeForEVT(
C);
7785 Align NewAlign =
DL.getABITypeAlign(Ty);
7791 if (!
TRI->hasStackRealignment(MF))
7792 while (NewAlign > Alignment &&
DL.exceedsNaturalStackAlignment(NewAlign))
7795 if (NewAlign > Alignment) {
7799 Alignment = NewAlign;
7807 const Value *SrcVal = dyn_cast_if_present<const Value *>(SrcPtrInfo.
V);
7817 unsigned NumMemOps = MemOps.
size();
7819 for (
unsigned i = 0; i != NumMemOps; ++i) {
7824 if (VTSize >
Size) {
7827 assert(i == NumMemOps-1 && i != 0);
7828 SrcOff -= VTSize -
Size;
7829 DstOff -= VTSize -
Size;
7832 if (CopyFromConstant &&
7840 if (SrcOff < Slice.
Length) {
7842 SubSlice.
move(SrcOff);
7845 SubSlice.
Array =
nullptr;
7847 SubSlice.
Length = VTSize;
7850 if (
Value.getNode()) {
7854 DstPtrInfo.
getWithOffset(DstOff), Alignment, MMOFlags, NewAAInfo);
7859 if (!Store.getNode()) {
7868 bool isDereferenceable =
7871 if (isDereferenceable)
7886 DstPtrInfo.
getWithOffset(DstOff), VT, Alignment, MMOFlags, NewAAInfo);
7896 unsigned NumLdStInMemcpy = OutStoreChains.
size();
7898 if (NumLdStInMemcpy) {
7904 for (
unsigned i = 0; i < NumLdStInMemcpy; ++i) {
7910 if (NumLdStInMemcpy <= GluedLdStLimit) {
7912 NumLdStInMemcpy, OutLoadChains,
7915 unsigned NumberLdChain = NumLdStInMemcpy / GluedLdStLimit;
7916 unsigned RemainingLdStInMemcpy = NumLdStInMemcpy % GluedLdStLimit;
7917 unsigned GlueIter = 0;
7919 for (
unsigned cnt = 0; cnt < NumberLdChain; ++cnt) {
7920 unsigned IndexFrom = NumLdStInMemcpy - GlueIter - GluedLdStLimit;
7921 unsigned IndexTo = NumLdStInMemcpy - GlueIter;
7924 OutLoadChains, OutStoreChains);
7925 GlueIter += GluedLdStLimit;
7929 if (RemainingLdStInMemcpy) {
7931 RemainingLdStInMemcpy, OutLoadChains,
7943 bool isVol,
bool AlwaysInline,
7957 std::vector<EVT> MemOps;
7958 bool DstAlignCanChange =
false;
7964 DstAlignCanChange =
true;
7966 if (!SrcAlign || Alignment > *SrcAlign)
7967 SrcAlign = Alignment;
7968 assert(SrcAlign &&
"SrcAlign must be set");
7978 if (DstAlignCanChange) {
7979 Type *Ty = MemOps[0].getTypeForEVT(
C);
7980 Align NewAlign =
DL.getABITypeAlign(Ty);
7986 if (!
TRI->hasStackRealignment(MF))
7987 while (NewAlign > Alignment &&
DL.exceedsNaturalStackAlignment(NewAlign))
7990 if (NewAlign > Alignment) {
7994 Alignment = NewAlign;
8008 unsigned NumMemOps = MemOps.
size();
8009 for (
unsigned i = 0; i < NumMemOps; i++) {
8014 bool isDereferenceable =
8017 if (isDereferenceable)
8023 SrcPtrInfo.
getWithOffset(SrcOff), *SrcAlign, SrcMMOFlags, NewAAInfo);
8030 for (
unsigned i = 0; i < NumMemOps; i++) {
8036 Chain, dl, LoadValues[i],
8038 DstPtrInfo.
getWithOffset(DstOff), Alignment, MMOFlags, NewAAInfo);
8078 std::vector<EVT> MemOps;
8079 bool DstAlignCanChange =
false;
8085 DstAlignCanChange =
true;
8091 MemOp::Set(
Size, DstAlignCanChange, Alignment, IsZeroVal, isVol),
8095 if (DstAlignCanChange) {
8098 Align NewAlign =
DL.getABITypeAlign(Ty);
8104 if (!
TRI->hasStackRealignment(MF))
8105 while (NewAlign > Alignment &&
DL.exceedsNaturalStackAlignment(NewAlign))
8108 if (NewAlign > Alignment) {
8112 Alignment = NewAlign;
8118 unsigned NumMemOps = MemOps.size();
8121 EVT LargestVT = MemOps[0];
8122 for (
unsigned i = 1; i < NumMemOps; i++)
8123 if (MemOps[i].bitsGT(LargestVT))
8124 LargestVT = MemOps[i];
8131 for (
unsigned i = 0; i < NumMemOps; i++) {
8134 if (VTSize >
Size) {
8137 assert(i == NumMemOps-1 && i != 0);
8138 DstOff -= VTSize -
Size;
8145 if (VT.
bitsLT(LargestVT)) {
8166 assert(
Value.getValueType() == VT &&
"Value with wrong type.");
8193 bool isVol,
bool AlwaysInline,
bool isTailCall,
8202 if (ConstantSize->
isZero())
8206 *
this, dl, Chain, Dst, Src, ConstantSize->
getZExtValue(), Alignment,
8207 isVol,
false, DstPtrInfo, SrcPtrInfo, AAInfo, AA);
8208 if (Result.getNode())
8216 *
this, dl, Chain, Dst, Src,
Size, Alignment, isVol, AlwaysInline,
8217 DstPtrInfo, SrcPtrInfo);
8218 if (Result.getNode())
8225 assert(ConstantSize &&
"AlwaysInline requires a constant size!");
8227 *
this, dl, Chain, Dst, Src, ConstantSize->
getZExtValue(), Alignment,
8228 isVol,
true, DstPtrInfo, SrcPtrInfo, AAInfo, AA);
8244 Entry.Node = Dst; Args.push_back(Entry);
8245 Entry.Node = Src; Args.push_back(Entry);
8248 Entry.Node =
Size; Args.push_back(Entry);
8254 Dst.getValueType().getTypeForEVT(*
getContext()),
8261 std::pair<SDValue,SDValue> CallResult = TLI->
LowerCallTo(CLI);
8262 return CallResult.second;
8267 Type *SizeTy,
unsigned ElemSz,
8276 Args.push_back(Entry);
8279 Args.push_back(Entry);
8283 Args.push_back(Entry);
8287 if (LibraryCall == RTLIB::UNKNOWN_LIBCALL)
8301 std::pair<SDValue, SDValue> CallResult = TLI->
LowerCallTo(CLI);
8302 return CallResult.second;
8307 bool isVol,
bool isTailCall,
8316 if (ConstantSize->
isZero())
8320 *
this, dl, Chain, Dst, Src, ConstantSize->
getZExtValue(), Alignment,
8321 isVol,
false, DstPtrInfo, SrcPtrInfo, AAInfo);
8322 if (Result.getNode())
8331 Alignment, isVol, DstPtrInfo, SrcPtrInfo);
8332 if (Result.getNode())
8346 Entry.Node = Dst; Args.push_back(Entry);
8347 Entry.Node = Src; Args.push_back(Entry);
8350 Entry.Node =
Size; Args.push_back(Entry);
8356 Dst.getValueType().getTypeForEVT(*
getContext()),
8363 std::pair<SDValue,SDValue> CallResult = TLI->
LowerCallTo(CLI);
8364 return CallResult.second;
8369 Type *SizeTy,
unsigned ElemSz,
8378 Args.push_back(Entry);
8381 Args.push_back(Entry);
8385 Args.push_back(Entry);
8389 if (LibraryCall == RTLIB::UNKNOWN_LIBCALL)
8403 std::pair<SDValue, SDValue> CallResult = TLI->
LowerCallTo(CLI);
8404 return CallResult.second;
8409 bool isVol,
bool AlwaysInline,
bool isTailCall,
8417 if (ConstantSize->
isZero())
8422 isVol,
false, DstPtrInfo, AAInfo);
8424 if (Result.getNode())
8432 *
this, dl, Chain, Dst, Src,
Size, Alignment, isVol, AlwaysInline, DstPtrInfo);
8433 if (Result.getNode())
8440 assert(ConstantSize &&
"AlwaysInline requires a constant size!");
8443 isVol,
true, DstPtrInfo, AAInfo);
8445 "getMemsetStores must return a valid sequence when AlwaysInline");
8462 const auto CreateEntry = [](
SDValue Node,
Type *Ty) {
8473 Args.push_back(CreateEntry(
Size,
DL.getIntPtrType(Ctx)));
8480 Args.push_back(CreateEntry(Src, Src.getValueType().getTypeForEVT(Ctx)));
8481 Args.push_back(CreateEntry(
Size,
DL.getIntPtrType(Ctx)));
8483 Dst.getValueType().getTypeForEVT(Ctx),
8491 std::pair<SDValue, SDValue> CallResult = TLI->
LowerCallTo(CLI);
8492 return CallResult.second;
8497 Type *SizeTy,
unsigned ElemSz,
8505 Args.push_back(Entry);
8509 Args.push_back(Entry);
8513 Args.push_back(Entry);
8517 if (LibraryCall == RTLIB::UNKNOWN_LIBCALL)
8531 std::pair<SDValue, SDValue> CallResult = TLI->
LowerCallTo(CLI);
8532 return CallResult.second;
8544 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
8545 cast<AtomicSDNode>(E)->refineAlignment(MMO);
8550 VTList, MemVT, MMO);
8551 createOperands(
N, Ops);
8553 CSEMap.InsertNode(
N, IP);
8567 return getAtomic(Opcode, dl, MemVT, VTs, Ops, MMO);
8592 "Invalid Atomic Op");
8599 return getAtomic(Opcode, dl, MemVT, VTs, Ops, MMO);
8609 return getAtomic(Opcode, dl, MemVT, VTs, Ops, MMO);
8614 if (Ops.
size() == 1)
8629 if (
Size.hasValue() && !
Size.getValue())
8646 (Opcode <= (
unsigned)std::numeric_limits<int>::max() &&
8648 "Opcode is not a memory-accessing opcode!");
8652 if (VTList.
VTs[VTList.
NumVTs-1] != MVT::Glue) {
8655 ID.AddInteger(getSyntheticNodeSubclassData<MemIntrinsicSDNode>(
8656 Opcode, dl.
getIROrder(), VTList, MemVT, MMO));
8661 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
8662 cast<MemIntrinsicSDNode>(E)->refineAlignment(MMO);
8667 VTList, MemVT, MMO);
8668 createOperands(
N, Ops);
8670 CSEMap.InsertNode(
N, IP);
8673 VTList, MemVT, MMO);
8674 createOperands(
N, Ops);
8683 SDValue Chain,
int FrameIndex,
8695 ID.AddInteger(FrameIndex);
8699 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
8704 createOperands(
N, Ops);
8705 CSEMap.InsertNode(
N, IP);
8723 if (
SDNode *E = FindNodeOrInsertPos(
ID, Dl, IP))
8726 auto *
N = newSDNode<PseudoProbeSDNode>(
8728 createOperands(
N, Ops);
8729 CSEMap.InsertNode(
N, IP);
8750 !isa<ConstantSDNode>(
Ptr.getOperand(1)) ||
8751 !isa<FrameIndexSDNode>(
Ptr.getOperand(0)))
8754 int FI = cast<FrameIndexSDNode>(
Ptr.getOperand(0))->getIndex();
8757 Offset + cast<ConstantSDNode>(
Ptr.getOperand(1))->getSExtValue());
8768 if (
ConstantSDNode *OffsetNode = dyn_cast<ConstantSDNode>(OffsetOp))
8783 "Invalid chain type");
8795 Alignment, AAInfo, Ranges);
8806 assert(VT == MemVT &&
"Non-extending load from different memory type!");
8810 "Should only be an extending load, not truncating!");
8812 "Cannot convert from FP to Int or Int -> FP!");
8814 "Cannot use an ext load to convert to or from a vector!");
8817 "Cannot use an ext load to change the number of vector elements!");
8829 ID.AddInteger(getSyntheticNodeSubclassData<LoadSDNode>(
8830 dl.
getIROrder(), VTs, AM, ExtType, MemVT, MMO));
8834 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
8835 cast<LoadSDNode>(E)->refineAlignment(MMO);
8839 ExtType, MemVT, MMO);
8840 createOperands(
N, Ops);
8842 CSEMap.InsertNode(
N, IP);
8856 PtrInfo, VT, Alignment, MMOFlags, AAInfo, Ranges);
8874 MemVT, Alignment, MMOFlags, AAInfo);
8889 assert(LD->getOffset().isUndef() &&
"Load is already a indexed load!");
8892 LD->getMemOperand()->getFlags() &
8895 LD->getChain(),
Base,
Offset, LD->getPointerInfo(),
8896 LD->getMemoryVT(), LD->getAlign(), MMOFlags, LD->getAAInfo());
8922 "Invalid chain type");
8930 ID.AddInteger(getSyntheticNodeSubclassData<StoreSDNode>(
8935 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
8936 cast<StoreSDNode>(E)->refineAlignment(MMO);
8941 createOperands(
N, Ops);
8943 CSEMap.InsertNode(
N, IP);
8956 "Invalid chain type");
8977 "Invalid chain type");
8982 "Should only be a truncating store, not extending!");
8984 "Can't do FP-INT conversion!");
8986 "Cannot use trunc store to convert to or from a vector!");
8989 "Cannot use trunc store to change the number of vector elements!");
8997 ID.AddInteger(getSyntheticNodeSubclassData<StoreSDNode>(
9002 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9003 cast<StoreSDNode>(E)->refineAlignment(MMO);
9008 createOperands(
N, Ops);
9010 CSEMap.InsertNode(
N, IP);
9021 assert(ST->getOffset().isUndef() &&
"Store is already a indexed store!");
9026 ID.AddInteger(ST->getMemoryVT().getRawBits());
9027 ID.AddInteger(ST->getRawSubclassData());
9028 ID.AddInteger(ST->getPointerInfo().getAddrSpace());
9029 ID.AddInteger(ST->getMemOperand()->getFlags());
9031 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
9035 ST->isTruncatingStore(), ST->getMemoryVT(),
9036 ST->getMemOperand());
9037 createOperands(
N, Ops);
9039 CSEMap.InsertNode(
N, IP);
9051 const MDNode *Ranges,
bool IsExpanding) {
9064 Alignment, AAInfo, Ranges);
9065 return getLoadVP(AM, ExtType, VT, dl, Chain,
Ptr,
Offset, Mask, EVL, MemVT,
9084 ID.AddInteger(getSyntheticNodeSubclassData<VPLoadSDNode>(
9085 dl.
getIROrder(), VTs, AM, ExtType, IsExpanding, MemVT, MMO));
9089 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9090 cast<VPLoadSDNode>(E)->refineAlignment(MMO);
9094 ExtType, IsExpanding, MemVT, MMO);
9095 createOperands(
N, Ops);
9097 CSEMap.InsertNode(
N, IP);
9113 Mask, EVL, PtrInfo, VT, Alignment, MMOFlags, AAInfo, Ranges,
9122 Mask, EVL, VT, MMO, IsExpanding);
9131 const AAMDNodes &AAInfo,
bool IsExpanding) {
9134 EVL, PtrInfo, MemVT, Alignment, MMOFlags, AAInfo,
nullptr,
9144 EVL, MemVT, MMO, IsExpanding);
9150 auto *LD = cast<VPLoadSDNode>(OrigLoad);
9151 assert(LD->getOffset().isUndef() &&
"Load is already a indexed load!");
9154 LD->getMemOperand()->getFlags() &
9158 LD->getVectorLength(), LD->getPointerInfo(),
9159 LD->getMemoryVT(), LD->getAlign(), MMOFlags, LD->getAAInfo(),
9160 nullptr, LD->isExpandingLoad());
9167 bool IsCompressing) {
9177 ID.AddInteger(getSyntheticNodeSubclassData<VPStoreSDNode>(
9178 dl.
getIROrder(), VTs, AM, IsTruncating, IsCompressing, MemVT, MMO));
9182 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9183 cast<VPStoreSDNode>(E)->refineAlignment(MMO);
9187 IsTruncating, IsCompressing, MemVT, MMO);
9188 createOperands(
N, Ops);
9190 CSEMap.InsertNode(
N, IP);
9203 bool IsCompressing) {
9224 bool IsCompressing) {
9231 false, IsCompressing);
9234 "Should only be a truncating store, not extending!");
9237 "Cannot use trunc store to convert to or from a vector!");
9240 "Cannot use trunc store to change the number of vector elements!");
9244 SDValue Ops[] = {Chain, Val,
Ptr, Undef, Mask, EVL};
9248 ID.AddInteger(getSyntheticNodeSubclassData<VPStoreSDNode>(
9253 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9254 cast<VPStoreSDNode>(E)->refineAlignment(MMO);
9260 createOperands(
N, Ops);
9262 CSEMap.InsertNode(
N, IP);
9272 auto *ST = cast<VPStoreSDNode>(OrigStore);
9273 assert(ST->getOffset().isUndef() &&
"Store is already an indexed store!");
9275 SDValue Ops[] = {ST->getChain(), ST->getValue(),
Base,
9276 Offset, ST->getMask(), ST->getVectorLength()};
9279 ID.AddInteger(ST->getMemoryVT().getRawBits());
9280 ID.AddInteger(ST->getRawSubclassData());
9281 ID.AddInteger(ST->getPointerInfo().getAddrSpace());
9282 ID.AddInteger(ST->getMemOperand()->getFlags());
9284 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
9287 auto *
N = newSDNode<VPStoreSDNode>(
9289 ST->isCompressingStore(), ST->getMemoryVT(), ST->getMemOperand());
9290 createOperands(
N, Ops);
9292 CSEMap.InsertNode(
N, IP);
9312 ID.AddInteger(getSyntheticNodeSubclassData<VPStridedLoadSDNode>(
9313 DL.getIROrder(), VTs, AM, ExtType, IsExpanding, MemVT, MMO));
9317 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
9318 cast<VPStridedLoadSDNode>(E)->refineAlignment(MMO);
9323 newSDNode<VPStridedLoadSDNode>(
DL.getIROrder(),
DL.getDebugLoc(), VTs, AM,
9324 ExtType, IsExpanding, MemVT, MMO);
9325 createOperands(
N, Ops);
9326 CSEMap.InsertNode(
N, IP);
9340 Undef, Stride, Mask, EVL, VT, MMO, IsExpanding);
9349 Stride, Mask, EVL, MemVT, MMO, IsExpanding);
9358 bool IsTruncating,
bool IsCompressing) {
9368 ID.AddInteger(getSyntheticNodeSubclassData<VPStridedStoreSDNode>(
9369 DL.getIROrder(), VTs, AM, IsTruncating, IsCompressing, MemVT, MMO));
9372 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
9373 cast<VPStridedStoreSDNode>(E)->refineAlignment(MMO);
9376 auto *
N = newSDNode<VPStridedStoreSDNode>(
DL.getIROrder(),
DL.getDebugLoc(),
9377 VTs, AM, IsTruncating,
9378 IsCompressing, MemVT, MMO);
9379 createOperands(
N, Ops);
9381 CSEMap.InsertNode(
N, IP);
9393 bool IsCompressing) {
9400 false, IsCompressing);
9403 "Should only be a truncating store, not extending!");
9406 "Cannot use trunc store to convert to or from a vector!");
9409 "Cannot use trunc store to change the number of vector elements!");
9413 SDValue Ops[] = {Chain, Val,
Ptr, Undef, Stride, Mask, EVL};
9417 ID.AddInteger(getSyntheticNodeSubclassData<VPStridedStoreSDNode>(
9421 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
9422 cast<VPStridedStoreSDNode>(E)->refineAlignment(MMO);
9425 auto *
N = newSDNode<VPStridedStoreSDNode>(
DL.getIROrder(),
DL.getDebugLoc(),
9427 IsCompressing, SVT, MMO);
9428 createOperands(
N, Ops);
9430 CSEMap.InsertNode(
N, IP);
9440 assert(Ops.
size() == 6 &&
"Incompatible number of operands");
9445 ID.AddInteger(getSyntheticNodeSubclassData<VPGatherSDNode>(
9450 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9451 cast<VPGatherSDNode>(E)->refineAlignment(MMO);
9456 VT, MMO, IndexType);
9457 createOperands(
N, Ops);
9459 assert(
N->getMask().getValueType().getVectorElementCount() ==
9460 N->getValueType(0).getVectorElementCount() &&
9461 "Vector width mismatch between mask and data");
9462 assert(
N->getIndex().getValueType().getVectorElementCount().isScalable() ==
9463 N->getValueType(0).getVectorElementCount().isScalable() &&
9464 "Scalable flags of index and data do not match");
9466 N->getIndex().getValueType().getVectorElementCount(),
9467 N->getValueType(0).getVectorElementCount()) &&
9468 "Vector width mismatch between index and data");
9469 assert(isa<ConstantSDNode>(
N->getScale()) &&
9470 N->getScale()->getAsAPIntVal().isPowerOf2() &&
9471 "Scale should be a constant power of 2");
9473 CSEMap.InsertNode(
N, IP);
9484 assert(Ops.
size() == 7 &&
"Incompatible number of operands");
9489 ID.AddInteger(getSyntheticNodeSubclassData<VPScatterSDNode>(
9494 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9495 cast<VPScatterSDNode>(E)->refineAlignment(MMO);
9499 VT, MMO, IndexType);
9500 createOperands(
N, Ops);
9502 assert(
N->getMask().getValueType().getVectorElementCount() ==
9503 N->getValue().getValueType().getVectorElementCount() &&
9504 "Vector width mismatch between mask and data");
9506 N->getIndex().getValueType().getVectorElementCount().isScalable() ==
9507 N->getValue().getValueType().getVectorElementCount().isScalable() &&
9508 "Scalable flags of index and data do not match");
9510 N->getIndex().getValueType().getVectorElementCount(),
9511 N->getValue().getValueType().getVectorElementCount()) &&
9512 "Vector width mismatch between index and data");
9513 assert(isa<ConstantSDNode>(
N->getScale()) &&
9514 N->getScale()->getAsAPIntVal().isPowerOf2() &&
9515 "Scale should be a constant power of 2");
9517 CSEMap.InsertNode(
N, IP);
9532 "Unindexed masked load with an offset!");
9539 ID.AddInteger(getSyntheticNodeSubclassData<MaskedLoadSDNode>(
9540 dl.
getIROrder(), VTs, AM, ExtTy, isExpanding, MemVT, MMO));
9544 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9545 cast<MaskedLoadSDNode>(E)->refineAlignment(MMO);
9549 AM, ExtTy, isExpanding, MemVT, MMO);
9550 createOperands(
N, Ops);
9552 CSEMap.InsertNode(
N, IP);
9563 assert(LD->getOffset().isUndef() &&
"Masked load is already a indexed load!");
9565 Offset, LD->getMask(), LD->getPassThru(),
9566 LD->getMemoryVT(), LD->getMemOperand(), AM,
9567 LD->getExtensionType(), LD->isExpandingLoad());
9575 bool IsCompressing) {
9577 "Invalid chain type");
9580 "Unindexed masked store with an offset!");
9587 ID.AddInteger(getSyntheticNodeSubclassData<MaskedStoreSDNode>(
9588 dl.
getIROrder(), VTs, AM, IsTruncating, IsCompressing, MemVT, MMO));
9592 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9593 cast<MaskedStoreSDNode>(E)->refineAlignment(MMO);
9598 IsTruncating, IsCompressing, MemVT, MMO);
9599 createOperands(
N, Ops);
9601 CSEMap.InsertNode(
N, IP);
9612 assert(ST->getOffset().isUndef() &&
9613 "Masked store is already a indexed store!");
9615 ST->getMask(), ST->getMemoryVT(), ST->getMemOperand(),
9616 AM, ST->isTruncatingStore(), ST->isCompressingStore());
9624 assert(Ops.
size() == 6 &&
"Incompatible number of operands");
9629 ID.AddInteger(getSyntheticNodeSubclassData<MaskedGatherSDNode>(
9630 dl.
getIROrder(), VTs, MemVT, MMO, IndexType, ExtTy));
9634 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9635 cast<MaskedGatherSDNode>(E)->refineAlignment(MMO);
9640 VTs, MemVT, MMO, IndexType, ExtTy);
9641 createOperands(
N, Ops);
9643 assert(
N->getPassThru().getValueType() ==
N->getValueType(0) &&
9644 "Incompatible type of the PassThru value in MaskedGatherSDNode");
9645 assert(
N->getMask().getValueType().getVectorElementCount() ==
9646 N->getValueType(0).getVectorElementCount() &&
9647 "Vector width mismatch between mask and data");
9648 assert(
N->getIndex().getValueType().getVectorElementCount().isScalable() ==
9649 N->getValueType(0).getVectorElementCount().isScalable() &&
9650 "Scalable flags of index and data do not match");
9652 N->getIndex().getValueType().getVectorElementCount(),
9653 N->getValueType(0).getVectorElementCount()) &&
9654 "Vector width mismatch between index and data");
9655 assert(isa<ConstantSDNode>(
N->getScale()) &&
9656 N->getScale()->getAsAPIntVal().isPowerOf2() &&
9657 "Scale should be a constant power of 2");
9659 CSEMap.InsertNode(
N, IP);
9671 assert(Ops.
size() == 6 &&
"Incompatible number of operands");
9676 ID.AddInteger(getSyntheticNodeSubclassData<MaskedScatterSDNode>(
9677 dl.
getIROrder(), VTs, MemVT, MMO, IndexType, IsTrunc));
9681 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9682 cast<MaskedScatterSDNode>(E)->refineAlignment(MMO);
9687 VTs, MemVT, MMO, IndexType, IsTrunc);
9688 createOperands(
N, Ops);
9690 assert(
N->getMask().getValueType().getVectorElementCount() ==
9691 N->getValue().getValueType().getVectorElementCount() &&
9692 "Vector width mismatch between mask and data");
9694 N->getIndex().getValueType().getVectorElementCount().isScalable() ==
9695 N->getValue().getValueType().getVectorElementCount().isScalable() &&
9696 "Scalable flags of index and data do not match");
9698 N->getIndex().getValueType().getVectorElementCount(),
9699 N->getValue().getValueType().getVectorElementCount()) &&
9700 "Vector width mismatch between index and data");
9701 assert(isa<ConstantSDNode>(
N->getScale()) &&
9702 N->getScale()->getAsAPIntVal().isPowerOf2() &&
9703 "Scale should be a constant power of 2");
9705 CSEMap.InsertNode(
N, IP);
9716 assert(Ops.
size() == 7 &&
"Incompatible number of operands");
9721 ID.AddInteger(getSyntheticNodeSubclassData<MaskedHistogramSDNode>(
9722 dl.
getIROrder(), VTs, MemVT, MMO, IndexType));
9726 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9727 cast<MaskedGatherSDNode>(E)->refineAlignment(MMO);
9732 VTs, MemVT, MMO, IndexType);
9733 createOperands(
N, Ops);
9735 assert(
N->getMask().getValueType().getVectorElementCount() ==
9736 N->getIndex().getValueType().getVectorElementCount() &&
9737 "Vector width mismatch between mask and data");
9738 assert(isa<ConstantSDNode>(
N->getScale()) &&
9739 N->getScale()->getAsAPIntVal().isPowerOf2() &&
9740 "Scale should be a constant power of 2");
9741 assert(
N->getInc().getValueType().isInteger() &&
"Non integer update value");
9743 CSEMap.InsertNode(
N, IP);
9758 ID.AddInteger(getSyntheticNodeSubclassData<FPStateAccessSDNode>(
9763 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
9768 createOperands(
N, Ops);
9770 CSEMap.InsertNode(
N, IP);
9785 ID.AddInteger(getSyntheticNodeSubclassData<FPStateAccessSDNode>(
9790 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
9795 createOperands(
N, Ops);
9797 CSEMap.InsertNode(
N, IP);
9817 if (
auto *CondC = dyn_cast<ConstantSDNode>(
Cond))
9818 return CondC->isZero() ?
F :
T;
9824 if (CondC->isZero())
9850 return !Val || Val->getAPIntValue().uge(
X.getScalarValueSizeInBits());
9856 if (
X.getValueType().getScalarType() == MVT::i1)
9869 bool HasNan = (XC && XC->getValueAPF().isNaN()) ||
9871 bool HasInf = (XC && XC->getValueAPF().isInfinity()) ||
9874 if (Flags.hasNoNaNs() && (HasNan ||
X.isUndef() ||
Y.isUndef()))
9877 if (Flags.hasNoInfs() && (HasInf ||
X.isUndef() ||
Y.isUndef()))
9900 if (Opcode ==
ISD::FMUL && Flags.hasNoNaNs() && Flags.hasNoSignedZeros())
9915 switch (Ops.
size()) {
9917 case 1:
return getNode(Opcode,
DL, VT,
static_cast<const SDValue>(Ops[0]));
9918 case 2:
return getNode(Opcode,
DL, VT, Ops[0], Ops[1]);
9919 case 3:
return getNode(Opcode,
DL, VT, Ops[0], Ops[1], Ops[2]);
9934 return getNode(Opcode,
DL, VT, Ops, Flags);
9939 unsigned NumOps = Ops.
size();
9942 case 1:
return getNode(Opcode,
DL, VT, Ops[0], Flags);
9943 case 2:
return getNode(Opcode,
DL, VT, Ops[0], Ops[1], Flags);
9944 case 3:
return getNode(Opcode,
DL, VT, Ops[0], Ops[1], Ops[2], Flags);
9949 for (
const auto &
Op : Ops)
9951 "Operand is DELETED_NODE!");
9966 assert(NumOps == 5 &&
"SELECT_CC takes 5 operands!");
9968 "LHS and RHS of condition must have same type!");
9970 "True and False arms of SelectCC must have same type!");
9972 "select_cc node must be of same type as true and false value!");
9976 "Expected select_cc with vector result to have the same sized "
9977 "comparison type!");
9980 assert(NumOps == 5 &&
"BR_CC takes 5 operands!");
9982 "LHS/RHS of comparison should match types!");
9988 Opcode = ISD::VP_XOR;
9993 Opcode = ISD::VP_AND;
9995 case ISD::VP_REDUCE_MUL:
9998 Opcode = ISD::VP_REDUCE_AND;
10000 case ISD::VP_REDUCE_ADD:
10003 Opcode = ISD::VP_REDUCE_XOR;
10005 case ISD::VP_REDUCE_SMAX:
10006 case ISD::VP_REDUCE_UMIN:
10010 Opcode = ISD::VP_REDUCE_AND;
10012 case ISD::VP_REDUCE_SMIN:
10013 case ISD::VP_REDUCE_UMAX:
10017 Opcode = ISD::VP_REDUCE_OR;
10025 if (VT != MVT::Glue) {
10028 void *IP =
nullptr;
10030 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP))
10033 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
10034 createOperands(
N, Ops);
10036 CSEMap.InsertNode(
N, IP);
10038 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
10039 createOperands(
N, Ops);
10042 N->setFlags(Flags);
10059 return getNode(Opcode,
DL, VTList, Ops, Flags);
10065 return getNode(Opcode,
DL, VTList.
VTs[0], Ops, Flags);
10068 for (
const auto &
Op : Ops)
10070 "Operand is DELETED_NODE!");
10079 "Invalid add/sub overflow op!");
10081 Ops[0].getValueType() == Ops[1].getValueType() &&
10082 Ops[0].getValueType() == VTList.
VTs[0] &&
10083 "Binary operator types must match!");
10084 SDValue N1 = Ops[0], N2 = Ops[1];
10090 if (N2CV && N2CV->
isZero()) {
10122 "Invalid add/sub overflow op!");
10124 Ops[0].getValueType() == Ops[1].getValueType() &&
10125 Ops[0].getValueType() == VTList.
VTs[0] &&
10126 Ops[2].getValueType() == VTList.
VTs[1] &&
10127 "Binary operator types must match!");
10133 VTList.
VTs[0] == Ops[0].getValueType() &&
10134 VTList.
VTs[0] == Ops[1].getValueType() &&
10135 "Binary operator types must match!");
10141 unsigned OutWidth = Width * 2;
10145 Val = Val.
sext(OutWidth);
10146 Mul =
Mul.sext(OutWidth);
10148 Val = Val.
zext(OutWidth);
10149 Mul =
Mul.zext(OutWidth);
10163 VTList.
VTs[0] == Ops[0].getValueType() &&
"frexp type mismatch");
10179 "Invalid STRICT_FP_EXTEND!");
10181 Ops[1].getValueType().isFloatingPoint() &&
"Invalid FP cast!");
10183 "STRICT_FP_EXTEND result type should be vector iff the operand "
10184 "type is vector!");
10187 Ops[1].getValueType().getVectorElementCount()) &&
10188 "Vector element count mismatch!");
10190 "Invalid fpext node, dst <= src!");
10193 assert(VTList.
NumVTs == 2 && Ops.
size() == 3 &&
"Invalid STRICT_FP_ROUND!");
10195 "STRICT_FP_ROUND result type should be vector iff the operand "
10196 "type is vector!");
10199 Ops[1].getValueType().getVectorElementCount()) &&
10200 "Vector element count mismatch!");
10202 Ops[1].getValueType().isFloatingPoint() &&
10203 VTList.
VTs[0].
bitsLT(Ops[1].getValueType()) &&
10204 isa<ConstantSDNode>(Ops[2]) &&
10205 (Ops[2]->getAsZExtVal() == 0 || Ops[2]->getAsZExtVal() == 1) &&
10206 "Invalid STRICT_FP_ROUND!");
10216 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1)
10217 return getNode(Opcode,
DL, VT, N1, N2, N3.getOperand(0));
10218 else if (N3.getOpcode() ==
ISD::AND)
10219 if (
ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) {
10223 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1)
10224 return getNode(Opcode,
DL, VT, N1, N2, N3.getOperand(0));
10232 if (VTList.
VTs[VTList.
NumVTs-1] != MVT::Glue) {
10235 void *IP =
nullptr;
10236 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP))
10239 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTList);
10240 createOperands(
N, Ops);
10241 CSEMap.InsertNode(
N, IP);
10243 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTList);
10244 createOperands(
N, Ops);
10247 N->setFlags(Flags);
10256 return getNode(Opcode,
DL, VTList, std::nullopt);
10262 return getNode(Opcode,
DL, VTList, Ops);
10268 return getNode(Opcode,
DL, VTList, Ops);
10273 SDValue Ops[] = { N1, N2, N3 };
10274 return getNode(Opcode,
DL, VTList, Ops);
10279 SDValue Ops[] = { N1, N2, N3, N4 };
10280 return getNode(Opcode,
DL, VTList, Ops);
10286 SDValue Ops[] = { N1, N2, N3, N4, N5 };
10287 return getNode(Opcode,
DL, VTList, Ops);
10291 return makeVTList(SDNode::getValueTypeList(VT), 1);
10300 void *IP =
nullptr;
10306 Result =
new (Allocator)
SDVTListNode(
ID.Intern(Allocator), Array, 2);
10307 VTListMap.InsertNode(Result, IP);
10309 return Result->getSDVTList();
10319 void *IP =
nullptr;
10326 Result =
new (Allocator)
SDVTListNode(
ID.Intern(Allocator), Array, 3);
10327 VTListMap.InsertNode(Result, IP);
10329 return Result->getSDVTList();
10340 void *IP =
nullptr;
10348 Result =
new (Allocator)
SDVTListNode(
ID.Intern(Allocator), Array, 4);
10349 VTListMap.InsertNode(Result, IP);
10351 return Result->getSDVTList();
10355 unsigned NumVTs = VTs.
size();
10357 ID.AddInteger(NumVTs);
10358 for (
unsigned index = 0; index < NumVTs; index++) {
10359 ID.AddInteger(VTs[index].getRawBits());
10362 void *IP =
nullptr;
10367 Result =
new (Allocator)
SDVTListNode(
ID.Intern(Allocator), Array, NumVTs);
10368 VTListMap.InsertNode(Result, IP);
10370 return Result->getSDVTList();
10381 assert(
N->getNumOperands() == 1 &&
"Update with wrong number of operands");
10384 if (
Op ==
N->getOperand(0))
return N;
10387 void *InsertPos =
nullptr;
10388 if (
SDNode *Existing = FindModifiedNodeSlot(
N,
Op, InsertPos))
10393 if (!RemoveNodeFromCSEMaps(
N))
10394 InsertPos =
nullptr;
10397 N->OperandList[0].set(
Op);
10401 if (InsertPos) CSEMap.InsertNode(
N, InsertPos);
10406 assert(
N->getNumOperands() == 2 &&
"Update with wrong number of operands");
10409 if (Op1 ==
N->getOperand(0) && Op2 ==
N->getOperand(1))
10413 void *InsertPos =
nullptr;
10414 if (
SDNode *Existing = FindModifiedNodeSlot(
N, Op1, Op2, InsertPos))
10419 if (!RemoveNodeFromCSEMaps(
N))
10420 InsertPos =
nullptr;
10423 if (
N->OperandList[0] != Op1)
10424 N->OperandList[0].set(Op1);
10425 if (
N->OperandList[1] != Op2)
10426 N->OperandList[1].set(Op2);
10430 if (InsertPos) CSEMap.InsertNode(
N, InsertPos);
10436 SDValue Ops[] = { Op1, Op2, Op3 };
10443 SDValue Ops[] = { Op1, Op2, Op3, Op4 };
10450 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 };
10456 unsigned NumOps = Ops.
size();
10457 assert(
N->getNumOperands() == NumOps &&
10458 "Update with wrong number of operands");
10461 if (std::equal(Ops.
begin(), Ops.
end(),
N->op_begin()))
10465 void *InsertPos =
nullptr;
10466 if (
SDNode *Existing = FindModifiedNodeSlot(
N, Ops, InsertPos))
10471 if (!RemoveNodeFromCSEMaps(
N))
10472 InsertPos =
nullptr;
10475 for (
unsigned i = 0; i != NumOps; ++i)
10476 if (
N->OperandList[i] != Ops[i])
10477 N->OperandList[i].set(Ops[i]);
10481 if (InsertPos) CSEMap.InsertNode(
N, InsertPos);
10498 if (NewMemRefs.
empty()) {
10504 if (NewMemRefs.
size() == 1) {
10505 N->MemRefs = NewMemRefs[0];
10511 Allocator.template Allocate<MachineMemOperand *>(NewMemRefs.
size());
10513 N->MemRefs = MemRefsBuffer;
10514 N->NumMemRefs =
static_cast<int>(NewMemRefs.
size());
10537 SDValue Ops[] = { Op1, Op2 };
10545 SDValue Ops[] = { Op1, Op2, Op3 };
10578 SDValue Ops[] = { Op1, Op2 };
10586 New->setNodeId(-1);
10606 unsigned Order = std::min(
N->getIROrder(), OLoc.
getIROrder());
10607 N->setIROrder(Order);
10630 void *IP =
nullptr;
10631 if (VTs.
VTs[VTs.
NumVTs-1] != MVT::Glue) {
10635 return UpdateSDLocOnMergeSDNode(ON,
SDLoc(
N));
10638 if (!RemoveNodeFromCSEMaps(
N))
10643 N->ValueList = VTs.
VTs;
10653 if (Used->use_empty())
10654 DeadNodeSet.
insert(Used);
10659 MN->clearMemRefs();
10663 createOperands(
N, Ops);
10667 if (!DeadNodeSet.
empty()) {
10669 for (
SDNode *
N : DeadNodeSet)
10670 if (
N->use_empty())
10676 CSEMap.InsertNode(
N, IP);
10681 unsigned OrigOpc = Node->getOpcode();
10686#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
10687 case ISD::STRICT_##DAGN: NewOpc = ISD::DAGN; break;
10688#define CMP_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
10689 case ISD::STRICT_##DAGN: NewOpc = ISD::SETCC; break;
10690#include "llvm/IR/ConstrainedOps.def"
10693 assert(Node->getNumValues() == 2 &&
"Unexpected number of results!");
10696 SDValue InputChain = Node->getOperand(0);
10701 for (
unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
10744 SDValue Ops[] = { Op1, Op2 };
10752 SDValue Ops[] = { Op1, Op2, Op3 };
10766 SDValue Ops[] = { Op1, Op2 };
10774 SDValue Ops[] = { Op1, Op2, Op3 };
10789 SDValue Ops[] = { Op1, Op2 };
10798 SDValue Ops[] = { Op1, Op2, Op3 };
10819 bool DoCSE = VTs.
VTs[VTs.
NumVTs-1] != MVT::Glue;
10821 void *IP =
nullptr;
10827 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
10828 return cast<MachineSDNode>(UpdateSDLocOnMergeSDNode(E,
DL));
10833 N = newSDNode<MachineSDNode>(~Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
10834 createOperands(
N, Ops);
10837 CSEMap.InsertNode(
N, IP);
10850 VT, Operand, SRIdxVal);
10860 VT, Operand, Subreg, SRIdxVal);
10877 if (VTList.
VTs[VTList.
NumVTs - 1] != MVT::Glue) {
10880 void *IP =
nullptr;
10882 E->intersectFlagsWith(Flags);
10892 if (VTList.
VTs[VTList.
NumVTs - 1] != MVT::Glue) {
10895 void *IP =
nullptr;
10896 if (FindNodeOrInsertPos(
ID,
SDLoc(), IP))
10906 SDNode *
N,
unsigned R,
bool IsIndirect,
10908 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10909 "Expected inlined-at fields to agree");
10912 {}, IsIndirect,
DL, O,
10921 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10922 "Expected inlined-at fields to agree");
10935 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10936 "Expected inlined-at fields to agree");
10947 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10948 "Expected inlined-at fields to agree");
10951 Dependencies, IsIndirect,
DL, O,
10957 unsigned VReg,
bool IsIndirect,
10959 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10960 "Expected inlined-at fields to agree");
10963 {}, IsIndirect,
DL, O,
10971 unsigned O,
bool IsVariadic) {
10972 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10973 "Expected inlined-at fields to agree");
10976 DL, O, IsVariadic);
10980 unsigned OffsetInBits,
unsigned SizeInBits,
10981 bool InvalidateDbg) {
10984 assert(FromNode && ToNode &&
"Can't modify dbg values");
10989 if (
From == To || FromNode == ToNode)
11001 if (Dbg->isInvalidated())
11008 bool Changed =
false;
11009 auto NewLocOps = Dbg->copyLocationOps();
11011 NewLocOps.begin(), NewLocOps.end(),
11013 bool Match = Op == FromLocOp;
11023 auto *Expr = Dbg->getExpression();
11029 if (
auto FI = Expr->getFragmentInfo())
11030 if (OffsetInBits + SizeInBits > FI->SizeInBits)
11039 auto AdditionalDependencies = Dbg->getAdditionalDependencies();
11042 Var, Expr, NewLocOps, AdditionalDependencies, Dbg->isIndirect(),
11043 Dbg->getDebugLoc(), std::max(ToNode->
getIROrder(), Dbg->getOrder()),
11044 Dbg->isVariadic());
11047 if (InvalidateDbg) {
11049 Dbg->setIsInvalidated();
11050 Dbg->setIsEmitted();
11056 "Transferred DbgValues should depend on the new SDNode");
11062 if (!
N.getHasDebugValue())
11067 if (DV->isInvalidated())
11069 switch (
N.getOpcode()) {
11075 if (!isa<ConstantSDNode>(N0)) {
11076 bool RHSConstant = isa<ConstantSDNode>(N1);
11079 Offset =
N.getConstantOperandVal(1);
11082 if (!RHSConstant && DV->isIndirect())
11089 auto *DIExpr = DV->getExpression();
11090 auto NewLocOps = DV->copyLocationOps();
11091 bool Changed =
false;
11092 size_t OrigLocOpsSize = NewLocOps.size();
11093 for (
size_t i = 0; i < OrigLocOpsSize; ++i) {
11098 NewLocOps[i].getSDNode() != &
N)
11109 const auto *TmpDIExpr =
11117 NewLocOps.push_back(
RHS);
11123 assert(Changed &&
"Salvage target doesn't use N");
11126 DV->isVariadic() || OrigLocOpsSize != NewLocOps.size();
11128 auto AdditionalDependencies = DV->getAdditionalDependencies();
11130 DV->getVariable(), DIExpr, NewLocOps, AdditionalDependencies,
11131 DV->isIndirect(), DV->getDebugLoc(), DV->getOrder(), IsVariadic);
11133 DV->setIsInvalidated();
11134 DV->setIsEmitted();
11136 N0.
getNode()->dumprFull(
this);
11137 dbgs() <<
" into " << *DIExpr <<
'\n');
11144 TypeSize ToSize =
N.getValueSizeInBits(0);
11148 auto NewLocOps = DV->copyLocationOps();
11149 bool Changed =
false;
11150 for (
size_t i = 0; i < NewLocOps.size(); ++i) {
11152 NewLocOps[i].getSDNode() != &
N)
11159 assert(Changed &&
"Salvage target doesn't use N");
11164 DV->getAdditionalDependencies(), DV->isIndirect(),
11165 DV->getDebugLoc(), DV->getOrder(), DV->isVariadic());
11168 DV->setIsInvalidated();
11169 DV->setIsEmitted();
11171 dbgs() <<
" into " << *DbgExpression <<
'\n');
11178 assert(!Dbg->getSDNodes().empty() &&
11179 "Salvaged DbgValue should depend on a new SDNode");
11187 assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(
DL) &&
11188 "Expected inlined-at fields to agree");
11204 while (UI != UE &&
N == *UI)
11212 :
SelectionDAG::DAGUpdateListener(d), UI(ui), UE(ue) {}
11225 "Cannot replace with this method!");
11241 RAUWUpdateListener Listener(*
this, UI, UE);
11246 RemoveNodeFromCSEMaps(
User);
11258 }
while (UI != UE && *UI ==
User);
11261 AddModifiedNodeToCSEMaps(
User);
11277 for (
unsigned i = 0, e =
From->getNumValues(); i != e; ++i)
11280 "Cannot use this version of ReplaceAllUsesWith!");
11288 for (
unsigned i = 0, e =
From->getNumValues(); i != e; ++i)
11289 if (
From->hasAnyUseOfValue(i)) {
11290 assert((i < To->getNumValues()) &&
"Invalid To location");
11299 RAUWUpdateListener Listener(*
this, UI, UE);
11304 RemoveNodeFromCSEMaps(
User);
11316 }
while (UI != UE && *UI ==
User);
11320 AddModifiedNodeToCSEMaps(
User);
11334 if (
From->getNumValues() == 1)
11337 for (
unsigned i = 0, e =
From->getNumValues(); i != e; ++i) {
11347 RAUWUpdateListener Listener(*
this, UI, UE);
11352 RemoveNodeFromCSEMaps(
User);
11358 bool To_IsDivergent =
false;
11365 }
while (UI != UE && *UI ==
User);
11367 if (To_IsDivergent !=
From->isDivergent())
11372 AddModifiedNodeToCSEMaps(
User);
11385 if (
From == To)
return;
11388 if (
From.getNode()->getNumValues() == 1) {
11400 UE =
From.getNode()->use_end();
11401 RAUWUpdateListener Listener(*
this, UI, UE);
11404 bool UserRemovedFromCSEMaps =
false;
11414 if (
Use.getResNo() !=
From.getResNo()) {
11421 if (!UserRemovedFromCSEMaps) {
11422 RemoveNodeFromCSEMaps(
User);
11423 UserRemovedFromCSEMaps =
true;
11430 }
while (UI != UE && *UI ==
User);
11433 if (!UserRemovedFromCSEMaps)
11438 AddModifiedNodeToCSEMaps(
User);
11457bool operator<(
const UseMemo &L,
const UseMemo &R) {
11458 return (intptr_t)L.User < (intptr_t)R.User;
11468 for (UseMemo &Memo :
Uses)
11469 if (Memo.User ==
N)
11470 Memo.User =
nullptr;
11483 "Conflicting divergence information!");
11488 for (
const auto &
Op :
N->ops()) {
11489 if (
Op.Val.getValueType() != MVT::Other &&
Op.getNode()->isDivergent())
11500 if (
N->SDNodeBits.IsDivergent != IsDivergent) {
11501 N->SDNodeBits.IsDivergent = IsDivergent;
11504 }
while (!Worklist.
empty());
11507void SelectionDAG::CreateTopologicalOrder(std::vector<SDNode *> &Order) {
11509 Order.
reserve(AllNodes.size());
11511 unsigned NOps =
N.getNumOperands();
11514 Order.push_back(&
N);
11516 for (
size_t I = 0;
I != Order.size(); ++
I) {
11518 for (
auto *U :
N->uses()) {
11519 unsigned &UnsortedOps = Degree[U];
11520 if (0 == --UnsortedOps)
11521 Order.push_back(U);
11528 std::vector<SDNode *> TopoOrder;
11529 CreateTopologicalOrder(TopoOrder);
11530 for (
auto *
N : TopoOrder) {
11532 "Divergence bit inconsistency detected");
11555 for (
unsigned i = 0; i != Num; ++i) {
11556 unsigned FromResNo =
From[i].getResNo();
11559 E = FromNode->
use_end(); UI != E; ++UI) {
11561 if (
Use.getResNo() == FromResNo) {
11562 UseMemo Memo = { *UI, i, &
Use };
11563 Uses.push_back(Memo);
11570 RAUOVWUpdateListener Listener(*
this,
Uses);
11572 for (
unsigned UseIndex = 0, UseIndexEnd =
Uses.size();
11573 UseIndex != UseIndexEnd; ) {
11579 if (
User ==
nullptr) {
11585 RemoveNodeFromCSEMaps(
User);
11592 unsigned i =
Uses[UseIndex].Index;
11597 }
while (UseIndex != UseIndexEnd &&
Uses[UseIndex].
User ==
User);
11601 AddModifiedNodeToCSEMaps(
User);
11609 unsigned DAGSize = 0;
11625 unsigned Degree =
N.getNumOperands();
11628 N.setNodeId(DAGSize++);
11630 if (Q != SortedPos)
11631 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q));
11632 assert(SortedPos != AllNodes.end() &&
"Overran node list");
11636 N.setNodeId(Degree);
11648 unsigned Degree =
P->getNodeId();
11649 assert(Degree != 0 &&
"Invalid node degree");
11653 P->setNodeId(DAGSize++);
11654 if (
P->getIterator() != SortedPos)
11655 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(
P));
11656 assert(SortedPos != AllNodes.end() &&
"Overran node list");
11660 P->setNodeId(Degree);
11663 if (Node.getIterator() == SortedPos) {
11667 dbgs() <<
"Overran sorted position:\n";
11669 dbgs() <<
"Checking if this is due to cycles\n";
11676 assert(SortedPos == AllNodes.end() &&
11677 "Topological sort incomplete!");
11679 "First node in topological sort is not the entry token!");
11680 assert(AllNodes.front().getNodeId() == 0 &&
11681 "First node in topological sort has non-zero id!");
11682 assert(AllNodes.front().getNumOperands() == 0 &&
11683 "First node in topological sort has operands!");
11684 assert(AllNodes.back().getNodeId() == (
int)DAGSize-1 &&
11685 "Last node in topologic sort has unexpected id!");
11686 assert(AllNodes.back().use_empty() &&
11687 "Last node in topologic sort has users!");
11695 for (
SDNode *SD : DB->getSDNodes()) {
11699 SD->setHasDebugValue(
true);
11701 DbgInfo->
add(DB, isParameter);
11708 assert(isa<MemSDNode>(NewMemOpChain) &&
"Expected a memop node");
11714 if (OldChain == NewMemOpChain || OldChain.
use_empty())
11715 return NewMemOpChain;
11718 OldChain, NewMemOpChain);
11721 return TokenFactor;
11726 assert(isa<MemSDNode>(NewMemOp.
getNode()) &&
"Expected a memop node");
11734 assert(isa<ExternalSymbolSDNode>(
Op) &&
"Node should be an ExternalSymbol");
11736 auto *Symbol = cast<ExternalSymbolSDNode>(
Op)->getSymbol();
11740 if (OutFunction !=
nullptr)
11748 std::string ErrorStr;
11750 ErrorFormatter <<
"Undefined external symbol ";
11751 ErrorFormatter <<
'"' << Symbol <<
'"';
11761 return Const !=
nullptr && Const->isZero();
11770 return Const !=
nullptr && Const->isZero() && !Const->isNegative();
11775 return Const !=
nullptr && Const->isAllOnes();
11780 return Const !=
nullptr && Const->isOne();
11785 return Const !=
nullptr && Const->isMinSignedValue();
11789 unsigned OperandNo) {
11794 APInt Const = ConstV->getAPIntValue().trunc(V.getScalarValueSizeInBits());
11800 return Const.isZero();
11802 return Const.isOne();
11805 return Const.isAllOnes();
11807 return Const.isMinSignedValue();
11809 return Const.isMaxSignedValue();
11814 return OperandNo == 1 && Const.isZero();
11817 return OperandNo == 1 && Const.isOne();
11822 return ConstFP->isZero() &&
11823 (Flags.hasNoSignedZeros() || ConstFP->isNegative());
11825 return OperandNo == 1 && ConstFP->isZero() &&
11826 (Flags.hasNoSignedZeros() || !ConstFP->isNegative());
11828 return ConstFP->isExactlyValue(1.0);
11830 return OperandNo == 1 && ConstFP->isExactlyValue(1.0);
11834 EVT VT = V.getValueType();
11836 APFloat NeutralAF = !Flags.hasNoNaNs()
11838 : !Flags.hasNoInfs()
11844 return ConstFP->isExactlyValue(NeutralAF);
11853 V = V.getOperand(0);
11858 while (V.getOpcode() ==
ISD::BITCAST && V.getOperand(0).hasOneUse())
11859 V = V.getOperand(0);
11865 V = V.getOperand(0);
11871 V = V.getOperand(0);
11879 unsigned NumBits = V.getScalarValueSizeInBits();
11882 return C && (
C->getAPIntValue().countr_one() >= NumBits);
11886 bool AllowTruncation) {
11887 EVT VT =
N.getValueType();
11896 bool AllowTruncation) {
11903 EVT VecEltVT =
N->getValueType(0).getVectorElementType();
11904 if (
auto *CN = dyn_cast<ConstantSDNode>(
N->getOperand(0))) {
11905 EVT CVT = CN->getValueType(0);
11906 assert(CVT.
bitsGE(VecEltVT) &&
"Illegal splat_vector element extension");
11907 if (AllowTruncation || CVT == VecEltVT)
11914 ConstantSDNode *CN = BV->getConstantSplatNode(DemandedElts, &UndefElements);
11919 if (CN && (UndefElements.
none() || AllowUndefs)) {
11921 EVT NSVT =
N.getValueType().getScalarType();
11922 assert(CVT.
bitsGE(NSVT) &&
"Illegal build vector element extension");
11923 if (AllowTruncation || (CVT == NSVT))
11932 EVT VT =
N.getValueType();
11940 const APInt &DemandedElts,
11941 bool AllowUndefs) {
11948 BV->getConstantFPSplatNode(DemandedElts, &UndefElements);
11950 if (CN && (UndefElements.
none() || AllowUndefs))
11965 return C &&
C->isZero();
11971 return C &&
C->isOne();
11976 unsigned BitWidth =
N.getScalarValueSizeInBits();
11978 return C &&
C->isAllOnes() &&
C->getValueSizeInBits(0) ==
BitWidth;
11987 :
SDNode(Opc, Order, dl, VTs), MemoryVT(memvt), MMO(mmo) {
12011 std::vector<EVT> VTs;
12024const EVT *SDNode::getValueTypeList(
EVT VT) {
12025 static std::set<EVT, EVT::compareRawBits> EVTs;
12026 static EVTArray SimpleVTArray;
12031 return &(*EVTs.insert(VT).first);
12045 if (UI.getUse().getResNo() ==
Value) {
12062 if (UI.getUse().getResNo() ==
Value)
12100 return any_of(
N->op_values(),
12101 [
this](
SDValue Op) { return this == Op.getNode(); });
12115 unsigned Depth)
const {
12116 if (*
this == Dest)
return true;
12120 if (
Depth == 0)
return false;
12140 return Op.reachesChainWithoutSideEffects(Dest, Depth - 1);
12145 if (
LoadSDNode *Ld = dyn_cast<LoadSDNode>(*
this)) {
12146 if (Ld->isUnordered())
12147 return Ld->getChain().reachesChainWithoutSideEffects(Dest,
Depth-1);
12166 bool AllowPartials) {
12175 return Op.getOpcode() ==
unsigned(BinOp);
12181 unsigned CandidateBinOp =
Op.getOpcode();
12182 if (
Op.getValueType().isFloatingPoint()) {
12184 switch (CandidateBinOp) {
12186 if (!Flags.hasNoSignedZeros() || !Flags.hasAllowReassociation())
12196 auto PartialReduction = [&](
SDValue Op,
unsigned NumSubElts) {
12197 if (!AllowPartials || !
Op)
12199 EVT OpVT =
Op.getValueType();
12222 unsigned Stages =
Log2_32(
Op.getValueType().getVectorNumElements());
12224 for (
unsigned i = 0; i < Stages; ++i) {
12225 unsigned MaskEnd = (1 << i);
12227 if (
Op.getOpcode() != CandidateBinOp)
12228 return PartialReduction(PrevOp, MaskEnd);
12237 Shuffle = dyn_cast<ShuffleVectorSDNode>(Op1);
12244 return PartialReduction(PrevOp, MaskEnd);
12249 return PartialReduction(PrevOp, MaskEnd);
12256 while (
Op.getOpcode() == CandidateBinOp) {
12257 unsigned NumElts =
Op.getValueType().getVectorNumElements();
12265 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
12266 if (NumSrcElts != (2 * NumElts))
12281 EVT VT =
N->getValueType(0);
12290 else if (NE > ResNE)
12293 if (
N->getNumValues() == 2) {
12296 EVT VT1 =
N->getValueType(1);
12300 for (i = 0; i != NE; ++i) {
12301 for (
unsigned j = 0, e =
N->getNumOperands(); j != e; ++j) {
12302 SDValue Operand =
N->getOperand(j);
12321 assert(
N->getNumValues() == 1 &&
12322 "Can't unroll a vector with multiple results!");
12328 for (i= 0; i != NE; ++i) {
12329 for (
unsigned j = 0, e =
N->getNumOperands(); j != e; ++j) {
12330 SDValue Operand =
N->getOperand(j);
12343 switch (
N->getOpcode()) {
12370 for (; i < ResNE; ++i)
12379 unsigned Opcode =
N->getOpcode();
12383 "Expected an overflow opcode");
12385 EVT ResVT =
N->getValueType(0);
12386 EVT OvVT =
N->getValueType(1);
12395 else if (NE > ResNE)
12407 for (
unsigned i = 0; i < NE; ++i) {
12408 SDValue Res =
getNode(Opcode, dl, VTs, LHSScalars[i], RHSScalars[i]);
12431 if (LD->isVolatile() ||
Base->isVolatile())
12434 if (!LD->isSimple())
12436 if (LD->isIndexed() ||
Base->isIndexed())
12438 if (LD->getChain() !=
Base->getChain())
12440 EVT VT = LD->getMemoryVT();
12448 if (BaseLocDecomp.equalBaseIndex(LocDecomp, *
this,
Offset))
12449 return (Dist * (int64_t)Bytes ==
Offset);
12458 int64_t GVOffset = 0;
12470 int FrameIdx = INT_MIN;
12471 int64_t FrameOffset = 0;
12473 FrameIdx = FI->getIndex();
12475 isa<FrameIndexSDNode>(
Ptr.getOperand(0))) {
12477 FrameIdx = cast<FrameIndexSDNode>(
Ptr.getOperand(0))->getIndex();
12478 FrameOffset =
Ptr.getConstantOperandVal(1);
12481 if (FrameIdx != INT_MIN) {
12486 return std::nullopt;
12496 "Split node must be a scalar type");
12501 return std::make_pair(
Lo,
Hi);
12514 return std::make_pair(LoVT, HiVT);
12522 bool *HiIsEmpty)
const {
12532 "Mixing fixed width and scalable vectors when enveloping a type");
12537 *HiIsEmpty =
false;
12545 return std::make_pair(LoVT, HiVT);
12550std::pair<SDValue, SDValue>
12555 "Splitting vector with an invalid mixture of fixed and scalable "
12558 N.getValueType().getVectorMinNumElements() &&
12559 "More vector elements requested than available!");
12569 return std::make_pair(
Lo,
Hi);
12576 EVT VT =
N.getValueType();
12578 "Expecting the mask to be an evenly-sized vector");
12586 return std::make_pair(
Lo,
Hi);
12591 EVT VT =
N.getValueType();
12600 unsigned Start,
unsigned Count,
12602 EVT VT =
Op.getValueType();
12605 if (EltVT ==
EVT())
12608 for (
unsigned i = Start, e = Start + Count; i != e; ++i) {
12621 return Val.MachineCPVal->getType();
12622 return Val.ConstVal->getType();
12626 unsigned &SplatBitSize,
12627 bool &HasAnyUndefs,
12628 unsigned MinSplatBits,
12629 bool IsBigEndian)
const {
12633 if (MinSplatBits > VecWidth)
12638 SplatValue =
APInt(VecWidth, 0);
12639 SplatUndef =
APInt(VecWidth, 0);
12646 assert(NumOps > 0 &&
"isConstantSplat has 0-size build vector");
12649 for (
unsigned j = 0; j < NumOps; ++j) {
12650 unsigned i = IsBigEndian ? NumOps - 1 - j : j;
12652 unsigned BitPos = j * EltWidth;
12655 SplatUndef.
setBits(BitPos, BitPos + EltWidth);
12656 else if (
auto *CN = dyn_cast<ConstantSDNode>(OpVal))
12657 SplatValue.
insertBits(CN->getAPIntValue().zextOrTrunc(EltWidth), BitPos);
12658 else if (
auto *CN = dyn_cast<ConstantFPSDNode>(OpVal))
12659 SplatValue.
insertBits(CN->getValueAPF().bitcastToAPInt(), BitPos);
12666 HasAnyUndefs = (SplatUndef != 0);
12669 while (VecWidth > 8) {
12674 unsigned HalfSize = VecWidth / 2;
12681 if ((HighValue & ~LowUndef) != (LowValue & ~HighUndef) ||
12682 MinSplatBits > HalfSize)
12685 SplatValue = HighValue | LowValue;
12686 SplatUndef = HighUndef & LowUndef;
12688 VecWidth = HalfSize;
12697 SplatBitSize = VecWidth;
12704 if (UndefElements) {
12705 UndefElements->
clear();
12706 UndefElements->
resize(NumOps);
12712 for (
unsigned i = 0; i != NumOps; ++i) {
12713 if (!DemandedElts[i])
12716 if (
Op.isUndef()) {
12718 (*UndefElements)[i] =
true;
12719 }
else if (!Splatted) {
12721 }
else if (Splatted !=
Op) {
12727 unsigned FirstDemandedIdx = DemandedElts.
countr_zero();
12729 "Can only have a splat without a constant for all undefs.");
12746 if (UndefElements) {
12747 UndefElements->
clear();
12748 UndefElements->
resize(NumOps);
12756 for (
unsigned I = 0;
I != NumOps; ++
I)
12758 (*UndefElements)[
I] =
true;
12761 for (
unsigned SeqLen = 1; SeqLen < NumOps; SeqLen *= 2) {
12762 Sequence.append(SeqLen,
SDValue());
12763 for (
unsigned I = 0;
I != NumOps; ++
I) {
12764 if (!DemandedElts[
I])
12766 SDValue &SeqOp = Sequence[
I % SeqLen];
12768 if (
Op.isUndef()) {
12773 if (SeqOp && !SeqOp.
isUndef() && SeqOp !=
Op) {
12779 if (!Sequence.empty())
12783 assert(Sequence.empty() &&
"Failed to empty non-repeating sequence pattern");
12796 return dyn_cast_or_null<ConstantSDNode>(
12802 return dyn_cast_or_null<ConstantSDNode>(
getSplatValue(UndefElements));
12808 return dyn_cast_or_null<ConstantFPSDNode>(
12814 return dyn_cast_or_null<ConstantFPSDNode>(
getSplatValue(UndefElements));
12821 dyn_cast_or_null<ConstantFPSDNode>(
getSplatValue(UndefElements))) {
12824 const APFloat &APF = CN->getValueAPF();
12830 return IntVal.exactLogBase2();
12836 bool IsLittleEndian,
unsigned DstEltSizeInBits,
12844 assert(((NumSrcOps * SrcEltSizeInBits) % DstEltSizeInBits) == 0 &&
12845 "Invalid bitcast scale");
12850 BitVector SrcUndeElements(NumSrcOps,
false);
12852 for (
unsigned I = 0;
I != NumSrcOps; ++
I) {
12854 if (
Op.isUndef()) {
12855 SrcUndeElements.
set(
I);
12858 auto *CInt = dyn_cast<ConstantSDNode>(
Op);
12859 auto *CFP = dyn_cast<ConstantFPSDNode>(
Op);
12860 assert((CInt || CFP) &&
"Unknown constant");
12861 SrcBitElements[
I] = CInt ? CInt->getAPIntValue().trunc(SrcEltSizeInBits)
12862 : CFP->getValueAPF().bitcastToAPInt();
12866 recastRawBits(IsLittleEndian, DstEltSizeInBits, RawBitElements,
12867 SrcBitElements, UndefElements, SrcUndeElements);
12872 unsigned DstEltSizeInBits,
12877 unsigned NumSrcOps = SrcBitElements.
size();
12878 unsigned SrcEltSizeInBits = SrcBitElements[0].getBitWidth();
12879 assert(((NumSrcOps * SrcEltSizeInBits) % DstEltSizeInBits) == 0 &&
12880 "Invalid bitcast scale");
12881 assert(NumSrcOps == SrcUndefElements.
size() &&
12882 "Vector size mismatch");
12884 unsigned NumDstOps = (NumSrcOps * SrcEltSizeInBits) / DstEltSizeInBits;
12885 DstUndefElements.
clear();
12886 DstUndefElements.
resize(NumDstOps,
false);
12890 if (SrcEltSizeInBits <= DstEltSizeInBits) {
12891 unsigned Scale = DstEltSizeInBits / SrcEltSizeInBits;
12892 for (
unsigned I = 0;
I != NumDstOps; ++
I) {
12893 DstUndefElements.
set(
I);
12894 APInt &DstBits = DstBitElements[
I];
12895 for (
unsigned J = 0; J != Scale; ++J) {
12896 unsigned Idx = (
I * Scale) + (IsLittleEndian ? J : (Scale - J - 1));
12897 if (SrcUndefElements[
Idx])
12899 DstUndefElements.
reset(
I);
12900 const APInt &SrcBits = SrcBitElements[
Idx];
12902 "Illegal constant bitwidths");
12903 DstBits.
insertBits(SrcBits, J * SrcEltSizeInBits);
12910 unsigned Scale = SrcEltSizeInBits / DstEltSizeInBits;
12911 for (
unsigned I = 0;
I != NumSrcOps; ++
I) {
12912 if (SrcUndefElements[
I]) {
12913 DstUndefElements.
set(
I * Scale, (
I + 1) * Scale);
12916 const APInt &SrcBits = SrcBitElements[
I];
12917 for (
unsigned J = 0; J != Scale; ++J) {
12918 unsigned Idx = (
I * Scale) + (IsLittleEndian ? J : (Scale - J - 1));
12919 APInt &DstBits = DstBitElements[
Idx];
12920 DstBits = SrcBits.
extractBits(DstEltSizeInBits, J * DstEltSizeInBits);
12927 unsigned Opc =
Op.getOpcode();
12934std::optional<std::pair<APInt, APInt>>
12938 return std::nullopt;
12942 return std::nullopt;
12949 return std::nullopt;
12951 for (
unsigned i = 2; i < NumOps; ++i) {
12953 return std::nullopt;
12956 if (Val != (Start + (Stride * i)))
12957 return std::nullopt;
12960 return std::make_pair(Start, Stride);
12976 for (
int Idx = Mask[i]; i != e; ++i)
12977 if (Mask[i] >= 0 && Mask[i] !=
Idx)
12985 if (isa<ConstantSDNode>(
N))
12986 return N.getNode();
12988 return N.getNode();
12996 isa<ConstantSDNode>(
N.getOperand(0)))
12997 return N.getNode();
13004 if (isa<ConstantFPSDNode>(
N))
13005 return N.getNode();
13008 return N.getNode();
13011 isa<ConstantFPSDNode>(
N.getOperand(0)))
13012 return N.getNode();
13018 assert(!Node->OperandList &&
"Node already has operands");
13020 "too many operands to fit into SDNode");
13021 SDUse *Ops = OperandRecycler.allocate(
13024 bool IsDivergent =
false;
13025 for (
unsigned I = 0;
I != Vals.
size(); ++
I) {
13026 Ops[
I].setUser(Node);
13027 Ops[
I].setInitial(Vals[
I]);
13028 if (Ops[
I].Val.getValueType() != MVT::Other)
13032 Node->OperandList = Ops;
13035 Node->SDNodeBits.IsDivergent = IsDivergent;
13043 while (Vals.
size() > Limit) {
13044 unsigned SliceIdx = Vals.
size() - Limit;
13118 const SDLoc &DLoc) {
13123 Entry.Ty =
Ptr.getValueType().getTypeForEVT(*
getContext());
13124 Args.push_back(Entry);
13136 assert(
From && To &&
"Invalid SDNode; empty source SDValue?");
13137 auto I = SDEI.find(
From);
13138 if (
I == SDEI.end())
13143 NodeExtraInfo NEI =
I->second;
13152 SDEI[To] = std::move(NEI);
13171 Leafs.emplace_back(
N);
13174 if (!FromReach.
insert(
N).second)
13182 auto DeepCopyTo = [&](
auto &&Self,
const SDNode *
N) {
13185 if (!Visited.
insert(
N).second)
13190 if (!Self(Self,
Op.getNode()))
13210 for (
const SDNode *
N : StartFrom)
13211 VisitFrom(VisitFrom,
N,
MaxDepth - PrevDepth);
13223 errs() <<
"warning: incomplete propagation of SelectionDAG::NodeExtraInfo\n";
13224 assert(
false &&
"From subgraph too complex - increase max. MaxDepth?");
13226 SDEI[To] = std::move(NEI);
13240 if (!Visited.
insert(
N).second) {
13241 errs() <<
"Detected cycle in SelectionDAG\n";
13242 dbgs() <<
"Offending node:\n";
13243 N->dumprFull(DAG);
dbgs() <<
"\n";
13259 bool check = force;
13260#ifdef EXPENSIVE_CHECKS
13264 assert(
N &&
"Checking nonexistent SDNode");
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static bool isConstant(const MachineInstr &MI)
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
This file implements the APSInt class, which is a simple class that represents an arbitrary sized int...
This file implements the BitVector class.
BlockVerifier::State From
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
static std::optional< bool > isBigEndian(const SmallDenseMap< int64_t, int64_t, 8 > &MemOffset2Idx, int64_t LowestIdx)
Given a map from byte offsets in memory to indices in a load/store, determine if that map corresponds...
#define __asan_unpoison_memory_region(p, size)
#define LLVM_LIKELY(EXPR)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
Looks at all the uses of the given value Returns the Liveness deduced from the uses of this value Adds all uses that cause the result to be MaybeLive to MaybeLiveRetUses If the result is MaybeLiveUses might be modified but its content should be ignored(since it might not be complete). DeadArgumentEliminationPass
Given that RA is a live propagate it s liveness to any other values it uses(according to Uses). void DeadArgumentEliminationPass
Given that RA is a live value
This file defines the DenseSet and SmallDenseSet classes.
This file contains constants used for implementing Dwarf debug support.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
This file defines a hash set that can be used to remove duplication of nodes in a graph.
Rewrite Partial Register Uses
static const unsigned MaxDepth
static Register getMemsetValue(Register Val, LLT Ty, MachineIRBuilder &MIB)
static bool shouldLowerMemFuncForSize(const MachineFunction &MF)
static bool isZero(Value *V, const DataLayout &DL, DominatorTree *DT, AssumptionCache *AC)
static Align getPrefTypeAlign(EVT VT, SelectionDAG &DAG)
mir Rename Register Operands
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
unsigned const TargetRegisterInfo * TRI
This file provides utility analysis objects describing memory locations.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
PowerPC Reduce CR logical Operation
const SmallVectorImpl< MachineOperand > & Cond
Contains matchers for matching SelectionDAG nodes and values.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static uint64_t umul_ov(uint64_t i, uint64_t j, bool &Overflow)
static SDValue getMemsetStores(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, Align Alignment, bool isVol, bool AlwaysInline, MachinePointerInfo DstPtrInfo, const AAMDNodes &AAInfo)
Lower the call to 'memset' intrinsic function into a series of store operations.
static std::optional< APInt > FoldValueWithUndef(unsigned Opcode, const APInt &C1, bool IsUndef1, const APInt &C2, bool IsUndef2)
static SDValue FoldSTEP_VECTOR(const SDLoc &DL, EVT VT, SDValue Step, SelectionDAG &DAG)
static void AddNodeIDNode(FoldingSetNodeID &ID, unsigned OpC, SDVTList VTList, ArrayRef< SDValue > OpList)
static SDValue getMemsetStringVal(EVT VT, const SDLoc &dl, SelectionDAG &DAG, const TargetLowering &TLI, const ConstantDataArraySlice &Slice)
getMemsetStringVal - Similar to getMemsetValue.
static cl::opt< bool > EnableMemCpyDAGOpt("enable-memcpy-dag-opt", cl::Hidden, cl::init(true), cl::desc("Gang up loads and stores generated by inlining of memcpy"))
static bool haveNoCommonBitsSetCommutative(SDValue A, SDValue B)
static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList)
AddNodeIDValueTypes - Value type lists are intern'd so we can represent them solely with their pointe...
static void commuteShuffle(SDValue &N1, SDValue &N2, MutableArrayRef< int > M)
Swaps the values of N1 and N2.
static bool isMemSrcFromConstant(SDValue Src, ConstantDataArraySlice &Slice)
Returns true if memcpy source is constant data.
static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, Align Alignment, bool isVol, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo)
static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, Align Alignment, bool isVol, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo, AAResults *AA)
static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC)
AddNodeIDOpcode - Add the node opcode to the NodeID data.
static ISD::CondCode getSetCCInverseImpl(ISD::CondCode Op, bool isIntegerLike)
static bool doNotCSE(SDNode *N)
doNotCSE - Return true if CSE should not be performed for this node.
static cl::opt< int > MaxLdStGlue("ldstmemcpy-glue-max", cl::desc("Number limit for gluing ld/st of memcpy."), cl::Hidden, cl::init(0))
static void AddNodeIDOperands(FoldingSetNodeID &ID, ArrayRef< SDValue > Ops)
AddNodeIDOperands - Various routines for adding operands to the NodeID data.
static SDValue foldCONCAT_VECTORS(const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops, SelectionDAG &DAG)
Try to simplify vector concatenation to an input value, undef, or build vector.
static MachinePointerInfo InferPointerInfo(const MachinePointerInfo &Info, SelectionDAG &DAG, SDValue Ptr, int64_t Offset=0)
InferPointerInfo - If the specified ptr/offset is a frame index, infer a MachinePointerInfo record fr...
static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N)
If this is an SDNode with special info, add this info to the NodeID data.
static void NewSDValueDbgMsg(SDValue V, StringRef Msg, SelectionDAG *G)
static SDVTList makeVTList(const EVT *VTs, unsigned NumVTs)
makeVTList - Return an instance of the SDVTList struct initialized with the specified members.
static void VerifySDNode(SDNode *N, const TargetLowering *TLI)
VerifySDNode - Check the given SDNode. Aborts if it is invalid.
static void checkForCyclesHelper(const SDNode *N, SmallPtrSetImpl< const SDNode * > &Visited, SmallPtrSetImpl< const SDNode * > &Checked, const llvm::SelectionDAG *DAG)
static void chainLoadsAndStoresForMemcpy(SelectionDAG &DAG, const SDLoc &dl, SmallVector< SDValue, 32 > &OutChains, unsigned From, unsigned To, SmallVector< SDValue, 16 > &OutLoadChains, SmallVector< SDValue, 16 > &OutStoreChains)
static int isSignedOp(ISD::CondCode Opcode)
For an integer comparison, return 1 if the comparison is a signed operation and 2 if the result is an...
static std::optional< APInt > FoldValue(unsigned Opcode, const APInt &C1, const APInt &C2)
static SDValue FoldBUILD_VECTOR(const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops, SelectionDAG &DAG)
static void checkAddrSpaceIsValidForLibcall(const TargetLowering *TLI, unsigned AS)
static Constant * ConstantFold(Instruction *I, const DataLayout &DL, const SmallDenseMap< Value *, Constant * > &ConstantPool)
Try to fold instruction I into a constant.
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
This file describes how to lower LLVM code to machine code.
static std::optional< unsigned > getOpcode(ArrayRef< VPValue * > Values)
Returns the opcode of Values or ~0 if they do not all agree.
static OverflowResult mapOverflowResult(ConstantRange::OverflowResult OR)
Convert ConstantRange OverflowResult into ValueTracking OverflowResult.
static unsigned getSize(unsigned Kind)
bool pointsToConstantMemory(const MemoryLocation &Loc, bool OrLocal=false)
Checks whether the given location points to constant memory, or if OrLocal is true whether it points ...
static APFloat getQNaN(const fltSemantics &Sem, bool Negative=false, const APInt *payload=nullptr)
Factory for QNaN values.
opStatus divide(const APFloat &RHS, roundingMode RM)
void copySign(const APFloat &RHS)
opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)
opStatus subtract(const APFloat &RHS, roundingMode RM)
bool isExactlyValue(double V) const
We don't rely on operator== working on double values, as it returns true for things that are clearly ...
opStatus add(const APFloat &RHS, roundingMode RM)
opStatus convertFromAPInt(const APInt &Input, bool IsSigned, roundingMode RM)
opStatus multiply(const APFloat &RHS, roundingMode RM)
opStatus fusedMultiplyAdd(const APFloat &Multiplicand, const APFloat &Addend, roundingMode RM)
static APFloat getLargest(const fltSemantics &Sem, bool Negative=false)
Returns the largest finite number in the given semantics.
opStatus convertToInteger(MutableArrayRef< integerPart > Input, unsigned int Width, bool IsSigned, roundingMode RM, bool *IsExact) const
static APFloat getInf(const fltSemantics &Sem, bool Negative=false)
Factory for Positive and Negative Infinity.
opStatus mod(const APFloat &RHS)
static APFloat getNaN(const fltSemantics &Sem, bool Negative=false, uint64_t payload=0)
Factory for NaN values.
Class for arbitrary precision integers.
APInt umul_ov(const APInt &RHS, bool &Overflow) const
APInt usub_sat(const APInt &RHS) const
APInt udiv(const APInt &RHS) const
Unsigned division operation.
static APInt getAllOnes(unsigned numBits)
Return an APInt of a specified width with all bits set.
void clearBit(unsigned BitPosition)
Set a given bit to 0.
APInt zext(unsigned width) const
Zero extend to a new width.
static APInt getSignMask(unsigned BitWidth)
Get the SignMask for a specific bit width.
uint64_t getZExtValue() const
Get zero extended value.
void setHighBits(unsigned hiBits)
Set the top hiBits bits.
unsigned popcount() const
Count the number of bits set.
void setBitsFrom(unsigned loBit)
Set the top bits starting from loBit.
APInt getHiBits(unsigned numBits) const
Compute an APInt containing numBits highbits from this APInt.
APInt zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
unsigned getActiveBits() const
Compute the number of active bits in the value.
APInt trunc(unsigned width) const
Truncate to new width.
void setBit(unsigned BitPosition)
Set the given bit to 1 whose position is given as "bitPosition".
APInt abs() const
Get the absolute value.
APInt sadd_sat(const APInt &RHS) const
bool isAllOnes() const
Determine if all bits are set. This is true for zero-width values.
bool ugt(const APInt &RHS) const
Unsigned greater than comparison.
bool isZero() const
Determine if this value is zero, i.e. all bits are clear.
APInt urem(const APInt &RHS) const
Unsigned remainder operation.
unsigned getBitWidth() const
Return the number of bits in the APInt.
bool ult(const APInt &RHS) const
Unsigned less than comparison.
static APInt getSignedMaxValue(unsigned numBits)
Gets maximum signed value of APInt for a specific bit width.
bool isNegative() const
Determine sign of this APInt.
APInt sdiv(const APInt &RHS) const
Signed division function for APInt.
void clearAllBits()
Set every bit to 0.
APInt rotr(unsigned rotateAmt) const
Rotate right by rotateAmt.
APInt reverseBits() const
void ashrInPlace(unsigned ShiftAmt)
Arithmetic right-shift this APInt by ShiftAmt in place.
bool sle(const APInt &RHS) const
Signed less or equal comparison.
unsigned countr_zero() const
Count the number of trailing zero bits.
unsigned getNumSignBits() const
Computes the number of leading bits of this APInt that are equal to its sign bit.
unsigned countl_zero() const
The APInt version of std::countl_zero.
static APInt getSplat(unsigned NewLen, const APInt &V)
Return a value containing V broadcasted over NewLen bits.
static APInt getSignedMinValue(unsigned numBits)
Gets minimum signed value of APInt for a specific bit width.
APInt sshl_sat(const APInt &RHS) const
APInt ushl_sat(const APInt &RHS) const
APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
APInt rotl(unsigned rotateAmt) const
Rotate left by rotateAmt.
void insertBits(const APInt &SubBits, unsigned bitPosition)
Insert the bits from a smaller APInt starting at bitPosition.
void clearLowBits(unsigned loBits)
Set bottom loBits bits to 0.
unsigned logBase2() const
APInt uadd_sat(const APInt &RHS) const
APInt ashr(unsigned ShiftAmt) const
Arithmetic right-shift function.
void setAllBits()
Set every bit to 1.
APInt srem(const APInt &RHS) const
Function for signed remainder operation.
bool isNonNegative() const
Determine if this APInt Value is non-negative (>= 0)
bool ule(const APInt &RHS) const
Unsigned less or equal comparison.
APInt sext(unsigned width) const
Sign extend to a new width.
void setBits(unsigned loBit, unsigned hiBit)
Set the bits from loBit (inclusive) to hiBit (exclusive) to 1.
APInt shl(unsigned shiftAmt) const
Left-shift function.
bool isSubsetOf(const APInt &RHS) const
This operation checks that all bits set in this APInt are also set in RHS.
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Constructs an APInt value that has the bottom loBitsSet bits set.
static APInt getZero(unsigned numBits)
Get the '0' value for the specified bit-width.
void setLowBits(unsigned loBits)
Set the bottom loBits bits.
APInt extractBits(unsigned numBits, unsigned bitPosition) const
Return an APInt with the extracted bits [bitPosition,bitPosition+numBits).
bool sge(const APInt &RHS) const
Signed greater or equal comparison.
static APInt getBitsSetFrom(unsigned numBits, unsigned loBit)
Constructs an APInt value that has a contiguous range of bits set.
static APInt getOneBitSet(unsigned numBits, unsigned BitNo)
Return an APInt with exactly one bit set in the result.
void lshrInPlace(unsigned ShiftAmt)
Logical right-shift this APInt by ShiftAmt in place.
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
bool uge(const APInt &RHS) const
Unsigned greater or equal comparison.
APInt ssub_sat(const APInt &RHS) const
An arbitrary precision integer that knows its signedness.
Recycle small arrays allocated from a BumpPtrAllocator.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
This is an SDNode representing atomic operations.
static BaseIndexOffset match(const SDNode *N, const SelectionDAG &DAG)
Parses tree in N for base, index, offset addresses.
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
void clear()
clear - Removes all bits from the bitvector.
bool none() const
none - Returns true if none of the bits are set.
size_type size() const
size - Returns the number of bits in this bitvector.
int64_t getOffset() const
unsigned getTargetFlags() const
const BlockAddress * getBlockAddress() const
The address of a basic block.
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
A "pseudo-class" with methods for operating on BUILD_VECTORs.
bool getConstantRawBits(bool IsLittleEndian, unsigned DstEltSizeInBits, SmallVectorImpl< APInt > &RawBitElements, BitVector &UndefElements) const
Extract the raw bit data from a build vector of Undef, Constant or ConstantFP node elements.
static void recastRawBits(bool IsLittleEndian, unsigned DstEltSizeInBits, SmallVectorImpl< APInt > &DstBitElements, ArrayRef< APInt > SrcBitElements, BitVector &DstUndefElements, const BitVector &SrcUndefElements)
Recast bit data SrcBitElements to DstEltSizeInBits wide elements.
bool getRepeatedSequence(const APInt &DemandedElts, SmallVectorImpl< SDValue > &Sequence, BitVector *UndefElements=nullptr) const
Find the shortest repeating sequence of values in the build vector.
ConstantFPSDNode * getConstantFPSplatNode(const APInt &DemandedElts, BitVector *UndefElements=nullptr) const
Returns the demanded splatted constant FP or null if this is not a constant FP splat.
std::optional< std::pair< APInt, APInt > > isConstantSequence() const
If this BuildVector is constant and represents the numerical series "<a, a+n, a+2n,...
SDValue getSplatValue(const APInt &DemandedElts, BitVector *UndefElements=nullptr) const
Returns the demanded splatted value or a null value if this is not a splat.
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
Check if this is a constant splat, and if so, find the smallest element size that splats the vector.
ConstantSDNode * getConstantSplatNode(const APInt &DemandedElts, BitVector *UndefElements=nullptr) const
Returns the demanded splatted constant or null if this is not a constant splat.
int32_t getConstantFPSplatPow2ToLog2Int(BitVector *UndefElements, uint32_t BitWidth) const
If this is a constant FP splat and the splatted constant FP is an exact power or 2,...
LLVM_ATTRIBUTE_RETURNS_NONNULL void * Allocate(size_t Size, Align Alignment)
Allocate space at the specified alignment.
void Reset()
Deallocate all but the current slab and reset the current pointer to the beginning of it,...
static bool isValueValidForType(EVT VT, const APFloat &Val)
const APFloat & getValueAPF() const
bool isExactlyValue(double V) const
We don't rely on operator== working on double values, as it returns true for things that are clearly ...
ConstantFP - Floating Point Values [float, double].
This is the shared class of boolean and integer constants.
unsigned getBitWidth() const
getBitWidth - Return the scalar bitwidth of this constant.
const APInt & getValue() const
Return the constant as an APInt value reference.
bool isMachineConstantPoolEntry() const
This class represents a range of values.
ConstantRange multiply(const ConstantRange &Other) const
Return a new range representing the possible values resulting from a multiplication of a value in thi...
const APInt * getSingleElement() const
If this set contains a single element, return it, otherwise return null.
static ConstantRange fromKnownBits(const KnownBits &Known, bool IsSigned)
Initialize a range based on a known bits constraint.
OverflowResult unsignedSubMayOverflow(const ConstantRange &Other) const
Return whether unsigned sub of the two ranges always/never overflows.
OverflowResult unsignedAddMayOverflow(const ConstantRange &Other) const
Return whether unsigned add of the two ranges always/never overflows.
KnownBits toKnownBits() const
Return known bits for values in this range.
ConstantRange zeroExtend(uint32_t BitWidth) const
Return a new range in the specified integer type, which must be strictly larger than the current type...
APInt getSignedMin() const
Return the smallest signed value contained in the ConstantRange.
OverflowResult unsignedMulMayOverflow(const ConstantRange &Other) const
Return whether unsigned mul of the two ranges always/never overflows.
ConstantRange signExtend(uint32_t BitWidth) const
Return a new range in the specified integer type, which must be strictly larger than the current type...
APInt getUnsignedMax() const
Return the largest unsigned value contained in the ConstantRange.
APInt getSignedMax() const
Return the largest signed value contained in the ConstantRange.
OverflowResult
Represents whether an operation on the given constant range is known to always or never overflow.
@ NeverOverflows
Never overflows.
@ AlwaysOverflowsHigh
Always overflows in the direction of signed/unsigned max value.
@ AlwaysOverflowsLow
Always overflows in the direction of signed/unsigned min value.
@ MayOverflow
May or may not overflow.
uint32_t getBitWidth() const
Get the bit width of this ConstantRange.
OverflowResult signedSubMayOverflow(const ConstantRange &Other) const
Return whether signed sub of the two ranges always/never overflows.
uint64_t getZExtValue() const
const APInt & getAPIntValue() const
This is an important base class in LLVM.
Constant * getSplatValue(bool AllowPoison=false) const
If all elements of the vector constant have the same value, return that value.
Constant * getAggregateElement(unsigned Elt) const
For aggregates (struct/array/vector) return the constant that corresponds to the specified element if...
static ExtOps getExtOps(unsigned FromSize, unsigned ToSize, bool Signed)
Returns the ops for a zero- or sign-extension in a DIExpression.
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
static DIExpression * appendOpsToArg(const DIExpression *Expr, ArrayRef< uint64_t > Ops, unsigned ArgNo, bool StackValue=false)
Create a copy of Expr by appending the given list of Ops to each instance of the operand DW_OP_LLVM_a...
static const DIExpression * convertToVariadicExpression(const DIExpression *Expr)
If Expr is a non-variadic expression (i.e.
static std::optional< DIExpression * > createFragmentExpression(const DIExpression *Expr, unsigned OffsetInBits, unsigned SizeInBits)
Create a DIExpression to describe one part of an aggregate variable that is fragmented across multipl...
Base class for variables.
This class represents an Operation in the Expression.
uint64_t getNumOperands() const
A parsed version of the target data layout string in and methods for querying it.
bool isLittleEndian() const
Layout endianness...
IntegerType * getIntPtrType(LLVMContext &C, unsigned AddressSpace=0) const
Returns an integer type with size at least as big as that of a pointer in the given address space.
Align getABITypeAlign(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
unsigned getPointerTypeSizeInBits(Type *) const
Layout pointer size, in bits, based on the type.
Align getPrefTypeAlign(Type *Ty) const
Returns the preferred stack/global alignment for the specified type.
void reserve(size_type NumEntries)
Grow the densemap so that it can contain at least NumEntries items before resizing again.
Implements a dense probed hash-table based set.
const char * getSymbol() const
unsigned getTargetFlags() const
FoldingSetNodeID - This class is used to gather all the unique data bits of a node.
MachineBasicBlock * MBB
MBB - The current block.
Data structure describing the variable locations in a function.
bool hasOptSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
AttributeList getAttributes() const
Return the attribute list for this Function.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
int64_t getOffset() const
unsigned getAddressSpace() const
unsigned getTargetFlags() const
const GlobalValue * getGlobal() const
bool isThreadLocal() const
If the value is "Thread Local", its value isn't shared by the threads.
unsigned getAddressSpace() const
Module * getParent()
Get the module that this global value is contained inside of...
PointerType * getType() const
Global values are always pointers.
This class is used to form a handle around another node that is persistent and is updated across invo...
static bool compare(const APInt &LHS, const APInt &RHS, ICmpInst::Predicate Pred)
Return result of LHS Pred RHS comparison.
constexpr bool isValid() const
This is an important class for using LLVM in a threaded context.
This SDNode is used for LIFETIME_START/LIFETIME_END values, which indicate the offet and size that ar...
This class is used to represent ISD::LOAD nodes.
static LocationSize precise(uint64_t Value)
TypeSize getValue() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
static MVT getIntegerVT(unsigned BitWidth)
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Abstract base class for all machine specific constantpool value subclasses.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
void setObjectAlignment(int ObjectIdx, Align Alignment)
setObjectAlignment - Change the alignment of the specified stack object.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
A description of a memory reference used in the backend.
LocationSize getSize() const
Return the size in bytes of the memory reference.
bool isNonTemporal() const
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
const MachinePointerInfo & getPointerInfo() const
Flags getFlags() const
Return the raw flags of the source value,.
bool isDereferenceable() const
An SDNode that represents everything that will be needed to construct a MachineInstr.
This class is used to represent an MGATHER node.
This class is used to represent an MLOAD node.
This class is used to represent an MSCATTER node.
This class is used to represent an MSTORE node.
This SDNode is used for target intrinsics that touch memory and need an associated MachineMemOperand.
MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT memvt, MachineMemOperand *MMO)
MachineMemOperand * MMO
Memory reference information.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
const MachinePointerInfo & getPointerInfo() const
unsigned getRawSubclassData() const
Return the SubclassData value, without HasDebugValue.
EVT getMemoryVT() const
Return the type of the in-memory value.
Representation for a specific memory location.
A Module instance is used to store all the information related to an LLVM module.
Function * getFunction(StringRef Name) const
Look up the specified function in the module symbol table.
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Pass interface - Implemented by all 'passes'.
static PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space.
static PointerType * getUnqual(Type *ElementType)
This constructs a pointer to an object of the specified type in the default address space (address sp...
unsigned getAddressSpace() const
Return the address space of the Pointer type.
bool isNull() const
Test if the pointer held in the union is null, regardless of which type it is.
Analysis providing profile information.
void Deallocate(SubClass *E)
Deallocate - Release storage for the pointed-to object.
Keeps track of dbg_value information through SDISel.
BumpPtrAllocator & getAlloc()
void add(SDDbgValue *V, bool isParameter)
void erase(const SDNode *Node)
Invalidate all DbgValues attached to the node and remove it from the Node-to-DbgValues map.
ArrayRef< SDDbgValue * > getSDDbgValues(const SDNode *Node) const
Holds the information from a dbg_label node through SDISel.
Holds the information for a single machine location through SDISel; either an SDNode,...
static SDDbgOperand fromNode(SDNode *Node, unsigned ResNo)
static SDDbgOperand fromFrameIdx(unsigned FrameIdx)
static SDDbgOperand fromVReg(unsigned VReg)
static SDDbgOperand fromConst(const Value *Const)
@ SDNODE
Value is the result of an expression.
Holds the information from a dbg_value node through SDISel.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
const DebugLoc & getDebugLoc() const
unsigned getIROrder() const
This class provides iterator support for SDUse operands that use a specific SDNode.
Represents one node in the SelectionDAG.
ArrayRef< SDUse > ops() const
const APInt & getAsAPIntVal() const
Helper method returns the APInt value of a ConstantSDNode.
void dumprFull(const SelectionDAG *G=nullptr) const
printrFull to dbgs().
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool isOnlyUserOf(const SDNode *N) const
Return true if this node is the only use of N.
iterator_range< value_op_iterator > op_values() const
unsigned getIROrder() const
Return the node ordering.
static constexpr size_t getMaxNumOperands()
Return the maximum number of operands that a SDNode can hold.
MemSDNodeBitfields MemSDNodeBits
void Profile(FoldingSetNodeID &ID) const
Gather unique data for the node.
bool getHasDebugValue() const
SDNodeFlags getFlags() const
void setNodeId(int Id)
Set unique node id.
void intersectFlagsWith(const SDNodeFlags Flags)
Clear any flags in this node that aren't also set in Flags.
static bool hasPredecessorHelper(const SDNode *N, SmallPtrSetImpl< const SDNode * > &Visited, SmallVectorImpl< const SDNode * > &Worklist, unsigned int MaxSteps=0, bool TopologicalPrune=false)
Returns true if N is a predecessor of any node in Worklist.
uint64_t getAsZExtVal() const
Helper method returns the zero-extended integer value of a ConstantSDNode.
bool use_empty() const
Return true if there are no uses of this node.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
unsigned getNumOperands() const
Return the number of values used by this operation.
const SDValue & getOperand(unsigned Num) const
static bool areOnlyUsersOf(ArrayRef< const SDNode * > Nodes, const SDNode *N)
Return true if all the users of N are contained in Nodes.
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
bool isOperandOf(const SDNode *N) const
Return true if this node is an operand of N.
const APInt & getConstantOperandAPInt(unsigned Num) const
Helper method returns the APInt of a ConstantSDNode operand.
bool hasPredecessor(const SDNode *N) const
Return true if N is a predecessor of this node.
bool hasAnyUseOfValue(unsigned Value) const
Return true if there are any use of the indicated value.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
bool isUndef() const
Return true if the type of the node type undefined.
bool hasNUsesOfValue(unsigned NUses, unsigned Value) const
Return true if there are exactly NUSES uses of the indicated value.
op_iterator op_end() const
op_iterator op_begin() const
static use_iterator use_end()
void DropOperands()
Release the operands and set this node to have zero operands.
Represents a use of a SDNode.
SDNode * getNode() const
Convenience function for get().getNode().
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
bool isOperandOf(const SDNode *N) const
Return true if this node is an operand of N.
bool reachesChainWithoutSideEffects(SDValue Dest, unsigned Depth=2) const
Return true if this operand (which must be a chain) reaches the specified operand without crossing an...
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
TypeSize getValueSizeInBits() const
Returns the size of the value in bits.
const SDValue & getOperand(unsigned i) const
bool use_empty() const
Return true if there are no nodes using value ResNo of Node.
const APInt & getConstantOperandAPInt(unsigned i) const
uint64_t getScalarValueSizeInBits() const
unsigned getResNo() const
get the index which selects a specific result in the SDNode
uint64_t getConstantOperandVal(unsigned i) const
unsigned getOpcode() const
virtual SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo) const
Emit target-specific code that performs a memset.
virtual SDValue EmitTargetCodeForMemmove(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const
Emit target-specific code that performs a memmove.
virtual SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const
Emit target-specific code that performs a memcpy.
SDNodeFlags getFlags() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Align getReducedAlign(EVT VT, bool UseABI)
In most cases this function returns the ABI alignment for a given type, except for illegal vector typ...
SDValue getVPZeroExtendInReg(SDValue Op, SDValue Mask, SDValue EVL, const SDLoc &DL, EVT VT)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.
SDValue getShiftAmountOperand(EVT LHSTy, SDValue Op)
Return the specified value casted to the target's desired shift amount type.
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getExtLoadVP(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, bool IsExpanding=false)
SDValue getSplatSourceVector(SDValue V, int &SplatIndex)
If V is a splatted value, return the source vector and its splat index.
SDValue getLabelNode(unsigned Opcode, const SDLoc &dl, SDValue Root, MCSymbol *Label)
OverflowKind computeOverflowForUnsignedSub(SDValue N0, SDValue N1) const
Determine if the result of the unsigned sub of 2 nodes can overflow.
unsigned ComputeMaxSignificantBits(SDValue Op, unsigned Depth=0) const
Get the upper bound on bit size for this Value Op as a signed integer.
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
SDValue getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
SDValue getMaskedGather(SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType, ISD::LoadExtType ExtTy)
bool isKnownNeverSNaN(SDValue Op, unsigned Depth=0) const
SDValue getAddrSpaceCast(const SDLoc &dl, EVT VT, SDValue Ptr, unsigned SrcAS, unsigned DestAS)
Return an AddrSpaceCastSDNode.
SDValue getStackArgumentTokenFactor(SDValue Chain)
Compute a TokenFactor to force all the incoming stack arguments to be loaded from the stack.
const TargetSubtargetInfo & getSubtarget() const
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
void updateDivergence(SDNode *N)
SDValue getSplatValue(SDValue V, bool LegalTypes=false)
If V is a splat vector, return its scalar source operand by extracting that element from the source v...
SDValue FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, const SDLoc &dl)
Constant fold a setcc to true or false.
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
void ExtractVectorElements(SDValue Op, SmallVectorImpl< SDValue > &Args, unsigned Start=0, unsigned Count=0, EVT EltVT=EVT())
Append the extracted elements from Start to Count out of the vector Op in Args.
SDValue getNeutralElement(unsigned Opcode, const SDLoc &DL, EVT VT, SDNodeFlags Flags)
Get the (commutative) neutral element for the given opcode, if it exists.
SDValue getAtomicMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Value, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo)
SDValue getVScale(const SDLoc &DL, EVT VT, APInt MulImm, bool ConstantFold=true)
Return a node that represents the runtime scaling 'MulImm * RuntimeVL'.
SDValue getPseudoProbeNode(const SDLoc &Dl, SDValue Chain, uint64_t Guid, uint64_t Index, uint32_t Attr)
Creates a PseudoProbeSDNode with function GUID Guid and the index of the block Index it is probing,...
SDValue getFreeze(SDValue V)
Return a freeze using the SDLoc of the value operand.
SDNode * SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT)
These are used for target selectors to mutate the specified node to have the specified return type,...
SelectionDAG(const TargetMachine &TM, CodeGenOptLevel)
SDValue getBitcastedSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potentia...
SDValue getConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offs=0, bool isT=false, unsigned TargetFlags=0)
SDValue getStridedLoadVP(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &DL, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false)
SDNode * isConstantIntBuildVectorOrConstantInt(SDValue N) const
Test whether the given value is a constant int or similar node.
SDValue getAtomicCmpSwap(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDVTList VTs, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachineMemOperand *MMO)
Gets a node for an atomic cmpxchg op.
SDValue makeEquivalentMemoryOrdering(SDValue OldChain, SDValue NewMemOpChain)
If an existing load has uses of its chain, create a token factor node with that chain and the new mem...
SDDbgValue * getVRegDbgValue(DIVariable *Var, DIExpression *Expr, unsigned VReg, bool IsIndirect, const DebugLoc &DL, unsigned O)
Creates a VReg SDDbgValue node.
void ReplaceAllUsesOfValuesWith(const SDValue *From, const SDValue *To, unsigned Num)
Like ReplaceAllUsesOfValueWith, but for multiple values at once.
SDValue getJumpTableDebugInfo(int JTI, SDValue Chain, const SDLoc &DL)
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SDValue getSymbolFunctionGlobalAddress(SDValue Op, Function **TargetFunction=nullptr)
Return a GlobalAddress of the function from the current module with name matching the given ExternalS...
SDValue UnrollVectorOp(SDNode *N, unsigned ResNE=0)
Utility function used by legalize and lowering to "unroll" a vector operation by splitting out the sc...
SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
OverflowKind
Used to represent the possible overflow behavior of an operation.
bool haveNoCommonBitsSet(SDValue A, SDValue B) const
Return true if A and B have no common bits set.
bool cannotBeOrderedNegativeFP(SDValue Op) const
Test whether the given float value is known to be positive.
bool calculateDivergence(SDNode *N)
SDValue getElementCount(const SDLoc &DL, EVT VT, ElementCount EC, bool ConstantFold=true)
SDValue getGetFPEnv(SDValue Chain, const SDLoc &dl, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO)
SDValue getAssertAlign(const SDLoc &DL, SDValue V, Align A)
Return an AssertAlignSDNode.
SDNode * mutateStrictFPToFP(SDNode *Node)
Mutate the specified strict FP node to its non-strict equivalent, unlinking the node from its chain a...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getBitcastedZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potentia...
SDValue getStepVector(const SDLoc &DL, EVT ResVT, const APInt &StepVal)
Returns a vector of type ResVT whose elements contain the linear sequence <0, Step,...
SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO)
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands.
std::optional< uint64_t > getValidMinimumShiftAmount(SDValue V, const APInt &DemandedElts, unsigned Depth=0) const
If a SHL/SRA/SRL node V has shift amounts that are all less than the element bit-width of the shift n...
Align getEVTAlign(EVT MemoryVT) const
Compute the default alignment value for the given type.
void VerifyDAGDivergence()
bool shouldOptForSize() const
SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
SDValue getVPZExtOrTrunc(const SDLoc &DL, EVT VT, SDValue Op, SDValue Mask, SDValue EVL)
Convert a vector-predicated Op, which must be an integer vector, to the vector-type VT,...
const TargetLowering & getTargetLoweringInfo() const
bool isEqualTo(SDValue A, SDValue B) const
Test whether two SDValues are known to compare equal.
static constexpr unsigned MaxRecursionDepth
SDValue getStridedStoreVP(SDValue Chain, const SDLoc &DL, SDValue Val, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
SDValue expandVACopy(SDNode *Node)
Expand the specified ISD::VACOPY node as the Legalize pass would.
SDValue getIndexedMaskedLoad(SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
APInt computeVectorKnownZeroElements(SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const
For each demanded element of a vector, see if it is known to be zero.
void AddDbgValue(SDDbgValue *DB, bool isParameter)
Add a dbg_value SDNode.
bool NewNodesMustHaveLegalTypes
When true, additional steps are taken to ensure that getConstant() and similar functions return DAG n...
std::pair< EVT, EVT > GetSplitDestVTs(const EVT &VT) const
Compute the VTs needed for the low/hi parts of a type which is split (or expanded) into two not neces...
void salvageDebugInfo(SDNode &N)
To be invoked on an SDNode that is slated to be erased.
SDNode * MorphNodeTo(SDNode *N, unsigned Opc, SDVTList VTs, ArrayRef< SDValue > Ops)
This mutates the specified node to have the specified return type, opcode, and operands.
std::pair< SDValue, SDValue > UnrollVectorOverflowOp(SDNode *N, unsigned ResNE=0)
Like UnrollVectorOp(), but for the [US](ADD|SUB|MUL)O family of opcodes.
allnodes_const_iterator allnodes_begin() const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
SDValue getGatherVP(SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType)
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
SDValue getBitcastedAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potentia...
bool isSplatValue(SDValue V, const APInt &DemandedElts, APInt &UndefElts, unsigned Depth=0) const
Test whether V has a splatted value for all the demanded elements.
void DeleteNode(SDNode *N)
Remove the specified node from the system.
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
SDDbgValue * getDbgValueList(DIVariable *Var, DIExpression *Expr, ArrayRef< SDDbgOperand > Locs, ArrayRef< SDNode * > Dependencies, bool IsIndirect, const DebugLoc &DL, unsigned O, bool IsVariadic)
Creates a SDDbgValue node from a list of locations.
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS, SDNodeFlags Flags=SDNodeFlags())
Helper function to make it easier to build Select's if you just have operands and don't want to check...
SDValue getNegative(SDValue Val, const SDLoc &DL, EVT VT)
Create negative operation as (SUB 0, Val).
void setNodeMemRefs(MachineSDNode *N, ArrayRef< MachineMemOperand * > NewMemRefs)
Mutate the specified machine node's memory references to the provided list.
SDValue simplifySelect(SDValue Cond, SDValue TVal, SDValue FVal)
Try to simplify a select/vselect into 1 of its operands or a constant.
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.
const DataLayout & getDataLayout() const
SDNode * isConstantFPBuildVectorOrConstantFP(SDValue N) const
Test whether the given value is a constant FP or similar node.
SDValue expandVAArg(SDNode *Node)
Expand the specified ISD::VAARG node as the Legalize pass would.
SDValue getTokenFactor(const SDLoc &DL, SmallVectorImpl< SDValue > &Vals)
Creates a new TokenFactor containing Vals.
bool doesNodeExist(unsigned Opcode, SDVTList VTList, ArrayRef< SDValue > Ops)
Check if a node exists without modifying its flags.
bool areNonVolatileConsecutiveLoads(LoadSDNode *LD, LoadSDNode *Base, unsigned Bytes, int Dist) const
Return true if loads are next to each other and can be merged.
SDValue getMaskedHistogram(SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType)
SDDbgLabel * getDbgLabel(DILabel *Label, const DebugLoc &DL, unsigned O)
Creates a SDDbgLabel node.
SDValue getStoreVP(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
OverflowKind computeOverflowForUnsignedMul(SDValue N0, SDValue N1) const
Determine if the result of the unsigned mul of 2 nodes can overflow.
void copyExtraInfo(SDNode *From, SDNode *To)
Copy extra info associated with one node to another.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getMemBasePlusOffset(SDValue Base, TypeSize Offset, const SDLoc &DL, const SDNodeFlags Flags=SDNodeFlags())
Returns sum of the base pointer and offset.
SDValue getGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, bool isTargetGA=false, unsigned TargetFlags=0)
SDValue getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getVAArg(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue SV, unsigned Align)
VAArg produces a result and token chain, and takes a pointer and a source value as input.
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getAllOnesConstant(const SDLoc &DL, EVT VT, bool IsTarget=false, bool IsOpaque=false)
SDValue getMDNode(const MDNode *MD)
Return an MDNodeSDNode which holds an MDNode.
void clear()
Clear state and free memory necessary to make this SelectionDAG ready to process a new block.
void ReplaceAllUsesWith(SDValue From, SDValue To)
Modify anything using 'From' to use 'To' instead.
SDValue getCommutedVectorShuffle(const ShuffleVectorSDNode &SV)
Returns an ISD::VECTOR_SHUFFLE node semantically equivalent to the shuffle node in input but with swa...
std::pair< SDValue, SDValue > SplitVector(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
Split the vector with EXTRACT_SUBVECTOR using the provided VTs and return the low/high part.
SDValue makeStateFunctionCall(unsigned LibFunc, SDValue Ptr, SDValue InChain, const SDLoc &DLoc)
Helper used to make a call to a library function that has one argument of pointer type.
bool isGuaranteedNotToBeUndefOrPoison(SDValue Op, bool PoisonOnly=false, unsigned Depth=0) const
Return true if this function can prove that Op is never poison and, if PoisonOnly is false,...
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getIndexedLoadVP(SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
SDValue getSrcValue(const Value *v)
Construct a node to track a Value* through the backend.
SDValue getSplatVector(EVT VT, const SDLoc &DL, SDValue Op)
SDValue getAtomicMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
OverflowKind computeOverflowForSignedMul(SDValue N0, SDValue N1) const
Determine if the result of the signed mul of 2 nodes can overflow.
MaybeAlign InferPtrAlign(SDValue Ptr) const
Infer alignment of a load / store address.
bool MaskedValueIsAllOnes(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if '(Op & Mask) == Mask'.
bool SignBitIsZero(SDValue Op, unsigned Depth=0) const
Return true if the sign bit of Op is known to be zero.
SDValue getRegister(unsigned Reg, EVT VT)
void init(MachineFunction &NewMF, OptimizationRemarkEmitter &NewORE, Pass *PassPtr, const TargetLibraryInfo *LibraryInfo, UniformityInfo *UA, ProfileSummaryInfo *PSIin, BlockFrequencyInfo *BFIin, FunctionVarLocs const *FnVarLocs)
Prepare this SelectionDAG to process code in the given MachineFunction.
void RemoveDeadNodes()
This method deletes all unreachable nodes in the SelectionDAG.
void RemoveDeadNode(SDNode *N)
Remove the specified node from the system.
void AddDbgLabel(SDDbgLabel *DB)
Add a dbg_label SDNode.
bool isConstantValueOfAnyType(SDValue N) const
SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
SDValue getBasicBlock(MachineBasicBlock *MBB)
SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or trunca...
bool isKnownToBeAPowerOfTwo(SDValue Val, unsigned Depth=0) const
Test if the given value is known to have exactly one bit set.
SDValue getEHLabel(const SDLoc &dl, SDValue Root, MCSymbol *Label)
SDValue getIndexedStoreVP(SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
bool isKnownNeverZero(SDValue Op, unsigned Depth=0) const
Test whether the given SDValue is known to contain non-zero value(s).
SDValue getIndexedStore(SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
SDValue FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops, SDNodeFlags Flags=SDNodeFlags())
SDValue getSetFPEnv(SDValue Chain, const SDLoc &dl, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO)
SDValue getBoolExtOrTrunc(SDValue Op, const SDLoc &SL, EVT VT, EVT OpVT)
Convert Op, which must be of integer type, to the integer type VT, by using an extension appropriate ...
SDValue getMaskedStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Base, SDValue Offset, SDValue Mask, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
static const fltSemantics & EVTToAPFloatSemantics(EVT VT)
Returns an APFloat semantics tag appropriate for the given type.
SDValue getExternalSymbol(const char *Sym, EVT VT)
const TargetMachine & getTarget() const
std::pair< SDValue, SDValue > getStrictFPExtendOrRound(SDValue Op, SDValue Chain, const SDLoc &DL, EVT VT)
Convert Op, which must be a STRICT operation of float type, to the float type VT, by either extending...
std::pair< SDValue, SDValue > SplitEVL(SDValue N, EVT VecVT, const SDLoc &DL)
Split the explicit vector length parameter of a VP operation.
SDValue getPtrExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either truncating it or perform...
SDValue getVPLogicalNOT(const SDLoc &DL, SDValue Val, SDValue Mask, SDValue EVL, EVT VT)
Create a vector-predicated logical NOT operation as (VP_XOR Val, BooleanOne, Mask,...
SDValue getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncat...
iterator_range< allnodes_iterator > allnodes()
SDValue getBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, bool isTarget=false, unsigned TargetFlags=0)
SDValue WidenVector(const SDValue &N, const SDLoc &DL)
Widen the vector up to the next power of two using INSERT_SUBVECTOR.
bool isKnownNeverZeroFloat(SDValue Op) const
Test whether the given floating point SDValue is known to never be positive or negative zero.
SDValue getLoadVP(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, Align Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, const MDNode *Ranges=nullptr, bool IsExpanding=false)
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDDbgValue * getConstantDbgValue(DIVariable *Var, DIExpression *Expr, const Value *C, const DebugLoc &DL, unsigned O)
Creates a constant SDDbgValue node.
SDValue getScatterVP(SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType)
SDValue getValueType(EVT)
ArrayRef< SDDbgValue * > GetDbgValues(const SDNode *SD) const
Get the debug values which reference the given SDNode.
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
OverflowKind computeOverflowForSignedAdd(SDValue N0, SDValue N1) const
Determine if the result of the signed addition of 2 nodes can overflow.
SDValue getFPExtendOrRound(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of float type, to the float type VT, by either extending or rounding (by tr...
unsigned AssignTopologicalOrder()
Topological-sort the AllNodes list and a assign a unique node id for each node in the DAG based on th...
ilist< SDNode >::size_type allnodes_size() const
SDValue getAtomicMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
bool isKnownNeverNaN(SDValue Op, bool SNaN=false, unsigned Depth=0) const
Test whether the given SDValue (or all elements of it, if it is a vector) is known to never be NaN.
SDValue getIndexedMaskedStore(SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
SDValue getTruncStoreVP(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, bool IsCompressing=false)
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
Return the number of times the sign bit of the register is replicated into the other bits.
bool MaskedVectorIsZero(SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const
Return true if 'Op' is known to be zero in DemandedElts.
SDValue getBoolConstant(bool V, const SDLoc &DL, EVT VT, EVT OpVT)
Create a true or false constant of type VT using the target's BooleanContent for type OpVT.
SDDbgValue * getFrameIndexDbgValue(DIVariable *Var, DIExpression *Expr, unsigned FI, bool IsIndirect, const DebugLoc &DL, unsigned O)
Creates a FrameIndex SDDbgValue node.
SDValue getExtStridedLoadVP(ISD::LoadExtType ExtType, const SDLoc &DL, EVT VT, SDValue Chain, SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false)
SDValue getJumpTable(int JTI, EVT VT, bool isTarget=false, unsigned TargetFlags=0)
bool isBaseWithConstantOffset(SDValue Op) const
Return true if the specified operand is an ISD::ADD with a ConstantSDNode on the right-hand side,...
SDValue getVPPtrExtOrTrunc(const SDLoc &DL, EVT VT, SDValue Op, SDValue Mask, SDValue EVL)
Convert a vector-predicated Op, which must be of integer type, to the vector-type integer type VT,...
SDValue getVectorIdxConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
MachineFunction & getMachineFunction() const
SDValue getPtrExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to extend the Op as a pointer value assuming it was the smaller SrcTy ...
bool canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts, bool PoisonOnly=false, bool ConsiderFlags=true, unsigned Depth=0) const
Return true if Op can create undef or poison from non-undef & non-poison operands.
OverflowKind computeOverflowForUnsignedAdd(SDValue N0, SDValue N1) const
Determine if the result of the unsigned addition of 2 nodes can overflow.
std::optional< uint64_t > getValidMaximumShiftAmount(SDValue V, const APInt &DemandedElts, unsigned Depth=0) const
If a SHL/SRA/SRL node V has shift amounts that are all less than the element bit-width of the shift n...
SDValue getSplatBuildVector(EVT VT, const SDLoc &DL, SDValue Op)
Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all elements.
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
SDValue getTruncStridedStoreVP(SDValue Chain, const SDLoc &DL, SDValue Val, SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL, EVT SVT, MachineMemOperand *MMO, bool IsCompressing=false)
void canonicalizeCommutativeBinop(unsigned Opcode, SDValue &N1, SDValue &N2) const
Swap N1 and N2 if Opcode is a commutative binary opcode and the canonical form expects the opposite o...
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
SDValue getRegisterMask(const uint32_t *RegMask)
SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
SDValue getCondCode(ISD::CondCode Cond)
SDValue getLifetimeNode(bool IsStart, const SDLoc &dl, SDValue Chain, int FrameIndex, int64_t Size, int64_t Offset=-1)
Creates a LifetimeSDNode that starts (IsStart==true) or ends (IsStart==false) the lifetime of the por...
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
bool isKnownToBeAPowerOfTwoFP(SDValue Val, unsigned Depth=0) const
Test if the given fp value is known to be an integer power-of-2, either positive or negative.
OverflowKind computeOverflowForSignedSub(SDValue N0, SDValue N1) const
Determine if the result of the signed sub of 2 nodes can overflow.
std::optional< uint64_t > getValidShiftAmount(SDValue V, const APInt &DemandedElts, unsigned Depth=0) const
If a SHL/SRA/SRL node V has a uniform shift amount that is less than the element bit-width of the shi...
LLVMContext * getContext() const
SDValue simplifyFPBinop(unsigned Opcode, SDValue X, SDValue Y, SDNodeFlags Flags)
Try to simplify a floating-point binary operation into 1 of its operands or a constant.
const SDValue & setRoot(SDValue N)
Set the current root tag of the SelectionDAG.
SDValue getShiftAmountConstant(uint64_t Val, EVT VT, const SDLoc &DL, bool LegalTypes=true)
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, LocationSize Size=0, const AAMDNodes &AAInfo=AAMDNodes())
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getMCSymbol(MCSymbol *Sym, EVT VT)
bool isUndef(unsigned Opcode, ArrayRef< SDValue > Ops)
Return true if the result of this operation is always undefined.
SDValue CreateStackTemporary(TypeSize Bytes, Align Alignment)
Create a stack temporary based on the size in bytes and the alignment.
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
std::pair< EVT, EVT > GetDependentSplitDestVTs(const EVT &VT, const EVT &EnvVT, bool *HiIsEmpty) const
Compute the VTs needed for the low/hi parts of a type, dependent on an enveloping VT that has been sp...
SDValue foldConstantFPMath(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops)
Fold floating-point operations when all operands are constants and/or undefined.
SDNode * getNodeIfExists(unsigned Opcode, SDVTList VTList, ArrayRef< SDValue > Ops, const SDNodeFlags Flags)
Get the specified node if it's already available, or else return NULL.
std::optional< ConstantRange > getValidShiftAmountRange(SDValue V, const APInt &DemandedElts, unsigned Depth) const
If a SHL/SRA/SRL node V has shift amounts that are all less than the element bit-width of the shift n...
SDValue FoldSymbolOffset(unsigned Opcode, EVT VT, const GlobalAddressSDNode *GA, const SDNode *N2)
SDValue getIndexedLoad(SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
SDValue getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand, SDValue Subreg)
A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
SDDbgValue * getDbgValue(DIVariable *Var, DIExpression *Expr, SDNode *N, unsigned R, bool IsIndirect, const DebugLoc &DL, unsigned O)
Creates a SDDbgValue node.
SDValue getMaskedLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Base, SDValue Offset, SDValue Mask, SDValue Src0, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, ISD::LoadExtType, bool IsExpanding=false)
SDValue getSplat(EVT VT, const SDLoc &DL, SDValue Op)
Returns a node representing a splat of one value into all lanes of the provided vector type.
std::pair< SDValue, SDValue > SplitScalar(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
Split the scalar node with EXTRACT_ELEMENT using the provided VTs and return the low/high part.
SDValue matchBinOpReduction(SDNode *Extract, ISD::NodeType &BinOp, ArrayRef< ISD::NodeType > CandidateBinOps, bool AllowPartials=false)
Match a binop + shuffle pyramid that represents a horizontal reduction over the elements of a vector ...
bool isADDLike(SDValue Op, bool NoWrap=false) const
Return true if the specified operand is an ISD::OR or ISD::XOR node that can be treated as an ISD::AD...
SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, ArrayRef< int > Mask)
Return an ISD::VECTOR_SHUFFLE node.
SDValue simplifyShift(SDValue X, SDValue Y)
Try to simplify a shift into 1 of its operands or a constant.
void transferDbgValues(SDValue From, SDValue To, unsigned OffsetInBits=0, unsigned SizeInBits=0, bool InvalidateDbg=true)
Transfer debug values from one node to another, while optionally generating fragment expressions for ...
SDValue getLogicalNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a logical NOT operation as (XOR Val, BooleanOne).
SDValue getMaskedScatter(SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType, bool IsTruncating=false)
ilist< SDNode >::iterator allnodes_iterator
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
static bool isSplatMask(const int *Mask, EVT VT)
int getMaskElt(unsigned Idx) const
ArrayRef< int > getMask() const
static void commuteMask(MutableArrayRef< int > Mask)
Change values in a shuffle permute mask assuming the two vector operands have swapped position.
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
bool erase(PtrType Ptr)
Remove pointer from the set.
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void assign(size_type NumElts, ValueParamT Elt)
reference emplace_back(ArgTypes &&... Args)
void reserve(size_type N)
iterator erase(const_iterator CI)
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
This class is used to represent ISD::STORE nodes.
StringRef - Represent a constant reference to a string, i.e.
Information about stack frame layout on the target.
virtual TargetStackID::Value getStackIDForScalableVectors() const
Returns the StackID that scalable vectors should be associated with.
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Completely target-dependent object reference.
int64_t getOffset() const
unsigned getTargetFlags() const
Provides information about what library functions are available for the current target.
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const
Return true if it is beneficial to convert a load of a constant to just the constant itself.
virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
const TargetMachine & getTargetMachine() const
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
unsigned getMaxStoresPerMemcpy(bool OptSize) const
Get maximum # of store operations permitted for llvm.memcpy.
virtual bool isCommutativeBinOp(unsigned Opcode) const
Returns true if the opcode is a commutative binary operation.
virtual ISD::NodeType getExtendForAtomicOps() const
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
virtual bool shallExtractConstSplatVectorElementToStore(Type *VectorTy, unsigned ElemSizeInBits, unsigned &Index) const
Return true if the target shall perform extract vector element and store given that the vector is kno...
virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const
Return true if it's free to truncate a value of type FromTy to type ToTy.
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
Returns the type for the shift amount of a shift opcode.
virtual EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal on this target.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
BooleanContent
Enum that describes how the target represents true/false values.
@ ZeroOrOneBooleanContent
@ UndefinedBooleanContent
@ ZeroOrNegativeOneBooleanContent
unsigned getMaxStoresPerMemmove(bool OptSize) const
Get maximum # of store operations permitted for llvm.memmove.
virtual unsigned getMaxGluedStoresPerMemcpy() const
Get maximum # of store operations to be glued together.
Align getMinStackArgumentAlignment() const
Return the minimum stack alignment of an argument.
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
std::vector< ArgListEntry > ArgListTy
virtual bool hasVectorBlend() const
Return true if the target has a vector blend instruction.
unsigned getMaxStoresPerMemset(bool OptSize) const
Get maximum # of store operations permitted for llvm.memset.
MVT getFrameIndexTy(const DataLayout &DL) const
Return the type for frame index, which is determined by the alloca address space specified through th...
virtual bool isLegalStoreImmediate(int64_t Value) const
Return true if the specified immediate is legal for the value input of a store instruction.
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
static ISD::NodeType getExtendForContent(BooleanContent Content)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual void computeKnownBitsForFrameIndex(int FIOp, KnownBits &Known, const MachineFunction &MF) const
Determine which of the bits of FrameIndex FIOp are known to be 0.
virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const
This method can be implemented by targets that want to expose additional information about sign bits ...
virtual void verifyTargetSDNode(const SDNode *N) const
Check the given SDNode. Aborts if it is invalid.
virtual bool findOptimalMemOpLowering(std::vector< EVT > &MemOps, unsigned Limit, const MemOp &Op, unsigned DstAS, unsigned SrcAS, const AttributeList &FuncAttributes) const
Determines the optimal series of memory ops to replace the memset / memcpy.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
virtual bool isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const
If SNaN is false,.
virtual void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
virtual bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, UniformityInfo *UA) const
virtual bool isSDNodeAlwaysUniform(const SDNode *N) const
virtual bool isSplatValueForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &UndefElts, const SelectionDAG &DAG, unsigned Depth=0) const
Return true if vector Op has the same value across all DemandedElts, indicating any elements which ma...
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const
Return true if folding a constant offset with the given GlobalAddress is legal.
virtual const Constant * getTargetConstantFromLoad(LoadSDNode *LD) const
This method returns the constant pool value that will be loaded by LD.
virtual bool isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const
Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.
virtual bool isGuaranteedNotToBeUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, unsigned Depth) const
Return true if this function can prove that Op is never poison and, if PoisonOnly is false,...
virtual bool canCreateUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const
Return true if Op can create undef or poison from non-undef & non-poison operands.
Primary interface to the complete machine description for the target machine.
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast between SrcAS and DestAS is a noop.
const Triple & getTargetTriple() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const SelectionDAGTargetInfo * getSelectionDAGInfo() const
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetFrameLowering * getFrameLowering() const
virtual const TargetLowering * getTargetLowering() const
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, XROS, or DriverKit).
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
static constexpr TypeSize getFixed(ScalarTy ExactSize)
The instances of the Type class are immutable: once they are created, they are never changed.
bool isVectorTy() const
True if this is an instance of VectorType.
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
static Type * getVoidTy(LLVMContext &C)
static IntegerType * getInt8Ty(LLVMContext &C)
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
A Use represents the edge between a Value definition and its users.
This class is used to represent an VP_GATHER node.
This class is used to represent a VP_LOAD node.
This class is used to represent an VP_SCATTER node.
This class is used to represent a VP_STORE node.
This class is used to represent an EXPERIMENTAL_VP_STRIDED_LOAD node.
This class is used to represent an EXPERIMENTAL_VP_STRIDED_STORE node.
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
std::pair< iterator, bool > insert(const ValueT &V)
bool contains(const_arg_type_t< ValueT > V) const
Check if the set contains the given element.
constexpr ScalarTy getFixedValue() const
static constexpr bool isKnownLE(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
constexpr bool isKnownEven() const
A return value of true indicates we know at compile time that the number of elements (vscale * Min) i...
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
static constexpr bool isKnownGE(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
A raw_ostream that writes to an std::string.
std::string & str()
Returns the string's reference.
SmartMutex - A mutex with a compile time constant parameter that indicates whether this mutex should ...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
APInt mulhu(const APInt &C1, const APInt &C2)
Performs (2*N)-bit multiplication on zero-extended operands.
const APInt abdu(const APInt &A, const APInt &B)
Determine the absolute difference of two APInts considered to be unsigned.
APInt avgCeilU(const APInt &C1, const APInt &C2)
Compute the ceil of the unsigned average of C1 and C2.
APInt avgFloorU(const APInt &C1, const APInt &C2)
Compute the floor of the unsigned average of C1 and C2.
const APInt abds(const APInt &A, const APInt &B)
Determine the absolute difference of two APInts considered to be signed.
APInt mulhs(const APInt &C1, const APInt &C2)
Performs (2*N)-bit multiplication on sign-extended operands.
APInt ScaleBitMask(const APInt &A, unsigned NewBitWidth, bool MatchAllBits=false)
Splat/Merge neighboring bits to widen/narrow the bitmask represented by.
APInt avgFloorS(const APInt &C1, const APInt &C2)
Compute the floor of the signed average of C1 and C2.
APInt avgCeilS(const APInt &C1, const APInt &C2)
Compute the ceil of the signed average of C1 and C2.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ C
The default llvm calling convention, compatible with C.
CondCode getSetCCInverse(CondCode Operation, bool isIntegerLike)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, EVT Type)
Return the result of a logical AND between different comparisons of identical values: ((X op1 Y) & (X...
bool isConstantSplatVectorAllOnes(const SDNode *N, bool BuildVectorOnly=false)
Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where all of the elements are ~0 ...
bool isNON_EXTLoad(const SDNode *N)
Returns true if the specified node is a non-extending load.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
@ MDNODE_SDNODE
MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to reference metadata in the IR.
@ STRICT_FSETCC
STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used for floating-point operands only.
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
@ VECREDUCE_SEQ_FADD
Generic reduction nodes.
@ FGETSIGN
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
@ INSERT_SUBVECTOR
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1.
@ JUMP_TABLE_DEBUG_INFO
JUMP_TABLE_DEBUG_INFO - Jumptable debug info.
@ BSWAP
Byte Swap and Counting operators.
@ ATOMIC_STORE
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
@ FMAD
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.
@ ADD
Simple integer binary arithmetic operators.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
@ VECREDUCE_FMAX
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
@ FADD
Simple binary floating point operators.
@ VECREDUCE_FMAXIMUM
FMINIMUM/FMAXIMUM nodes propatate NaNs and signed zeroes using the llvm.minimum and llvm....
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
@ SIGN_EXTEND_VECTOR_INREG
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
@ FLDEXP
FLDEXP - ldexp, inspired by libm (op0 * 2**op1).
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
@ SRCVALUE
SRCVALUE - This is a node type that holds a Value* that is used to make reference to a value in the L...
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
@ SIGN_EXTEND
Conversion operators.
@ AVGCEILS
AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an integer of type i[N+2],...
@ SCALAR_TO_VECTOR
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
@ VECREDUCE_FADD
These reductions have relaxed evaluation order semantics, and have a single vector operand.
@ CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
@ TargetIndex
TargetIndex - Like a constant pool entry, but with completely target-dependent semantics.
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
@ SETCCCARRY
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
@ FNEG
Perform various unary floating-point operations inspired by libm.
@ BR_CC
BR_CC - Conditional branch.
@ SSUBO
Same for subtraction.
@ STEP_VECTOR
STEP_VECTOR(IMM) - Returns a scalable vector whose lanes are comprised of a linear sequence of unsign...
@ FCANONICALIZE
Returns platform specific canonical encoding of a floating point number.
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ ATOMIC_LOAD
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
@ UNDEF
UNDEF - An undefined node.
@ EXTRACT_ELEMENT
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
@ AssertAlign
AssertAlign - These nodes record if a register contains a value that has a known alignment and the tr...
@ BasicBlock
Various leaf nodes.
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
@ TargetGlobalAddress
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
@ SHL
Shift and rotation operations.
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
@ EXTRACT_SUBVECTOR
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimumNumber or maximumNumber on two values,...
@ EntryToken
EntryToken - This is the marker used to indicate the start of a region.
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
@ VSCALE
VSCALE(IMM) - Returns the runtime scaling factor used to calculate the number of elements within a sc...
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
@ SSHLSAT
RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.
@ SMULO
Same for multiplication.
@ ANY_EXTEND_VECTOR_INREG
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
@ LIFETIME_START
This corresponds to the llvm.lifetime.
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ VSELECT
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
@ UADDO_CARRY
Carry-using nodes for multiple precision addition and subtraction.
@ HANDLENODE
HANDLENODE node - Used as a handle for various purposes.
@ BF16_TO_FP
BF16_TO_FP, FP_TO_BF16 - These operators are used to perform promotions and truncation for bfloat16.
@ STRICT_FP_ROUND
X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision ...
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ TargetConstant
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification,...
@ STRICT_FP_EXTEND
X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
@ GET_FPENV_MEM
Gets the current floating-point environment.
@ PSEUDO_PROBE
Pseudo probe for AutoFDO, as a place holder in a basic block to improve the sample counts quality.
@ AVGFLOORS
AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of type i[N+1],...
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
@ SPLAT_VECTOR_PARTS
SPLAT_VECTOR_PARTS(SCALAR1, SCALAR2, ...) - Returns a vector with the scalar values joined together a...
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ VECTOR_SPLICE
VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
@ FFREXP
FFREXP - frexp, extract fractional and exponent component of a floating-point value.
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
@ ZERO_EXTEND_VECTOR_INREG
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
@ ADDRSPACECAST
ADDRSPACECAST - This operator converts between pointers of different address spaces.
@ EXPERIMENTAL_VECTOR_HISTOGRAM
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
@ SET_FPENV_MEM
Sets the current floating point environment.
@ SADDO_CARRY
Carry-using overflow-aware nodes for multiple precision addition and subtraction.
@ INTRINSIC_W_CHAIN
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
unsigned getVPForBaseOpcode(unsigned Opcode)
Translate this non-VP Opcode to its corresponding VP Opcode.
bool isBuildVectorOfConstantSDNodes(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR node of all ConstantSDNode or undef.
NodeType getExtForLoadExtType(bool IsFP, LoadExtType)
bool matchUnaryPredicate(SDValue Op, std::function< bool(ConstantSDNode *)> Match, bool AllowUndefs=false)
Hook for matching ConstantSDNode predicate.
bool isZEXTLoad(const SDNode *N)
Returns true if the specified node is a ZEXTLOAD.
bool matchUnaryFpPredicate(SDValue Op, std::function< bool(ConstantFPSDNode *)> Match, bool AllowUndefs=false)
Hook for matching ConstantFPSDNode predicate.
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
bool isConstantSplatVectorAllZeros(const SDNode *N, bool BuildVectorOnly=false)
Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where all of the elements are 0 o...
bool isVectorShrinkable(const SDNode *N, unsigned NewEltSize, bool Signed)
Returns true if the specified node is a vector where all elements can be truncated to the specified e...
bool matchUnaryPredicateImpl(SDValue Op, std::function< bool(ConstNodeType *)> Match, bool AllowUndefs=false)
Attempt to match a unary predicate against a scalar/splat constant or every element of a constant BUI...
bool isVPBinaryOp(unsigned Opcode)
Whether this is a vector-predicated binary operation opcode.
CondCode getSetCCInverse(CondCode Operation, EVT Type)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
std::optional< unsigned > getBaseOpcodeForVP(unsigned Opcode, bool hasFPExcept)
Translate this VP Opcode to its corresponding non-VP Opcode.
bool isTrueWhenEqual(CondCode Cond)
Return true if the specified condition returns true if the two operands to the condition are equal.
std::optional< unsigned > getVPMaskIdx(unsigned Opcode)
The operand position of the vector mask.
unsigned getUnorderedFlavor(CondCode Cond)
This function returns 0 if the condition is always false if an operand is a NaN, 1 if the condition i...
std::optional< unsigned > getVPExplicitVectorLengthIdx(unsigned Opcode)
The operand position of the explicit vector length parameter.
bool isEXTLoad(const SDNode *N)
Returns true if the specified node is a EXTLOAD.
bool allOperandsUndef(const SDNode *N)
Return true if the node has at least one operand and all operands of the specified node are ISD::UNDE...
bool isFreezeUndef(const SDNode *N)
Return true if the specified node is FREEZE(UNDEF).
CondCode getSetCCSwappedOperands(CondCode Operation)
Return the operation corresponding to (Y op X) when given the operation for (X op Y).
MemIndexType
MemIndexType enum - This enum defines how to interpret MGATHER/SCATTER's index parameter when calcula...
bool isBuildVectorAllZeros(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR where all of the elements are 0 or undef.
bool isConstantSplatVector(const SDNode *N, APInt &SplatValue)
Node predicates.
bool matchBinaryPredicate(SDValue LHS, SDValue RHS, std::function< bool(ConstantSDNode *, ConstantSDNode *)> Match, bool AllowUndefs=false, bool AllowTypeMismatch=false)
Attempt to match a binary predicate against a pair of scalar/splat constants or every element of a pa...
bool isVPReduction(unsigned Opcode)
Whether this is a vector-predicated reduction opcode.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
bool isBuildVectorOfConstantFPSDNodes(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR node of all ConstantFPSDNode or undef.
bool isSEXTLoad(const SDNode *N)
Returns true if the specified node is a SEXTLOAD.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
bool isBuildVectorAllOnes(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR where all of the elements are ~0 or undef.
NodeType getVecReduceBaseOpcode(unsigned VecReduceOpcode)
Get underlying scalar opcode for VECREDUCE opcode.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
bool isVPOpcode(unsigned Opcode)
Whether this is a vector-predicated Opcode.
CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, EVT Type)
Return the result of a logical OR between different comparisons of identical values: ((X op1 Y) | (X ...
BinaryOp_match< LHS, RHS, Instruction::And > m_And(const LHS &L, const RHS &R)
deferredval_ty< Value > m_Deferred(Value *const &V)
Like m_Specific(), but works if the specific value to match is determined as part of the same match()...
BinaryOp_match< cst_pred_ty< is_zero_int >, ValTy, Instruction::Sub > m_Neg(const ValTy &V)
Matches a 'Neg' as 'sub 0, V'.
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMSET_ELEMENT_UNORDERED_ATOMIC - Return MEMSET_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Libcall getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given e...
bool sd_match(SDNode *N, const SelectionDAG *DAG, Pattern &&P)
initializer< Ty > init(const Ty &Val)
@ DW_OP_LLVM_arg
Only used in LLVM metadata.
std::lock_guard< SmartMutex< mt_only > > SmartScopedLock
This is an optimization pass for GlobalISel generic memory operations.
unsigned Log2_32_Ceil(uint32_t Value)
Return the ceil log base 2 of the specified value, 32 if the value is zero.
bool operator<(int64_t V1, const APSInt &V2)
ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred)
getICmpCondCode - Return the ISD condition code corresponding to the given LLVM IR integer condition ...
SDValue peekThroughExtractSubvectors(SDValue V)
Return the non-extracted vector source operand of V if it exists.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
bool isUIntN(unsigned N, uint64_t x)
Checks if an unsigned integer fits into the given (dynamic) bit width.
bool isAllOnesOrAllOnesSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant -1 integer or a splatted vector of a constant -1 integer (with...
SDValue getBitwiseNotOperand(SDValue V, SDValue Mask, bool AllowUndefs)
If V is a bitwise not, returns the inverted operand.
SDValue peekThroughBitcasts(SDValue V)
Return the non-bitcasted source operand of V if it exists.
auto enumerate(FirstRange &&First, RestRanges &&...Rest)
Given two or more input ranges, returns a new range whose values are are tuples (A,...
int countr_one(T Value)
Count the number of ones from the least significant bit to the first zero bit.
bool isIntOrFPConstant(SDValue V)
Return true if V is either a integer or FP constant.
bool getConstantDataArrayInfo(const Value *V, ConstantDataArraySlice &Slice, unsigned ElementSize, uint64_t Offset=0)
Returns true if the value V is a pointer into a ConstantDataArray.
int bit_width(T Value)
Returns the number of bits needed to represent Value if Value is nonzero.
LLVM_READONLY APFloat maximum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2019 maximum semantics.
void append_range(Container &C, Range &&R)
Wrapper function to append range R to container C.
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
MaybeAlign getAlign(const Function &F, unsigned Index)
bool isNullOrNullSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant 0 integer or a splatted vector of a constant 0 integer (with n...
bool isMinSignedConstant(SDValue V)
Returns true if V is a constant min signed integer value.
ConstantFPSDNode * isConstOrConstSplatFP(SDValue N, bool AllowUndefs=false)
Returns the SDNode if it is a constant splat BuildVector or constant float.
ConstantRange getConstantRangeFromMetadata(const MDNode &RangeMD)
Parse out a conservative ConstantRange from !range metadata.
APFloat frexp(const APFloat &X, int &Exp, APFloat::roundingMode RM)
Equivalent of C standard library function.
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
bool getShuffleDemandedElts(int SrcWidth, ArrayRef< int > Mask, const APInt &DemandedElts, APInt &DemandedLHS, APInt &DemandedRHS, bool AllowUndefElts=false)
Transform a shuffle mask's output demanded element mask into demanded element masks for the 2 operand...
LLVM_READONLY APFloat maxnum(const APFloat &A, const APFloat &B)
Implements IEEE-754 2019 maximumNumber semantics.
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
bool isBitwiseNot(SDValue V, bool AllowUndefs=false)
Returns true if V is a bitwise not operation.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
void checkForCycles(const SelectionDAG *DAG, bool force=false)
void sort(IteratorTy Start, IteratorTy End)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
SDValue peekThroughTruncates(SDValue V)
Return the non-truncated source operand of V if it exists.
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
ConstantRange getVScaleRange(const Function *F, unsigned BitWidth)
Determine the possible constant range of vscale with the given bit width, based on the vscale_range f...
SDValue peekThroughOneUseBitcasts(SDValue V)
Return the non-bitcasted and one-use source operand of V if it exists.
CodeGenOptLevel
Code generation optimization level.
bool isOneOrOneSplat(SDValue V, bool AllowUndefs=false)
Return true if the value is a constant 1 integer or a splatted vector of a constant 1 integer (with n...
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
LLVM_READONLY APFloat minnum(const APFloat &A, const APFloat &B)
Implements IEEE-754 2019 minimumNumber semantics.
@ Mul
Product of integers.
bool isNullConstantOrUndef(SDValue V)
Returns true if V is a constant integer zero or an UNDEF node.
void computeKnownBits(const Value *V, KnownBits &Known, const DataLayout &DL, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Determine which bits of V are known to be either zero or one and return them in the KnownZero/KnownOn...
DWARFExpression::Operation Op
ConstantSDNode * isConstOrConstSplat(SDValue N, bool AllowUndefs=false, bool AllowTruncation=false)
Returns the SDNode if it is a constant splat BuildVector or constant int.
OutputIt copy(R &&Range, OutputIt Out)
constexpr unsigned BitWidth
bool isOneConstant(SDValue V)
Returns true if V is a constant integer one.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
bool isNullFPConstant(SDValue V)
Returns true if V is an FP constant with a value of positive zero.
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
unsigned Log2(Align A)
Returns the log2 of the alignment.
void computeKnownBitsFromRangeMetadata(const MDNode &Ranges, KnownBits &Known)
Compute known bits from the range metadata.
LLVM_READONLY APFloat minimum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2019 minimum semantics.
bool isNeutralConstant(unsigned Opc, SDNodeFlags Flags, SDValue V, unsigned OperandNo)
Returns true if V is a neutral element of Opc with Flags.
bool isAllOnesConstant(SDValue V)
Returns true if V is an integer constant with all bits set.
constexpr uint64_t NextPowerOf2(uint64_t A)
Returns the next power of two (in 64-bits) that is strictly greater than A.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
MDNode * TBAAStruct
The tag for type-based alias analysis (tbaa struct).
MDNode * TBAA
The tag for type-based alias analysis.
static const fltSemantics & IEEEsingle() LLVM_READNONE
cmpResult
IEEE-754R 5.11: Floating Point Comparison Relations.
static constexpr roundingMode rmTowardNegative
static constexpr roundingMode rmNearestTiesToEven
static constexpr roundingMode rmTowardZero
static const fltSemantics & IEEEquad() LLVM_READNONE
static const fltSemantics & IEEEdouble() LLVM_READNONE
static const fltSemantics & IEEEhalf() LLVM_READNONE
static constexpr roundingMode rmTowardPositive
static const fltSemantics & BFloat() LLVM_READNONE
opStatus
IEEE-754R 7: Default exception handling.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Represents offset+length into a ConstantDataArray.
uint64_t Length
Length of the slice.
uint64_t Offset
Slice starts at this Offset.
void move(uint64_t Delta)
Moves the Offset and adjusts Length accordingly.
const ConstantDataArray * Array
ConstantDataArray pointer.
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
intptr_t getRawBits() const
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
bool bitsGT(EVT VT) const
Return true if this has more bits than VT.
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
ElementCount getVectorElementCount() const
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
unsigned getVectorMinNumElements() const
Given a vector type, return the minimum number of elements it contains.
uint64_t getScalarSizeInBits() const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
bool isFixedLengthVector() const
bool isVector() const
Return true if this is a vector value type.
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
bool bitsGE(EVT VT) const
Return true if this has no less bits than VT.
bool bitsEq(EVT VT) const
Return true if this has the same number of bits as VT.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
bool isScalableVector() const
Return true if this is a vector type where the runtime length is machine dependent.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
bool isExtended() const
Test if the given EVT is extended (as opposed to being simple).
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
bool bitsLE(EVT VT) const
Return true if this has no more bits than VT.
EVT getHalfNumVectorElementsVT(LLVMContext &Context) const
bool isInteger() const
Return true if this is an integer or a vector integer type.
static KnownBits makeConstant(const APInt &C)
Create known bits from a known constant.
KnownBits sextInReg(unsigned SrcBitWidth) const
Return known bits for a in-register sign extension of the value we're tracking.
static KnownBits mulhu(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits from zero-extended multiply-hi.
unsigned countMinSignBits() const
Returns the number of times the sign bit is replicated into the other bits.
static KnownBits smax(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for smax(LHS, RHS).
bool isNonNegative() const
Returns true if this value is known to be non-negative.
bool isZero() const
Returns true if value is all zero.
void makeNonNegative()
Make this value non-negative.
static KnownBits usub_sat(const KnownBits &LHS, const KnownBits &RHS)
Compute knownbits resulting from llvm.usub.sat(LHS, RHS)
unsigned countMinTrailingZeros() const
Returns the minimum number of trailing zero bits.
static KnownBits ashr(const KnownBits &LHS, const KnownBits &RHS, bool ShAmtNonZero=false, bool Exact=false)
Compute known bits for ashr(LHS, RHS).
static KnownBits urem(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for urem(LHS, RHS).
bool isUnknown() const
Returns true if we don't know any bits.
unsigned countMaxTrailingZeros() const
Returns the maximum number of trailing zero bits possible.
static std::optional< bool > ne(const KnownBits &LHS, const KnownBits &RHS)
Determine if these known bits always give the same ICMP_NE result.
void makeNegative()
Make this value negative.
KnownBits trunc(unsigned BitWidth) const
Return known bits for a truncation of the value we're tracking.
KnownBits byteSwap() const
unsigned countMaxPopulation() const
Returns the maximum number of bits that could be one.
void setAllZero()
Make all bits known to be zero and discard any previous information.
KnownBits reverseBits() const
KnownBits concat(const KnownBits &Lo) const
Concatenate the bits from Lo onto the bottom of *this.
unsigned getBitWidth() const
Get the bit width of this value.
static KnownBits umax(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for umax(LHS, RHS).
KnownBits zext(unsigned BitWidth) const
Return known bits for a zero extension of the value we're tracking.
void resetAll()
Resets the known state of all bits.
KnownBits unionWith(const KnownBits &RHS) const
Returns KnownBits information that is known to be true for either this or RHS or both.
static KnownBits lshr(const KnownBits &LHS, const KnownBits &RHS, bool ShAmtNonZero=false, bool Exact=false)
Compute known bits for lshr(LHS, RHS).
bool isNonZero() const
Returns true if this value is known to be non-zero.
static KnownBits abdu(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for abdu(LHS, RHS).
KnownBits extractBits(unsigned NumBits, unsigned BitPosition) const
Return a subset of the known bits from [bitPosition,bitPosition+numBits).
static KnownBits avgFloorU(const KnownBits &LHS, const KnownBits &RHS)
Compute knownbits resulting from APIntOps::avgFloorU.
KnownBits intersectWith(const KnownBits &RHS) const
Returns KnownBits information that is known to be true for both this and RHS.
KnownBits sext(unsigned BitWidth) const
Return known bits for a sign extension of the value we're tracking.
static KnownBits computeForSubBorrow(const KnownBits &LHS, KnownBits RHS, const KnownBits &Borrow)
Compute known bits results from subtracting RHS from LHS with 1-bit Borrow.
KnownBits zextOrTrunc(unsigned BitWidth) const
Return known bits for a zero extension or truncation of the value we're tracking.
APInt getMaxValue() const
Return the maximal unsigned value possible given these KnownBits.
static KnownBits abds(KnownBits LHS, KnownBits RHS)
Compute known bits for abds(LHS, RHS).
static KnownBits smin(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for smin(LHS, RHS).
static KnownBits mulhs(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits from sign-extended multiply-hi.
static KnownBits srem(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for srem(LHS, RHS).
static KnownBits udiv(const KnownBits &LHS, const KnownBits &RHS, bool Exact=false)
Compute known bits for udiv(LHS, RHS).
static KnownBits computeForAddSub(bool Add, bool NSW, bool NUW, const KnownBits &LHS, const KnownBits &RHS)
Compute known bits resulting from adding LHS and RHS.
bool isStrictlyPositive() const
Returns true if this value is known to be positive.
static KnownBits sdiv(const KnownBits &LHS, const KnownBits &RHS, bool Exact=false)
Compute known bits for sdiv(LHS, RHS).
static KnownBits avgFloorS(const KnownBits &LHS, const KnownBits &RHS)
Compute knownbits resulting from APIntOps::avgFloorS.
static bool haveNoCommonBitsSet(const KnownBits &LHS, const KnownBits &RHS)
Return true if LHS and RHS have no common bits set.
bool isNegative() const
Returns true if this value is known to be negative.
static KnownBits computeForAddCarry(const KnownBits &LHS, const KnownBits &RHS, const KnownBits &Carry)
Compute known bits resulting from adding LHS, RHS and a 1-bit Carry.
unsigned countMaxLeadingZeros() const
Returns the maximum number of leading zero bits possible.
void insertBits(const KnownBits &SubBits, unsigned BitPosition)
Insert the bits from a smaller known bits starting at bitPosition.
static KnownBits avgCeilU(const KnownBits &LHS, const KnownBits &RHS)
Compute knownbits resulting from APIntOps::avgCeilU.
static KnownBits mul(const KnownBits &LHS, const KnownBits &RHS, bool NoUndefSelfMultiply=false)
Compute known bits resulting from multiplying LHS and RHS.
KnownBits anyext(unsigned BitWidth) const
Return known bits for an "any" extension of the value we're tracking, where we don't know anything ab...
KnownBits abs(bool IntMinIsPoison=false) const
Compute known bits for the absolute value.
static KnownBits shl(const KnownBits &LHS, const KnownBits &RHS, bool NUW=false, bool NSW=false, bool ShAmtNonZero=false)
Compute known bits for shl(LHS, RHS).
static KnownBits umin(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for umin(LHS, RHS).
static KnownBits avgCeilS(const KnownBits &LHS, const KnownBits &RHS)
Compute knownbits resulting from APIntOps::avgCeilS.
This class contains a discriminated union of information about pointers in memory operands,...
bool isDereferenceable(unsigned Size, LLVMContext &C, const DataLayout &DL) const
Return true if memory region [V, V+Offset+Size) is known to be dereferenceable.
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
MachinePointerInfo getWithOffset(int64_t O) const
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
static MemOp Set(uint64_t Size, bool DstAlignCanChange, Align DstAlign, bool IsZeroMemset, bool IsVolatile)
static MemOp Copy(uint64_t Size, bool DstAlignCanChange, Align DstAlign, Align SrcAlign, bool IsVolatile, bool MemcpyStrSrc=false)
These are IR-level optimization flags that may be propagated to SDNodes.
void intersectWith(const SDNodeFlags Flags)
Clear any flags in this flag set that aren't also set in Flags.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Clients of various APIs that cause global effects on the DAG can optionally implement this interface.
DAGUpdateListener *const Next
virtual void NodeDeleted(SDNode *N, SDNode *E)
The node N that was deleted and, if E is not null, an equivalent node E that replaced it.
virtual void NodeInserted(SDNode *N)
The node N that was inserted.
virtual void NodeUpdated(SDNode *N)
The node N that was updated.
This structure contains all information that is necessary for lowering calls.
CallLoweringInfo & setLibCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList)
CallLoweringInfo & setDiscardResult(bool Value=true)
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
CallLoweringInfo & setTailCall(bool Value=true)
CallLoweringInfo & setChain(SDValue InChain)